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[deliverable/linux.git] / arch / x86 / kvm / lapic.c
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
40 #include "irq.h"
41 #include "trace.h"
42 #include "x86.h"
43 #include "cpuid.h"
44
45 #ifndef CONFIG_X86_64
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #else
48 #define mod_64(x, y) ((x) % (y))
49 #endif
50
51 #define PRId64 "d"
52 #define PRIx64 "llx"
53 #define PRIu64 "u"
54 #define PRIo64 "o"
55
56 #define APIC_BUS_CYCLE_NS 1
57
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
60
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
71
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
74
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
77
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 {
80 *((u32 *) (apic->regs + reg_off)) = val;
81 }
82
83 static inline int apic_test_vector(int vec, void *bitmap)
84 {
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86 }
87
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89 {
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94 }
95
96 static inline void apic_set_vector(int vec, void *bitmap)
97 {
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99 }
100
101 static inline void apic_clear_vector(int vec, void *bitmap)
102 {
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104 }
105
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 {
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109 }
110
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 {
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114 }
115
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
118
119 static inline int apic_enabled(struct kvm_lapic *apic)
120 {
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
122 }
123
124 #define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127 #define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 {
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
134 }
135
136 static void recalculate_apic_map(struct kvm *kvm)
137 {
138 struct kvm_apic_map *new, *old = NULL;
139 struct kvm_vcpu *vcpu;
140 int i;
141
142 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
143
144 mutex_lock(&kvm->arch.apic_map_lock);
145
146 if (!new)
147 goto out;
148
149 new->ldr_bits = 8;
150 /* flat mode is default */
151 new->cid_shift = 8;
152 new->cid_mask = 0;
153 new->lid_mask = 0xff;
154 new->broadcast = APIC_BROADCAST;
155
156 kvm_for_each_vcpu(i, vcpu, kvm) {
157 struct kvm_lapic *apic = vcpu->arch.apic;
158
159 if (!kvm_apic_present(vcpu))
160 continue;
161
162 if (apic_x2apic_mode(apic)) {
163 new->ldr_bits = 32;
164 new->cid_shift = 16;
165 new->cid_mask = new->lid_mask = 0xffff;
166 new->broadcast = X2APIC_BROADCAST;
167 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
168 if (kvm_apic_get_reg(apic, APIC_DFR) ==
169 APIC_DFR_CLUSTER) {
170 new->cid_shift = 4;
171 new->cid_mask = 0xf;
172 new->lid_mask = 0xf;
173 } else {
174 new->cid_shift = 8;
175 new->cid_mask = 0;
176 new->lid_mask = 0xff;
177 }
178 }
179
180 /*
181 * All APICs have to be configured in the same mode by an OS.
182 * We take advatage of this while building logical id loockup
183 * table. After reset APICs are in software disabled mode, so if
184 * we find apic with different setting we assume this is the mode
185 * OS wants all apics to be in; build lookup table accordingly.
186 */
187 if (kvm_apic_sw_enabled(apic))
188 break;
189 }
190
191 kvm_for_each_vcpu(i, vcpu, kvm) {
192 struct kvm_lapic *apic = vcpu->arch.apic;
193 u16 cid, lid;
194 u32 ldr, aid;
195
196 aid = kvm_apic_id(apic);
197 ldr = kvm_apic_get_reg(apic, APIC_LDR);
198 cid = apic_cluster_id(new, ldr);
199 lid = apic_logical_id(new, ldr);
200
201 if (aid < ARRAY_SIZE(new->phys_map))
202 new->phys_map[aid] = apic;
203 if (lid && cid < ARRAY_SIZE(new->logical_map))
204 new->logical_map[cid][ffs(lid) - 1] = apic;
205 }
206 out:
207 old = rcu_dereference_protected(kvm->arch.apic_map,
208 lockdep_is_held(&kvm->arch.apic_map_lock));
209 rcu_assign_pointer(kvm->arch.apic_map, new);
210 mutex_unlock(&kvm->arch.apic_map_lock);
211
212 if (old)
213 kfree_rcu(old, rcu);
214
215 kvm_vcpu_request_scan_ioapic(kvm);
216 }
217
218 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
219 {
220 bool enabled = val & APIC_SPIV_APIC_ENABLED;
221
222 apic_set_reg(apic, APIC_SPIV, val);
223
224 if (enabled != apic->sw_enabled) {
225 apic->sw_enabled = enabled;
226 if (enabled) {
227 static_key_slow_dec_deferred(&apic_sw_disabled);
228 recalculate_apic_map(apic->vcpu->kvm);
229 } else
230 static_key_slow_inc(&apic_sw_disabled.key);
231 }
232 }
233
234 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
235 {
236 apic_set_reg(apic, APIC_ID, id << 24);
237 recalculate_apic_map(apic->vcpu->kvm);
238 }
239
240 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
241 {
242 apic_set_reg(apic, APIC_LDR, id);
243 recalculate_apic_map(apic->vcpu->kvm);
244 }
245
246 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
247 {
248 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
249 }
250
251 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
252 {
253 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
254 }
255
256 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
257 {
258 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
259 }
260
261 static inline int apic_lvtt_period(struct kvm_lapic *apic)
262 {
263 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
264 }
265
266 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
267 {
268 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
269 }
270
271 static inline int apic_lvt_nmi_mode(u32 lvt_val)
272 {
273 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
274 }
275
276 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
277 {
278 struct kvm_lapic *apic = vcpu->arch.apic;
279 struct kvm_cpuid_entry2 *feat;
280 u32 v = APIC_VERSION;
281
282 if (!kvm_vcpu_has_lapic(vcpu))
283 return;
284
285 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
286 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
287 v |= APIC_LVR_DIRECTED_EOI;
288 apic_set_reg(apic, APIC_LVR, v);
289 }
290
291 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
292 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
293 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
294 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
295 LINT_MASK, LINT_MASK, /* LVT0-1 */
296 LVT_MASK /* LVTERR */
297 };
298
299 static int find_highest_vector(void *bitmap)
300 {
301 int vec;
302 u32 *reg;
303
304 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
305 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
306 reg = bitmap + REG_POS(vec);
307 if (*reg)
308 return fls(*reg) - 1 + vec;
309 }
310
311 return -1;
312 }
313
314 static u8 count_vectors(void *bitmap)
315 {
316 int vec;
317 u32 *reg;
318 u8 count = 0;
319
320 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
321 reg = bitmap + REG_POS(vec);
322 count += hweight32(*reg);
323 }
324
325 return count;
326 }
327
328 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
329 {
330 u32 i, pir_val;
331 struct kvm_lapic *apic = vcpu->arch.apic;
332
333 for (i = 0; i <= 7; i++) {
334 pir_val = xchg(&pir[i], 0);
335 if (pir_val)
336 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
337 }
338 }
339 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
340
341 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
342 {
343 apic_set_vector(vec, apic->regs + APIC_IRR);
344 /*
345 * irr_pending must be true if any interrupt is pending; set it after
346 * APIC_IRR to avoid race with apic_clear_irr
347 */
348 apic->irr_pending = true;
349 }
350
351 static inline int apic_search_irr(struct kvm_lapic *apic)
352 {
353 return find_highest_vector(apic->regs + APIC_IRR);
354 }
355
356 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
357 {
358 int result;
359
360 /*
361 * Note that irr_pending is just a hint. It will be always
362 * true with virtual interrupt delivery enabled.
363 */
364 if (!apic->irr_pending)
365 return -1;
366
367 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
368 result = apic_search_irr(apic);
369 ASSERT(result == -1 || result >= 16);
370
371 return result;
372 }
373
374 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
375 {
376 struct kvm_vcpu *vcpu;
377
378 vcpu = apic->vcpu;
379
380 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
381 /* try to update RVI */
382 apic_clear_vector(vec, apic->regs + APIC_IRR);
383 kvm_make_request(KVM_REQ_EVENT, vcpu);
384 } else {
385 apic->irr_pending = false;
386 apic_clear_vector(vec, apic->regs + APIC_IRR);
387 if (apic_search_irr(apic) != -1)
388 apic->irr_pending = true;
389 }
390 }
391
392 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
393 {
394 struct kvm_vcpu *vcpu;
395
396 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
397 return;
398
399 vcpu = apic->vcpu;
400
401 /*
402 * With APIC virtualization enabled, all caching is disabled
403 * because the processor can modify ISR under the hood. Instead
404 * just set SVI.
405 */
406 if (unlikely(kvm_x86_ops->hwapic_isr_update))
407 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
408 else {
409 ++apic->isr_count;
410 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
411 /*
412 * ISR (in service register) bit is set when injecting an interrupt.
413 * The highest vector is injected. Thus the latest bit set matches
414 * the highest bit in ISR.
415 */
416 apic->highest_isr_cache = vec;
417 }
418 }
419
420 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
421 {
422 int result;
423
424 /*
425 * Note that isr_count is always 1, and highest_isr_cache
426 * is always -1, with APIC virtualization enabled.
427 */
428 if (!apic->isr_count)
429 return -1;
430 if (likely(apic->highest_isr_cache != -1))
431 return apic->highest_isr_cache;
432
433 result = find_highest_vector(apic->regs + APIC_ISR);
434 ASSERT(result == -1 || result >= 16);
435
436 return result;
437 }
438
439 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
440 {
441 struct kvm_vcpu *vcpu;
442 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
443 return;
444
445 vcpu = apic->vcpu;
446
447 /*
448 * We do get here for APIC virtualization enabled if the guest
449 * uses the Hyper-V APIC enlightenment. In this case we may need
450 * to trigger a new interrupt delivery by writing the SVI field;
451 * on the other hand isr_count and highest_isr_cache are unused
452 * and must be left alone.
453 */
454 if (unlikely(kvm_x86_ops->hwapic_isr_update))
455 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
456 apic_find_highest_isr(apic));
457 else {
458 --apic->isr_count;
459 BUG_ON(apic->isr_count < 0);
460 apic->highest_isr_cache = -1;
461 }
462 }
463
464 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
465 {
466 int highest_irr;
467
468 /* This may race with setting of irr in __apic_accept_irq() and
469 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
470 * will cause vmexit immediately and the value will be recalculated
471 * on the next vmentry.
472 */
473 if (!kvm_vcpu_has_lapic(vcpu))
474 return 0;
475 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
476
477 return highest_irr;
478 }
479
480 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
481 int vector, int level, int trig_mode,
482 unsigned long *dest_map);
483
484 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
485 unsigned long *dest_map)
486 {
487 struct kvm_lapic *apic = vcpu->arch.apic;
488
489 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
490 irq->level, irq->trig_mode, dest_map);
491 }
492
493 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
494 {
495
496 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
497 sizeof(val));
498 }
499
500 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
501 {
502
503 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
504 sizeof(*val));
505 }
506
507 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
508 {
509 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
510 }
511
512 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
513 {
514 u8 val;
515 if (pv_eoi_get_user(vcpu, &val) < 0)
516 apic_debug("Can't read EOI MSR value: 0x%llx\n",
517 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
518 return val & 0x1;
519 }
520
521 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
522 {
523 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
524 apic_debug("Can't set EOI MSR value: 0x%llx\n",
525 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
526 return;
527 }
528 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
529 }
530
531 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
532 {
533 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
534 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
535 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
536 return;
537 }
538 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
539 }
540
541 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
542 {
543 struct kvm_lapic *apic = vcpu->arch.apic;
544 int i;
545
546 for (i = 0; i < 8; i++)
547 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
548 }
549
550 static void apic_update_ppr(struct kvm_lapic *apic)
551 {
552 u32 tpr, isrv, ppr, old_ppr;
553 int isr;
554
555 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
556 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
557 isr = apic_find_highest_isr(apic);
558 isrv = (isr != -1) ? isr : 0;
559
560 if ((tpr & 0xf0) >= (isrv & 0xf0))
561 ppr = tpr & 0xff;
562 else
563 ppr = isrv & 0xf0;
564
565 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
566 apic, ppr, isr, isrv);
567
568 if (old_ppr != ppr) {
569 apic_set_reg(apic, APIC_PROCPRI, ppr);
570 if (ppr < old_ppr)
571 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
572 }
573 }
574
575 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
576 {
577 apic_set_reg(apic, APIC_TASKPRI, tpr);
578 apic_update_ppr(apic);
579 }
580
581 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
582 {
583 return dest == (apic_x2apic_mode(apic) ?
584 X2APIC_BROADCAST : APIC_BROADCAST);
585 }
586
587 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
588 {
589 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
590 }
591
592 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
593 {
594 int result = 0;
595 u32 logical_id;
596
597 if (kvm_apic_broadcast(apic, mda))
598 return 1;
599
600 if (apic_x2apic_mode(apic)) {
601 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
602 return logical_id & mda;
603 }
604
605 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
606
607 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
608 case APIC_DFR_FLAT:
609 if (logical_id & mda)
610 result = 1;
611 break;
612 case APIC_DFR_CLUSTER:
613 if (((logical_id >> 4) == (mda >> 0x4))
614 && (logical_id & mda & 0xf))
615 result = 1;
616 break;
617 default:
618 apic_debug("Bad DFR vcpu %d: %08x\n",
619 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
620 break;
621 }
622
623 return result;
624 }
625
626 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
627 int short_hand, unsigned int dest, int dest_mode)
628 {
629 int result = 0;
630 struct kvm_lapic *target = vcpu->arch.apic;
631
632 apic_debug("target %p, source %p, dest 0x%x, "
633 "dest_mode 0x%x, short_hand 0x%x\n",
634 target, source, dest, dest_mode, short_hand);
635
636 ASSERT(target);
637 switch (short_hand) {
638 case APIC_DEST_NOSHORT:
639 if (dest_mode == 0)
640 /* Physical mode. */
641 result = kvm_apic_match_physical_addr(target, dest);
642 else
643 /* Logical mode. */
644 result = kvm_apic_match_logical_addr(target, dest);
645 break;
646 case APIC_DEST_SELF:
647 result = (target == source);
648 break;
649 case APIC_DEST_ALLINC:
650 result = 1;
651 break;
652 case APIC_DEST_ALLBUT:
653 result = (target != source);
654 break;
655 default:
656 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
657 short_hand);
658 break;
659 }
660
661 return result;
662 }
663
664 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
665 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
666 {
667 struct kvm_apic_map *map;
668 unsigned long bitmap = 1;
669 struct kvm_lapic **dst;
670 int i;
671 bool ret = false;
672
673 *r = -1;
674
675 if (irq->shorthand == APIC_DEST_SELF) {
676 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
677 return true;
678 }
679
680 if (irq->shorthand)
681 return false;
682
683 rcu_read_lock();
684 map = rcu_dereference(kvm->arch.apic_map);
685
686 if (!map)
687 goto out;
688
689 if (irq->dest_id == map->broadcast)
690 goto out;
691
692 ret = true;
693
694 if (irq->dest_mode == 0) { /* physical mode */
695 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
696 goto out;
697
698 dst = &map->phys_map[irq->dest_id];
699 } else {
700 u32 mda = irq->dest_id << (32 - map->ldr_bits);
701 u16 cid = apic_cluster_id(map, mda);
702
703 if (cid >= ARRAY_SIZE(map->logical_map))
704 goto out;
705
706 dst = map->logical_map[cid];
707
708 bitmap = apic_logical_id(map, mda);
709
710 if (irq->delivery_mode == APIC_DM_LOWEST) {
711 int l = -1;
712 for_each_set_bit(i, &bitmap, 16) {
713 if (!dst[i])
714 continue;
715 if (l < 0)
716 l = i;
717 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
718 l = i;
719 }
720
721 bitmap = (l >= 0) ? 1 << l : 0;
722 }
723 }
724
725 for_each_set_bit(i, &bitmap, 16) {
726 if (!dst[i])
727 continue;
728 if (*r < 0)
729 *r = 0;
730 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
731 }
732 out:
733 rcu_read_unlock();
734 return ret;
735 }
736
737 /*
738 * Add a pending IRQ into lapic.
739 * Return 1 if successfully added and 0 if discarded.
740 */
741 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
742 int vector, int level, int trig_mode,
743 unsigned long *dest_map)
744 {
745 int result = 0;
746 struct kvm_vcpu *vcpu = apic->vcpu;
747
748 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
749 trig_mode, vector);
750 switch (delivery_mode) {
751 case APIC_DM_LOWEST:
752 vcpu->arch.apic_arb_prio++;
753 case APIC_DM_FIXED:
754 /* FIXME add logic for vcpu on reset */
755 if (unlikely(!apic_enabled(apic)))
756 break;
757
758 result = 1;
759
760 if (dest_map)
761 __set_bit(vcpu->vcpu_id, dest_map);
762
763 if (kvm_x86_ops->deliver_posted_interrupt)
764 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
765 else {
766 apic_set_irr(vector, apic);
767
768 kvm_make_request(KVM_REQ_EVENT, vcpu);
769 kvm_vcpu_kick(vcpu);
770 }
771 break;
772
773 case APIC_DM_REMRD:
774 result = 1;
775 vcpu->arch.pv.pv_unhalted = 1;
776 kvm_make_request(KVM_REQ_EVENT, vcpu);
777 kvm_vcpu_kick(vcpu);
778 break;
779
780 case APIC_DM_SMI:
781 apic_debug("Ignoring guest SMI\n");
782 break;
783
784 case APIC_DM_NMI:
785 result = 1;
786 kvm_inject_nmi(vcpu);
787 kvm_vcpu_kick(vcpu);
788 break;
789
790 case APIC_DM_INIT:
791 if (!trig_mode || level) {
792 result = 1;
793 /* assumes that there are only KVM_APIC_INIT/SIPI */
794 apic->pending_events = (1UL << KVM_APIC_INIT);
795 /* make sure pending_events is visible before sending
796 * the request */
797 smp_wmb();
798 kvm_make_request(KVM_REQ_EVENT, vcpu);
799 kvm_vcpu_kick(vcpu);
800 } else {
801 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
802 vcpu->vcpu_id);
803 }
804 break;
805
806 case APIC_DM_STARTUP:
807 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
808 vcpu->vcpu_id, vector);
809 result = 1;
810 apic->sipi_vector = vector;
811 /* make sure sipi_vector is visible for the receiver */
812 smp_wmb();
813 set_bit(KVM_APIC_SIPI, &apic->pending_events);
814 kvm_make_request(KVM_REQ_EVENT, vcpu);
815 kvm_vcpu_kick(vcpu);
816 break;
817
818 case APIC_DM_EXTINT:
819 /*
820 * Should only be called by kvm_apic_local_deliver() with LVT0,
821 * before NMI watchdog was enabled. Already handled by
822 * kvm_apic_accept_pic_intr().
823 */
824 break;
825
826 default:
827 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
828 delivery_mode);
829 break;
830 }
831 return result;
832 }
833
834 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
835 {
836 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
837 }
838
839 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
840 {
841 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
842 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
843 int trigger_mode;
844 if (apic_test_vector(vector, apic->regs + APIC_TMR))
845 trigger_mode = IOAPIC_LEVEL_TRIG;
846 else
847 trigger_mode = IOAPIC_EDGE_TRIG;
848 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
849 }
850 }
851
852 static int apic_set_eoi(struct kvm_lapic *apic)
853 {
854 int vector = apic_find_highest_isr(apic);
855
856 trace_kvm_eoi(apic, vector);
857
858 /*
859 * Not every write EOI will has corresponding ISR,
860 * one example is when Kernel check timer on setup_IO_APIC
861 */
862 if (vector == -1)
863 return vector;
864
865 apic_clear_isr(vector, apic);
866 apic_update_ppr(apic);
867
868 kvm_ioapic_send_eoi(apic, vector);
869 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
870 return vector;
871 }
872
873 /*
874 * this interface assumes a trap-like exit, which has already finished
875 * desired side effect including vISR and vPPR update.
876 */
877 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
878 {
879 struct kvm_lapic *apic = vcpu->arch.apic;
880
881 trace_kvm_eoi(apic, vector);
882
883 kvm_ioapic_send_eoi(apic, vector);
884 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
885 }
886 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
887
888 static void apic_send_ipi(struct kvm_lapic *apic)
889 {
890 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
891 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
892 struct kvm_lapic_irq irq;
893
894 irq.vector = icr_low & APIC_VECTOR_MASK;
895 irq.delivery_mode = icr_low & APIC_MODE_MASK;
896 irq.dest_mode = icr_low & APIC_DEST_MASK;
897 irq.level = icr_low & APIC_INT_ASSERT;
898 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
899 irq.shorthand = icr_low & APIC_SHORT_MASK;
900 if (apic_x2apic_mode(apic))
901 irq.dest_id = icr_high;
902 else
903 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
904
905 trace_kvm_apic_ipi(icr_low, irq.dest_id);
906
907 apic_debug("icr_high 0x%x, icr_low 0x%x, "
908 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
909 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
910 icr_high, icr_low, irq.shorthand, irq.dest_id,
911 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
912 irq.vector);
913
914 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
915 }
916
917 static u32 apic_get_tmcct(struct kvm_lapic *apic)
918 {
919 ktime_t remaining;
920 s64 ns;
921 u32 tmcct;
922
923 ASSERT(apic != NULL);
924
925 /* if initial count is 0, current count should also be 0 */
926 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
927 apic->lapic_timer.period == 0)
928 return 0;
929
930 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
931 if (ktime_to_ns(remaining) < 0)
932 remaining = ktime_set(0, 0);
933
934 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
935 tmcct = div64_u64(ns,
936 (APIC_BUS_CYCLE_NS * apic->divide_count));
937
938 return tmcct;
939 }
940
941 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
942 {
943 struct kvm_vcpu *vcpu = apic->vcpu;
944 struct kvm_run *run = vcpu->run;
945
946 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
947 run->tpr_access.rip = kvm_rip_read(vcpu);
948 run->tpr_access.is_write = write;
949 }
950
951 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
952 {
953 if (apic->vcpu->arch.tpr_access_reporting)
954 __report_tpr_access(apic, write);
955 }
956
957 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
958 {
959 u32 val = 0;
960
961 if (offset >= LAPIC_MMIO_LENGTH)
962 return 0;
963
964 switch (offset) {
965 case APIC_ID:
966 if (apic_x2apic_mode(apic))
967 val = kvm_apic_id(apic);
968 else
969 val = kvm_apic_id(apic) << 24;
970 break;
971 case APIC_ARBPRI:
972 apic_debug("Access APIC ARBPRI register which is for P6\n");
973 break;
974
975 case APIC_TMCCT: /* Timer CCR */
976 if (apic_lvtt_tscdeadline(apic))
977 return 0;
978
979 val = apic_get_tmcct(apic);
980 break;
981 case APIC_PROCPRI:
982 apic_update_ppr(apic);
983 val = kvm_apic_get_reg(apic, offset);
984 break;
985 case APIC_TASKPRI:
986 report_tpr_access(apic, false);
987 /* fall thru */
988 default:
989 val = kvm_apic_get_reg(apic, offset);
990 break;
991 }
992
993 return val;
994 }
995
996 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
997 {
998 return container_of(dev, struct kvm_lapic, dev);
999 }
1000
1001 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1002 void *data)
1003 {
1004 unsigned char alignment = offset & 0xf;
1005 u32 result;
1006 /* this bitmask has a bit cleared for each reserved register */
1007 static const u64 rmask = 0x43ff01ffffffe70cULL;
1008
1009 if ((alignment + len) > 4) {
1010 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1011 offset, len);
1012 return 1;
1013 }
1014
1015 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1016 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1017 offset);
1018 return 1;
1019 }
1020
1021 result = __apic_read(apic, offset & ~0xf);
1022
1023 trace_kvm_apic_read(offset, result);
1024
1025 switch (len) {
1026 case 1:
1027 case 2:
1028 case 4:
1029 memcpy(data, (char *)&result + alignment, len);
1030 break;
1031 default:
1032 printk(KERN_ERR "Local APIC read with len = %x, "
1033 "should be 1,2, or 4 instead\n", len);
1034 break;
1035 }
1036 return 0;
1037 }
1038
1039 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1040 {
1041 return kvm_apic_hw_enabled(apic) &&
1042 addr >= apic->base_address &&
1043 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1044 }
1045
1046 static int apic_mmio_read(struct kvm_io_device *this,
1047 gpa_t address, int len, void *data)
1048 {
1049 struct kvm_lapic *apic = to_lapic(this);
1050 u32 offset = address - apic->base_address;
1051
1052 if (!apic_mmio_in_range(apic, address))
1053 return -EOPNOTSUPP;
1054
1055 apic_reg_read(apic, offset, len, data);
1056
1057 return 0;
1058 }
1059
1060 static void update_divide_count(struct kvm_lapic *apic)
1061 {
1062 u32 tmp1, tmp2, tdcr;
1063
1064 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1065 tmp1 = tdcr & 0xf;
1066 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1067 apic->divide_count = 0x1 << (tmp2 & 0x7);
1068
1069 apic_debug("timer divide count is 0x%x\n",
1070 apic->divide_count);
1071 }
1072
1073 static void apic_timer_expired(struct kvm_lapic *apic)
1074 {
1075 struct kvm_vcpu *vcpu = apic->vcpu;
1076 wait_queue_head_t *q = &vcpu->wq;
1077 struct kvm_timer *ktimer = &apic->lapic_timer;
1078
1079 if (atomic_read(&apic->lapic_timer.pending))
1080 return;
1081
1082 atomic_inc(&apic->lapic_timer.pending);
1083 kvm_set_pending_timer(vcpu);
1084
1085 if (waitqueue_active(q))
1086 wake_up_interruptible(q);
1087
1088 if (apic_lvtt_tscdeadline(apic))
1089 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1090 }
1091
1092 /*
1093 * On APICv, this test will cause a busy wait
1094 * during a higher-priority task.
1095 */
1096
1097 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1098 {
1099 struct kvm_lapic *apic = vcpu->arch.apic;
1100 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1101
1102 if (kvm_apic_hw_enabled(apic)) {
1103 int vec = reg & APIC_VECTOR_MASK;
1104
1105 if (kvm_x86_ops->test_posted_interrupt)
1106 return kvm_x86_ops->test_posted_interrupt(vcpu, vec);
1107 else {
1108 if (apic_test_vector(vec, apic->regs + APIC_ISR))
1109 return true;
1110 }
1111 }
1112 return false;
1113 }
1114
1115 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1116 {
1117 struct kvm_lapic *apic = vcpu->arch.apic;
1118 u64 guest_tsc, tsc_deadline;
1119
1120 if (!kvm_vcpu_has_lapic(vcpu))
1121 return;
1122
1123 if (apic->lapic_timer.expired_tscdeadline == 0)
1124 return;
1125
1126 if (!lapic_timer_int_injected(vcpu))
1127 return;
1128
1129 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1130 apic->lapic_timer.expired_tscdeadline = 0;
1131 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1132 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1133
1134 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1135 if (guest_tsc < tsc_deadline)
1136 __delay(tsc_deadline - guest_tsc);
1137 }
1138
1139 static void start_apic_timer(struct kvm_lapic *apic)
1140 {
1141 ktime_t now;
1142
1143 atomic_set(&apic->lapic_timer.pending, 0);
1144
1145 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1146 /* lapic timer in oneshot or periodic mode */
1147 now = apic->lapic_timer.timer.base->get_time();
1148 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1149 * APIC_BUS_CYCLE_NS * apic->divide_count;
1150
1151 if (!apic->lapic_timer.period)
1152 return;
1153 /*
1154 * Do not allow the guest to program periodic timers with small
1155 * interval, since the hrtimers are not throttled by the host
1156 * scheduler.
1157 */
1158 if (apic_lvtt_period(apic)) {
1159 s64 min_period = min_timer_period_us * 1000LL;
1160
1161 if (apic->lapic_timer.period < min_period) {
1162 pr_info_ratelimited(
1163 "kvm: vcpu %i: requested %lld ns "
1164 "lapic timer period limited to %lld ns\n",
1165 apic->vcpu->vcpu_id,
1166 apic->lapic_timer.period, min_period);
1167 apic->lapic_timer.period = min_period;
1168 }
1169 }
1170
1171 hrtimer_start(&apic->lapic_timer.timer,
1172 ktime_add_ns(now, apic->lapic_timer.period),
1173 HRTIMER_MODE_ABS);
1174
1175 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1176 PRIx64 ", "
1177 "timer initial count 0x%x, period %lldns, "
1178 "expire @ 0x%016" PRIx64 ".\n", __func__,
1179 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1180 kvm_apic_get_reg(apic, APIC_TMICT),
1181 apic->lapic_timer.period,
1182 ktime_to_ns(ktime_add_ns(now,
1183 apic->lapic_timer.period)));
1184 } else if (apic_lvtt_tscdeadline(apic)) {
1185 /* lapic timer in tsc deadline mode */
1186 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1187 u64 ns = 0;
1188 ktime_t expire;
1189 struct kvm_vcpu *vcpu = apic->vcpu;
1190 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1191 unsigned long flags;
1192
1193 if (unlikely(!tscdeadline || !this_tsc_khz))
1194 return;
1195
1196 local_irq_save(flags);
1197
1198 now = apic->lapic_timer.timer.base->get_time();
1199 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1200 if (likely(tscdeadline > guest_tsc)) {
1201 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1202 do_div(ns, this_tsc_khz);
1203 expire = ktime_add_ns(now, ns);
1204 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1205 hrtimer_start(&apic->lapic_timer.timer,
1206 expire, HRTIMER_MODE_ABS);
1207 } else
1208 apic_timer_expired(apic);
1209
1210 local_irq_restore(flags);
1211 }
1212 }
1213
1214 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1215 {
1216 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1217
1218 if (apic_lvt_nmi_mode(lvt0_val)) {
1219 if (!nmi_wd_enabled) {
1220 apic_debug("Receive NMI setting on APIC_LVT0 "
1221 "for cpu %d\n", apic->vcpu->vcpu_id);
1222 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1223 }
1224 } else if (nmi_wd_enabled)
1225 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1226 }
1227
1228 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1229 {
1230 int ret = 0;
1231
1232 trace_kvm_apic_write(reg, val);
1233
1234 switch (reg) {
1235 case APIC_ID: /* Local APIC ID */
1236 if (!apic_x2apic_mode(apic))
1237 kvm_apic_set_id(apic, val >> 24);
1238 else
1239 ret = 1;
1240 break;
1241
1242 case APIC_TASKPRI:
1243 report_tpr_access(apic, true);
1244 apic_set_tpr(apic, val & 0xff);
1245 break;
1246
1247 case APIC_EOI:
1248 apic_set_eoi(apic);
1249 break;
1250
1251 case APIC_LDR:
1252 if (!apic_x2apic_mode(apic))
1253 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1254 else
1255 ret = 1;
1256 break;
1257
1258 case APIC_DFR:
1259 if (!apic_x2apic_mode(apic)) {
1260 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1261 recalculate_apic_map(apic->vcpu->kvm);
1262 } else
1263 ret = 1;
1264 break;
1265
1266 case APIC_SPIV: {
1267 u32 mask = 0x3ff;
1268 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1269 mask |= APIC_SPIV_DIRECTED_EOI;
1270 apic_set_spiv(apic, val & mask);
1271 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1272 int i;
1273 u32 lvt_val;
1274
1275 for (i = 0; i < APIC_LVT_NUM; i++) {
1276 lvt_val = kvm_apic_get_reg(apic,
1277 APIC_LVTT + 0x10 * i);
1278 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1279 lvt_val | APIC_LVT_MASKED);
1280 }
1281 atomic_set(&apic->lapic_timer.pending, 0);
1282
1283 }
1284 break;
1285 }
1286 case APIC_ICR:
1287 /* No delay here, so we always clear the pending bit */
1288 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1289 apic_send_ipi(apic);
1290 break;
1291
1292 case APIC_ICR2:
1293 if (!apic_x2apic_mode(apic))
1294 val &= 0xff000000;
1295 apic_set_reg(apic, APIC_ICR2, val);
1296 break;
1297
1298 case APIC_LVT0:
1299 apic_manage_nmi_watchdog(apic, val);
1300 case APIC_LVTTHMR:
1301 case APIC_LVTPC:
1302 case APIC_LVT1:
1303 case APIC_LVTERR:
1304 /* TODO: Check vector */
1305 if (!kvm_apic_sw_enabled(apic))
1306 val |= APIC_LVT_MASKED;
1307
1308 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1309 apic_set_reg(apic, reg, val);
1310
1311 break;
1312
1313 case APIC_LVTT: {
1314 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1315
1316 if (apic->lapic_timer.timer_mode != timer_mode) {
1317 apic->lapic_timer.timer_mode = timer_mode;
1318 hrtimer_cancel(&apic->lapic_timer.timer);
1319 }
1320
1321 if (!kvm_apic_sw_enabled(apic))
1322 val |= APIC_LVT_MASKED;
1323 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1324 apic_set_reg(apic, APIC_LVTT, val);
1325 break;
1326 }
1327
1328 case APIC_TMICT:
1329 if (apic_lvtt_tscdeadline(apic))
1330 break;
1331
1332 hrtimer_cancel(&apic->lapic_timer.timer);
1333 apic_set_reg(apic, APIC_TMICT, val);
1334 start_apic_timer(apic);
1335 break;
1336
1337 case APIC_TDCR:
1338 if (val & 4)
1339 apic_debug("KVM_WRITE:TDCR %x\n", val);
1340 apic_set_reg(apic, APIC_TDCR, val);
1341 update_divide_count(apic);
1342 break;
1343
1344 case APIC_ESR:
1345 if (apic_x2apic_mode(apic) && val != 0) {
1346 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1347 ret = 1;
1348 }
1349 break;
1350
1351 case APIC_SELF_IPI:
1352 if (apic_x2apic_mode(apic)) {
1353 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1354 } else
1355 ret = 1;
1356 break;
1357 default:
1358 ret = 1;
1359 break;
1360 }
1361 if (ret)
1362 apic_debug("Local APIC Write to read-only register %x\n", reg);
1363 return ret;
1364 }
1365
1366 static int apic_mmio_write(struct kvm_io_device *this,
1367 gpa_t address, int len, const void *data)
1368 {
1369 struct kvm_lapic *apic = to_lapic(this);
1370 unsigned int offset = address - apic->base_address;
1371 u32 val;
1372
1373 if (!apic_mmio_in_range(apic, address))
1374 return -EOPNOTSUPP;
1375
1376 /*
1377 * APIC register must be aligned on 128-bits boundary.
1378 * 32/64/128 bits registers must be accessed thru 32 bits.
1379 * Refer SDM 8.4.1
1380 */
1381 if (len != 4 || (offset & 0xf)) {
1382 /* Don't shout loud, $infamous_os would cause only noise. */
1383 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1384 return 0;
1385 }
1386
1387 val = *(u32*)data;
1388
1389 /* too common printing */
1390 if (offset != APIC_EOI)
1391 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1392 "0x%x\n", __func__, offset, len, val);
1393
1394 apic_reg_write(apic, offset & 0xff0, val);
1395
1396 return 0;
1397 }
1398
1399 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1400 {
1401 if (kvm_vcpu_has_lapic(vcpu))
1402 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1403 }
1404 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1405
1406 /* emulate APIC access in a trap manner */
1407 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1408 {
1409 u32 val = 0;
1410
1411 /* hw has done the conditional check and inst decode */
1412 offset &= 0xff0;
1413
1414 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1415
1416 /* TODO: optimize to just emulate side effect w/o one more write */
1417 apic_reg_write(vcpu->arch.apic, offset, val);
1418 }
1419 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1420
1421 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1422 {
1423 struct kvm_lapic *apic = vcpu->arch.apic;
1424
1425 if (!vcpu->arch.apic)
1426 return;
1427
1428 hrtimer_cancel(&apic->lapic_timer.timer);
1429
1430 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1431 static_key_slow_dec_deferred(&apic_hw_disabled);
1432
1433 if (!apic->sw_enabled)
1434 static_key_slow_dec_deferred(&apic_sw_disabled);
1435
1436 if (apic->regs)
1437 free_page((unsigned long)apic->regs);
1438
1439 kfree(apic);
1440 }
1441
1442 /*
1443 *----------------------------------------------------------------------
1444 * LAPIC interface
1445 *----------------------------------------------------------------------
1446 */
1447
1448 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1449 {
1450 struct kvm_lapic *apic = vcpu->arch.apic;
1451
1452 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1453 apic_lvtt_period(apic))
1454 return 0;
1455
1456 return apic->lapic_timer.tscdeadline;
1457 }
1458
1459 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1460 {
1461 struct kvm_lapic *apic = vcpu->arch.apic;
1462
1463 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1464 apic_lvtt_period(apic))
1465 return;
1466
1467 hrtimer_cancel(&apic->lapic_timer.timer);
1468 apic->lapic_timer.tscdeadline = data;
1469 start_apic_timer(apic);
1470 }
1471
1472 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1473 {
1474 struct kvm_lapic *apic = vcpu->arch.apic;
1475
1476 if (!kvm_vcpu_has_lapic(vcpu))
1477 return;
1478
1479 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1480 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1481 }
1482
1483 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1484 {
1485 u64 tpr;
1486
1487 if (!kvm_vcpu_has_lapic(vcpu))
1488 return 0;
1489
1490 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1491
1492 return (tpr & 0xf0) >> 4;
1493 }
1494
1495 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1496 {
1497 u64 old_value = vcpu->arch.apic_base;
1498 struct kvm_lapic *apic = vcpu->arch.apic;
1499
1500 if (!apic) {
1501 value |= MSR_IA32_APICBASE_BSP;
1502 vcpu->arch.apic_base = value;
1503 return;
1504 }
1505
1506 if (!kvm_vcpu_is_bsp(apic->vcpu))
1507 value &= ~MSR_IA32_APICBASE_BSP;
1508 vcpu->arch.apic_base = value;
1509
1510 /* update jump label if enable bit changes */
1511 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1512 if (value & MSR_IA32_APICBASE_ENABLE)
1513 static_key_slow_dec_deferred(&apic_hw_disabled);
1514 else
1515 static_key_slow_inc(&apic_hw_disabled.key);
1516 recalculate_apic_map(vcpu->kvm);
1517 }
1518
1519 if ((old_value ^ value) & X2APIC_ENABLE) {
1520 if (value & X2APIC_ENABLE) {
1521 u32 id = kvm_apic_id(apic);
1522 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1523 kvm_apic_set_ldr(apic, ldr);
1524 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1525 } else
1526 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1527 }
1528
1529 apic->base_address = apic->vcpu->arch.apic_base &
1530 MSR_IA32_APICBASE_BASE;
1531
1532 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1533 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1534 pr_warn_once("APIC base relocation is unsupported by KVM");
1535
1536 /* with FSB delivery interrupt, we can restart APIC functionality */
1537 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1538 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1539
1540 }
1541
1542 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1543 {
1544 struct kvm_lapic *apic;
1545 int i;
1546
1547 apic_debug("%s\n", __func__);
1548
1549 ASSERT(vcpu);
1550 apic = vcpu->arch.apic;
1551 ASSERT(apic != NULL);
1552
1553 /* Stop the timer in case it's a reset to an active apic */
1554 hrtimer_cancel(&apic->lapic_timer.timer);
1555
1556 kvm_apic_set_id(apic, vcpu->vcpu_id);
1557 kvm_apic_set_version(apic->vcpu);
1558
1559 for (i = 0; i < APIC_LVT_NUM; i++)
1560 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1561 apic->lapic_timer.timer_mode = 0;
1562 apic_set_reg(apic, APIC_LVT0,
1563 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1564
1565 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1566 apic_set_spiv(apic, 0xff);
1567 apic_set_reg(apic, APIC_TASKPRI, 0);
1568 kvm_apic_set_ldr(apic, 0);
1569 apic_set_reg(apic, APIC_ESR, 0);
1570 apic_set_reg(apic, APIC_ICR, 0);
1571 apic_set_reg(apic, APIC_ICR2, 0);
1572 apic_set_reg(apic, APIC_TDCR, 0);
1573 apic_set_reg(apic, APIC_TMICT, 0);
1574 for (i = 0; i < 8; i++) {
1575 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1576 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1577 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1578 }
1579 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1580 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1581 apic->highest_isr_cache = -1;
1582 update_divide_count(apic);
1583 atomic_set(&apic->lapic_timer.pending, 0);
1584 if (kvm_vcpu_is_bsp(vcpu))
1585 kvm_lapic_set_base(vcpu,
1586 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1587 vcpu->arch.pv_eoi.msr_val = 0;
1588 apic_update_ppr(apic);
1589
1590 vcpu->arch.apic_arb_prio = 0;
1591 vcpu->arch.apic_attention = 0;
1592
1593 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1594 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1595 vcpu, kvm_apic_id(apic),
1596 vcpu->arch.apic_base, apic->base_address);
1597 }
1598
1599 /*
1600 *----------------------------------------------------------------------
1601 * timer interface
1602 *----------------------------------------------------------------------
1603 */
1604
1605 static bool lapic_is_periodic(struct kvm_lapic *apic)
1606 {
1607 return apic_lvtt_period(apic);
1608 }
1609
1610 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1611 {
1612 struct kvm_lapic *apic = vcpu->arch.apic;
1613
1614 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1615 apic_lvt_enabled(apic, APIC_LVTT))
1616 return atomic_read(&apic->lapic_timer.pending);
1617
1618 return 0;
1619 }
1620
1621 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1622 {
1623 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1624 int vector, mode, trig_mode;
1625
1626 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1627 vector = reg & APIC_VECTOR_MASK;
1628 mode = reg & APIC_MODE_MASK;
1629 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1630 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1631 NULL);
1632 }
1633 return 0;
1634 }
1635
1636 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1637 {
1638 struct kvm_lapic *apic = vcpu->arch.apic;
1639
1640 if (apic)
1641 kvm_apic_local_deliver(apic, APIC_LVT0);
1642 }
1643
1644 static const struct kvm_io_device_ops apic_mmio_ops = {
1645 .read = apic_mmio_read,
1646 .write = apic_mmio_write,
1647 };
1648
1649 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1650 {
1651 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1652 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1653
1654 apic_timer_expired(apic);
1655
1656 if (lapic_is_periodic(apic)) {
1657 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1658 return HRTIMER_RESTART;
1659 } else
1660 return HRTIMER_NORESTART;
1661 }
1662
1663 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1664 {
1665 struct kvm_lapic *apic;
1666
1667 ASSERT(vcpu != NULL);
1668 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1669
1670 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1671 if (!apic)
1672 goto nomem;
1673
1674 vcpu->arch.apic = apic;
1675
1676 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1677 if (!apic->regs) {
1678 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1679 vcpu->vcpu_id);
1680 goto nomem_free_apic;
1681 }
1682 apic->vcpu = vcpu;
1683
1684 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1685 HRTIMER_MODE_ABS);
1686 apic->lapic_timer.timer.function = apic_timer_fn;
1687
1688 /*
1689 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1690 * thinking that APIC satet has changed.
1691 */
1692 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1693 kvm_lapic_set_base(vcpu,
1694 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1695
1696 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1697 kvm_lapic_reset(vcpu);
1698 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1699
1700 return 0;
1701 nomem_free_apic:
1702 kfree(apic);
1703 nomem:
1704 return -ENOMEM;
1705 }
1706
1707 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1708 {
1709 struct kvm_lapic *apic = vcpu->arch.apic;
1710 int highest_irr;
1711
1712 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1713 return -1;
1714
1715 apic_update_ppr(apic);
1716 highest_irr = apic_find_highest_irr(apic);
1717 if ((highest_irr == -1) ||
1718 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1719 return -1;
1720 return highest_irr;
1721 }
1722
1723 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1724 {
1725 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1726 int r = 0;
1727
1728 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1729 r = 1;
1730 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1731 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1732 r = 1;
1733 return r;
1734 }
1735
1736 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1737 {
1738 struct kvm_lapic *apic = vcpu->arch.apic;
1739
1740 if (!kvm_vcpu_has_lapic(vcpu))
1741 return;
1742
1743 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1744 kvm_apic_local_deliver(apic, APIC_LVTT);
1745 if (apic_lvtt_tscdeadline(apic))
1746 apic->lapic_timer.tscdeadline = 0;
1747 atomic_set(&apic->lapic_timer.pending, 0);
1748 }
1749 }
1750
1751 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1752 {
1753 int vector = kvm_apic_has_interrupt(vcpu);
1754 struct kvm_lapic *apic = vcpu->arch.apic;
1755
1756 if (vector == -1)
1757 return -1;
1758
1759 /*
1760 * We get here even with APIC virtualization enabled, if doing
1761 * nested virtualization and L1 runs with the "acknowledge interrupt
1762 * on exit" mode. Then we cannot inject the interrupt via RVI,
1763 * because the process would deliver it through the IDT.
1764 */
1765
1766 apic_set_isr(vector, apic);
1767 apic_update_ppr(apic);
1768 apic_clear_irr(vector, apic);
1769 return vector;
1770 }
1771
1772 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1773 struct kvm_lapic_state *s)
1774 {
1775 struct kvm_lapic *apic = vcpu->arch.apic;
1776
1777 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1778 /* set SPIV separately to get count of SW disabled APICs right */
1779 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1780 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1781 /* call kvm_apic_set_id() to put apic into apic_map */
1782 kvm_apic_set_id(apic, kvm_apic_id(apic));
1783 kvm_apic_set_version(vcpu);
1784
1785 apic_update_ppr(apic);
1786 hrtimer_cancel(&apic->lapic_timer.timer);
1787 update_divide_count(apic);
1788 start_apic_timer(apic);
1789 apic->irr_pending = true;
1790 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1791 1 : count_vectors(apic->regs + APIC_ISR);
1792 apic->highest_isr_cache = -1;
1793 if (kvm_x86_ops->hwapic_irr_update)
1794 kvm_x86_ops->hwapic_irr_update(vcpu,
1795 apic_find_highest_irr(apic));
1796 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1797 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1798 apic_find_highest_isr(apic));
1799 kvm_make_request(KVM_REQ_EVENT, vcpu);
1800 kvm_rtc_eoi_tracking_restore_one(vcpu);
1801 }
1802
1803 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1804 {
1805 struct hrtimer *timer;
1806
1807 if (!kvm_vcpu_has_lapic(vcpu))
1808 return;
1809
1810 timer = &vcpu->arch.apic->lapic_timer.timer;
1811 if (hrtimer_cancel(timer))
1812 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1813 }
1814
1815 /*
1816 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1817 *
1818 * Detect whether guest triggered PV EOI since the
1819 * last entry. If yes, set EOI on guests's behalf.
1820 * Clear PV EOI in guest memory in any case.
1821 */
1822 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1823 struct kvm_lapic *apic)
1824 {
1825 bool pending;
1826 int vector;
1827 /*
1828 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1829 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1830 *
1831 * KVM_APIC_PV_EOI_PENDING is unset:
1832 * -> host disabled PV EOI.
1833 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1834 * -> host enabled PV EOI, guest did not execute EOI yet.
1835 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1836 * -> host enabled PV EOI, guest executed EOI.
1837 */
1838 BUG_ON(!pv_eoi_enabled(vcpu));
1839 pending = pv_eoi_get_pending(vcpu);
1840 /*
1841 * Clear pending bit in any case: it will be set again on vmentry.
1842 * While this might not be ideal from performance point of view,
1843 * this makes sure pv eoi is only enabled when we know it's safe.
1844 */
1845 pv_eoi_clr_pending(vcpu);
1846 if (pending)
1847 return;
1848 vector = apic_set_eoi(apic);
1849 trace_kvm_pv_eoi(apic, vector);
1850 }
1851
1852 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1853 {
1854 u32 data;
1855
1856 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1857 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1858
1859 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1860 return;
1861
1862 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1863 sizeof(u32));
1864
1865 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1866 }
1867
1868 /*
1869 * apic_sync_pv_eoi_to_guest - called before vmentry
1870 *
1871 * Detect whether it's safe to enable PV EOI and
1872 * if yes do so.
1873 */
1874 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1875 struct kvm_lapic *apic)
1876 {
1877 if (!pv_eoi_enabled(vcpu) ||
1878 /* IRR set or many bits in ISR: could be nested. */
1879 apic->irr_pending ||
1880 /* Cache not set: could be safe but we don't bother. */
1881 apic->highest_isr_cache == -1 ||
1882 /* Need EOI to update ioapic. */
1883 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1884 /*
1885 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1886 * so we need not do anything here.
1887 */
1888 return;
1889 }
1890
1891 pv_eoi_set_pending(apic->vcpu);
1892 }
1893
1894 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1895 {
1896 u32 data, tpr;
1897 int max_irr, max_isr;
1898 struct kvm_lapic *apic = vcpu->arch.apic;
1899
1900 apic_sync_pv_eoi_to_guest(vcpu, apic);
1901
1902 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1903 return;
1904
1905 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1906 max_irr = apic_find_highest_irr(apic);
1907 if (max_irr < 0)
1908 max_irr = 0;
1909 max_isr = apic_find_highest_isr(apic);
1910 if (max_isr < 0)
1911 max_isr = 0;
1912 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1913
1914 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1915 sizeof(u32));
1916 }
1917
1918 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1919 {
1920 if (vapic_addr) {
1921 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1922 &vcpu->arch.apic->vapic_cache,
1923 vapic_addr, sizeof(u32)))
1924 return -EINVAL;
1925 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1926 } else {
1927 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1928 }
1929
1930 vcpu->arch.apic->vapic_addr = vapic_addr;
1931 return 0;
1932 }
1933
1934 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1935 {
1936 struct kvm_lapic *apic = vcpu->arch.apic;
1937 u32 reg = (msr - APIC_BASE_MSR) << 4;
1938
1939 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1940 return 1;
1941
1942 if (reg == APIC_ICR2)
1943 return 1;
1944
1945 /* if this is ICR write vector before command */
1946 if (reg == APIC_ICR)
1947 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1948 return apic_reg_write(apic, reg, (u32)data);
1949 }
1950
1951 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1952 {
1953 struct kvm_lapic *apic = vcpu->arch.apic;
1954 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1955
1956 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1957 return 1;
1958
1959 if (reg == APIC_DFR || reg == APIC_ICR2) {
1960 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1961 reg);
1962 return 1;
1963 }
1964
1965 if (apic_reg_read(apic, reg, 4, &low))
1966 return 1;
1967 if (reg == APIC_ICR)
1968 apic_reg_read(apic, APIC_ICR2, 4, &high);
1969
1970 *data = (((u64)high) << 32) | low;
1971
1972 return 0;
1973 }
1974
1975 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1976 {
1977 struct kvm_lapic *apic = vcpu->arch.apic;
1978
1979 if (!kvm_vcpu_has_lapic(vcpu))
1980 return 1;
1981
1982 /* if this is ICR write vector before command */
1983 if (reg == APIC_ICR)
1984 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1985 return apic_reg_write(apic, reg, (u32)data);
1986 }
1987
1988 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1989 {
1990 struct kvm_lapic *apic = vcpu->arch.apic;
1991 u32 low, high = 0;
1992
1993 if (!kvm_vcpu_has_lapic(vcpu))
1994 return 1;
1995
1996 if (apic_reg_read(apic, reg, 4, &low))
1997 return 1;
1998 if (reg == APIC_ICR)
1999 apic_reg_read(apic, APIC_ICR2, 4, &high);
2000
2001 *data = (((u64)high) << 32) | low;
2002
2003 return 0;
2004 }
2005
2006 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2007 {
2008 u64 addr = data & ~KVM_MSR_ENABLED;
2009 if (!IS_ALIGNED(addr, 4))
2010 return 1;
2011
2012 vcpu->arch.pv_eoi.msr_val = data;
2013 if (!pv_eoi_enabled(vcpu))
2014 return 0;
2015 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2016 addr, sizeof(u8));
2017 }
2018
2019 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2020 {
2021 struct kvm_lapic *apic = vcpu->arch.apic;
2022 u8 sipi_vector;
2023 unsigned long pe;
2024
2025 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2026 return;
2027
2028 pe = xchg(&apic->pending_events, 0);
2029
2030 if (test_bit(KVM_APIC_INIT, &pe)) {
2031 kvm_lapic_reset(vcpu);
2032 kvm_vcpu_reset(vcpu);
2033 if (kvm_vcpu_is_bsp(apic->vcpu))
2034 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2035 else
2036 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2037 }
2038 if (test_bit(KVM_APIC_SIPI, &pe) &&
2039 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2040 /* evaluate pending_events before reading the vector */
2041 smp_rmb();
2042 sipi_vector = apic->sipi_vector;
2043 apic_debug("vcpu %d received sipi with vector # %x\n",
2044 vcpu->vcpu_id, sipi_vector);
2045 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2046 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2047 }
2048 }
2049
2050 void kvm_lapic_init(void)
2051 {
2052 /* do not patch jump label more than once per second */
2053 jump_label_rate_limit(&apic_hw_disabled, HZ);
2054 jump_label_rate_limit(&apic_sw_disabled, HZ);
2055 }
Linux kernel - Deliverables
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