3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
80 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
83 static inline int apic_test_vector(int vec
, void *bitmap
)
85 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
90 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
92 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
93 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
96 static inline void apic_set_vector(int vec
, void *bitmap
)
98 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
101 static inline void apic_clear_vector(int vec
, void *bitmap
)
103 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
106 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
108 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
111 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
113 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
116 struct static_key_deferred apic_hw_disabled __read_mostly
;
117 struct static_key_deferred apic_sw_disabled __read_mostly
;
119 static inline int apic_enabled(struct kvm_lapic
*apic
)
121 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
133 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map
*map
)
141 return !(map
->mode
& (map
->mode
- 1));
145 apic_logical_id(struct kvm_apic_map
*map
, u32 dest_id
, u16
*cid
, u16
*lid
)
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER
!= 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT
!= 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC
!= 16);
152 lid_bits
= map
->mode
;
154 *cid
= dest_id
>> lid_bits
;
155 *lid
= dest_id
& ((1 << lid_bits
) - 1);
158 static void recalculate_apic_map(struct kvm
*kvm
)
160 struct kvm_apic_map
*new, *old
= NULL
;
161 struct kvm_vcpu
*vcpu
;
164 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
166 mutex_lock(&kvm
->arch
.apic_map_lock
);
171 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
172 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
176 if (!kvm_apic_present(vcpu
))
179 aid
= kvm_apic_id(apic
);
180 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
182 if (aid
< ARRAY_SIZE(new->phys_map
))
183 new->phys_map
[aid
] = apic
;
185 if (apic_x2apic_mode(apic
)) {
186 new->mode
|= KVM_APIC_MODE_X2APIC
;
188 ldr
= GET_APIC_LOGICAL_ID(ldr
);
189 if (kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
190 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
192 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
195 if (!kvm_apic_logical_map_valid(new))
198 apic_logical_id(new, ldr
, &cid
, &lid
);
200 if (lid
&& cid
< ARRAY_SIZE(new->logical_map
))
201 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
204 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
205 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
206 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
207 mutex_unlock(&kvm
->arch
.apic_map_lock
);
212 kvm_make_scan_ioapic_request(kvm
);
215 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
217 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
219 apic_set_reg(apic
, APIC_SPIV
, val
);
221 if (enabled
!= apic
->sw_enabled
) {
222 apic
->sw_enabled
= enabled
;
224 static_key_slow_dec_deferred(&apic_sw_disabled
);
225 recalculate_apic_map(apic
->vcpu
->kvm
);
227 static_key_slow_inc(&apic_sw_disabled
.key
);
231 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
233 apic_set_reg(apic
, APIC_ID
, id
<< 24);
234 recalculate_apic_map(apic
->vcpu
->kvm
);
237 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
239 apic_set_reg(apic
, APIC_LDR
, id
);
240 recalculate_apic_map(apic
->vcpu
->kvm
);
243 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic
*apic
, u8 id
)
245 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
247 apic_set_reg(apic
, APIC_ID
, id
<< 24);
248 apic_set_reg(apic
, APIC_LDR
, ldr
);
249 recalculate_apic_map(apic
->vcpu
->kvm
);
252 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
254 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
257 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
259 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
262 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
264 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
267 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
269 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
272 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
274 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
277 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
279 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
282 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
284 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
285 struct kvm_cpuid_entry2
*feat
;
286 u32 v
= APIC_VERSION
;
288 if (!kvm_vcpu_has_lapic(vcpu
))
291 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
292 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
293 v
|= APIC_LVR_DIRECTED_EOI
;
294 apic_set_reg(apic
, APIC_LVR
, v
);
297 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
298 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
299 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
300 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
301 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
302 LVT_MASK
/* LVTERR */
305 static int find_highest_vector(void *bitmap
)
310 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
311 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
312 reg
= bitmap
+ REG_POS(vec
);
314 return fls(*reg
) - 1 + vec
;
320 static u8
count_vectors(void *bitmap
)
326 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
327 reg
= bitmap
+ REG_POS(vec
);
328 count
+= hweight32(*reg
);
334 void __kvm_apic_update_irr(u32
*pir
, void *regs
)
338 for (i
= 0; i
<= 7; i
++) {
339 pir_val
= xchg(&pir
[i
], 0);
341 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
344 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
346 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
348 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
350 __kvm_apic_update_irr(pir
, apic
->regs
);
352 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
354 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
356 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
358 * irr_pending must be true if any interrupt is pending; set it after
359 * APIC_IRR to avoid race with apic_clear_irr
361 apic
->irr_pending
= true;
364 static inline int apic_search_irr(struct kvm_lapic
*apic
)
366 return find_highest_vector(apic
->regs
+ APIC_IRR
);
369 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
377 if (!apic
->irr_pending
)
380 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
381 result
= apic_search_irr(apic
);
382 ASSERT(result
== -1 || result
>= 16);
387 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
389 struct kvm_vcpu
*vcpu
;
393 if (unlikely(kvm_vcpu_apic_vid_enabled(vcpu
))) {
394 /* try to update RVI */
395 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
396 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
398 apic
->irr_pending
= false;
399 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
400 if (apic_search_irr(apic
) != -1)
401 apic
->irr_pending
= true;
405 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
407 struct kvm_vcpu
*vcpu
;
409 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
415 * With APIC virtualization enabled, all caching is disabled
416 * because the processor can modify ISR under the hood. Instead
419 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
420 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
423 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
425 * ISR (in service register) bit is set when injecting an interrupt.
426 * The highest vector is injected. Thus the latest bit set matches
427 * the highest bit in ISR.
429 apic
->highest_isr_cache
= vec
;
433 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
438 * Note that isr_count is always 1, and highest_isr_cache
439 * is always -1, with APIC virtualization enabled.
441 if (!apic
->isr_count
)
443 if (likely(apic
->highest_isr_cache
!= -1))
444 return apic
->highest_isr_cache
;
446 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
447 ASSERT(result
== -1 || result
>= 16);
452 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
454 struct kvm_vcpu
*vcpu
;
455 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
461 * We do get here for APIC virtualization enabled if the guest
462 * uses the Hyper-V APIC enlightenment. In this case we may need
463 * to trigger a new interrupt delivery by writing the SVI field;
464 * on the other hand isr_count and highest_isr_cache are unused
465 * and must be left alone.
467 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
468 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
469 apic_find_highest_isr(apic
));
472 BUG_ON(apic
->isr_count
< 0);
473 apic
->highest_isr_cache
= -1;
477 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
481 /* This may race with setting of irr in __apic_accept_irq() and
482 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
483 * will cause vmexit immediately and the value will be recalculated
484 * on the next vmentry.
486 if (!kvm_vcpu_has_lapic(vcpu
))
488 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
493 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
494 int vector
, int level
, int trig_mode
,
495 unsigned long *dest_map
);
497 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
498 unsigned long *dest_map
)
500 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
502 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
503 irq
->level
, irq
->trig_mode
, dest_map
);
506 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
509 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
513 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
516 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
520 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
522 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
525 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
528 if (pv_eoi_get_user(vcpu
, &val
) < 0)
529 apic_debug("Can't read EOI MSR value: 0x%llx\n",
530 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
534 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
536 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
537 apic_debug("Can't set EOI MSR value: 0x%llx\n",
538 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
541 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
544 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
546 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
547 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
548 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
551 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
554 static void apic_update_ppr(struct kvm_lapic
*apic
)
556 u32 tpr
, isrv
, ppr
, old_ppr
;
559 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
560 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
561 isr
= apic_find_highest_isr(apic
);
562 isrv
= (isr
!= -1) ? isr
: 0;
564 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic
, ppr
, isr
, isrv
);
572 if (old_ppr
!= ppr
) {
573 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
575 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
579 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
581 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
582 apic_update_ppr(apic
);
585 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
587 if (apic_x2apic_mode(apic
))
588 return mda
== X2APIC_BROADCAST
;
590 return GET_APIC_DEST_FIELD(mda
) == APIC_BROADCAST
;
593 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
595 if (kvm_apic_broadcast(apic
, mda
))
598 if (apic_x2apic_mode(apic
))
599 return mda
== kvm_apic_id(apic
);
601 return mda
== SET_APIC_DEST_FIELD(kvm_apic_id(apic
));
604 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
608 if (kvm_apic_broadcast(apic
, mda
))
611 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
613 if (apic_x2apic_mode(apic
))
614 return ((logical_id
>> 16) == (mda
>> 16))
615 && (logical_id
& mda
& 0xffff) != 0;
617 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
618 mda
= GET_APIC_DEST_FIELD(mda
);
620 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
622 return (logical_id
& mda
) != 0;
623 case APIC_DFR_CLUSTER
:
624 return ((logical_id
>> 4) == (mda
>> 4))
625 && (logical_id
& mda
& 0xf) != 0;
627 apic_debug("Bad DFR vcpu %d: %08x\n",
628 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
633 /* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
637 static u32
kvm_apic_mda(unsigned int dest_id
, struct kvm_lapic
*source
,
638 struct kvm_lapic
*target
)
640 bool ipi
= source
!= NULL
;
641 bool x2apic_mda
= apic_x2apic_mode(ipi
? source
: target
);
643 if (!ipi
&& dest_id
== APIC_BROADCAST
&& x2apic_mda
)
644 return X2APIC_BROADCAST
;
646 return x2apic_mda
? dest_id
: SET_APIC_DEST_FIELD(dest_id
);
649 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
650 int short_hand
, unsigned int dest
, int dest_mode
)
652 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
653 u32 mda
= kvm_apic_mda(dest
, source
, target
);
655 apic_debug("target %p, source %p, dest 0x%x, "
656 "dest_mode 0x%x, short_hand 0x%x\n",
657 target
, source
, dest
, dest_mode
, short_hand
);
660 switch (short_hand
) {
661 case APIC_DEST_NOSHORT
:
662 if (dest_mode
== APIC_DEST_PHYSICAL
)
663 return kvm_apic_match_physical_addr(target
, mda
);
665 return kvm_apic_match_logical_addr(target
, mda
);
667 return target
== source
;
668 case APIC_DEST_ALLINC
:
670 case APIC_DEST_ALLBUT
:
671 return target
!= source
;
673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
679 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
680 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
682 struct kvm_apic_map
*map
;
683 unsigned long bitmap
= 1;
684 struct kvm_lapic
**dst
;
686 bool ret
, x2apic_ipi
;
690 if (irq
->shorthand
== APIC_DEST_SELF
) {
691 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
698 x2apic_ipi
= src
&& apic_x2apic_mode(src
);
699 if (irq
->dest_id
== (x2apic_ipi
? X2APIC_BROADCAST
: APIC_BROADCAST
))
704 map
= rcu_dereference(kvm
->arch
.apic_map
);
711 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
712 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
715 dst
= &map
->phys_map
[irq
->dest_id
];
719 if (!kvm_apic_logical_map_valid(map
)) {
724 apic_logical_id(map
, irq
->dest_id
, &cid
, (u16
*)&bitmap
);
726 if (cid
>= ARRAY_SIZE(map
->logical_map
))
729 dst
= map
->logical_map
[cid
];
731 if (kvm_lowest_prio_delivery(irq
)) {
733 for_each_set_bit(i
, &bitmap
, 16) {
738 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
742 bitmap
= (l
>= 0) ? 1 << l
: 0;
746 for_each_set_bit(i
, &bitmap
, 16) {
751 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
758 bool kvm_intr_is_single_vcpu_fast(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
759 struct kvm_vcpu
**dest_vcpu
)
761 struct kvm_apic_map
*map
;
763 struct kvm_lapic
*dst
= NULL
;
769 map
= rcu_dereference(kvm
->arch
.apic_map
);
774 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
775 if (irq
->dest_id
== 0xFF)
778 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
781 dst
= map
->phys_map
[irq
->dest_id
];
782 if (dst
&& kvm_apic_present(dst
->vcpu
))
783 *dest_vcpu
= dst
->vcpu
;
788 unsigned long bitmap
= 1;
791 if (!kvm_apic_logical_map_valid(map
))
794 apic_logical_id(map
, irq
->dest_id
, &cid
, (u16
*)&bitmap
);
796 if (cid
>= ARRAY_SIZE(map
->logical_map
))
799 for_each_set_bit(i
, &bitmap
, 16) {
800 dst
= map
->logical_map
[cid
][i
];
805 if (dst
&& kvm_apic_present(dst
->vcpu
))
806 *dest_vcpu
= dst
->vcpu
;
818 * Add a pending IRQ into lapic.
819 * Return 1 if successfully added and 0 if discarded.
821 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
822 int vector
, int level
, int trig_mode
,
823 unsigned long *dest_map
)
826 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
828 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
830 switch (delivery_mode
) {
832 vcpu
->arch
.apic_arb_prio
++;
834 if (unlikely(trig_mode
&& !level
))
837 /* FIXME add logic for vcpu on reset */
838 if (unlikely(!apic_enabled(apic
)))
844 __set_bit(vcpu
->vcpu_id
, dest_map
);
846 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
) != !!trig_mode
) {
848 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
850 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
853 if (kvm_x86_ops
->deliver_posted_interrupt
)
854 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
856 apic_set_irr(vector
, apic
);
858 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
865 vcpu
->arch
.pv
.pv_unhalted
= 1;
866 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
872 kvm_make_request(KVM_REQ_SMI
, vcpu
);
878 kvm_inject_nmi(vcpu
);
883 if (!trig_mode
|| level
) {
885 /* assumes that there are only KVM_APIC_INIT/SIPI */
886 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
887 /* make sure pending_events is visible before sending
890 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
893 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
898 case APIC_DM_STARTUP
:
899 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
900 vcpu
->vcpu_id
, vector
);
902 apic
->sipi_vector
= vector
;
903 /* make sure sipi_vector is visible for the receiver */
905 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
906 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
912 * Should only be called by kvm_apic_local_deliver() with LVT0,
913 * before NMI watchdog was enabled. Already handled by
914 * kvm_apic_accept_pic_intr().
919 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
926 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
928 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
931 static bool kvm_ioapic_handles_vector(struct kvm_lapic
*apic
, int vector
)
933 return test_bit(vector
, (ulong
*)apic
->vcpu
->arch
.eoi_exit_bitmap
);
936 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
940 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
941 if (!kvm_ioapic_handles_vector(apic
, vector
))
944 /* Request a KVM exit to inform the userspace IOAPIC. */
945 if (irqchip_split(apic
->vcpu
->kvm
)) {
946 apic
->vcpu
->arch
.pending_ioapic_eoi
= vector
;
947 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT
, apic
->vcpu
);
951 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
952 trigger_mode
= IOAPIC_LEVEL_TRIG
;
954 trigger_mode
= IOAPIC_EDGE_TRIG
;
956 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
959 static int apic_set_eoi(struct kvm_lapic
*apic
)
961 int vector
= apic_find_highest_isr(apic
);
963 trace_kvm_eoi(apic
, vector
);
966 * Not every write EOI will has corresponding ISR,
967 * one example is when Kernel check timer on setup_IO_APIC
972 apic_clear_isr(vector
, apic
);
973 apic_update_ppr(apic
);
975 kvm_ioapic_send_eoi(apic
, vector
);
976 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
981 * this interface assumes a trap-like exit, which has already finished
982 * desired side effect including vISR and vPPR update.
984 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
986 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
988 trace_kvm_eoi(apic
, vector
);
990 kvm_ioapic_send_eoi(apic
, vector
);
991 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
993 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
995 static void apic_send_ipi(struct kvm_lapic
*apic
)
997 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
998 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
999 struct kvm_lapic_irq irq
;
1001 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
1002 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
1003 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
1004 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
1005 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
1006 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
1007 irq
.msi_redir_hint
= false;
1008 if (apic_x2apic_mode(apic
))
1009 irq
.dest_id
= icr_high
;
1011 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
1013 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
1015 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1016 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1017 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1018 "msi_redir_hint 0x%x\n",
1019 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
1020 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
1021 irq
.vector
, irq
.msi_redir_hint
);
1023 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
1026 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
1032 ASSERT(apic
!= NULL
);
1034 /* if initial count is 0, current count should also be 0 */
1035 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
1036 apic
->lapic_timer
.period
== 0)
1039 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
1040 if (ktime_to_ns(remaining
) < 0)
1041 remaining
= ktime_set(0, 0);
1043 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
1044 tmcct
= div64_u64(ns
,
1045 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
1050 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1052 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1053 struct kvm_run
*run
= vcpu
->run
;
1055 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
1056 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
1057 run
->tpr_access
.is_write
= write
;
1060 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1062 if (apic
->vcpu
->arch
.tpr_access_reporting
)
1063 __report_tpr_access(apic
, write
);
1066 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
1070 if (offset
>= LAPIC_MMIO_LENGTH
)
1075 if (apic_x2apic_mode(apic
))
1076 val
= kvm_apic_id(apic
);
1078 val
= kvm_apic_id(apic
) << 24;
1081 apic_debug("Access APIC ARBPRI register which is for P6\n");
1084 case APIC_TMCCT
: /* Timer CCR */
1085 if (apic_lvtt_tscdeadline(apic
))
1088 val
= apic_get_tmcct(apic
);
1091 apic_update_ppr(apic
);
1092 val
= kvm_apic_get_reg(apic
, offset
);
1095 report_tpr_access(apic
, false);
1098 val
= kvm_apic_get_reg(apic
, offset
);
1105 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1107 return container_of(dev
, struct kvm_lapic
, dev
);
1110 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1113 unsigned char alignment
= offset
& 0xf;
1115 /* this bitmask has a bit cleared for each reserved register */
1116 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1118 if ((alignment
+ len
) > 4) {
1119 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1124 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1125 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1130 result
= __apic_read(apic
, offset
& ~0xf);
1132 trace_kvm_apic_read(offset
, result
);
1138 memcpy(data
, (char *)&result
+ alignment
, len
);
1141 printk(KERN_ERR
"Local APIC read with len = %x, "
1142 "should be 1,2, or 4 instead\n", len
);
1148 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1150 return kvm_apic_hw_enabled(apic
) &&
1151 addr
>= apic
->base_address
&&
1152 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1155 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1156 gpa_t address
, int len
, void *data
)
1158 struct kvm_lapic
*apic
= to_lapic(this);
1159 u32 offset
= address
- apic
->base_address
;
1161 if (!apic_mmio_in_range(apic
, address
))
1164 apic_reg_read(apic
, offset
, len
, data
);
1169 static void update_divide_count(struct kvm_lapic
*apic
)
1171 u32 tmp1
, tmp2
, tdcr
;
1173 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1175 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1176 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1178 apic_debug("timer divide count is 0x%x\n",
1179 apic
->divide_count
);
1182 static void apic_update_lvtt(struct kvm_lapic
*apic
)
1184 u32 timer_mode
= kvm_apic_get_reg(apic
, APIC_LVTT
) &
1185 apic
->lapic_timer
.timer_mode_mask
;
1187 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1188 apic
->lapic_timer
.timer_mode
= timer_mode
;
1189 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1193 static void apic_timer_expired(struct kvm_lapic
*apic
)
1195 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1196 wait_queue_head_t
*q
= &vcpu
->wq
;
1197 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1199 if (atomic_read(&apic
->lapic_timer
.pending
))
1202 atomic_inc(&apic
->lapic_timer
.pending
);
1203 kvm_set_pending_timer(vcpu
);
1205 if (waitqueue_active(q
))
1206 wake_up_interruptible(q
);
1208 if (apic_lvtt_tscdeadline(apic
))
1209 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1213 * On APICv, this test will cause a busy wait
1214 * during a higher-priority task.
1217 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1219 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1220 u32 reg
= kvm_apic_get_reg(apic
, APIC_LVTT
);
1222 if (kvm_apic_hw_enabled(apic
)) {
1223 int vec
= reg
& APIC_VECTOR_MASK
;
1224 void *bitmap
= apic
->regs
+ APIC_ISR
;
1226 if (kvm_x86_ops
->deliver_posted_interrupt
)
1227 bitmap
= apic
->regs
+ APIC_IRR
;
1229 if (apic_test_vector(vec
, bitmap
))
1235 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1237 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1238 u64 guest_tsc
, tsc_deadline
;
1240 if (!kvm_vcpu_has_lapic(vcpu
))
1243 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1246 if (!lapic_timer_int_injected(vcpu
))
1249 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1250 apic
->lapic_timer
.expired_tscdeadline
= 0;
1251 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, rdtsc());
1252 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1254 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1255 if (guest_tsc
< tsc_deadline
)
1256 __delay(tsc_deadline
- guest_tsc
);
1259 static void start_apic_timer(struct kvm_lapic
*apic
)
1263 atomic_set(&apic
->lapic_timer
.pending
, 0);
1265 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1266 /* lapic timer in oneshot or periodic mode */
1267 now
= apic
->lapic_timer
.timer
.base
->get_time();
1268 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1269 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1271 if (!apic
->lapic_timer
.period
)
1274 * Do not allow the guest to program periodic timers with small
1275 * interval, since the hrtimers are not throttled by the host
1278 if (apic_lvtt_period(apic
)) {
1279 s64 min_period
= min_timer_period_us
* 1000LL;
1281 if (apic
->lapic_timer
.period
< min_period
) {
1282 pr_info_ratelimited(
1283 "kvm: vcpu %i: requested %lld ns "
1284 "lapic timer period limited to %lld ns\n",
1285 apic
->vcpu
->vcpu_id
,
1286 apic
->lapic_timer
.period
, min_period
);
1287 apic
->lapic_timer
.period
= min_period
;
1291 hrtimer_start(&apic
->lapic_timer
.timer
,
1292 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1295 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1297 "timer initial count 0x%x, period %lldns, "
1298 "expire @ 0x%016" PRIx64
".\n", __func__
,
1299 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1300 kvm_apic_get_reg(apic
, APIC_TMICT
),
1301 apic
->lapic_timer
.period
,
1302 ktime_to_ns(ktime_add_ns(now
,
1303 apic
->lapic_timer
.period
)));
1304 } else if (apic_lvtt_tscdeadline(apic
)) {
1305 /* lapic timer in tsc deadline mode */
1306 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1309 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1310 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1311 unsigned long flags
;
1313 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1316 local_irq_save(flags
);
1318 now
= apic
->lapic_timer
.timer
.base
->get_time();
1319 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, rdtsc());
1320 if (likely(tscdeadline
> guest_tsc
)) {
1321 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1322 do_div(ns
, this_tsc_khz
);
1323 expire
= ktime_add_ns(now
, ns
);
1324 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1325 hrtimer_start(&apic
->lapic_timer
.timer
,
1326 expire
, HRTIMER_MODE_ABS
);
1328 apic_timer_expired(apic
);
1330 local_irq_restore(flags
);
1334 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1336 bool lvt0_in_nmi_mode
= apic_lvt_nmi_mode(lvt0_val
);
1338 if (apic
->lvt0_in_nmi_mode
!= lvt0_in_nmi_mode
) {
1339 apic
->lvt0_in_nmi_mode
= lvt0_in_nmi_mode
;
1340 if (lvt0_in_nmi_mode
) {
1341 apic_debug("Receive NMI setting on APIC_LVT0 "
1342 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1343 atomic_inc(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1345 atomic_dec(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1349 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1353 trace_kvm_apic_write(reg
, val
);
1356 case APIC_ID
: /* Local APIC ID */
1357 if (!apic_x2apic_mode(apic
))
1358 kvm_apic_set_id(apic
, val
>> 24);
1364 report_tpr_access(apic
, true);
1365 apic_set_tpr(apic
, val
& 0xff);
1373 if (!apic_x2apic_mode(apic
))
1374 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1380 if (!apic_x2apic_mode(apic
)) {
1381 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1382 recalculate_apic_map(apic
->vcpu
->kvm
);
1389 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1390 mask
|= APIC_SPIV_DIRECTED_EOI
;
1391 apic_set_spiv(apic
, val
& mask
);
1392 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1396 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1397 lvt_val
= kvm_apic_get_reg(apic
,
1398 APIC_LVTT
+ 0x10 * i
);
1399 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1400 lvt_val
| APIC_LVT_MASKED
);
1402 apic_update_lvtt(apic
);
1403 atomic_set(&apic
->lapic_timer
.pending
, 0);
1409 /* No delay here, so we always clear the pending bit */
1410 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1411 apic_send_ipi(apic
);
1415 if (!apic_x2apic_mode(apic
))
1417 apic_set_reg(apic
, APIC_ICR2
, val
);
1421 apic_manage_nmi_watchdog(apic
, val
);
1426 /* TODO: Check vector */
1427 if (!kvm_apic_sw_enabled(apic
))
1428 val
|= APIC_LVT_MASKED
;
1430 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1431 apic_set_reg(apic
, reg
, val
);
1436 if (!kvm_apic_sw_enabled(apic
))
1437 val
|= APIC_LVT_MASKED
;
1438 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1439 apic_set_reg(apic
, APIC_LVTT
, val
);
1440 apic_update_lvtt(apic
);
1444 if (apic_lvtt_tscdeadline(apic
))
1447 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1448 apic_set_reg(apic
, APIC_TMICT
, val
);
1449 start_apic_timer(apic
);
1454 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1455 apic_set_reg(apic
, APIC_TDCR
, val
);
1456 update_divide_count(apic
);
1460 if (apic_x2apic_mode(apic
) && val
!= 0) {
1461 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1467 if (apic_x2apic_mode(apic
)) {
1468 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1477 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1481 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1482 gpa_t address
, int len
, const void *data
)
1484 struct kvm_lapic
*apic
= to_lapic(this);
1485 unsigned int offset
= address
- apic
->base_address
;
1488 if (!apic_mmio_in_range(apic
, address
))
1492 * APIC register must be aligned on 128-bits boundary.
1493 * 32/64/128 bits registers must be accessed thru 32 bits.
1496 if (len
!= 4 || (offset
& 0xf)) {
1497 /* Don't shout loud, $infamous_os would cause only noise. */
1498 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1504 /* too common printing */
1505 if (offset
!= APIC_EOI
)
1506 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1507 "0x%x\n", __func__
, offset
, len
, val
);
1509 apic_reg_write(apic
, offset
& 0xff0, val
);
1514 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1516 if (kvm_vcpu_has_lapic(vcpu
))
1517 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1519 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1521 /* emulate APIC access in a trap manner */
1522 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1526 /* hw has done the conditional check and inst decode */
1529 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1531 /* TODO: optimize to just emulate side effect w/o one more write */
1532 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1534 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1536 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1538 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1540 if (!vcpu
->arch
.apic
)
1543 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1545 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1546 static_key_slow_dec_deferred(&apic_hw_disabled
);
1548 if (!apic
->sw_enabled
)
1549 static_key_slow_dec_deferred(&apic_sw_disabled
);
1552 free_page((unsigned long)apic
->regs
);
1558 *----------------------------------------------------------------------
1560 *----------------------------------------------------------------------
1563 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1565 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1567 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1568 apic_lvtt_period(apic
))
1571 return apic
->lapic_timer
.tscdeadline
;
1574 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1576 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1578 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1579 apic_lvtt_period(apic
))
1582 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1583 apic
->lapic_timer
.tscdeadline
= data
;
1584 start_apic_timer(apic
);
1587 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1589 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1591 if (!kvm_vcpu_has_lapic(vcpu
))
1594 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1595 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1598 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1602 if (!kvm_vcpu_has_lapic(vcpu
))
1605 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1607 return (tpr
& 0xf0) >> 4;
1610 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1612 u64 old_value
= vcpu
->arch
.apic_base
;
1613 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1616 value
|= MSR_IA32_APICBASE_BSP
;
1617 vcpu
->arch
.apic_base
= value
;
1621 vcpu
->arch
.apic_base
= value
;
1623 /* update jump label if enable bit changes */
1624 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1625 if (value
& MSR_IA32_APICBASE_ENABLE
)
1626 static_key_slow_dec_deferred(&apic_hw_disabled
);
1628 static_key_slow_inc(&apic_hw_disabled
.key
);
1629 recalculate_apic_map(vcpu
->kvm
);
1632 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1633 if (value
& X2APIC_ENABLE
) {
1634 kvm_apic_set_x2apic_id(apic
, vcpu
->vcpu_id
);
1635 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1637 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1640 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1641 MSR_IA32_APICBASE_BASE
;
1643 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1644 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1645 pr_warn_once("APIC base relocation is unsupported by KVM");
1647 /* with FSB delivery interrupt, we can restart APIC functionality */
1648 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1649 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1653 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1655 struct kvm_lapic
*apic
;
1658 apic_debug("%s\n", __func__
);
1661 apic
= vcpu
->arch
.apic
;
1662 ASSERT(apic
!= NULL
);
1664 /* Stop the timer in case it's a reset to an active apic */
1665 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1668 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1669 kvm_apic_set_version(apic
->vcpu
);
1671 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1672 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1673 apic_update_lvtt(apic
);
1674 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_LINT0_REENABLED
))
1675 apic_set_reg(apic
, APIC_LVT0
,
1676 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1677 apic_manage_nmi_watchdog(apic
, kvm_apic_get_reg(apic
, APIC_LVT0
));
1679 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1680 apic_set_spiv(apic
, 0xff);
1681 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1682 if (!apic_x2apic_mode(apic
))
1683 kvm_apic_set_ldr(apic
, 0);
1684 apic_set_reg(apic
, APIC_ESR
, 0);
1685 apic_set_reg(apic
, APIC_ICR
, 0);
1686 apic_set_reg(apic
, APIC_ICR2
, 0);
1687 apic_set_reg(apic
, APIC_TDCR
, 0);
1688 apic_set_reg(apic
, APIC_TMICT
, 0);
1689 for (i
= 0; i
< 8; i
++) {
1690 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1691 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1692 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1694 apic
->irr_pending
= kvm_vcpu_apic_vid_enabled(vcpu
);
1695 apic
->isr_count
= kvm_x86_ops
->hwapic_isr_update
? 1 : 0;
1696 apic
->highest_isr_cache
= -1;
1697 update_divide_count(apic
);
1698 atomic_set(&apic
->lapic_timer
.pending
, 0);
1699 if (kvm_vcpu_is_bsp(vcpu
))
1700 kvm_lapic_set_base(vcpu
,
1701 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1702 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1703 apic_update_ppr(apic
);
1705 vcpu
->arch
.apic_arb_prio
= 0;
1706 vcpu
->arch
.apic_attention
= 0;
1708 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1709 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1710 vcpu
, kvm_apic_id(apic
),
1711 vcpu
->arch
.apic_base
, apic
->base_address
);
1715 *----------------------------------------------------------------------
1717 *----------------------------------------------------------------------
1720 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1722 return apic_lvtt_period(apic
);
1725 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1727 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1729 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1730 apic_lvt_enabled(apic
, APIC_LVTT
))
1731 return atomic_read(&apic
->lapic_timer
.pending
);
1736 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1738 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1739 int vector
, mode
, trig_mode
;
1741 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1742 vector
= reg
& APIC_VECTOR_MASK
;
1743 mode
= reg
& APIC_MODE_MASK
;
1744 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1745 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1751 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1753 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1756 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1759 static const struct kvm_io_device_ops apic_mmio_ops
= {
1760 .read
= apic_mmio_read
,
1761 .write
= apic_mmio_write
,
1764 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1766 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1767 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1769 apic_timer_expired(apic
);
1771 if (lapic_is_periodic(apic
)) {
1772 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1773 return HRTIMER_RESTART
;
1775 return HRTIMER_NORESTART
;
1778 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1780 struct kvm_lapic
*apic
;
1782 ASSERT(vcpu
!= NULL
);
1783 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1785 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1789 vcpu
->arch
.apic
= apic
;
1791 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1793 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1795 goto nomem_free_apic
;
1799 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1801 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1804 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1805 * thinking that APIC satet has changed.
1807 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1808 kvm_lapic_set_base(vcpu
,
1809 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1811 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1812 kvm_lapic_reset(vcpu
, false);
1813 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1822 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1824 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1827 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1830 apic_update_ppr(apic
);
1831 highest_irr
= apic_find_highest_irr(apic
);
1832 if ((highest_irr
== -1) ||
1833 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1838 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1840 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1843 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1845 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1846 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1851 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1853 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1855 if (!kvm_vcpu_has_lapic(vcpu
))
1858 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1859 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1860 if (apic_lvtt_tscdeadline(apic
))
1861 apic
->lapic_timer
.tscdeadline
= 0;
1862 atomic_set(&apic
->lapic_timer
.pending
, 0);
1866 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1868 int vector
= kvm_apic_has_interrupt(vcpu
);
1869 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1875 * We get here even with APIC virtualization enabled, if doing
1876 * nested virtualization and L1 runs with the "acknowledge interrupt
1877 * on exit" mode. Then we cannot inject the interrupt via RVI,
1878 * because the process would deliver it through the IDT.
1881 apic_set_isr(vector
, apic
);
1882 apic_update_ppr(apic
);
1883 apic_clear_irr(vector
, apic
);
1887 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1888 struct kvm_lapic_state
*s
)
1890 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1892 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1893 /* set SPIV separately to get count of SW disabled APICs right */
1894 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1895 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1896 /* call kvm_apic_set_id() to put apic into apic_map */
1897 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1898 kvm_apic_set_version(vcpu
);
1900 apic_update_ppr(apic
);
1901 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1902 apic_update_lvtt(apic
);
1903 apic_manage_nmi_watchdog(apic
, kvm_apic_get_reg(apic
, APIC_LVT0
));
1904 update_divide_count(apic
);
1905 start_apic_timer(apic
);
1906 apic
->irr_pending
= true;
1907 apic
->isr_count
= kvm_x86_ops
->hwapic_isr_update
?
1908 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1909 apic
->highest_isr_cache
= -1;
1910 if (kvm_x86_ops
->hwapic_irr_update
)
1911 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1912 apic_find_highest_irr(apic
));
1913 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
1914 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
1915 apic_find_highest_isr(apic
));
1916 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1917 if (ioapic_in_kernel(vcpu
->kvm
))
1918 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1921 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1923 struct hrtimer
*timer
;
1925 if (!kvm_vcpu_has_lapic(vcpu
))
1928 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1929 if (hrtimer_cancel(timer
))
1930 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1934 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1936 * Detect whether guest triggered PV EOI since the
1937 * last entry. If yes, set EOI on guests's behalf.
1938 * Clear PV EOI in guest memory in any case.
1940 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1941 struct kvm_lapic
*apic
)
1946 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1947 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1949 * KVM_APIC_PV_EOI_PENDING is unset:
1950 * -> host disabled PV EOI.
1951 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1952 * -> host enabled PV EOI, guest did not execute EOI yet.
1953 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1954 * -> host enabled PV EOI, guest executed EOI.
1956 BUG_ON(!pv_eoi_enabled(vcpu
));
1957 pending
= pv_eoi_get_pending(vcpu
);
1959 * Clear pending bit in any case: it will be set again on vmentry.
1960 * While this might not be ideal from performance point of view,
1961 * this makes sure pv eoi is only enabled when we know it's safe.
1963 pv_eoi_clr_pending(vcpu
);
1966 vector
= apic_set_eoi(apic
);
1967 trace_kvm_pv_eoi(apic
, vector
);
1970 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1974 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1975 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1977 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1980 if (kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1984 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1988 * apic_sync_pv_eoi_to_guest - called before vmentry
1990 * Detect whether it's safe to enable PV EOI and
1993 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1994 struct kvm_lapic
*apic
)
1996 if (!pv_eoi_enabled(vcpu
) ||
1997 /* IRR set or many bits in ISR: could be nested. */
1998 apic
->irr_pending
||
1999 /* Cache not set: could be safe but we don't bother. */
2000 apic
->highest_isr_cache
== -1 ||
2001 /* Need EOI to update ioapic. */
2002 kvm_ioapic_handles_vector(apic
, apic
->highest_isr_cache
)) {
2004 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2005 * so we need not do anything here.
2010 pv_eoi_set_pending(apic
->vcpu
);
2013 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
2016 int max_irr
, max_isr
;
2017 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2019 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
2021 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2024 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
2025 max_irr
= apic_find_highest_irr(apic
);
2028 max_isr
= apic_find_highest_isr(apic
);
2031 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
2033 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2037 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
2040 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
2041 &vcpu
->arch
.apic
->vapic_cache
,
2042 vapic_addr
, sizeof(u32
)))
2044 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2046 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2049 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
2053 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
2055 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2056 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
2058 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2061 if (reg
== APIC_ICR2
)
2064 /* if this is ICR write vector before command */
2065 if (reg
== APIC_ICR
)
2066 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2067 return apic_reg_write(apic
, reg
, (u32
)data
);
2070 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
2072 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2073 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
2075 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2078 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
2079 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2084 if (apic_reg_read(apic
, reg
, 4, &low
))
2086 if (reg
== APIC_ICR
)
2087 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2089 *data
= (((u64
)high
) << 32) | low
;
2094 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
2096 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2098 if (!kvm_vcpu_has_lapic(vcpu
))
2101 /* if this is ICR write vector before command */
2102 if (reg
== APIC_ICR
)
2103 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2104 return apic_reg_write(apic
, reg
, (u32
)data
);
2107 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2109 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2112 if (!kvm_vcpu_has_lapic(vcpu
))
2115 if (apic_reg_read(apic
, reg
, 4, &low
))
2117 if (reg
== APIC_ICR
)
2118 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2120 *data
= (((u64
)high
) << 32) | low
;
2125 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
2127 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2128 if (!IS_ALIGNED(addr
, 4))
2131 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2132 if (!pv_eoi_enabled(vcpu
))
2134 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2138 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2140 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2144 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
2148 * INITs are latched while in SMM. Because an SMM CPU cannot
2149 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2150 * and delay processing of INIT until the next RSM.
2153 WARN_ON_ONCE(vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
);
2154 if (test_bit(KVM_APIC_SIPI
, &apic
->pending_events
))
2155 clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
2159 pe
= xchg(&apic
->pending_events
, 0);
2160 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2161 kvm_lapic_reset(vcpu
, true);
2162 kvm_vcpu_reset(vcpu
, true);
2163 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2164 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2166 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2168 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2169 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2170 /* evaluate pending_events before reading the vector */
2172 sipi_vector
= apic
->sipi_vector
;
2173 apic_debug("vcpu %d received sipi with vector # %x\n",
2174 vcpu
->vcpu_id
, sipi_vector
);
2175 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2176 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2180 void kvm_lapic_init(void)
2182 /* do not patch jump label more than once per second */
2183 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2184 jump_label_rate_limit(&apic_sw_disabled
, HZ
);