3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
80 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
83 static inline int apic_test_vector(int vec
, void *bitmap
)
85 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
90 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
92 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
93 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
96 static inline void apic_set_vector(int vec
, void *bitmap
)
98 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
101 static inline void apic_clear_vector(int vec
, void *bitmap
)
103 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
106 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
108 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
111 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
113 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
116 struct static_key_deferred apic_hw_disabled __read_mostly
;
117 struct static_key_deferred apic_sw_disabled __read_mostly
;
119 static inline int apic_enabled(struct kvm_lapic
*apic
)
121 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
133 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map
*map
)
141 return !(map
->mode
& (map
->mode
- 1));
145 apic_logical_id(struct kvm_apic_map
*map
, u32 dest_id
, u16
*cid
, u16
*lid
)
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER
!= 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT
!= 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC
!= 16);
152 lid_bits
= map
->mode
;
154 *cid
= dest_id
>> lid_bits
;
155 *lid
= dest_id
& ((1 << lid_bits
) - 1);
158 static void recalculate_apic_map(struct kvm
*kvm
)
160 struct kvm_apic_map
*new, *old
= NULL
;
161 struct kvm_vcpu
*vcpu
;
164 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
166 mutex_lock(&kvm
->arch
.apic_map_lock
);
171 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
172 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
176 if (!kvm_apic_present(vcpu
))
179 aid
= kvm_apic_id(apic
);
180 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
182 if (aid
< ARRAY_SIZE(new->phys_map
))
183 new->phys_map
[aid
] = apic
;
185 if (apic_x2apic_mode(apic
)) {
186 new->mode
|= KVM_APIC_MODE_X2APIC
;
188 ldr
= GET_APIC_LOGICAL_ID(ldr
);
189 if (kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
190 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
192 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
195 if (!kvm_apic_logical_map_valid(new))
198 apic_logical_id(new, ldr
, &cid
, &lid
);
200 if (lid
&& cid
< ARRAY_SIZE(new->logical_map
))
201 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
204 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
205 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
206 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
207 mutex_unlock(&kvm
->arch
.apic_map_lock
);
212 kvm_vcpu_request_scan_ioapic(kvm
);
215 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
217 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
219 apic_set_reg(apic
, APIC_SPIV
, val
);
221 if (enabled
!= apic
->sw_enabled
) {
222 apic
->sw_enabled
= enabled
;
224 static_key_slow_dec_deferred(&apic_sw_disabled
);
225 recalculate_apic_map(apic
->vcpu
->kvm
);
227 static_key_slow_inc(&apic_sw_disabled
.key
);
231 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
233 apic_set_reg(apic
, APIC_ID
, id
<< 24);
234 recalculate_apic_map(apic
->vcpu
->kvm
);
237 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
239 apic_set_reg(apic
, APIC_LDR
, id
);
240 recalculate_apic_map(apic
->vcpu
->kvm
);
243 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
245 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
248 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
250 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
253 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
255 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
258 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
260 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
263 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
265 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
268 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
270 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
273 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
275 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
276 struct kvm_cpuid_entry2
*feat
;
277 u32 v
= APIC_VERSION
;
279 if (!kvm_vcpu_has_lapic(vcpu
))
282 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
283 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
284 v
|= APIC_LVR_DIRECTED_EOI
;
285 apic_set_reg(apic
, APIC_LVR
, v
);
288 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
289 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
290 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
291 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
292 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
293 LVT_MASK
/* LVTERR */
296 static int find_highest_vector(void *bitmap
)
301 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
302 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
303 reg
= bitmap
+ REG_POS(vec
);
305 return fls(*reg
) - 1 + vec
;
311 static u8
count_vectors(void *bitmap
)
317 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
318 reg
= bitmap
+ REG_POS(vec
);
319 count
+= hweight32(*reg
);
325 void __kvm_apic_update_irr(u32
*pir
, void *regs
)
329 for (i
= 0; i
<= 7; i
++) {
330 pir_val
= xchg(&pir
[i
], 0);
332 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
335 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
337 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
339 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
341 __kvm_apic_update_irr(pir
, apic
->regs
);
343 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
345 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
347 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
349 * irr_pending must be true if any interrupt is pending; set it after
350 * APIC_IRR to avoid race with apic_clear_irr
352 apic
->irr_pending
= true;
355 static inline int apic_search_irr(struct kvm_lapic
*apic
)
357 return find_highest_vector(apic
->regs
+ APIC_IRR
);
360 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
365 * Note that irr_pending is just a hint. It will be always
366 * true with virtual interrupt delivery enabled.
368 if (!apic
->irr_pending
)
371 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
372 result
= apic_search_irr(apic
);
373 ASSERT(result
== -1 || result
>= 16);
378 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
380 struct kvm_vcpu
*vcpu
;
384 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
))) {
385 /* try to update RVI */
386 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
387 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
389 apic
->irr_pending
= false;
390 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
391 if (apic_search_irr(apic
) != -1)
392 apic
->irr_pending
= true;
396 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
398 struct kvm_vcpu
*vcpu
;
400 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
406 * With APIC virtualization enabled, all caching is disabled
407 * because the processor can modify ISR under the hood. Instead
410 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
411 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
414 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
416 * ISR (in service register) bit is set when injecting an interrupt.
417 * The highest vector is injected. Thus the latest bit set matches
418 * the highest bit in ISR.
420 apic
->highest_isr_cache
= vec
;
424 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
429 * Note that isr_count is always 1, and highest_isr_cache
430 * is always -1, with APIC virtualization enabled.
432 if (!apic
->isr_count
)
434 if (likely(apic
->highest_isr_cache
!= -1))
435 return apic
->highest_isr_cache
;
437 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
438 ASSERT(result
== -1 || result
>= 16);
443 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
445 struct kvm_vcpu
*vcpu
;
446 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
452 * We do get here for APIC virtualization enabled if the guest
453 * uses the Hyper-V APIC enlightenment. In this case we may need
454 * to trigger a new interrupt delivery by writing the SVI field;
455 * on the other hand isr_count and highest_isr_cache are unused
456 * and must be left alone.
458 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
459 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
460 apic_find_highest_isr(apic
));
463 BUG_ON(apic
->isr_count
< 0);
464 apic
->highest_isr_cache
= -1;
468 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
472 /* This may race with setting of irr in __apic_accept_irq() and
473 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
474 * will cause vmexit immediately and the value will be recalculated
475 * on the next vmentry.
477 if (!kvm_vcpu_has_lapic(vcpu
))
479 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
484 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
485 int vector
, int level
, int trig_mode
,
486 unsigned long *dest_map
);
488 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
489 unsigned long *dest_map
)
491 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
493 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
494 irq
->level
, irq
->trig_mode
, dest_map
);
497 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
500 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
504 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
507 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
511 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
513 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
516 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
519 if (pv_eoi_get_user(vcpu
, &val
) < 0)
520 apic_debug("Can't read EOI MSR value: 0x%llx\n",
521 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
525 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
527 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
528 apic_debug("Can't set EOI MSR value: 0x%llx\n",
529 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
532 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
535 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
537 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
538 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
539 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
542 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
545 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
547 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
550 for (i
= 0; i
< 8; i
++)
551 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
554 static void apic_update_ppr(struct kvm_lapic
*apic
)
556 u32 tpr
, isrv
, ppr
, old_ppr
;
559 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
560 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
561 isr
= apic_find_highest_isr(apic
);
562 isrv
= (isr
!= -1) ? isr
: 0;
564 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic
, ppr
, isr
, isrv
);
572 if (old_ppr
!= ppr
) {
573 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
575 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
579 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
581 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
582 apic_update_ppr(apic
);
585 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
587 if (apic_x2apic_mode(apic
))
588 return mda
== X2APIC_BROADCAST
;
590 return GET_APIC_DEST_FIELD(mda
) == APIC_BROADCAST
;
593 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
595 if (kvm_apic_broadcast(apic
, mda
))
598 if (apic_x2apic_mode(apic
))
599 return mda
== kvm_apic_id(apic
);
601 return mda
== SET_APIC_DEST_FIELD(kvm_apic_id(apic
));
604 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
608 if (kvm_apic_broadcast(apic
, mda
))
611 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
613 if (apic_x2apic_mode(apic
))
614 return ((logical_id
>> 16) == (mda
>> 16))
615 && (logical_id
& mda
& 0xffff) != 0;
617 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
618 mda
= GET_APIC_DEST_FIELD(mda
);
620 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
622 return (logical_id
& mda
) != 0;
623 case APIC_DFR_CLUSTER
:
624 return ((logical_id
>> 4) == (mda
>> 4))
625 && (logical_id
& mda
& 0xf) != 0;
627 apic_debug("Bad DFR vcpu %d: %08x\n",
628 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
633 /* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
637 static u32
kvm_apic_mda(unsigned int dest_id
, struct kvm_lapic
*source
,
638 struct kvm_lapic
*target
)
640 bool ipi
= source
!= NULL
;
641 bool x2apic_mda
= apic_x2apic_mode(ipi
? source
: target
);
643 if (!ipi
&& dest_id
== APIC_BROADCAST
&& x2apic_mda
)
644 return X2APIC_BROADCAST
;
646 return x2apic_mda
? dest_id
: SET_APIC_DEST_FIELD(dest_id
);
649 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
650 int short_hand
, unsigned int dest
, int dest_mode
)
652 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
653 u32 mda
= kvm_apic_mda(dest
, source
, target
);
655 apic_debug("target %p, source %p, dest 0x%x, "
656 "dest_mode 0x%x, short_hand 0x%x\n",
657 target
, source
, dest
, dest_mode
, short_hand
);
660 switch (short_hand
) {
661 case APIC_DEST_NOSHORT
:
662 if (dest_mode
== APIC_DEST_PHYSICAL
)
663 return kvm_apic_match_physical_addr(target
, mda
);
665 return kvm_apic_match_logical_addr(target
, mda
);
667 return target
== source
;
668 case APIC_DEST_ALLINC
:
670 case APIC_DEST_ALLBUT
:
671 return target
!= source
;
673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
679 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
680 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
682 struct kvm_apic_map
*map
;
683 unsigned long bitmap
= 1;
684 struct kvm_lapic
**dst
;
686 bool ret
, x2apic_ipi
;
690 if (irq
->shorthand
== APIC_DEST_SELF
) {
691 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
698 x2apic_ipi
= src
&& apic_x2apic_mode(src
);
699 if (irq
->dest_id
== (x2apic_ipi
? X2APIC_BROADCAST
: APIC_BROADCAST
))
704 map
= rcu_dereference(kvm
->arch
.apic_map
);
711 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
712 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
715 dst
= &map
->phys_map
[irq
->dest_id
];
719 if (!kvm_apic_logical_map_valid(map
)) {
724 apic_logical_id(map
, irq
->dest_id
, &cid
, (u16
*)&bitmap
);
726 if (cid
>= ARRAY_SIZE(map
->logical_map
))
729 dst
= map
->logical_map
[cid
];
731 if (kvm_lowest_prio_delivery(irq
)) {
733 for_each_set_bit(i
, &bitmap
, 16) {
738 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
742 bitmap
= (l
>= 0) ? 1 << l
: 0;
746 for_each_set_bit(i
, &bitmap
, 16) {
751 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
759 * Add a pending IRQ into lapic.
760 * Return 1 if successfully added and 0 if discarded.
762 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
763 int vector
, int level
, int trig_mode
,
764 unsigned long *dest_map
)
767 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
769 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
771 switch (delivery_mode
) {
773 vcpu
->arch
.apic_arb_prio
++;
775 /* FIXME add logic for vcpu on reset */
776 if (unlikely(!apic_enabled(apic
)))
782 __set_bit(vcpu
->vcpu_id
, dest_map
);
784 if (kvm_x86_ops
->deliver_posted_interrupt
)
785 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
787 apic_set_irr(vector
, apic
);
789 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
796 vcpu
->arch
.pv
.pv_unhalted
= 1;
797 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
802 apic_debug("Ignoring guest SMI\n");
807 kvm_inject_nmi(vcpu
);
812 if (!trig_mode
|| level
) {
814 /* assumes that there are only KVM_APIC_INIT/SIPI */
815 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
816 /* make sure pending_events is visible before sending
819 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
822 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
827 case APIC_DM_STARTUP
:
828 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
829 vcpu
->vcpu_id
, vector
);
831 apic
->sipi_vector
= vector
;
832 /* make sure sipi_vector is visible for the receiver */
834 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
835 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
841 * Should only be called by kvm_apic_local_deliver() with LVT0,
842 * before NMI watchdog was enabled. Already handled by
843 * kvm_apic_accept_pic_intr().
848 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
855 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
857 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
860 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
862 if (kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
864 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
865 trigger_mode
= IOAPIC_LEVEL_TRIG
;
867 trigger_mode
= IOAPIC_EDGE_TRIG
;
868 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
872 static int apic_set_eoi(struct kvm_lapic
*apic
)
874 int vector
= apic_find_highest_isr(apic
);
876 trace_kvm_eoi(apic
, vector
);
879 * Not every write EOI will has corresponding ISR,
880 * one example is when Kernel check timer on setup_IO_APIC
885 apic_clear_isr(vector
, apic
);
886 apic_update_ppr(apic
);
888 kvm_ioapic_send_eoi(apic
, vector
);
889 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
894 * this interface assumes a trap-like exit, which has already finished
895 * desired side effect including vISR and vPPR update.
897 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
899 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
901 trace_kvm_eoi(apic
, vector
);
903 kvm_ioapic_send_eoi(apic
, vector
);
904 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
906 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
908 static void apic_send_ipi(struct kvm_lapic
*apic
)
910 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
911 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
912 struct kvm_lapic_irq irq
;
914 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
915 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
916 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
917 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
918 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
919 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
920 irq
.msi_redir_hint
= false;
921 if (apic_x2apic_mode(apic
))
922 irq
.dest_id
= icr_high
;
924 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
926 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
928 apic_debug("icr_high 0x%x, icr_low 0x%x, "
929 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
930 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
931 "msi_redir_hint 0x%x\n",
932 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
933 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
934 irq
.vector
, irq
.msi_redir_hint
);
936 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
939 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
945 ASSERT(apic
!= NULL
);
947 /* if initial count is 0, current count should also be 0 */
948 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
949 apic
->lapic_timer
.period
== 0)
952 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
953 if (ktime_to_ns(remaining
) < 0)
954 remaining
= ktime_set(0, 0);
956 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
957 tmcct
= div64_u64(ns
,
958 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
963 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
965 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
966 struct kvm_run
*run
= vcpu
->run
;
968 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
969 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
970 run
->tpr_access
.is_write
= write
;
973 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
975 if (apic
->vcpu
->arch
.tpr_access_reporting
)
976 __report_tpr_access(apic
, write
);
979 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
983 if (offset
>= LAPIC_MMIO_LENGTH
)
988 if (apic_x2apic_mode(apic
))
989 val
= kvm_apic_id(apic
);
991 val
= kvm_apic_id(apic
) << 24;
994 apic_debug("Access APIC ARBPRI register which is for P6\n");
997 case APIC_TMCCT
: /* Timer CCR */
998 if (apic_lvtt_tscdeadline(apic
))
1001 val
= apic_get_tmcct(apic
);
1004 apic_update_ppr(apic
);
1005 val
= kvm_apic_get_reg(apic
, offset
);
1008 report_tpr_access(apic
, false);
1011 val
= kvm_apic_get_reg(apic
, offset
);
1018 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1020 return container_of(dev
, struct kvm_lapic
, dev
);
1023 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1026 unsigned char alignment
= offset
& 0xf;
1028 /* this bitmask has a bit cleared for each reserved register */
1029 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1031 if ((alignment
+ len
) > 4) {
1032 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1037 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1038 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1043 result
= __apic_read(apic
, offset
& ~0xf);
1045 trace_kvm_apic_read(offset
, result
);
1051 memcpy(data
, (char *)&result
+ alignment
, len
);
1054 printk(KERN_ERR
"Local APIC read with len = %x, "
1055 "should be 1,2, or 4 instead\n", len
);
1061 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1063 return kvm_apic_hw_enabled(apic
) &&
1064 addr
>= apic
->base_address
&&
1065 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1068 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1069 gpa_t address
, int len
, void *data
)
1071 struct kvm_lapic
*apic
= to_lapic(this);
1072 u32 offset
= address
- apic
->base_address
;
1074 if (!apic_mmio_in_range(apic
, address
))
1077 apic_reg_read(apic
, offset
, len
, data
);
1082 static void update_divide_count(struct kvm_lapic
*apic
)
1084 u32 tmp1
, tmp2
, tdcr
;
1086 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1088 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1089 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1091 apic_debug("timer divide count is 0x%x\n",
1092 apic
->divide_count
);
1095 static void apic_timer_expired(struct kvm_lapic
*apic
)
1097 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1098 wait_queue_head_t
*q
= &vcpu
->wq
;
1099 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1101 if (atomic_read(&apic
->lapic_timer
.pending
))
1104 atomic_inc(&apic
->lapic_timer
.pending
);
1105 kvm_set_pending_timer(vcpu
);
1107 if (waitqueue_active(q
))
1108 wake_up_interruptible(q
);
1110 if (apic_lvtt_tscdeadline(apic
))
1111 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1115 * On APICv, this test will cause a busy wait
1116 * during a higher-priority task.
1119 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1121 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1122 u32 reg
= kvm_apic_get_reg(apic
, APIC_LVTT
);
1124 if (kvm_apic_hw_enabled(apic
)) {
1125 int vec
= reg
& APIC_VECTOR_MASK
;
1126 void *bitmap
= apic
->regs
+ APIC_ISR
;
1128 if (kvm_x86_ops
->deliver_posted_interrupt
)
1129 bitmap
= apic
->regs
+ APIC_IRR
;
1131 if (apic_test_vector(vec
, bitmap
))
1137 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1139 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1140 u64 guest_tsc
, tsc_deadline
;
1142 if (!kvm_vcpu_has_lapic(vcpu
))
1145 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1148 if (!lapic_timer_int_injected(vcpu
))
1151 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1152 apic
->lapic_timer
.expired_tscdeadline
= 0;
1153 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1154 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1156 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1157 if (guest_tsc
< tsc_deadline
)
1158 __delay(tsc_deadline
- guest_tsc
);
1161 static void start_apic_timer(struct kvm_lapic
*apic
)
1165 atomic_set(&apic
->lapic_timer
.pending
, 0);
1167 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1168 /* lapic timer in oneshot or periodic mode */
1169 now
= apic
->lapic_timer
.timer
.base
->get_time();
1170 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1171 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1173 if (!apic
->lapic_timer
.period
)
1176 * Do not allow the guest to program periodic timers with small
1177 * interval, since the hrtimers are not throttled by the host
1180 if (apic_lvtt_period(apic
)) {
1181 s64 min_period
= min_timer_period_us
* 1000LL;
1183 if (apic
->lapic_timer
.period
< min_period
) {
1184 pr_info_ratelimited(
1185 "kvm: vcpu %i: requested %lld ns "
1186 "lapic timer period limited to %lld ns\n",
1187 apic
->vcpu
->vcpu_id
,
1188 apic
->lapic_timer
.period
, min_period
);
1189 apic
->lapic_timer
.period
= min_period
;
1193 hrtimer_start(&apic
->lapic_timer
.timer
,
1194 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1197 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1199 "timer initial count 0x%x, period %lldns, "
1200 "expire @ 0x%016" PRIx64
".\n", __func__
,
1201 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1202 kvm_apic_get_reg(apic
, APIC_TMICT
),
1203 apic
->lapic_timer
.period
,
1204 ktime_to_ns(ktime_add_ns(now
,
1205 apic
->lapic_timer
.period
)));
1206 } else if (apic_lvtt_tscdeadline(apic
)) {
1207 /* lapic timer in tsc deadline mode */
1208 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1211 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1212 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1213 unsigned long flags
;
1215 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1218 local_irq_save(flags
);
1220 now
= apic
->lapic_timer
.timer
.base
->get_time();
1221 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1222 if (likely(tscdeadline
> guest_tsc
)) {
1223 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1224 do_div(ns
, this_tsc_khz
);
1225 expire
= ktime_add_ns(now
, ns
);
1226 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1227 hrtimer_start(&apic
->lapic_timer
.timer
,
1228 expire
, HRTIMER_MODE_ABS
);
1230 apic_timer_expired(apic
);
1232 local_irq_restore(flags
);
1236 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1238 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1240 if (apic_lvt_nmi_mode(lvt0_val
)) {
1241 if (!nmi_wd_enabled
) {
1242 apic_debug("Receive NMI setting on APIC_LVT0 "
1243 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1244 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1246 } else if (nmi_wd_enabled
)
1247 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1250 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1254 trace_kvm_apic_write(reg
, val
);
1257 case APIC_ID
: /* Local APIC ID */
1258 if (!apic_x2apic_mode(apic
))
1259 kvm_apic_set_id(apic
, val
>> 24);
1265 report_tpr_access(apic
, true);
1266 apic_set_tpr(apic
, val
& 0xff);
1274 if (!apic_x2apic_mode(apic
))
1275 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1281 if (!apic_x2apic_mode(apic
)) {
1282 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1283 recalculate_apic_map(apic
->vcpu
->kvm
);
1290 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1291 mask
|= APIC_SPIV_DIRECTED_EOI
;
1292 apic_set_spiv(apic
, val
& mask
);
1293 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1297 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1298 lvt_val
= kvm_apic_get_reg(apic
,
1299 APIC_LVTT
+ 0x10 * i
);
1300 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1301 lvt_val
| APIC_LVT_MASKED
);
1303 atomic_set(&apic
->lapic_timer
.pending
, 0);
1309 /* No delay here, so we always clear the pending bit */
1310 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1311 apic_send_ipi(apic
);
1315 if (!apic_x2apic_mode(apic
))
1317 apic_set_reg(apic
, APIC_ICR2
, val
);
1321 apic_manage_nmi_watchdog(apic
, val
);
1326 /* TODO: Check vector */
1327 if (!kvm_apic_sw_enabled(apic
))
1328 val
|= APIC_LVT_MASKED
;
1330 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1331 apic_set_reg(apic
, reg
, val
);
1336 u32 timer_mode
= val
& apic
->lapic_timer
.timer_mode_mask
;
1338 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1339 apic
->lapic_timer
.timer_mode
= timer_mode
;
1340 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1343 if (!kvm_apic_sw_enabled(apic
))
1344 val
|= APIC_LVT_MASKED
;
1345 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1346 apic_set_reg(apic
, APIC_LVTT
, val
);
1351 if (apic_lvtt_tscdeadline(apic
))
1354 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1355 apic_set_reg(apic
, APIC_TMICT
, val
);
1356 start_apic_timer(apic
);
1361 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1362 apic_set_reg(apic
, APIC_TDCR
, val
);
1363 update_divide_count(apic
);
1367 if (apic_x2apic_mode(apic
) && val
!= 0) {
1368 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1374 if (apic_x2apic_mode(apic
)) {
1375 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1384 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1388 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1389 gpa_t address
, int len
, const void *data
)
1391 struct kvm_lapic
*apic
= to_lapic(this);
1392 unsigned int offset
= address
- apic
->base_address
;
1395 if (!apic_mmio_in_range(apic
, address
))
1399 * APIC register must be aligned on 128-bits boundary.
1400 * 32/64/128 bits registers must be accessed thru 32 bits.
1403 if (len
!= 4 || (offset
& 0xf)) {
1404 /* Don't shout loud, $infamous_os would cause only noise. */
1405 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1411 /* too common printing */
1412 if (offset
!= APIC_EOI
)
1413 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1414 "0x%x\n", __func__
, offset
, len
, val
);
1416 apic_reg_write(apic
, offset
& 0xff0, val
);
1421 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1423 if (kvm_vcpu_has_lapic(vcpu
))
1424 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1426 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1428 /* emulate APIC access in a trap manner */
1429 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1433 /* hw has done the conditional check and inst decode */
1436 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1438 /* TODO: optimize to just emulate side effect w/o one more write */
1439 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1441 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1443 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1445 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1447 if (!vcpu
->arch
.apic
)
1450 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1452 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1453 static_key_slow_dec_deferred(&apic_hw_disabled
);
1455 if (!apic
->sw_enabled
)
1456 static_key_slow_dec_deferred(&apic_sw_disabled
);
1459 free_page((unsigned long)apic
->regs
);
1465 *----------------------------------------------------------------------
1467 *----------------------------------------------------------------------
1470 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1472 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1474 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1475 apic_lvtt_period(apic
))
1478 return apic
->lapic_timer
.tscdeadline
;
1481 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1483 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1485 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1486 apic_lvtt_period(apic
))
1489 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1490 apic
->lapic_timer
.tscdeadline
= data
;
1491 start_apic_timer(apic
);
1494 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1496 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1498 if (!kvm_vcpu_has_lapic(vcpu
))
1501 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1502 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1505 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1509 if (!kvm_vcpu_has_lapic(vcpu
))
1512 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1514 return (tpr
& 0xf0) >> 4;
1517 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1519 u64 old_value
= vcpu
->arch
.apic_base
;
1520 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1523 value
|= MSR_IA32_APICBASE_BSP
;
1524 vcpu
->arch
.apic_base
= value
;
1528 vcpu
->arch
.apic_base
= value
;
1530 /* update jump label if enable bit changes */
1531 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1532 if (value
& MSR_IA32_APICBASE_ENABLE
)
1533 static_key_slow_dec_deferred(&apic_hw_disabled
);
1535 static_key_slow_inc(&apic_hw_disabled
.key
);
1536 recalculate_apic_map(vcpu
->kvm
);
1539 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1540 if (value
& X2APIC_ENABLE
) {
1541 u32 id
= kvm_apic_id(apic
);
1542 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1543 kvm_apic_set_ldr(apic
, ldr
);
1544 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1546 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1549 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1550 MSR_IA32_APICBASE_BASE
;
1552 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1553 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1554 pr_warn_once("APIC base relocation is unsupported by KVM");
1556 /* with FSB delivery interrupt, we can restart APIC functionality */
1557 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1558 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1562 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1564 struct kvm_lapic
*apic
;
1567 apic_debug("%s\n", __func__
);
1570 apic
= vcpu
->arch
.apic
;
1571 ASSERT(apic
!= NULL
);
1573 /* Stop the timer in case it's a reset to an active apic */
1574 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1577 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1578 kvm_apic_set_version(apic
->vcpu
);
1580 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1581 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1582 apic
->lapic_timer
.timer_mode
= 0;
1583 if (!(vcpu
->kvm
->arch
.disabled_quirks
& KVM_QUIRK_LINT0_REENABLED
))
1584 apic_set_reg(apic
, APIC_LVT0
,
1585 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1587 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1588 apic_set_spiv(apic
, 0xff);
1589 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1590 kvm_apic_set_ldr(apic
, 0);
1591 apic_set_reg(apic
, APIC_ESR
, 0);
1592 apic_set_reg(apic
, APIC_ICR
, 0);
1593 apic_set_reg(apic
, APIC_ICR2
, 0);
1594 apic_set_reg(apic
, APIC_TDCR
, 0);
1595 apic_set_reg(apic
, APIC_TMICT
, 0);
1596 for (i
= 0; i
< 8; i
++) {
1597 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1598 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1599 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1601 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1602 apic
->isr_count
= kvm_x86_ops
->hwapic_isr_update
? 1 : 0;
1603 apic
->highest_isr_cache
= -1;
1604 update_divide_count(apic
);
1605 atomic_set(&apic
->lapic_timer
.pending
, 0);
1606 if (kvm_vcpu_is_bsp(vcpu
))
1607 kvm_lapic_set_base(vcpu
,
1608 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1609 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1610 apic_update_ppr(apic
);
1612 vcpu
->arch
.apic_arb_prio
= 0;
1613 vcpu
->arch
.apic_attention
= 0;
1615 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1616 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1617 vcpu
, kvm_apic_id(apic
),
1618 vcpu
->arch
.apic_base
, apic
->base_address
);
1622 *----------------------------------------------------------------------
1624 *----------------------------------------------------------------------
1627 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1629 return apic_lvtt_period(apic
);
1632 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1634 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1636 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1637 apic_lvt_enabled(apic
, APIC_LVTT
))
1638 return atomic_read(&apic
->lapic_timer
.pending
);
1643 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1645 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1646 int vector
, mode
, trig_mode
;
1648 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1649 vector
= reg
& APIC_VECTOR_MASK
;
1650 mode
= reg
& APIC_MODE_MASK
;
1651 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1652 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1658 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1660 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1663 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1666 static const struct kvm_io_device_ops apic_mmio_ops
= {
1667 .read
= apic_mmio_read
,
1668 .write
= apic_mmio_write
,
1671 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1673 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1674 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1676 apic_timer_expired(apic
);
1678 if (lapic_is_periodic(apic
)) {
1679 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1680 return HRTIMER_RESTART
;
1682 return HRTIMER_NORESTART
;
1685 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1687 struct kvm_lapic
*apic
;
1689 ASSERT(vcpu
!= NULL
);
1690 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1692 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1696 vcpu
->arch
.apic
= apic
;
1698 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1700 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1702 goto nomem_free_apic
;
1706 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1708 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1711 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1712 * thinking that APIC satet has changed.
1714 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1715 kvm_lapic_set_base(vcpu
,
1716 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1718 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1719 kvm_lapic_reset(vcpu
, false);
1720 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1729 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1731 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1734 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1737 apic_update_ppr(apic
);
1738 highest_irr
= apic_find_highest_irr(apic
);
1739 if ((highest_irr
== -1) ||
1740 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1745 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1747 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1750 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1752 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1753 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1758 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1760 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1762 if (!kvm_vcpu_has_lapic(vcpu
))
1765 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1766 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1767 if (apic_lvtt_tscdeadline(apic
))
1768 apic
->lapic_timer
.tscdeadline
= 0;
1769 atomic_set(&apic
->lapic_timer
.pending
, 0);
1773 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1775 int vector
= kvm_apic_has_interrupt(vcpu
);
1776 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1782 * We get here even with APIC virtualization enabled, if doing
1783 * nested virtualization and L1 runs with the "acknowledge interrupt
1784 * on exit" mode. Then we cannot inject the interrupt via RVI,
1785 * because the process would deliver it through the IDT.
1788 apic_set_isr(vector
, apic
);
1789 apic_update_ppr(apic
);
1790 apic_clear_irr(vector
, apic
);
1794 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1795 struct kvm_lapic_state
*s
)
1797 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1799 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1800 /* set SPIV separately to get count of SW disabled APICs right */
1801 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1802 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1803 /* call kvm_apic_set_id() to put apic into apic_map */
1804 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1805 kvm_apic_set_version(vcpu
);
1807 apic_update_ppr(apic
);
1808 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1809 update_divide_count(apic
);
1810 start_apic_timer(apic
);
1811 apic
->irr_pending
= true;
1812 apic
->isr_count
= kvm_x86_ops
->hwapic_isr_update
?
1813 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1814 apic
->highest_isr_cache
= -1;
1815 if (kvm_x86_ops
->hwapic_irr_update
)
1816 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1817 apic_find_highest_irr(apic
));
1818 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
1819 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
1820 apic_find_highest_isr(apic
));
1821 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1822 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1825 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1827 struct hrtimer
*timer
;
1829 if (!kvm_vcpu_has_lapic(vcpu
))
1832 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1833 if (hrtimer_cancel(timer
))
1834 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1838 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1840 * Detect whether guest triggered PV EOI since the
1841 * last entry. If yes, set EOI on guests's behalf.
1842 * Clear PV EOI in guest memory in any case.
1844 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1845 struct kvm_lapic
*apic
)
1850 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1851 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1853 * KVM_APIC_PV_EOI_PENDING is unset:
1854 * -> host disabled PV EOI.
1855 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1856 * -> host enabled PV EOI, guest did not execute EOI yet.
1857 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1858 * -> host enabled PV EOI, guest executed EOI.
1860 BUG_ON(!pv_eoi_enabled(vcpu
));
1861 pending
= pv_eoi_get_pending(vcpu
);
1863 * Clear pending bit in any case: it will be set again on vmentry.
1864 * While this might not be ideal from performance point of view,
1865 * this makes sure pv eoi is only enabled when we know it's safe.
1867 pv_eoi_clr_pending(vcpu
);
1870 vector
= apic_set_eoi(apic
);
1871 trace_kvm_pv_eoi(apic
, vector
);
1874 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1878 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1879 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1881 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1884 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1887 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1891 * apic_sync_pv_eoi_to_guest - called before vmentry
1893 * Detect whether it's safe to enable PV EOI and
1896 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1897 struct kvm_lapic
*apic
)
1899 if (!pv_eoi_enabled(vcpu
) ||
1900 /* IRR set or many bits in ISR: could be nested. */
1901 apic
->irr_pending
||
1902 /* Cache not set: could be safe but we don't bother. */
1903 apic
->highest_isr_cache
== -1 ||
1904 /* Need EOI to update ioapic. */
1905 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1907 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1908 * so we need not do anything here.
1913 pv_eoi_set_pending(apic
->vcpu
);
1916 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1919 int max_irr
, max_isr
;
1920 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1922 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1924 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1927 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1928 max_irr
= apic_find_highest_irr(apic
);
1931 max_isr
= apic_find_highest_isr(apic
);
1934 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1936 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1940 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1943 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1944 &vcpu
->arch
.apic
->vapic_cache
,
1945 vapic_addr
, sizeof(u32
)))
1947 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1949 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1952 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1956 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1958 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1959 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1961 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1964 if (reg
== APIC_ICR2
)
1967 /* if this is ICR write vector before command */
1968 if (reg
== APIC_ICR
)
1969 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1970 return apic_reg_write(apic
, reg
, (u32
)data
);
1973 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1975 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1976 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1978 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1981 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
1982 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1987 if (apic_reg_read(apic
, reg
, 4, &low
))
1989 if (reg
== APIC_ICR
)
1990 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1992 *data
= (((u64
)high
) << 32) | low
;
1997 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1999 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2001 if (!kvm_vcpu_has_lapic(vcpu
))
2004 /* if this is ICR write vector before command */
2005 if (reg
== APIC_ICR
)
2006 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2007 return apic_reg_write(apic
, reg
, (u32
)data
);
2010 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2012 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2015 if (!kvm_vcpu_has_lapic(vcpu
))
2018 if (apic_reg_read(apic
, reg
, 4, &low
))
2020 if (reg
== APIC_ICR
)
2021 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2023 *data
= (((u64
)high
) << 32) | low
;
2028 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
2030 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2031 if (!IS_ALIGNED(addr
, 4))
2034 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2035 if (!pv_eoi_enabled(vcpu
))
2037 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2041 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2043 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2047 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
2050 pe
= xchg(&apic
->pending_events
, 0);
2052 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2053 kvm_lapic_reset(vcpu
, true);
2054 kvm_vcpu_reset(vcpu
, true);
2055 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2056 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2058 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2060 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2061 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2062 /* evaluate pending_events before reading the vector */
2064 sipi_vector
= apic
->sipi_vector
;
2065 apic_debug("vcpu %d received sipi with vector # %x\n",
2066 vcpu
->vcpu_id
, sipi_vector
);
2067 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2068 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2072 void kvm_lapic_init(void)
2074 /* do not patch jump label more than once per second */
2075 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2076 jump_label_rate_limit(&apic_sw_disabled
, HZ
);