3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
79 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
82 static inline int apic_test_vector(int vec
, void *bitmap
)
84 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
89 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
91 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
92 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
95 static inline void apic_set_vector(int vec
, void *bitmap
)
97 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
100 static inline void apic_clear_vector(int vec
, void *bitmap
)
102 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
105 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
107 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
110 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
112 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
115 struct static_key_deferred apic_hw_disabled __read_mostly
;
116 struct static_key_deferred apic_sw_disabled __read_mostly
;
118 static inline int apic_enabled(struct kvm_lapic
*apic
)
120 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
132 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
135 #define KVM_X2APIC_CID_BITS 0
137 static void recalculate_apic_map(struct kvm
*kvm
)
139 struct kvm_apic_map
*new, *old
= NULL
;
140 struct kvm_vcpu
*vcpu
;
143 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
145 mutex_lock(&kvm
->arch
.apic_map_lock
);
151 /* flat mode is default */
154 new->lid_mask
= 0xff;
155 new->broadcast
= APIC_BROADCAST
;
157 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
158 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
162 if (!kvm_apic_present(vcpu
))
166 * All APICs have to be configured in the same mode by an OS.
167 * We take advatage of this while building logical id loockup
168 * table. After reset APICs are in xapic/flat mode, so if we
169 * find apic with different setting we assume this is the mode
170 * OS wants all apics to be in; build lookup table accordingly.
172 if (apic_x2apic_mode(apic
)) {
175 new->cid_mask
= (1 << KVM_X2APIC_CID_BITS
) - 1;
176 new->lid_mask
= 0xffff;
177 new->broadcast
= X2APIC_BROADCAST
;
178 } else if (kvm_apic_sw_enabled(apic
) &&
179 !new->cid_mask
/* flat mode */ &&
180 kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_CLUSTER
) {
186 new->phys_map
[kvm_apic_id(apic
)] = apic
;
188 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
189 cid
= apic_cluster_id(new, ldr
);
190 lid
= apic_logical_id(new, ldr
);
193 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
196 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
197 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
198 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
199 mutex_unlock(&kvm
->arch
.apic_map_lock
);
204 kvm_vcpu_request_scan_ioapic(kvm
);
207 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
209 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
211 apic_set_reg(apic
, APIC_SPIV
, val
);
213 if (enabled
!= apic
->sw_enabled
) {
214 apic
->sw_enabled
= enabled
;
216 static_key_slow_dec_deferred(&apic_sw_disabled
);
217 recalculate_apic_map(apic
->vcpu
->kvm
);
219 static_key_slow_inc(&apic_sw_disabled
.key
);
223 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
225 apic_set_reg(apic
, APIC_ID
, id
<< 24);
226 recalculate_apic_map(apic
->vcpu
->kvm
);
229 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
231 apic_set_reg(apic
, APIC_LDR
, id
);
232 recalculate_apic_map(apic
->vcpu
->kvm
);
235 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
237 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
240 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
242 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
245 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
247 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
248 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_ONESHOT
);
251 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
253 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
254 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_PERIODIC
);
257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
259 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
260 apic
->lapic_timer
.timer_mode_mask
) ==
261 APIC_LVT_TIMER_TSCDEADLINE
);
264 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
266 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
269 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
271 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
272 struct kvm_cpuid_entry2
*feat
;
273 u32 v
= APIC_VERSION
;
275 if (!kvm_vcpu_has_lapic(vcpu
))
278 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
279 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
280 v
|= APIC_LVR_DIRECTED_EOI
;
281 apic_set_reg(apic
, APIC_LVR
, v
);
284 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
285 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
286 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
287 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
288 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
289 LVT_MASK
/* LVTERR */
292 static int find_highest_vector(void *bitmap
)
297 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
298 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
299 reg
= bitmap
+ REG_POS(vec
);
301 return fls(*reg
) - 1 + vec
;
307 static u8
count_vectors(void *bitmap
)
313 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
314 reg
= bitmap
+ REG_POS(vec
);
315 count
+= hweight32(*reg
);
321 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
324 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
326 for (i
= 0; i
<= 7; i
++) {
327 pir_val
= xchg(&pir
[i
], 0);
329 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
334 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
336 apic
->irr_pending
= true;
337 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
340 static inline int apic_search_irr(struct kvm_lapic
*apic
)
342 return find_highest_vector(apic
->regs
+ APIC_IRR
);
345 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
350 * Note that irr_pending is just a hint. It will be always
351 * true with virtual interrupt delivery enabled.
353 if (!apic
->irr_pending
)
356 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
357 result
= apic_search_irr(apic
);
358 ASSERT(result
== -1 || result
>= 16);
363 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
365 struct kvm_vcpu
*vcpu
;
369 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
370 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
371 /* try to update RVI */
372 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
374 vec
= apic_search_irr(apic
);
375 apic
->irr_pending
= (vec
!= -1);
379 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
381 struct kvm_vcpu
*vcpu
;
383 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
389 * With APIC virtualization enabled, all caching is disabled
390 * because the processor can modify ISR under the hood. Instead
393 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
394 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
397 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
399 * ISR (in service register) bit is set when injecting an interrupt.
400 * The highest vector is injected. Thus the latest bit set matches
401 * the highest bit in ISR.
403 apic
->highest_isr_cache
= vec
;
407 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
412 * Note that isr_count is always 1, and highest_isr_cache
413 * is always -1, with APIC virtualization enabled.
415 if (!apic
->isr_count
)
417 if (likely(apic
->highest_isr_cache
!= -1))
418 return apic
->highest_isr_cache
;
420 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
421 ASSERT(result
== -1 || result
>= 16);
426 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
428 struct kvm_vcpu
*vcpu
;
429 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
435 * We do get here for APIC virtualization enabled if the guest
436 * uses the Hyper-V APIC enlightenment. In this case we may need
437 * to trigger a new interrupt delivery by writing the SVI field;
438 * on the other hand isr_count and highest_isr_cache are unused
439 * and must be left alone.
441 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
442 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
443 apic_find_highest_isr(apic
));
446 BUG_ON(apic
->isr_count
< 0);
447 apic
->highest_isr_cache
= -1;
451 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
455 /* This may race with setting of irr in __apic_accept_irq() and
456 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
457 * will cause vmexit immediately and the value will be recalculated
458 * on the next vmentry.
460 if (!kvm_vcpu_has_lapic(vcpu
))
462 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
467 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
468 int vector
, int level
, int trig_mode
,
469 unsigned long *dest_map
);
471 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
472 unsigned long *dest_map
)
474 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
476 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
477 irq
->level
, irq
->trig_mode
, dest_map
);
480 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
483 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
487 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
490 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
494 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
496 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
499 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
502 if (pv_eoi_get_user(vcpu
, &val
) < 0)
503 apic_debug("Can't read EOI MSR value: 0x%llx\n",
504 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
508 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
510 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
511 apic_debug("Can't set EOI MSR value: 0x%llx\n",
512 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
515 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
518 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
520 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
521 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
522 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
525 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
528 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
530 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
533 for (i
= 0; i
< 8; i
++)
534 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
537 static void apic_update_ppr(struct kvm_lapic
*apic
)
539 u32 tpr
, isrv
, ppr
, old_ppr
;
542 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
543 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
544 isr
= apic_find_highest_isr(apic
);
545 isrv
= (isr
!= -1) ? isr
: 0;
547 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
552 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
553 apic
, ppr
, isr
, isrv
);
555 if (old_ppr
!= ppr
) {
556 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
558 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
562 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
564 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
565 apic_update_ppr(apic
);
568 static int kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 dest
)
570 return dest
== (apic_x2apic_mode(apic
) ?
571 X2APIC_BROADCAST
: APIC_BROADCAST
);
574 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 dest
)
576 return kvm_apic_id(apic
) == dest
|| kvm_apic_broadcast(apic
, dest
);
579 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
584 if (kvm_apic_broadcast(apic
, mda
))
587 if (apic_x2apic_mode(apic
)) {
588 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
589 return logical_id
& mda
;
592 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
594 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
596 if (logical_id
& mda
)
599 case APIC_DFR_CLUSTER
:
600 if (((logical_id
>> 4) == (mda
>> 0x4))
601 && (logical_id
& mda
& 0xf))
605 apic_debug("Bad DFR vcpu %d: %08x\n",
606 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
613 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
614 int short_hand
, unsigned int dest
, int dest_mode
)
617 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
619 apic_debug("target %p, source %p, dest 0x%x, "
620 "dest_mode 0x%x, short_hand 0x%x\n",
621 target
, source
, dest
, dest_mode
, short_hand
);
624 switch (short_hand
) {
625 case APIC_DEST_NOSHORT
:
628 result
= kvm_apic_match_physical_addr(target
, dest
);
631 result
= kvm_apic_match_logical_addr(target
, dest
);
634 result
= (target
== source
);
636 case APIC_DEST_ALLINC
:
639 case APIC_DEST_ALLBUT
:
640 result
= (target
!= source
);
643 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
651 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
652 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
654 struct kvm_apic_map
*map
;
655 unsigned long bitmap
= 1;
656 struct kvm_lapic
**dst
;
662 if (irq
->shorthand
== APIC_DEST_SELF
) {
663 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
671 map
= rcu_dereference(kvm
->arch
.apic_map
);
676 if (irq
->dest_id
== map
->broadcast
)
679 if (irq
->dest_mode
== 0) { /* physical mode */
680 if (irq
->delivery_mode
== APIC_DM_LOWEST
)
682 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
684 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
686 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
688 bitmap
= apic_logical_id(map
, mda
);
690 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
692 for_each_set_bit(i
, &bitmap
, 16) {
697 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
701 bitmap
= (l
>= 0) ? 1 << l
: 0;
705 for_each_set_bit(i
, &bitmap
, 16) {
710 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
720 * Add a pending IRQ into lapic.
721 * Return 1 if successfully added and 0 if discarded.
723 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
724 int vector
, int level
, int trig_mode
,
725 unsigned long *dest_map
)
728 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
730 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
732 switch (delivery_mode
) {
734 vcpu
->arch
.apic_arb_prio
++;
736 /* FIXME add logic for vcpu on reset */
737 if (unlikely(!apic_enabled(apic
)))
743 __set_bit(vcpu
->vcpu_id
, dest_map
);
745 if (kvm_x86_ops
->deliver_posted_interrupt
)
746 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
748 apic_set_irr(vector
, apic
);
750 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
757 vcpu
->arch
.pv
.pv_unhalted
= 1;
758 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
763 apic_debug("Ignoring guest SMI\n");
768 kvm_inject_nmi(vcpu
);
773 if (!trig_mode
|| level
) {
775 /* assumes that there are only KVM_APIC_INIT/SIPI */
776 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
777 /* make sure pending_events is visible before sending
780 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
783 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
788 case APIC_DM_STARTUP
:
789 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
790 vcpu
->vcpu_id
, vector
);
792 apic
->sipi_vector
= vector
;
793 /* make sure sipi_vector is visible for the receiver */
795 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
796 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
802 * Should only be called by kvm_apic_local_deliver() with LVT0,
803 * before NMI watchdog was enabled. Already handled by
804 * kvm_apic_accept_pic_intr().
809 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
816 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
818 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
821 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
823 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
824 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
826 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
827 trigger_mode
= IOAPIC_LEVEL_TRIG
;
829 trigger_mode
= IOAPIC_EDGE_TRIG
;
830 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
834 static int apic_set_eoi(struct kvm_lapic
*apic
)
836 int vector
= apic_find_highest_isr(apic
);
838 trace_kvm_eoi(apic
, vector
);
841 * Not every write EOI will has corresponding ISR,
842 * one example is when Kernel check timer on setup_IO_APIC
847 apic_clear_isr(vector
, apic
);
848 apic_update_ppr(apic
);
850 kvm_ioapic_send_eoi(apic
, vector
);
851 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
856 * this interface assumes a trap-like exit, which has already finished
857 * desired side effect including vISR and vPPR update.
859 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
861 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
863 trace_kvm_eoi(apic
, vector
);
865 kvm_ioapic_send_eoi(apic
, vector
);
866 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
868 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
870 static void apic_send_ipi(struct kvm_lapic
*apic
)
872 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
873 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
874 struct kvm_lapic_irq irq
;
876 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
877 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
878 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
879 irq
.level
= icr_low
& APIC_INT_ASSERT
;
880 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
881 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
882 if (apic_x2apic_mode(apic
))
883 irq
.dest_id
= icr_high
;
885 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
887 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
889 apic_debug("icr_high 0x%x, icr_low 0x%x, "
890 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
891 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
892 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
893 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
896 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
899 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
905 ASSERT(apic
!= NULL
);
907 /* if initial count is 0, current count should also be 0 */
908 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
909 apic
->lapic_timer
.period
== 0)
912 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
913 if (ktime_to_ns(remaining
) < 0)
914 remaining
= ktime_set(0, 0);
916 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
917 tmcct
= div64_u64(ns
,
918 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
923 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
925 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
926 struct kvm_run
*run
= vcpu
->run
;
928 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
929 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
930 run
->tpr_access
.is_write
= write
;
933 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
935 if (apic
->vcpu
->arch
.tpr_access_reporting
)
936 __report_tpr_access(apic
, write
);
939 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
943 if (offset
>= LAPIC_MMIO_LENGTH
)
948 if (apic_x2apic_mode(apic
))
949 val
= kvm_apic_id(apic
);
951 val
= kvm_apic_id(apic
) << 24;
954 apic_debug("Access APIC ARBPRI register which is for P6\n");
957 case APIC_TMCCT
: /* Timer CCR */
958 if (apic_lvtt_tscdeadline(apic
))
961 val
= apic_get_tmcct(apic
);
964 apic_update_ppr(apic
);
965 val
= kvm_apic_get_reg(apic
, offset
);
968 report_tpr_access(apic
, false);
971 val
= kvm_apic_get_reg(apic
, offset
);
978 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
980 return container_of(dev
, struct kvm_lapic
, dev
);
983 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
986 unsigned char alignment
= offset
& 0xf;
988 /* this bitmask has a bit cleared for each reserved register */
989 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
991 if ((alignment
+ len
) > 4) {
992 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
997 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
998 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1003 result
= __apic_read(apic
, offset
& ~0xf);
1005 trace_kvm_apic_read(offset
, result
);
1011 memcpy(data
, (char *)&result
+ alignment
, len
);
1014 printk(KERN_ERR
"Local APIC read with len = %x, "
1015 "should be 1,2, or 4 instead\n", len
);
1021 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1023 return kvm_apic_hw_enabled(apic
) &&
1024 addr
>= apic
->base_address
&&
1025 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1028 static int apic_mmio_read(struct kvm_io_device
*this,
1029 gpa_t address
, int len
, void *data
)
1031 struct kvm_lapic
*apic
= to_lapic(this);
1032 u32 offset
= address
- apic
->base_address
;
1034 if (!apic_mmio_in_range(apic
, address
))
1037 apic_reg_read(apic
, offset
, len
, data
);
1042 static void update_divide_count(struct kvm_lapic
*apic
)
1044 u32 tmp1
, tmp2
, tdcr
;
1046 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1048 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1049 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1051 apic_debug("timer divide count is 0x%x\n",
1052 apic
->divide_count
);
1055 static void apic_timer_expired(struct kvm_lapic
*apic
)
1057 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1058 wait_queue_head_t
*q
= &vcpu
->wq
;
1061 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1064 if (atomic_read(&apic
->lapic_timer
.pending
))
1067 atomic_inc(&apic
->lapic_timer
.pending
);
1068 /* FIXME: this code should not know anything about vcpus */
1069 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1071 if (waitqueue_active(q
))
1072 wake_up_interruptible(q
);
1075 static void start_apic_timer(struct kvm_lapic
*apic
)
1078 atomic_set(&apic
->lapic_timer
.pending
, 0);
1080 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1081 /* lapic timer in oneshot or periodic mode */
1082 now
= apic
->lapic_timer
.timer
.base
->get_time();
1083 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1084 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1086 if (!apic
->lapic_timer
.period
)
1089 * Do not allow the guest to program periodic timers with small
1090 * interval, since the hrtimers are not throttled by the host
1093 if (apic_lvtt_period(apic
)) {
1094 s64 min_period
= min_timer_period_us
* 1000LL;
1096 if (apic
->lapic_timer
.period
< min_period
) {
1097 pr_info_ratelimited(
1098 "kvm: vcpu %i: requested %lld ns "
1099 "lapic timer period limited to %lld ns\n",
1100 apic
->vcpu
->vcpu_id
,
1101 apic
->lapic_timer
.period
, min_period
);
1102 apic
->lapic_timer
.period
= min_period
;
1106 hrtimer_start(&apic
->lapic_timer
.timer
,
1107 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1110 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1112 "timer initial count 0x%x, period %lldns, "
1113 "expire @ 0x%016" PRIx64
".\n", __func__
,
1114 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1115 kvm_apic_get_reg(apic
, APIC_TMICT
),
1116 apic
->lapic_timer
.period
,
1117 ktime_to_ns(ktime_add_ns(now
,
1118 apic
->lapic_timer
.period
)));
1119 } else if (apic_lvtt_tscdeadline(apic
)) {
1120 /* lapic timer in tsc deadline mode */
1121 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1123 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1124 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1125 unsigned long flags
;
1127 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1130 local_irq_save(flags
);
1132 now
= apic
->lapic_timer
.timer
.base
->get_time();
1133 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1134 if (likely(tscdeadline
> guest_tsc
)) {
1135 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1136 do_div(ns
, this_tsc_khz
);
1137 hrtimer_start(&apic
->lapic_timer
.timer
,
1138 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1140 apic_timer_expired(apic
);
1142 local_irq_restore(flags
);
1146 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1148 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1150 if (apic_lvt_nmi_mode(lvt0_val
)) {
1151 if (!nmi_wd_enabled
) {
1152 apic_debug("Receive NMI setting on APIC_LVT0 "
1153 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1154 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1156 } else if (nmi_wd_enabled
)
1157 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1160 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1164 trace_kvm_apic_write(reg
, val
);
1167 case APIC_ID
: /* Local APIC ID */
1168 if (!apic_x2apic_mode(apic
))
1169 kvm_apic_set_id(apic
, val
>> 24);
1175 report_tpr_access(apic
, true);
1176 apic_set_tpr(apic
, val
& 0xff);
1184 if (!apic_x2apic_mode(apic
))
1185 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1191 if (!apic_x2apic_mode(apic
)) {
1192 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1193 recalculate_apic_map(apic
->vcpu
->kvm
);
1200 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1201 mask
|= APIC_SPIV_DIRECTED_EOI
;
1202 apic_set_spiv(apic
, val
& mask
);
1203 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1207 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1208 lvt_val
= kvm_apic_get_reg(apic
,
1209 APIC_LVTT
+ 0x10 * i
);
1210 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1211 lvt_val
| APIC_LVT_MASKED
);
1213 atomic_set(&apic
->lapic_timer
.pending
, 0);
1219 /* No delay here, so we always clear the pending bit */
1220 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1221 apic_send_ipi(apic
);
1225 if (!apic_x2apic_mode(apic
))
1227 apic_set_reg(apic
, APIC_ICR2
, val
);
1231 apic_manage_nmi_watchdog(apic
, val
);
1236 /* TODO: Check vector */
1237 if (!kvm_apic_sw_enabled(apic
))
1238 val
|= APIC_LVT_MASKED
;
1240 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1241 apic_set_reg(apic
, reg
, val
);
1246 u32 timer_mode
= val
& apic
->lapic_timer
.timer_mode_mask
;
1248 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1249 apic
->lapic_timer
.timer_mode
= timer_mode
;
1250 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1253 if (!kvm_apic_sw_enabled(apic
))
1254 val
|= APIC_LVT_MASKED
;
1255 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1256 apic_set_reg(apic
, APIC_LVTT
, val
);
1261 if (apic_lvtt_tscdeadline(apic
))
1264 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1265 apic_set_reg(apic
, APIC_TMICT
, val
);
1266 start_apic_timer(apic
);
1271 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1272 apic_set_reg(apic
, APIC_TDCR
, val
);
1273 update_divide_count(apic
);
1277 if (apic_x2apic_mode(apic
) && val
!= 0) {
1278 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1284 if (apic_x2apic_mode(apic
)) {
1285 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1294 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1298 static int apic_mmio_write(struct kvm_io_device
*this,
1299 gpa_t address
, int len
, const void *data
)
1301 struct kvm_lapic
*apic
= to_lapic(this);
1302 unsigned int offset
= address
- apic
->base_address
;
1305 if (!apic_mmio_in_range(apic
, address
))
1309 * APIC register must be aligned on 128-bits boundary.
1310 * 32/64/128 bits registers must be accessed thru 32 bits.
1313 if (len
!= 4 || (offset
& 0xf)) {
1314 /* Don't shout loud, $infamous_os would cause only noise. */
1315 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1321 /* too common printing */
1322 if (offset
!= APIC_EOI
)
1323 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1324 "0x%x\n", __func__
, offset
, len
, val
);
1326 apic_reg_write(apic
, offset
& 0xff0, val
);
1331 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1333 if (kvm_vcpu_has_lapic(vcpu
))
1334 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1336 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1338 /* emulate APIC access in a trap manner */
1339 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1343 /* hw has done the conditional check and inst decode */
1346 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1348 /* TODO: optimize to just emulate side effect w/o one more write */
1349 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1351 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1353 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1355 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1357 if (!vcpu
->arch
.apic
)
1360 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1362 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1363 static_key_slow_dec_deferred(&apic_hw_disabled
);
1365 if (!apic
->sw_enabled
)
1366 static_key_slow_dec_deferred(&apic_sw_disabled
);
1369 free_page((unsigned long)apic
->regs
);
1375 *----------------------------------------------------------------------
1377 *----------------------------------------------------------------------
1380 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1382 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1384 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1385 apic_lvtt_period(apic
))
1388 return apic
->lapic_timer
.tscdeadline
;
1391 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1393 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1395 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1396 apic_lvtt_period(apic
))
1399 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1400 apic
->lapic_timer
.tscdeadline
= data
;
1401 start_apic_timer(apic
);
1404 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1406 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1408 if (!kvm_vcpu_has_lapic(vcpu
))
1411 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1412 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1415 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1419 if (!kvm_vcpu_has_lapic(vcpu
))
1422 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1424 return (tpr
& 0xf0) >> 4;
1427 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1429 u64 old_value
= vcpu
->arch
.apic_base
;
1430 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1433 value
|= MSR_IA32_APICBASE_BSP
;
1434 vcpu
->arch
.apic_base
= value
;
1438 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1439 value
&= ~MSR_IA32_APICBASE_BSP
;
1440 vcpu
->arch
.apic_base
= value
;
1442 /* update jump label if enable bit changes */
1443 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1444 if (value
& MSR_IA32_APICBASE_ENABLE
)
1445 static_key_slow_dec_deferred(&apic_hw_disabled
);
1447 static_key_slow_inc(&apic_hw_disabled
.key
);
1448 recalculate_apic_map(vcpu
->kvm
);
1451 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1452 if (value
& X2APIC_ENABLE
) {
1453 u32 id
= kvm_apic_id(apic
);
1454 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1455 kvm_apic_set_ldr(apic
, ldr
);
1456 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1458 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1461 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1462 MSR_IA32_APICBASE_BASE
;
1464 /* with FSB delivery interrupt, we can restart APIC functionality */
1465 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1466 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1470 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1472 struct kvm_lapic
*apic
;
1475 apic_debug("%s\n", __func__
);
1478 apic
= vcpu
->arch
.apic
;
1479 ASSERT(apic
!= NULL
);
1481 /* Stop the timer in case it's a reset to an active apic */
1482 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1484 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1485 kvm_apic_set_version(apic
->vcpu
);
1487 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1488 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1489 apic
->lapic_timer
.timer_mode
= 0;
1490 apic_set_reg(apic
, APIC_LVT0
,
1491 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1493 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1494 apic_set_spiv(apic
, 0xff);
1495 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1496 kvm_apic_set_ldr(apic
, 0);
1497 apic_set_reg(apic
, APIC_ESR
, 0);
1498 apic_set_reg(apic
, APIC_ICR
, 0);
1499 apic_set_reg(apic
, APIC_ICR2
, 0);
1500 apic_set_reg(apic
, APIC_TDCR
, 0);
1501 apic_set_reg(apic
, APIC_TMICT
, 0);
1502 for (i
= 0; i
< 8; i
++) {
1503 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1504 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1505 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1507 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1508 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1509 apic
->highest_isr_cache
= -1;
1510 update_divide_count(apic
);
1511 atomic_set(&apic
->lapic_timer
.pending
, 0);
1512 if (kvm_vcpu_is_bsp(vcpu
))
1513 kvm_lapic_set_base(vcpu
,
1514 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1515 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1516 apic_update_ppr(apic
);
1518 vcpu
->arch
.apic_arb_prio
= 0;
1519 vcpu
->arch
.apic_attention
= 0;
1521 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1522 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1523 vcpu
, kvm_apic_id(apic
),
1524 vcpu
->arch
.apic_base
, apic
->base_address
);
1528 *----------------------------------------------------------------------
1530 *----------------------------------------------------------------------
1533 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1535 return apic_lvtt_period(apic
);
1538 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1540 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1542 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1543 apic_lvt_enabled(apic
, APIC_LVTT
))
1544 return atomic_read(&apic
->lapic_timer
.pending
);
1549 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1551 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1552 int vector
, mode
, trig_mode
;
1554 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1555 vector
= reg
& APIC_VECTOR_MASK
;
1556 mode
= reg
& APIC_MODE_MASK
;
1557 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1558 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1564 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1566 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1569 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1572 static const struct kvm_io_device_ops apic_mmio_ops
= {
1573 .read
= apic_mmio_read
,
1574 .write
= apic_mmio_write
,
1577 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1579 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1580 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1582 apic_timer_expired(apic
);
1584 if (lapic_is_periodic(apic
)) {
1585 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1586 return HRTIMER_RESTART
;
1588 return HRTIMER_NORESTART
;
1591 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1593 struct kvm_lapic
*apic
;
1595 ASSERT(vcpu
!= NULL
);
1596 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1598 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1602 vcpu
->arch
.apic
= apic
;
1604 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1606 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1608 goto nomem_free_apic
;
1612 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1614 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1617 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1618 * thinking that APIC satet has changed.
1620 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1621 kvm_lapic_set_base(vcpu
,
1622 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1624 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1625 kvm_lapic_reset(vcpu
);
1626 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1635 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1637 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1640 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1643 apic_update_ppr(apic
);
1644 highest_irr
= apic_find_highest_irr(apic
);
1645 if ((highest_irr
== -1) ||
1646 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1651 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1653 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1656 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1658 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1659 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1664 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1666 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1668 if (!kvm_vcpu_has_lapic(vcpu
))
1671 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1672 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1673 if (apic_lvtt_tscdeadline(apic
))
1674 apic
->lapic_timer
.tscdeadline
= 0;
1675 atomic_set(&apic
->lapic_timer
.pending
, 0);
1679 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1681 int vector
= kvm_apic_has_interrupt(vcpu
);
1682 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1688 * We get here even with APIC virtualization enabled, if doing
1689 * nested virtualization and L1 runs with the "acknowledge interrupt
1690 * on exit" mode. Then we cannot inject the interrupt via RVI,
1691 * because the process would deliver it through the IDT.
1694 apic_set_isr(vector
, apic
);
1695 apic_update_ppr(apic
);
1696 apic_clear_irr(vector
, apic
);
1700 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1701 struct kvm_lapic_state
*s
)
1703 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1705 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1706 /* set SPIV separately to get count of SW disabled APICs right */
1707 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1708 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1709 /* call kvm_apic_set_id() to put apic into apic_map */
1710 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1711 kvm_apic_set_version(vcpu
);
1713 apic_update_ppr(apic
);
1714 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1715 update_divide_count(apic
);
1716 start_apic_timer(apic
);
1717 apic
->irr_pending
= true;
1718 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1719 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1720 apic
->highest_isr_cache
= -1;
1721 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1722 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1723 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1726 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1728 struct hrtimer
*timer
;
1730 if (!kvm_vcpu_has_lapic(vcpu
))
1733 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1734 if (hrtimer_cancel(timer
))
1735 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1739 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1741 * Detect whether guest triggered PV EOI since the
1742 * last entry. If yes, set EOI on guests's behalf.
1743 * Clear PV EOI in guest memory in any case.
1745 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1746 struct kvm_lapic
*apic
)
1751 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1752 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1754 * KVM_APIC_PV_EOI_PENDING is unset:
1755 * -> host disabled PV EOI.
1756 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1757 * -> host enabled PV EOI, guest did not execute EOI yet.
1758 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1759 * -> host enabled PV EOI, guest executed EOI.
1761 BUG_ON(!pv_eoi_enabled(vcpu
));
1762 pending
= pv_eoi_get_pending(vcpu
);
1764 * Clear pending bit in any case: it will be set again on vmentry.
1765 * While this might not be ideal from performance point of view,
1766 * this makes sure pv eoi is only enabled when we know it's safe.
1768 pv_eoi_clr_pending(vcpu
);
1771 vector
= apic_set_eoi(apic
);
1772 trace_kvm_pv_eoi(apic
, vector
);
1775 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1779 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1780 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1782 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1785 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1788 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1792 * apic_sync_pv_eoi_to_guest - called before vmentry
1794 * Detect whether it's safe to enable PV EOI and
1797 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1798 struct kvm_lapic
*apic
)
1800 if (!pv_eoi_enabled(vcpu
) ||
1801 /* IRR set or many bits in ISR: could be nested. */
1802 apic
->irr_pending
||
1803 /* Cache not set: could be safe but we don't bother. */
1804 apic
->highest_isr_cache
== -1 ||
1805 /* Need EOI to update ioapic. */
1806 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1808 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1809 * so we need not do anything here.
1814 pv_eoi_set_pending(apic
->vcpu
);
1817 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1820 int max_irr
, max_isr
;
1821 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1823 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1825 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1828 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1829 max_irr
= apic_find_highest_irr(apic
);
1832 max_isr
= apic_find_highest_isr(apic
);
1835 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1837 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1841 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1844 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1845 &vcpu
->arch
.apic
->vapic_cache
,
1846 vapic_addr
, sizeof(u32
)))
1848 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1850 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1853 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1857 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1859 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1860 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1862 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1865 /* if this is ICR write vector before command */
1867 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1868 return apic_reg_write(apic
, reg
, (u32
)data
);
1871 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1873 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1874 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1876 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1879 if (apic_reg_read(apic
, reg
, 4, &low
))
1882 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1884 *data
= (((u64
)high
) << 32) | low
;
1889 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1891 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1893 if (!kvm_vcpu_has_lapic(vcpu
))
1896 /* if this is ICR write vector before command */
1897 if (reg
== APIC_ICR
)
1898 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1899 return apic_reg_write(apic
, reg
, (u32
)data
);
1902 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1904 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1907 if (!kvm_vcpu_has_lapic(vcpu
))
1910 if (apic_reg_read(apic
, reg
, 4, &low
))
1912 if (reg
== APIC_ICR
)
1913 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1915 *data
= (((u64
)high
) << 32) | low
;
1920 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1922 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1923 if (!IS_ALIGNED(addr
, 4))
1926 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1927 if (!pv_eoi_enabled(vcpu
))
1929 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1933 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1935 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1936 unsigned int sipi_vector
;
1939 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
1942 pe
= xchg(&apic
->pending_events
, 0);
1944 if (test_bit(KVM_APIC_INIT
, &pe
)) {
1945 kvm_lapic_reset(vcpu
);
1946 kvm_vcpu_reset(vcpu
);
1947 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1948 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1950 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1952 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
1953 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1954 /* evaluate pending_events before reading the vector */
1956 sipi_vector
= apic
->sipi_vector
;
1957 apic_debug("vcpu %d received sipi with vector # %x\n",
1958 vcpu
->vcpu_id
, sipi_vector
);
1959 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1960 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1964 void kvm_lapic_init(void)
1966 /* do not patch jump label more than once per second */
1967 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1968 jump_label_rate_limit(&apic_sw_disabled
, HZ
);