3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
79 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
82 static inline int apic_test_vector(int vec
, void *bitmap
)
84 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
89 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
91 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
92 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
95 static inline void apic_set_vector(int vec
, void *bitmap
)
97 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
100 static inline void apic_clear_vector(int vec
, void *bitmap
)
102 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
105 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
107 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
110 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
112 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
115 struct static_key_deferred apic_hw_disabled __read_mostly
;
116 struct static_key_deferred apic_sw_disabled __read_mostly
;
118 static inline int apic_enabled(struct kvm_lapic
*apic
)
120 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
132 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
135 #define KVM_X2APIC_CID_BITS 0
137 static void recalculate_apic_map(struct kvm
*kvm
)
139 struct kvm_apic_map
*new, *old
= NULL
;
140 struct kvm_vcpu
*vcpu
;
143 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
145 mutex_lock(&kvm
->arch
.apic_map_lock
);
151 /* flat mode is default */
154 new->lid_mask
= 0xff;
155 new->broadcast
= APIC_BROADCAST
;
157 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
158 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
160 if (!kvm_apic_present(vcpu
))
164 * All APICs have to be configured in the same mode by an OS.
165 * We take advatage of this while building logical id loockup
166 * table. After reset APICs are in xapic/flat mode, so if we
167 * find apic with different setting we assume this is the mode
168 * OS wants all apics to be in; build lookup table accordingly.
170 if (apic_x2apic_mode(apic
)) {
173 new->cid_mask
= (1 << KVM_X2APIC_CID_BITS
) - 1;
174 new->lid_mask
= 0xffff;
175 new->broadcast
= X2APIC_BROADCAST
;
177 } else if (kvm_apic_sw_enabled(apic
)) {
178 if (kvm_apic_get_reg(apic
, APIC_DFR
) ==
188 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
189 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
193 new->phys_map
[kvm_apic_id(apic
)] = apic
;
195 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
196 cid
= apic_cluster_id(new, ldr
);
197 lid
= apic_logical_id(new, ldr
);
200 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
203 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
204 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
205 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
206 mutex_unlock(&kvm
->arch
.apic_map_lock
);
211 kvm_vcpu_request_scan_ioapic(kvm
);
214 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
216 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
218 apic_set_reg(apic
, APIC_SPIV
, val
);
220 if (enabled
!= apic
->sw_enabled
) {
221 apic
->sw_enabled
= enabled
;
223 static_key_slow_dec_deferred(&apic_sw_disabled
);
224 recalculate_apic_map(apic
->vcpu
->kvm
);
226 static_key_slow_inc(&apic_sw_disabled
.key
);
230 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
232 apic_set_reg(apic
, APIC_ID
, id
<< 24);
233 recalculate_apic_map(apic
->vcpu
->kvm
);
236 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
238 apic_set_reg(apic
, APIC_LDR
, id
);
239 recalculate_apic_map(apic
->vcpu
->kvm
);
242 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
244 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
247 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
249 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
252 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
254 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
257 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
259 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
262 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
264 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
267 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
269 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
272 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
274 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
275 struct kvm_cpuid_entry2
*feat
;
276 u32 v
= APIC_VERSION
;
278 if (!kvm_vcpu_has_lapic(vcpu
))
281 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
282 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
283 v
|= APIC_LVR_DIRECTED_EOI
;
284 apic_set_reg(apic
, APIC_LVR
, v
);
287 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
288 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
289 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
290 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
291 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
292 LVT_MASK
/* LVTERR */
295 static int find_highest_vector(void *bitmap
)
300 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
301 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
302 reg
= bitmap
+ REG_POS(vec
);
304 return fls(*reg
) - 1 + vec
;
310 static u8
count_vectors(void *bitmap
)
316 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
317 reg
= bitmap
+ REG_POS(vec
);
318 count
+= hweight32(*reg
);
324 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
327 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
329 for (i
= 0; i
<= 7; i
++) {
330 pir_val
= xchg(&pir
[i
], 0);
332 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
335 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
337 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
339 apic
->irr_pending
= true;
340 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
343 static inline int apic_search_irr(struct kvm_lapic
*apic
)
345 return find_highest_vector(apic
->regs
+ APIC_IRR
);
348 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
353 * Note that irr_pending is just a hint. It will be always
354 * true with virtual interrupt delivery enabled.
356 if (!apic
->irr_pending
)
359 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
360 result
= apic_search_irr(apic
);
361 ASSERT(result
== -1 || result
>= 16);
366 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
368 struct kvm_vcpu
*vcpu
;
372 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
373 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
374 /* try to update RVI */
375 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
377 vec
= apic_search_irr(apic
);
378 apic
->irr_pending
= (vec
!= -1);
382 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
384 struct kvm_vcpu
*vcpu
;
386 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
392 * With APIC virtualization enabled, all caching is disabled
393 * because the processor can modify ISR under the hood. Instead
396 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
397 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
400 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
402 * ISR (in service register) bit is set when injecting an interrupt.
403 * The highest vector is injected. Thus the latest bit set matches
404 * the highest bit in ISR.
406 apic
->highest_isr_cache
= vec
;
410 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
415 * Note that isr_count is always 1, and highest_isr_cache
416 * is always -1, with APIC virtualization enabled.
418 if (!apic
->isr_count
)
420 if (likely(apic
->highest_isr_cache
!= -1))
421 return apic
->highest_isr_cache
;
423 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
424 ASSERT(result
== -1 || result
>= 16);
429 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
431 struct kvm_vcpu
*vcpu
;
432 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
438 * We do get here for APIC virtualization enabled if the guest
439 * uses the Hyper-V APIC enlightenment. In this case we may need
440 * to trigger a new interrupt delivery by writing the SVI field;
441 * on the other hand isr_count and highest_isr_cache are unused
442 * and must be left alone.
444 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
445 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
446 apic_find_highest_isr(apic
));
449 BUG_ON(apic
->isr_count
< 0);
450 apic
->highest_isr_cache
= -1;
454 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
458 /* This may race with setting of irr in __apic_accept_irq() and
459 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
460 * will cause vmexit immediately and the value will be recalculated
461 * on the next vmentry.
463 if (!kvm_vcpu_has_lapic(vcpu
))
465 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
470 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
471 int vector
, int level
, int trig_mode
,
472 unsigned long *dest_map
);
474 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
475 unsigned long *dest_map
)
477 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
479 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
480 irq
->level
, irq
->trig_mode
, dest_map
);
483 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
486 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
490 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
493 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
497 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
499 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
502 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
505 if (pv_eoi_get_user(vcpu
, &val
) < 0)
506 apic_debug("Can't read EOI MSR value: 0x%llx\n",
507 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
511 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
513 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
514 apic_debug("Can't set EOI MSR value: 0x%llx\n",
515 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
518 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
521 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
523 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
524 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
525 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
528 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
531 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
533 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
536 for (i
= 0; i
< 8; i
++)
537 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
540 static void apic_update_ppr(struct kvm_lapic
*apic
)
542 u32 tpr
, isrv
, ppr
, old_ppr
;
545 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
546 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
547 isr
= apic_find_highest_isr(apic
);
548 isrv
= (isr
!= -1) ? isr
: 0;
550 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
555 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
556 apic
, ppr
, isr
, isrv
);
558 if (old_ppr
!= ppr
) {
559 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
561 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
565 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
567 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
568 apic_update_ppr(apic
);
571 static int kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 dest
)
573 return dest
== (apic_x2apic_mode(apic
) ?
574 X2APIC_BROADCAST
: APIC_BROADCAST
);
577 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 dest
)
579 return kvm_apic_id(apic
) == dest
|| kvm_apic_broadcast(apic
, dest
);
582 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
587 if (kvm_apic_broadcast(apic
, mda
))
590 if (apic_x2apic_mode(apic
)) {
591 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
592 return logical_id
& mda
;
595 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
597 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
599 if (logical_id
& mda
)
602 case APIC_DFR_CLUSTER
:
603 if (((logical_id
>> 4) == (mda
>> 0x4))
604 && (logical_id
& mda
& 0xf))
608 apic_debug("Bad DFR vcpu %d: %08x\n",
609 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
616 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
617 int short_hand
, unsigned int dest
, int dest_mode
)
620 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
622 apic_debug("target %p, source %p, dest 0x%x, "
623 "dest_mode 0x%x, short_hand 0x%x\n",
624 target
, source
, dest
, dest_mode
, short_hand
);
627 switch (short_hand
) {
628 case APIC_DEST_NOSHORT
:
631 result
= kvm_apic_match_physical_addr(target
, dest
);
634 result
= kvm_apic_match_logical_addr(target
, dest
);
637 result
= (target
== source
);
639 case APIC_DEST_ALLINC
:
642 case APIC_DEST_ALLBUT
:
643 result
= (target
!= source
);
646 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
654 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
655 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
657 struct kvm_apic_map
*map
;
658 unsigned long bitmap
= 1;
659 struct kvm_lapic
**dst
;
665 if (irq
->shorthand
== APIC_DEST_SELF
) {
666 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
674 map
= rcu_dereference(kvm
->arch
.apic_map
);
679 if (irq
->dest_id
== map
->broadcast
)
682 if (irq
->dest_mode
== 0) { /* physical mode */
683 if (irq
->delivery_mode
== APIC_DM_LOWEST
)
685 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
687 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
689 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
691 bitmap
= apic_logical_id(map
, mda
);
693 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
695 for_each_set_bit(i
, &bitmap
, 16) {
700 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
704 bitmap
= (l
>= 0) ? 1 << l
: 0;
708 for_each_set_bit(i
, &bitmap
, 16) {
713 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
723 * Add a pending IRQ into lapic.
724 * Return 1 if successfully added and 0 if discarded.
726 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
727 int vector
, int level
, int trig_mode
,
728 unsigned long *dest_map
)
731 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
733 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
735 switch (delivery_mode
) {
737 vcpu
->arch
.apic_arb_prio
++;
739 /* FIXME add logic for vcpu on reset */
740 if (unlikely(!apic_enabled(apic
)))
746 __set_bit(vcpu
->vcpu_id
, dest_map
);
748 if (kvm_x86_ops
->deliver_posted_interrupt
)
749 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
751 apic_set_irr(vector
, apic
);
753 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
760 vcpu
->arch
.pv
.pv_unhalted
= 1;
761 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
766 apic_debug("Ignoring guest SMI\n");
771 kvm_inject_nmi(vcpu
);
776 if (!trig_mode
|| level
) {
778 /* assumes that there are only KVM_APIC_INIT/SIPI */
779 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
780 /* make sure pending_events is visible before sending
783 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
786 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
791 case APIC_DM_STARTUP
:
792 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
793 vcpu
->vcpu_id
, vector
);
795 apic
->sipi_vector
= vector
;
796 /* make sure sipi_vector is visible for the receiver */
798 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
799 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
805 * Should only be called by kvm_apic_local_deliver() with LVT0,
806 * before NMI watchdog was enabled. Already handled by
807 * kvm_apic_accept_pic_intr().
812 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
819 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
821 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
824 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
826 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
827 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
829 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
830 trigger_mode
= IOAPIC_LEVEL_TRIG
;
832 trigger_mode
= IOAPIC_EDGE_TRIG
;
833 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
837 static int apic_set_eoi(struct kvm_lapic
*apic
)
839 int vector
= apic_find_highest_isr(apic
);
841 trace_kvm_eoi(apic
, vector
);
844 * Not every write EOI will has corresponding ISR,
845 * one example is when Kernel check timer on setup_IO_APIC
850 apic_clear_isr(vector
, apic
);
851 apic_update_ppr(apic
);
853 kvm_ioapic_send_eoi(apic
, vector
);
854 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
859 * this interface assumes a trap-like exit, which has already finished
860 * desired side effect including vISR and vPPR update.
862 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
864 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
866 trace_kvm_eoi(apic
, vector
);
868 kvm_ioapic_send_eoi(apic
, vector
);
869 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
871 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
873 static void apic_send_ipi(struct kvm_lapic
*apic
)
875 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
876 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
877 struct kvm_lapic_irq irq
;
879 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
880 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
881 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
882 irq
.level
= icr_low
& APIC_INT_ASSERT
;
883 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
884 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
885 if (apic_x2apic_mode(apic
))
886 irq
.dest_id
= icr_high
;
888 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
890 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
892 apic_debug("icr_high 0x%x, icr_low 0x%x, "
893 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
894 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
895 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
896 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
899 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
902 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
908 ASSERT(apic
!= NULL
);
910 /* if initial count is 0, current count should also be 0 */
911 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
912 apic
->lapic_timer
.period
== 0)
915 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
916 if (ktime_to_ns(remaining
) < 0)
917 remaining
= ktime_set(0, 0);
919 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
920 tmcct
= div64_u64(ns
,
921 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
926 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
928 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
929 struct kvm_run
*run
= vcpu
->run
;
931 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
932 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
933 run
->tpr_access
.is_write
= write
;
936 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
938 if (apic
->vcpu
->arch
.tpr_access_reporting
)
939 __report_tpr_access(apic
, write
);
942 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
946 if (offset
>= LAPIC_MMIO_LENGTH
)
951 if (apic_x2apic_mode(apic
))
952 val
= kvm_apic_id(apic
);
954 val
= kvm_apic_id(apic
) << 24;
957 apic_debug("Access APIC ARBPRI register which is for P6\n");
960 case APIC_TMCCT
: /* Timer CCR */
961 if (apic_lvtt_tscdeadline(apic
))
964 val
= apic_get_tmcct(apic
);
967 apic_update_ppr(apic
);
968 val
= kvm_apic_get_reg(apic
, offset
);
971 report_tpr_access(apic
, false);
974 val
= kvm_apic_get_reg(apic
, offset
);
981 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
983 return container_of(dev
, struct kvm_lapic
, dev
);
986 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
989 unsigned char alignment
= offset
& 0xf;
991 /* this bitmask has a bit cleared for each reserved register */
992 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
994 if ((alignment
+ len
) > 4) {
995 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1000 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1001 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1006 result
= __apic_read(apic
, offset
& ~0xf);
1008 trace_kvm_apic_read(offset
, result
);
1014 memcpy(data
, (char *)&result
+ alignment
, len
);
1017 printk(KERN_ERR
"Local APIC read with len = %x, "
1018 "should be 1,2, or 4 instead\n", len
);
1024 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1026 return kvm_apic_hw_enabled(apic
) &&
1027 addr
>= apic
->base_address
&&
1028 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1031 static int apic_mmio_read(struct kvm_io_device
*this,
1032 gpa_t address
, int len
, void *data
)
1034 struct kvm_lapic
*apic
= to_lapic(this);
1035 u32 offset
= address
- apic
->base_address
;
1037 if (!apic_mmio_in_range(apic
, address
))
1040 apic_reg_read(apic
, offset
, len
, data
);
1045 static void update_divide_count(struct kvm_lapic
*apic
)
1047 u32 tmp1
, tmp2
, tdcr
;
1049 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1051 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1052 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1054 apic_debug("timer divide count is 0x%x\n",
1055 apic
->divide_count
);
1058 static void apic_timer_expired(struct kvm_lapic
*apic
)
1060 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1061 wait_queue_head_t
*q
= &vcpu
->wq
;
1064 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1067 if (atomic_read(&apic
->lapic_timer
.pending
))
1070 atomic_inc(&apic
->lapic_timer
.pending
);
1071 /* FIXME: this code should not know anything about vcpus */
1072 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1074 if (waitqueue_active(q
))
1075 wake_up_interruptible(q
);
1078 static void start_apic_timer(struct kvm_lapic
*apic
)
1081 atomic_set(&apic
->lapic_timer
.pending
, 0);
1083 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1084 /* lapic timer in oneshot or periodic mode */
1085 now
= apic
->lapic_timer
.timer
.base
->get_time();
1086 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1087 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1089 if (!apic
->lapic_timer
.period
)
1092 * Do not allow the guest to program periodic timers with small
1093 * interval, since the hrtimers are not throttled by the host
1096 if (apic_lvtt_period(apic
)) {
1097 s64 min_period
= min_timer_period_us
* 1000LL;
1099 if (apic
->lapic_timer
.period
< min_period
) {
1100 pr_info_ratelimited(
1101 "kvm: vcpu %i: requested %lld ns "
1102 "lapic timer period limited to %lld ns\n",
1103 apic
->vcpu
->vcpu_id
,
1104 apic
->lapic_timer
.period
, min_period
);
1105 apic
->lapic_timer
.period
= min_period
;
1109 hrtimer_start(&apic
->lapic_timer
.timer
,
1110 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1113 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1115 "timer initial count 0x%x, period %lldns, "
1116 "expire @ 0x%016" PRIx64
".\n", __func__
,
1117 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1118 kvm_apic_get_reg(apic
, APIC_TMICT
),
1119 apic
->lapic_timer
.period
,
1120 ktime_to_ns(ktime_add_ns(now
,
1121 apic
->lapic_timer
.period
)));
1122 } else if (apic_lvtt_tscdeadline(apic
)) {
1123 /* lapic timer in tsc deadline mode */
1124 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1126 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1127 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1128 unsigned long flags
;
1130 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1133 local_irq_save(flags
);
1135 now
= apic
->lapic_timer
.timer
.base
->get_time();
1136 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1137 if (likely(tscdeadline
> guest_tsc
)) {
1138 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1139 do_div(ns
, this_tsc_khz
);
1140 hrtimer_start(&apic
->lapic_timer
.timer
,
1141 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1143 apic_timer_expired(apic
);
1145 local_irq_restore(flags
);
1149 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1151 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1153 if (apic_lvt_nmi_mode(lvt0_val
)) {
1154 if (!nmi_wd_enabled
) {
1155 apic_debug("Receive NMI setting on APIC_LVT0 "
1156 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1157 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1159 } else if (nmi_wd_enabled
)
1160 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1163 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1167 trace_kvm_apic_write(reg
, val
);
1170 case APIC_ID
: /* Local APIC ID */
1171 if (!apic_x2apic_mode(apic
))
1172 kvm_apic_set_id(apic
, val
>> 24);
1178 report_tpr_access(apic
, true);
1179 apic_set_tpr(apic
, val
& 0xff);
1187 if (!apic_x2apic_mode(apic
))
1188 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1194 if (!apic_x2apic_mode(apic
)) {
1195 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1196 recalculate_apic_map(apic
->vcpu
->kvm
);
1203 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1204 mask
|= APIC_SPIV_DIRECTED_EOI
;
1205 apic_set_spiv(apic
, val
& mask
);
1206 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1210 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1211 lvt_val
= kvm_apic_get_reg(apic
,
1212 APIC_LVTT
+ 0x10 * i
);
1213 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1214 lvt_val
| APIC_LVT_MASKED
);
1216 atomic_set(&apic
->lapic_timer
.pending
, 0);
1222 /* No delay here, so we always clear the pending bit */
1223 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1224 apic_send_ipi(apic
);
1228 if (!apic_x2apic_mode(apic
))
1230 apic_set_reg(apic
, APIC_ICR2
, val
);
1234 apic_manage_nmi_watchdog(apic
, val
);
1239 /* TODO: Check vector */
1240 if (!kvm_apic_sw_enabled(apic
))
1241 val
|= APIC_LVT_MASKED
;
1243 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1244 apic_set_reg(apic
, reg
, val
);
1249 u32 timer_mode
= val
& apic
->lapic_timer
.timer_mode_mask
;
1251 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1252 apic
->lapic_timer
.timer_mode
= timer_mode
;
1253 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1256 if (!kvm_apic_sw_enabled(apic
))
1257 val
|= APIC_LVT_MASKED
;
1258 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1259 apic_set_reg(apic
, APIC_LVTT
, val
);
1264 if (apic_lvtt_tscdeadline(apic
))
1267 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1268 apic_set_reg(apic
, APIC_TMICT
, val
);
1269 start_apic_timer(apic
);
1274 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1275 apic_set_reg(apic
, APIC_TDCR
, val
);
1276 update_divide_count(apic
);
1280 if (apic_x2apic_mode(apic
) && val
!= 0) {
1281 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1287 if (apic_x2apic_mode(apic
)) {
1288 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1297 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1301 static int apic_mmio_write(struct kvm_io_device
*this,
1302 gpa_t address
, int len
, const void *data
)
1304 struct kvm_lapic
*apic
= to_lapic(this);
1305 unsigned int offset
= address
- apic
->base_address
;
1308 if (!apic_mmio_in_range(apic
, address
))
1312 * APIC register must be aligned on 128-bits boundary.
1313 * 32/64/128 bits registers must be accessed thru 32 bits.
1316 if (len
!= 4 || (offset
& 0xf)) {
1317 /* Don't shout loud, $infamous_os would cause only noise. */
1318 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1324 /* too common printing */
1325 if (offset
!= APIC_EOI
)
1326 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1327 "0x%x\n", __func__
, offset
, len
, val
);
1329 apic_reg_write(apic
, offset
& 0xff0, val
);
1334 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1336 if (kvm_vcpu_has_lapic(vcpu
))
1337 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1339 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1341 /* emulate APIC access in a trap manner */
1342 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1346 /* hw has done the conditional check and inst decode */
1349 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1351 /* TODO: optimize to just emulate side effect w/o one more write */
1352 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1354 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1356 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1358 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1360 if (!vcpu
->arch
.apic
)
1363 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1365 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1366 static_key_slow_dec_deferred(&apic_hw_disabled
);
1368 if (!apic
->sw_enabled
)
1369 static_key_slow_dec_deferred(&apic_sw_disabled
);
1372 free_page((unsigned long)apic
->regs
);
1378 *----------------------------------------------------------------------
1380 *----------------------------------------------------------------------
1383 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1385 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1387 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1388 apic_lvtt_period(apic
))
1391 return apic
->lapic_timer
.tscdeadline
;
1394 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1396 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1398 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1399 apic_lvtt_period(apic
))
1402 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1403 apic
->lapic_timer
.tscdeadline
= data
;
1404 start_apic_timer(apic
);
1407 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1409 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1411 if (!kvm_vcpu_has_lapic(vcpu
))
1414 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1415 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1418 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1422 if (!kvm_vcpu_has_lapic(vcpu
))
1425 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1427 return (tpr
& 0xf0) >> 4;
1430 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1432 u64 old_value
= vcpu
->arch
.apic_base
;
1433 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1436 value
|= MSR_IA32_APICBASE_BSP
;
1437 vcpu
->arch
.apic_base
= value
;
1441 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1442 value
&= ~MSR_IA32_APICBASE_BSP
;
1443 vcpu
->arch
.apic_base
= value
;
1445 /* update jump label if enable bit changes */
1446 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1447 if (value
& MSR_IA32_APICBASE_ENABLE
)
1448 static_key_slow_dec_deferred(&apic_hw_disabled
);
1450 static_key_slow_inc(&apic_hw_disabled
.key
);
1451 recalculate_apic_map(vcpu
->kvm
);
1454 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1455 if (value
& X2APIC_ENABLE
) {
1456 u32 id
= kvm_apic_id(apic
);
1457 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1458 kvm_apic_set_ldr(apic
, ldr
);
1459 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1461 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1464 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1465 MSR_IA32_APICBASE_BASE
;
1467 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1468 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1469 pr_warn_once("APIC base relocation is unsupported by KVM");
1471 /* with FSB delivery interrupt, we can restart APIC functionality */
1472 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1473 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1477 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1479 struct kvm_lapic
*apic
;
1482 apic_debug("%s\n", __func__
);
1485 apic
= vcpu
->arch
.apic
;
1486 ASSERT(apic
!= NULL
);
1488 /* Stop the timer in case it's a reset to an active apic */
1489 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1491 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1492 kvm_apic_set_version(apic
->vcpu
);
1494 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1495 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1496 apic
->lapic_timer
.timer_mode
= 0;
1497 apic_set_reg(apic
, APIC_LVT0
,
1498 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1500 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1501 apic_set_spiv(apic
, 0xff);
1502 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1503 kvm_apic_set_ldr(apic
, 0);
1504 apic_set_reg(apic
, APIC_ESR
, 0);
1505 apic_set_reg(apic
, APIC_ICR
, 0);
1506 apic_set_reg(apic
, APIC_ICR2
, 0);
1507 apic_set_reg(apic
, APIC_TDCR
, 0);
1508 apic_set_reg(apic
, APIC_TMICT
, 0);
1509 for (i
= 0; i
< 8; i
++) {
1510 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1511 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1512 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1514 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1515 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1516 apic
->highest_isr_cache
= -1;
1517 update_divide_count(apic
);
1518 atomic_set(&apic
->lapic_timer
.pending
, 0);
1519 if (kvm_vcpu_is_bsp(vcpu
))
1520 kvm_lapic_set_base(vcpu
,
1521 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1522 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1523 apic_update_ppr(apic
);
1525 vcpu
->arch
.apic_arb_prio
= 0;
1526 vcpu
->arch
.apic_attention
= 0;
1528 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1529 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1530 vcpu
, kvm_apic_id(apic
),
1531 vcpu
->arch
.apic_base
, apic
->base_address
);
1535 *----------------------------------------------------------------------
1537 *----------------------------------------------------------------------
1540 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1542 return apic_lvtt_period(apic
);
1545 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1547 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1549 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1550 apic_lvt_enabled(apic
, APIC_LVTT
))
1551 return atomic_read(&apic
->lapic_timer
.pending
);
1556 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1558 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1559 int vector
, mode
, trig_mode
;
1561 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1562 vector
= reg
& APIC_VECTOR_MASK
;
1563 mode
= reg
& APIC_MODE_MASK
;
1564 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1565 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1571 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1573 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1576 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1579 static const struct kvm_io_device_ops apic_mmio_ops
= {
1580 .read
= apic_mmio_read
,
1581 .write
= apic_mmio_write
,
1584 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1586 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1587 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1589 apic_timer_expired(apic
);
1591 if (lapic_is_periodic(apic
)) {
1592 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1593 return HRTIMER_RESTART
;
1595 return HRTIMER_NORESTART
;
1598 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1600 struct kvm_lapic
*apic
;
1602 ASSERT(vcpu
!= NULL
);
1603 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1605 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1609 vcpu
->arch
.apic
= apic
;
1611 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1613 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1615 goto nomem_free_apic
;
1619 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1621 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1624 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1625 * thinking that APIC satet has changed.
1627 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1628 kvm_lapic_set_base(vcpu
,
1629 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1631 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1632 kvm_lapic_reset(vcpu
);
1633 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1642 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1644 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1647 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1650 apic_update_ppr(apic
);
1651 highest_irr
= apic_find_highest_irr(apic
);
1652 if ((highest_irr
== -1) ||
1653 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1658 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1660 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1663 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1665 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1666 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1671 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1673 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1675 if (!kvm_vcpu_has_lapic(vcpu
))
1678 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1679 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1680 if (apic_lvtt_tscdeadline(apic
))
1681 apic
->lapic_timer
.tscdeadline
= 0;
1682 atomic_set(&apic
->lapic_timer
.pending
, 0);
1686 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1688 int vector
= kvm_apic_has_interrupt(vcpu
);
1689 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1695 * We get here even with APIC virtualization enabled, if doing
1696 * nested virtualization and L1 runs with the "acknowledge interrupt
1697 * on exit" mode. Then we cannot inject the interrupt via RVI,
1698 * because the process would deliver it through the IDT.
1701 apic_set_isr(vector
, apic
);
1702 apic_update_ppr(apic
);
1703 apic_clear_irr(vector
, apic
);
1707 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1708 struct kvm_lapic_state
*s
)
1710 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1712 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1713 /* set SPIV separately to get count of SW disabled APICs right */
1714 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1715 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1716 /* call kvm_apic_set_id() to put apic into apic_map */
1717 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1718 kvm_apic_set_version(vcpu
);
1720 apic_update_ppr(apic
);
1721 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1722 update_divide_count(apic
);
1723 start_apic_timer(apic
);
1724 apic
->irr_pending
= true;
1725 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1726 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1727 apic
->highest_isr_cache
= -1;
1728 if (kvm_x86_ops
->hwapic_irr_update
)
1729 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1730 apic_find_highest_irr(apic
));
1731 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1732 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1733 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1736 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1738 struct hrtimer
*timer
;
1740 if (!kvm_vcpu_has_lapic(vcpu
))
1743 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1744 if (hrtimer_cancel(timer
))
1745 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1749 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1751 * Detect whether guest triggered PV EOI since the
1752 * last entry. If yes, set EOI on guests's behalf.
1753 * Clear PV EOI in guest memory in any case.
1755 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1756 struct kvm_lapic
*apic
)
1761 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1762 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1764 * KVM_APIC_PV_EOI_PENDING is unset:
1765 * -> host disabled PV EOI.
1766 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1767 * -> host enabled PV EOI, guest did not execute EOI yet.
1768 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1769 * -> host enabled PV EOI, guest executed EOI.
1771 BUG_ON(!pv_eoi_enabled(vcpu
));
1772 pending
= pv_eoi_get_pending(vcpu
);
1774 * Clear pending bit in any case: it will be set again on vmentry.
1775 * While this might not be ideal from performance point of view,
1776 * this makes sure pv eoi is only enabled when we know it's safe.
1778 pv_eoi_clr_pending(vcpu
);
1781 vector
= apic_set_eoi(apic
);
1782 trace_kvm_pv_eoi(apic
, vector
);
1785 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1789 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1790 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1792 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1795 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1798 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1802 * apic_sync_pv_eoi_to_guest - called before vmentry
1804 * Detect whether it's safe to enable PV EOI and
1807 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1808 struct kvm_lapic
*apic
)
1810 if (!pv_eoi_enabled(vcpu
) ||
1811 /* IRR set or many bits in ISR: could be nested. */
1812 apic
->irr_pending
||
1813 /* Cache not set: could be safe but we don't bother. */
1814 apic
->highest_isr_cache
== -1 ||
1815 /* Need EOI to update ioapic. */
1816 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1818 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1819 * so we need not do anything here.
1824 pv_eoi_set_pending(apic
->vcpu
);
1827 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1830 int max_irr
, max_isr
;
1831 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1833 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1835 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1838 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1839 max_irr
= apic_find_highest_irr(apic
);
1842 max_isr
= apic_find_highest_isr(apic
);
1845 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1847 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1851 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1854 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1855 &vcpu
->arch
.apic
->vapic_cache
,
1856 vapic_addr
, sizeof(u32
)))
1858 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1860 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1863 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1867 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1869 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1870 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1872 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1875 /* if this is ICR write vector before command */
1877 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1878 return apic_reg_write(apic
, reg
, (u32
)data
);
1881 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1883 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1884 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1886 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1889 if (apic_reg_read(apic
, reg
, 4, &low
))
1892 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1894 *data
= (((u64
)high
) << 32) | low
;
1899 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1901 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1903 if (!kvm_vcpu_has_lapic(vcpu
))
1906 /* if this is ICR write vector before command */
1907 if (reg
== APIC_ICR
)
1908 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1909 return apic_reg_write(apic
, reg
, (u32
)data
);
1912 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1914 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1917 if (!kvm_vcpu_has_lapic(vcpu
))
1920 if (apic_reg_read(apic
, reg
, 4, &low
))
1922 if (reg
== APIC_ICR
)
1923 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1925 *data
= (((u64
)high
) << 32) | low
;
1930 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1932 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1933 if (!IS_ALIGNED(addr
, 4))
1936 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1937 if (!pv_eoi_enabled(vcpu
))
1939 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1943 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1945 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1946 unsigned int sipi_vector
;
1949 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
1952 pe
= xchg(&apic
->pending_events
, 0);
1954 if (test_bit(KVM_APIC_INIT
, &pe
)) {
1955 kvm_lapic_reset(vcpu
);
1956 kvm_vcpu_reset(vcpu
);
1957 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1958 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1960 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1962 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
1963 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1964 /* evaluate pending_events before reading the vector */
1966 sipi_vector
= apic
->sipi_vector
;
1967 apic_debug("vcpu %d received sipi with vector # %x\n",
1968 vcpu
->vcpu_id
, sipi_vector
);
1969 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1970 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1974 void kvm_lapic_init(void)
1976 /* do not patch jump label more than once per second */
1977 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1978 jump_label_rate_limit(&apic_sw_disabled
, HZ
);