arch/x86/kvm/lapic.h

   1 #ifndef __KVM_X86_LAPIC_H
   2 #define __KVM_X86_LAPIC_H
   3
   4 #include "iodev.h"
   5
   6 #include <linux/kvm_host.h>
   7
   8 struct kvm_timer {
   9         struct hrtimer timer;
  10         s64 period;                             /* unit: ns */
  11         u32 timer_mode_mask;
  12         u64 tscdeadline;
  13         atomic_t pending;                       /* accumulated triggered timers */
  14         bool reinject;
  15         struct kvm_timer_ops *t_ops;
  16         struct kvm *kvm;
  17         struct kvm_vcpu *vcpu;
  18 };
  19
  20 struct kvm_timer_ops {
  21         bool (*is_periodic)(struct kvm_timer *);
  22 };
  23
  24 struct kvm_lapic {
  25         unsigned long base_address;
  26         struct kvm_io_device dev;
  27         struct kvm_timer lapic_timer;
  28         u32 divide_count;
  29         struct kvm_vcpu *vcpu;
  30         bool irr_pending;
  31         /* Number of bits set in ISR. */
  32         s16 isr_count;
  33         /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
  34         int highest_isr_cache;
  35         /**
  36          * APIC register page.  The layout matches the register layout seen by
  37          * the guest 1:1, because it is accessed by the vmx microcode.
  38          * Note: Only one register, the TPR, is used by the microcode.
  39          */
  40         void *regs;
  41         gpa_t vapic_addr;
  42         struct page *vapic_page;
  43 };
  44 int kvm_create_lapic(struct kvm_vcpu *vcpu);
  45 void kvm_free_lapic(struct kvm_vcpu *vcpu);
  46
  47 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
  48 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
  49 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
  50 void kvm_lapic_reset(struct kvm_vcpu *vcpu);
  51 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
  52 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
  53 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
  54 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
  55 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
  56 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
  57
  58 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
  59 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
  60 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
  61 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
  62
  63 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
  64 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
  65 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
  66 int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
  67 bool kvm_apic_present(struct kvm_vcpu *vcpu);
  68 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
  69
  70 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
  71 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
  72
  73 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
  74 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
  75 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
  76
  77 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
  78 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
  79
  80 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
  81 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
  82
  83 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
  84 {
  85         return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
  86 }
  87
  88 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
  89 #endif