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KVM: MMU: remove kvm_mmu_set_base_ptes
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
30 #include <linux/mm.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39
40 #include <asm/page.h>
41 #include <asm/cmpxchg.h>
42 #include <asm/io.h>
43 #include <asm/vmx.h>
44
45 /*
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
51 */
52 bool tdp_enabled = false;
53
54 enum {
55 AUDIT_PRE_PAGE_FAULT,
56 AUDIT_POST_PAGE_FAULT,
57 AUDIT_PRE_PTE_WRITE,
58 AUDIT_POST_PTE_WRITE,
59 AUDIT_PRE_SYNC,
60 AUDIT_POST_SYNC
61 };
62
63 char *audit_point_name[] = {
64 "pre page fault",
65 "post page fault",
66 "pre pte write",
67 "post pte write",
68 "pre sync",
69 "post sync"
70 };
71
72 #undef MMU_DEBUG
73
74 #ifdef MMU_DEBUG
75
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78
79 #else
80
81 #define pgprintk(x...) do { } while (0)
82 #define rmap_printk(x...) do { } while (0)
83
84 #endif
85
86 #ifdef MMU_DEBUG
87 static int dbg = 0;
88 module_param(dbg, bool, 0644);
89 #endif
90
91 static int oos_shadow = 1;
92 module_param(oos_shadow, bool, 0644);
93
94 #ifndef MMU_DEBUG
95 #define ASSERT(x) do { } while (0)
96 #else
97 #define ASSERT(x) \
98 if (!(x)) { \
99 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
100 __FILE__, __LINE__, #x); \
101 }
102 #endif
103
104 #define PTE_PREFETCH_NUM 8
105
106 #define PT_FIRST_AVAIL_BITS_SHIFT 9
107 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
108
109 #define PT64_LEVEL_BITS 9
110
111 #define PT64_LEVEL_SHIFT(level) \
112 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
113
114 #define PT64_LEVEL_MASK(level) \
115 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
116
117 #define PT64_INDEX(address, level)\
118 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
119
120
121 #define PT32_LEVEL_BITS 10
122
123 #define PT32_LEVEL_SHIFT(level) \
124 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
125
126 #define PT32_LEVEL_MASK(level) \
127 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
128 #define PT32_LVL_OFFSET_MASK(level) \
129 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT32_LEVEL_BITS))) - 1))
131
132 #define PT32_INDEX(address, level)\
133 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
134
135
136 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
137 #define PT64_DIR_BASE_ADDR_MASK \
138 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
139 #define PT64_LVL_ADDR_MASK(level) \
140 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
141 * PT64_LEVEL_BITS))) - 1))
142 #define PT64_LVL_OFFSET_MASK(level) \
143 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
144 * PT64_LEVEL_BITS))) - 1))
145
146 #define PT32_BASE_ADDR_MASK PAGE_MASK
147 #define PT32_DIR_BASE_ADDR_MASK \
148 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
149 #define PT32_LVL_ADDR_MASK(level) \
150 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
151 * PT32_LEVEL_BITS))) - 1))
152
153 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
154 | PT64_NX_MASK)
155
156 #define RMAP_EXT 4
157
158 #define ACC_EXEC_MASK 1
159 #define ACC_WRITE_MASK PT_WRITABLE_MASK
160 #define ACC_USER_MASK PT_USER_MASK
161 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
162
163 #include <trace/events/kvm.h>
164
165 #define CREATE_TRACE_POINTS
166 #include "mmutrace.h"
167
168 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
169
170 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
171
172 struct kvm_rmap_desc {
173 u64 *sptes[RMAP_EXT];
174 struct kvm_rmap_desc *more;
175 };
176
177 struct kvm_shadow_walk_iterator {
178 u64 addr;
179 hpa_t shadow_addr;
180 int level;
181 u64 *sptep;
182 unsigned index;
183 };
184
185 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
186 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
187 shadow_walk_okay(&(_walker)); \
188 shadow_walk_next(&(_walker)))
189
190 typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte);
191
192 static struct kmem_cache *pte_chain_cache;
193 static struct kmem_cache *rmap_desc_cache;
194 static struct kmem_cache *mmu_page_header_cache;
195 static struct percpu_counter kvm_total_used_mmu_pages;
196
197 static u64 __read_mostly shadow_trap_nonpresent_pte;
198 static u64 __read_mostly shadow_notrap_nonpresent_pte;
199 static u64 __read_mostly shadow_nx_mask;
200 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
201 static u64 __read_mostly shadow_user_mask;
202 static u64 __read_mostly shadow_accessed_mask;
203 static u64 __read_mostly shadow_dirty_mask;
204
205 static inline u64 rsvd_bits(int s, int e)
206 {
207 return ((1ULL << (e - s + 1)) - 1) << s;
208 }
209
210 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
211 {
212 shadow_trap_nonpresent_pte = trap_pte;
213 shadow_notrap_nonpresent_pte = notrap_pte;
214 }
215 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
216
217 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
218 u64 dirty_mask, u64 nx_mask, u64 x_mask)
219 {
220 shadow_user_mask = user_mask;
221 shadow_accessed_mask = accessed_mask;
222 shadow_dirty_mask = dirty_mask;
223 shadow_nx_mask = nx_mask;
224 shadow_x_mask = x_mask;
225 }
226 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
227
228 static bool is_write_protection(struct kvm_vcpu *vcpu)
229 {
230 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
231 }
232
233 static int is_cpuid_PSE36(void)
234 {
235 return 1;
236 }
237
238 static int is_nx(struct kvm_vcpu *vcpu)
239 {
240 return vcpu->arch.efer & EFER_NX;
241 }
242
243 static int is_shadow_present_pte(u64 pte)
244 {
245 return pte != shadow_trap_nonpresent_pte
246 && pte != shadow_notrap_nonpresent_pte;
247 }
248
249 static int is_large_pte(u64 pte)
250 {
251 return pte & PT_PAGE_SIZE_MASK;
252 }
253
254 static int is_writable_pte(unsigned long pte)
255 {
256 return pte & PT_WRITABLE_MASK;
257 }
258
259 static int is_dirty_gpte(unsigned long pte)
260 {
261 return pte & PT_DIRTY_MASK;
262 }
263
264 static int is_rmap_spte(u64 pte)
265 {
266 return is_shadow_present_pte(pte);
267 }
268
269 static int is_last_spte(u64 pte, int level)
270 {
271 if (level == PT_PAGE_TABLE_LEVEL)
272 return 1;
273 if (is_large_pte(pte))
274 return 1;
275 return 0;
276 }
277
278 static pfn_t spte_to_pfn(u64 pte)
279 {
280 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
281 }
282
283 static gfn_t pse36_gfn_delta(u32 gpte)
284 {
285 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
286
287 return (gpte & PT32_DIR_PSE36_MASK) << shift;
288 }
289
290 static void __set_spte(u64 *sptep, u64 spte)
291 {
292 set_64bit(sptep, spte);
293 }
294
295 static u64 __xchg_spte(u64 *sptep, u64 new_spte)
296 {
297 #ifdef CONFIG_X86_64
298 return xchg(sptep, new_spte);
299 #else
300 u64 old_spte;
301
302 do {
303 old_spte = *sptep;
304 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
305
306 return old_spte;
307 #endif
308 }
309
310 static bool spte_has_volatile_bits(u64 spte)
311 {
312 if (!shadow_accessed_mask)
313 return false;
314
315 if (!is_shadow_present_pte(spte))
316 return false;
317
318 if ((spte & shadow_accessed_mask) &&
319 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
320 return false;
321
322 return true;
323 }
324
325 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
326 {
327 return (old_spte & bit_mask) && !(new_spte & bit_mask);
328 }
329
330 static void update_spte(u64 *sptep, u64 new_spte)
331 {
332 u64 mask, old_spte = *sptep;
333
334 WARN_ON(!is_rmap_spte(new_spte));
335
336 new_spte |= old_spte & shadow_dirty_mask;
337
338 mask = shadow_accessed_mask;
339 if (is_writable_pte(old_spte))
340 mask |= shadow_dirty_mask;
341
342 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
343 __set_spte(sptep, new_spte);
344 else
345 old_spte = __xchg_spte(sptep, new_spte);
346
347 if (!shadow_accessed_mask)
348 return;
349
350 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
351 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
352 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
353 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
354 }
355
356 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
357 struct kmem_cache *base_cache, int min)
358 {
359 void *obj;
360
361 if (cache->nobjs >= min)
362 return 0;
363 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
364 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
365 if (!obj)
366 return -ENOMEM;
367 cache->objects[cache->nobjs++] = obj;
368 }
369 return 0;
370 }
371
372 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
373 struct kmem_cache *cache)
374 {
375 while (mc->nobjs)
376 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
377 }
378
379 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
380 int min)
381 {
382 struct page *page;
383
384 if (cache->nobjs >= min)
385 return 0;
386 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
387 page = alloc_page(GFP_KERNEL);
388 if (!page)
389 return -ENOMEM;
390 cache->objects[cache->nobjs++] = page_address(page);
391 }
392 return 0;
393 }
394
395 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
396 {
397 while (mc->nobjs)
398 free_page((unsigned long)mc->objects[--mc->nobjs]);
399 }
400
401 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
402 {
403 int r;
404
405 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
406 pte_chain_cache, 4);
407 if (r)
408 goto out;
409 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
410 rmap_desc_cache, 4 + PTE_PREFETCH_NUM);
411 if (r)
412 goto out;
413 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
414 if (r)
415 goto out;
416 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
417 mmu_page_header_cache, 4);
418 out:
419 return r;
420 }
421
422 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
423 {
424 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
425 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
426 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
427 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
428 mmu_page_header_cache);
429 }
430
431 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
432 size_t size)
433 {
434 void *p;
435
436 BUG_ON(!mc->nobjs);
437 p = mc->objects[--mc->nobjs];
438 return p;
439 }
440
441 static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
442 {
443 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
444 sizeof(struct kvm_pte_chain));
445 }
446
447 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
448 {
449 kmem_cache_free(pte_chain_cache, pc);
450 }
451
452 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
453 {
454 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
455 sizeof(struct kvm_rmap_desc));
456 }
457
458 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
459 {
460 kmem_cache_free(rmap_desc_cache, rd);
461 }
462
463 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
464 {
465 if (!sp->role.direct)
466 return sp->gfns[index];
467
468 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
469 }
470
471 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
472 {
473 if (sp->role.direct)
474 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
475 else
476 sp->gfns[index] = gfn;
477 }
478
479 /*
480 * Return the pointer to the largepage write count for a given
481 * gfn, handling slots that are not large page aligned.
482 */
483 static int *slot_largepage_idx(gfn_t gfn,
484 struct kvm_memory_slot *slot,
485 int level)
486 {
487 unsigned long idx;
488
489 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
490 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
491 return &slot->lpage_info[level - 2][idx].write_count;
492 }
493
494 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
495 {
496 struct kvm_memory_slot *slot;
497 int *write_count;
498 int i;
499
500 slot = gfn_to_memslot(kvm, gfn);
501 for (i = PT_DIRECTORY_LEVEL;
502 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
503 write_count = slot_largepage_idx(gfn, slot, i);
504 *write_count += 1;
505 }
506 }
507
508 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
509 {
510 struct kvm_memory_slot *slot;
511 int *write_count;
512 int i;
513
514 slot = gfn_to_memslot(kvm, gfn);
515 for (i = PT_DIRECTORY_LEVEL;
516 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
517 write_count = slot_largepage_idx(gfn, slot, i);
518 *write_count -= 1;
519 WARN_ON(*write_count < 0);
520 }
521 }
522
523 static int has_wrprotected_page(struct kvm *kvm,
524 gfn_t gfn,
525 int level)
526 {
527 struct kvm_memory_slot *slot;
528 int *largepage_idx;
529
530 slot = gfn_to_memslot(kvm, gfn);
531 if (slot) {
532 largepage_idx = slot_largepage_idx(gfn, slot, level);
533 return *largepage_idx;
534 }
535
536 return 1;
537 }
538
539 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
540 {
541 unsigned long page_size;
542 int i, ret = 0;
543
544 page_size = kvm_host_page_size(kvm, gfn);
545
546 for (i = PT_PAGE_TABLE_LEVEL;
547 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
548 if (page_size >= KVM_HPAGE_SIZE(i))
549 ret = i;
550 else
551 break;
552 }
553
554 return ret;
555 }
556
557 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
558 {
559 struct kvm_memory_slot *slot;
560 int host_level, level, max_level;
561
562 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
563 if (slot && slot->dirty_bitmap)
564 return PT_PAGE_TABLE_LEVEL;
565
566 host_level = host_mapping_level(vcpu->kvm, large_gfn);
567
568 if (host_level == PT_PAGE_TABLE_LEVEL)
569 return host_level;
570
571 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
572 kvm_x86_ops->get_lpage_level() : host_level;
573
574 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
575 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
576 break;
577
578 return level - 1;
579 }
580
581 /*
582 * Take gfn and return the reverse mapping to it.
583 */
584
585 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
586 {
587 struct kvm_memory_slot *slot;
588 unsigned long idx;
589
590 slot = gfn_to_memslot(kvm, gfn);
591 if (likely(level == PT_PAGE_TABLE_LEVEL))
592 return &slot->rmap[gfn - slot->base_gfn];
593
594 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
595 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
596
597 return &slot->lpage_info[level - 2][idx].rmap_pde;
598 }
599
600 /*
601 * Reverse mapping data structures:
602 *
603 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
604 * that points to page_address(page).
605 *
606 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
607 * containing more mappings.
608 *
609 * Returns the number of rmap entries before the spte was added or zero if
610 * the spte was not added.
611 *
612 */
613 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
614 {
615 struct kvm_mmu_page *sp;
616 struct kvm_rmap_desc *desc;
617 unsigned long *rmapp;
618 int i, count = 0;
619
620 if (!is_rmap_spte(*spte))
621 return count;
622 sp = page_header(__pa(spte));
623 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
624 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
625 if (!*rmapp) {
626 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
627 *rmapp = (unsigned long)spte;
628 } else if (!(*rmapp & 1)) {
629 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
630 desc = mmu_alloc_rmap_desc(vcpu);
631 desc->sptes[0] = (u64 *)*rmapp;
632 desc->sptes[1] = spte;
633 *rmapp = (unsigned long)desc | 1;
634 ++count;
635 } else {
636 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
637 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
638 while (desc->sptes[RMAP_EXT-1] && desc->more) {
639 desc = desc->more;
640 count += RMAP_EXT;
641 }
642 if (desc->sptes[RMAP_EXT-1]) {
643 desc->more = mmu_alloc_rmap_desc(vcpu);
644 desc = desc->more;
645 }
646 for (i = 0; desc->sptes[i]; ++i)
647 ++count;
648 desc->sptes[i] = spte;
649 }
650 return count;
651 }
652
653 static void rmap_desc_remove_entry(unsigned long *rmapp,
654 struct kvm_rmap_desc *desc,
655 int i,
656 struct kvm_rmap_desc *prev_desc)
657 {
658 int j;
659
660 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
661 ;
662 desc->sptes[i] = desc->sptes[j];
663 desc->sptes[j] = NULL;
664 if (j != 0)
665 return;
666 if (!prev_desc && !desc->more)
667 *rmapp = (unsigned long)desc->sptes[0];
668 else
669 if (prev_desc)
670 prev_desc->more = desc->more;
671 else
672 *rmapp = (unsigned long)desc->more | 1;
673 mmu_free_rmap_desc(desc);
674 }
675
676 static void rmap_remove(struct kvm *kvm, u64 *spte)
677 {
678 struct kvm_rmap_desc *desc;
679 struct kvm_rmap_desc *prev_desc;
680 struct kvm_mmu_page *sp;
681 gfn_t gfn;
682 unsigned long *rmapp;
683 int i;
684
685 sp = page_header(__pa(spte));
686 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
687 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
688 if (!*rmapp) {
689 printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte);
690 BUG();
691 } else if (!(*rmapp & 1)) {
692 rmap_printk("rmap_remove: %p 1->0\n", spte);
693 if ((u64 *)*rmapp != spte) {
694 printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte);
695 BUG();
696 }
697 *rmapp = 0;
698 } else {
699 rmap_printk("rmap_remove: %p many->many\n", spte);
700 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
701 prev_desc = NULL;
702 while (desc) {
703 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
704 if (desc->sptes[i] == spte) {
705 rmap_desc_remove_entry(rmapp,
706 desc, i,
707 prev_desc);
708 return;
709 }
710 prev_desc = desc;
711 desc = desc->more;
712 }
713 pr_err("rmap_remove: %p many->many\n", spte);
714 BUG();
715 }
716 }
717
718 static int set_spte_track_bits(u64 *sptep, u64 new_spte)
719 {
720 pfn_t pfn;
721 u64 old_spte = *sptep;
722
723 if (!spte_has_volatile_bits(old_spte))
724 __set_spte(sptep, new_spte);
725 else
726 old_spte = __xchg_spte(sptep, new_spte);
727
728 if (!is_rmap_spte(old_spte))
729 return 0;
730
731 pfn = spte_to_pfn(old_spte);
732 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
733 kvm_set_pfn_accessed(pfn);
734 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
735 kvm_set_pfn_dirty(pfn);
736 return 1;
737 }
738
739 static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
740 {
741 if (set_spte_track_bits(sptep, new_spte))
742 rmap_remove(kvm, sptep);
743 }
744
745 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
746 {
747 struct kvm_rmap_desc *desc;
748 u64 *prev_spte;
749 int i;
750
751 if (!*rmapp)
752 return NULL;
753 else if (!(*rmapp & 1)) {
754 if (!spte)
755 return (u64 *)*rmapp;
756 return NULL;
757 }
758 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
759 prev_spte = NULL;
760 while (desc) {
761 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
762 if (prev_spte == spte)
763 return desc->sptes[i];
764 prev_spte = desc->sptes[i];
765 }
766 desc = desc->more;
767 }
768 return NULL;
769 }
770
771 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
772 {
773 unsigned long *rmapp;
774 u64 *spte;
775 int i, write_protected = 0;
776
777 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
778
779 spte = rmap_next(kvm, rmapp, NULL);
780 while (spte) {
781 BUG_ON(!spte);
782 BUG_ON(!(*spte & PT_PRESENT_MASK));
783 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
784 if (is_writable_pte(*spte)) {
785 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
786 write_protected = 1;
787 }
788 spte = rmap_next(kvm, rmapp, spte);
789 }
790
791 /* check for huge page mappings */
792 for (i = PT_DIRECTORY_LEVEL;
793 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
794 rmapp = gfn_to_rmap(kvm, gfn, i);
795 spte = rmap_next(kvm, rmapp, NULL);
796 while (spte) {
797 BUG_ON(!spte);
798 BUG_ON(!(*spte & PT_PRESENT_MASK));
799 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
800 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
801 if (is_writable_pte(*spte)) {
802 drop_spte(kvm, spte,
803 shadow_trap_nonpresent_pte);
804 --kvm->stat.lpages;
805 spte = NULL;
806 write_protected = 1;
807 }
808 spte = rmap_next(kvm, rmapp, spte);
809 }
810 }
811
812 return write_protected;
813 }
814
815 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
816 unsigned long data)
817 {
818 u64 *spte;
819 int need_tlb_flush = 0;
820
821 while ((spte = rmap_next(kvm, rmapp, NULL))) {
822 BUG_ON(!(*spte & PT_PRESENT_MASK));
823 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
824 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
825 need_tlb_flush = 1;
826 }
827 return need_tlb_flush;
828 }
829
830 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
831 unsigned long data)
832 {
833 int need_flush = 0;
834 u64 *spte, new_spte;
835 pte_t *ptep = (pte_t *)data;
836 pfn_t new_pfn;
837
838 WARN_ON(pte_huge(*ptep));
839 new_pfn = pte_pfn(*ptep);
840 spte = rmap_next(kvm, rmapp, NULL);
841 while (spte) {
842 BUG_ON(!is_shadow_present_pte(*spte));
843 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
844 need_flush = 1;
845 if (pte_write(*ptep)) {
846 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
847 spte = rmap_next(kvm, rmapp, NULL);
848 } else {
849 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
850 new_spte |= (u64)new_pfn << PAGE_SHIFT;
851
852 new_spte &= ~PT_WRITABLE_MASK;
853 new_spte &= ~SPTE_HOST_WRITEABLE;
854 new_spte &= ~shadow_accessed_mask;
855 set_spte_track_bits(spte, new_spte);
856 spte = rmap_next(kvm, rmapp, spte);
857 }
858 }
859 if (need_flush)
860 kvm_flush_remote_tlbs(kvm);
861
862 return 0;
863 }
864
865 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
866 unsigned long data,
867 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
868 unsigned long data))
869 {
870 int i, j;
871 int ret;
872 int retval = 0;
873 struct kvm_memslots *slots;
874
875 slots = kvm_memslots(kvm);
876
877 for (i = 0; i < slots->nmemslots; i++) {
878 struct kvm_memory_slot *memslot = &slots->memslots[i];
879 unsigned long start = memslot->userspace_addr;
880 unsigned long end;
881
882 end = start + (memslot->npages << PAGE_SHIFT);
883 if (hva >= start && hva < end) {
884 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
885
886 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
887
888 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
889 unsigned long idx;
890 int sh;
891
892 sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j);
893 idx = ((memslot->base_gfn+gfn_offset) >> sh) -
894 (memslot->base_gfn >> sh);
895 ret |= handler(kvm,
896 &memslot->lpage_info[j][idx].rmap_pde,
897 data);
898 }
899 trace_kvm_age_page(hva, memslot, ret);
900 retval |= ret;
901 }
902 }
903
904 return retval;
905 }
906
907 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
908 {
909 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
910 }
911
912 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
913 {
914 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
915 }
916
917 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
918 unsigned long data)
919 {
920 u64 *spte;
921 int young = 0;
922
923 /*
924 * Emulate the accessed bit for EPT, by checking if this page has
925 * an EPT mapping, and clearing it if it does. On the next access,
926 * a new EPT mapping will be established.
927 * This has some overhead, but not as much as the cost of swapping
928 * out actively used pages or breaking up actively used hugepages.
929 */
930 if (!shadow_accessed_mask)
931 return kvm_unmap_rmapp(kvm, rmapp, data);
932
933 spte = rmap_next(kvm, rmapp, NULL);
934 while (spte) {
935 int _young;
936 u64 _spte = *spte;
937 BUG_ON(!(_spte & PT_PRESENT_MASK));
938 _young = _spte & PT_ACCESSED_MASK;
939 if (_young) {
940 young = 1;
941 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
942 }
943 spte = rmap_next(kvm, rmapp, spte);
944 }
945 return young;
946 }
947
948 #define RMAP_RECYCLE_THRESHOLD 1000
949
950 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
951 {
952 unsigned long *rmapp;
953 struct kvm_mmu_page *sp;
954
955 sp = page_header(__pa(spte));
956
957 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
958
959 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
960 kvm_flush_remote_tlbs(vcpu->kvm);
961 }
962
963 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
964 {
965 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
966 }
967
968 #ifdef MMU_DEBUG
969 static int is_empty_shadow_page(u64 *spt)
970 {
971 u64 *pos;
972 u64 *end;
973
974 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
975 if (is_shadow_present_pte(*pos)) {
976 printk(KERN_ERR "%s: %p %llx\n", __func__,
977 pos, *pos);
978 return 0;
979 }
980 return 1;
981 }
982 #endif
983
984 /*
985 * This value is the sum of all of the kvm instances's
986 * kvm->arch.n_used_mmu_pages values. We need a global,
987 * aggregate version in order to make the slab shrinker
988 * faster
989 */
990 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
991 {
992 kvm->arch.n_used_mmu_pages += nr;
993 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
994 }
995
996 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
997 {
998 ASSERT(is_empty_shadow_page(sp->spt));
999 hlist_del(&sp->hash_link);
1000 list_del(&sp->link);
1001 __free_page(virt_to_page(sp->spt));
1002 if (!sp->role.direct)
1003 __free_page(virt_to_page(sp->gfns));
1004 kmem_cache_free(mmu_page_header_cache, sp);
1005 kvm_mod_used_mmu_pages(kvm, -1);
1006 }
1007
1008 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1009 {
1010 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1011 }
1012
1013 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1014 u64 *parent_pte, int direct)
1015 {
1016 struct kvm_mmu_page *sp;
1017
1018 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
1019 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1020 if (!direct)
1021 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1022 PAGE_SIZE);
1023 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1024 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1025 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1026 sp->multimapped = 0;
1027 sp->parent_pte = parent_pte;
1028 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1029 return sp;
1030 }
1031
1032 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1033 struct kvm_mmu_page *sp, u64 *parent_pte)
1034 {
1035 struct kvm_pte_chain *pte_chain;
1036 struct hlist_node *node;
1037 int i;
1038
1039 if (!parent_pte)
1040 return;
1041 if (!sp->multimapped) {
1042 u64 *old = sp->parent_pte;
1043
1044 if (!old) {
1045 sp->parent_pte = parent_pte;
1046 return;
1047 }
1048 sp->multimapped = 1;
1049 pte_chain = mmu_alloc_pte_chain(vcpu);
1050 INIT_HLIST_HEAD(&sp->parent_ptes);
1051 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
1052 pte_chain->parent_ptes[0] = old;
1053 }
1054 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
1055 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
1056 continue;
1057 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
1058 if (!pte_chain->parent_ptes[i]) {
1059 pte_chain->parent_ptes[i] = parent_pte;
1060 return;
1061 }
1062 }
1063 pte_chain = mmu_alloc_pte_chain(vcpu);
1064 BUG_ON(!pte_chain);
1065 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
1066 pte_chain->parent_ptes[0] = parent_pte;
1067 }
1068
1069 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1070 u64 *parent_pte)
1071 {
1072 struct kvm_pte_chain *pte_chain;
1073 struct hlist_node *node;
1074 int i;
1075
1076 if (!sp->multimapped) {
1077 BUG_ON(sp->parent_pte != parent_pte);
1078 sp->parent_pte = NULL;
1079 return;
1080 }
1081 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1082 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1083 if (!pte_chain->parent_ptes[i])
1084 break;
1085 if (pte_chain->parent_ptes[i] != parent_pte)
1086 continue;
1087 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1088 && pte_chain->parent_ptes[i + 1]) {
1089 pte_chain->parent_ptes[i]
1090 = pte_chain->parent_ptes[i + 1];
1091 ++i;
1092 }
1093 pte_chain->parent_ptes[i] = NULL;
1094 if (i == 0) {
1095 hlist_del(&pte_chain->link);
1096 mmu_free_pte_chain(pte_chain);
1097 if (hlist_empty(&sp->parent_ptes)) {
1098 sp->multimapped = 0;
1099 sp->parent_pte = NULL;
1100 }
1101 }
1102 return;
1103 }
1104 BUG();
1105 }
1106
1107 static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
1108 {
1109 struct kvm_pte_chain *pte_chain;
1110 struct hlist_node *node;
1111 struct kvm_mmu_page *parent_sp;
1112 int i;
1113
1114 if (!sp->multimapped && sp->parent_pte) {
1115 parent_sp = page_header(__pa(sp->parent_pte));
1116 fn(parent_sp, sp->parent_pte);
1117 return;
1118 }
1119
1120 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1121 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1122 u64 *spte = pte_chain->parent_ptes[i];
1123
1124 if (!spte)
1125 break;
1126 parent_sp = page_header(__pa(spte));
1127 fn(parent_sp, spte);
1128 }
1129 }
1130
1131 static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte);
1132 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1133 {
1134 mmu_parent_walk(sp, mark_unsync);
1135 }
1136
1137 static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte)
1138 {
1139 unsigned int index;
1140
1141 index = spte - sp->spt;
1142 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1143 return;
1144 if (sp->unsync_children++)
1145 return;
1146 kvm_mmu_mark_parents_unsync(sp);
1147 }
1148
1149 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1150 struct kvm_mmu_page *sp)
1151 {
1152 int i;
1153
1154 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1155 sp->spt[i] = shadow_trap_nonpresent_pte;
1156 }
1157
1158 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1159 struct kvm_mmu_page *sp, bool clear_unsync)
1160 {
1161 return 1;
1162 }
1163
1164 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1165 {
1166 }
1167
1168 #define KVM_PAGE_ARRAY_NR 16
1169
1170 struct kvm_mmu_pages {
1171 struct mmu_page_and_offset {
1172 struct kvm_mmu_page *sp;
1173 unsigned int idx;
1174 } page[KVM_PAGE_ARRAY_NR];
1175 unsigned int nr;
1176 };
1177
1178 #define for_each_unsync_children(bitmap, idx) \
1179 for (idx = find_first_bit(bitmap, 512); \
1180 idx < 512; \
1181 idx = find_next_bit(bitmap, 512, idx+1))
1182
1183 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1184 int idx)
1185 {
1186 int i;
1187
1188 if (sp->unsync)
1189 for (i=0; i < pvec->nr; i++)
1190 if (pvec->page[i].sp == sp)
1191 return 0;
1192
1193 pvec->page[pvec->nr].sp = sp;
1194 pvec->page[pvec->nr].idx = idx;
1195 pvec->nr++;
1196 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1197 }
1198
1199 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1200 struct kvm_mmu_pages *pvec)
1201 {
1202 int i, ret, nr_unsync_leaf = 0;
1203
1204 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1205 struct kvm_mmu_page *child;
1206 u64 ent = sp->spt[i];
1207
1208 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1209 goto clear_child_bitmap;
1210
1211 child = page_header(ent & PT64_BASE_ADDR_MASK);
1212
1213 if (child->unsync_children) {
1214 if (mmu_pages_add(pvec, child, i))
1215 return -ENOSPC;
1216
1217 ret = __mmu_unsync_walk(child, pvec);
1218 if (!ret)
1219 goto clear_child_bitmap;
1220 else if (ret > 0)
1221 nr_unsync_leaf += ret;
1222 else
1223 return ret;
1224 } else if (child->unsync) {
1225 nr_unsync_leaf++;
1226 if (mmu_pages_add(pvec, child, i))
1227 return -ENOSPC;
1228 } else
1229 goto clear_child_bitmap;
1230
1231 continue;
1232
1233 clear_child_bitmap:
1234 __clear_bit(i, sp->unsync_child_bitmap);
1235 sp->unsync_children--;
1236 WARN_ON((int)sp->unsync_children < 0);
1237 }
1238
1239
1240 return nr_unsync_leaf;
1241 }
1242
1243 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1244 struct kvm_mmu_pages *pvec)
1245 {
1246 if (!sp->unsync_children)
1247 return 0;
1248
1249 mmu_pages_add(pvec, sp, 0);
1250 return __mmu_unsync_walk(sp, pvec);
1251 }
1252
1253 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1254 {
1255 WARN_ON(!sp->unsync);
1256 trace_kvm_mmu_sync_page(sp);
1257 sp->unsync = 0;
1258 --kvm->stat.mmu_unsync;
1259 }
1260
1261 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1262 struct list_head *invalid_list);
1263 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1264 struct list_head *invalid_list);
1265
1266 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1267 hlist_for_each_entry(sp, pos, \
1268 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1269 if ((sp)->gfn != (gfn)) {} else
1270
1271 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1272 hlist_for_each_entry(sp, pos, \
1273 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1274 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1275 (sp)->role.invalid) {} else
1276
1277 /* @sp->gfn should be write-protected at the call site */
1278 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1279 struct list_head *invalid_list, bool clear_unsync)
1280 {
1281 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1282 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1283 return 1;
1284 }
1285
1286 if (clear_unsync)
1287 kvm_unlink_unsync_page(vcpu->kvm, sp);
1288
1289 if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) {
1290 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1291 return 1;
1292 }
1293
1294 kvm_mmu_flush_tlb(vcpu);
1295 return 0;
1296 }
1297
1298 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1299 struct kvm_mmu_page *sp)
1300 {
1301 LIST_HEAD(invalid_list);
1302 int ret;
1303
1304 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1305 if (ret)
1306 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1307
1308 return ret;
1309 }
1310
1311 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1312 struct list_head *invalid_list)
1313 {
1314 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1315 }
1316
1317 /* @gfn should be write-protected at the call site */
1318 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1319 {
1320 struct kvm_mmu_page *s;
1321 struct hlist_node *node;
1322 LIST_HEAD(invalid_list);
1323 bool flush = false;
1324
1325 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1326 if (!s->unsync)
1327 continue;
1328
1329 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1330 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1331 (vcpu->arch.mmu.sync_page(vcpu, s, true))) {
1332 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1333 continue;
1334 }
1335 kvm_unlink_unsync_page(vcpu->kvm, s);
1336 flush = true;
1337 }
1338
1339 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1340 if (flush)
1341 kvm_mmu_flush_tlb(vcpu);
1342 }
1343
1344 struct mmu_page_path {
1345 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1346 unsigned int idx[PT64_ROOT_LEVEL-1];
1347 };
1348
1349 #define for_each_sp(pvec, sp, parents, i) \
1350 for (i = mmu_pages_next(&pvec, &parents, -1), \
1351 sp = pvec.page[i].sp; \
1352 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1353 i = mmu_pages_next(&pvec, &parents, i))
1354
1355 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1356 struct mmu_page_path *parents,
1357 int i)
1358 {
1359 int n;
1360
1361 for (n = i+1; n < pvec->nr; n++) {
1362 struct kvm_mmu_page *sp = pvec->page[n].sp;
1363
1364 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1365 parents->idx[0] = pvec->page[n].idx;
1366 return n;
1367 }
1368
1369 parents->parent[sp->role.level-2] = sp;
1370 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1371 }
1372
1373 return n;
1374 }
1375
1376 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1377 {
1378 struct kvm_mmu_page *sp;
1379 unsigned int level = 0;
1380
1381 do {
1382 unsigned int idx = parents->idx[level];
1383
1384 sp = parents->parent[level];
1385 if (!sp)
1386 return;
1387
1388 --sp->unsync_children;
1389 WARN_ON((int)sp->unsync_children < 0);
1390 __clear_bit(idx, sp->unsync_child_bitmap);
1391 level++;
1392 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1393 }
1394
1395 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1396 struct mmu_page_path *parents,
1397 struct kvm_mmu_pages *pvec)
1398 {
1399 parents->parent[parent->role.level-1] = NULL;
1400 pvec->nr = 0;
1401 }
1402
1403 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1404 struct kvm_mmu_page *parent)
1405 {
1406 int i;
1407 struct kvm_mmu_page *sp;
1408 struct mmu_page_path parents;
1409 struct kvm_mmu_pages pages;
1410 LIST_HEAD(invalid_list);
1411
1412 kvm_mmu_pages_init(parent, &parents, &pages);
1413 while (mmu_unsync_walk(parent, &pages)) {
1414 int protected = 0;
1415
1416 for_each_sp(pages, sp, parents, i)
1417 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1418
1419 if (protected)
1420 kvm_flush_remote_tlbs(vcpu->kvm);
1421
1422 for_each_sp(pages, sp, parents, i) {
1423 kvm_sync_page(vcpu, sp, &invalid_list);
1424 mmu_pages_clear_parents(&parents);
1425 }
1426 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1427 cond_resched_lock(&vcpu->kvm->mmu_lock);
1428 kvm_mmu_pages_init(parent, &parents, &pages);
1429 }
1430 }
1431
1432 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1433 gfn_t gfn,
1434 gva_t gaddr,
1435 unsigned level,
1436 int direct,
1437 unsigned access,
1438 u64 *parent_pte)
1439 {
1440 union kvm_mmu_page_role role;
1441 unsigned quadrant;
1442 struct kvm_mmu_page *sp;
1443 struct hlist_node *node;
1444 bool need_sync = false;
1445
1446 role = vcpu->arch.mmu.base_role;
1447 role.level = level;
1448 role.direct = direct;
1449 if (role.direct)
1450 role.cr4_pae = 0;
1451 role.access = access;
1452 if (!vcpu->arch.mmu.direct_map
1453 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1454 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1455 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1456 role.quadrant = quadrant;
1457 }
1458 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1459 if (!need_sync && sp->unsync)
1460 need_sync = true;
1461
1462 if (sp->role.word != role.word)
1463 continue;
1464
1465 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1466 break;
1467
1468 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1469 if (sp->unsync_children) {
1470 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1471 kvm_mmu_mark_parents_unsync(sp);
1472 } else if (sp->unsync)
1473 kvm_mmu_mark_parents_unsync(sp);
1474
1475 trace_kvm_mmu_get_page(sp, false);
1476 return sp;
1477 }
1478 ++vcpu->kvm->stat.mmu_cache_miss;
1479 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1480 if (!sp)
1481 return sp;
1482 sp->gfn = gfn;
1483 sp->role = role;
1484 hlist_add_head(&sp->hash_link,
1485 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1486 if (!direct) {
1487 if (rmap_write_protect(vcpu->kvm, gfn))
1488 kvm_flush_remote_tlbs(vcpu->kvm);
1489 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1490 kvm_sync_pages(vcpu, gfn);
1491
1492 account_shadowed(vcpu->kvm, gfn);
1493 }
1494 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1495 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1496 else
1497 nonpaging_prefetch_page(vcpu, sp);
1498 trace_kvm_mmu_get_page(sp, true);
1499 return sp;
1500 }
1501
1502 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1503 struct kvm_vcpu *vcpu, u64 addr)
1504 {
1505 iterator->addr = addr;
1506 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1507 iterator->level = vcpu->arch.mmu.shadow_root_level;
1508
1509 if (iterator->level == PT64_ROOT_LEVEL &&
1510 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1511 !vcpu->arch.mmu.direct_map)
1512 --iterator->level;
1513
1514 if (iterator->level == PT32E_ROOT_LEVEL) {
1515 iterator->shadow_addr
1516 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1517 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1518 --iterator->level;
1519 if (!iterator->shadow_addr)
1520 iterator->level = 0;
1521 }
1522 }
1523
1524 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1525 {
1526 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1527 return false;
1528
1529 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1530 if (is_large_pte(*iterator->sptep))
1531 return false;
1532
1533 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1534 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1535 return true;
1536 }
1537
1538 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1539 {
1540 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1541 --iterator->level;
1542 }
1543
1544 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1545 {
1546 u64 spte;
1547
1548 spte = __pa(sp->spt)
1549 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1550 | PT_WRITABLE_MASK | PT_USER_MASK;
1551 __set_spte(sptep, spte);
1552 }
1553
1554 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1555 {
1556 if (is_large_pte(*sptep)) {
1557 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1558 kvm_flush_remote_tlbs(vcpu->kvm);
1559 }
1560 }
1561
1562 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1563 unsigned direct_access)
1564 {
1565 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1566 struct kvm_mmu_page *child;
1567
1568 /*
1569 * For the direct sp, if the guest pte's dirty bit
1570 * changed form clean to dirty, it will corrupt the
1571 * sp's access: allow writable in the read-only sp,
1572 * so we should update the spte at this point to get
1573 * a new sp with the correct access.
1574 */
1575 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1576 if (child->role.access == direct_access)
1577 return;
1578
1579 mmu_page_remove_parent_pte(child, sptep);
1580 __set_spte(sptep, shadow_trap_nonpresent_pte);
1581 kvm_flush_remote_tlbs(vcpu->kvm);
1582 }
1583 }
1584
1585 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1586 struct kvm_mmu_page *sp)
1587 {
1588 unsigned i;
1589 u64 *pt;
1590 u64 ent;
1591
1592 pt = sp->spt;
1593
1594 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1595 ent = pt[i];
1596
1597 if (is_shadow_present_pte(ent)) {
1598 if (!is_last_spte(ent, sp->role.level)) {
1599 ent &= PT64_BASE_ADDR_MASK;
1600 mmu_page_remove_parent_pte(page_header(ent),
1601 &pt[i]);
1602 } else {
1603 if (is_large_pte(ent))
1604 --kvm->stat.lpages;
1605 drop_spte(kvm, &pt[i],
1606 shadow_trap_nonpresent_pte);
1607 }
1608 }
1609 pt[i] = shadow_trap_nonpresent_pte;
1610 }
1611 }
1612
1613 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1614 {
1615 mmu_page_remove_parent_pte(sp, parent_pte);
1616 }
1617
1618 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1619 {
1620 int i;
1621 struct kvm_vcpu *vcpu;
1622
1623 kvm_for_each_vcpu(i, vcpu, kvm)
1624 vcpu->arch.last_pte_updated = NULL;
1625 }
1626
1627 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1628 {
1629 u64 *parent_pte;
1630
1631 while (sp->multimapped || sp->parent_pte) {
1632 if (!sp->multimapped)
1633 parent_pte = sp->parent_pte;
1634 else {
1635 struct kvm_pte_chain *chain;
1636
1637 chain = container_of(sp->parent_ptes.first,
1638 struct kvm_pte_chain, link);
1639 parent_pte = chain->parent_ptes[0];
1640 }
1641 BUG_ON(!parent_pte);
1642 kvm_mmu_put_page(sp, parent_pte);
1643 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1644 }
1645 }
1646
1647 static int mmu_zap_unsync_children(struct kvm *kvm,
1648 struct kvm_mmu_page *parent,
1649 struct list_head *invalid_list)
1650 {
1651 int i, zapped = 0;
1652 struct mmu_page_path parents;
1653 struct kvm_mmu_pages pages;
1654
1655 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1656 return 0;
1657
1658 kvm_mmu_pages_init(parent, &parents, &pages);
1659 while (mmu_unsync_walk(parent, &pages)) {
1660 struct kvm_mmu_page *sp;
1661
1662 for_each_sp(pages, sp, parents, i) {
1663 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1664 mmu_pages_clear_parents(&parents);
1665 zapped++;
1666 }
1667 kvm_mmu_pages_init(parent, &parents, &pages);
1668 }
1669
1670 return zapped;
1671 }
1672
1673 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1674 struct list_head *invalid_list)
1675 {
1676 int ret;
1677
1678 trace_kvm_mmu_prepare_zap_page(sp);
1679 ++kvm->stat.mmu_shadow_zapped;
1680 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1681 kvm_mmu_page_unlink_children(kvm, sp);
1682 kvm_mmu_unlink_parents(kvm, sp);
1683 if (!sp->role.invalid && !sp->role.direct)
1684 unaccount_shadowed(kvm, sp->gfn);
1685 if (sp->unsync)
1686 kvm_unlink_unsync_page(kvm, sp);
1687 if (!sp->root_count) {
1688 /* Count self */
1689 ret++;
1690 list_move(&sp->link, invalid_list);
1691 } else {
1692 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1693 kvm_reload_remote_mmus(kvm);
1694 }
1695
1696 sp->role.invalid = 1;
1697 kvm_mmu_reset_last_pte_updated(kvm);
1698 return ret;
1699 }
1700
1701 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1702 struct list_head *invalid_list)
1703 {
1704 struct kvm_mmu_page *sp;
1705
1706 if (list_empty(invalid_list))
1707 return;
1708
1709 kvm_flush_remote_tlbs(kvm);
1710
1711 do {
1712 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1713 WARN_ON(!sp->role.invalid || sp->root_count);
1714 kvm_mmu_free_page(kvm, sp);
1715 } while (!list_empty(invalid_list));
1716
1717 }
1718
1719 /*
1720 * Changing the number of mmu pages allocated to the vm
1721 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1722 */
1723 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1724 {
1725 LIST_HEAD(invalid_list);
1726 /*
1727 * If we set the number of mmu pages to be smaller be than the
1728 * number of actived pages , we must to free some mmu pages before we
1729 * change the value
1730 */
1731
1732 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1733 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1734 !list_empty(&kvm->arch.active_mmu_pages)) {
1735 struct kvm_mmu_page *page;
1736
1737 page = container_of(kvm->arch.active_mmu_pages.prev,
1738 struct kvm_mmu_page, link);
1739 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1740 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1741 }
1742 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1743 }
1744
1745 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1746 }
1747
1748 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1749 {
1750 struct kvm_mmu_page *sp;
1751 struct hlist_node *node;
1752 LIST_HEAD(invalid_list);
1753 int r;
1754
1755 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1756 r = 0;
1757
1758 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1759 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
1760 sp->role.word);
1761 r = 1;
1762 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1763 }
1764 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1765 return r;
1766 }
1767
1768 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1769 {
1770 struct kvm_mmu_page *sp;
1771 struct hlist_node *node;
1772 LIST_HEAD(invalid_list);
1773
1774 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1775 pgprintk("%s: zap %llx %x\n",
1776 __func__, gfn, sp->role.word);
1777 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1778 }
1779 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1780 }
1781
1782 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1783 {
1784 int slot = memslot_id(kvm, gfn);
1785 struct kvm_mmu_page *sp = page_header(__pa(pte));
1786
1787 __set_bit(slot, sp->slot_bitmap);
1788 }
1789
1790 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1791 {
1792 int i;
1793 u64 *pt = sp->spt;
1794
1795 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1796 return;
1797
1798 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1799 if (pt[i] == shadow_notrap_nonpresent_pte)
1800 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1801 }
1802 }
1803
1804 /*
1805 * The function is based on mtrr_type_lookup() in
1806 * arch/x86/kernel/cpu/mtrr/generic.c
1807 */
1808 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1809 u64 start, u64 end)
1810 {
1811 int i;
1812 u64 base, mask;
1813 u8 prev_match, curr_match;
1814 int num_var_ranges = KVM_NR_VAR_MTRR;
1815
1816 if (!mtrr_state->enabled)
1817 return 0xFF;
1818
1819 /* Make end inclusive end, instead of exclusive */
1820 end--;
1821
1822 /* Look in fixed ranges. Just return the type as per start */
1823 if (mtrr_state->have_fixed && (start < 0x100000)) {
1824 int idx;
1825
1826 if (start < 0x80000) {
1827 idx = 0;
1828 idx += (start >> 16);
1829 return mtrr_state->fixed_ranges[idx];
1830 } else if (start < 0xC0000) {
1831 idx = 1 * 8;
1832 idx += ((start - 0x80000) >> 14);
1833 return mtrr_state->fixed_ranges[idx];
1834 } else if (start < 0x1000000) {
1835 idx = 3 * 8;
1836 idx += ((start - 0xC0000) >> 12);
1837 return mtrr_state->fixed_ranges[idx];
1838 }
1839 }
1840
1841 /*
1842 * Look in variable ranges
1843 * Look of multiple ranges matching this address and pick type
1844 * as per MTRR precedence
1845 */
1846 if (!(mtrr_state->enabled & 2))
1847 return mtrr_state->def_type;
1848
1849 prev_match = 0xFF;
1850 for (i = 0; i < num_var_ranges; ++i) {
1851 unsigned short start_state, end_state;
1852
1853 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1854 continue;
1855
1856 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1857 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1858 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1859 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1860
1861 start_state = ((start & mask) == (base & mask));
1862 end_state = ((end & mask) == (base & mask));
1863 if (start_state != end_state)
1864 return 0xFE;
1865
1866 if ((start & mask) != (base & mask))
1867 continue;
1868
1869 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1870 if (prev_match == 0xFF) {
1871 prev_match = curr_match;
1872 continue;
1873 }
1874
1875 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1876 curr_match == MTRR_TYPE_UNCACHABLE)
1877 return MTRR_TYPE_UNCACHABLE;
1878
1879 if ((prev_match == MTRR_TYPE_WRBACK &&
1880 curr_match == MTRR_TYPE_WRTHROUGH) ||
1881 (prev_match == MTRR_TYPE_WRTHROUGH &&
1882 curr_match == MTRR_TYPE_WRBACK)) {
1883 prev_match = MTRR_TYPE_WRTHROUGH;
1884 curr_match = MTRR_TYPE_WRTHROUGH;
1885 }
1886
1887 if (prev_match != curr_match)
1888 return MTRR_TYPE_UNCACHABLE;
1889 }
1890
1891 if (prev_match != 0xFF)
1892 return prev_match;
1893
1894 return mtrr_state->def_type;
1895 }
1896
1897 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1898 {
1899 u8 mtrr;
1900
1901 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1902 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1903 if (mtrr == 0xfe || mtrr == 0xff)
1904 mtrr = MTRR_TYPE_WRBACK;
1905 return mtrr;
1906 }
1907 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1908
1909 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1910 {
1911 trace_kvm_mmu_unsync_page(sp);
1912 ++vcpu->kvm->stat.mmu_unsync;
1913 sp->unsync = 1;
1914
1915 kvm_mmu_mark_parents_unsync(sp);
1916 mmu_convert_notrap(sp);
1917 }
1918
1919 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1920 {
1921 struct kvm_mmu_page *s;
1922 struct hlist_node *node;
1923
1924 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1925 if (s->unsync)
1926 continue;
1927 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1928 __kvm_unsync_page(vcpu, s);
1929 }
1930 }
1931
1932 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1933 bool can_unsync)
1934 {
1935 struct kvm_mmu_page *s;
1936 struct hlist_node *node;
1937 bool need_unsync = false;
1938
1939 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1940 if (!can_unsync)
1941 return 1;
1942
1943 if (s->role.level != PT_PAGE_TABLE_LEVEL)
1944 return 1;
1945
1946 if (!need_unsync && !s->unsync) {
1947 if (!oos_shadow)
1948 return 1;
1949 need_unsync = true;
1950 }
1951 }
1952 if (need_unsync)
1953 kvm_unsync_pages(vcpu, gfn);
1954 return 0;
1955 }
1956
1957 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1958 unsigned pte_access, int user_fault,
1959 int write_fault, int dirty, int level,
1960 gfn_t gfn, pfn_t pfn, bool speculative,
1961 bool can_unsync, bool reset_host_protection)
1962 {
1963 u64 spte;
1964 int ret = 0;
1965
1966 /*
1967 * We don't set the accessed bit, since we sometimes want to see
1968 * whether the guest actually used the pte (in order to detect
1969 * demand paging).
1970 */
1971 spte = PT_PRESENT_MASK;
1972 if (!speculative)
1973 spte |= shadow_accessed_mask;
1974 if (!dirty)
1975 pte_access &= ~ACC_WRITE_MASK;
1976 if (pte_access & ACC_EXEC_MASK)
1977 spte |= shadow_x_mask;
1978 else
1979 spte |= shadow_nx_mask;
1980 if (pte_access & ACC_USER_MASK)
1981 spte |= shadow_user_mask;
1982 if (level > PT_PAGE_TABLE_LEVEL)
1983 spte |= PT_PAGE_SIZE_MASK;
1984 if (tdp_enabled)
1985 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1986 kvm_is_mmio_pfn(pfn));
1987
1988 if (reset_host_protection)
1989 spte |= SPTE_HOST_WRITEABLE;
1990
1991 spte |= (u64)pfn << PAGE_SHIFT;
1992
1993 if ((pte_access & ACC_WRITE_MASK)
1994 || (!vcpu->arch.mmu.direct_map && write_fault
1995 && !is_write_protection(vcpu) && !user_fault)) {
1996
1997 if (level > PT_PAGE_TABLE_LEVEL &&
1998 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1999 ret = 1;
2000 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
2001 goto done;
2002 }
2003
2004 spte |= PT_WRITABLE_MASK;
2005
2006 if (!vcpu->arch.mmu.direct_map
2007 && !(pte_access & ACC_WRITE_MASK))
2008 spte &= ~PT_USER_MASK;
2009
2010 /*
2011 * Optimization: for pte sync, if spte was writable the hash
2012 * lookup is unnecessary (and expensive). Write protection
2013 * is responsibility of mmu_get_page / kvm_sync_page.
2014 * Same reasoning can be applied to dirty page accounting.
2015 */
2016 if (!can_unsync && is_writable_pte(*sptep))
2017 goto set_pte;
2018
2019 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2020 pgprintk("%s: found shadow page for %llx, marking ro\n",
2021 __func__, gfn);
2022 ret = 1;
2023 pte_access &= ~ACC_WRITE_MASK;
2024 if (is_writable_pte(spte))
2025 spte &= ~PT_WRITABLE_MASK;
2026 }
2027 }
2028
2029 if (pte_access & ACC_WRITE_MASK)
2030 mark_page_dirty(vcpu->kvm, gfn);
2031
2032 set_pte:
2033 update_spte(sptep, spte);
2034 done:
2035 return ret;
2036 }
2037
2038 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2039 unsigned pt_access, unsigned pte_access,
2040 int user_fault, int write_fault, int dirty,
2041 int *ptwrite, int level, gfn_t gfn,
2042 pfn_t pfn, bool speculative,
2043 bool reset_host_protection)
2044 {
2045 int was_rmapped = 0;
2046 int rmap_count;
2047
2048 pgprintk("%s: spte %llx access %x write_fault %d"
2049 " user_fault %d gfn %llx\n",
2050 __func__, *sptep, pt_access,
2051 write_fault, user_fault, gfn);
2052
2053 if (is_rmap_spte(*sptep)) {
2054 /*
2055 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2056 * the parent of the now unreachable PTE.
2057 */
2058 if (level > PT_PAGE_TABLE_LEVEL &&
2059 !is_large_pte(*sptep)) {
2060 struct kvm_mmu_page *child;
2061 u64 pte = *sptep;
2062
2063 child = page_header(pte & PT64_BASE_ADDR_MASK);
2064 mmu_page_remove_parent_pte(child, sptep);
2065 __set_spte(sptep, shadow_trap_nonpresent_pte);
2066 kvm_flush_remote_tlbs(vcpu->kvm);
2067 } else if (pfn != spte_to_pfn(*sptep)) {
2068 pgprintk("hfn old %llx new %llx\n",
2069 spte_to_pfn(*sptep), pfn);
2070 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
2071 kvm_flush_remote_tlbs(vcpu->kvm);
2072 } else
2073 was_rmapped = 1;
2074 }
2075
2076 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2077 dirty, level, gfn, pfn, speculative, true,
2078 reset_host_protection)) {
2079 if (write_fault)
2080 *ptwrite = 1;
2081 kvm_mmu_flush_tlb(vcpu);
2082 }
2083
2084 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2085 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2086 is_large_pte(*sptep)? "2MB" : "4kB",
2087 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2088 *sptep, sptep);
2089 if (!was_rmapped && is_large_pte(*sptep))
2090 ++vcpu->kvm->stat.lpages;
2091
2092 page_header_update_slot(vcpu->kvm, sptep, gfn);
2093 if (!was_rmapped) {
2094 rmap_count = rmap_add(vcpu, sptep, gfn);
2095 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2096 rmap_recycle(vcpu, sptep, gfn);
2097 }
2098 kvm_release_pfn_clean(pfn);
2099 if (speculative) {
2100 vcpu->arch.last_pte_updated = sptep;
2101 vcpu->arch.last_pte_gfn = gfn;
2102 }
2103 }
2104
2105 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2106 {
2107 }
2108
2109 static struct kvm_memory_slot *
2110 pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log)
2111 {
2112 struct kvm_memory_slot *slot;
2113
2114 slot = gfn_to_memslot(vcpu->kvm, gfn);
2115 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
2116 (no_dirty_log && slot->dirty_bitmap))
2117 slot = NULL;
2118
2119 return slot;
2120 }
2121
2122 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2123 bool no_dirty_log)
2124 {
2125 struct kvm_memory_slot *slot;
2126 unsigned long hva;
2127
2128 slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log);
2129 if (!slot) {
2130 get_page(bad_page);
2131 return page_to_pfn(bad_page);
2132 }
2133
2134 hva = gfn_to_hva_memslot(slot, gfn);
2135
2136 return hva_to_pfn_atomic(vcpu->kvm, hva);
2137 }
2138
2139 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2140 struct kvm_mmu_page *sp,
2141 u64 *start, u64 *end)
2142 {
2143 struct page *pages[PTE_PREFETCH_NUM];
2144 unsigned access = sp->role.access;
2145 int i, ret;
2146 gfn_t gfn;
2147
2148 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2149 if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK))
2150 return -1;
2151
2152 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2153 if (ret <= 0)
2154 return -1;
2155
2156 for (i = 0; i < ret; i++, gfn++, start++)
2157 mmu_set_spte(vcpu, start, ACC_ALL,
2158 access, 0, 0, 1, NULL,
2159 sp->role.level, gfn,
2160 page_to_pfn(pages[i]), true, true);
2161
2162 return 0;
2163 }
2164
2165 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2166 struct kvm_mmu_page *sp, u64 *sptep)
2167 {
2168 u64 *spte, *start = NULL;
2169 int i;
2170
2171 WARN_ON(!sp->role.direct);
2172
2173 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2174 spte = sp->spt + i;
2175
2176 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2177 if (*spte != shadow_trap_nonpresent_pte || spte == sptep) {
2178 if (!start)
2179 continue;
2180 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2181 break;
2182 start = NULL;
2183 } else if (!start)
2184 start = spte;
2185 }
2186 }
2187
2188 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2189 {
2190 struct kvm_mmu_page *sp;
2191
2192 /*
2193 * Since it's no accessed bit on EPT, it's no way to
2194 * distinguish between actually accessed translations
2195 * and prefetched, so disable pte prefetch if EPT is
2196 * enabled.
2197 */
2198 if (!shadow_accessed_mask)
2199 return;
2200
2201 sp = page_header(__pa(sptep));
2202 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2203 return;
2204
2205 __direct_pte_prefetch(vcpu, sp, sptep);
2206 }
2207
2208 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2209 int level, gfn_t gfn, pfn_t pfn)
2210 {
2211 struct kvm_shadow_walk_iterator iterator;
2212 struct kvm_mmu_page *sp;
2213 int pt_write = 0;
2214 gfn_t pseudo_gfn;
2215
2216 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2217 if (iterator.level == level) {
2218 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
2219 0, write, 1, &pt_write,
2220 level, gfn, pfn, false, true);
2221 direct_pte_prefetch(vcpu, iterator.sptep);
2222 ++vcpu->stat.pf_fixed;
2223 break;
2224 }
2225
2226 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
2227 u64 base_addr = iterator.addr;
2228
2229 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2230 pseudo_gfn = base_addr >> PAGE_SHIFT;
2231 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2232 iterator.level - 1,
2233 1, ACC_ALL, iterator.sptep);
2234 if (!sp) {
2235 pgprintk("nonpaging_map: ENOMEM\n");
2236 kvm_release_pfn_clean(pfn);
2237 return -ENOMEM;
2238 }
2239
2240 __set_spte(iterator.sptep,
2241 __pa(sp->spt)
2242 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2243 | shadow_user_mask | shadow_x_mask
2244 | shadow_accessed_mask);
2245 }
2246 }
2247 return pt_write;
2248 }
2249
2250 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2251 {
2252 siginfo_t info;
2253
2254 info.si_signo = SIGBUS;
2255 info.si_errno = 0;
2256 info.si_code = BUS_MCEERR_AR;
2257 info.si_addr = (void __user *)address;
2258 info.si_addr_lsb = PAGE_SHIFT;
2259
2260 send_sig_info(SIGBUS, &info, tsk);
2261 }
2262
2263 static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2264 {
2265 kvm_release_pfn_clean(pfn);
2266 if (is_hwpoison_pfn(pfn)) {
2267 kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current);
2268 return 0;
2269 } else if (is_fault_pfn(pfn))
2270 return -EFAULT;
2271
2272 return 1;
2273 }
2274
2275 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2276 {
2277 int r;
2278 int level;
2279 pfn_t pfn;
2280 unsigned long mmu_seq;
2281
2282 level = mapping_level(vcpu, gfn);
2283
2284 /*
2285 * This path builds a PAE pagetable - so we can map 2mb pages at
2286 * maximum. Therefore check if the level is larger than that.
2287 */
2288 if (level > PT_DIRECTORY_LEVEL)
2289 level = PT_DIRECTORY_LEVEL;
2290
2291 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2292
2293 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2294 smp_rmb();
2295 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2296
2297 /* mmio */
2298 if (is_error_pfn(pfn))
2299 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2300
2301 spin_lock(&vcpu->kvm->mmu_lock);
2302 if (mmu_notifier_retry(vcpu, mmu_seq))
2303 goto out_unlock;
2304 kvm_mmu_free_some_pages(vcpu);
2305 r = __direct_map(vcpu, v, write, level, gfn, pfn);
2306 spin_unlock(&vcpu->kvm->mmu_lock);
2307
2308
2309 return r;
2310
2311 out_unlock:
2312 spin_unlock(&vcpu->kvm->mmu_lock);
2313 kvm_release_pfn_clean(pfn);
2314 return 0;
2315 }
2316
2317
2318 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2319 {
2320 int i;
2321 struct kvm_mmu_page *sp;
2322 LIST_HEAD(invalid_list);
2323
2324 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2325 return;
2326 spin_lock(&vcpu->kvm->mmu_lock);
2327 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2328 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2329 vcpu->arch.mmu.direct_map)) {
2330 hpa_t root = vcpu->arch.mmu.root_hpa;
2331
2332 sp = page_header(root);
2333 --sp->root_count;
2334 if (!sp->root_count && sp->role.invalid) {
2335 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2336 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2337 }
2338 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2339 spin_unlock(&vcpu->kvm->mmu_lock);
2340 return;
2341 }
2342 for (i = 0; i < 4; ++i) {
2343 hpa_t root = vcpu->arch.mmu.pae_root[i];
2344
2345 if (root) {
2346 root &= PT64_BASE_ADDR_MASK;
2347 sp = page_header(root);
2348 --sp->root_count;
2349 if (!sp->root_count && sp->role.invalid)
2350 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2351 &invalid_list);
2352 }
2353 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2354 }
2355 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2356 spin_unlock(&vcpu->kvm->mmu_lock);
2357 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2358 }
2359
2360 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2361 {
2362 int ret = 0;
2363
2364 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2365 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2366 ret = 1;
2367 }
2368
2369 return ret;
2370 }
2371
2372 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2373 {
2374 struct kvm_mmu_page *sp;
2375 unsigned i;
2376
2377 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2378 spin_lock(&vcpu->kvm->mmu_lock);
2379 kvm_mmu_free_some_pages(vcpu);
2380 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2381 1, ACC_ALL, NULL);
2382 ++sp->root_count;
2383 spin_unlock(&vcpu->kvm->mmu_lock);
2384 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2385 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2386 for (i = 0; i < 4; ++i) {
2387 hpa_t root = vcpu->arch.mmu.pae_root[i];
2388
2389 ASSERT(!VALID_PAGE(root));
2390 spin_lock(&vcpu->kvm->mmu_lock);
2391 kvm_mmu_free_some_pages(vcpu);
2392 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2393 i << 30,
2394 PT32_ROOT_LEVEL, 1, ACC_ALL,
2395 NULL);
2396 root = __pa(sp->spt);
2397 ++sp->root_count;
2398 spin_unlock(&vcpu->kvm->mmu_lock);
2399 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2400 }
2401 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2402 } else
2403 BUG();
2404
2405 return 0;
2406 }
2407
2408 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2409 {
2410 struct kvm_mmu_page *sp;
2411 u64 pdptr, pm_mask;
2412 gfn_t root_gfn;
2413 int i;
2414
2415 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2416
2417 if (mmu_check_root(vcpu, root_gfn))
2418 return 1;
2419
2420 /*
2421 * Do we shadow a long mode page table? If so we need to
2422 * write-protect the guests page table root.
2423 */
2424 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2425 hpa_t root = vcpu->arch.mmu.root_hpa;
2426
2427 ASSERT(!VALID_PAGE(root));
2428
2429 spin_lock(&vcpu->kvm->mmu_lock);
2430 kvm_mmu_free_some_pages(vcpu);
2431 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2432 0, ACC_ALL, NULL);
2433 root = __pa(sp->spt);
2434 ++sp->root_count;
2435 spin_unlock(&vcpu->kvm->mmu_lock);
2436 vcpu->arch.mmu.root_hpa = root;
2437 return 0;
2438 }
2439
2440 /*
2441 * We shadow a 32 bit page table. This may be a legacy 2-level
2442 * or a PAE 3-level page table. In either case we need to be aware that
2443 * the shadow page table may be a PAE or a long mode page table.
2444 */
2445 pm_mask = PT_PRESENT_MASK;
2446 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2447 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2448
2449 for (i = 0; i < 4; ++i) {
2450 hpa_t root = vcpu->arch.mmu.pae_root[i];
2451
2452 ASSERT(!VALID_PAGE(root));
2453 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2454 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2455 if (!is_present_gpte(pdptr)) {
2456 vcpu->arch.mmu.pae_root[i] = 0;
2457 continue;
2458 }
2459 root_gfn = pdptr >> PAGE_SHIFT;
2460 if (mmu_check_root(vcpu, root_gfn))
2461 return 1;
2462 }
2463 spin_lock(&vcpu->kvm->mmu_lock);
2464 kvm_mmu_free_some_pages(vcpu);
2465 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2466 PT32_ROOT_LEVEL, 0,
2467 ACC_ALL, NULL);
2468 root = __pa(sp->spt);
2469 ++sp->root_count;
2470 spin_unlock(&vcpu->kvm->mmu_lock);
2471
2472 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2473 }
2474 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2475
2476 /*
2477 * If we shadow a 32 bit page table with a long mode page
2478 * table we enter this path.
2479 */
2480 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2481 if (vcpu->arch.mmu.lm_root == NULL) {
2482 /*
2483 * The additional page necessary for this is only
2484 * allocated on demand.
2485 */
2486
2487 u64 *lm_root;
2488
2489 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2490 if (lm_root == NULL)
2491 return 1;
2492
2493 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2494
2495 vcpu->arch.mmu.lm_root = lm_root;
2496 }
2497
2498 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2499 }
2500
2501 return 0;
2502 }
2503
2504 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2505 {
2506 if (vcpu->arch.mmu.direct_map)
2507 return mmu_alloc_direct_roots(vcpu);
2508 else
2509 return mmu_alloc_shadow_roots(vcpu);
2510 }
2511
2512 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2513 {
2514 int i;
2515 struct kvm_mmu_page *sp;
2516
2517 if (vcpu->arch.mmu.direct_map)
2518 return;
2519
2520 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2521 return;
2522
2523 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2524 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2525 hpa_t root = vcpu->arch.mmu.root_hpa;
2526 sp = page_header(root);
2527 mmu_sync_children(vcpu, sp);
2528 return;
2529 }
2530 for (i = 0; i < 4; ++i) {
2531 hpa_t root = vcpu->arch.mmu.pae_root[i];
2532
2533 if (root && VALID_PAGE(root)) {
2534 root &= PT64_BASE_ADDR_MASK;
2535 sp = page_header(root);
2536 mmu_sync_children(vcpu, sp);
2537 }
2538 }
2539 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2540 }
2541
2542 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2543 {
2544 spin_lock(&vcpu->kvm->mmu_lock);
2545 mmu_sync_roots(vcpu);
2546 spin_unlock(&vcpu->kvm->mmu_lock);
2547 }
2548
2549 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2550 u32 access, u32 *error)
2551 {
2552 if (error)
2553 *error = 0;
2554 return vaddr;
2555 }
2556
2557 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2558 u32 access, u32 *error)
2559 {
2560 if (error)
2561 *error = 0;
2562 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2563 }
2564
2565 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2566 u32 error_code, bool no_apf)
2567 {
2568 gfn_t gfn;
2569 int r;
2570
2571 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2572 r = mmu_topup_memory_caches(vcpu);
2573 if (r)
2574 return r;
2575
2576 ASSERT(vcpu);
2577 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2578
2579 gfn = gva >> PAGE_SHIFT;
2580
2581 return nonpaging_map(vcpu, gva & PAGE_MASK,
2582 error_code & PFERR_WRITE_MASK, gfn);
2583 }
2584
2585 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
2586 {
2587 struct kvm_arch_async_pf arch;
2588 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
2589 arch.gfn = gfn;
2590
2591 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
2592 }
2593
2594 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
2595 {
2596 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
2597 kvm_event_needs_reinjection(vcpu)))
2598 return false;
2599
2600 return kvm_x86_ops->interrupt_allowed(vcpu);
2601 }
2602
2603 static bool try_async_pf(struct kvm_vcpu *vcpu, bool no_apf, gfn_t gfn,
2604 gva_t gva, pfn_t *pfn)
2605 {
2606 bool async;
2607
2608 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async);
2609
2610 if (!async)
2611 return false; /* *pfn has correct page already */
2612
2613 put_page(pfn_to_page(*pfn));
2614
2615 if (!no_apf && can_do_async_pf(vcpu)) {
2616 trace_kvm_try_async_get_page(async, *pfn);
2617 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
2618 trace_kvm_async_pf_doublefault(gva, gfn);
2619 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
2620 return true;
2621 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
2622 return true;
2623 }
2624
2625 *pfn = gfn_to_pfn(vcpu->kvm, gfn);
2626
2627 return false;
2628 }
2629
2630 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
2631 bool no_apf)
2632 {
2633 pfn_t pfn;
2634 int r;
2635 int level;
2636 gfn_t gfn = gpa >> PAGE_SHIFT;
2637 unsigned long mmu_seq;
2638
2639 ASSERT(vcpu);
2640 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2641
2642 r = mmu_topup_memory_caches(vcpu);
2643 if (r)
2644 return r;
2645
2646 level = mapping_level(vcpu, gfn);
2647
2648 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2649
2650 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2651 smp_rmb();
2652
2653 if (try_async_pf(vcpu, no_apf, gfn, gpa, &pfn))
2654 return 0;
2655
2656 /* mmio */
2657 if (is_error_pfn(pfn))
2658 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2659 spin_lock(&vcpu->kvm->mmu_lock);
2660 if (mmu_notifier_retry(vcpu, mmu_seq))
2661 goto out_unlock;
2662 kvm_mmu_free_some_pages(vcpu);
2663 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
2664 level, gfn, pfn);
2665 spin_unlock(&vcpu->kvm->mmu_lock);
2666
2667 return r;
2668
2669 out_unlock:
2670 spin_unlock(&vcpu->kvm->mmu_lock);
2671 kvm_release_pfn_clean(pfn);
2672 return 0;
2673 }
2674
2675 static void nonpaging_free(struct kvm_vcpu *vcpu)
2676 {
2677 mmu_free_roots(vcpu);
2678 }
2679
2680 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2681 struct kvm_mmu *context)
2682 {
2683 context->new_cr3 = nonpaging_new_cr3;
2684 context->page_fault = nonpaging_page_fault;
2685 context->gva_to_gpa = nonpaging_gva_to_gpa;
2686 context->free = nonpaging_free;
2687 context->prefetch_page = nonpaging_prefetch_page;
2688 context->sync_page = nonpaging_sync_page;
2689 context->invlpg = nonpaging_invlpg;
2690 context->root_level = 0;
2691 context->shadow_root_level = PT32E_ROOT_LEVEL;
2692 context->root_hpa = INVALID_PAGE;
2693 context->direct_map = true;
2694 context->nx = false;
2695 return 0;
2696 }
2697
2698 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2699 {
2700 ++vcpu->stat.tlb_flush;
2701 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2702 }
2703
2704 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2705 {
2706 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
2707 mmu_free_roots(vcpu);
2708 }
2709
2710 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2711 {
2712 return vcpu->arch.cr3;
2713 }
2714
2715 static void inject_page_fault(struct kvm_vcpu *vcpu)
2716 {
2717 vcpu->arch.mmu.inject_page_fault(vcpu);
2718 }
2719
2720 static void paging_free(struct kvm_vcpu *vcpu)
2721 {
2722 nonpaging_free(vcpu);
2723 }
2724
2725 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2726 {
2727 int bit7;
2728
2729 bit7 = (gpte >> 7) & 1;
2730 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2731 }
2732
2733 #define PTTYPE 64
2734 #include "paging_tmpl.h"
2735 #undef PTTYPE
2736
2737 #define PTTYPE 32
2738 #include "paging_tmpl.h"
2739 #undef PTTYPE
2740
2741 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
2742 struct kvm_mmu *context,
2743 int level)
2744 {
2745 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2746 u64 exb_bit_rsvd = 0;
2747
2748 if (!context->nx)
2749 exb_bit_rsvd = rsvd_bits(63, 63);
2750 switch (level) {
2751 case PT32_ROOT_LEVEL:
2752 /* no rsvd bits for 2 level 4K page table entries */
2753 context->rsvd_bits_mask[0][1] = 0;
2754 context->rsvd_bits_mask[0][0] = 0;
2755 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2756
2757 if (!is_pse(vcpu)) {
2758 context->rsvd_bits_mask[1][1] = 0;
2759 break;
2760 }
2761
2762 if (is_cpuid_PSE36())
2763 /* 36bits PSE 4MB page */
2764 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2765 else
2766 /* 32 bits PSE 4MB page */
2767 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2768 break;
2769 case PT32E_ROOT_LEVEL:
2770 context->rsvd_bits_mask[0][2] =
2771 rsvd_bits(maxphyaddr, 63) |
2772 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2773 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2774 rsvd_bits(maxphyaddr, 62); /* PDE */
2775 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2776 rsvd_bits(maxphyaddr, 62); /* PTE */
2777 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2778 rsvd_bits(maxphyaddr, 62) |
2779 rsvd_bits(13, 20); /* large page */
2780 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2781 break;
2782 case PT64_ROOT_LEVEL:
2783 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2784 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2785 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2786 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2787 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2788 rsvd_bits(maxphyaddr, 51);
2789 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2790 rsvd_bits(maxphyaddr, 51);
2791 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2792 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2793 rsvd_bits(maxphyaddr, 51) |
2794 rsvd_bits(13, 29);
2795 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2796 rsvd_bits(maxphyaddr, 51) |
2797 rsvd_bits(13, 20); /* large page */
2798 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2799 break;
2800 }
2801 }
2802
2803 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
2804 struct kvm_mmu *context,
2805 int level)
2806 {
2807 context->nx = is_nx(vcpu);
2808
2809 reset_rsvds_bits_mask(vcpu, context, level);
2810
2811 ASSERT(is_pae(vcpu));
2812 context->new_cr3 = paging_new_cr3;
2813 context->page_fault = paging64_page_fault;
2814 context->gva_to_gpa = paging64_gva_to_gpa;
2815 context->prefetch_page = paging64_prefetch_page;
2816 context->sync_page = paging64_sync_page;
2817 context->invlpg = paging64_invlpg;
2818 context->free = paging_free;
2819 context->root_level = level;
2820 context->shadow_root_level = level;
2821 context->root_hpa = INVALID_PAGE;
2822 context->direct_map = false;
2823 return 0;
2824 }
2825
2826 static int paging64_init_context(struct kvm_vcpu *vcpu,
2827 struct kvm_mmu *context)
2828 {
2829 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
2830 }
2831
2832 static int paging32_init_context(struct kvm_vcpu *vcpu,
2833 struct kvm_mmu *context)
2834 {
2835 context->nx = false;
2836
2837 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2838
2839 context->new_cr3 = paging_new_cr3;
2840 context->page_fault = paging32_page_fault;
2841 context->gva_to_gpa = paging32_gva_to_gpa;
2842 context->free = paging_free;
2843 context->prefetch_page = paging32_prefetch_page;
2844 context->sync_page = paging32_sync_page;
2845 context->invlpg = paging32_invlpg;
2846 context->root_level = PT32_ROOT_LEVEL;
2847 context->shadow_root_level = PT32E_ROOT_LEVEL;
2848 context->root_hpa = INVALID_PAGE;
2849 context->direct_map = false;
2850 return 0;
2851 }
2852
2853 static int paging32E_init_context(struct kvm_vcpu *vcpu,
2854 struct kvm_mmu *context)
2855 {
2856 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
2857 }
2858
2859 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2860 {
2861 struct kvm_mmu *context = vcpu->arch.walk_mmu;
2862
2863 context->new_cr3 = nonpaging_new_cr3;
2864 context->page_fault = tdp_page_fault;
2865 context->free = nonpaging_free;
2866 context->prefetch_page = nonpaging_prefetch_page;
2867 context->sync_page = nonpaging_sync_page;
2868 context->invlpg = nonpaging_invlpg;
2869 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2870 context->root_hpa = INVALID_PAGE;
2871 context->direct_map = true;
2872 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
2873 context->get_cr3 = get_cr3;
2874 context->inject_page_fault = kvm_inject_page_fault;
2875 context->nx = is_nx(vcpu);
2876
2877 if (!is_paging(vcpu)) {
2878 context->nx = false;
2879 context->gva_to_gpa = nonpaging_gva_to_gpa;
2880 context->root_level = 0;
2881 } else if (is_long_mode(vcpu)) {
2882 context->nx = is_nx(vcpu);
2883 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
2884 context->gva_to_gpa = paging64_gva_to_gpa;
2885 context->root_level = PT64_ROOT_LEVEL;
2886 } else if (is_pae(vcpu)) {
2887 context->nx = is_nx(vcpu);
2888 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
2889 context->gva_to_gpa = paging64_gva_to_gpa;
2890 context->root_level = PT32E_ROOT_LEVEL;
2891 } else {
2892 context->nx = false;
2893 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2894 context->gva_to_gpa = paging32_gva_to_gpa;
2895 context->root_level = PT32_ROOT_LEVEL;
2896 }
2897
2898 return 0;
2899 }
2900
2901 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
2902 {
2903 int r;
2904 ASSERT(vcpu);
2905 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2906
2907 if (!is_paging(vcpu))
2908 r = nonpaging_init_context(vcpu, context);
2909 else if (is_long_mode(vcpu))
2910 r = paging64_init_context(vcpu, context);
2911 else if (is_pae(vcpu))
2912 r = paging32E_init_context(vcpu, context);
2913 else
2914 r = paging32_init_context(vcpu, context);
2915
2916 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
2917 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2918
2919 return r;
2920 }
2921 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
2922
2923 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2924 {
2925 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
2926
2927 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
2928 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
2929 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
2930
2931 return r;
2932 }
2933
2934 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
2935 {
2936 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
2937
2938 g_context->get_cr3 = get_cr3;
2939 g_context->inject_page_fault = kvm_inject_page_fault;
2940
2941 /*
2942 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
2943 * translation of l2_gpa to l1_gpa addresses is done using the
2944 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
2945 * functions between mmu and nested_mmu are swapped.
2946 */
2947 if (!is_paging(vcpu)) {
2948 g_context->nx = false;
2949 g_context->root_level = 0;
2950 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
2951 } else if (is_long_mode(vcpu)) {
2952 g_context->nx = is_nx(vcpu);
2953 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
2954 g_context->root_level = PT64_ROOT_LEVEL;
2955 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
2956 } else if (is_pae(vcpu)) {
2957 g_context->nx = is_nx(vcpu);
2958 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
2959 g_context->root_level = PT32E_ROOT_LEVEL;
2960 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
2961 } else {
2962 g_context->nx = false;
2963 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
2964 g_context->root_level = PT32_ROOT_LEVEL;
2965 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
2966 }
2967
2968 return 0;
2969 }
2970
2971 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2972 {
2973 vcpu->arch.update_pte.pfn = bad_pfn;
2974
2975 if (mmu_is_nested(vcpu))
2976 return init_kvm_nested_mmu(vcpu);
2977 else if (tdp_enabled)
2978 return init_kvm_tdp_mmu(vcpu);
2979 else
2980 return init_kvm_softmmu(vcpu);
2981 }
2982
2983 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2984 {
2985 ASSERT(vcpu);
2986 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2987 /* mmu.free() should set root_hpa = INVALID_PAGE */
2988 vcpu->arch.mmu.free(vcpu);
2989 }
2990
2991 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
2992 {
2993 destroy_kvm_mmu(vcpu);
2994 return init_kvm_mmu(vcpu);
2995 }
2996 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
2997
2998 int kvm_mmu_load(struct kvm_vcpu *vcpu)
2999 {
3000 int r;
3001
3002 r = mmu_topup_memory_caches(vcpu);
3003 if (r)
3004 goto out;
3005 r = mmu_alloc_roots(vcpu);
3006 spin_lock(&vcpu->kvm->mmu_lock);
3007 mmu_sync_roots(vcpu);
3008 spin_unlock(&vcpu->kvm->mmu_lock);
3009 if (r)
3010 goto out;
3011 /* set_cr3() should ensure TLB has been flushed */
3012 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3013 out:
3014 return r;
3015 }
3016 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3017
3018 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3019 {
3020 mmu_free_roots(vcpu);
3021 }
3022 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3023
3024 static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
3025 struct kvm_mmu_page *sp,
3026 u64 *spte)
3027 {
3028 u64 pte;
3029 struct kvm_mmu_page *child;
3030
3031 pte = *spte;
3032 if (is_shadow_present_pte(pte)) {
3033 if (is_last_spte(pte, sp->role.level))
3034 drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte);
3035 else {
3036 child = page_header(pte & PT64_BASE_ADDR_MASK);
3037 mmu_page_remove_parent_pte(child, spte);
3038 }
3039 }
3040 __set_spte(spte, shadow_trap_nonpresent_pte);
3041 if (is_large_pte(pte))
3042 --vcpu->kvm->stat.lpages;
3043 }
3044
3045 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3046 struct kvm_mmu_page *sp,
3047 u64 *spte,
3048 const void *new)
3049 {
3050 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3051 ++vcpu->kvm->stat.mmu_pde_zapped;
3052 return;
3053 }
3054
3055 if (is_rsvd_bits_set(&vcpu->arch.mmu, *(u64 *)new, PT_PAGE_TABLE_LEVEL))
3056 return;
3057
3058 ++vcpu->kvm->stat.mmu_pte_updated;
3059 if (!sp->role.cr4_pae)
3060 paging32_update_pte(vcpu, sp, spte, new);
3061 else
3062 paging64_update_pte(vcpu, sp, spte, new);
3063 }
3064
3065 static bool need_remote_flush(u64 old, u64 new)
3066 {
3067 if (!is_shadow_present_pte(old))
3068 return false;
3069 if (!is_shadow_present_pte(new))
3070 return true;
3071 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3072 return true;
3073 old ^= PT64_NX_MASK;
3074 new ^= PT64_NX_MASK;
3075 return (old & ~new & PT64_PERM_MASK) != 0;
3076 }
3077
3078 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3079 bool remote_flush, bool local_flush)
3080 {
3081 if (zap_page)
3082 return;
3083
3084 if (remote_flush)
3085 kvm_flush_remote_tlbs(vcpu->kvm);
3086 else if (local_flush)
3087 kvm_mmu_flush_tlb(vcpu);
3088 }
3089
3090 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3091 {
3092 u64 *spte = vcpu->arch.last_pte_updated;
3093
3094 return !!(spte && (*spte & shadow_accessed_mask));
3095 }
3096
3097 static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3098 u64 gpte)
3099 {
3100 gfn_t gfn;
3101 pfn_t pfn;
3102
3103 if (!is_present_gpte(gpte))
3104 return;
3105 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
3106
3107 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
3108 smp_rmb();
3109 pfn = gfn_to_pfn(vcpu->kvm, gfn);
3110
3111 if (is_error_pfn(pfn)) {
3112 kvm_release_pfn_clean(pfn);
3113 return;
3114 }
3115 vcpu->arch.update_pte.gfn = gfn;
3116 vcpu->arch.update_pte.pfn = pfn;
3117 }
3118
3119 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3120 {
3121 u64 *spte = vcpu->arch.last_pte_updated;
3122
3123 if (spte
3124 && vcpu->arch.last_pte_gfn == gfn
3125 && shadow_accessed_mask
3126 && !(*spte & shadow_accessed_mask)
3127 && is_shadow_present_pte(*spte))
3128 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3129 }
3130
3131 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3132 const u8 *new, int bytes,
3133 bool guest_initiated)
3134 {
3135 gfn_t gfn = gpa >> PAGE_SHIFT;
3136 union kvm_mmu_page_role mask = { .word = 0 };
3137 struct kvm_mmu_page *sp;
3138 struct hlist_node *node;
3139 LIST_HEAD(invalid_list);
3140 u64 entry, gentry;
3141 u64 *spte;
3142 unsigned offset = offset_in_page(gpa);
3143 unsigned pte_size;
3144 unsigned page_offset;
3145 unsigned misaligned;
3146 unsigned quadrant;
3147 int level;
3148 int flooded = 0;
3149 int npte;
3150 int r;
3151 int invlpg_counter;
3152 bool remote_flush, local_flush, zap_page;
3153
3154 zap_page = remote_flush = local_flush = false;
3155
3156 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3157
3158 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3159
3160 /*
3161 * Assume that the pte write on a page table of the same type
3162 * as the current vcpu paging mode. This is nearly always true
3163 * (might be false while changing modes). Note it is verified later
3164 * by update_pte().
3165 */
3166 if ((is_pae(vcpu) && bytes == 4) || !new) {
3167 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3168 if (is_pae(vcpu)) {
3169 gpa &= ~(gpa_t)7;
3170 bytes = 8;
3171 }
3172 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3173 if (r)
3174 gentry = 0;
3175 new = (const u8 *)&gentry;
3176 }
3177
3178 switch (bytes) {
3179 case 4:
3180 gentry = *(const u32 *)new;
3181 break;
3182 case 8:
3183 gentry = *(const u64 *)new;
3184 break;
3185 default:
3186 gentry = 0;
3187 break;
3188 }
3189
3190 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
3191 spin_lock(&vcpu->kvm->mmu_lock);
3192 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3193 gentry = 0;
3194 kvm_mmu_access_page(vcpu, gfn);
3195 kvm_mmu_free_some_pages(vcpu);
3196 ++vcpu->kvm->stat.mmu_pte_write;
3197 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3198 if (guest_initiated) {
3199 if (gfn == vcpu->arch.last_pt_write_gfn
3200 && !last_updated_pte_accessed(vcpu)) {
3201 ++vcpu->arch.last_pt_write_count;
3202 if (vcpu->arch.last_pt_write_count >= 3)
3203 flooded = 1;
3204 } else {
3205 vcpu->arch.last_pt_write_gfn = gfn;
3206 vcpu->arch.last_pt_write_count = 1;
3207 vcpu->arch.last_pte_updated = NULL;
3208 }
3209 }
3210
3211 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3212 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3213 pte_size = sp->role.cr4_pae ? 8 : 4;
3214 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3215 misaligned |= bytes < 4;
3216 if (misaligned || flooded) {
3217 /*
3218 * Misaligned accesses are too much trouble to fix
3219 * up; also, they usually indicate a page is not used
3220 * as a page table.
3221 *
3222 * If we're seeing too many writes to a page,
3223 * it may no longer be a page table, or we may be
3224 * forking, in which case it is better to unmap the
3225 * page.
3226 */
3227 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3228 gpa, bytes, sp->role.word);
3229 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3230 &invalid_list);
3231 ++vcpu->kvm->stat.mmu_flooded;
3232 continue;
3233 }
3234 page_offset = offset;
3235 level = sp->role.level;
3236 npte = 1;
3237 if (!sp->role.cr4_pae) {
3238 page_offset <<= 1; /* 32->64 */
3239 /*
3240 * A 32-bit pde maps 4MB while the shadow pdes map
3241 * only 2MB. So we need to double the offset again
3242 * and zap two pdes instead of one.
3243 */
3244 if (level == PT32_ROOT_LEVEL) {
3245 page_offset &= ~7; /* kill rounding error */
3246 page_offset <<= 1;
3247 npte = 2;
3248 }
3249 quadrant = page_offset >> PAGE_SHIFT;
3250 page_offset &= ~PAGE_MASK;
3251 if (quadrant != sp->role.quadrant)
3252 continue;
3253 }
3254 local_flush = true;
3255 spte = &sp->spt[page_offset / sizeof(*spte)];
3256 while (npte--) {
3257 entry = *spte;
3258 mmu_pte_write_zap_pte(vcpu, sp, spte);
3259 if (gentry &&
3260 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3261 & mask.word))
3262 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3263 if (!remote_flush && need_remote_flush(entry, *spte))
3264 remote_flush = true;
3265 ++spte;
3266 }
3267 }
3268 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3269 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3270 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3271 spin_unlock(&vcpu->kvm->mmu_lock);
3272 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
3273 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
3274 vcpu->arch.update_pte.pfn = bad_pfn;
3275 }
3276 }
3277
3278 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3279 {
3280 gpa_t gpa;
3281 int r;
3282
3283 if (vcpu->arch.mmu.direct_map)
3284 return 0;
3285
3286 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3287
3288 spin_lock(&vcpu->kvm->mmu_lock);
3289 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3290 spin_unlock(&vcpu->kvm->mmu_lock);
3291 return r;
3292 }
3293 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3294
3295 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3296 {
3297 LIST_HEAD(invalid_list);
3298
3299 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3300 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3301 struct kvm_mmu_page *sp;
3302
3303 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3304 struct kvm_mmu_page, link);
3305 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3306 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3307 ++vcpu->kvm->stat.mmu_recycled;
3308 }
3309 }
3310
3311 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
3312 {
3313 int r;
3314 enum emulation_result er;
3315
3316 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3317 if (r < 0)
3318 goto out;
3319
3320 if (!r) {
3321 r = 1;
3322 goto out;
3323 }
3324
3325 r = mmu_topup_memory_caches(vcpu);
3326 if (r)
3327 goto out;
3328
3329 er = emulate_instruction(vcpu, cr2, error_code, 0);
3330
3331 switch (er) {
3332 case EMULATE_DONE:
3333 return 1;
3334 case EMULATE_DO_MMIO:
3335 ++vcpu->stat.mmio_exits;
3336 /* fall through */
3337 case EMULATE_FAIL:
3338 return 0;
3339 default:
3340 BUG();
3341 }
3342 out:
3343 return r;
3344 }
3345 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3346
3347 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3348 {
3349 vcpu->arch.mmu.invlpg(vcpu, gva);
3350 kvm_mmu_flush_tlb(vcpu);
3351 ++vcpu->stat.invlpg;
3352 }
3353 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3354
3355 void kvm_enable_tdp(void)
3356 {
3357 tdp_enabled = true;
3358 }
3359 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3360
3361 void kvm_disable_tdp(void)
3362 {
3363 tdp_enabled = false;
3364 }
3365 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3366
3367 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3368 {
3369 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3370 if (vcpu->arch.mmu.lm_root != NULL)
3371 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3372 }
3373
3374 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3375 {
3376 struct page *page;
3377 int i;
3378
3379 ASSERT(vcpu);
3380
3381 /*
3382 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3383 * Therefore we need to allocate shadow page tables in the first
3384 * 4GB of memory, which happens to fit the DMA32 zone.
3385 */
3386 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3387 if (!page)
3388 return -ENOMEM;
3389
3390 vcpu->arch.mmu.pae_root = page_address(page);
3391 for (i = 0; i < 4; ++i)
3392 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3393
3394 return 0;
3395 }
3396
3397 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3398 {
3399 ASSERT(vcpu);
3400 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3401
3402 return alloc_mmu_pages(vcpu);
3403 }
3404
3405 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3406 {
3407 ASSERT(vcpu);
3408 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3409
3410 return init_kvm_mmu(vcpu);
3411 }
3412
3413 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3414 {
3415 struct kvm_mmu_page *sp;
3416
3417 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3418 int i;
3419 u64 *pt;
3420
3421 if (!test_bit(slot, sp->slot_bitmap))
3422 continue;
3423
3424 pt = sp->spt;
3425 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
3426 /* avoid RMW */
3427 if (is_writable_pte(pt[i]))
3428 pt[i] &= ~PT_WRITABLE_MASK;
3429 }
3430 kvm_flush_remote_tlbs(kvm);
3431 }
3432
3433 void kvm_mmu_zap_all(struct kvm *kvm)
3434 {
3435 struct kvm_mmu_page *sp, *node;
3436 LIST_HEAD(invalid_list);
3437
3438 spin_lock(&kvm->mmu_lock);
3439 restart:
3440 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3441 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3442 goto restart;
3443
3444 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3445 spin_unlock(&kvm->mmu_lock);
3446 }
3447
3448 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3449 struct list_head *invalid_list)
3450 {
3451 struct kvm_mmu_page *page;
3452
3453 page = container_of(kvm->arch.active_mmu_pages.prev,
3454 struct kvm_mmu_page, link);
3455 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3456 }
3457
3458 static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3459 {
3460 struct kvm *kvm;
3461 struct kvm *kvm_freed = NULL;
3462
3463 if (nr_to_scan == 0)
3464 goto out;
3465
3466 spin_lock(&kvm_lock);
3467
3468 list_for_each_entry(kvm, &vm_list, vm_list) {
3469 int idx, freed_pages;
3470 LIST_HEAD(invalid_list);
3471
3472 idx = srcu_read_lock(&kvm->srcu);
3473 spin_lock(&kvm->mmu_lock);
3474 if (!kvm_freed && nr_to_scan > 0 &&
3475 kvm->arch.n_used_mmu_pages > 0) {
3476 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3477 &invalid_list);
3478 kvm_freed = kvm;
3479 }
3480 nr_to_scan--;
3481
3482 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3483 spin_unlock(&kvm->mmu_lock);
3484 srcu_read_unlock(&kvm->srcu, idx);
3485 }
3486 if (kvm_freed)
3487 list_move_tail(&kvm_freed->vm_list, &vm_list);
3488
3489 spin_unlock(&kvm_lock);
3490
3491 out:
3492 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3493 }
3494
3495 static struct shrinker mmu_shrinker = {
3496 .shrink = mmu_shrink,
3497 .seeks = DEFAULT_SEEKS * 10,
3498 };
3499
3500 static void mmu_destroy_caches(void)
3501 {
3502 if (pte_chain_cache)
3503 kmem_cache_destroy(pte_chain_cache);
3504 if (rmap_desc_cache)
3505 kmem_cache_destroy(rmap_desc_cache);
3506 if (mmu_page_header_cache)
3507 kmem_cache_destroy(mmu_page_header_cache);
3508 }
3509
3510 void kvm_mmu_module_exit(void)
3511 {
3512 mmu_destroy_caches();
3513 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3514 unregister_shrinker(&mmu_shrinker);
3515 }
3516
3517 int kvm_mmu_module_init(void)
3518 {
3519 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3520 sizeof(struct kvm_pte_chain),
3521 0, 0, NULL);
3522 if (!pte_chain_cache)
3523 goto nomem;
3524 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3525 sizeof(struct kvm_rmap_desc),
3526 0, 0, NULL);
3527 if (!rmap_desc_cache)
3528 goto nomem;
3529
3530 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3531 sizeof(struct kvm_mmu_page),
3532 0, 0, NULL);
3533 if (!mmu_page_header_cache)
3534 goto nomem;
3535
3536 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3537 goto nomem;
3538
3539 register_shrinker(&mmu_shrinker);
3540
3541 return 0;
3542
3543 nomem:
3544 mmu_destroy_caches();
3545 return -ENOMEM;
3546 }
3547
3548 /*
3549 * Caculate mmu pages needed for kvm.
3550 */
3551 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3552 {
3553 int i;
3554 unsigned int nr_mmu_pages;
3555 unsigned int nr_pages = 0;
3556 struct kvm_memslots *slots;
3557
3558 slots = kvm_memslots(kvm);
3559
3560 for (i = 0; i < slots->nmemslots; i++)
3561 nr_pages += slots->memslots[i].npages;
3562
3563 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3564 nr_mmu_pages = max(nr_mmu_pages,
3565 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3566
3567 return nr_mmu_pages;
3568 }
3569
3570 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3571 unsigned len)
3572 {
3573 if (len > buffer->len)
3574 return NULL;
3575 return buffer->ptr;
3576 }
3577
3578 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3579 unsigned len)
3580 {
3581 void *ret;
3582
3583 ret = pv_mmu_peek_buffer(buffer, len);
3584 if (!ret)
3585 return ret;
3586 buffer->ptr += len;
3587 buffer->len -= len;
3588 buffer->processed += len;
3589 return ret;
3590 }
3591
3592 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3593 gpa_t addr, gpa_t value)
3594 {
3595 int bytes = 8;
3596 int r;
3597
3598 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3599 bytes = 4;
3600
3601 r = mmu_topup_memory_caches(vcpu);
3602 if (r)
3603 return r;
3604
3605 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3606 return -EFAULT;
3607
3608 return 1;
3609 }
3610
3611 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3612 {
3613 (void)kvm_set_cr3(vcpu, vcpu->arch.cr3);
3614 return 1;
3615 }
3616
3617 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3618 {
3619 spin_lock(&vcpu->kvm->mmu_lock);
3620 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3621 spin_unlock(&vcpu->kvm->mmu_lock);
3622 return 1;
3623 }
3624
3625 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3626 struct kvm_pv_mmu_op_buffer *buffer)
3627 {
3628 struct kvm_mmu_op_header *header;
3629
3630 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3631 if (!header)
3632 return 0;
3633 switch (header->op) {
3634 case KVM_MMU_OP_WRITE_PTE: {
3635 struct kvm_mmu_op_write_pte *wpte;
3636
3637 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3638 if (!wpte)
3639 return 0;
3640 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3641 wpte->pte_val);
3642 }
3643 case KVM_MMU_OP_FLUSH_TLB: {
3644 struct kvm_mmu_op_flush_tlb *ftlb;
3645
3646 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3647 if (!ftlb)
3648 return 0;
3649 return kvm_pv_mmu_flush_tlb(vcpu);
3650 }
3651 case KVM_MMU_OP_RELEASE_PT: {
3652 struct kvm_mmu_op_release_pt *rpt;
3653
3654 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3655 if (!rpt)
3656 return 0;
3657 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3658 }
3659 default: return 0;
3660 }
3661 }
3662
3663 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3664 gpa_t addr, unsigned long *ret)
3665 {
3666 int r;
3667 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3668
3669 buffer->ptr = buffer->buf;
3670 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3671 buffer->processed = 0;
3672
3673 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3674 if (r)
3675 goto out;
3676
3677 while (buffer->len) {
3678 r = kvm_pv_mmu_op_one(vcpu, buffer);
3679 if (r < 0)
3680 goto out;
3681 if (r == 0)
3682 break;
3683 }
3684
3685 r = 1;
3686 out:
3687 *ret = buffer->processed;
3688 return r;
3689 }
3690
3691 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3692 {
3693 struct kvm_shadow_walk_iterator iterator;
3694 int nr_sptes = 0;
3695
3696 spin_lock(&vcpu->kvm->mmu_lock);
3697 for_each_shadow_entry(vcpu, addr, iterator) {
3698 sptes[iterator.level-1] = *iterator.sptep;
3699 nr_sptes++;
3700 if (!is_shadow_present_pte(*iterator.sptep))
3701 break;
3702 }
3703 spin_unlock(&vcpu->kvm->mmu_lock);
3704
3705 return nr_sptes;
3706 }
3707 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3708
3709 #ifdef CONFIG_KVM_MMU_AUDIT
3710 #include "mmu_audit.c"
3711 #else
3712 static void mmu_audit_disable(void) { }
3713 #endif
3714
3715 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3716 {
3717 ASSERT(vcpu);
3718
3719 destroy_kvm_mmu(vcpu);
3720 free_mmu_pages(vcpu);
3721 mmu_free_memory_caches(vcpu);
3722 mmu_audit_disable();
3723 }
Linux kernel - Deliverables
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