2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg
, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc
{
157 u64
*sptes
[PTE_LIST_EXT
];
158 struct pte_list_desc
*more
;
161 struct kvm_shadow_walk_iterator
{
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache
*pte_list_desc_cache
;
181 static struct kmem_cache
*mmu_page_header_cache
;
182 static struct percpu_counter kvm_total_used_mmu_pages
;
184 static u64 __read_mostly shadow_nx_mask
;
185 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask
;
187 static u64 __read_mostly shadow_accessed_mask
;
188 static u64 __read_mostly shadow_dirty_mask
;
189 static u64 __read_mostly shadow_mmio_mask
;
191 static void mmu_spte_set(u64
*sptep
, u64 spte
);
192 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
196 shadow_mmio_mask
= mmio_mask
;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
200 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
202 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
204 trace_mark_mmio_spte(sptep
, gfn
, access
);
205 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
208 static bool is_mmio_spte(u64 spte
)
210 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
213 static gfn_t
get_mmio_spte_gfn(u64 spte
)
215 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
218 static unsigned get_mmio_spte_access(u64 spte
)
220 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
223 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
225 if (unlikely(is_noslot_pfn(pfn
))) {
226 mark_mmio_spte(sptep
, gfn
, access
);
233 static inline u64
rsvd_bits(int s
, int e
)
235 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
238 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
239 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
241 shadow_user_mask
= user_mask
;
242 shadow_accessed_mask
= accessed_mask
;
243 shadow_dirty_mask
= dirty_mask
;
244 shadow_nx_mask
= nx_mask
;
245 shadow_x_mask
= x_mask
;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu
*vcpu
)
256 return vcpu
->arch
.efer
& EFER_NX
;
259 static int is_shadow_present_pte(u64 pte
)
261 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
264 static int is_large_pte(u64 pte
)
266 return pte
& PT_PAGE_SIZE_MASK
;
269 static int is_dirty_gpte(unsigned long pte
)
271 return pte
& PT_DIRTY_MASK
;
274 static int is_rmap_spte(u64 pte
)
276 return is_shadow_present_pte(pte
);
279 static int is_last_spte(u64 pte
, int level
)
281 if (level
== PT_PAGE_TABLE_LEVEL
)
283 if (is_large_pte(pte
))
288 static pfn_t
spte_to_pfn(u64 pte
)
290 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
293 static gfn_t
pse36_gfn_delta(u32 gpte
)
295 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
297 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
301 static void __set_spte(u64
*sptep
, u64 spte
)
306 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
311 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
313 return xchg(sptep
, spte
);
316 static u64
__get_spte_lockless(u64
*sptep
)
318 return ACCESS_ONCE(*sptep
);
321 static bool __check_direct_spte_mmio_pf(u64 spte
)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64
*sptep
, u64 spte
)
337 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
339 if (is_shadow_present_pte(spte
))
342 /* Ensure the spte is completely set before we increase the count */
344 sp
->clear_spte_count
++;
347 static void __set_spte(u64
*sptep
, u64 spte
)
349 union split_spte
*ssptep
, sspte
;
351 ssptep
= (union split_spte
*)sptep
;
352 sspte
= (union split_spte
)spte
;
354 ssptep
->spte_high
= sspte
.spte_high
;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep
->spte_low
= sspte
.spte_low
;
366 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
368 union split_spte
*ssptep
, sspte
;
370 ssptep
= (union split_spte
*)sptep
;
371 sspte
= (union split_spte
)spte
;
373 ssptep
->spte_low
= sspte
.spte_low
;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep
->spte_high
= sspte
.spte_high
;
382 count_spte_clear(sptep
, spte
);
385 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
387 union split_spte
*ssptep
, sspte
, orig
;
389 ssptep
= (union split_spte
*)sptep
;
390 sspte
= (union split_spte
)spte
;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
394 orig
.spte_high
= ssptep
->spte_high
;
395 ssptep
->spte_high
= sspte
.spte_high
;
396 count_spte_clear(sptep
, spte
);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64
__get_spte_lockless(u64
*sptep
)
410 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
411 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
415 count
= sp
->clear_spte_count
;
418 spte
.spte_low
= orig
->spte_low
;
421 spte
.spte_high
= orig
->spte_high
;
424 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
425 count
!= sp
->clear_spte_count
))
431 static bool __check_direct_spte_mmio_pf(u64 spte
)
433 union split_spte sspte
= (union split_spte
)spte
;
434 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte
.spte_low
== 0ull &&
442 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
449 static bool spte_is_locklessly_modifiable(u64 spte
)
451 return !(~spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
));
454 static bool spte_has_volatile_bits(u64 spte
)
457 * Always atomicly update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_is_locklessly_modifiable(spte
))
465 if (!shadow_accessed_mask
)
468 if (!is_shadow_present_pte(spte
))
471 if ((spte
& shadow_accessed_mask
) &&
472 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
478 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
480 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
483 /* Rules for using mmu_spte_set:
484 * Set the sptep from nonpresent to present.
485 * Note: the sptep being assigned *must* be either not present
486 * or in a state where the hardware will not attempt to update
489 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
491 WARN_ON(is_shadow_present_pte(*sptep
));
492 __set_spte(sptep
, new_spte
);
495 /* Rules for using mmu_spte_update:
496 * Update the state bits, it means the mapped pfn is not changged.
498 * Whenever we overwrite a writable spte with a read-only one we
499 * should flush remote TLBs. Otherwise rmap_write_protect
500 * will find a read-only spte, even though the writable spte
501 * might be cached on a CPU's TLB, the return value indicates this
504 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
506 u64 old_spte
= *sptep
;
509 WARN_ON(!is_rmap_spte(new_spte
));
511 if (!is_shadow_present_pte(old_spte
)) {
512 mmu_spte_set(sptep
, new_spte
);
516 if (!spte_has_volatile_bits(old_spte
))
517 __update_clear_spte_fast(sptep
, new_spte
);
519 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
522 * For the spte updated out of mmu-lock is safe, since
523 * we always atomicly update it, see the comments in
524 * spte_has_volatile_bits().
526 if (is_writable_pte(old_spte
) && !is_writable_pte(new_spte
))
529 if (!shadow_accessed_mask
)
532 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
533 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
534 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
535 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
541 * Rules for using mmu_spte_clear_track_bits:
542 * It sets the sptep from present to nonpresent, and track the
543 * state bits, it is used to clear the last level sptep.
545 static int mmu_spte_clear_track_bits(u64
*sptep
)
548 u64 old_spte
= *sptep
;
550 if (!spte_has_volatile_bits(old_spte
))
551 __update_clear_spte_fast(sptep
, 0ull);
553 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
555 if (!is_rmap_spte(old_spte
))
558 pfn
= spte_to_pfn(old_spte
);
559 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
560 kvm_set_pfn_accessed(pfn
);
561 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
562 kvm_set_pfn_dirty(pfn
);
567 * Rules for using mmu_spte_clear_no_track:
568 * Directly clear spte without caring the state bits of sptep,
569 * it is used to set the upper level spte.
571 static void mmu_spte_clear_no_track(u64
*sptep
)
573 __update_clear_spte_fast(sptep
, 0ull);
576 static u64
mmu_spte_get_lockless(u64
*sptep
)
578 return __get_spte_lockless(sptep
);
581 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
584 * Prevent page table teardown by making any free-er wait during
585 * kvm_flush_remote_tlbs() IPI to all active vcpus.
588 vcpu
->mode
= READING_SHADOW_PAGE_TABLES
;
590 * Make sure a following spte read is not reordered ahead of the write
596 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
599 * Make sure the write to vcpu->mode is not reordered in front of
600 * reads to sptes. If it does, kvm_commit_zap_page() can see us
601 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
604 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
608 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
609 struct kmem_cache
*base_cache
, int min
)
613 if (cache
->nobjs
>= min
)
615 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
616 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
619 cache
->objects
[cache
->nobjs
++] = obj
;
624 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
629 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
630 struct kmem_cache
*cache
)
633 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
636 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
641 if (cache
->nobjs
>= min
)
643 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
644 page
= (void *)__get_free_page(GFP_KERNEL
);
647 cache
->objects
[cache
->nobjs
++] = page
;
652 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
655 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
658 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
662 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
663 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
666 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
669 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
670 mmu_page_header_cache
, 4);
675 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
677 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
678 pte_list_desc_cache
);
679 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
680 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
681 mmu_page_header_cache
);
684 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
689 p
= mc
->objects
[--mc
->nobjs
];
693 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
695 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
698 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
700 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
703 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
705 if (!sp
->role
.direct
)
706 return sp
->gfns
[index
];
708 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
711 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
714 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
716 sp
->gfns
[index
] = gfn
;
720 * Return the pointer to the large page information for a given gfn,
721 * handling slots that are not large page aligned.
723 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
724 struct kvm_memory_slot
*slot
,
729 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
730 return &slot
->arch
.lpage_info
[level
- 2][idx
];
733 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
735 struct kvm_memory_slot
*slot
;
736 struct kvm_lpage_info
*linfo
;
739 slot
= gfn_to_memslot(kvm
, gfn
);
740 for (i
= PT_DIRECTORY_LEVEL
;
741 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
742 linfo
= lpage_info_slot(gfn
, slot
, i
);
743 linfo
->write_count
+= 1;
745 kvm
->arch
.indirect_shadow_pages
++;
748 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
750 struct kvm_memory_slot
*slot
;
751 struct kvm_lpage_info
*linfo
;
754 slot
= gfn_to_memslot(kvm
, gfn
);
755 for (i
= PT_DIRECTORY_LEVEL
;
756 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
757 linfo
= lpage_info_slot(gfn
, slot
, i
);
758 linfo
->write_count
-= 1;
759 WARN_ON(linfo
->write_count
< 0);
761 kvm
->arch
.indirect_shadow_pages
--;
764 static int has_wrprotected_page(struct kvm
*kvm
,
768 struct kvm_memory_slot
*slot
;
769 struct kvm_lpage_info
*linfo
;
771 slot
= gfn_to_memslot(kvm
, gfn
);
773 linfo
= lpage_info_slot(gfn
, slot
, level
);
774 return linfo
->write_count
;
780 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
782 unsigned long page_size
;
785 page_size
= kvm_host_page_size(kvm
, gfn
);
787 for (i
= PT_PAGE_TABLE_LEVEL
;
788 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
789 if (page_size
>= KVM_HPAGE_SIZE(i
))
798 static struct kvm_memory_slot
*
799 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
802 struct kvm_memory_slot
*slot
;
804 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
805 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
806 (no_dirty_log
&& slot
->dirty_bitmap
))
812 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
814 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
817 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
819 int host_level
, level
, max_level
;
821 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
823 if (host_level
== PT_PAGE_TABLE_LEVEL
)
826 max_level
= kvm_x86_ops
->get_lpage_level() < host_level
?
827 kvm_x86_ops
->get_lpage_level() : host_level
;
829 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
830 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
837 * Pte mapping structures:
839 * If pte_list bit zero is zero, then pte_list point to the spte.
841 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
842 * pte_list_desc containing more mappings.
844 * Returns the number of pte entries before the spte was added or zero if
845 * the spte was not added.
848 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
849 unsigned long *pte_list
)
851 struct pte_list_desc
*desc
;
855 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
856 *pte_list
= (unsigned long)spte
;
857 } else if (!(*pte_list
& 1)) {
858 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
859 desc
= mmu_alloc_pte_list_desc(vcpu
);
860 desc
->sptes
[0] = (u64
*)*pte_list
;
861 desc
->sptes
[1] = spte
;
862 *pte_list
= (unsigned long)desc
| 1;
865 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
866 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
867 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
869 count
+= PTE_LIST_EXT
;
871 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
872 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
875 for (i
= 0; desc
->sptes
[i
]; ++i
)
877 desc
->sptes
[i
] = spte
;
883 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
884 int i
, struct pte_list_desc
*prev_desc
)
888 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
890 desc
->sptes
[i
] = desc
->sptes
[j
];
891 desc
->sptes
[j
] = NULL
;
894 if (!prev_desc
&& !desc
->more
)
895 *pte_list
= (unsigned long)desc
->sptes
[0];
898 prev_desc
->more
= desc
->more
;
900 *pte_list
= (unsigned long)desc
->more
| 1;
901 mmu_free_pte_list_desc(desc
);
904 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
906 struct pte_list_desc
*desc
;
907 struct pte_list_desc
*prev_desc
;
911 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
913 } else if (!(*pte_list
& 1)) {
914 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
915 if ((u64
*)*pte_list
!= spte
) {
916 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
921 rmap_printk("pte_list_remove: %p many->many\n", spte
);
922 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
925 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
926 if (desc
->sptes
[i
] == spte
) {
927 pte_list_desc_remove_entry(pte_list
,
935 pr_err("pte_list_remove: %p many->many\n", spte
);
940 typedef void (*pte_list_walk_fn
) (u64
*spte
);
941 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
943 struct pte_list_desc
*desc
;
949 if (!(*pte_list
& 1))
950 return fn((u64
*)*pte_list
);
952 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
954 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
960 static unsigned long *__gfn_to_rmap(gfn_t gfn
, int level
,
961 struct kvm_memory_slot
*slot
)
963 struct kvm_lpage_info
*linfo
;
965 if (likely(level
== PT_PAGE_TABLE_LEVEL
))
966 return &slot
->rmap
[gfn
- slot
->base_gfn
];
968 linfo
= lpage_info_slot(gfn
, slot
, level
);
969 return &linfo
->rmap_pde
;
973 * Take gfn and return the reverse mapping to it.
975 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
977 struct kvm_memory_slot
*slot
;
979 slot
= gfn_to_memslot(kvm
, gfn
);
980 return __gfn_to_rmap(gfn
, level
, slot
);
983 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
985 struct kvm_mmu_memory_cache
*cache
;
987 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
988 return mmu_memory_cache_free_objects(cache
);
991 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
993 struct kvm_mmu_page
*sp
;
994 unsigned long *rmapp
;
996 sp
= page_header(__pa(spte
));
997 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
998 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
999 return pte_list_add(vcpu
, spte
, rmapp
);
1002 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1004 struct kvm_mmu_page
*sp
;
1006 unsigned long *rmapp
;
1008 sp
= page_header(__pa(spte
));
1009 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1010 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
1011 pte_list_remove(spte
, rmapp
);
1015 * Used by the following functions to iterate through the sptes linked by a
1016 * rmap. All fields are private and not assumed to be used outside.
1018 struct rmap_iterator
{
1019 /* private fields */
1020 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1021 int pos
; /* index of the sptep */
1025 * Iteration must be started by this function. This should also be used after
1026 * removing/dropping sptes from the rmap link because in such cases the
1027 * information in the itererator may not be valid.
1029 * Returns sptep if found, NULL otherwise.
1031 static u64
*rmap_get_first(unsigned long rmap
, struct rmap_iterator
*iter
)
1041 iter
->desc
= (struct pte_list_desc
*)(rmap
& ~1ul);
1043 return iter
->desc
->sptes
[iter
->pos
];
1047 * Must be used with a valid iterator: e.g. after rmap_get_first().
1049 * Returns sptep if found, NULL otherwise.
1051 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1054 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1058 sptep
= iter
->desc
->sptes
[iter
->pos
];
1063 iter
->desc
= iter
->desc
->more
;
1067 /* desc->sptes[0] cannot be NULL */
1068 return iter
->desc
->sptes
[iter
->pos
];
1075 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1077 if (mmu_spte_clear_track_bits(sptep
))
1078 rmap_remove(kvm
, sptep
);
1082 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1084 if (is_large_pte(*sptep
)) {
1085 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1086 PT_PAGE_TABLE_LEVEL
);
1087 drop_spte(kvm
, sptep
);
1095 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1097 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1098 kvm_flush_remote_tlbs(vcpu
->kvm
);
1102 * Write-protect on the specified @sptep, @pt_protect indicates whether
1103 * spte writ-protection is caused by protecting shadow page table.
1104 * @flush indicates whether tlb need be flushed.
1106 * Note: write protection is difference between drity logging and spte
1108 * - for dirty logging, the spte can be set to writable at anytime if
1109 * its dirty bitmap is properly set.
1110 * - for spte protection, the spte can be writable only after unsync-ing
1113 * Return true if the spte is dropped.
1116 spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool *flush
, bool pt_protect
)
1120 if (!is_writable_pte(spte
) &&
1121 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1124 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1126 if (__drop_large_spte(kvm
, sptep
)) {
1132 spte
&= ~SPTE_MMU_WRITEABLE
;
1133 spte
= spte
& ~PT_WRITABLE_MASK
;
1135 *flush
|= mmu_spte_update(sptep
, spte
);
1139 static bool __rmap_write_protect(struct kvm
*kvm
, unsigned long *rmapp
,
1140 int level
, bool pt_protect
)
1143 struct rmap_iterator iter
;
1146 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1147 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1148 if (spte_write_protect(kvm
, sptep
, &flush
, pt_protect
)) {
1149 sptep
= rmap_get_first(*rmapp
, &iter
);
1153 sptep
= rmap_get_next(&iter
);
1160 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1161 * @kvm: kvm instance
1162 * @slot: slot to protect
1163 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1164 * @mask: indicates which pages we should protect
1166 * Used when we do not need to care about huge page mappings: e.g. during dirty
1167 * logging we do not have any such mappings.
1169 void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1170 struct kvm_memory_slot
*slot
,
1171 gfn_t gfn_offset
, unsigned long mask
)
1173 unsigned long *rmapp
;
1176 rmapp
= &slot
->rmap
[gfn_offset
+ __ffs(mask
)];
1177 __rmap_write_protect(kvm
, rmapp
, PT_PAGE_TABLE_LEVEL
, false);
1179 /* clear the first set bit */
1184 static bool rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1186 struct kvm_memory_slot
*slot
;
1187 unsigned long *rmapp
;
1189 bool write_protected
= false;
1191 slot
= gfn_to_memslot(kvm
, gfn
);
1193 for (i
= PT_PAGE_TABLE_LEVEL
;
1194 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1195 rmapp
= __gfn_to_rmap(gfn
, i
, slot
);
1196 write_protected
|= __rmap_write_protect(kvm
, rmapp
, i
, true);
1199 return write_protected
;
1202 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1206 struct rmap_iterator iter
;
1207 int need_tlb_flush
= 0;
1209 while ((sptep
= rmap_get_first(*rmapp
, &iter
))) {
1210 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1211 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep
, *sptep
);
1213 drop_spte(kvm
, sptep
);
1217 return need_tlb_flush
;
1220 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1224 struct rmap_iterator iter
;
1227 pte_t
*ptep
= (pte_t
*)data
;
1230 WARN_ON(pte_huge(*ptep
));
1231 new_pfn
= pte_pfn(*ptep
);
1233 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1234 BUG_ON(!is_shadow_present_pte(*sptep
));
1235 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep
, *sptep
);
1239 if (pte_write(*ptep
)) {
1240 drop_spte(kvm
, sptep
);
1241 sptep
= rmap_get_first(*rmapp
, &iter
);
1243 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1244 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1246 new_spte
&= ~PT_WRITABLE_MASK
;
1247 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1248 new_spte
&= ~shadow_accessed_mask
;
1250 mmu_spte_clear_track_bits(sptep
);
1251 mmu_spte_set(sptep
, new_spte
);
1252 sptep
= rmap_get_next(&iter
);
1257 kvm_flush_remote_tlbs(kvm
);
1262 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1264 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1265 unsigned long data
))
1270 struct kvm_memslots
*slots
;
1271 struct kvm_memory_slot
*memslot
;
1273 slots
= kvm_memslots(kvm
);
1275 kvm_for_each_memslot(memslot
, slots
) {
1276 unsigned long start
= memslot
->userspace_addr
;
1279 end
= start
+ (memslot
->npages
<< PAGE_SHIFT
);
1280 if (hva
>= start
&& hva
< end
) {
1281 gfn_t gfn
= hva_to_gfn_memslot(hva
, memslot
);
1285 for (j
= PT_PAGE_TABLE_LEVEL
;
1286 j
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++j
) {
1287 unsigned long *rmapp
;
1289 rmapp
= __gfn_to_rmap(gfn
, j
, memslot
);
1290 ret
|= handler(kvm
, rmapp
, data
);
1292 trace_kvm_age_page(hva
, memslot
, ret
);
1300 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1302 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1305 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1307 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1310 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1314 struct rmap_iterator
uninitialized_var(iter
);
1318 * In case of absence of EPT Access and Dirty Bits supports,
1319 * emulate the accessed bit for EPT, by checking if this page has
1320 * an EPT mapping, and clearing it if it does. On the next access,
1321 * a new EPT mapping will be established.
1322 * This has some overhead, but not as much as the cost of swapping
1323 * out actively used pages or breaking up actively used hugepages.
1325 if (!shadow_accessed_mask
)
1326 return kvm_unmap_rmapp(kvm
, rmapp
, data
);
1328 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1329 sptep
= rmap_get_next(&iter
)) {
1330 BUG_ON(!is_shadow_present_pte(*sptep
));
1332 if (*sptep
& shadow_accessed_mask
) {
1334 clear_bit((ffs(shadow_accessed_mask
) - 1),
1335 (unsigned long *)sptep
);
1342 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1346 struct rmap_iterator iter
;
1350 * If there's no access bit in the secondary pte set by the
1351 * hardware it's up to gup-fast/gup to set the access bit in
1352 * the primary pte or in the page structure.
1354 if (!shadow_accessed_mask
)
1357 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1358 sptep
= rmap_get_next(&iter
)) {
1359 BUG_ON(!is_shadow_present_pte(*sptep
));
1361 if (*sptep
& shadow_accessed_mask
) {
1370 #define RMAP_RECYCLE_THRESHOLD 1000
1372 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1374 unsigned long *rmapp
;
1375 struct kvm_mmu_page
*sp
;
1377 sp
= page_header(__pa(spte
));
1379 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1381 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, 0);
1382 kvm_flush_remote_tlbs(vcpu
->kvm
);
1385 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1387 return kvm_handle_hva(kvm
, hva
, 0, kvm_age_rmapp
);
1390 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1392 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1396 static int is_empty_shadow_page(u64
*spt
)
1401 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1402 if (is_shadow_present_pte(*pos
)) {
1403 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1412 * This value is the sum of all of the kvm instances's
1413 * kvm->arch.n_used_mmu_pages values. We need a global,
1414 * aggregate version in order to make the slab shrinker
1417 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1419 kvm
->arch
.n_used_mmu_pages
+= nr
;
1420 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1424 * Remove the sp from shadow page cache, after call it,
1425 * we can not find this sp from the cache, and the shadow
1426 * page table is still valid.
1427 * It should be under the protection of mmu lock.
1429 static void kvm_mmu_isolate_page(struct kvm_mmu_page
*sp
)
1431 ASSERT(is_empty_shadow_page(sp
->spt
));
1432 hlist_del(&sp
->hash_link
);
1433 if (!sp
->role
.direct
)
1434 free_page((unsigned long)sp
->gfns
);
1438 * Free the shadow page table and the sp, we can do it
1439 * out of the protection of mmu lock.
1441 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1443 list_del(&sp
->link
);
1444 free_page((unsigned long)sp
->spt
);
1445 kmem_cache_free(mmu_page_header_cache
, sp
);
1448 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1450 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1453 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1454 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1459 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1462 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1465 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1468 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1471 mmu_page_remove_parent_pte(sp
, parent_pte
);
1472 mmu_spte_clear_no_track(parent_pte
);
1475 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1476 u64
*parent_pte
, int direct
)
1478 struct kvm_mmu_page
*sp
;
1479 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1480 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1482 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1483 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1484 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1485 bitmap_zero(sp
->slot_bitmap
, KVM_MEM_SLOTS_NUM
);
1486 sp
->parent_ptes
= 0;
1487 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1488 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1492 static void mark_unsync(u64
*spte
);
1493 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1495 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1498 static void mark_unsync(u64
*spte
)
1500 struct kvm_mmu_page
*sp
;
1503 sp
= page_header(__pa(spte
));
1504 index
= spte
- sp
->spt
;
1505 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1507 if (sp
->unsync_children
++)
1509 kvm_mmu_mark_parents_unsync(sp
);
1512 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1513 struct kvm_mmu_page
*sp
)
1518 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1522 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1523 struct kvm_mmu_page
*sp
, u64
*spte
,
1529 #define KVM_PAGE_ARRAY_NR 16
1531 struct kvm_mmu_pages
{
1532 struct mmu_page_and_offset
{
1533 struct kvm_mmu_page
*sp
;
1535 } page
[KVM_PAGE_ARRAY_NR
];
1539 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1545 for (i
=0; i
< pvec
->nr
; i
++)
1546 if (pvec
->page
[i
].sp
== sp
)
1549 pvec
->page
[pvec
->nr
].sp
= sp
;
1550 pvec
->page
[pvec
->nr
].idx
= idx
;
1552 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1555 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1556 struct kvm_mmu_pages
*pvec
)
1558 int i
, ret
, nr_unsync_leaf
= 0;
1560 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1561 struct kvm_mmu_page
*child
;
1562 u64 ent
= sp
->spt
[i
];
1564 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1565 goto clear_child_bitmap
;
1567 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1569 if (child
->unsync_children
) {
1570 if (mmu_pages_add(pvec
, child
, i
))
1573 ret
= __mmu_unsync_walk(child
, pvec
);
1575 goto clear_child_bitmap
;
1577 nr_unsync_leaf
+= ret
;
1580 } else if (child
->unsync
) {
1582 if (mmu_pages_add(pvec
, child
, i
))
1585 goto clear_child_bitmap
;
1590 __clear_bit(i
, sp
->unsync_child_bitmap
);
1591 sp
->unsync_children
--;
1592 WARN_ON((int)sp
->unsync_children
< 0);
1596 return nr_unsync_leaf
;
1599 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1600 struct kvm_mmu_pages
*pvec
)
1602 if (!sp
->unsync_children
)
1605 mmu_pages_add(pvec
, sp
, 0);
1606 return __mmu_unsync_walk(sp
, pvec
);
1609 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1611 WARN_ON(!sp
->unsync
);
1612 trace_kvm_mmu_sync_page(sp
);
1614 --kvm
->stat
.mmu_unsync
;
1617 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1618 struct list_head
*invalid_list
);
1619 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1620 struct list_head
*invalid_list
);
1622 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1623 hlist_for_each_entry(sp, pos, \
1624 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1625 if ((sp)->gfn != (gfn)) {} else
1627 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1628 hlist_for_each_entry(sp, pos, \
1629 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1630 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1631 (sp)->role.invalid) {} else
1633 /* @sp->gfn should be write-protected at the call site */
1634 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1635 struct list_head
*invalid_list
, bool clear_unsync
)
1637 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1638 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1643 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1645 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1646 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1650 kvm_mmu_flush_tlb(vcpu
);
1654 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1655 struct kvm_mmu_page
*sp
)
1657 LIST_HEAD(invalid_list
);
1660 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1662 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1667 #ifdef CONFIG_KVM_MMU_AUDIT
1668 #include "mmu_audit.c"
1670 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1671 static void mmu_audit_disable(void) { }
1674 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1675 struct list_head
*invalid_list
)
1677 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1680 /* @gfn should be write-protected at the call site */
1681 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1683 struct kvm_mmu_page
*s
;
1684 struct hlist_node
*node
;
1685 LIST_HEAD(invalid_list
);
1688 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
1692 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1693 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1694 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1695 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1696 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1702 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1704 kvm_mmu_flush_tlb(vcpu
);
1707 struct mmu_page_path
{
1708 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1709 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1712 #define for_each_sp(pvec, sp, parents, i) \
1713 for (i = mmu_pages_next(&pvec, &parents, -1), \
1714 sp = pvec.page[i].sp; \
1715 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1716 i = mmu_pages_next(&pvec, &parents, i))
1718 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1719 struct mmu_page_path
*parents
,
1724 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1725 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1727 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1728 parents
->idx
[0] = pvec
->page
[n
].idx
;
1732 parents
->parent
[sp
->role
.level
-2] = sp
;
1733 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1739 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1741 struct kvm_mmu_page
*sp
;
1742 unsigned int level
= 0;
1745 unsigned int idx
= parents
->idx
[level
];
1747 sp
= parents
->parent
[level
];
1751 --sp
->unsync_children
;
1752 WARN_ON((int)sp
->unsync_children
< 0);
1753 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1755 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1758 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1759 struct mmu_page_path
*parents
,
1760 struct kvm_mmu_pages
*pvec
)
1762 parents
->parent
[parent
->role
.level
-1] = NULL
;
1766 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1767 struct kvm_mmu_page
*parent
)
1770 struct kvm_mmu_page
*sp
;
1771 struct mmu_page_path parents
;
1772 struct kvm_mmu_pages pages
;
1773 LIST_HEAD(invalid_list
);
1775 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1776 while (mmu_unsync_walk(parent
, &pages
)) {
1777 bool protected = false;
1779 for_each_sp(pages
, sp
, parents
, i
)
1780 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1783 kvm_flush_remote_tlbs(vcpu
->kvm
);
1785 for_each_sp(pages
, sp
, parents
, i
) {
1786 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1787 mmu_pages_clear_parents(&parents
);
1789 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1790 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1791 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1795 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1799 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1803 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1805 sp
->write_flooding_count
= 0;
1808 static void clear_sp_write_flooding_count(u64
*spte
)
1810 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
1812 __clear_sp_write_flooding_count(sp
);
1815 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1823 union kvm_mmu_page_role role
;
1825 struct kvm_mmu_page
*sp
;
1826 struct hlist_node
*node
;
1827 bool need_sync
= false;
1829 role
= vcpu
->arch
.mmu
.base_role
;
1831 role
.direct
= direct
;
1834 role
.access
= access
;
1835 if (!vcpu
->arch
.mmu
.direct_map
1836 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1837 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1838 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1839 role
.quadrant
= quadrant
;
1841 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
, node
) {
1842 if (!need_sync
&& sp
->unsync
)
1845 if (sp
->role
.word
!= role
.word
)
1848 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1851 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1852 if (sp
->unsync_children
) {
1853 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1854 kvm_mmu_mark_parents_unsync(sp
);
1855 } else if (sp
->unsync
)
1856 kvm_mmu_mark_parents_unsync(sp
);
1858 __clear_sp_write_flooding_count(sp
);
1859 trace_kvm_mmu_get_page(sp
, false);
1862 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1863 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1868 hlist_add_head(&sp
->hash_link
,
1869 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1871 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1872 kvm_flush_remote_tlbs(vcpu
->kvm
);
1873 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1874 kvm_sync_pages(vcpu
, gfn
);
1876 account_shadowed(vcpu
->kvm
, gfn
);
1878 init_shadow_page_table(sp
);
1879 trace_kvm_mmu_get_page(sp
, true);
1883 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1884 struct kvm_vcpu
*vcpu
, u64 addr
)
1886 iterator
->addr
= addr
;
1887 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1888 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1890 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1891 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1892 !vcpu
->arch
.mmu
.direct_map
)
1895 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1896 iterator
->shadow_addr
1897 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1898 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1900 if (!iterator
->shadow_addr
)
1901 iterator
->level
= 0;
1905 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1907 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1910 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1911 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1915 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1918 if (is_last_spte(spte
, iterator
->level
)) {
1919 iterator
->level
= 0;
1923 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1927 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1929 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1932 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1936 spte
= __pa(sp
->spt
)
1937 | PT_PRESENT_MASK
| PT_ACCESSED_MASK
1938 | PT_WRITABLE_MASK
| PT_USER_MASK
;
1939 mmu_spte_set(sptep
, spte
);
1942 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1943 unsigned direct_access
)
1945 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1946 struct kvm_mmu_page
*child
;
1949 * For the direct sp, if the guest pte's dirty bit
1950 * changed form clean to dirty, it will corrupt the
1951 * sp's access: allow writable in the read-only sp,
1952 * so we should update the spte at this point to get
1953 * a new sp with the correct access.
1955 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
1956 if (child
->role
.access
== direct_access
)
1959 drop_parent_pte(child
, sptep
);
1960 kvm_flush_remote_tlbs(vcpu
->kvm
);
1964 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1968 struct kvm_mmu_page
*child
;
1971 if (is_shadow_present_pte(pte
)) {
1972 if (is_last_spte(pte
, sp
->role
.level
)) {
1973 drop_spte(kvm
, spte
);
1974 if (is_large_pte(pte
))
1977 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
1978 drop_parent_pte(child
, spte
);
1983 if (is_mmio_spte(pte
))
1984 mmu_spte_clear_no_track(spte
);
1989 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
1990 struct kvm_mmu_page
*sp
)
1994 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1995 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
1998 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
2000 mmu_page_remove_parent_pte(sp
, parent_pte
);
2003 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2006 struct rmap_iterator iter
;
2008 while ((sptep
= rmap_get_first(sp
->parent_ptes
, &iter
)))
2009 drop_parent_pte(sp
, sptep
);
2012 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2013 struct kvm_mmu_page
*parent
,
2014 struct list_head
*invalid_list
)
2017 struct mmu_page_path parents
;
2018 struct kvm_mmu_pages pages
;
2020 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2023 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2024 while (mmu_unsync_walk(parent
, &pages
)) {
2025 struct kvm_mmu_page
*sp
;
2027 for_each_sp(pages
, sp
, parents
, i
) {
2028 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2029 mmu_pages_clear_parents(&parents
);
2032 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2038 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2039 struct list_head
*invalid_list
)
2043 trace_kvm_mmu_prepare_zap_page(sp
);
2044 ++kvm
->stat
.mmu_shadow_zapped
;
2045 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2046 kvm_mmu_page_unlink_children(kvm
, sp
);
2047 kvm_mmu_unlink_parents(kvm
, sp
);
2048 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2049 unaccount_shadowed(kvm
, sp
->gfn
);
2051 kvm_unlink_unsync_page(kvm
, sp
);
2052 if (!sp
->root_count
) {
2055 list_move(&sp
->link
, invalid_list
);
2056 kvm_mod_used_mmu_pages(kvm
, -1);
2058 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2059 kvm_reload_remote_mmus(kvm
);
2062 sp
->role
.invalid
= 1;
2066 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2067 struct list_head
*invalid_list
)
2069 struct kvm_mmu_page
*sp
;
2071 if (list_empty(invalid_list
))
2075 * wmb: make sure everyone sees our modifications to the page tables
2076 * rmb: make sure we see changes to vcpu->mode
2081 * Wait for all vcpus to exit guest mode and/or lockless shadow
2084 kvm_flush_remote_tlbs(kvm
);
2087 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
2088 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2089 kvm_mmu_isolate_page(sp
);
2090 kvm_mmu_free_page(sp
);
2091 } while (!list_empty(invalid_list
));
2095 * Changing the number of mmu pages allocated to the vm
2096 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2098 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2100 LIST_HEAD(invalid_list
);
2102 * If we set the number of mmu pages to be smaller be than the
2103 * number of actived pages , we must to free some mmu pages before we
2107 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2108 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
&&
2109 !list_empty(&kvm
->arch
.active_mmu_pages
)) {
2110 struct kvm_mmu_page
*page
;
2112 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
2113 struct kvm_mmu_page
, link
);
2114 kvm_mmu_prepare_zap_page(kvm
, page
, &invalid_list
);
2116 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2117 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2120 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2123 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2125 struct kvm_mmu_page
*sp
;
2126 struct hlist_node
*node
;
2127 LIST_HEAD(invalid_list
);
2130 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2132 spin_lock(&kvm
->mmu_lock
);
2133 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2134 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2137 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2139 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2140 spin_unlock(&kvm
->mmu_lock
);
2144 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2146 static void page_header_update_slot(struct kvm
*kvm
, void *pte
, gfn_t gfn
)
2148 int slot
= memslot_id(kvm
, gfn
);
2149 struct kvm_mmu_page
*sp
= page_header(__pa(pte
));
2151 __set_bit(slot
, sp
->slot_bitmap
);
2155 * The function is based on mtrr_type_lookup() in
2156 * arch/x86/kernel/cpu/mtrr/generic.c
2158 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2163 u8 prev_match
, curr_match
;
2164 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2166 if (!mtrr_state
->enabled
)
2169 /* Make end inclusive end, instead of exclusive */
2172 /* Look in fixed ranges. Just return the type as per start */
2173 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2176 if (start
< 0x80000) {
2178 idx
+= (start
>> 16);
2179 return mtrr_state
->fixed_ranges
[idx
];
2180 } else if (start
< 0xC0000) {
2182 idx
+= ((start
- 0x80000) >> 14);
2183 return mtrr_state
->fixed_ranges
[idx
];
2184 } else if (start
< 0x1000000) {
2186 idx
+= ((start
- 0xC0000) >> 12);
2187 return mtrr_state
->fixed_ranges
[idx
];
2192 * Look in variable ranges
2193 * Look of multiple ranges matching this address and pick type
2194 * as per MTRR precedence
2196 if (!(mtrr_state
->enabled
& 2))
2197 return mtrr_state
->def_type
;
2200 for (i
= 0; i
< num_var_ranges
; ++i
) {
2201 unsigned short start_state
, end_state
;
2203 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2206 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2207 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2208 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2209 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2211 start_state
= ((start
& mask
) == (base
& mask
));
2212 end_state
= ((end
& mask
) == (base
& mask
));
2213 if (start_state
!= end_state
)
2216 if ((start
& mask
) != (base
& mask
))
2219 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2220 if (prev_match
== 0xFF) {
2221 prev_match
= curr_match
;
2225 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2226 curr_match
== MTRR_TYPE_UNCACHABLE
)
2227 return MTRR_TYPE_UNCACHABLE
;
2229 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2230 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2231 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2232 curr_match
== MTRR_TYPE_WRBACK
)) {
2233 prev_match
= MTRR_TYPE_WRTHROUGH
;
2234 curr_match
= MTRR_TYPE_WRTHROUGH
;
2237 if (prev_match
!= curr_match
)
2238 return MTRR_TYPE_UNCACHABLE
;
2241 if (prev_match
!= 0xFF)
2244 return mtrr_state
->def_type
;
2247 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2251 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2252 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2253 if (mtrr
== 0xfe || mtrr
== 0xff)
2254 mtrr
= MTRR_TYPE_WRBACK
;
2257 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2259 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2261 trace_kvm_mmu_unsync_page(sp
);
2262 ++vcpu
->kvm
->stat
.mmu_unsync
;
2265 kvm_mmu_mark_parents_unsync(sp
);
2268 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2270 struct kvm_mmu_page
*s
;
2271 struct hlist_node
*node
;
2273 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2276 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2277 __kvm_unsync_page(vcpu
, s
);
2281 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2284 struct kvm_mmu_page
*s
;
2285 struct hlist_node
*node
;
2286 bool need_unsync
= false;
2288 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2292 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2295 if (!need_unsync
&& !s
->unsync
) {
2300 kvm_unsync_pages(vcpu
, gfn
);
2304 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2305 unsigned pte_access
, int user_fault
,
2306 int write_fault
, int level
,
2307 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2308 bool can_unsync
, bool host_writable
)
2313 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2316 spte
= PT_PRESENT_MASK
;
2318 spte
|= shadow_accessed_mask
;
2320 if (pte_access
& ACC_EXEC_MASK
)
2321 spte
|= shadow_x_mask
;
2323 spte
|= shadow_nx_mask
;
2325 if (pte_access
& ACC_USER_MASK
)
2326 spte
|= shadow_user_mask
;
2328 if (level
> PT_PAGE_TABLE_LEVEL
)
2329 spte
|= PT_PAGE_SIZE_MASK
;
2331 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2332 kvm_is_mmio_pfn(pfn
));
2335 spte
|= SPTE_HOST_WRITEABLE
;
2337 pte_access
&= ~ACC_WRITE_MASK
;
2339 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2341 if ((pte_access
& ACC_WRITE_MASK
)
2342 || (!vcpu
->arch
.mmu
.direct_map
&& write_fault
2343 && !is_write_protection(vcpu
) && !user_fault
)) {
2345 if (level
> PT_PAGE_TABLE_LEVEL
&&
2346 has_wrprotected_page(vcpu
->kvm
, gfn
, level
)) {
2348 drop_spte(vcpu
->kvm
, sptep
);
2352 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2354 if (!vcpu
->arch
.mmu
.direct_map
2355 && !(pte_access
& ACC_WRITE_MASK
)) {
2356 spte
&= ~PT_USER_MASK
;
2358 * If we converted a user page to a kernel page,
2359 * so that the kernel can write to it when cr0.wp=0,
2360 * then we should prevent the kernel from executing it
2361 * if SMEP is enabled.
2363 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
2364 spte
|= PT64_NX_MASK
;
2368 * Optimization: for pte sync, if spte was writable the hash
2369 * lookup is unnecessary (and expensive). Write protection
2370 * is responsibility of mmu_get_page / kvm_sync_page.
2371 * Same reasoning can be applied to dirty page accounting.
2373 if (!can_unsync
&& is_writable_pte(*sptep
))
2376 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2377 pgprintk("%s: found shadow page for %llx, marking ro\n",
2380 pte_access
&= ~ACC_WRITE_MASK
;
2381 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2385 if (pte_access
& ACC_WRITE_MASK
)
2386 mark_page_dirty(vcpu
->kvm
, gfn
);
2389 if (mmu_spte_update(sptep
, spte
))
2390 kvm_flush_remote_tlbs(vcpu
->kvm
);
2395 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2396 unsigned pt_access
, unsigned pte_access
,
2397 int user_fault
, int write_fault
,
2398 int *emulate
, int level
, gfn_t gfn
,
2399 pfn_t pfn
, bool speculative
,
2402 int was_rmapped
= 0;
2405 pgprintk("%s: spte %llx access %x write_fault %d"
2406 " user_fault %d gfn %llx\n",
2407 __func__
, *sptep
, pt_access
,
2408 write_fault
, user_fault
, gfn
);
2410 if (is_rmap_spte(*sptep
)) {
2412 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2413 * the parent of the now unreachable PTE.
2415 if (level
> PT_PAGE_TABLE_LEVEL
&&
2416 !is_large_pte(*sptep
)) {
2417 struct kvm_mmu_page
*child
;
2420 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2421 drop_parent_pte(child
, sptep
);
2422 kvm_flush_remote_tlbs(vcpu
->kvm
);
2423 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2424 pgprintk("hfn old %llx new %llx\n",
2425 spte_to_pfn(*sptep
), pfn
);
2426 drop_spte(vcpu
->kvm
, sptep
);
2427 kvm_flush_remote_tlbs(vcpu
->kvm
);
2432 if (set_spte(vcpu
, sptep
, pte_access
, user_fault
, write_fault
,
2433 level
, gfn
, pfn
, speculative
, true,
2437 kvm_mmu_flush_tlb(vcpu
);
2440 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2443 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2444 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2445 is_large_pte(*sptep
)? "2MB" : "4kB",
2446 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2448 if (!was_rmapped
&& is_large_pte(*sptep
))
2449 ++vcpu
->kvm
->stat
.lpages
;
2451 if (is_shadow_present_pte(*sptep
)) {
2452 page_header_update_slot(vcpu
->kvm
, sptep
, gfn
);
2454 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2455 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2456 rmap_recycle(vcpu
, sptep
, gfn
);
2459 kvm_release_pfn_clean(pfn
);
2462 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2464 mmu_free_roots(vcpu
);
2467 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2470 struct kvm_memory_slot
*slot
;
2473 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2475 get_page(fault_page
);
2476 return page_to_pfn(fault_page
);
2479 hva
= gfn_to_hva_memslot(slot
, gfn
);
2481 return hva_to_pfn_atomic(vcpu
->kvm
, hva
);
2484 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2485 struct kvm_mmu_page
*sp
,
2486 u64
*start
, u64
*end
)
2488 struct page
*pages
[PTE_PREFETCH_NUM
];
2489 unsigned access
= sp
->role
.access
;
2493 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2494 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2497 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2501 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2502 mmu_set_spte(vcpu
, start
, ACC_ALL
,
2504 sp
->role
.level
, gfn
,
2505 page_to_pfn(pages
[i
]), true, true);
2510 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2511 struct kvm_mmu_page
*sp
, u64
*sptep
)
2513 u64
*spte
, *start
= NULL
;
2516 WARN_ON(!sp
->role
.direct
);
2518 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2521 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2522 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2525 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2533 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2535 struct kvm_mmu_page
*sp
;
2538 * Since it's no accessed bit on EPT, it's no way to
2539 * distinguish between actually accessed translations
2540 * and prefetched, so disable pte prefetch if EPT is
2543 if (!shadow_accessed_mask
)
2546 sp
= page_header(__pa(sptep
));
2547 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2550 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2553 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2554 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2557 struct kvm_shadow_walk_iterator iterator
;
2558 struct kvm_mmu_page
*sp
;
2562 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2563 if (iterator
.level
== level
) {
2564 unsigned pte_access
= ACC_ALL
;
2566 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
, pte_access
,
2568 level
, gfn
, pfn
, prefault
, map_writable
);
2569 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2570 ++vcpu
->stat
.pf_fixed
;
2574 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2575 u64 base_addr
= iterator
.addr
;
2577 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2578 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2579 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2581 1, ACC_ALL
, iterator
.sptep
);
2583 pgprintk("nonpaging_map: ENOMEM\n");
2584 kvm_release_pfn_clean(pfn
);
2588 mmu_spte_set(iterator
.sptep
,
2590 | PT_PRESENT_MASK
| PT_WRITABLE_MASK
2591 | shadow_user_mask
| shadow_x_mask
2592 | shadow_accessed_mask
);
2598 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2602 info
.si_signo
= SIGBUS
;
2604 info
.si_code
= BUS_MCEERR_AR
;
2605 info
.si_addr
= (void __user
*)address
;
2606 info
.si_addr_lsb
= PAGE_SHIFT
;
2608 send_sig_info(SIGBUS
, &info
, tsk
);
2611 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2613 kvm_release_pfn_clean(pfn
);
2614 if (is_hwpoison_pfn(pfn
)) {
2615 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2622 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2623 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2627 int level
= *levelp
;
2630 * Check if it's a transparent hugepage. If this would be an
2631 * hugetlbfs page, level wouldn't be set to
2632 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2635 if (!is_error_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2636 level
== PT_PAGE_TABLE_LEVEL
&&
2637 PageTransCompound(pfn_to_page(pfn
)) &&
2638 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2641 * mmu_notifier_retry was successful and we hold the
2642 * mmu_lock here, so the pmd can't become splitting
2643 * from under us, and in turn
2644 * __split_huge_page_refcount() can't run from under
2645 * us and we can safely transfer the refcount from
2646 * PG_tail to PG_head as we switch the pfn to tail to
2649 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2650 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2651 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2655 kvm_release_pfn_clean(pfn
);
2663 static bool mmu_invalid_pfn(pfn_t pfn
)
2665 return unlikely(is_invalid_pfn(pfn
));
2668 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2669 pfn_t pfn
, unsigned access
, int *ret_val
)
2673 /* The pfn is invalid, report the error! */
2674 if (unlikely(is_invalid_pfn(pfn
))) {
2675 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2679 if (unlikely(is_noslot_pfn(pfn
)))
2680 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2687 static bool page_fault_can_be_fast(struct kvm_vcpu
*vcpu
, u32 error_code
)
2690 * #PF can be fast only if the shadow page table is present and it
2691 * is caused by write-protect, that means we just need change the
2692 * W bit of the spte which can be done out of mmu-lock.
2694 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2695 !(error_code
& PFERR_WRITE_MASK
))
2702 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 spte
)
2704 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
2707 WARN_ON(!sp
->role
.direct
);
2710 * The gfn of direct spte is stable since it is calculated
2713 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2715 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2716 mark_page_dirty(vcpu
->kvm
, gfn
);
2723 * - true: let the vcpu to access on the same address again.
2724 * - false: let the real page fault path to fix it.
2726 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2729 struct kvm_shadow_walk_iterator iterator
;
2733 if (!page_fault_can_be_fast(vcpu
, error_code
))
2736 walk_shadow_page_lockless_begin(vcpu
);
2737 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2738 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2742 * If the mapping has been changed, let the vcpu fault on the
2743 * same address again.
2745 if (!is_rmap_spte(spte
)) {
2750 if (!is_last_spte(spte
, level
))
2754 * Check if it is a spurious fault caused by TLB lazily flushed.
2756 * Need not check the access of upper level table entries since
2757 * they are always ACC_ALL.
2759 if (is_writable_pte(spte
)) {
2765 * Currently, to simplify the code, only the spte write-protected
2766 * by dirty-log can be fast fixed.
2768 if (!spte_is_locklessly_modifiable(spte
))
2772 * Currently, fast page fault only works for direct mapping since
2773 * the gfn is not stable for indirect shadow page.
2774 * See Documentation/virtual/kvm/locking.txt to get more detail.
2776 ret
= fast_pf_fix_direct_spte(vcpu
, iterator
.sptep
, spte
);
2778 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
2780 walk_shadow_page_lockless_end(vcpu
);
2785 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2786 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2788 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
2789 gfn_t gfn
, bool prefault
)
2795 unsigned long mmu_seq
;
2796 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
2798 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2799 if (likely(!force_pt_level
)) {
2800 level
= mapping_level(vcpu
, gfn
);
2802 * This path builds a PAE pagetable - so we can map
2803 * 2mb pages at maximum. Therefore check if the level
2804 * is larger than that.
2806 if (level
> PT_DIRECTORY_LEVEL
)
2807 level
= PT_DIRECTORY_LEVEL
;
2809 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2811 level
= PT_PAGE_TABLE_LEVEL
;
2813 if (fast_page_fault(vcpu
, v
, level
, error_code
))
2816 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2819 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2822 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2825 spin_lock(&vcpu
->kvm
->mmu_lock
);
2826 if (mmu_notifier_retry(vcpu
, mmu_seq
))
2828 kvm_mmu_free_some_pages(vcpu
);
2829 if (likely(!force_pt_level
))
2830 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2831 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2833 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2839 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2840 kvm_release_pfn_clean(pfn
);
2845 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2848 struct kvm_mmu_page
*sp
;
2849 LIST_HEAD(invalid_list
);
2851 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2853 spin_lock(&vcpu
->kvm
->mmu_lock
);
2854 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2855 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2856 vcpu
->arch
.mmu
.direct_map
)) {
2857 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2859 sp
= page_header(root
);
2861 if (!sp
->root_count
&& sp
->role
.invalid
) {
2862 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2863 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2865 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2866 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2869 for (i
= 0; i
< 4; ++i
) {
2870 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2873 root
&= PT64_BASE_ADDR_MASK
;
2874 sp
= page_header(root
);
2876 if (!sp
->root_count
&& sp
->role
.invalid
)
2877 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2880 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2882 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2883 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2884 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2887 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2891 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2892 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2899 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2901 struct kvm_mmu_page
*sp
;
2904 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2905 spin_lock(&vcpu
->kvm
->mmu_lock
);
2906 kvm_mmu_free_some_pages(vcpu
);
2907 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2910 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2911 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2912 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2913 for (i
= 0; i
< 4; ++i
) {
2914 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2916 ASSERT(!VALID_PAGE(root
));
2917 spin_lock(&vcpu
->kvm
->mmu_lock
);
2918 kvm_mmu_free_some_pages(vcpu
);
2919 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2921 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2923 root
= __pa(sp
->spt
);
2925 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2926 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2928 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2935 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2937 struct kvm_mmu_page
*sp
;
2942 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2944 if (mmu_check_root(vcpu
, root_gfn
))
2948 * Do we shadow a long mode page table? If so we need to
2949 * write-protect the guests page table root.
2951 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2952 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2954 ASSERT(!VALID_PAGE(root
));
2956 spin_lock(&vcpu
->kvm
->mmu_lock
);
2957 kvm_mmu_free_some_pages(vcpu
);
2958 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
2960 root
= __pa(sp
->spt
);
2962 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2963 vcpu
->arch
.mmu
.root_hpa
= root
;
2968 * We shadow a 32 bit page table. This may be a legacy 2-level
2969 * or a PAE 3-level page table. In either case we need to be aware that
2970 * the shadow page table may be a PAE or a long mode page table.
2972 pm_mask
= PT_PRESENT_MASK
;
2973 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
2974 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
2976 for (i
= 0; i
< 4; ++i
) {
2977 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2979 ASSERT(!VALID_PAGE(root
));
2980 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
2981 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
2982 if (!is_present_gpte(pdptr
)) {
2983 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
2986 root_gfn
= pdptr
>> PAGE_SHIFT
;
2987 if (mmu_check_root(vcpu
, root_gfn
))
2990 spin_lock(&vcpu
->kvm
->mmu_lock
);
2991 kvm_mmu_free_some_pages(vcpu
);
2992 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
2995 root
= __pa(sp
->spt
);
2997 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2999 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3001 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3004 * If we shadow a 32 bit page table with a long mode page
3005 * table we enter this path.
3007 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3008 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3010 * The additional page necessary for this is only
3011 * allocated on demand.
3016 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3017 if (lm_root
== NULL
)
3020 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3022 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3025 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3031 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3033 if (vcpu
->arch
.mmu
.direct_map
)
3034 return mmu_alloc_direct_roots(vcpu
);
3036 return mmu_alloc_shadow_roots(vcpu
);
3039 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3042 struct kvm_mmu_page
*sp
;
3044 if (vcpu
->arch
.mmu
.direct_map
)
3047 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3050 vcpu_clear_mmio_info(vcpu
, ~0ul);
3051 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3052 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3053 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3054 sp
= page_header(root
);
3055 mmu_sync_children(vcpu
, sp
);
3056 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3059 for (i
= 0; i
< 4; ++i
) {
3060 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3062 if (root
&& VALID_PAGE(root
)) {
3063 root
&= PT64_BASE_ADDR_MASK
;
3064 sp
= page_header(root
);
3065 mmu_sync_children(vcpu
, sp
);
3068 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3071 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3073 spin_lock(&vcpu
->kvm
->mmu_lock
);
3074 mmu_sync_roots(vcpu
);
3075 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3078 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3079 u32 access
, struct x86_exception
*exception
)
3082 exception
->error_code
= 0;
3086 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3088 struct x86_exception
*exception
)
3091 exception
->error_code
= 0;
3092 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
3095 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3098 return vcpu_match_mmio_gpa(vcpu
, addr
);
3100 return vcpu_match_mmio_gva(vcpu
, addr
);
3105 * On direct hosts, the last spte is only allows two states
3106 * for mmio page fault:
3107 * - It is the mmio spte
3108 * - It is zapped or it is being zapped.
3110 * This function completely checks the spte when the last spte
3111 * is not the mmio spte.
3113 static bool check_direct_spte_mmio_pf(u64 spte
)
3115 return __check_direct_spte_mmio_pf(spte
);
3118 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
3120 struct kvm_shadow_walk_iterator iterator
;
3123 walk_shadow_page_lockless_begin(vcpu
);
3124 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
3125 if (!is_shadow_present_pte(spte
))
3127 walk_shadow_page_lockless_end(vcpu
);
3133 * If it is a real mmio page fault, return 1 and emulat the instruction
3134 * directly, return 0 to let CPU fault again on the address, -1 is
3135 * returned if bug is detected.
3137 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3141 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
3144 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
3146 if (is_mmio_spte(spte
)) {
3147 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3148 unsigned access
= get_mmio_spte_access(spte
);
3153 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3154 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3159 * It's ok if the gva is remapped by other cpus on shadow guest,
3160 * it's a BUG if the gfn is not a mmio page.
3162 if (direct
&& !check_direct_spte_mmio_pf(spte
))
3166 * If the page table is zapped by other cpus, let CPU fault again on
3171 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
3173 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
3174 u32 error_code
, bool direct
)
3178 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
3183 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3184 u32 error_code
, bool prefault
)
3189 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3191 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3192 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
3194 r
= mmu_topup_memory_caches(vcpu
);
3199 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3201 gfn
= gva
>> PAGE_SHIFT
;
3203 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3204 error_code
, gfn
, prefault
);
3207 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3209 struct kvm_arch_async_pf arch
;
3211 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3213 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3214 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3216 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3219 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3221 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3222 kvm_event_needs_reinjection(vcpu
)))
3225 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3228 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3229 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3233 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3236 return false; /* *pfn has correct page already */
3238 put_page(pfn_to_page(*pfn
));
3240 if (!prefault
&& can_do_async_pf(vcpu
)) {
3241 trace_kvm_try_async_get_page(gva
, gfn
);
3242 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3243 trace_kvm_async_pf_doublefault(gva
, gfn
);
3244 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3246 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3250 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3255 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3262 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3263 unsigned long mmu_seq
;
3264 int write
= error_code
& PFERR_WRITE_MASK
;
3268 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3270 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3271 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3273 r
= mmu_topup_memory_caches(vcpu
);
3277 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3278 if (likely(!force_pt_level
)) {
3279 level
= mapping_level(vcpu
, gfn
);
3280 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3282 level
= PT_PAGE_TABLE_LEVEL
;
3284 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3287 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3290 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3293 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3296 spin_lock(&vcpu
->kvm
->mmu_lock
);
3297 if (mmu_notifier_retry(vcpu
, mmu_seq
))
3299 kvm_mmu_free_some_pages(vcpu
);
3300 if (likely(!force_pt_level
))
3301 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3302 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3303 level
, gfn
, pfn
, prefault
);
3304 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3309 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3310 kvm_release_pfn_clean(pfn
);
3314 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3316 mmu_free_roots(vcpu
);
3319 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3320 struct kvm_mmu
*context
)
3322 context
->new_cr3
= nonpaging_new_cr3
;
3323 context
->page_fault
= nonpaging_page_fault
;
3324 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3325 context
->free
= nonpaging_free
;
3326 context
->sync_page
= nonpaging_sync_page
;
3327 context
->invlpg
= nonpaging_invlpg
;
3328 context
->update_pte
= nonpaging_update_pte
;
3329 context
->root_level
= 0;
3330 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3331 context
->root_hpa
= INVALID_PAGE
;
3332 context
->direct_map
= true;
3333 context
->nx
= false;
3337 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3339 ++vcpu
->stat
.tlb_flush
;
3340 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3343 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3345 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3346 mmu_free_roots(vcpu
);
3349 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3351 return kvm_read_cr3(vcpu
);
3354 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3355 struct x86_exception
*fault
)
3357 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3360 static void paging_free(struct kvm_vcpu
*vcpu
)
3362 nonpaging_free(vcpu
);
3365 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3369 bit7
= (gpte
>> 7) & 1;
3370 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
3373 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3376 if (unlikely(is_mmio_spte(*sptep
))) {
3377 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3378 mmu_spte_clear_no_track(sptep
);
3383 mark_mmio_spte(sptep
, gfn
, access
);
3391 #include "paging_tmpl.h"
3395 #include "paging_tmpl.h"
3398 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3399 struct kvm_mmu
*context
)
3401 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3402 u64 exb_bit_rsvd
= 0;
3405 exb_bit_rsvd
= rsvd_bits(63, 63);
3406 switch (context
->root_level
) {
3407 case PT32_ROOT_LEVEL
:
3408 /* no rsvd bits for 2 level 4K page table entries */
3409 context
->rsvd_bits_mask
[0][1] = 0;
3410 context
->rsvd_bits_mask
[0][0] = 0;
3411 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3413 if (!is_pse(vcpu
)) {
3414 context
->rsvd_bits_mask
[1][1] = 0;
3418 if (is_cpuid_PSE36())
3419 /* 36bits PSE 4MB page */
3420 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3422 /* 32 bits PSE 4MB page */
3423 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3425 case PT32E_ROOT_LEVEL
:
3426 context
->rsvd_bits_mask
[0][2] =
3427 rsvd_bits(maxphyaddr
, 63) |
3428 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3429 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3430 rsvd_bits(maxphyaddr
, 62); /* PDE */
3431 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3432 rsvd_bits(maxphyaddr
, 62); /* PTE */
3433 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3434 rsvd_bits(maxphyaddr
, 62) |
3435 rsvd_bits(13, 20); /* large page */
3436 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3438 case PT64_ROOT_LEVEL
:
3439 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3440 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3441 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3442 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3443 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3444 rsvd_bits(maxphyaddr
, 51);
3445 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3446 rsvd_bits(maxphyaddr
, 51);
3447 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3448 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3449 rsvd_bits(maxphyaddr
, 51) |
3451 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3452 rsvd_bits(maxphyaddr
, 51) |
3453 rsvd_bits(13, 20); /* large page */
3454 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3459 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3460 struct kvm_mmu
*context
,
3463 context
->nx
= is_nx(vcpu
);
3464 context
->root_level
= level
;
3466 reset_rsvds_bits_mask(vcpu
, context
);
3468 ASSERT(is_pae(vcpu
));
3469 context
->new_cr3
= paging_new_cr3
;
3470 context
->page_fault
= paging64_page_fault
;
3471 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3472 context
->sync_page
= paging64_sync_page
;
3473 context
->invlpg
= paging64_invlpg
;
3474 context
->update_pte
= paging64_update_pte
;
3475 context
->free
= paging_free
;
3476 context
->shadow_root_level
= level
;
3477 context
->root_hpa
= INVALID_PAGE
;
3478 context
->direct_map
= false;
3482 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3483 struct kvm_mmu
*context
)
3485 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3488 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3489 struct kvm_mmu
*context
)
3491 context
->nx
= false;
3492 context
->root_level
= PT32_ROOT_LEVEL
;
3494 reset_rsvds_bits_mask(vcpu
, context
);
3496 context
->new_cr3
= paging_new_cr3
;
3497 context
->page_fault
= paging32_page_fault
;
3498 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3499 context
->free
= paging_free
;
3500 context
->sync_page
= paging32_sync_page
;
3501 context
->invlpg
= paging32_invlpg
;
3502 context
->update_pte
= paging32_update_pte
;
3503 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3504 context
->root_hpa
= INVALID_PAGE
;
3505 context
->direct_map
= false;
3509 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3510 struct kvm_mmu
*context
)
3512 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3515 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3517 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3519 context
->base_role
.word
= 0;
3520 context
->new_cr3
= nonpaging_new_cr3
;
3521 context
->page_fault
= tdp_page_fault
;
3522 context
->free
= nonpaging_free
;
3523 context
->sync_page
= nonpaging_sync_page
;
3524 context
->invlpg
= nonpaging_invlpg
;
3525 context
->update_pte
= nonpaging_update_pte
;
3526 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3527 context
->root_hpa
= INVALID_PAGE
;
3528 context
->direct_map
= true;
3529 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3530 context
->get_cr3
= get_cr3
;
3531 context
->get_pdptr
= kvm_pdptr_read
;
3532 context
->inject_page_fault
= kvm_inject_page_fault
;
3534 if (!is_paging(vcpu
)) {
3535 context
->nx
= false;
3536 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3537 context
->root_level
= 0;
3538 } else if (is_long_mode(vcpu
)) {
3539 context
->nx
= is_nx(vcpu
);
3540 context
->root_level
= PT64_ROOT_LEVEL
;
3541 reset_rsvds_bits_mask(vcpu
, context
);
3542 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3543 } else if (is_pae(vcpu
)) {
3544 context
->nx
= is_nx(vcpu
);
3545 context
->root_level
= PT32E_ROOT_LEVEL
;
3546 reset_rsvds_bits_mask(vcpu
, context
);
3547 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3549 context
->nx
= false;
3550 context
->root_level
= PT32_ROOT_LEVEL
;
3551 reset_rsvds_bits_mask(vcpu
, context
);
3552 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3558 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3561 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3563 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3565 if (!is_paging(vcpu
))
3566 r
= nonpaging_init_context(vcpu
, context
);
3567 else if (is_long_mode(vcpu
))
3568 r
= paging64_init_context(vcpu
, context
);
3569 else if (is_pae(vcpu
))
3570 r
= paging32E_init_context(vcpu
, context
);
3572 r
= paging32_init_context(vcpu
, context
);
3574 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3575 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3576 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3577 = smep
&& !is_write_protection(vcpu
);
3581 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3583 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3585 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3587 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3588 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3589 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3590 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3595 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3597 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3599 g_context
->get_cr3
= get_cr3
;
3600 g_context
->get_pdptr
= kvm_pdptr_read
;
3601 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3604 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3605 * translation of l2_gpa to l1_gpa addresses is done using the
3606 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3607 * functions between mmu and nested_mmu are swapped.
3609 if (!is_paging(vcpu
)) {
3610 g_context
->nx
= false;
3611 g_context
->root_level
= 0;
3612 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3613 } else if (is_long_mode(vcpu
)) {
3614 g_context
->nx
= is_nx(vcpu
);
3615 g_context
->root_level
= PT64_ROOT_LEVEL
;
3616 reset_rsvds_bits_mask(vcpu
, g_context
);
3617 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3618 } else if (is_pae(vcpu
)) {
3619 g_context
->nx
= is_nx(vcpu
);
3620 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3621 reset_rsvds_bits_mask(vcpu
, g_context
);
3622 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3624 g_context
->nx
= false;
3625 g_context
->root_level
= PT32_ROOT_LEVEL
;
3626 reset_rsvds_bits_mask(vcpu
, g_context
);
3627 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3633 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3635 if (mmu_is_nested(vcpu
))
3636 return init_kvm_nested_mmu(vcpu
);
3637 else if (tdp_enabled
)
3638 return init_kvm_tdp_mmu(vcpu
);
3640 return init_kvm_softmmu(vcpu
);
3643 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3646 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3647 /* mmu.free() should set root_hpa = INVALID_PAGE */
3648 vcpu
->arch
.mmu
.free(vcpu
);
3651 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3653 destroy_kvm_mmu(vcpu
);
3654 return init_kvm_mmu(vcpu
);
3656 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3658 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3662 r
= mmu_topup_memory_caches(vcpu
);
3665 r
= mmu_alloc_roots(vcpu
);
3666 spin_lock(&vcpu
->kvm
->mmu_lock
);
3667 mmu_sync_roots(vcpu
);
3668 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3671 /* set_cr3() should ensure TLB has been flushed */
3672 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3676 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3678 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3680 mmu_free_roots(vcpu
);
3682 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3684 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3685 struct kvm_mmu_page
*sp
, u64
*spte
,
3688 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3689 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3693 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3694 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3697 static bool need_remote_flush(u64 old
, u64
new)
3699 if (!is_shadow_present_pte(old
))
3701 if (!is_shadow_present_pte(new))
3703 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3705 old
^= PT64_NX_MASK
;
3706 new ^= PT64_NX_MASK
;
3707 return (old
& ~new & PT64_PERM_MASK
) != 0;
3710 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3711 bool remote_flush
, bool local_flush
)
3717 kvm_flush_remote_tlbs(vcpu
->kvm
);
3718 else if (local_flush
)
3719 kvm_mmu_flush_tlb(vcpu
);
3722 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
3723 const u8
*new, int *bytes
)
3729 * Assume that the pte write on a page table of the same type
3730 * as the current vcpu paging mode since we update the sptes only
3731 * when they have the same mode.
3733 if (is_pae(vcpu
) && *bytes
== 4) {
3734 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3737 r
= kvm_read_guest(vcpu
->kvm
, *gpa
, &gentry
, min(*bytes
, 8));
3740 new = (const u8
*)&gentry
;
3745 gentry
= *(const u32
*)new;
3748 gentry
= *(const u64
*)new;
3759 * If we're seeing too many writes to a page, it may no longer be a page table,
3760 * or we may be forking, in which case it is better to unmap the page.
3762 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
3765 * Skip write-flooding detected for the sp whose level is 1, because
3766 * it can become unsync, then the guest page is not write-protected.
3768 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
3771 return ++sp
->write_flooding_count
>= 3;
3775 * Misaligned accesses are too much trouble to fix up; also, they usually
3776 * indicate a page is not used as a page table.
3778 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
3781 unsigned offset
, pte_size
, misaligned
;
3783 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3784 gpa
, bytes
, sp
->role
.word
);
3786 offset
= offset_in_page(gpa
);
3787 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3790 * Sometimes, the OS only writes the last one bytes to update status
3791 * bits, for example, in linux, andb instruction is used in clear_bit().
3793 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
3796 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3797 misaligned
|= bytes
< 4;
3802 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
3804 unsigned page_offset
, quadrant
;
3808 page_offset
= offset_in_page(gpa
);
3809 level
= sp
->role
.level
;
3811 if (!sp
->role
.cr4_pae
) {
3812 page_offset
<<= 1; /* 32->64 */
3814 * A 32-bit pde maps 4MB while the shadow pdes map
3815 * only 2MB. So we need to double the offset again
3816 * and zap two pdes instead of one.
3818 if (level
== PT32_ROOT_LEVEL
) {
3819 page_offset
&= ~7; /* kill rounding error */
3823 quadrant
= page_offset
>> PAGE_SHIFT
;
3824 page_offset
&= ~PAGE_MASK
;
3825 if (quadrant
!= sp
->role
.quadrant
)
3829 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3833 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3834 const u8
*new, int bytes
)
3836 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3837 union kvm_mmu_page_role mask
= { .word
= 0 };
3838 struct kvm_mmu_page
*sp
;
3839 struct hlist_node
*node
;
3840 LIST_HEAD(invalid_list
);
3841 u64 entry
, gentry
, *spte
;
3843 bool remote_flush
, local_flush
, zap_page
;
3846 * If we don't have indirect shadow pages, it means no page is
3847 * write-protected, so we can exit simply.
3849 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3852 zap_page
= remote_flush
= local_flush
= false;
3854 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3856 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
3859 * No need to care whether allocation memory is successful
3860 * or not since pte prefetch is skiped if it does not have
3861 * enough objects in the cache.
3863 mmu_topup_memory_caches(vcpu
);
3865 spin_lock(&vcpu
->kvm
->mmu_lock
);
3866 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3867 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3869 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3870 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
, node
) {
3871 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
3872 detect_write_flooding(sp
)) {
3873 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3875 ++vcpu
->kvm
->stat
.mmu_flooded
;
3879 spte
= get_written_sptes(sp
, gpa
, &npte
);
3886 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
3888 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
3889 & mask
.word
) && rmap_can_add(vcpu
))
3890 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
3891 if (!remote_flush
&& need_remote_flush(entry
, *spte
))
3892 remote_flush
= true;
3896 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
3897 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3898 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
3899 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3902 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
3907 if (vcpu
->arch
.mmu
.direct_map
)
3910 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
3912 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
3916 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
3918 void __kvm_mmu_free_some_pages(struct kvm_vcpu
*vcpu
)
3920 LIST_HEAD(invalid_list
);
3922 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
&&
3923 !list_empty(&vcpu
->kvm
->arch
.active_mmu_pages
)) {
3924 struct kvm_mmu_page
*sp
;
3926 sp
= container_of(vcpu
->kvm
->arch
.active_mmu_pages
.prev
,
3927 struct kvm_mmu_page
, link
);
3928 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3929 ++vcpu
->kvm
->stat
.mmu_recycled
;
3931 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3934 static bool is_mmio_page_fault(struct kvm_vcpu
*vcpu
, gva_t addr
)
3936 if (vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
))
3937 return vcpu_match_mmio_gpa(vcpu
, addr
);
3939 return vcpu_match_mmio_gva(vcpu
, addr
);
3942 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
3943 void *insn
, int insn_len
)
3945 int r
, emulation_type
= EMULTYPE_RETRY
;
3946 enum emulation_result er
;
3948 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
3957 if (is_mmio_page_fault(vcpu
, cr2
))
3960 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
3965 case EMULATE_DO_MMIO
:
3966 ++vcpu
->stat
.mmio_exits
;
3976 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
3978 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
3980 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
3981 kvm_mmu_flush_tlb(vcpu
);
3982 ++vcpu
->stat
.invlpg
;
3984 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
3986 void kvm_enable_tdp(void)
3990 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
3992 void kvm_disable_tdp(void)
3994 tdp_enabled
= false;
3996 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
3998 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4000 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4001 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4002 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4005 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4013 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4014 * Therefore we need to allocate shadow page tables in the first
4015 * 4GB of memory, which happens to fit the DMA32 zone.
4017 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4021 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4022 for (i
= 0; i
< 4; ++i
)
4023 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4028 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4032 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4033 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4034 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4035 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4037 return alloc_mmu_pages(vcpu
);
4040 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4043 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4045 return init_kvm_mmu(vcpu
);
4048 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
4050 struct kvm_mmu_page
*sp
;
4053 list_for_each_entry(sp
, &kvm
->arch
.active_mmu_pages
, link
) {
4057 if (!test_bit(slot
, sp
->slot_bitmap
))
4061 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
) {
4062 if (!is_shadow_present_pte(pt
[i
]) ||
4063 !is_last_spte(pt
[i
], sp
->role
.level
))
4066 spte_write_protect(kvm
, &pt
[i
], &flush
, false);
4069 kvm_flush_remote_tlbs(kvm
);
4072 void kvm_mmu_zap_all(struct kvm
*kvm
)
4074 struct kvm_mmu_page
*sp
, *node
;
4075 LIST_HEAD(invalid_list
);
4077 spin_lock(&kvm
->mmu_lock
);
4079 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
)
4080 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
4083 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4084 spin_unlock(&kvm
->mmu_lock
);
4087 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm
*kvm
,
4088 struct list_head
*invalid_list
)
4090 struct kvm_mmu_page
*page
;
4092 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
4093 struct kvm_mmu_page
, link
);
4094 kvm_mmu_prepare_zap_page(kvm
, page
, invalid_list
);
4097 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
4100 int nr_to_scan
= sc
->nr_to_scan
;
4102 if (nr_to_scan
== 0)
4105 raw_spin_lock(&kvm_lock
);
4107 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4109 LIST_HEAD(invalid_list
);
4112 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4113 * here. We may skip a VM instance errorneosly, but we do not
4114 * want to shrink a VM that only started to populate its MMU
4117 if (kvm
->arch
.n_used_mmu_pages
> 0) {
4123 idx
= srcu_read_lock(&kvm
->srcu
);
4124 spin_lock(&kvm
->mmu_lock
);
4126 kvm_mmu_remove_some_alloc_mmu_pages(kvm
, &invalid_list
);
4127 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4129 spin_unlock(&kvm
->mmu_lock
);
4130 srcu_read_unlock(&kvm
->srcu
, idx
);
4132 list_move_tail(&kvm
->vm_list
, &vm_list
);
4136 raw_spin_unlock(&kvm_lock
);
4139 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
4142 static struct shrinker mmu_shrinker
= {
4143 .shrink
= mmu_shrink
,
4144 .seeks
= DEFAULT_SEEKS
* 10,
4147 static void mmu_destroy_caches(void)
4149 if (pte_list_desc_cache
)
4150 kmem_cache_destroy(pte_list_desc_cache
);
4151 if (mmu_page_header_cache
)
4152 kmem_cache_destroy(mmu_page_header_cache
);
4155 int kvm_mmu_module_init(void)
4157 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
4158 sizeof(struct pte_list_desc
),
4160 if (!pte_list_desc_cache
)
4163 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
4164 sizeof(struct kvm_mmu_page
),
4166 if (!mmu_page_header_cache
)
4169 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
4172 register_shrinker(&mmu_shrinker
);
4177 mmu_destroy_caches();
4182 * Caculate mmu pages needed for kvm.
4184 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
4186 unsigned int nr_mmu_pages
;
4187 unsigned int nr_pages
= 0;
4188 struct kvm_memslots
*slots
;
4189 struct kvm_memory_slot
*memslot
;
4191 slots
= kvm_memslots(kvm
);
4193 kvm_for_each_memslot(memslot
, slots
)
4194 nr_pages
+= memslot
->npages
;
4196 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
4197 nr_mmu_pages
= max(nr_mmu_pages
,
4198 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
4200 return nr_mmu_pages
;
4203 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4205 struct kvm_shadow_walk_iterator iterator
;
4209 walk_shadow_page_lockless_begin(vcpu
);
4210 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4211 sptes
[iterator
.level
-1] = spte
;
4213 if (!is_shadow_present_pte(spte
))
4216 walk_shadow_page_lockless_end(vcpu
);
4220 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4222 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4226 destroy_kvm_mmu(vcpu
);
4227 free_mmu_pages(vcpu
);
4228 mmu_free_memory_caches(vcpu
);
4231 void kvm_mmu_module_exit(void)
4233 mmu_destroy_caches();
4234 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4235 unregister_shrinker(&mmu_shrinker
);
4236 mmu_audit_disable();