2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg
, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc
{
157 u64
*sptes
[PTE_LIST_EXT
];
158 struct pte_list_desc
*more
;
161 struct kvm_shadow_walk_iterator
{
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache
*pte_list_desc_cache
;
181 static struct kmem_cache
*mmu_page_header_cache
;
182 static struct percpu_counter kvm_total_used_mmu_pages
;
184 static u64 __read_mostly shadow_nx_mask
;
185 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask
;
187 static u64 __read_mostly shadow_accessed_mask
;
188 static u64 __read_mostly shadow_dirty_mask
;
189 static u64 __read_mostly shadow_mmio_mask
;
191 static void mmu_spte_set(u64
*sptep
, u64 spte
);
192 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
196 shadow_mmio_mask
= mmio_mask
;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
200 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
202 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
204 trace_mark_mmio_spte(sptep
, gfn
, access
);
205 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
208 static bool is_mmio_spte(u64 spte
)
210 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
213 static gfn_t
get_mmio_spte_gfn(u64 spte
)
215 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
218 static unsigned get_mmio_spte_access(u64 spte
)
220 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
223 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
225 if (unlikely(is_noslot_pfn(pfn
))) {
226 mark_mmio_spte(sptep
, gfn
, access
);
233 static inline u64
rsvd_bits(int s
, int e
)
235 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
238 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
239 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
241 shadow_user_mask
= user_mask
;
242 shadow_accessed_mask
= accessed_mask
;
243 shadow_dirty_mask
= dirty_mask
;
244 shadow_nx_mask
= nx_mask
;
245 shadow_x_mask
= x_mask
;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu
*vcpu
)
256 return vcpu
->arch
.efer
& EFER_NX
;
259 static int is_shadow_present_pte(u64 pte
)
261 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
264 static int is_large_pte(u64 pte
)
266 return pte
& PT_PAGE_SIZE_MASK
;
269 static int is_dirty_gpte(unsigned long pte
)
271 return pte
& PT_DIRTY_MASK
;
274 static int is_rmap_spte(u64 pte
)
276 return is_shadow_present_pte(pte
);
279 static int is_last_spte(u64 pte
, int level
)
281 if (level
== PT_PAGE_TABLE_LEVEL
)
283 if (is_large_pte(pte
))
288 static pfn_t
spte_to_pfn(u64 pte
)
290 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
293 static gfn_t
pse36_gfn_delta(u32 gpte
)
295 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
297 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
301 static void __set_spte(u64
*sptep
, u64 spte
)
306 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
311 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
313 return xchg(sptep
, spte
);
316 static u64
__get_spte_lockless(u64
*sptep
)
318 return ACCESS_ONCE(*sptep
);
321 static bool __check_direct_spte_mmio_pf(u64 spte
)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64
*sptep
, u64 spte
)
337 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
339 if (is_shadow_present_pte(spte
))
342 /* Ensure the spte is completely set before we increase the count */
344 sp
->clear_spte_count
++;
347 static void __set_spte(u64
*sptep
, u64 spte
)
349 union split_spte
*ssptep
, sspte
;
351 ssptep
= (union split_spte
*)sptep
;
352 sspte
= (union split_spte
)spte
;
354 ssptep
->spte_high
= sspte
.spte_high
;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep
->spte_low
= sspte
.spte_low
;
366 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
368 union split_spte
*ssptep
, sspte
;
370 ssptep
= (union split_spte
*)sptep
;
371 sspte
= (union split_spte
)spte
;
373 ssptep
->spte_low
= sspte
.spte_low
;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep
->spte_high
= sspte
.spte_high
;
382 count_spte_clear(sptep
, spte
);
385 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
387 union split_spte
*ssptep
, sspte
, orig
;
389 ssptep
= (union split_spte
*)sptep
;
390 sspte
= (union split_spte
)spte
;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
394 orig
.spte_high
= ssptep
->spte_high
;
395 ssptep
->spte_high
= sspte
.spte_high
;
396 count_spte_clear(sptep
, spte
);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64
__get_spte_lockless(u64
*sptep
)
410 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
411 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
415 count
= sp
->clear_spte_count
;
418 spte
.spte_low
= orig
->spte_low
;
421 spte
.spte_high
= orig
->spte_high
;
424 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
425 count
!= sp
->clear_spte_count
))
431 static bool __check_direct_spte_mmio_pf(u64 spte
)
433 union split_spte sspte
= (union split_spte
)spte
;
434 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte
.spte_low
== 0ull &&
442 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
449 static bool spte_is_locklessly_modifiable(u64 spte
)
451 return !(~spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
));
454 static bool spte_has_volatile_bits(u64 spte
)
457 * Always atomicly update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_is_locklessly_modifiable(spte
))
465 if (!shadow_accessed_mask
)
468 if (!is_shadow_present_pte(spte
))
471 if ((spte
& shadow_accessed_mask
) &&
472 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
478 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
480 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
483 /* Rules for using mmu_spte_set:
484 * Set the sptep from nonpresent to present.
485 * Note: the sptep being assigned *must* be either not present
486 * or in a state where the hardware will not attempt to update
489 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
491 WARN_ON(is_shadow_present_pte(*sptep
));
492 __set_spte(sptep
, new_spte
);
495 /* Rules for using mmu_spte_update:
496 * Update the state bits, it means the mapped pfn is not changged.
498 * Whenever we overwrite a writable spte with a read-only one we
499 * should flush remote TLBs. Otherwise rmap_write_protect
500 * will find a read-only spte, even though the writable spte
501 * might be cached on a CPU's TLB, the return value indicates this
504 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
506 u64 old_spte
= *sptep
;
509 WARN_ON(!is_rmap_spte(new_spte
));
511 if (!is_shadow_present_pte(old_spte
)) {
512 mmu_spte_set(sptep
, new_spte
);
516 if (!spte_has_volatile_bits(old_spte
))
517 __update_clear_spte_fast(sptep
, new_spte
);
519 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
522 * For the spte updated out of mmu-lock is safe, since
523 * we always atomicly update it, see the comments in
524 * spte_has_volatile_bits().
526 if (is_writable_pte(old_spte
) && !is_writable_pte(new_spte
))
529 if (!shadow_accessed_mask
)
532 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
533 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
534 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
535 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
541 * Rules for using mmu_spte_clear_track_bits:
542 * It sets the sptep from present to nonpresent, and track the
543 * state bits, it is used to clear the last level sptep.
545 static int mmu_spte_clear_track_bits(u64
*sptep
)
548 u64 old_spte
= *sptep
;
550 if (!spte_has_volatile_bits(old_spte
))
551 __update_clear_spte_fast(sptep
, 0ull);
553 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
555 if (!is_rmap_spte(old_spte
))
558 pfn
= spte_to_pfn(old_spte
);
559 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
560 kvm_set_pfn_accessed(pfn
);
561 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
562 kvm_set_pfn_dirty(pfn
);
567 * Rules for using mmu_spte_clear_no_track:
568 * Directly clear spte without caring the state bits of sptep,
569 * it is used to set the upper level spte.
571 static void mmu_spte_clear_no_track(u64
*sptep
)
573 __update_clear_spte_fast(sptep
, 0ull);
576 static u64
mmu_spte_get_lockless(u64
*sptep
)
578 return __get_spte_lockless(sptep
);
581 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
584 * Prevent page table teardown by making any free-er wait during
585 * kvm_flush_remote_tlbs() IPI to all active vcpus.
588 vcpu
->mode
= READING_SHADOW_PAGE_TABLES
;
590 * Make sure a following spte read is not reordered ahead of the write
596 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
599 * Make sure the write to vcpu->mode is not reordered in front of
600 * reads to sptes. If it does, kvm_commit_zap_page() can see us
601 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
604 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
608 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
609 struct kmem_cache
*base_cache
, int min
)
613 if (cache
->nobjs
>= min
)
615 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
616 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
619 cache
->objects
[cache
->nobjs
++] = obj
;
624 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
629 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
630 struct kmem_cache
*cache
)
633 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
636 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
641 if (cache
->nobjs
>= min
)
643 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
644 page
= (void *)__get_free_page(GFP_KERNEL
);
647 cache
->objects
[cache
->nobjs
++] = page
;
652 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
655 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
658 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
662 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
663 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
666 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
669 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
670 mmu_page_header_cache
, 4);
675 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
677 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
678 pte_list_desc_cache
);
679 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
680 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
681 mmu_page_header_cache
);
684 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
689 p
= mc
->objects
[--mc
->nobjs
];
693 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
695 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
698 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
700 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
703 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
705 if (!sp
->role
.direct
)
706 return sp
->gfns
[index
];
708 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
711 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
714 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
716 sp
->gfns
[index
] = gfn
;
720 * Return the pointer to the large page information for a given gfn,
721 * handling slots that are not large page aligned.
723 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
724 struct kvm_memory_slot
*slot
,
729 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
730 return &slot
->arch
.lpage_info
[level
- 2][idx
];
733 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
735 struct kvm_memory_slot
*slot
;
736 struct kvm_lpage_info
*linfo
;
739 slot
= gfn_to_memslot(kvm
, gfn
);
740 for (i
= PT_DIRECTORY_LEVEL
;
741 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
742 linfo
= lpage_info_slot(gfn
, slot
, i
);
743 linfo
->write_count
+= 1;
745 kvm
->arch
.indirect_shadow_pages
++;
748 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
750 struct kvm_memory_slot
*slot
;
751 struct kvm_lpage_info
*linfo
;
754 slot
= gfn_to_memslot(kvm
, gfn
);
755 for (i
= PT_DIRECTORY_LEVEL
;
756 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
757 linfo
= lpage_info_slot(gfn
, slot
, i
);
758 linfo
->write_count
-= 1;
759 WARN_ON(linfo
->write_count
< 0);
761 kvm
->arch
.indirect_shadow_pages
--;
764 static int has_wrprotected_page(struct kvm
*kvm
,
768 struct kvm_memory_slot
*slot
;
769 struct kvm_lpage_info
*linfo
;
771 slot
= gfn_to_memslot(kvm
, gfn
);
773 linfo
= lpage_info_slot(gfn
, slot
, level
);
774 return linfo
->write_count
;
780 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
782 unsigned long page_size
;
785 page_size
= kvm_host_page_size(kvm
, gfn
);
787 for (i
= PT_PAGE_TABLE_LEVEL
;
788 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
789 if (page_size
>= KVM_HPAGE_SIZE(i
))
798 static struct kvm_memory_slot
*
799 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
802 struct kvm_memory_slot
*slot
;
804 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
805 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
806 (no_dirty_log
&& slot
->dirty_bitmap
))
812 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
814 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
817 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
819 int host_level
, level
, max_level
;
821 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
823 if (host_level
== PT_PAGE_TABLE_LEVEL
)
826 max_level
= kvm_x86_ops
->get_lpage_level() < host_level
?
827 kvm_x86_ops
->get_lpage_level() : host_level
;
829 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
830 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
837 * Pte mapping structures:
839 * If pte_list bit zero is zero, then pte_list point to the spte.
841 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
842 * pte_list_desc containing more mappings.
844 * Returns the number of pte entries before the spte was added or zero if
845 * the spte was not added.
848 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
849 unsigned long *pte_list
)
851 struct pte_list_desc
*desc
;
855 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
856 *pte_list
= (unsigned long)spte
;
857 } else if (!(*pte_list
& 1)) {
858 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
859 desc
= mmu_alloc_pte_list_desc(vcpu
);
860 desc
->sptes
[0] = (u64
*)*pte_list
;
861 desc
->sptes
[1] = spte
;
862 *pte_list
= (unsigned long)desc
| 1;
865 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
866 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
867 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
869 count
+= PTE_LIST_EXT
;
871 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
872 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
875 for (i
= 0; desc
->sptes
[i
]; ++i
)
877 desc
->sptes
[i
] = spte
;
883 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
884 int i
, struct pte_list_desc
*prev_desc
)
888 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
890 desc
->sptes
[i
] = desc
->sptes
[j
];
891 desc
->sptes
[j
] = NULL
;
894 if (!prev_desc
&& !desc
->more
)
895 *pte_list
= (unsigned long)desc
->sptes
[0];
898 prev_desc
->more
= desc
->more
;
900 *pte_list
= (unsigned long)desc
->more
| 1;
901 mmu_free_pte_list_desc(desc
);
904 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
906 struct pte_list_desc
*desc
;
907 struct pte_list_desc
*prev_desc
;
911 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
913 } else if (!(*pte_list
& 1)) {
914 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
915 if ((u64
*)*pte_list
!= spte
) {
916 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
921 rmap_printk("pte_list_remove: %p many->many\n", spte
);
922 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
925 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
926 if (desc
->sptes
[i
] == spte
) {
927 pte_list_desc_remove_entry(pte_list
,
935 pr_err("pte_list_remove: %p many->many\n", spte
);
940 typedef void (*pte_list_walk_fn
) (u64
*spte
);
941 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
943 struct pte_list_desc
*desc
;
949 if (!(*pte_list
& 1))
950 return fn((u64
*)*pte_list
);
952 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
954 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
960 static unsigned long *__gfn_to_rmap(gfn_t gfn
, int level
,
961 struct kvm_memory_slot
*slot
)
963 struct kvm_lpage_info
*linfo
;
965 if (likely(level
== PT_PAGE_TABLE_LEVEL
))
966 return &slot
->rmap
[gfn
- slot
->base_gfn
];
968 linfo
= lpage_info_slot(gfn
, slot
, level
);
969 return &linfo
->rmap_pde
;
973 * Take gfn and return the reverse mapping to it.
975 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
977 struct kvm_memory_slot
*slot
;
979 slot
= gfn_to_memslot(kvm
, gfn
);
980 return __gfn_to_rmap(gfn
, level
, slot
);
983 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
985 struct kvm_mmu_memory_cache
*cache
;
987 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
988 return mmu_memory_cache_free_objects(cache
);
991 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
993 struct kvm_mmu_page
*sp
;
994 unsigned long *rmapp
;
996 sp
= page_header(__pa(spte
));
997 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
998 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
999 return pte_list_add(vcpu
, spte
, rmapp
);
1002 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1004 struct kvm_mmu_page
*sp
;
1006 unsigned long *rmapp
;
1008 sp
= page_header(__pa(spte
));
1009 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1010 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
1011 pte_list_remove(spte
, rmapp
);
1015 * Used by the following functions to iterate through the sptes linked by a
1016 * rmap. All fields are private and not assumed to be used outside.
1018 struct rmap_iterator
{
1019 /* private fields */
1020 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1021 int pos
; /* index of the sptep */
1025 * Iteration must be started by this function. This should also be used after
1026 * removing/dropping sptes from the rmap link because in such cases the
1027 * information in the itererator may not be valid.
1029 * Returns sptep if found, NULL otherwise.
1031 static u64
*rmap_get_first(unsigned long rmap
, struct rmap_iterator
*iter
)
1041 iter
->desc
= (struct pte_list_desc
*)(rmap
& ~1ul);
1043 return iter
->desc
->sptes
[iter
->pos
];
1047 * Must be used with a valid iterator: e.g. after rmap_get_first().
1049 * Returns sptep if found, NULL otherwise.
1051 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1054 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1058 sptep
= iter
->desc
->sptes
[iter
->pos
];
1063 iter
->desc
= iter
->desc
->more
;
1067 /* desc->sptes[0] cannot be NULL */
1068 return iter
->desc
->sptes
[iter
->pos
];
1075 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1077 if (mmu_spte_clear_track_bits(sptep
))
1078 rmap_remove(kvm
, sptep
);
1082 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1084 if (is_large_pte(*sptep
)) {
1085 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1086 PT_PAGE_TABLE_LEVEL
);
1087 drop_spte(kvm
, sptep
);
1095 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1097 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1098 kvm_flush_remote_tlbs(vcpu
->kvm
);
1102 * Write-protect on the specified @sptep, @pt_protect indicates whether
1103 * spte writ-protection is caused by protecting shadow page table.
1104 * @flush indicates whether tlb need be flushed.
1106 * Note: write protection is difference between drity logging and spte
1108 * - for dirty logging, the spte can be set to writable at anytime if
1109 * its dirty bitmap is properly set.
1110 * - for spte protection, the spte can be writable only after unsync-ing
1113 * Return true if the spte is dropped.
1116 spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool *flush
, bool pt_protect
)
1120 if (!is_writable_pte(spte
) &&
1121 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1124 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1126 if (__drop_large_spte(kvm
, sptep
)) {
1132 spte
&= ~SPTE_MMU_WRITEABLE
;
1133 spte
= spte
& ~PT_WRITABLE_MASK
;
1135 *flush
|= mmu_spte_update(sptep
, spte
);
1139 static bool __rmap_write_protect(struct kvm
*kvm
, unsigned long *rmapp
,
1140 int level
, bool pt_protect
)
1143 struct rmap_iterator iter
;
1146 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1147 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1148 if (spte_write_protect(kvm
, sptep
, &flush
, pt_protect
)) {
1149 sptep
= rmap_get_first(*rmapp
, &iter
);
1153 sptep
= rmap_get_next(&iter
);
1160 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1161 * @kvm: kvm instance
1162 * @slot: slot to protect
1163 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1164 * @mask: indicates which pages we should protect
1166 * Used when we do not need to care about huge page mappings: e.g. during dirty
1167 * logging we do not have any such mappings.
1169 void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1170 struct kvm_memory_slot
*slot
,
1171 gfn_t gfn_offset
, unsigned long mask
)
1173 unsigned long *rmapp
;
1176 rmapp
= &slot
->rmap
[gfn_offset
+ __ffs(mask
)];
1177 __rmap_write_protect(kvm
, rmapp
, PT_PAGE_TABLE_LEVEL
, false);
1179 /* clear the first set bit */
1184 static bool rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1186 struct kvm_memory_slot
*slot
;
1187 unsigned long *rmapp
;
1189 bool write_protected
= false;
1191 slot
= gfn_to_memslot(kvm
, gfn
);
1193 for (i
= PT_PAGE_TABLE_LEVEL
;
1194 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1195 rmapp
= __gfn_to_rmap(gfn
, i
, slot
);
1196 write_protected
|= __rmap_write_protect(kvm
, rmapp
, i
, true);
1199 return write_protected
;
1202 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1206 struct rmap_iterator iter
;
1207 int need_tlb_flush
= 0;
1209 while ((sptep
= rmap_get_first(*rmapp
, &iter
))) {
1210 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1211 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep
, *sptep
);
1213 drop_spte(kvm
, sptep
);
1217 return need_tlb_flush
;
1220 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1224 struct rmap_iterator iter
;
1227 pte_t
*ptep
= (pte_t
*)data
;
1230 WARN_ON(pte_huge(*ptep
));
1231 new_pfn
= pte_pfn(*ptep
);
1233 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1234 BUG_ON(!is_shadow_present_pte(*sptep
));
1235 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep
, *sptep
);
1239 if (pte_write(*ptep
)) {
1240 drop_spte(kvm
, sptep
);
1241 sptep
= rmap_get_first(*rmapp
, &iter
);
1243 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1244 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1246 new_spte
&= ~PT_WRITABLE_MASK
;
1247 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1248 new_spte
&= ~shadow_accessed_mask
;
1250 mmu_spte_clear_track_bits(sptep
);
1251 mmu_spte_set(sptep
, new_spte
);
1252 sptep
= rmap_get_next(&iter
);
1257 kvm_flush_remote_tlbs(kvm
);
1262 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1264 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1265 unsigned long data
))
1270 struct kvm_memslots
*slots
;
1271 struct kvm_memory_slot
*memslot
;
1273 slots
= kvm_memslots(kvm
);
1275 kvm_for_each_memslot(memslot
, slots
) {
1276 unsigned long start
= memslot
->userspace_addr
;
1279 end
= start
+ (memslot
->npages
<< PAGE_SHIFT
);
1280 if (hva
>= start
&& hva
< end
) {
1281 gfn_t gfn_offset
= (hva
- start
) >> PAGE_SHIFT
;
1282 gfn_t gfn
= memslot
->base_gfn
+ gfn_offset
;
1284 ret
= handler(kvm
, &memslot
->rmap
[gfn_offset
], data
);
1286 for (j
= 0; j
< KVM_NR_PAGE_SIZES
- 1; ++j
) {
1287 struct kvm_lpage_info
*linfo
;
1289 linfo
= lpage_info_slot(gfn
, memslot
,
1290 PT_DIRECTORY_LEVEL
+ j
);
1291 ret
|= handler(kvm
, &linfo
->rmap_pde
, data
);
1293 trace_kvm_age_page(hva
, memslot
, ret
);
1301 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1303 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1306 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1308 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1311 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1315 struct rmap_iterator
uninitialized_var(iter
);
1319 * In case of absence of EPT Access and Dirty Bits supports,
1320 * emulate the accessed bit for EPT, by checking if this page has
1321 * an EPT mapping, and clearing it if it does. On the next access,
1322 * a new EPT mapping will be established.
1323 * This has some overhead, but not as much as the cost of swapping
1324 * out actively used pages or breaking up actively used hugepages.
1326 if (!shadow_accessed_mask
)
1327 return kvm_unmap_rmapp(kvm
, rmapp
, data
);
1329 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1330 sptep
= rmap_get_next(&iter
)) {
1331 BUG_ON(!is_shadow_present_pte(*sptep
));
1333 if (*sptep
& shadow_accessed_mask
) {
1335 clear_bit((ffs(shadow_accessed_mask
) - 1),
1336 (unsigned long *)sptep
);
1343 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1347 struct rmap_iterator iter
;
1351 * If there's no access bit in the secondary pte set by the
1352 * hardware it's up to gup-fast/gup to set the access bit in
1353 * the primary pte or in the page structure.
1355 if (!shadow_accessed_mask
)
1358 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1359 sptep
= rmap_get_next(&iter
)) {
1360 BUG_ON(!is_shadow_present_pte(*sptep
));
1362 if (*sptep
& shadow_accessed_mask
) {
1371 #define RMAP_RECYCLE_THRESHOLD 1000
1373 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1375 unsigned long *rmapp
;
1376 struct kvm_mmu_page
*sp
;
1378 sp
= page_header(__pa(spte
));
1380 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1382 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, 0);
1383 kvm_flush_remote_tlbs(vcpu
->kvm
);
1386 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1388 return kvm_handle_hva(kvm
, hva
, 0, kvm_age_rmapp
);
1391 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1393 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1397 static int is_empty_shadow_page(u64
*spt
)
1402 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1403 if (is_shadow_present_pte(*pos
)) {
1404 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1413 * This value is the sum of all of the kvm instances's
1414 * kvm->arch.n_used_mmu_pages values. We need a global,
1415 * aggregate version in order to make the slab shrinker
1418 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1420 kvm
->arch
.n_used_mmu_pages
+= nr
;
1421 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1425 * Remove the sp from shadow page cache, after call it,
1426 * we can not find this sp from the cache, and the shadow
1427 * page table is still valid.
1428 * It should be under the protection of mmu lock.
1430 static void kvm_mmu_isolate_page(struct kvm_mmu_page
*sp
)
1432 ASSERT(is_empty_shadow_page(sp
->spt
));
1433 hlist_del(&sp
->hash_link
);
1434 if (!sp
->role
.direct
)
1435 free_page((unsigned long)sp
->gfns
);
1439 * Free the shadow page table and the sp, we can do it
1440 * out of the protection of mmu lock.
1442 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1444 list_del(&sp
->link
);
1445 free_page((unsigned long)sp
->spt
);
1446 kmem_cache_free(mmu_page_header_cache
, sp
);
1449 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1451 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1454 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1455 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1460 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1463 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1466 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1469 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1472 mmu_page_remove_parent_pte(sp
, parent_pte
);
1473 mmu_spte_clear_no_track(parent_pte
);
1476 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1477 u64
*parent_pte
, int direct
)
1479 struct kvm_mmu_page
*sp
;
1480 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1481 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1483 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1484 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1485 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1486 bitmap_zero(sp
->slot_bitmap
, KVM_MEM_SLOTS_NUM
);
1487 sp
->parent_ptes
= 0;
1488 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1489 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1493 static void mark_unsync(u64
*spte
);
1494 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1496 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1499 static void mark_unsync(u64
*spte
)
1501 struct kvm_mmu_page
*sp
;
1504 sp
= page_header(__pa(spte
));
1505 index
= spte
- sp
->spt
;
1506 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1508 if (sp
->unsync_children
++)
1510 kvm_mmu_mark_parents_unsync(sp
);
1513 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1514 struct kvm_mmu_page
*sp
)
1519 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1523 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1524 struct kvm_mmu_page
*sp
, u64
*spte
,
1530 #define KVM_PAGE_ARRAY_NR 16
1532 struct kvm_mmu_pages
{
1533 struct mmu_page_and_offset
{
1534 struct kvm_mmu_page
*sp
;
1536 } page
[KVM_PAGE_ARRAY_NR
];
1540 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1546 for (i
=0; i
< pvec
->nr
; i
++)
1547 if (pvec
->page
[i
].sp
== sp
)
1550 pvec
->page
[pvec
->nr
].sp
= sp
;
1551 pvec
->page
[pvec
->nr
].idx
= idx
;
1553 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1556 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1557 struct kvm_mmu_pages
*pvec
)
1559 int i
, ret
, nr_unsync_leaf
= 0;
1561 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1562 struct kvm_mmu_page
*child
;
1563 u64 ent
= sp
->spt
[i
];
1565 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1566 goto clear_child_bitmap
;
1568 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1570 if (child
->unsync_children
) {
1571 if (mmu_pages_add(pvec
, child
, i
))
1574 ret
= __mmu_unsync_walk(child
, pvec
);
1576 goto clear_child_bitmap
;
1578 nr_unsync_leaf
+= ret
;
1581 } else if (child
->unsync
) {
1583 if (mmu_pages_add(pvec
, child
, i
))
1586 goto clear_child_bitmap
;
1591 __clear_bit(i
, sp
->unsync_child_bitmap
);
1592 sp
->unsync_children
--;
1593 WARN_ON((int)sp
->unsync_children
< 0);
1597 return nr_unsync_leaf
;
1600 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1601 struct kvm_mmu_pages
*pvec
)
1603 if (!sp
->unsync_children
)
1606 mmu_pages_add(pvec
, sp
, 0);
1607 return __mmu_unsync_walk(sp
, pvec
);
1610 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1612 WARN_ON(!sp
->unsync
);
1613 trace_kvm_mmu_sync_page(sp
);
1615 --kvm
->stat
.mmu_unsync
;
1618 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1619 struct list_head
*invalid_list
);
1620 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1621 struct list_head
*invalid_list
);
1623 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1624 hlist_for_each_entry(sp, pos, \
1625 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1626 if ((sp)->gfn != (gfn)) {} else
1628 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1629 hlist_for_each_entry(sp, pos, \
1630 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1631 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1632 (sp)->role.invalid) {} else
1634 /* @sp->gfn should be write-protected at the call site */
1635 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1636 struct list_head
*invalid_list
, bool clear_unsync
)
1638 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1639 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1644 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1646 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1647 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1651 kvm_mmu_flush_tlb(vcpu
);
1655 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1656 struct kvm_mmu_page
*sp
)
1658 LIST_HEAD(invalid_list
);
1661 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1663 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1668 #ifdef CONFIG_KVM_MMU_AUDIT
1669 #include "mmu_audit.c"
1671 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1672 static void mmu_audit_disable(void) { }
1675 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1676 struct list_head
*invalid_list
)
1678 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1681 /* @gfn should be write-protected at the call site */
1682 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1684 struct kvm_mmu_page
*s
;
1685 struct hlist_node
*node
;
1686 LIST_HEAD(invalid_list
);
1689 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
1693 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1694 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1695 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1696 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1697 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1703 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1705 kvm_mmu_flush_tlb(vcpu
);
1708 struct mmu_page_path
{
1709 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1710 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1713 #define for_each_sp(pvec, sp, parents, i) \
1714 for (i = mmu_pages_next(&pvec, &parents, -1), \
1715 sp = pvec.page[i].sp; \
1716 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1717 i = mmu_pages_next(&pvec, &parents, i))
1719 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1720 struct mmu_page_path
*parents
,
1725 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1726 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1728 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1729 parents
->idx
[0] = pvec
->page
[n
].idx
;
1733 parents
->parent
[sp
->role
.level
-2] = sp
;
1734 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1740 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1742 struct kvm_mmu_page
*sp
;
1743 unsigned int level
= 0;
1746 unsigned int idx
= parents
->idx
[level
];
1748 sp
= parents
->parent
[level
];
1752 --sp
->unsync_children
;
1753 WARN_ON((int)sp
->unsync_children
< 0);
1754 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1756 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1759 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1760 struct mmu_page_path
*parents
,
1761 struct kvm_mmu_pages
*pvec
)
1763 parents
->parent
[parent
->role
.level
-1] = NULL
;
1767 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1768 struct kvm_mmu_page
*parent
)
1771 struct kvm_mmu_page
*sp
;
1772 struct mmu_page_path parents
;
1773 struct kvm_mmu_pages pages
;
1774 LIST_HEAD(invalid_list
);
1776 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1777 while (mmu_unsync_walk(parent
, &pages
)) {
1778 bool protected = false;
1780 for_each_sp(pages
, sp
, parents
, i
)
1781 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1784 kvm_flush_remote_tlbs(vcpu
->kvm
);
1786 for_each_sp(pages
, sp
, parents
, i
) {
1787 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1788 mmu_pages_clear_parents(&parents
);
1790 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1791 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1792 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1796 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1800 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1804 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1806 sp
->write_flooding_count
= 0;
1809 static void clear_sp_write_flooding_count(u64
*spte
)
1811 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
1813 __clear_sp_write_flooding_count(sp
);
1816 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1824 union kvm_mmu_page_role role
;
1826 struct kvm_mmu_page
*sp
;
1827 struct hlist_node
*node
;
1828 bool need_sync
= false;
1830 role
= vcpu
->arch
.mmu
.base_role
;
1832 role
.direct
= direct
;
1835 role
.access
= access
;
1836 if (!vcpu
->arch
.mmu
.direct_map
1837 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1838 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1839 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1840 role
.quadrant
= quadrant
;
1842 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
, node
) {
1843 if (!need_sync
&& sp
->unsync
)
1846 if (sp
->role
.word
!= role
.word
)
1849 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1852 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1853 if (sp
->unsync_children
) {
1854 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1855 kvm_mmu_mark_parents_unsync(sp
);
1856 } else if (sp
->unsync
)
1857 kvm_mmu_mark_parents_unsync(sp
);
1859 __clear_sp_write_flooding_count(sp
);
1860 trace_kvm_mmu_get_page(sp
, false);
1863 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1864 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1869 hlist_add_head(&sp
->hash_link
,
1870 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1872 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1873 kvm_flush_remote_tlbs(vcpu
->kvm
);
1874 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1875 kvm_sync_pages(vcpu
, gfn
);
1877 account_shadowed(vcpu
->kvm
, gfn
);
1879 init_shadow_page_table(sp
);
1880 trace_kvm_mmu_get_page(sp
, true);
1884 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1885 struct kvm_vcpu
*vcpu
, u64 addr
)
1887 iterator
->addr
= addr
;
1888 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1889 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1891 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1892 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1893 !vcpu
->arch
.mmu
.direct_map
)
1896 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1897 iterator
->shadow_addr
1898 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1899 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1901 if (!iterator
->shadow_addr
)
1902 iterator
->level
= 0;
1906 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1908 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1911 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1912 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1916 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1919 if (is_last_spte(spte
, iterator
->level
)) {
1920 iterator
->level
= 0;
1924 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1928 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1930 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1933 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1937 spte
= __pa(sp
->spt
)
1938 | PT_PRESENT_MASK
| PT_ACCESSED_MASK
1939 | PT_WRITABLE_MASK
| PT_USER_MASK
;
1940 mmu_spte_set(sptep
, spte
);
1943 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1944 unsigned direct_access
)
1946 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1947 struct kvm_mmu_page
*child
;
1950 * For the direct sp, if the guest pte's dirty bit
1951 * changed form clean to dirty, it will corrupt the
1952 * sp's access: allow writable in the read-only sp,
1953 * so we should update the spte at this point to get
1954 * a new sp with the correct access.
1956 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
1957 if (child
->role
.access
== direct_access
)
1960 drop_parent_pte(child
, sptep
);
1961 kvm_flush_remote_tlbs(vcpu
->kvm
);
1965 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1969 struct kvm_mmu_page
*child
;
1972 if (is_shadow_present_pte(pte
)) {
1973 if (is_last_spte(pte
, sp
->role
.level
)) {
1974 drop_spte(kvm
, spte
);
1975 if (is_large_pte(pte
))
1978 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
1979 drop_parent_pte(child
, spte
);
1984 if (is_mmio_spte(pte
))
1985 mmu_spte_clear_no_track(spte
);
1990 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
1991 struct kvm_mmu_page
*sp
)
1995 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1996 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
1999 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
2001 mmu_page_remove_parent_pte(sp
, parent_pte
);
2004 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2007 struct rmap_iterator iter
;
2009 while ((sptep
= rmap_get_first(sp
->parent_ptes
, &iter
)))
2010 drop_parent_pte(sp
, sptep
);
2013 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2014 struct kvm_mmu_page
*parent
,
2015 struct list_head
*invalid_list
)
2018 struct mmu_page_path parents
;
2019 struct kvm_mmu_pages pages
;
2021 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2024 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2025 while (mmu_unsync_walk(parent
, &pages
)) {
2026 struct kvm_mmu_page
*sp
;
2028 for_each_sp(pages
, sp
, parents
, i
) {
2029 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2030 mmu_pages_clear_parents(&parents
);
2033 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2039 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2040 struct list_head
*invalid_list
)
2044 trace_kvm_mmu_prepare_zap_page(sp
);
2045 ++kvm
->stat
.mmu_shadow_zapped
;
2046 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2047 kvm_mmu_page_unlink_children(kvm
, sp
);
2048 kvm_mmu_unlink_parents(kvm
, sp
);
2049 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2050 unaccount_shadowed(kvm
, sp
->gfn
);
2052 kvm_unlink_unsync_page(kvm
, sp
);
2053 if (!sp
->root_count
) {
2056 list_move(&sp
->link
, invalid_list
);
2057 kvm_mod_used_mmu_pages(kvm
, -1);
2059 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2060 kvm_reload_remote_mmus(kvm
);
2063 sp
->role
.invalid
= 1;
2067 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2068 struct list_head
*invalid_list
)
2070 struct kvm_mmu_page
*sp
;
2072 if (list_empty(invalid_list
))
2076 * wmb: make sure everyone sees our modifications to the page tables
2077 * rmb: make sure we see changes to vcpu->mode
2082 * Wait for all vcpus to exit guest mode and/or lockless shadow
2085 kvm_flush_remote_tlbs(kvm
);
2088 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
2089 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2090 kvm_mmu_isolate_page(sp
);
2091 kvm_mmu_free_page(sp
);
2092 } while (!list_empty(invalid_list
));
2096 * Changing the number of mmu pages allocated to the vm
2097 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2099 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2101 LIST_HEAD(invalid_list
);
2103 * If we set the number of mmu pages to be smaller be than the
2104 * number of actived pages , we must to free some mmu pages before we
2108 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2109 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
&&
2110 !list_empty(&kvm
->arch
.active_mmu_pages
)) {
2111 struct kvm_mmu_page
*page
;
2113 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
2114 struct kvm_mmu_page
, link
);
2115 kvm_mmu_prepare_zap_page(kvm
, page
, &invalid_list
);
2117 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2118 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2121 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2124 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2126 struct kvm_mmu_page
*sp
;
2127 struct hlist_node
*node
;
2128 LIST_HEAD(invalid_list
);
2131 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2133 spin_lock(&kvm
->mmu_lock
);
2134 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2135 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2138 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2140 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2141 spin_unlock(&kvm
->mmu_lock
);
2145 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2147 static void page_header_update_slot(struct kvm
*kvm
, void *pte
, gfn_t gfn
)
2149 int slot
= memslot_id(kvm
, gfn
);
2150 struct kvm_mmu_page
*sp
= page_header(__pa(pte
));
2152 __set_bit(slot
, sp
->slot_bitmap
);
2156 * The function is based on mtrr_type_lookup() in
2157 * arch/x86/kernel/cpu/mtrr/generic.c
2159 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2164 u8 prev_match
, curr_match
;
2165 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2167 if (!mtrr_state
->enabled
)
2170 /* Make end inclusive end, instead of exclusive */
2173 /* Look in fixed ranges. Just return the type as per start */
2174 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2177 if (start
< 0x80000) {
2179 idx
+= (start
>> 16);
2180 return mtrr_state
->fixed_ranges
[idx
];
2181 } else if (start
< 0xC0000) {
2183 idx
+= ((start
- 0x80000) >> 14);
2184 return mtrr_state
->fixed_ranges
[idx
];
2185 } else if (start
< 0x1000000) {
2187 idx
+= ((start
- 0xC0000) >> 12);
2188 return mtrr_state
->fixed_ranges
[idx
];
2193 * Look in variable ranges
2194 * Look of multiple ranges matching this address and pick type
2195 * as per MTRR precedence
2197 if (!(mtrr_state
->enabled
& 2))
2198 return mtrr_state
->def_type
;
2201 for (i
= 0; i
< num_var_ranges
; ++i
) {
2202 unsigned short start_state
, end_state
;
2204 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2207 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2208 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2209 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2210 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2212 start_state
= ((start
& mask
) == (base
& mask
));
2213 end_state
= ((end
& mask
) == (base
& mask
));
2214 if (start_state
!= end_state
)
2217 if ((start
& mask
) != (base
& mask
))
2220 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2221 if (prev_match
== 0xFF) {
2222 prev_match
= curr_match
;
2226 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2227 curr_match
== MTRR_TYPE_UNCACHABLE
)
2228 return MTRR_TYPE_UNCACHABLE
;
2230 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2231 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2232 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2233 curr_match
== MTRR_TYPE_WRBACK
)) {
2234 prev_match
= MTRR_TYPE_WRTHROUGH
;
2235 curr_match
= MTRR_TYPE_WRTHROUGH
;
2238 if (prev_match
!= curr_match
)
2239 return MTRR_TYPE_UNCACHABLE
;
2242 if (prev_match
!= 0xFF)
2245 return mtrr_state
->def_type
;
2248 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2252 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2253 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2254 if (mtrr
== 0xfe || mtrr
== 0xff)
2255 mtrr
= MTRR_TYPE_WRBACK
;
2258 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2260 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2262 trace_kvm_mmu_unsync_page(sp
);
2263 ++vcpu
->kvm
->stat
.mmu_unsync
;
2266 kvm_mmu_mark_parents_unsync(sp
);
2269 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2271 struct kvm_mmu_page
*s
;
2272 struct hlist_node
*node
;
2274 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2277 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2278 __kvm_unsync_page(vcpu
, s
);
2282 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2285 struct kvm_mmu_page
*s
;
2286 struct hlist_node
*node
;
2287 bool need_unsync
= false;
2289 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2293 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2296 if (!need_unsync
&& !s
->unsync
) {
2301 kvm_unsync_pages(vcpu
, gfn
);
2305 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2306 unsigned pte_access
, int user_fault
,
2307 int write_fault
, int level
,
2308 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2309 bool can_unsync
, bool host_writable
)
2314 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2317 spte
= PT_PRESENT_MASK
;
2319 spte
|= shadow_accessed_mask
;
2321 if (pte_access
& ACC_EXEC_MASK
)
2322 spte
|= shadow_x_mask
;
2324 spte
|= shadow_nx_mask
;
2326 if (pte_access
& ACC_USER_MASK
)
2327 spte
|= shadow_user_mask
;
2329 if (level
> PT_PAGE_TABLE_LEVEL
)
2330 spte
|= PT_PAGE_SIZE_MASK
;
2332 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2333 kvm_is_mmio_pfn(pfn
));
2336 spte
|= SPTE_HOST_WRITEABLE
;
2338 pte_access
&= ~ACC_WRITE_MASK
;
2340 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2342 if ((pte_access
& ACC_WRITE_MASK
)
2343 || (!vcpu
->arch
.mmu
.direct_map
&& write_fault
2344 && !is_write_protection(vcpu
) && !user_fault
)) {
2346 if (level
> PT_PAGE_TABLE_LEVEL
&&
2347 has_wrprotected_page(vcpu
->kvm
, gfn
, level
)) {
2349 drop_spte(vcpu
->kvm
, sptep
);
2353 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2355 if (!vcpu
->arch
.mmu
.direct_map
2356 && !(pte_access
& ACC_WRITE_MASK
)) {
2357 spte
&= ~PT_USER_MASK
;
2359 * If we converted a user page to a kernel page,
2360 * so that the kernel can write to it when cr0.wp=0,
2361 * then we should prevent the kernel from executing it
2362 * if SMEP is enabled.
2364 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
2365 spte
|= PT64_NX_MASK
;
2369 * Optimization: for pte sync, if spte was writable the hash
2370 * lookup is unnecessary (and expensive). Write protection
2371 * is responsibility of mmu_get_page / kvm_sync_page.
2372 * Same reasoning can be applied to dirty page accounting.
2374 if (!can_unsync
&& is_writable_pte(*sptep
))
2377 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2378 pgprintk("%s: found shadow page for %llx, marking ro\n",
2381 pte_access
&= ~ACC_WRITE_MASK
;
2382 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2386 if (pte_access
& ACC_WRITE_MASK
)
2387 mark_page_dirty(vcpu
->kvm
, gfn
);
2390 if (mmu_spte_update(sptep
, spte
))
2391 kvm_flush_remote_tlbs(vcpu
->kvm
);
2396 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2397 unsigned pt_access
, unsigned pte_access
,
2398 int user_fault
, int write_fault
,
2399 int *emulate
, int level
, gfn_t gfn
,
2400 pfn_t pfn
, bool speculative
,
2403 int was_rmapped
= 0;
2406 pgprintk("%s: spte %llx access %x write_fault %d"
2407 " user_fault %d gfn %llx\n",
2408 __func__
, *sptep
, pt_access
,
2409 write_fault
, user_fault
, gfn
);
2411 if (is_rmap_spte(*sptep
)) {
2413 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2414 * the parent of the now unreachable PTE.
2416 if (level
> PT_PAGE_TABLE_LEVEL
&&
2417 !is_large_pte(*sptep
)) {
2418 struct kvm_mmu_page
*child
;
2421 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2422 drop_parent_pte(child
, sptep
);
2423 kvm_flush_remote_tlbs(vcpu
->kvm
);
2424 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2425 pgprintk("hfn old %llx new %llx\n",
2426 spte_to_pfn(*sptep
), pfn
);
2427 drop_spte(vcpu
->kvm
, sptep
);
2428 kvm_flush_remote_tlbs(vcpu
->kvm
);
2433 if (set_spte(vcpu
, sptep
, pte_access
, user_fault
, write_fault
,
2434 level
, gfn
, pfn
, speculative
, true,
2438 kvm_mmu_flush_tlb(vcpu
);
2441 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2444 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2445 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2446 is_large_pte(*sptep
)? "2MB" : "4kB",
2447 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2449 if (!was_rmapped
&& is_large_pte(*sptep
))
2450 ++vcpu
->kvm
->stat
.lpages
;
2452 if (is_shadow_present_pte(*sptep
)) {
2453 page_header_update_slot(vcpu
->kvm
, sptep
, gfn
);
2455 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2456 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2457 rmap_recycle(vcpu
, sptep
, gfn
);
2460 kvm_release_pfn_clean(pfn
);
2463 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2465 mmu_free_roots(vcpu
);
2468 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2471 struct kvm_memory_slot
*slot
;
2474 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2476 get_page(fault_page
);
2477 return page_to_pfn(fault_page
);
2480 hva
= gfn_to_hva_memslot(slot
, gfn
);
2482 return hva_to_pfn_atomic(vcpu
->kvm
, hva
);
2485 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2486 struct kvm_mmu_page
*sp
,
2487 u64
*start
, u64
*end
)
2489 struct page
*pages
[PTE_PREFETCH_NUM
];
2490 unsigned access
= sp
->role
.access
;
2494 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2495 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2498 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2502 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2503 mmu_set_spte(vcpu
, start
, ACC_ALL
,
2505 sp
->role
.level
, gfn
,
2506 page_to_pfn(pages
[i
]), true, true);
2511 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2512 struct kvm_mmu_page
*sp
, u64
*sptep
)
2514 u64
*spte
, *start
= NULL
;
2517 WARN_ON(!sp
->role
.direct
);
2519 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2522 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2523 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2526 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2534 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2536 struct kvm_mmu_page
*sp
;
2539 * Since it's no accessed bit on EPT, it's no way to
2540 * distinguish between actually accessed translations
2541 * and prefetched, so disable pte prefetch if EPT is
2544 if (!shadow_accessed_mask
)
2547 sp
= page_header(__pa(sptep
));
2548 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2551 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2554 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2555 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2558 struct kvm_shadow_walk_iterator iterator
;
2559 struct kvm_mmu_page
*sp
;
2563 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2564 if (iterator
.level
== level
) {
2565 unsigned pte_access
= ACC_ALL
;
2567 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
, pte_access
,
2569 level
, gfn
, pfn
, prefault
, map_writable
);
2570 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2571 ++vcpu
->stat
.pf_fixed
;
2575 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2576 u64 base_addr
= iterator
.addr
;
2578 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2579 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2580 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2582 1, ACC_ALL
, iterator
.sptep
);
2584 pgprintk("nonpaging_map: ENOMEM\n");
2585 kvm_release_pfn_clean(pfn
);
2589 mmu_spte_set(iterator
.sptep
,
2591 | PT_PRESENT_MASK
| PT_WRITABLE_MASK
2592 | shadow_user_mask
| shadow_x_mask
2593 | shadow_accessed_mask
);
2599 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2603 info
.si_signo
= SIGBUS
;
2605 info
.si_code
= BUS_MCEERR_AR
;
2606 info
.si_addr
= (void __user
*)address
;
2607 info
.si_addr_lsb
= PAGE_SHIFT
;
2609 send_sig_info(SIGBUS
, &info
, tsk
);
2612 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2614 kvm_release_pfn_clean(pfn
);
2615 if (is_hwpoison_pfn(pfn
)) {
2616 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2623 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2624 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2628 int level
= *levelp
;
2631 * Check if it's a transparent hugepage. If this would be an
2632 * hugetlbfs page, level wouldn't be set to
2633 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2636 if (!is_error_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2637 level
== PT_PAGE_TABLE_LEVEL
&&
2638 PageTransCompound(pfn_to_page(pfn
)) &&
2639 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2642 * mmu_notifier_retry was successful and we hold the
2643 * mmu_lock here, so the pmd can't become splitting
2644 * from under us, and in turn
2645 * __split_huge_page_refcount() can't run from under
2646 * us and we can safely transfer the refcount from
2647 * PG_tail to PG_head as we switch the pfn to tail to
2650 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2651 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2652 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2656 kvm_release_pfn_clean(pfn
);
2664 static bool mmu_invalid_pfn(pfn_t pfn
)
2666 return unlikely(is_invalid_pfn(pfn
));
2669 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2670 pfn_t pfn
, unsigned access
, int *ret_val
)
2674 /* The pfn is invalid, report the error! */
2675 if (unlikely(is_invalid_pfn(pfn
))) {
2676 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2680 if (unlikely(is_noslot_pfn(pfn
)))
2681 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2688 static bool page_fault_can_be_fast(struct kvm_vcpu
*vcpu
, u32 error_code
)
2691 * #PF can be fast only if the shadow page table is present and it
2692 * is caused by write-protect, that means we just need change the
2693 * W bit of the spte which can be done out of mmu-lock.
2695 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2696 !(error_code
& PFERR_WRITE_MASK
))
2703 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 spte
)
2705 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
2708 WARN_ON(!sp
->role
.direct
);
2711 * The gfn of direct spte is stable since it is calculated
2714 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2716 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2717 mark_page_dirty(vcpu
->kvm
, gfn
);
2724 * - true: let the vcpu to access on the same address again.
2725 * - false: let the real page fault path to fix it.
2727 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2730 struct kvm_shadow_walk_iterator iterator
;
2734 if (!page_fault_can_be_fast(vcpu
, error_code
))
2737 walk_shadow_page_lockless_begin(vcpu
);
2738 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2739 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2743 * If the mapping has been changed, let the vcpu fault on the
2744 * same address again.
2746 if (!is_rmap_spte(spte
)) {
2751 if (!is_last_spte(spte
, level
))
2755 * Check if it is a spurious fault caused by TLB lazily flushed.
2757 * Need not check the access of upper level table entries since
2758 * they are always ACC_ALL.
2760 if (is_writable_pte(spte
)) {
2766 * Currently, to simplify the code, only the spte write-protected
2767 * by dirty-log can be fast fixed.
2769 if (!spte_is_locklessly_modifiable(spte
))
2773 * Currently, fast page fault only works for direct mapping since
2774 * the gfn is not stable for indirect shadow page.
2775 * See Documentation/virtual/kvm/locking.txt to get more detail.
2777 ret
= fast_pf_fix_direct_spte(vcpu
, iterator
.sptep
, spte
);
2779 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
2781 walk_shadow_page_lockless_end(vcpu
);
2786 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2787 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2789 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
2790 gfn_t gfn
, bool prefault
)
2796 unsigned long mmu_seq
;
2797 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
2799 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2800 if (likely(!force_pt_level
)) {
2801 level
= mapping_level(vcpu
, gfn
);
2803 * This path builds a PAE pagetable - so we can map
2804 * 2mb pages at maximum. Therefore check if the level
2805 * is larger than that.
2807 if (level
> PT_DIRECTORY_LEVEL
)
2808 level
= PT_DIRECTORY_LEVEL
;
2810 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2812 level
= PT_PAGE_TABLE_LEVEL
;
2814 if (fast_page_fault(vcpu
, v
, level
, error_code
))
2817 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2820 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2823 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2826 spin_lock(&vcpu
->kvm
->mmu_lock
);
2827 if (mmu_notifier_retry(vcpu
, mmu_seq
))
2829 kvm_mmu_free_some_pages(vcpu
);
2830 if (likely(!force_pt_level
))
2831 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2832 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2834 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2840 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2841 kvm_release_pfn_clean(pfn
);
2846 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2849 struct kvm_mmu_page
*sp
;
2850 LIST_HEAD(invalid_list
);
2852 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2854 spin_lock(&vcpu
->kvm
->mmu_lock
);
2855 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2856 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2857 vcpu
->arch
.mmu
.direct_map
)) {
2858 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2860 sp
= page_header(root
);
2862 if (!sp
->root_count
&& sp
->role
.invalid
) {
2863 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2864 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2866 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2867 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2870 for (i
= 0; i
< 4; ++i
) {
2871 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2874 root
&= PT64_BASE_ADDR_MASK
;
2875 sp
= page_header(root
);
2877 if (!sp
->root_count
&& sp
->role
.invalid
)
2878 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2881 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2883 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2884 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2885 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2888 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2892 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2893 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2900 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2902 struct kvm_mmu_page
*sp
;
2905 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2906 spin_lock(&vcpu
->kvm
->mmu_lock
);
2907 kvm_mmu_free_some_pages(vcpu
);
2908 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2911 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2912 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2913 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2914 for (i
= 0; i
< 4; ++i
) {
2915 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2917 ASSERT(!VALID_PAGE(root
));
2918 spin_lock(&vcpu
->kvm
->mmu_lock
);
2919 kvm_mmu_free_some_pages(vcpu
);
2920 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2922 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2924 root
= __pa(sp
->spt
);
2926 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2927 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2929 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2936 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2938 struct kvm_mmu_page
*sp
;
2943 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2945 if (mmu_check_root(vcpu
, root_gfn
))
2949 * Do we shadow a long mode page table? If so we need to
2950 * write-protect the guests page table root.
2952 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2953 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2955 ASSERT(!VALID_PAGE(root
));
2957 spin_lock(&vcpu
->kvm
->mmu_lock
);
2958 kvm_mmu_free_some_pages(vcpu
);
2959 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
2961 root
= __pa(sp
->spt
);
2963 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2964 vcpu
->arch
.mmu
.root_hpa
= root
;
2969 * We shadow a 32 bit page table. This may be a legacy 2-level
2970 * or a PAE 3-level page table. In either case we need to be aware that
2971 * the shadow page table may be a PAE or a long mode page table.
2973 pm_mask
= PT_PRESENT_MASK
;
2974 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
2975 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
2977 for (i
= 0; i
< 4; ++i
) {
2978 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2980 ASSERT(!VALID_PAGE(root
));
2981 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
2982 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
2983 if (!is_present_gpte(pdptr
)) {
2984 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
2987 root_gfn
= pdptr
>> PAGE_SHIFT
;
2988 if (mmu_check_root(vcpu
, root_gfn
))
2991 spin_lock(&vcpu
->kvm
->mmu_lock
);
2992 kvm_mmu_free_some_pages(vcpu
);
2993 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
2996 root
= __pa(sp
->spt
);
2998 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3000 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3002 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3005 * If we shadow a 32 bit page table with a long mode page
3006 * table we enter this path.
3008 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3009 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3011 * The additional page necessary for this is only
3012 * allocated on demand.
3017 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3018 if (lm_root
== NULL
)
3021 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3023 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3026 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3032 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3034 if (vcpu
->arch
.mmu
.direct_map
)
3035 return mmu_alloc_direct_roots(vcpu
);
3037 return mmu_alloc_shadow_roots(vcpu
);
3040 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3043 struct kvm_mmu_page
*sp
;
3045 if (vcpu
->arch
.mmu
.direct_map
)
3048 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3051 vcpu_clear_mmio_info(vcpu
, ~0ul);
3052 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3053 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3054 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3055 sp
= page_header(root
);
3056 mmu_sync_children(vcpu
, sp
);
3057 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3060 for (i
= 0; i
< 4; ++i
) {
3061 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3063 if (root
&& VALID_PAGE(root
)) {
3064 root
&= PT64_BASE_ADDR_MASK
;
3065 sp
= page_header(root
);
3066 mmu_sync_children(vcpu
, sp
);
3069 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3072 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3074 spin_lock(&vcpu
->kvm
->mmu_lock
);
3075 mmu_sync_roots(vcpu
);
3076 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3079 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3080 u32 access
, struct x86_exception
*exception
)
3083 exception
->error_code
= 0;
3087 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3089 struct x86_exception
*exception
)
3092 exception
->error_code
= 0;
3093 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
3096 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3099 return vcpu_match_mmio_gpa(vcpu
, addr
);
3101 return vcpu_match_mmio_gva(vcpu
, addr
);
3106 * On direct hosts, the last spte is only allows two states
3107 * for mmio page fault:
3108 * - It is the mmio spte
3109 * - It is zapped or it is being zapped.
3111 * This function completely checks the spte when the last spte
3112 * is not the mmio spte.
3114 static bool check_direct_spte_mmio_pf(u64 spte
)
3116 return __check_direct_spte_mmio_pf(spte
);
3119 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
3121 struct kvm_shadow_walk_iterator iterator
;
3124 walk_shadow_page_lockless_begin(vcpu
);
3125 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
3126 if (!is_shadow_present_pte(spte
))
3128 walk_shadow_page_lockless_end(vcpu
);
3134 * If it is a real mmio page fault, return 1 and emulat the instruction
3135 * directly, return 0 to let CPU fault again on the address, -1 is
3136 * returned if bug is detected.
3138 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3142 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
3145 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
3147 if (is_mmio_spte(spte
)) {
3148 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3149 unsigned access
= get_mmio_spte_access(spte
);
3154 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3155 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3160 * It's ok if the gva is remapped by other cpus on shadow guest,
3161 * it's a BUG if the gfn is not a mmio page.
3163 if (direct
&& !check_direct_spte_mmio_pf(spte
))
3167 * If the page table is zapped by other cpus, let CPU fault again on
3172 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
3174 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
3175 u32 error_code
, bool direct
)
3179 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
3184 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3185 u32 error_code
, bool prefault
)
3190 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3192 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3193 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
3195 r
= mmu_topup_memory_caches(vcpu
);
3200 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3202 gfn
= gva
>> PAGE_SHIFT
;
3204 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3205 error_code
, gfn
, prefault
);
3208 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3210 struct kvm_arch_async_pf arch
;
3212 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3214 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3215 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3217 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3220 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3222 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3223 kvm_event_needs_reinjection(vcpu
)))
3226 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3229 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3230 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3234 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3237 return false; /* *pfn has correct page already */
3239 put_page(pfn_to_page(*pfn
));
3241 if (!prefault
&& can_do_async_pf(vcpu
)) {
3242 trace_kvm_try_async_get_page(gva
, gfn
);
3243 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3244 trace_kvm_async_pf_doublefault(gva
, gfn
);
3245 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3247 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3251 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3256 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3263 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3264 unsigned long mmu_seq
;
3265 int write
= error_code
& PFERR_WRITE_MASK
;
3269 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3271 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3272 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3274 r
= mmu_topup_memory_caches(vcpu
);
3278 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3279 if (likely(!force_pt_level
)) {
3280 level
= mapping_level(vcpu
, gfn
);
3281 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3283 level
= PT_PAGE_TABLE_LEVEL
;
3285 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3288 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3291 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3294 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3297 spin_lock(&vcpu
->kvm
->mmu_lock
);
3298 if (mmu_notifier_retry(vcpu
, mmu_seq
))
3300 kvm_mmu_free_some_pages(vcpu
);
3301 if (likely(!force_pt_level
))
3302 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3303 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3304 level
, gfn
, pfn
, prefault
);
3305 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3310 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3311 kvm_release_pfn_clean(pfn
);
3315 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3317 mmu_free_roots(vcpu
);
3320 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3321 struct kvm_mmu
*context
)
3323 context
->new_cr3
= nonpaging_new_cr3
;
3324 context
->page_fault
= nonpaging_page_fault
;
3325 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3326 context
->free
= nonpaging_free
;
3327 context
->sync_page
= nonpaging_sync_page
;
3328 context
->invlpg
= nonpaging_invlpg
;
3329 context
->update_pte
= nonpaging_update_pte
;
3330 context
->root_level
= 0;
3331 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3332 context
->root_hpa
= INVALID_PAGE
;
3333 context
->direct_map
= true;
3334 context
->nx
= false;
3338 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3340 ++vcpu
->stat
.tlb_flush
;
3341 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3344 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3346 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3347 mmu_free_roots(vcpu
);
3350 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3352 return kvm_read_cr3(vcpu
);
3355 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3356 struct x86_exception
*fault
)
3358 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3361 static void paging_free(struct kvm_vcpu
*vcpu
)
3363 nonpaging_free(vcpu
);
3366 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3370 bit7
= (gpte
>> 7) & 1;
3371 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
3374 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3377 if (unlikely(is_mmio_spte(*sptep
))) {
3378 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3379 mmu_spte_clear_no_track(sptep
);
3384 mark_mmio_spte(sptep
, gfn
, access
);
3392 #include "paging_tmpl.h"
3396 #include "paging_tmpl.h"
3399 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3400 struct kvm_mmu
*context
)
3402 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3403 u64 exb_bit_rsvd
= 0;
3406 exb_bit_rsvd
= rsvd_bits(63, 63);
3407 switch (context
->root_level
) {
3408 case PT32_ROOT_LEVEL
:
3409 /* no rsvd bits for 2 level 4K page table entries */
3410 context
->rsvd_bits_mask
[0][1] = 0;
3411 context
->rsvd_bits_mask
[0][0] = 0;
3412 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3414 if (!is_pse(vcpu
)) {
3415 context
->rsvd_bits_mask
[1][1] = 0;
3419 if (is_cpuid_PSE36())
3420 /* 36bits PSE 4MB page */
3421 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3423 /* 32 bits PSE 4MB page */
3424 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3426 case PT32E_ROOT_LEVEL
:
3427 context
->rsvd_bits_mask
[0][2] =
3428 rsvd_bits(maxphyaddr
, 63) |
3429 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3430 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3431 rsvd_bits(maxphyaddr
, 62); /* PDE */
3432 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3433 rsvd_bits(maxphyaddr
, 62); /* PTE */
3434 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3435 rsvd_bits(maxphyaddr
, 62) |
3436 rsvd_bits(13, 20); /* large page */
3437 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3439 case PT64_ROOT_LEVEL
:
3440 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3441 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3442 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3443 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3444 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3445 rsvd_bits(maxphyaddr
, 51);
3446 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3447 rsvd_bits(maxphyaddr
, 51);
3448 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3449 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3450 rsvd_bits(maxphyaddr
, 51) |
3452 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3453 rsvd_bits(maxphyaddr
, 51) |
3454 rsvd_bits(13, 20); /* large page */
3455 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3460 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3461 struct kvm_mmu
*context
,
3464 context
->nx
= is_nx(vcpu
);
3465 context
->root_level
= level
;
3467 reset_rsvds_bits_mask(vcpu
, context
);
3469 ASSERT(is_pae(vcpu
));
3470 context
->new_cr3
= paging_new_cr3
;
3471 context
->page_fault
= paging64_page_fault
;
3472 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3473 context
->sync_page
= paging64_sync_page
;
3474 context
->invlpg
= paging64_invlpg
;
3475 context
->update_pte
= paging64_update_pte
;
3476 context
->free
= paging_free
;
3477 context
->shadow_root_level
= level
;
3478 context
->root_hpa
= INVALID_PAGE
;
3479 context
->direct_map
= false;
3483 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3484 struct kvm_mmu
*context
)
3486 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3489 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3490 struct kvm_mmu
*context
)
3492 context
->nx
= false;
3493 context
->root_level
= PT32_ROOT_LEVEL
;
3495 reset_rsvds_bits_mask(vcpu
, context
);
3497 context
->new_cr3
= paging_new_cr3
;
3498 context
->page_fault
= paging32_page_fault
;
3499 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3500 context
->free
= paging_free
;
3501 context
->sync_page
= paging32_sync_page
;
3502 context
->invlpg
= paging32_invlpg
;
3503 context
->update_pte
= paging32_update_pte
;
3504 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3505 context
->root_hpa
= INVALID_PAGE
;
3506 context
->direct_map
= false;
3510 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3511 struct kvm_mmu
*context
)
3513 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3516 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3518 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3520 context
->base_role
.word
= 0;
3521 context
->new_cr3
= nonpaging_new_cr3
;
3522 context
->page_fault
= tdp_page_fault
;
3523 context
->free
= nonpaging_free
;
3524 context
->sync_page
= nonpaging_sync_page
;
3525 context
->invlpg
= nonpaging_invlpg
;
3526 context
->update_pte
= nonpaging_update_pte
;
3527 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3528 context
->root_hpa
= INVALID_PAGE
;
3529 context
->direct_map
= true;
3530 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3531 context
->get_cr3
= get_cr3
;
3532 context
->get_pdptr
= kvm_pdptr_read
;
3533 context
->inject_page_fault
= kvm_inject_page_fault
;
3535 if (!is_paging(vcpu
)) {
3536 context
->nx
= false;
3537 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3538 context
->root_level
= 0;
3539 } else if (is_long_mode(vcpu
)) {
3540 context
->nx
= is_nx(vcpu
);
3541 context
->root_level
= PT64_ROOT_LEVEL
;
3542 reset_rsvds_bits_mask(vcpu
, context
);
3543 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3544 } else if (is_pae(vcpu
)) {
3545 context
->nx
= is_nx(vcpu
);
3546 context
->root_level
= PT32E_ROOT_LEVEL
;
3547 reset_rsvds_bits_mask(vcpu
, context
);
3548 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3550 context
->nx
= false;
3551 context
->root_level
= PT32_ROOT_LEVEL
;
3552 reset_rsvds_bits_mask(vcpu
, context
);
3553 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3559 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3562 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3564 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3566 if (!is_paging(vcpu
))
3567 r
= nonpaging_init_context(vcpu
, context
);
3568 else if (is_long_mode(vcpu
))
3569 r
= paging64_init_context(vcpu
, context
);
3570 else if (is_pae(vcpu
))
3571 r
= paging32E_init_context(vcpu
, context
);
3573 r
= paging32_init_context(vcpu
, context
);
3575 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3576 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3577 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3578 = smep
&& !is_write_protection(vcpu
);
3582 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3584 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3586 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3588 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3589 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3590 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3591 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3596 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3598 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3600 g_context
->get_cr3
= get_cr3
;
3601 g_context
->get_pdptr
= kvm_pdptr_read
;
3602 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3605 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3606 * translation of l2_gpa to l1_gpa addresses is done using the
3607 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3608 * functions between mmu and nested_mmu are swapped.
3610 if (!is_paging(vcpu
)) {
3611 g_context
->nx
= false;
3612 g_context
->root_level
= 0;
3613 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3614 } else if (is_long_mode(vcpu
)) {
3615 g_context
->nx
= is_nx(vcpu
);
3616 g_context
->root_level
= PT64_ROOT_LEVEL
;
3617 reset_rsvds_bits_mask(vcpu
, g_context
);
3618 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3619 } else if (is_pae(vcpu
)) {
3620 g_context
->nx
= is_nx(vcpu
);
3621 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3622 reset_rsvds_bits_mask(vcpu
, g_context
);
3623 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3625 g_context
->nx
= false;
3626 g_context
->root_level
= PT32_ROOT_LEVEL
;
3627 reset_rsvds_bits_mask(vcpu
, g_context
);
3628 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3634 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3636 if (mmu_is_nested(vcpu
))
3637 return init_kvm_nested_mmu(vcpu
);
3638 else if (tdp_enabled
)
3639 return init_kvm_tdp_mmu(vcpu
);
3641 return init_kvm_softmmu(vcpu
);
3644 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3647 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3648 /* mmu.free() should set root_hpa = INVALID_PAGE */
3649 vcpu
->arch
.mmu
.free(vcpu
);
3652 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3654 destroy_kvm_mmu(vcpu
);
3655 return init_kvm_mmu(vcpu
);
3657 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3659 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3663 r
= mmu_topup_memory_caches(vcpu
);
3666 r
= mmu_alloc_roots(vcpu
);
3667 spin_lock(&vcpu
->kvm
->mmu_lock
);
3668 mmu_sync_roots(vcpu
);
3669 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3672 /* set_cr3() should ensure TLB has been flushed */
3673 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3677 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3679 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3681 mmu_free_roots(vcpu
);
3683 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3685 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3686 struct kvm_mmu_page
*sp
, u64
*spte
,
3689 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3690 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3694 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3695 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3698 static bool need_remote_flush(u64 old
, u64
new)
3700 if (!is_shadow_present_pte(old
))
3702 if (!is_shadow_present_pte(new))
3704 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3706 old
^= PT64_NX_MASK
;
3707 new ^= PT64_NX_MASK
;
3708 return (old
& ~new & PT64_PERM_MASK
) != 0;
3711 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3712 bool remote_flush
, bool local_flush
)
3718 kvm_flush_remote_tlbs(vcpu
->kvm
);
3719 else if (local_flush
)
3720 kvm_mmu_flush_tlb(vcpu
);
3723 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
3724 const u8
*new, int *bytes
)
3730 * Assume that the pte write on a page table of the same type
3731 * as the current vcpu paging mode since we update the sptes only
3732 * when they have the same mode.
3734 if (is_pae(vcpu
) && *bytes
== 4) {
3735 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3738 r
= kvm_read_guest(vcpu
->kvm
, *gpa
, &gentry
, min(*bytes
, 8));
3741 new = (const u8
*)&gentry
;
3746 gentry
= *(const u32
*)new;
3749 gentry
= *(const u64
*)new;
3760 * If we're seeing too many writes to a page, it may no longer be a page table,
3761 * or we may be forking, in which case it is better to unmap the page.
3763 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
3766 * Skip write-flooding detected for the sp whose level is 1, because
3767 * it can become unsync, then the guest page is not write-protected.
3769 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
3772 return ++sp
->write_flooding_count
>= 3;
3776 * Misaligned accesses are too much trouble to fix up; also, they usually
3777 * indicate a page is not used as a page table.
3779 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
3782 unsigned offset
, pte_size
, misaligned
;
3784 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3785 gpa
, bytes
, sp
->role
.word
);
3787 offset
= offset_in_page(gpa
);
3788 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3791 * Sometimes, the OS only writes the last one bytes to update status
3792 * bits, for example, in linux, andb instruction is used in clear_bit().
3794 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
3797 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3798 misaligned
|= bytes
< 4;
3803 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
3805 unsigned page_offset
, quadrant
;
3809 page_offset
= offset_in_page(gpa
);
3810 level
= sp
->role
.level
;
3812 if (!sp
->role
.cr4_pae
) {
3813 page_offset
<<= 1; /* 32->64 */
3815 * A 32-bit pde maps 4MB while the shadow pdes map
3816 * only 2MB. So we need to double the offset again
3817 * and zap two pdes instead of one.
3819 if (level
== PT32_ROOT_LEVEL
) {
3820 page_offset
&= ~7; /* kill rounding error */
3824 quadrant
= page_offset
>> PAGE_SHIFT
;
3825 page_offset
&= ~PAGE_MASK
;
3826 if (quadrant
!= sp
->role
.quadrant
)
3830 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3834 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3835 const u8
*new, int bytes
)
3837 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3838 union kvm_mmu_page_role mask
= { .word
= 0 };
3839 struct kvm_mmu_page
*sp
;
3840 struct hlist_node
*node
;
3841 LIST_HEAD(invalid_list
);
3842 u64 entry
, gentry
, *spte
;
3844 bool remote_flush
, local_flush
, zap_page
;
3847 * If we don't have indirect shadow pages, it means no page is
3848 * write-protected, so we can exit simply.
3850 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3853 zap_page
= remote_flush
= local_flush
= false;
3855 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3857 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
3860 * No need to care whether allocation memory is successful
3861 * or not since pte prefetch is skiped if it does not have
3862 * enough objects in the cache.
3864 mmu_topup_memory_caches(vcpu
);
3866 spin_lock(&vcpu
->kvm
->mmu_lock
);
3867 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3868 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3870 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3871 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
, node
) {
3872 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
3873 detect_write_flooding(sp
)) {
3874 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3876 ++vcpu
->kvm
->stat
.mmu_flooded
;
3880 spte
= get_written_sptes(sp
, gpa
, &npte
);
3887 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
3889 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
3890 & mask
.word
) && rmap_can_add(vcpu
))
3891 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
3892 if (!remote_flush
&& need_remote_flush(entry
, *spte
))
3893 remote_flush
= true;
3897 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
3898 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3899 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
3900 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3903 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
3908 if (vcpu
->arch
.mmu
.direct_map
)
3911 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
3913 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
3917 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
3919 void __kvm_mmu_free_some_pages(struct kvm_vcpu
*vcpu
)
3921 LIST_HEAD(invalid_list
);
3923 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
&&
3924 !list_empty(&vcpu
->kvm
->arch
.active_mmu_pages
)) {
3925 struct kvm_mmu_page
*sp
;
3927 sp
= container_of(vcpu
->kvm
->arch
.active_mmu_pages
.prev
,
3928 struct kvm_mmu_page
, link
);
3929 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3930 ++vcpu
->kvm
->stat
.mmu_recycled
;
3932 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3935 static bool is_mmio_page_fault(struct kvm_vcpu
*vcpu
, gva_t addr
)
3937 if (vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
))
3938 return vcpu_match_mmio_gpa(vcpu
, addr
);
3940 return vcpu_match_mmio_gva(vcpu
, addr
);
3943 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
3944 void *insn
, int insn_len
)
3946 int r
, emulation_type
= EMULTYPE_RETRY
;
3947 enum emulation_result er
;
3949 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
3958 if (is_mmio_page_fault(vcpu
, cr2
))
3961 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
3966 case EMULATE_DO_MMIO
:
3967 ++vcpu
->stat
.mmio_exits
;
3977 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
3979 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
3981 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
3982 kvm_mmu_flush_tlb(vcpu
);
3983 ++vcpu
->stat
.invlpg
;
3985 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
3987 void kvm_enable_tdp(void)
3991 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
3993 void kvm_disable_tdp(void)
3995 tdp_enabled
= false;
3997 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
3999 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4001 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4002 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4003 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4006 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4014 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4015 * Therefore we need to allocate shadow page tables in the first
4016 * 4GB of memory, which happens to fit the DMA32 zone.
4018 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4022 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4023 for (i
= 0; i
< 4; ++i
)
4024 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4029 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4033 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4034 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4035 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4036 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4038 return alloc_mmu_pages(vcpu
);
4041 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4044 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4046 return init_kvm_mmu(vcpu
);
4049 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
4051 struct kvm_mmu_page
*sp
;
4054 list_for_each_entry(sp
, &kvm
->arch
.active_mmu_pages
, link
) {
4058 if (!test_bit(slot
, sp
->slot_bitmap
))
4062 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
) {
4063 if (!is_shadow_present_pte(pt
[i
]) ||
4064 !is_last_spte(pt
[i
], sp
->role
.level
))
4067 spte_write_protect(kvm
, &pt
[i
], &flush
, false);
4070 kvm_flush_remote_tlbs(kvm
);
4073 void kvm_mmu_zap_all(struct kvm
*kvm
)
4075 struct kvm_mmu_page
*sp
, *node
;
4076 LIST_HEAD(invalid_list
);
4078 spin_lock(&kvm
->mmu_lock
);
4080 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
)
4081 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
4084 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4085 spin_unlock(&kvm
->mmu_lock
);
4088 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm
*kvm
,
4089 struct list_head
*invalid_list
)
4091 struct kvm_mmu_page
*page
;
4093 if (list_empty(&kvm
->arch
.active_mmu_pages
))
4096 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
4097 struct kvm_mmu_page
, link
);
4098 kvm_mmu_prepare_zap_page(kvm
, page
, invalid_list
);
4101 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
4104 int nr_to_scan
= sc
->nr_to_scan
;
4106 if (nr_to_scan
== 0)
4109 raw_spin_lock(&kvm_lock
);
4111 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4113 LIST_HEAD(invalid_list
);
4116 * Never scan more than sc->nr_to_scan VM instances.
4117 * Will not hit this condition practically since we do not try
4118 * to shrink more than one VM and it is very unlikely to see
4119 * !n_used_mmu_pages so many times.
4124 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4125 * here. We may skip a VM instance errorneosly, but we do not
4126 * want to shrink a VM that only started to populate its MMU
4129 if (!kvm
->arch
.n_used_mmu_pages
)
4132 idx
= srcu_read_lock(&kvm
->srcu
);
4133 spin_lock(&kvm
->mmu_lock
);
4135 kvm_mmu_remove_some_alloc_mmu_pages(kvm
, &invalid_list
);
4136 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4138 spin_unlock(&kvm
->mmu_lock
);
4139 srcu_read_unlock(&kvm
->srcu
, idx
);
4141 list_move_tail(&kvm
->vm_list
, &vm_list
);
4145 raw_spin_unlock(&kvm_lock
);
4148 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
4151 static struct shrinker mmu_shrinker
= {
4152 .shrink
= mmu_shrink
,
4153 .seeks
= DEFAULT_SEEKS
* 10,
4156 static void mmu_destroy_caches(void)
4158 if (pte_list_desc_cache
)
4159 kmem_cache_destroy(pte_list_desc_cache
);
4160 if (mmu_page_header_cache
)
4161 kmem_cache_destroy(mmu_page_header_cache
);
4164 int kvm_mmu_module_init(void)
4166 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
4167 sizeof(struct pte_list_desc
),
4169 if (!pte_list_desc_cache
)
4172 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
4173 sizeof(struct kvm_mmu_page
),
4175 if (!mmu_page_header_cache
)
4178 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
4181 register_shrinker(&mmu_shrinker
);
4186 mmu_destroy_caches();
4191 * Caculate mmu pages needed for kvm.
4193 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
4195 unsigned int nr_mmu_pages
;
4196 unsigned int nr_pages
= 0;
4197 struct kvm_memslots
*slots
;
4198 struct kvm_memory_slot
*memslot
;
4200 slots
= kvm_memslots(kvm
);
4202 kvm_for_each_memslot(memslot
, slots
)
4203 nr_pages
+= memslot
->npages
;
4205 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
4206 nr_mmu_pages
= max(nr_mmu_pages
,
4207 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
4209 return nr_mmu_pages
;
4212 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4214 struct kvm_shadow_walk_iterator iterator
;
4218 walk_shadow_page_lockless_begin(vcpu
);
4219 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4220 sptes
[iterator
.level
-1] = spte
;
4222 if (!is_shadow_present_pte(spte
))
4225 walk_shadow_page_lockless_end(vcpu
);
4229 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4231 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4235 destroy_kvm_mmu(vcpu
);
4236 free_mmu_pages(vcpu
);
4237 mmu_free_memory_caches(vcpu
);
4240 void kvm_mmu_module_exit(void)
4242 mmu_destroy_caches();
4243 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4244 unregister_shrinker(&mmu_shrinker
);
4245 mmu_audit_disable();