KVM: Fix mov cr3 #GP at wrong instruction
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include "mmu.h"
22 #include "x86.h"
23 #include "kvm_cache_regs.h"
24
25 #include <linux/kvm_host.h>
26 #include <linux/types.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/highmem.h>
30 #include <linux/module.h>
31 #include <linux/swap.h>
32 #include <linux/hugetlb.h>
33 #include <linux/compiler.h>
34 #include <linux/srcu.h>
35 #include <linux/slab.h>
36 #include <linux/uaccess.h>
37
38 #include <asm/page.h>
39 #include <asm/cmpxchg.h>
40 #include <asm/io.h>
41 #include <asm/vmx.h>
42
43 /*
44 * When setting this variable to true it enables Two-Dimensional-Paging
45 * where the hardware walks 2 page tables:
46 * 1. the guest-virtual to guest-physical
47 * 2. while doing 1. it walks guest-physical to host-physical
48 * If the hardware supports that we don't need to do shadow paging.
49 */
50 bool tdp_enabled = false;
51
52 #undef MMU_DEBUG
53
54 #undef AUDIT
55
56 #ifdef AUDIT
57 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
58 #else
59 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
60 #endif
61
62 #ifdef MMU_DEBUG
63
64 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
65 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
66
67 #else
68
69 #define pgprintk(x...) do { } while (0)
70 #define rmap_printk(x...) do { } while (0)
71
72 #endif
73
74 #if defined(MMU_DEBUG) || defined(AUDIT)
75 static int dbg = 0;
76 module_param(dbg, bool, 0644);
77 #endif
78
79 static int oos_shadow = 1;
80 module_param(oos_shadow, bool, 0644);
81
82 #ifndef MMU_DEBUG
83 #define ASSERT(x) do { } while (0)
84 #else
85 #define ASSERT(x) \
86 if (!(x)) { \
87 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
88 __FILE__, __LINE__, #x); \
89 }
90 #endif
91
92 #define PT_FIRST_AVAIL_BITS_SHIFT 9
93 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
94
95 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
96
97 #define PT64_LEVEL_BITS 9
98
99 #define PT64_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101
102 #define PT64_LEVEL_MASK(level) \
103 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
104
105 #define PT64_INDEX(address, level)\
106 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
107
108
109 #define PT32_LEVEL_BITS 10
110
111 #define PT32_LEVEL_SHIFT(level) \
112 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
113
114 #define PT32_LEVEL_MASK(level) \
115 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
116 #define PT32_LVL_OFFSET_MASK(level) \
117 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
118 * PT32_LEVEL_BITS))) - 1))
119
120 #define PT32_INDEX(address, level)\
121 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
122
123
124 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
125 #define PT64_DIR_BASE_ADDR_MASK \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
127 #define PT64_LVL_ADDR_MASK(level) \
128 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
129 * PT64_LEVEL_BITS))) - 1))
130 #define PT64_LVL_OFFSET_MASK(level) \
131 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
132 * PT64_LEVEL_BITS))) - 1))
133
134 #define PT32_BASE_ADDR_MASK PAGE_MASK
135 #define PT32_DIR_BASE_ADDR_MASK \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
137 #define PT32_LVL_ADDR_MASK(level) \
138 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT32_LEVEL_BITS))) - 1))
140
141 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
142 | PT64_NX_MASK)
143
144 #define RMAP_EXT 4
145
146 #define ACC_EXEC_MASK 1
147 #define ACC_WRITE_MASK PT_WRITABLE_MASK
148 #define ACC_USER_MASK PT_USER_MASK
149 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
150
151 #include <trace/events/kvm.h>
152
153 #define CREATE_TRACE_POINTS
154 #include "mmutrace.h"
155
156 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
157
158 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
159
160 struct kvm_rmap_desc {
161 u64 *sptes[RMAP_EXT];
162 struct kvm_rmap_desc *more;
163 };
164
165 struct kvm_shadow_walk_iterator {
166 u64 addr;
167 hpa_t shadow_addr;
168 int level;
169 u64 *sptep;
170 unsigned index;
171 };
172
173 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
174 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
175 shadow_walk_okay(&(_walker)); \
176 shadow_walk_next(&(_walker)))
177
178 typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
179
180 static struct kmem_cache *pte_chain_cache;
181 static struct kmem_cache *rmap_desc_cache;
182 static struct kmem_cache *mmu_page_header_cache;
183
184 static u64 __read_mostly shadow_trap_nonpresent_pte;
185 static u64 __read_mostly shadow_notrap_nonpresent_pte;
186 static u64 __read_mostly shadow_base_present_pte;
187 static u64 __read_mostly shadow_nx_mask;
188 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
189 static u64 __read_mostly shadow_user_mask;
190 static u64 __read_mostly shadow_accessed_mask;
191 static u64 __read_mostly shadow_dirty_mask;
192
193 static inline u64 rsvd_bits(int s, int e)
194 {
195 return ((1ULL << (e - s + 1)) - 1) << s;
196 }
197
198 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
199 {
200 shadow_trap_nonpresent_pte = trap_pte;
201 shadow_notrap_nonpresent_pte = notrap_pte;
202 }
203 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
204
205 void kvm_mmu_set_base_ptes(u64 base_pte)
206 {
207 shadow_base_present_pte = base_pte;
208 }
209 EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
210
211 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
212 u64 dirty_mask, u64 nx_mask, u64 x_mask)
213 {
214 shadow_user_mask = user_mask;
215 shadow_accessed_mask = accessed_mask;
216 shadow_dirty_mask = dirty_mask;
217 shadow_nx_mask = nx_mask;
218 shadow_x_mask = x_mask;
219 }
220 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
221
222 static bool is_write_protection(struct kvm_vcpu *vcpu)
223 {
224 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
225 }
226
227 static int is_cpuid_PSE36(void)
228 {
229 return 1;
230 }
231
232 static int is_nx(struct kvm_vcpu *vcpu)
233 {
234 return vcpu->arch.efer & EFER_NX;
235 }
236
237 static int is_shadow_present_pte(u64 pte)
238 {
239 return pte != shadow_trap_nonpresent_pte
240 && pte != shadow_notrap_nonpresent_pte;
241 }
242
243 static int is_large_pte(u64 pte)
244 {
245 return pte & PT_PAGE_SIZE_MASK;
246 }
247
248 static int is_writable_pte(unsigned long pte)
249 {
250 return pte & PT_WRITABLE_MASK;
251 }
252
253 static int is_dirty_gpte(unsigned long pte)
254 {
255 return pte & PT_DIRTY_MASK;
256 }
257
258 static int is_rmap_spte(u64 pte)
259 {
260 return is_shadow_present_pte(pte);
261 }
262
263 static int is_last_spte(u64 pte, int level)
264 {
265 if (level == PT_PAGE_TABLE_LEVEL)
266 return 1;
267 if (is_large_pte(pte))
268 return 1;
269 return 0;
270 }
271
272 static pfn_t spte_to_pfn(u64 pte)
273 {
274 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
275 }
276
277 static gfn_t pse36_gfn_delta(u32 gpte)
278 {
279 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
280
281 return (gpte & PT32_DIR_PSE36_MASK) << shift;
282 }
283
284 static void __set_spte(u64 *sptep, u64 spte)
285 {
286 #ifdef CONFIG_X86_64
287 set_64bit((unsigned long *)sptep, spte);
288 #else
289 set_64bit((unsigned long long *)sptep, spte);
290 #endif
291 }
292
293 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
294 struct kmem_cache *base_cache, int min)
295 {
296 void *obj;
297
298 if (cache->nobjs >= min)
299 return 0;
300 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
301 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
302 if (!obj)
303 return -ENOMEM;
304 cache->objects[cache->nobjs++] = obj;
305 }
306 return 0;
307 }
308
309 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
310 struct kmem_cache *cache)
311 {
312 while (mc->nobjs)
313 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
314 }
315
316 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
317 int min)
318 {
319 struct page *page;
320
321 if (cache->nobjs >= min)
322 return 0;
323 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
324 page = alloc_page(GFP_KERNEL);
325 if (!page)
326 return -ENOMEM;
327 cache->objects[cache->nobjs++] = page_address(page);
328 }
329 return 0;
330 }
331
332 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
333 {
334 while (mc->nobjs)
335 free_page((unsigned long)mc->objects[--mc->nobjs]);
336 }
337
338 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
339 {
340 int r;
341
342 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
343 pte_chain_cache, 4);
344 if (r)
345 goto out;
346 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
347 rmap_desc_cache, 4);
348 if (r)
349 goto out;
350 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
351 if (r)
352 goto out;
353 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
354 mmu_page_header_cache, 4);
355 out:
356 return r;
357 }
358
359 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
360 {
361 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
362 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
363 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
364 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
365 mmu_page_header_cache);
366 }
367
368 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
369 size_t size)
370 {
371 void *p;
372
373 BUG_ON(!mc->nobjs);
374 p = mc->objects[--mc->nobjs];
375 return p;
376 }
377
378 static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
379 {
380 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
381 sizeof(struct kvm_pte_chain));
382 }
383
384 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
385 {
386 kmem_cache_free(pte_chain_cache, pc);
387 }
388
389 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
390 {
391 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
392 sizeof(struct kvm_rmap_desc));
393 }
394
395 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
396 {
397 kmem_cache_free(rmap_desc_cache, rd);
398 }
399
400 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
401 {
402 if (!sp->role.direct)
403 return sp->gfns[index];
404
405 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
406 }
407
408 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
409 {
410 if (sp->role.direct)
411 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
412 else
413 sp->gfns[index] = gfn;
414 }
415
416 /*
417 * Return the pointer to the largepage write count for a given
418 * gfn, handling slots that are not large page aligned.
419 */
420 static int *slot_largepage_idx(gfn_t gfn,
421 struct kvm_memory_slot *slot,
422 int level)
423 {
424 unsigned long idx;
425
426 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
427 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
428 return &slot->lpage_info[level - 2][idx].write_count;
429 }
430
431 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
432 {
433 struct kvm_memory_slot *slot;
434 int *write_count;
435 int i;
436
437 gfn = unalias_gfn(kvm, gfn);
438
439 slot = gfn_to_memslot_unaliased(kvm, gfn);
440 for (i = PT_DIRECTORY_LEVEL;
441 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
442 write_count = slot_largepage_idx(gfn, slot, i);
443 *write_count += 1;
444 }
445 }
446
447 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
448 {
449 struct kvm_memory_slot *slot;
450 int *write_count;
451 int i;
452
453 gfn = unalias_gfn(kvm, gfn);
454 slot = gfn_to_memslot_unaliased(kvm, gfn);
455 for (i = PT_DIRECTORY_LEVEL;
456 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
457 write_count = slot_largepage_idx(gfn, slot, i);
458 *write_count -= 1;
459 WARN_ON(*write_count < 0);
460 }
461 }
462
463 static int has_wrprotected_page(struct kvm *kvm,
464 gfn_t gfn,
465 int level)
466 {
467 struct kvm_memory_slot *slot;
468 int *largepage_idx;
469
470 gfn = unalias_gfn(kvm, gfn);
471 slot = gfn_to_memslot_unaliased(kvm, gfn);
472 if (slot) {
473 largepage_idx = slot_largepage_idx(gfn, slot, level);
474 return *largepage_idx;
475 }
476
477 return 1;
478 }
479
480 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
481 {
482 unsigned long page_size;
483 int i, ret = 0;
484
485 page_size = kvm_host_page_size(kvm, gfn);
486
487 for (i = PT_PAGE_TABLE_LEVEL;
488 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
489 if (page_size >= KVM_HPAGE_SIZE(i))
490 ret = i;
491 else
492 break;
493 }
494
495 return ret;
496 }
497
498 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
499 {
500 struct kvm_memory_slot *slot;
501 int host_level, level, max_level;
502
503 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
504 if (slot && slot->dirty_bitmap)
505 return PT_PAGE_TABLE_LEVEL;
506
507 host_level = host_mapping_level(vcpu->kvm, large_gfn);
508
509 if (host_level == PT_PAGE_TABLE_LEVEL)
510 return host_level;
511
512 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
513 kvm_x86_ops->get_lpage_level() : host_level;
514
515 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
516 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
517 break;
518
519 return level - 1;
520 }
521
522 /*
523 * Take gfn and return the reverse mapping to it.
524 * Note: gfn must be unaliased before this function get called
525 */
526
527 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
528 {
529 struct kvm_memory_slot *slot;
530 unsigned long idx;
531
532 slot = gfn_to_memslot(kvm, gfn);
533 if (likely(level == PT_PAGE_TABLE_LEVEL))
534 return &slot->rmap[gfn - slot->base_gfn];
535
536 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
537 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
538
539 return &slot->lpage_info[level - 2][idx].rmap_pde;
540 }
541
542 /*
543 * Reverse mapping data structures:
544 *
545 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
546 * that points to page_address(page).
547 *
548 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
549 * containing more mappings.
550 *
551 * Returns the number of rmap entries before the spte was added or zero if
552 * the spte was not added.
553 *
554 */
555 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
556 {
557 struct kvm_mmu_page *sp;
558 struct kvm_rmap_desc *desc;
559 unsigned long *rmapp;
560 int i, count = 0;
561
562 if (!is_rmap_spte(*spte))
563 return count;
564 gfn = unalias_gfn(vcpu->kvm, gfn);
565 sp = page_header(__pa(spte));
566 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
567 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
568 if (!*rmapp) {
569 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
570 *rmapp = (unsigned long)spte;
571 } else if (!(*rmapp & 1)) {
572 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
573 desc = mmu_alloc_rmap_desc(vcpu);
574 desc->sptes[0] = (u64 *)*rmapp;
575 desc->sptes[1] = spte;
576 *rmapp = (unsigned long)desc | 1;
577 } else {
578 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
579 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
580 while (desc->sptes[RMAP_EXT-1] && desc->more) {
581 desc = desc->more;
582 count += RMAP_EXT;
583 }
584 if (desc->sptes[RMAP_EXT-1]) {
585 desc->more = mmu_alloc_rmap_desc(vcpu);
586 desc = desc->more;
587 }
588 for (i = 0; desc->sptes[i]; ++i)
589 ;
590 desc->sptes[i] = spte;
591 }
592 return count;
593 }
594
595 static void rmap_desc_remove_entry(unsigned long *rmapp,
596 struct kvm_rmap_desc *desc,
597 int i,
598 struct kvm_rmap_desc *prev_desc)
599 {
600 int j;
601
602 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
603 ;
604 desc->sptes[i] = desc->sptes[j];
605 desc->sptes[j] = NULL;
606 if (j != 0)
607 return;
608 if (!prev_desc && !desc->more)
609 *rmapp = (unsigned long)desc->sptes[0];
610 else
611 if (prev_desc)
612 prev_desc->more = desc->more;
613 else
614 *rmapp = (unsigned long)desc->more | 1;
615 mmu_free_rmap_desc(desc);
616 }
617
618 static void rmap_remove(struct kvm *kvm, u64 *spte)
619 {
620 struct kvm_rmap_desc *desc;
621 struct kvm_rmap_desc *prev_desc;
622 struct kvm_mmu_page *sp;
623 pfn_t pfn;
624 gfn_t gfn;
625 unsigned long *rmapp;
626 int i;
627
628 if (!is_rmap_spte(*spte))
629 return;
630 sp = page_header(__pa(spte));
631 pfn = spte_to_pfn(*spte);
632 if (*spte & shadow_accessed_mask)
633 kvm_set_pfn_accessed(pfn);
634 if (is_writable_pte(*spte))
635 kvm_set_pfn_dirty(pfn);
636 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
637 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
638 if (!*rmapp) {
639 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
640 BUG();
641 } else if (!(*rmapp & 1)) {
642 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
643 if ((u64 *)*rmapp != spte) {
644 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
645 spte, *spte);
646 BUG();
647 }
648 *rmapp = 0;
649 } else {
650 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
651 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
652 prev_desc = NULL;
653 while (desc) {
654 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
655 if (desc->sptes[i] == spte) {
656 rmap_desc_remove_entry(rmapp,
657 desc, i,
658 prev_desc);
659 return;
660 }
661 prev_desc = desc;
662 desc = desc->more;
663 }
664 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
665 BUG();
666 }
667 }
668
669 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
670 {
671 struct kvm_rmap_desc *desc;
672 u64 *prev_spte;
673 int i;
674
675 if (!*rmapp)
676 return NULL;
677 else if (!(*rmapp & 1)) {
678 if (!spte)
679 return (u64 *)*rmapp;
680 return NULL;
681 }
682 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
683 prev_spte = NULL;
684 while (desc) {
685 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
686 if (prev_spte == spte)
687 return desc->sptes[i];
688 prev_spte = desc->sptes[i];
689 }
690 desc = desc->more;
691 }
692 return NULL;
693 }
694
695 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
696 {
697 unsigned long *rmapp;
698 u64 *spte;
699 int i, write_protected = 0;
700
701 gfn = unalias_gfn(kvm, gfn);
702 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
703
704 spte = rmap_next(kvm, rmapp, NULL);
705 while (spte) {
706 BUG_ON(!spte);
707 BUG_ON(!(*spte & PT_PRESENT_MASK));
708 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
709 if (is_writable_pte(*spte)) {
710 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
711 write_protected = 1;
712 }
713 spte = rmap_next(kvm, rmapp, spte);
714 }
715 if (write_protected) {
716 pfn_t pfn;
717
718 spte = rmap_next(kvm, rmapp, NULL);
719 pfn = spte_to_pfn(*spte);
720 kvm_set_pfn_dirty(pfn);
721 }
722
723 /* check for huge page mappings */
724 for (i = PT_DIRECTORY_LEVEL;
725 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
726 rmapp = gfn_to_rmap(kvm, gfn, i);
727 spte = rmap_next(kvm, rmapp, NULL);
728 while (spte) {
729 BUG_ON(!spte);
730 BUG_ON(!(*spte & PT_PRESENT_MASK));
731 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
732 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
733 if (is_writable_pte(*spte)) {
734 rmap_remove(kvm, spte);
735 --kvm->stat.lpages;
736 __set_spte(spte, shadow_trap_nonpresent_pte);
737 spte = NULL;
738 write_protected = 1;
739 }
740 spte = rmap_next(kvm, rmapp, spte);
741 }
742 }
743
744 return write_protected;
745 }
746
747 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
748 unsigned long data)
749 {
750 u64 *spte;
751 int need_tlb_flush = 0;
752
753 while ((spte = rmap_next(kvm, rmapp, NULL))) {
754 BUG_ON(!(*spte & PT_PRESENT_MASK));
755 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
756 rmap_remove(kvm, spte);
757 __set_spte(spte, shadow_trap_nonpresent_pte);
758 need_tlb_flush = 1;
759 }
760 return need_tlb_flush;
761 }
762
763 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
764 unsigned long data)
765 {
766 int need_flush = 0;
767 u64 *spte, new_spte;
768 pte_t *ptep = (pte_t *)data;
769 pfn_t new_pfn;
770
771 WARN_ON(pte_huge(*ptep));
772 new_pfn = pte_pfn(*ptep);
773 spte = rmap_next(kvm, rmapp, NULL);
774 while (spte) {
775 BUG_ON(!is_shadow_present_pte(*spte));
776 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
777 need_flush = 1;
778 if (pte_write(*ptep)) {
779 rmap_remove(kvm, spte);
780 __set_spte(spte, shadow_trap_nonpresent_pte);
781 spte = rmap_next(kvm, rmapp, NULL);
782 } else {
783 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
784 new_spte |= (u64)new_pfn << PAGE_SHIFT;
785
786 new_spte &= ~PT_WRITABLE_MASK;
787 new_spte &= ~SPTE_HOST_WRITEABLE;
788 if (is_writable_pte(*spte))
789 kvm_set_pfn_dirty(spte_to_pfn(*spte));
790 __set_spte(spte, new_spte);
791 spte = rmap_next(kvm, rmapp, spte);
792 }
793 }
794 if (need_flush)
795 kvm_flush_remote_tlbs(kvm);
796
797 return 0;
798 }
799
800 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
801 unsigned long data,
802 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
803 unsigned long data))
804 {
805 int i, j;
806 int ret;
807 int retval = 0;
808 struct kvm_memslots *slots;
809
810 slots = kvm_memslots(kvm);
811
812 for (i = 0; i < slots->nmemslots; i++) {
813 struct kvm_memory_slot *memslot = &slots->memslots[i];
814 unsigned long start = memslot->userspace_addr;
815 unsigned long end;
816
817 end = start + (memslot->npages << PAGE_SHIFT);
818 if (hva >= start && hva < end) {
819 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
820
821 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
822
823 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
824 int idx = gfn_offset;
825 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
826 ret |= handler(kvm,
827 &memslot->lpage_info[j][idx].rmap_pde,
828 data);
829 }
830 trace_kvm_age_page(hva, memslot, ret);
831 retval |= ret;
832 }
833 }
834
835 return retval;
836 }
837
838 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
839 {
840 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
841 }
842
843 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
844 {
845 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
846 }
847
848 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
849 unsigned long data)
850 {
851 u64 *spte;
852 int young = 0;
853
854 /*
855 * Emulate the accessed bit for EPT, by checking if this page has
856 * an EPT mapping, and clearing it if it does. On the next access,
857 * a new EPT mapping will be established.
858 * This has some overhead, but not as much as the cost of swapping
859 * out actively used pages or breaking up actively used hugepages.
860 */
861 if (!shadow_accessed_mask)
862 return kvm_unmap_rmapp(kvm, rmapp, data);
863
864 spte = rmap_next(kvm, rmapp, NULL);
865 while (spte) {
866 int _young;
867 u64 _spte = *spte;
868 BUG_ON(!(_spte & PT_PRESENT_MASK));
869 _young = _spte & PT_ACCESSED_MASK;
870 if (_young) {
871 young = 1;
872 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
873 }
874 spte = rmap_next(kvm, rmapp, spte);
875 }
876 return young;
877 }
878
879 #define RMAP_RECYCLE_THRESHOLD 1000
880
881 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
882 {
883 unsigned long *rmapp;
884 struct kvm_mmu_page *sp;
885
886 sp = page_header(__pa(spte));
887
888 gfn = unalias_gfn(vcpu->kvm, gfn);
889 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
890
891 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
892 kvm_flush_remote_tlbs(vcpu->kvm);
893 }
894
895 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
896 {
897 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
898 }
899
900 #ifdef MMU_DEBUG
901 static int is_empty_shadow_page(u64 *spt)
902 {
903 u64 *pos;
904 u64 *end;
905
906 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
907 if (is_shadow_present_pte(*pos)) {
908 printk(KERN_ERR "%s: %p %llx\n", __func__,
909 pos, *pos);
910 return 0;
911 }
912 return 1;
913 }
914 #endif
915
916 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
917 {
918 ASSERT(is_empty_shadow_page(sp->spt));
919 hlist_del(&sp->hash_link);
920 list_del(&sp->link);
921 __free_page(virt_to_page(sp->spt));
922 if (!sp->role.direct)
923 __free_page(virt_to_page(sp->gfns));
924 kmem_cache_free(mmu_page_header_cache, sp);
925 ++kvm->arch.n_free_mmu_pages;
926 }
927
928 static unsigned kvm_page_table_hashfn(gfn_t gfn)
929 {
930 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
931 }
932
933 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
934 u64 *parent_pte, int direct)
935 {
936 struct kvm_mmu_page *sp;
937
938 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
939 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
940 if (!direct)
941 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
942 PAGE_SIZE);
943 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
944 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
945 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
946 sp->multimapped = 0;
947 sp->parent_pte = parent_pte;
948 --vcpu->kvm->arch.n_free_mmu_pages;
949 return sp;
950 }
951
952 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
953 struct kvm_mmu_page *sp, u64 *parent_pte)
954 {
955 struct kvm_pte_chain *pte_chain;
956 struct hlist_node *node;
957 int i;
958
959 if (!parent_pte)
960 return;
961 if (!sp->multimapped) {
962 u64 *old = sp->parent_pte;
963
964 if (!old) {
965 sp->parent_pte = parent_pte;
966 return;
967 }
968 sp->multimapped = 1;
969 pte_chain = mmu_alloc_pte_chain(vcpu);
970 INIT_HLIST_HEAD(&sp->parent_ptes);
971 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
972 pte_chain->parent_ptes[0] = old;
973 }
974 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
975 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
976 continue;
977 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
978 if (!pte_chain->parent_ptes[i]) {
979 pte_chain->parent_ptes[i] = parent_pte;
980 return;
981 }
982 }
983 pte_chain = mmu_alloc_pte_chain(vcpu);
984 BUG_ON(!pte_chain);
985 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
986 pte_chain->parent_ptes[0] = parent_pte;
987 }
988
989 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
990 u64 *parent_pte)
991 {
992 struct kvm_pte_chain *pte_chain;
993 struct hlist_node *node;
994 int i;
995
996 if (!sp->multimapped) {
997 BUG_ON(sp->parent_pte != parent_pte);
998 sp->parent_pte = NULL;
999 return;
1000 }
1001 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1002 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1003 if (!pte_chain->parent_ptes[i])
1004 break;
1005 if (pte_chain->parent_ptes[i] != parent_pte)
1006 continue;
1007 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1008 && pte_chain->parent_ptes[i + 1]) {
1009 pte_chain->parent_ptes[i]
1010 = pte_chain->parent_ptes[i + 1];
1011 ++i;
1012 }
1013 pte_chain->parent_ptes[i] = NULL;
1014 if (i == 0) {
1015 hlist_del(&pte_chain->link);
1016 mmu_free_pte_chain(pte_chain);
1017 if (hlist_empty(&sp->parent_ptes)) {
1018 sp->multimapped = 0;
1019 sp->parent_pte = NULL;
1020 }
1021 }
1022 return;
1023 }
1024 BUG();
1025 }
1026
1027
1028 static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
1029 {
1030 struct kvm_pte_chain *pte_chain;
1031 struct hlist_node *node;
1032 struct kvm_mmu_page *parent_sp;
1033 int i;
1034
1035 if (!sp->multimapped && sp->parent_pte) {
1036 parent_sp = page_header(__pa(sp->parent_pte));
1037 fn(parent_sp);
1038 mmu_parent_walk(parent_sp, fn);
1039 return;
1040 }
1041 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1042 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1043 if (!pte_chain->parent_ptes[i])
1044 break;
1045 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1046 fn(parent_sp);
1047 mmu_parent_walk(parent_sp, fn);
1048 }
1049 }
1050
1051 static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1052 {
1053 unsigned int index;
1054 struct kvm_mmu_page *sp = page_header(__pa(spte));
1055
1056 index = spte - sp->spt;
1057 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1058 sp->unsync_children++;
1059 WARN_ON(!sp->unsync_children);
1060 }
1061
1062 static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1063 {
1064 struct kvm_pte_chain *pte_chain;
1065 struct hlist_node *node;
1066 int i;
1067
1068 if (!sp->parent_pte)
1069 return;
1070
1071 if (!sp->multimapped) {
1072 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1073 return;
1074 }
1075
1076 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1077 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1078 if (!pte_chain->parent_ptes[i])
1079 break;
1080 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1081 }
1082 }
1083
1084 static int unsync_walk_fn(struct kvm_mmu_page *sp)
1085 {
1086 kvm_mmu_update_parents_unsync(sp);
1087 return 1;
1088 }
1089
1090 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1091 {
1092 mmu_parent_walk(sp, unsync_walk_fn);
1093 kvm_mmu_update_parents_unsync(sp);
1094 }
1095
1096 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1097 struct kvm_mmu_page *sp)
1098 {
1099 int i;
1100
1101 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1102 sp->spt[i] = shadow_trap_nonpresent_pte;
1103 }
1104
1105 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1106 struct kvm_mmu_page *sp)
1107 {
1108 return 1;
1109 }
1110
1111 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1112 {
1113 }
1114
1115 #define KVM_PAGE_ARRAY_NR 16
1116
1117 struct kvm_mmu_pages {
1118 struct mmu_page_and_offset {
1119 struct kvm_mmu_page *sp;
1120 unsigned int idx;
1121 } page[KVM_PAGE_ARRAY_NR];
1122 unsigned int nr;
1123 };
1124
1125 #define for_each_unsync_children(bitmap, idx) \
1126 for (idx = find_first_bit(bitmap, 512); \
1127 idx < 512; \
1128 idx = find_next_bit(bitmap, 512, idx+1))
1129
1130 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1131 int idx)
1132 {
1133 int i;
1134
1135 if (sp->unsync)
1136 for (i=0; i < pvec->nr; i++)
1137 if (pvec->page[i].sp == sp)
1138 return 0;
1139
1140 pvec->page[pvec->nr].sp = sp;
1141 pvec->page[pvec->nr].idx = idx;
1142 pvec->nr++;
1143 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1144 }
1145
1146 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1147 struct kvm_mmu_pages *pvec)
1148 {
1149 int i, ret, nr_unsync_leaf = 0;
1150
1151 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1152 u64 ent = sp->spt[i];
1153
1154 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
1155 struct kvm_mmu_page *child;
1156 child = page_header(ent & PT64_BASE_ADDR_MASK);
1157
1158 if (child->unsync_children) {
1159 if (mmu_pages_add(pvec, child, i))
1160 return -ENOSPC;
1161
1162 ret = __mmu_unsync_walk(child, pvec);
1163 if (!ret)
1164 __clear_bit(i, sp->unsync_child_bitmap);
1165 else if (ret > 0)
1166 nr_unsync_leaf += ret;
1167 else
1168 return ret;
1169 }
1170
1171 if (child->unsync) {
1172 nr_unsync_leaf++;
1173 if (mmu_pages_add(pvec, child, i))
1174 return -ENOSPC;
1175 }
1176 }
1177 }
1178
1179 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
1180 sp->unsync_children = 0;
1181
1182 return nr_unsync_leaf;
1183 }
1184
1185 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1186 struct kvm_mmu_pages *pvec)
1187 {
1188 if (!sp->unsync_children)
1189 return 0;
1190
1191 mmu_pages_add(pvec, sp, 0);
1192 return __mmu_unsync_walk(sp, pvec);
1193 }
1194
1195 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1196 {
1197 WARN_ON(!sp->unsync);
1198 trace_kvm_mmu_sync_page(sp);
1199 sp->unsync = 0;
1200 --kvm->stat.mmu_unsync;
1201 }
1202
1203 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1204 struct list_head *invalid_list);
1205 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1206 struct list_head *invalid_list);
1207
1208 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1209 hlist_for_each_entry(sp, pos, \
1210 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1211 if ((sp)->gfn != (gfn)) {} else
1212
1213 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1214 hlist_for_each_entry(sp, pos, \
1215 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1216 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1217 (sp)->role.invalid) {} else
1218
1219 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1220 struct list_head *invalid_list, bool clear_unsync)
1221 {
1222 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1223 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1224 return 1;
1225 }
1226
1227 if (clear_unsync) {
1228 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1229 kvm_flush_remote_tlbs(vcpu->kvm);
1230 kvm_unlink_unsync_page(vcpu->kvm, sp);
1231 }
1232
1233 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1234 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1235 return 1;
1236 }
1237
1238 kvm_mmu_flush_tlb(vcpu);
1239 return 0;
1240 }
1241
1242 static void mmu_convert_notrap(struct kvm_mmu_page *sp);
1243 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1244 struct kvm_mmu_page *sp)
1245 {
1246 LIST_HEAD(invalid_list);
1247 int ret;
1248
1249 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1250 if (!ret)
1251 mmu_convert_notrap(sp);
1252 else
1253 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1254
1255 return ret;
1256 }
1257
1258 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1259 struct list_head *invalid_list)
1260 {
1261 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1262 }
1263
1264 /* @gfn should be write-protected at the call site */
1265 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1266 {
1267 struct kvm_mmu_page *s;
1268 struct hlist_node *node;
1269 LIST_HEAD(invalid_list);
1270 bool flush = false;
1271
1272 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1273 if (!s->unsync)
1274 continue;
1275
1276 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1277 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1278 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1279 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1280 continue;
1281 }
1282 kvm_unlink_unsync_page(vcpu->kvm, s);
1283 flush = true;
1284 }
1285
1286 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1287 if (flush)
1288 kvm_mmu_flush_tlb(vcpu);
1289 }
1290
1291 struct mmu_page_path {
1292 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1293 unsigned int idx[PT64_ROOT_LEVEL-1];
1294 };
1295
1296 #define for_each_sp(pvec, sp, parents, i) \
1297 for (i = mmu_pages_next(&pvec, &parents, -1), \
1298 sp = pvec.page[i].sp; \
1299 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1300 i = mmu_pages_next(&pvec, &parents, i))
1301
1302 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1303 struct mmu_page_path *parents,
1304 int i)
1305 {
1306 int n;
1307
1308 for (n = i+1; n < pvec->nr; n++) {
1309 struct kvm_mmu_page *sp = pvec->page[n].sp;
1310
1311 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1312 parents->idx[0] = pvec->page[n].idx;
1313 return n;
1314 }
1315
1316 parents->parent[sp->role.level-2] = sp;
1317 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1318 }
1319
1320 return n;
1321 }
1322
1323 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1324 {
1325 struct kvm_mmu_page *sp;
1326 unsigned int level = 0;
1327
1328 do {
1329 unsigned int idx = parents->idx[level];
1330
1331 sp = parents->parent[level];
1332 if (!sp)
1333 return;
1334
1335 --sp->unsync_children;
1336 WARN_ON((int)sp->unsync_children < 0);
1337 __clear_bit(idx, sp->unsync_child_bitmap);
1338 level++;
1339 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1340 }
1341
1342 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1343 struct mmu_page_path *parents,
1344 struct kvm_mmu_pages *pvec)
1345 {
1346 parents->parent[parent->role.level-1] = NULL;
1347 pvec->nr = 0;
1348 }
1349
1350 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1351 struct kvm_mmu_page *parent)
1352 {
1353 int i;
1354 struct kvm_mmu_page *sp;
1355 struct mmu_page_path parents;
1356 struct kvm_mmu_pages pages;
1357 LIST_HEAD(invalid_list);
1358
1359 kvm_mmu_pages_init(parent, &parents, &pages);
1360 while (mmu_unsync_walk(parent, &pages)) {
1361 int protected = 0;
1362
1363 for_each_sp(pages, sp, parents, i)
1364 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1365
1366 if (protected)
1367 kvm_flush_remote_tlbs(vcpu->kvm);
1368
1369 for_each_sp(pages, sp, parents, i) {
1370 kvm_sync_page(vcpu, sp, &invalid_list);
1371 mmu_pages_clear_parents(&parents);
1372 }
1373 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1374 cond_resched_lock(&vcpu->kvm->mmu_lock);
1375 kvm_mmu_pages_init(parent, &parents, &pages);
1376 }
1377 }
1378
1379 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1380 gfn_t gfn,
1381 gva_t gaddr,
1382 unsigned level,
1383 int direct,
1384 unsigned access,
1385 u64 *parent_pte)
1386 {
1387 union kvm_mmu_page_role role;
1388 unsigned quadrant;
1389 struct kvm_mmu_page *sp;
1390 struct hlist_node *node;
1391 bool need_sync = false;
1392
1393 role = vcpu->arch.mmu.base_role;
1394 role.level = level;
1395 role.direct = direct;
1396 if (role.direct)
1397 role.cr4_pae = 0;
1398 role.access = access;
1399 if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1400 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1401 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1402 role.quadrant = quadrant;
1403 }
1404 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1405 if (!need_sync && sp->unsync)
1406 need_sync = true;
1407
1408 if (sp->role.word != role.word)
1409 continue;
1410
1411 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1412 break;
1413
1414 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1415 if (sp->unsync_children) {
1416 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1417 kvm_mmu_mark_parents_unsync(sp);
1418 } else if (sp->unsync)
1419 kvm_mmu_mark_parents_unsync(sp);
1420
1421 trace_kvm_mmu_get_page(sp, false);
1422 return sp;
1423 }
1424 ++vcpu->kvm->stat.mmu_cache_miss;
1425 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1426 if (!sp)
1427 return sp;
1428 sp->gfn = gfn;
1429 sp->role = role;
1430 hlist_add_head(&sp->hash_link,
1431 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1432 if (!direct) {
1433 if (rmap_write_protect(vcpu->kvm, gfn))
1434 kvm_flush_remote_tlbs(vcpu->kvm);
1435 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1436 kvm_sync_pages(vcpu, gfn);
1437
1438 account_shadowed(vcpu->kvm, gfn);
1439 }
1440 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1441 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1442 else
1443 nonpaging_prefetch_page(vcpu, sp);
1444 trace_kvm_mmu_get_page(sp, true);
1445 return sp;
1446 }
1447
1448 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1449 struct kvm_vcpu *vcpu, u64 addr)
1450 {
1451 iterator->addr = addr;
1452 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1453 iterator->level = vcpu->arch.mmu.shadow_root_level;
1454 if (iterator->level == PT32E_ROOT_LEVEL) {
1455 iterator->shadow_addr
1456 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1457 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1458 --iterator->level;
1459 if (!iterator->shadow_addr)
1460 iterator->level = 0;
1461 }
1462 }
1463
1464 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1465 {
1466 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1467 return false;
1468
1469 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1470 if (is_large_pte(*iterator->sptep))
1471 return false;
1472
1473 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1474 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1475 return true;
1476 }
1477
1478 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1479 {
1480 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1481 --iterator->level;
1482 }
1483
1484 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1485 struct kvm_mmu_page *sp)
1486 {
1487 unsigned i;
1488 u64 *pt;
1489 u64 ent;
1490
1491 pt = sp->spt;
1492
1493 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1494 ent = pt[i];
1495
1496 if (is_shadow_present_pte(ent)) {
1497 if (!is_last_spte(ent, sp->role.level)) {
1498 ent &= PT64_BASE_ADDR_MASK;
1499 mmu_page_remove_parent_pte(page_header(ent),
1500 &pt[i]);
1501 } else {
1502 if (is_large_pte(ent))
1503 --kvm->stat.lpages;
1504 rmap_remove(kvm, &pt[i]);
1505 }
1506 }
1507 pt[i] = shadow_trap_nonpresent_pte;
1508 }
1509 }
1510
1511 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1512 {
1513 mmu_page_remove_parent_pte(sp, parent_pte);
1514 }
1515
1516 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1517 {
1518 int i;
1519 struct kvm_vcpu *vcpu;
1520
1521 kvm_for_each_vcpu(i, vcpu, kvm)
1522 vcpu->arch.last_pte_updated = NULL;
1523 }
1524
1525 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1526 {
1527 u64 *parent_pte;
1528
1529 while (sp->multimapped || sp->parent_pte) {
1530 if (!sp->multimapped)
1531 parent_pte = sp->parent_pte;
1532 else {
1533 struct kvm_pte_chain *chain;
1534
1535 chain = container_of(sp->parent_ptes.first,
1536 struct kvm_pte_chain, link);
1537 parent_pte = chain->parent_ptes[0];
1538 }
1539 BUG_ON(!parent_pte);
1540 kvm_mmu_put_page(sp, parent_pte);
1541 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1542 }
1543 }
1544
1545 static int mmu_zap_unsync_children(struct kvm *kvm,
1546 struct kvm_mmu_page *parent,
1547 struct list_head *invalid_list)
1548 {
1549 int i, zapped = 0;
1550 struct mmu_page_path parents;
1551 struct kvm_mmu_pages pages;
1552
1553 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1554 return 0;
1555
1556 kvm_mmu_pages_init(parent, &parents, &pages);
1557 while (mmu_unsync_walk(parent, &pages)) {
1558 struct kvm_mmu_page *sp;
1559
1560 for_each_sp(pages, sp, parents, i) {
1561 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1562 mmu_pages_clear_parents(&parents);
1563 zapped++;
1564 }
1565 kvm_mmu_pages_init(parent, &parents, &pages);
1566 }
1567
1568 return zapped;
1569 }
1570
1571 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1572 struct list_head *invalid_list)
1573 {
1574 int ret;
1575
1576 trace_kvm_mmu_prepare_zap_page(sp);
1577 ++kvm->stat.mmu_shadow_zapped;
1578 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1579 kvm_mmu_page_unlink_children(kvm, sp);
1580 kvm_mmu_unlink_parents(kvm, sp);
1581 if (!sp->role.invalid && !sp->role.direct)
1582 unaccount_shadowed(kvm, sp->gfn);
1583 if (sp->unsync)
1584 kvm_unlink_unsync_page(kvm, sp);
1585 if (!sp->root_count) {
1586 /* Count self */
1587 ret++;
1588 list_move(&sp->link, invalid_list);
1589 } else {
1590 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1591 kvm_reload_remote_mmus(kvm);
1592 }
1593
1594 sp->role.invalid = 1;
1595 kvm_mmu_reset_last_pte_updated(kvm);
1596 return ret;
1597 }
1598
1599 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1600 struct list_head *invalid_list)
1601 {
1602 struct kvm_mmu_page *sp;
1603
1604 if (list_empty(invalid_list))
1605 return;
1606
1607 kvm_flush_remote_tlbs(kvm);
1608
1609 do {
1610 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1611 WARN_ON(!sp->role.invalid || sp->root_count);
1612 kvm_mmu_free_page(kvm, sp);
1613 } while (!list_empty(invalid_list));
1614
1615 }
1616
1617 /*
1618 * Changing the number of mmu pages allocated to the vm
1619 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1620 */
1621 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1622 {
1623 int used_pages;
1624 LIST_HEAD(invalid_list);
1625
1626 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1627 used_pages = max(0, used_pages);
1628
1629 /*
1630 * If we set the number of mmu pages to be smaller be than the
1631 * number of actived pages , we must to free some mmu pages before we
1632 * change the value
1633 */
1634
1635 if (used_pages > kvm_nr_mmu_pages) {
1636 while (used_pages > kvm_nr_mmu_pages &&
1637 !list_empty(&kvm->arch.active_mmu_pages)) {
1638 struct kvm_mmu_page *page;
1639
1640 page = container_of(kvm->arch.active_mmu_pages.prev,
1641 struct kvm_mmu_page, link);
1642 used_pages -= kvm_mmu_prepare_zap_page(kvm, page,
1643 &invalid_list);
1644 }
1645 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1646 kvm_nr_mmu_pages = used_pages;
1647 kvm->arch.n_free_mmu_pages = 0;
1648 }
1649 else
1650 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1651 - kvm->arch.n_alloc_mmu_pages;
1652
1653 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
1654 }
1655
1656 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1657 {
1658 struct kvm_mmu_page *sp;
1659 struct hlist_node *node;
1660 LIST_HEAD(invalid_list);
1661 int r;
1662
1663 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1664 r = 0;
1665
1666 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1667 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
1668 sp->role.word);
1669 r = 1;
1670 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1671 }
1672 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1673 return r;
1674 }
1675
1676 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1677 {
1678 struct kvm_mmu_page *sp;
1679 struct hlist_node *node;
1680 LIST_HEAD(invalid_list);
1681
1682 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1683 pgprintk("%s: zap %lx %x\n",
1684 __func__, gfn, sp->role.word);
1685 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1686 }
1687 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1688 }
1689
1690 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1691 {
1692 int slot = memslot_id(kvm, gfn);
1693 struct kvm_mmu_page *sp = page_header(__pa(pte));
1694
1695 __set_bit(slot, sp->slot_bitmap);
1696 }
1697
1698 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1699 {
1700 int i;
1701 u64 *pt = sp->spt;
1702
1703 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1704 return;
1705
1706 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1707 if (pt[i] == shadow_notrap_nonpresent_pte)
1708 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1709 }
1710 }
1711
1712 /*
1713 * The function is based on mtrr_type_lookup() in
1714 * arch/x86/kernel/cpu/mtrr/generic.c
1715 */
1716 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1717 u64 start, u64 end)
1718 {
1719 int i;
1720 u64 base, mask;
1721 u8 prev_match, curr_match;
1722 int num_var_ranges = KVM_NR_VAR_MTRR;
1723
1724 if (!mtrr_state->enabled)
1725 return 0xFF;
1726
1727 /* Make end inclusive end, instead of exclusive */
1728 end--;
1729
1730 /* Look in fixed ranges. Just return the type as per start */
1731 if (mtrr_state->have_fixed && (start < 0x100000)) {
1732 int idx;
1733
1734 if (start < 0x80000) {
1735 idx = 0;
1736 idx += (start >> 16);
1737 return mtrr_state->fixed_ranges[idx];
1738 } else if (start < 0xC0000) {
1739 idx = 1 * 8;
1740 idx += ((start - 0x80000) >> 14);
1741 return mtrr_state->fixed_ranges[idx];
1742 } else if (start < 0x1000000) {
1743 idx = 3 * 8;
1744 idx += ((start - 0xC0000) >> 12);
1745 return mtrr_state->fixed_ranges[idx];
1746 }
1747 }
1748
1749 /*
1750 * Look in variable ranges
1751 * Look of multiple ranges matching this address and pick type
1752 * as per MTRR precedence
1753 */
1754 if (!(mtrr_state->enabled & 2))
1755 return mtrr_state->def_type;
1756
1757 prev_match = 0xFF;
1758 for (i = 0; i < num_var_ranges; ++i) {
1759 unsigned short start_state, end_state;
1760
1761 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1762 continue;
1763
1764 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1765 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1766 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1767 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1768
1769 start_state = ((start & mask) == (base & mask));
1770 end_state = ((end & mask) == (base & mask));
1771 if (start_state != end_state)
1772 return 0xFE;
1773
1774 if ((start & mask) != (base & mask))
1775 continue;
1776
1777 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1778 if (prev_match == 0xFF) {
1779 prev_match = curr_match;
1780 continue;
1781 }
1782
1783 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1784 curr_match == MTRR_TYPE_UNCACHABLE)
1785 return MTRR_TYPE_UNCACHABLE;
1786
1787 if ((prev_match == MTRR_TYPE_WRBACK &&
1788 curr_match == MTRR_TYPE_WRTHROUGH) ||
1789 (prev_match == MTRR_TYPE_WRTHROUGH &&
1790 curr_match == MTRR_TYPE_WRBACK)) {
1791 prev_match = MTRR_TYPE_WRTHROUGH;
1792 curr_match = MTRR_TYPE_WRTHROUGH;
1793 }
1794
1795 if (prev_match != curr_match)
1796 return MTRR_TYPE_UNCACHABLE;
1797 }
1798
1799 if (prev_match != 0xFF)
1800 return prev_match;
1801
1802 return mtrr_state->def_type;
1803 }
1804
1805 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1806 {
1807 u8 mtrr;
1808
1809 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1810 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1811 if (mtrr == 0xfe || mtrr == 0xff)
1812 mtrr = MTRR_TYPE_WRBACK;
1813 return mtrr;
1814 }
1815 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1816
1817 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1818 {
1819 trace_kvm_mmu_unsync_page(sp);
1820 ++vcpu->kvm->stat.mmu_unsync;
1821 sp->unsync = 1;
1822
1823 kvm_mmu_mark_parents_unsync(sp);
1824 mmu_convert_notrap(sp);
1825 }
1826
1827 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1828 {
1829 struct kvm_mmu_page *s;
1830 struct hlist_node *node;
1831
1832 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1833 if (s->unsync)
1834 continue;
1835 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1836 __kvm_unsync_page(vcpu, s);
1837 }
1838 }
1839
1840 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1841 bool can_unsync)
1842 {
1843 struct kvm_mmu_page *s;
1844 struct hlist_node *node;
1845 bool need_unsync = false;
1846
1847 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1848 if (s->role.level != PT_PAGE_TABLE_LEVEL)
1849 return 1;
1850
1851 if (!need_unsync && !s->unsync) {
1852 if (!can_unsync || !oos_shadow)
1853 return 1;
1854 need_unsync = true;
1855 }
1856 }
1857 if (need_unsync)
1858 kvm_unsync_pages(vcpu, gfn);
1859 return 0;
1860 }
1861
1862 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1863 unsigned pte_access, int user_fault,
1864 int write_fault, int dirty, int level,
1865 gfn_t gfn, pfn_t pfn, bool speculative,
1866 bool can_unsync, bool reset_host_protection)
1867 {
1868 u64 spte;
1869 int ret = 0;
1870
1871 /*
1872 * We don't set the accessed bit, since we sometimes want to see
1873 * whether the guest actually used the pte (in order to detect
1874 * demand paging).
1875 */
1876 spte = shadow_base_present_pte | shadow_dirty_mask;
1877 if (!speculative)
1878 spte |= shadow_accessed_mask;
1879 if (!dirty)
1880 pte_access &= ~ACC_WRITE_MASK;
1881 if (pte_access & ACC_EXEC_MASK)
1882 spte |= shadow_x_mask;
1883 else
1884 spte |= shadow_nx_mask;
1885 if (pte_access & ACC_USER_MASK)
1886 spte |= shadow_user_mask;
1887 if (level > PT_PAGE_TABLE_LEVEL)
1888 spte |= PT_PAGE_SIZE_MASK;
1889 if (tdp_enabled)
1890 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1891 kvm_is_mmio_pfn(pfn));
1892
1893 if (reset_host_protection)
1894 spte |= SPTE_HOST_WRITEABLE;
1895
1896 spte |= (u64)pfn << PAGE_SHIFT;
1897
1898 if ((pte_access & ACC_WRITE_MASK)
1899 || (!tdp_enabled && write_fault && !is_write_protection(vcpu)
1900 && !user_fault)) {
1901
1902 if (level > PT_PAGE_TABLE_LEVEL &&
1903 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1904 ret = 1;
1905 rmap_remove(vcpu->kvm, sptep);
1906 spte = shadow_trap_nonpresent_pte;
1907 goto set_pte;
1908 }
1909
1910 spte |= PT_WRITABLE_MASK;
1911
1912 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1913 spte &= ~PT_USER_MASK;
1914
1915 /*
1916 * Optimization: for pte sync, if spte was writable the hash
1917 * lookup is unnecessary (and expensive). Write protection
1918 * is responsibility of mmu_get_page / kvm_sync_page.
1919 * Same reasoning can be applied to dirty page accounting.
1920 */
1921 if (!can_unsync && is_writable_pte(*sptep))
1922 goto set_pte;
1923
1924 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1925 pgprintk("%s: found shadow page for %lx, marking ro\n",
1926 __func__, gfn);
1927 ret = 1;
1928 pte_access &= ~ACC_WRITE_MASK;
1929 if (is_writable_pte(spte))
1930 spte &= ~PT_WRITABLE_MASK;
1931 }
1932 }
1933
1934 if (pte_access & ACC_WRITE_MASK)
1935 mark_page_dirty(vcpu->kvm, gfn);
1936
1937 set_pte:
1938 __set_spte(sptep, spte);
1939 return ret;
1940 }
1941
1942 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1943 unsigned pt_access, unsigned pte_access,
1944 int user_fault, int write_fault, int dirty,
1945 int *ptwrite, int level, gfn_t gfn,
1946 pfn_t pfn, bool speculative,
1947 bool reset_host_protection)
1948 {
1949 int was_rmapped = 0;
1950 int was_writable = is_writable_pte(*sptep);
1951 int rmap_count;
1952
1953 pgprintk("%s: spte %llx access %x write_fault %d"
1954 " user_fault %d gfn %lx\n",
1955 __func__, *sptep, pt_access,
1956 write_fault, user_fault, gfn);
1957
1958 if (is_rmap_spte(*sptep)) {
1959 /*
1960 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1961 * the parent of the now unreachable PTE.
1962 */
1963 if (level > PT_PAGE_TABLE_LEVEL &&
1964 !is_large_pte(*sptep)) {
1965 struct kvm_mmu_page *child;
1966 u64 pte = *sptep;
1967
1968 child = page_header(pte & PT64_BASE_ADDR_MASK);
1969 mmu_page_remove_parent_pte(child, sptep);
1970 __set_spte(sptep, shadow_trap_nonpresent_pte);
1971 kvm_flush_remote_tlbs(vcpu->kvm);
1972 } else if (pfn != spte_to_pfn(*sptep)) {
1973 pgprintk("hfn old %lx new %lx\n",
1974 spte_to_pfn(*sptep), pfn);
1975 rmap_remove(vcpu->kvm, sptep);
1976 __set_spte(sptep, shadow_trap_nonpresent_pte);
1977 kvm_flush_remote_tlbs(vcpu->kvm);
1978 } else
1979 was_rmapped = 1;
1980 }
1981
1982 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1983 dirty, level, gfn, pfn, speculative, true,
1984 reset_host_protection)) {
1985 if (write_fault)
1986 *ptwrite = 1;
1987 kvm_mmu_flush_tlb(vcpu);
1988 }
1989
1990 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1991 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
1992 is_large_pte(*sptep)? "2MB" : "4kB",
1993 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1994 *sptep, sptep);
1995 if (!was_rmapped && is_large_pte(*sptep))
1996 ++vcpu->kvm->stat.lpages;
1997
1998 page_header_update_slot(vcpu->kvm, sptep, gfn);
1999 if (!was_rmapped) {
2000 rmap_count = rmap_add(vcpu, sptep, gfn);
2001 kvm_release_pfn_clean(pfn);
2002 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2003 rmap_recycle(vcpu, sptep, gfn);
2004 } else {
2005 if (was_writable)
2006 kvm_release_pfn_dirty(pfn);
2007 else
2008 kvm_release_pfn_clean(pfn);
2009 }
2010 if (speculative) {
2011 vcpu->arch.last_pte_updated = sptep;
2012 vcpu->arch.last_pte_gfn = gfn;
2013 }
2014 }
2015
2016 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2017 {
2018 }
2019
2020 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2021 int level, gfn_t gfn, pfn_t pfn)
2022 {
2023 struct kvm_shadow_walk_iterator iterator;
2024 struct kvm_mmu_page *sp;
2025 int pt_write = 0;
2026 gfn_t pseudo_gfn;
2027
2028 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2029 if (iterator.level == level) {
2030 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
2031 0, write, 1, &pt_write,
2032 level, gfn, pfn, false, true);
2033 ++vcpu->stat.pf_fixed;
2034 break;
2035 }
2036
2037 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
2038 u64 base_addr = iterator.addr;
2039
2040 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2041 pseudo_gfn = base_addr >> PAGE_SHIFT;
2042 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2043 iterator.level - 1,
2044 1, ACC_ALL, iterator.sptep);
2045 if (!sp) {
2046 pgprintk("nonpaging_map: ENOMEM\n");
2047 kvm_release_pfn_clean(pfn);
2048 return -ENOMEM;
2049 }
2050
2051 __set_spte(iterator.sptep,
2052 __pa(sp->spt)
2053 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2054 | shadow_user_mask | shadow_x_mask);
2055 }
2056 }
2057 return pt_write;
2058 }
2059
2060 static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
2061 {
2062 char buf[1];
2063 void __user *hva;
2064 int r;
2065
2066 /* Touch the page, so send SIGBUS */
2067 hva = (void __user *)gfn_to_hva(kvm, gfn);
2068 r = copy_from_user(buf, hva, 1);
2069 }
2070
2071 static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2072 {
2073 kvm_release_pfn_clean(pfn);
2074 if (is_hwpoison_pfn(pfn)) {
2075 kvm_send_hwpoison_signal(kvm, gfn);
2076 return 0;
2077 }
2078 return 1;
2079 }
2080
2081 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2082 {
2083 int r;
2084 int level;
2085 pfn_t pfn;
2086 unsigned long mmu_seq;
2087
2088 level = mapping_level(vcpu, gfn);
2089
2090 /*
2091 * This path builds a PAE pagetable - so we can map 2mb pages at
2092 * maximum. Therefore check if the level is larger than that.
2093 */
2094 if (level > PT_DIRECTORY_LEVEL)
2095 level = PT_DIRECTORY_LEVEL;
2096
2097 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2098
2099 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2100 smp_rmb();
2101 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2102
2103 /* mmio */
2104 if (is_error_pfn(pfn))
2105 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2106
2107 spin_lock(&vcpu->kvm->mmu_lock);
2108 if (mmu_notifier_retry(vcpu, mmu_seq))
2109 goto out_unlock;
2110 kvm_mmu_free_some_pages(vcpu);
2111 r = __direct_map(vcpu, v, write, level, gfn, pfn);
2112 spin_unlock(&vcpu->kvm->mmu_lock);
2113
2114
2115 return r;
2116
2117 out_unlock:
2118 spin_unlock(&vcpu->kvm->mmu_lock);
2119 kvm_release_pfn_clean(pfn);
2120 return 0;
2121 }
2122
2123
2124 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2125 {
2126 int i;
2127 struct kvm_mmu_page *sp;
2128 LIST_HEAD(invalid_list);
2129
2130 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2131 return;
2132 spin_lock(&vcpu->kvm->mmu_lock);
2133 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2134 hpa_t root = vcpu->arch.mmu.root_hpa;
2135
2136 sp = page_header(root);
2137 --sp->root_count;
2138 if (!sp->root_count && sp->role.invalid) {
2139 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2140 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2141 }
2142 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2143 spin_unlock(&vcpu->kvm->mmu_lock);
2144 return;
2145 }
2146 for (i = 0; i < 4; ++i) {
2147 hpa_t root = vcpu->arch.mmu.pae_root[i];
2148
2149 if (root) {
2150 root &= PT64_BASE_ADDR_MASK;
2151 sp = page_header(root);
2152 --sp->root_count;
2153 if (!sp->root_count && sp->role.invalid)
2154 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2155 &invalid_list);
2156 }
2157 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2158 }
2159 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2160 spin_unlock(&vcpu->kvm->mmu_lock);
2161 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2162 }
2163
2164 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2165 {
2166 int ret = 0;
2167
2168 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2169 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2170 ret = 1;
2171 }
2172
2173 return ret;
2174 }
2175
2176 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2177 {
2178 int i;
2179 gfn_t root_gfn;
2180 struct kvm_mmu_page *sp;
2181 int direct = 0;
2182 u64 pdptr;
2183
2184 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
2185
2186 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2187 hpa_t root = vcpu->arch.mmu.root_hpa;
2188
2189 ASSERT(!VALID_PAGE(root));
2190 if (mmu_check_root(vcpu, root_gfn))
2191 return 1;
2192 if (tdp_enabled) {
2193 direct = 1;
2194 root_gfn = 0;
2195 }
2196 spin_lock(&vcpu->kvm->mmu_lock);
2197 kvm_mmu_free_some_pages(vcpu);
2198 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
2199 PT64_ROOT_LEVEL, direct,
2200 ACC_ALL, NULL);
2201 root = __pa(sp->spt);
2202 ++sp->root_count;
2203 spin_unlock(&vcpu->kvm->mmu_lock);
2204 vcpu->arch.mmu.root_hpa = root;
2205 return 0;
2206 }
2207 direct = !is_paging(vcpu);
2208 for (i = 0; i < 4; ++i) {
2209 hpa_t root = vcpu->arch.mmu.pae_root[i];
2210
2211 ASSERT(!VALID_PAGE(root));
2212 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2213 pdptr = kvm_pdptr_read(vcpu, i);
2214 if (!is_present_gpte(pdptr)) {
2215 vcpu->arch.mmu.pae_root[i] = 0;
2216 continue;
2217 }
2218 root_gfn = pdptr >> PAGE_SHIFT;
2219 } else if (vcpu->arch.mmu.root_level == 0)
2220 root_gfn = 0;
2221 if (mmu_check_root(vcpu, root_gfn))
2222 return 1;
2223 if (tdp_enabled) {
2224 direct = 1;
2225 root_gfn = i << 30;
2226 }
2227 spin_lock(&vcpu->kvm->mmu_lock);
2228 kvm_mmu_free_some_pages(vcpu);
2229 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2230 PT32_ROOT_LEVEL, direct,
2231 ACC_ALL, NULL);
2232 root = __pa(sp->spt);
2233 ++sp->root_count;
2234 spin_unlock(&vcpu->kvm->mmu_lock);
2235
2236 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2237 }
2238 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2239 return 0;
2240 }
2241
2242 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2243 {
2244 int i;
2245 struct kvm_mmu_page *sp;
2246
2247 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2248 return;
2249 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2250 hpa_t root = vcpu->arch.mmu.root_hpa;
2251 sp = page_header(root);
2252 mmu_sync_children(vcpu, sp);
2253 return;
2254 }
2255 for (i = 0; i < 4; ++i) {
2256 hpa_t root = vcpu->arch.mmu.pae_root[i];
2257
2258 if (root && VALID_PAGE(root)) {
2259 root &= PT64_BASE_ADDR_MASK;
2260 sp = page_header(root);
2261 mmu_sync_children(vcpu, sp);
2262 }
2263 }
2264 }
2265
2266 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2267 {
2268 spin_lock(&vcpu->kvm->mmu_lock);
2269 mmu_sync_roots(vcpu);
2270 spin_unlock(&vcpu->kvm->mmu_lock);
2271 }
2272
2273 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2274 u32 access, u32 *error)
2275 {
2276 if (error)
2277 *error = 0;
2278 return vaddr;
2279 }
2280
2281 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2282 u32 error_code)
2283 {
2284 gfn_t gfn;
2285 int r;
2286
2287 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2288 r = mmu_topup_memory_caches(vcpu);
2289 if (r)
2290 return r;
2291
2292 ASSERT(vcpu);
2293 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2294
2295 gfn = gva >> PAGE_SHIFT;
2296
2297 return nonpaging_map(vcpu, gva & PAGE_MASK,
2298 error_code & PFERR_WRITE_MASK, gfn);
2299 }
2300
2301 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2302 u32 error_code)
2303 {
2304 pfn_t pfn;
2305 int r;
2306 int level;
2307 gfn_t gfn = gpa >> PAGE_SHIFT;
2308 unsigned long mmu_seq;
2309
2310 ASSERT(vcpu);
2311 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2312
2313 r = mmu_topup_memory_caches(vcpu);
2314 if (r)
2315 return r;
2316
2317 level = mapping_level(vcpu, gfn);
2318
2319 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2320
2321 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2322 smp_rmb();
2323 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2324 if (is_error_pfn(pfn))
2325 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2326 spin_lock(&vcpu->kvm->mmu_lock);
2327 if (mmu_notifier_retry(vcpu, mmu_seq))
2328 goto out_unlock;
2329 kvm_mmu_free_some_pages(vcpu);
2330 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
2331 level, gfn, pfn);
2332 spin_unlock(&vcpu->kvm->mmu_lock);
2333
2334 return r;
2335
2336 out_unlock:
2337 spin_unlock(&vcpu->kvm->mmu_lock);
2338 kvm_release_pfn_clean(pfn);
2339 return 0;
2340 }
2341
2342 static void nonpaging_free(struct kvm_vcpu *vcpu)
2343 {
2344 mmu_free_roots(vcpu);
2345 }
2346
2347 static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2348 {
2349 struct kvm_mmu *context = &vcpu->arch.mmu;
2350
2351 context->new_cr3 = nonpaging_new_cr3;
2352 context->page_fault = nonpaging_page_fault;
2353 context->gva_to_gpa = nonpaging_gva_to_gpa;
2354 context->free = nonpaging_free;
2355 context->prefetch_page = nonpaging_prefetch_page;
2356 context->sync_page = nonpaging_sync_page;
2357 context->invlpg = nonpaging_invlpg;
2358 context->root_level = 0;
2359 context->shadow_root_level = PT32E_ROOT_LEVEL;
2360 context->root_hpa = INVALID_PAGE;
2361 return 0;
2362 }
2363
2364 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2365 {
2366 ++vcpu->stat.tlb_flush;
2367 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
2368 }
2369
2370 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2371 {
2372 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
2373 mmu_free_roots(vcpu);
2374 }
2375
2376 static void inject_page_fault(struct kvm_vcpu *vcpu,
2377 u64 addr,
2378 u32 err_code)
2379 {
2380 kvm_inject_page_fault(vcpu, addr, err_code);
2381 }
2382
2383 static void paging_free(struct kvm_vcpu *vcpu)
2384 {
2385 nonpaging_free(vcpu);
2386 }
2387
2388 static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2389 {
2390 int bit7;
2391
2392 bit7 = (gpte >> 7) & 1;
2393 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2394 }
2395
2396 #define PTTYPE 64
2397 #include "paging_tmpl.h"
2398 #undef PTTYPE
2399
2400 #define PTTYPE 32
2401 #include "paging_tmpl.h"
2402 #undef PTTYPE
2403
2404 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2405 {
2406 struct kvm_mmu *context = &vcpu->arch.mmu;
2407 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2408 u64 exb_bit_rsvd = 0;
2409
2410 if (!is_nx(vcpu))
2411 exb_bit_rsvd = rsvd_bits(63, 63);
2412 switch (level) {
2413 case PT32_ROOT_LEVEL:
2414 /* no rsvd bits for 2 level 4K page table entries */
2415 context->rsvd_bits_mask[0][1] = 0;
2416 context->rsvd_bits_mask[0][0] = 0;
2417 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2418
2419 if (!is_pse(vcpu)) {
2420 context->rsvd_bits_mask[1][1] = 0;
2421 break;
2422 }
2423
2424 if (is_cpuid_PSE36())
2425 /* 36bits PSE 4MB page */
2426 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2427 else
2428 /* 32 bits PSE 4MB page */
2429 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2430 break;
2431 case PT32E_ROOT_LEVEL:
2432 context->rsvd_bits_mask[0][2] =
2433 rsvd_bits(maxphyaddr, 63) |
2434 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2435 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2436 rsvd_bits(maxphyaddr, 62); /* PDE */
2437 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2438 rsvd_bits(maxphyaddr, 62); /* PTE */
2439 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2440 rsvd_bits(maxphyaddr, 62) |
2441 rsvd_bits(13, 20); /* large page */
2442 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2443 break;
2444 case PT64_ROOT_LEVEL:
2445 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2446 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2447 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2448 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2449 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2450 rsvd_bits(maxphyaddr, 51);
2451 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2452 rsvd_bits(maxphyaddr, 51);
2453 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2454 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2455 rsvd_bits(maxphyaddr, 51) |
2456 rsvd_bits(13, 29);
2457 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2458 rsvd_bits(maxphyaddr, 51) |
2459 rsvd_bits(13, 20); /* large page */
2460 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2461 break;
2462 }
2463 }
2464
2465 static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
2466 {
2467 struct kvm_mmu *context = &vcpu->arch.mmu;
2468
2469 ASSERT(is_pae(vcpu));
2470 context->new_cr3 = paging_new_cr3;
2471 context->page_fault = paging64_page_fault;
2472 context->gva_to_gpa = paging64_gva_to_gpa;
2473 context->prefetch_page = paging64_prefetch_page;
2474 context->sync_page = paging64_sync_page;
2475 context->invlpg = paging64_invlpg;
2476 context->free = paging_free;
2477 context->root_level = level;
2478 context->shadow_root_level = level;
2479 context->root_hpa = INVALID_PAGE;
2480 return 0;
2481 }
2482
2483 static int paging64_init_context(struct kvm_vcpu *vcpu)
2484 {
2485 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2486 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2487 }
2488
2489 static int paging32_init_context(struct kvm_vcpu *vcpu)
2490 {
2491 struct kvm_mmu *context = &vcpu->arch.mmu;
2492
2493 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2494 context->new_cr3 = paging_new_cr3;
2495 context->page_fault = paging32_page_fault;
2496 context->gva_to_gpa = paging32_gva_to_gpa;
2497 context->free = paging_free;
2498 context->prefetch_page = paging32_prefetch_page;
2499 context->sync_page = paging32_sync_page;
2500 context->invlpg = paging32_invlpg;
2501 context->root_level = PT32_ROOT_LEVEL;
2502 context->shadow_root_level = PT32E_ROOT_LEVEL;
2503 context->root_hpa = INVALID_PAGE;
2504 return 0;
2505 }
2506
2507 static int paging32E_init_context(struct kvm_vcpu *vcpu)
2508 {
2509 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2510 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
2511 }
2512
2513 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2514 {
2515 struct kvm_mmu *context = &vcpu->arch.mmu;
2516
2517 context->new_cr3 = nonpaging_new_cr3;
2518 context->page_fault = tdp_page_fault;
2519 context->free = nonpaging_free;
2520 context->prefetch_page = nonpaging_prefetch_page;
2521 context->sync_page = nonpaging_sync_page;
2522 context->invlpg = nonpaging_invlpg;
2523 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2524 context->root_hpa = INVALID_PAGE;
2525
2526 if (!is_paging(vcpu)) {
2527 context->gva_to_gpa = nonpaging_gva_to_gpa;
2528 context->root_level = 0;
2529 } else if (is_long_mode(vcpu)) {
2530 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2531 context->gva_to_gpa = paging64_gva_to_gpa;
2532 context->root_level = PT64_ROOT_LEVEL;
2533 } else if (is_pae(vcpu)) {
2534 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2535 context->gva_to_gpa = paging64_gva_to_gpa;
2536 context->root_level = PT32E_ROOT_LEVEL;
2537 } else {
2538 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2539 context->gva_to_gpa = paging32_gva_to_gpa;
2540 context->root_level = PT32_ROOT_LEVEL;
2541 }
2542
2543 return 0;
2544 }
2545
2546 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2547 {
2548 int r;
2549
2550 ASSERT(vcpu);
2551 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2552
2553 if (!is_paging(vcpu))
2554 r = nonpaging_init_context(vcpu);
2555 else if (is_long_mode(vcpu))
2556 r = paging64_init_context(vcpu);
2557 else if (is_pae(vcpu))
2558 r = paging32E_init_context(vcpu);
2559 else
2560 r = paging32_init_context(vcpu);
2561
2562 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
2563 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2564
2565 return r;
2566 }
2567
2568 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2569 {
2570 vcpu->arch.update_pte.pfn = bad_pfn;
2571
2572 if (tdp_enabled)
2573 return init_kvm_tdp_mmu(vcpu);
2574 else
2575 return init_kvm_softmmu(vcpu);
2576 }
2577
2578 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2579 {
2580 ASSERT(vcpu);
2581 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2582 /* mmu.free() should set root_hpa = INVALID_PAGE */
2583 vcpu->arch.mmu.free(vcpu);
2584 }
2585
2586 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
2587 {
2588 destroy_kvm_mmu(vcpu);
2589 return init_kvm_mmu(vcpu);
2590 }
2591 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
2592
2593 int kvm_mmu_load(struct kvm_vcpu *vcpu)
2594 {
2595 int r;
2596
2597 r = mmu_topup_memory_caches(vcpu);
2598 if (r)
2599 goto out;
2600 r = mmu_alloc_roots(vcpu);
2601 spin_lock(&vcpu->kvm->mmu_lock);
2602 mmu_sync_roots(vcpu);
2603 spin_unlock(&vcpu->kvm->mmu_lock);
2604 if (r)
2605 goto out;
2606 /* set_cr3() should ensure TLB has been flushed */
2607 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
2608 out:
2609 return r;
2610 }
2611 EXPORT_SYMBOL_GPL(kvm_mmu_load);
2612
2613 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2614 {
2615 mmu_free_roots(vcpu);
2616 }
2617
2618 static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
2619 struct kvm_mmu_page *sp,
2620 u64 *spte)
2621 {
2622 u64 pte;
2623 struct kvm_mmu_page *child;
2624
2625 pte = *spte;
2626 if (is_shadow_present_pte(pte)) {
2627 if (is_last_spte(pte, sp->role.level))
2628 rmap_remove(vcpu->kvm, spte);
2629 else {
2630 child = page_header(pte & PT64_BASE_ADDR_MASK);
2631 mmu_page_remove_parent_pte(child, spte);
2632 }
2633 }
2634 __set_spte(spte, shadow_trap_nonpresent_pte);
2635 if (is_large_pte(pte))
2636 --vcpu->kvm->stat.lpages;
2637 }
2638
2639 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
2640 struct kvm_mmu_page *sp,
2641 u64 *spte,
2642 const void *new)
2643 {
2644 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
2645 ++vcpu->kvm->stat.mmu_pde_zapped;
2646 return;
2647 }
2648
2649 ++vcpu->kvm->stat.mmu_pte_updated;
2650 if (!sp->role.cr4_pae)
2651 paging32_update_pte(vcpu, sp, spte, new);
2652 else
2653 paging64_update_pte(vcpu, sp, spte, new);
2654 }
2655
2656 static bool need_remote_flush(u64 old, u64 new)
2657 {
2658 if (!is_shadow_present_pte(old))
2659 return false;
2660 if (!is_shadow_present_pte(new))
2661 return true;
2662 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2663 return true;
2664 old ^= PT64_NX_MASK;
2665 new ^= PT64_NX_MASK;
2666 return (old & ~new & PT64_PERM_MASK) != 0;
2667 }
2668
2669 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
2670 bool remote_flush, bool local_flush)
2671 {
2672 if (zap_page)
2673 return;
2674
2675 if (remote_flush)
2676 kvm_flush_remote_tlbs(vcpu->kvm);
2677 else if (local_flush)
2678 kvm_mmu_flush_tlb(vcpu);
2679 }
2680
2681 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2682 {
2683 u64 *spte = vcpu->arch.last_pte_updated;
2684
2685 return !!(spte && (*spte & shadow_accessed_mask));
2686 }
2687
2688 static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2689 u64 gpte)
2690 {
2691 gfn_t gfn;
2692 pfn_t pfn;
2693
2694 if (!is_present_gpte(gpte))
2695 return;
2696 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
2697
2698 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
2699 smp_rmb();
2700 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2701
2702 if (is_error_pfn(pfn)) {
2703 kvm_release_pfn_clean(pfn);
2704 return;
2705 }
2706 vcpu->arch.update_pte.gfn = gfn;
2707 vcpu->arch.update_pte.pfn = pfn;
2708 }
2709
2710 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2711 {
2712 u64 *spte = vcpu->arch.last_pte_updated;
2713
2714 if (spte
2715 && vcpu->arch.last_pte_gfn == gfn
2716 && shadow_accessed_mask
2717 && !(*spte & shadow_accessed_mask)
2718 && is_shadow_present_pte(*spte))
2719 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2720 }
2721
2722 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2723 const u8 *new, int bytes,
2724 bool guest_initiated)
2725 {
2726 gfn_t gfn = gpa >> PAGE_SHIFT;
2727 struct kvm_mmu_page *sp;
2728 struct hlist_node *node;
2729 LIST_HEAD(invalid_list);
2730 u64 entry, gentry;
2731 u64 *spte;
2732 unsigned offset = offset_in_page(gpa);
2733 unsigned pte_size;
2734 unsigned page_offset;
2735 unsigned misaligned;
2736 unsigned quadrant;
2737 int level;
2738 int flooded = 0;
2739 int npte;
2740 int r;
2741 int invlpg_counter;
2742 bool remote_flush, local_flush, zap_page;
2743
2744 zap_page = remote_flush = local_flush = false;
2745
2746 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
2747
2748 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
2749
2750 /*
2751 * Assume that the pte write on a page table of the same type
2752 * as the current vcpu paging mode. This is nearly always true
2753 * (might be false while changing modes). Note it is verified later
2754 * by update_pte().
2755 */
2756 if ((is_pae(vcpu) && bytes == 4) || !new) {
2757 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2758 if (is_pae(vcpu)) {
2759 gpa &= ~(gpa_t)7;
2760 bytes = 8;
2761 }
2762 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
2763 if (r)
2764 gentry = 0;
2765 new = (const u8 *)&gentry;
2766 }
2767
2768 switch (bytes) {
2769 case 4:
2770 gentry = *(const u32 *)new;
2771 break;
2772 case 8:
2773 gentry = *(const u64 *)new;
2774 break;
2775 default:
2776 gentry = 0;
2777 break;
2778 }
2779
2780 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
2781 spin_lock(&vcpu->kvm->mmu_lock);
2782 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2783 gentry = 0;
2784 kvm_mmu_access_page(vcpu, gfn);
2785 kvm_mmu_free_some_pages(vcpu);
2786 ++vcpu->kvm->stat.mmu_pte_write;
2787 kvm_mmu_audit(vcpu, "pre pte write");
2788 if (guest_initiated) {
2789 if (gfn == vcpu->arch.last_pt_write_gfn
2790 && !last_updated_pte_accessed(vcpu)) {
2791 ++vcpu->arch.last_pt_write_count;
2792 if (vcpu->arch.last_pt_write_count >= 3)
2793 flooded = 1;
2794 } else {
2795 vcpu->arch.last_pt_write_gfn = gfn;
2796 vcpu->arch.last_pt_write_count = 1;
2797 vcpu->arch.last_pte_updated = NULL;
2798 }
2799 }
2800
2801 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
2802 pte_size = sp->role.cr4_pae ? 8 : 4;
2803 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
2804 misaligned |= bytes < 4;
2805 if (misaligned || flooded) {
2806 /*
2807 * Misaligned accesses are too much trouble to fix
2808 * up; also, they usually indicate a page is not used
2809 * as a page table.
2810 *
2811 * If we're seeing too many writes to a page,
2812 * it may no longer be a page table, or we may be
2813 * forking, in which case it is better to unmap the
2814 * page.
2815 */
2816 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
2817 gpa, bytes, sp->role.word);
2818 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2819 &invalid_list);
2820 ++vcpu->kvm->stat.mmu_flooded;
2821 continue;
2822 }
2823 page_offset = offset;
2824 level = sp->role.level;
2825 npte = 1;
2826 if (!sp->role.cr4_pae) {
2827 page_offset <<= 1; /* 32->64 */
2828 /*
2829 * A 32-bit pde maps 4MB while the shadow pdes map
2830 * only 2MB. So we need to double the offset again
2831 * and zap two pdes instead of one.
2832 */
2833 if (level == PT32_ROOT_LEVEL) {
2834 page_offset &= ~7; /* kill rounding error */
2835 page_offset <<= 1;
2836 npte = 2;
2837 }
2838 quadrant = page_offset >> PAGE_SHIFT;
2839 page_offset &= ~PAGE_MASK;
2840 if (quadrant != sp->role.quadrant)
2841 continue;
2842 }
2843 local_flush = true;
2844 spte = &sp->spt[page_offset / sizeof(*spte)];
2845 while (npte--) {
2846 entry = *spte;
2847 mmu_pte_write_zap_pte(vcpu, sp, spte);
2848 if (gentry)
2849 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
2850 if (!remote_flush && need_remote_flush(entry, *spte))
2851 remote_flush = true;
2852 ++spte;
2853 }
2854 }
2855 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
2856 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2857 kvm_mmu_audit(vcpu, "post pte write");
2858 spin_unlock(&vcpu->kvm->mmu_lock);
2859 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2860 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2861 vcpu->arch.update_pte.pfn = bad_pfn;
2862 }
2863 }
2864
2865 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2866 {
2867 gpa_t gpa;
2868 int r;
2869
2870 if (tdp_enabled)
2871 return 0;
2872
2873 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2874
2875 spin_lock(&vcpu->kvm->mmu_lock);
2876 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2877 spin_unlock(&vcpu->kvm->mmu_lock);
2878 return r;
2879 }
2880 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
2881
2882 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
2883 {
2884 int free_pages;
2885 LIST_HEAD(invalid_list);
2886
2887 free_pages = vcpu->kvm->arch.n_free_mmu_pages;
2888 while (free_pages < KVM_REFILL_PAGES &&
2889 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
2890 struct kvm_mmu_page *sp;
2891
2892 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
2893 struct kvm_mmu_page, link);
2894 free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2895 &invalid_list);
2896 ++vcpu->kvm->stat.mmu_recycled;
2897 }
2898 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2899 }
2900
2901 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2902 {
2903 int r;
2904 enum emulation_result er;
2905
2906 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
2907 if (r < 0)
2908 goto out;
2909
2910 if (!r) {
2911 r = 1;
2912 goto out;
2913 }
2914
2915 r = mmu_topup_memory_caches(vcpu);
2916 if (r)
2917 goto out;
2918
2919 er = emulate_instruction(vcpu, cr2, error_code, 0);
2920
2921 switch (er) {
2922 case EMULATE_DONE:
2923 return 1;
2924 case EMULATE_DO_MMIO:
2925 ++vcpu->stat.mmio_exits;
2926 /* fall through */
2927 case EMULATE_FAIL:
2928 return 0;
2929 default:
2930 BUG();
2931 }
2932 out:
2933 return r;
2934 }
2935 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2936
2937 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2938 {
2939 vcpu->arch.mmu.invlpg(vcpu, gva);
2940 kvm_mmu_flush_tlb(vcpu);
2941 ++vcpu->stat.invlpg;
2942 }
2943 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2944
2945 void kvm_enable_tdp(void)
2946 {
2947 tdp_enabled = true;
2948 }
2949 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2950
2951 void kvm_disable_tdp(void)
2952 {
2953 tdp_enabled = false;
2954 }
2955 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2956
2957 static void free_mmu_pages(struct kvm_vcpu *vcpu)
2958 {
2959 free_page((unsigned long)vcpu->arch.mmu.pae_root);
2960 }
2961
2962 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2963 {
2964 struct page *page;
2965 int i;
2966
2967 ASSERT(vcpu);
2968
2969 /*
2970 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2971 * Therefore we need to allocate shadow page tables in the first
2972 * 4GB of memory, which happens to fit the DMA32 zone.
2973 */
2974 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2975 if (!page)
2976 return -ENOMEM;
2977
2978 vcpu->arch.mmu.pae_root = page_address(page);
2979 for (i = 0; i < 4; ++i)
2980 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2981
2982 return 0;
2983 }
2984
2985 int kvm_mmu_create(struct kvm_vcpu *vcpu)
2986 {
2987 ASSERT(vcpu);
2988 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2989
2990 return alloc_mmu_pages(vcpu);
2991 }
2992
2993 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2994 {
2995 ASSERT(vcpu);
2996 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2997
2998 return init_kvm_mmu(vcpu);
2999 }
3000
3001 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3002 {
3003 ASSERT(vcpu);
3004
3005 destroy_kvm_mmu(vcpu);
3006 free_mmu_pages(vcpu);
3007 mmu_free_memory_caches(vcpu);
3008 }
3009
3010 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3011 {
3012 struct kvm_mmu_page *sp;
3013
3014 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3015 int i;
3016 u64 *pt;
3017
3018 if (!test_bit(slot, sp->slot_bitmap))
3019 continue;
3020
3021 pt = sp->spt;
3022 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
3023 /* avoid RMW */
3024 if (is_writable_pte(pt[i]))
3025 pt[i] &= ~PT_WRITABLE_MASK;
3026 }
3027 kvm_flush_remote_tlbs(kvm);
3028 }
3029
3030 void kvm_mmu_zap_all(struct kvm *kvm)
3031 {
3032 struct kvm_mmu_page *sp, *node;
3033 LIST_HEAD(invalid_list);
3034
3035 spin_lock(&kvm->mmu_lock);
3036 restart:
3037 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3038 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3039 goto restart;
3040
3041 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3042 spin_unlock(&kvm->mmu_lock);
3043 }
3044
3045 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3046 struct list_head *invalid_list)
3047 {
3048 struct kvm_mmu_page *page;
3049
3050 page = container_of(kvm->arch.active_mmu_pages.prev,
3051 struct kvm_mmu_page, link);
3052 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3053 }
3054
3055 static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3056 {
3057 struct kvm *kvm;
3058 struct kvm *kvm_freed = NULL;
3059 int cache_count = 0;
3060
3061 spin_lock(&kvm_lock);
3062
3063 list_for_each_entry(kvm, &vm_list, vm_list) {
3064 int npages, idx, freed_pages;
3065 LIST_HEAD(invalid_list);
3066
3067 idx = srcu_read_lock(&kvm->srcu);
3068 spin_lock(&kvm->mmu_lock);
3069 npages = kvm->arch.n_alloc_mmu_pages -
3070 kvm->arch.n_free_mmu_pages;
3071 cache_count += npages;
3072 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
3073 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3074 &invalid_list);
3075 cache_count -= freed_pages;
3076 kvm_freed = kvm;
3077 }
3078 nr_to_scan--;
3079
3080 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3081 spin_unlock(&kvm->mmu_lock);
3082 srcu_read_unlock(&kvm->srcu, idx);
3083 }
3084 if (kvm_freed)
3085 list_move_tail(&kvm_freed->vm_list, &vm_list);
3086
3087 spin_unlock(&kvm_lock);
3088
3089 return cache_count;
3090 }
3091
3092 static struct shrinker mmu_shrinker = {
3093 .shrink = mmu_shrink,
3094 .seeks = DEFAULT_SEEKS * 10,
3095 };
3096
3097 static void mmu_destroy_caches(void)
3098 {
3099 if (pte_chain_cache)
3100 kmem_cache_destroy(pte_chain_cache);
3101 if (rmap_desc_cache)
3102 kmem_cache_destroy(rmap_desc_cache);
3103 if (mmu_page_header_cache)
3104 kmem_cache_destroy(mmu_page_header_cache);
3105 }
3106
3107 void kvm_mmu_module_exit(void)
3108 {
3109 mmu_destroy_caches();
3110 unregister_shrinker(&mmu_shrinker);
3111 }
3112
3113 int kvm_mmu_module_init(void)
3114 {
3115 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3116 sizeof(struct kvm_pte_chain),
3117 0, 0, NULL);
3118 if (!pte_chain_cache)
3119 goto nomem;
3120 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3121 sizeof(struct kvm_rmap_desc),
3122 0, 0, NULL);
3123 if (!rmap_desc_cache)
3124 goto nomem;
3125
3126 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3127 sizeof(struct kvm_mmu_page),
3128 0, 0, NULL);
3129 if (!mmu_page_header_cache)
3130 goto nomem;
3131
3132 register_shrinker(&mmu_shrinker);
3133
3134 return 0;
3135
3136 nomem:
3137 mmu_destroy_caches();
3138 return -ENOMEM;
3139 }
3140
3141 /*
3142 * Caculate mmu pages needed for kvm.
3143 */
3144 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3145 {
3146 int i;
3147 unsigned int nr_mmu_pages;
3148 unsigned int nr_pages = 0;
3149 struct kvm_memslots *slots;
3150
3151 slots = kvm_memslots(kvm);
3152
3153 for (i = 0; i < slots->nmemslots; i++)
3154 nr_pages += slots->memslots[i].npages;
3155
3156 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3157 nr_mmu_pages = max(nr_mmu_pages,
3158 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3159
3160 return nr_mmu_pages;
3161 }
3162
3163 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3164 unsigned len)
3165 {
3166 if (len > buffer->len)
3167 return NULL;
3168 return buffer->ptr;
3169 }
3170
3171 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3172 unsigned len)
3173 {
3174 void *ret;
3175
3176 ret = pv_mmu_peek_buffer(buffer, len);
3177 if (!ret)
3178 return ret;
3179 buffer->ptr += len;
3180 buffer->len -= len;
3181 buffer->processed += len;
3182 return ret;
3183 }
3184
3185 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3186 gpa_t addr, gpa_t value)
3187 {
3188 int bytes = 8;
3189 int r;
3190
3191 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3192 bytes = 4;
3193
3194 r = mmu_topup_memory_caches(vcpu);
3195 if (r)
3196 return r;
3197
3198 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3199 return -EFAULT;
3200
3201 return 1;
3202 }
3203
3204 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3205 {
3206 (void)kvm_set_cr3(vcpu, vcpu->arch.cr3);
3207 return 1;
3208 }
3209
3210 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3211 {
3212 spin_lock(&vcpu->kvm->mmu_lock);
3213 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3214 spin_unlock(&vcpu->kvm->mmu_lock);
3215 return 1;
3216 }
3217
3218 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3219 struct kvm_pv_mmu_op_buffer *buffer)
3220 {
3221 struct kvm_mmu_op_header *header;
3222
3223 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3224 if (!header)
3225 return 0;
3226 switch (header->op) {
3227 case KVM_MMU_OP_WRITE_PTE: {
3228 struct kvm_mmu_op_write_pte *wpte;
3229
3230 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3231 if (!wpte)
3232 return 0;
3233 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3234 wpte->pte_val);
3235 }
3236 case KVM_MMU_OP_FLUSH_TLB: {
3237 struct kvm_mmu_op_flush_tlb *ftlb;
3238
3239 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3240 if (!ftlb)
3241 return 0;
3242 return kvm_pv_mmu_flush_tlb(vcpu);
3243 }
3244 case KVM_MMU_OP_RELEASE_PT: {
3245 struct kvm_mmu_op_release_pt *rpt;
3246
3247 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3248 if (!rpt)
3249 return 0;
3250 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3251 }
3252 default: return 0;
3253 }
3254 }
3255
3256 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3257 gpa_t addr, unsigned long *ret)
3258 {
3259 int r;
3260 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3261
3262 buffer->ptr = buffer->buf;
3263 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3264 buffer->processed = 0;
3265
3266 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3267 if (r)
3268 goto out;
3269
3270 while (buffer->len) {
3271 r = kvm_pv_mmu_op_one(vcpu, buffer);
3272 if (r < 0)
3273 goto out;
3274 if (r == 0)
3275 break;
3276 }
3277
3278 r = 1;
3279 out:
3280 *ret = buffer->processed;
3281 return r;
3282 }
3283
3284 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3285 {
3286 struct kvm_shadow_walk_iterator iterator;
3287 int nr_sptes = 0;
3288
3289 spin_lock(&vcpu->kvm->mmu_lock);
3290 for_each_shadow_entry(vcpu, addr, iterator) {
3291 sptes[iterator.level-1] = *iterator.sptep;
3292 nr_sptes++;
3293 if (!is_shadow_present_pte(*iterator.sptep))
3294 break;
3295 }
3296 spin_unlock(&vcpu->kvm->mmu_lock);
3297
3298 return nr_sptes;
3299 }
3300 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3301
3302 #ifdef AUDIT
3303
3304 static const char *audit_msg;
3305
3306 static gva_t canonicalize(gva_t gva)
3307 {
3308 #ifdef CONFIG_X86_64
3309 gva = (long long)(gva << 16) >> 16;
3310 #endif
3311 return gva;
3312 }
3313
3314
3315 typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
3316
3317 static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3318 inspect_spte_fn fn)
3319 {
3320 int i;
3321
3322 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3323 u64 ent = sp->spt[i];
3324
3325 if (is_shadow_present_pte(ent)) {
3326 if (!is_last_spte(ent, sp->role.level)) {
3327 struct kvm_mmu_page *child;
3328 child = page_header(ent & PT64_BASE_ADDR_MASK);
3329 __mmu_spte_walk(kvm, child, fn);
3330 } else
3331 fn(kvm, &sp->spt[i]);
3332 }
3333 }
3334 }
3335
3336 static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3337 {
3338 int i;
3339 struct kvm_mmu_page *sp;
3340
3341 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3342 return;
3343 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3344 hpa_t root = vcpu->arch.mmu.root_hpa;
3345 sp = page_header(root);
3346 __mmu_spte_walk(vcpu->kvm, sp, fn);
3347 return;
3348 }
3349 for (i = 0; i < 4; ++i) {
3350 hpa_t root = vcpu->arch.mmu.pae_root[i];
3351
3352 if (root && VALID_PAGE(root)) {
3353 root &= PT64_BASE_ADDR_MASK;
3354 sp = page_header(root);
3355 __mmu_spte_walk(vcpu->kvm, sp, fn);
3356 }
3357 }
3358 return;
3359 }
3360
3361 static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3362 gva_t va, int level)
3363 {
3364 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3365 int i;
3366 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3367
3368 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3369 u64 ent = pt[i];
3370
3371 if (ent == shadow_trap_nonpresent_pte)
3372 continue;
3373
3374 va = canonicalize(va);
3375 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3376 audit_mappings_page(vcpu, ent, va, level - 1);
3377 else {
3378 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
3379 gfn_t gfn = gpa >> PAGE_SHIFT;
3380 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3381 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
3382
3383 if (is_error_pfn(pfn)) {
3384 kvm_release_pfn_clean(pfn);
3385 continue;
3386 }
3387
3388 if (is_shadow_present_pte(ent)
3389 && (ent & PT64_BASE_ADDR_MASK) != hpa)
3390 printk(KERN_ERR "xx audit error: (%s) levels %d"
3391 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
3392 audit_msg, vcpu->arch.mmu.root_level,
3393 va, gpa, hpa, ent,
3394 is_shadow_present_pte(ent));
3395 else if (ent == shadow_notrap_nonpresent_pte
3396 && !is_error_hpa(hpa))
3397 printk(KERN_ERR "audit: (%s) notrap shadow,"
3398 " valid guest gva %lx\n", audit_msg, va);
3399 kvm_release_pfn_clean(pfn);
3400
3401 }
3402 }
3403 }
3404
3405 static void audit_mappings(struct kvm_vcpu *vcpu)
3406 {
3407 unsigned i;
3408
3409 if (vcpu->arch.mmu.root_level == 4)
3410 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
3411 else
3412 for (i = 0; i < 4; ++i)
3413 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
3414 audit_mappings_page(vcpu,
3415 vcpu->arch.mmu.pae_root[i],
3416 i << 30,
3417 2);
3418 }
3419
3420 static int count_rmaps(struct kvm_vcpu *vcpu)
3421 {
3422 struct kvm *kvm = vcpu->kvm;
3423 struct kvm_memslots *slots;
3424 int nmaps = 0;
3425 int i, j, k, idx;
3426
3427 idx = srcu_read_lock(&kvm->srcu);
3428 slots = kvm_memslots(kvm);
3429 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3430 struct kvm_memory_slot *m = &slots->memslots[i];
3431 struct kvm_rmap_desc *d;
3432
3433 for (j = 0; j < m->npages; ++j) {
3434 unsigned long *rmapp = &m->rmap[j];
3435
3436 if (!*rmapp)
3437 continue;
3438 if (!(*rmapp & 1)) {
3439 ++nmaps;
3440 continue;
3441 }
3442 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
3443 while (d) {
3444 for (k = 0; k < RMAP_EXT; ++k)
3445 if (d->sptes[k])
3446 ++nmaps;
3447 else
3448 break;
3449 d = d->more;
3450 }
3451 }
3452 }
3453 srcu_read_unlock(&kvm->srcu, idx);
3454 return nmaps;
3455 }
3456
3457 void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
3458 {
3459 unsigned long *rmapp;
3460 struct kvm_mmu_page *rev_sp;
3461 gfn_t gfn;
3462
3463 if (is_writable_pte(*sptep)) {
3464 rev_sp = page_header(__pa(sptep));
3465 gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt);
3466
3467 if (!gfn_to_memslot(kvm, gfn)) {
3468 if (!printk_ratelimit())
3469 return;
3470 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3471 audit_msg, gfn);
3472 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3473 audit_msg, (long int)(sptep - rev_sp->spt),
3474 rev_sp->gfn);
3475 dump_stack();
3476 return;
3477 }
3478
3479 rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level);
3480 if (!*rmapp) {
3481 if (!printk_ratelimit())
3482 return;
3483 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3484 audit_msg, *sptep);
3485 dump_stack();
3486 }
3487 }
3488
3489 }
3490
3491 void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3492 {
3493 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3494 }
3495
3496 static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
3497 {
3498 struct kvm_mmu_page *sp;
3499 int i;
3500
3501 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3502 u64 *pt = sp->spt;
3503
3504 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
3505 continue;
3506
3507 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3508 u64 ent = pt[i];
3509
3510 if (!(ent & PT_PRESENT_MASK))
3511 continue;
3512 if (!is_writable_pte(ent))
3513 continue;
3514 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
3515 }
3516 }
3517 return;
3518 }
3519
3520 static void audit_rmap(struct kvm_vcpu *vcpu)
3521 {
3522 check_writable_mappings_rmap(vcpu);
3523 count_rmaps(vcpu);
3524 }
3525
3526 static void audit_write_protection(struct kvm_vcpu *vcpu)
3527 {
3528 struct kvm_mmu_page *sp;
3529 struct kvm_memory_slot *slot;
3530 unsigned long *rmapp;
3531 u64 *spte;
3532 gfn_t gfn;
3533
3534 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3535 if (sp->role.direct)
3536 continue;
3537 if (sp->unsync)
3538 continue;
3539
3540 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
3541 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
3542 rmapp = &slot->rmap[gfn - slot->base_gfn];
3543
3544 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3545 while (spte) {
3546 if (is_writable_pte(*spte))
3547 printk(KERN_ERR "%s: (%s) shadow page has "
3548 "writable mappings: gfn %lx role %x\n",
3549 __func__, audit_msg, sp->gfn,
3550 sp->role.word);
3551 spte = rmap_next(vcpu->kvm, rmapp, spte);
3552 }
3553 }
3554 }
3555
3556 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3557 {
3558 int olddbg = dbg;
3559
3560 dbg = 0;
3561 audit_msg = msg;
3562 audit_rmap(vcpu);
3563 audit_write_protection(vcpu);
3564 if (strcmp("pre pte write", audit_msg) != 0)
3565 audit_mappings(vcpu);
3566 audit_writable_sptes_have_rmaps(vcpu);
3567 dbg = olddbg;
3568 }
3569
3570 #endif
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