arch/x86/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  31         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  32         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  33         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  34         #ifdef CONFIG_X86_64
  35         #define PT_MAX_FULL_LEVELS 4
  36         #define CMPXCHG cmpxchg
  37         #else
  38         #define CMPXCHG cmpxchg64
  39         #define PT_MAX_FULL_LEVELS 2
  40         #endif
  41 #elif PTTYPE == 32
  42         #define pt_element_t u32
  43         #define guest_walker guest_walker32
  44         #define FNAME(name) paging##32_##name
  45         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  46         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  47         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  48         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  49         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  50         #define PT_MAX_FULL_LEVELS 2
  51         #define CMPXCHG cmpxchg
  52 #else
  53         #error Invalid PTTYPE value
  54 #endif
  55
  56 #define gpte_to_gfn FNAME(gpte_to_gfn)
  57 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
  58
  59 /*
  60  * The guest_walker structure emulates the behavior of the hardware page
  61  * table walker.
  62  */
  63 struct guest_walker {
  64         int level;
  65         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  66         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  67         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  68         unsigned pt_access;
  69         unsigned pte_access;
  70         gfn_t gfn;
  71         u32 error_code;
  72 };
  73
  74 static gfn_t gpte_to_gfn(pt_element_t gpte)
  75 {
  76         return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
  77 }
  78
  79 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
  80 {
  81         return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
  82 }
  83
  84 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
  85                          gfn_t table_gfn, unsigned index,
  86                          pt_element_t orig_pte, pt_element_t new_pte)
  87 {
  88         pt_element_t ret;
  89         pt_element_t *table;
  90         struct page *page;
  91
  92         page = gfn_to_page(kvm, table_gfn);
  93
  94         table = kmap_atomic(page, KM_USER0);
  95         ret = CMPXCHG(&table[index], orig_pte, new_pte);
  96         kunmap_atomic(table, KM_USER0);
  97
  98         kvm_release_page_dirty(page);
  99
 100         return (ret != orig_pte);
 101 }
 102
 103 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
 104 {
 105         unsigned access;
 106
 107         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
 108 #if PTTYPE == 64
 109         if (is_nx(vcpu))
 110                 access &= ~(gpte >> PT64_NX_SHIFT);
 111 #endif
 112         return access;
 113 }
 114
 115 /*
 116  * Fetch a guest pte for a guest virtual address
 117  */
 118 static int FNAME(walk_addr)(struct guest_walker *walker,
 119                             struct kvm_vcpu *vcpu, gva_t addr,
 120                             int write_fault, int user_fault, int fetch_fault)
 121 {
 122         pt_element_t pte;
 123         gfn_t table_gfn;
 124         unsigned index, pt_access, pte_access;
 125         gpa_t pte_gpa;
 126         int rsvd_fault = 0;
 127
 128         pgprintk("%s: addr %lx\n", __func__, addr);
 129 walk:
 130         walker->level = vcpu->arch.mmu.root_level;
 131         pte = vcpu->arch.cr3;
 132 #if PTTYPE == 64
 133         if (!is_long_mode(vcpu)) {
 134                 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
 135                 if (!is_present_gpte(pte))
 136                         goto not_present;
 137                 --walker->level;
 138         }
 139 #endif
 140         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 141                (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
 142
 143         pt_access = ACC_ALL;
 144
 145         for (;;) {
 146                 index = PT_INDEX(addr, walker->level);
 147
 148                 table_gfn = gpte_to_gfn(pte);
 149                 pte_gpa = gfn_to_gpa(table_gfn);
 150                 pte_gpa += index * sizeof(pt_element_t);
 151                 walker->table_gfn[walker->level - 1] = table_gfn;
 152                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 153                 pgprintk("%s: table_gfn[%d] %lx\n", __func__,
 154                          walker->level - 1, table_gfn);
 155
 156                 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 157
 158                 if (!is_present_gpte(pte))
 159                         goto not_present;
 160
 161                 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
 162                 if (rsvd_fault)
 163                         goto access_error;
 164
 165                 if (write_fault && !is_writeble_pte(pte))
 166                         if (user_fault || is_write_protection(vcpu))
 167                                 goto access_error;
 168
 169                 if (user_fault && !(pte & PT_USER_MASK))
 170                         goto access_error;
 171
 172 #if PTTYPE == 64
 173                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 174                         goto access_error;
 175 #endif
 176
 177                 if (!(pte & PT_ACCESSED_MASK)) {
 178                         mark_page_dirty(vcpu->kvm, table_gfn);
 179                         if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
 180                             index, pte, pte|PT_ACCESSED_MASK))
 181                                 goto walk;
 182                         pte |= PT_ACCESSED_MASK;
 183                 }
 184
 185                 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
 186
 187                 walker->ptes[walker->level - 1] = pte;
 188
 189                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 190                         walker->gfn = gpte_to_gfn(pte);
 191                         break;
 192                 }
 193
 194                 if (walker->level == PT_DIRECTORY_LEVEL
 195                     && (pte & PT_PAGE_SIZE_MASK)
 196                     && (PTTYPE == 64 || is_pse(vcpu))) {
 197                         walker->gfn = gpte_to_gfn_pde(pte);
 198                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 199                         if (PTTYPE == 32 && is_cpuid_PSE36())
 200                                 walker->gfn += pse36_gfn_delta(pte);
 201                         break;
 202                 }
 203
 204                 pt_access = pte_access;
 205                 --walker->level;
 206         }
 207
 208         if (write_fault && !is_dirty_gpte(pte)) {
 209                 bool ret;
 210
 211                 mark_page_dirty(vcpu->kvm, table_gfn);
 212                 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
 213                             pte|PT_DIRTY_MASK);
 214                 if (ret)
 215                         goto walk;
 216                 pte |= PT_DIRTY_MASK;
 217                 walker->ptes[walker->level - 1] = pte;
 218         }
 219
 220         walker->pt_access = pt_access;
 221         walker->pte_access = pte_access;
 222         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 223                  __func__, (u64)pte, pt_access, pte_access);
 224         return 1;
 225
 226 not_present:
 227         walker->error_code = 0;
 228         goto err;
 229
 230 access_error:
 231         walker->error_code = PFERR_PRESENT_MASK;
 232
 233 err:
 234         if (write_fault)
 235                 walker->error_code |= PFERR_WRITE_MASK;
 236         if (user_fault)
 237                 walker->error_code |= PFERR_USER_MASK;
 238         if (fetch_fault)
 239                 walker->error_code |= PFERR_FETCH_MASK;
 240         if (rsvd_fault)
 241                 walker->error_code |= PFERR_RSVD_MASK;
 242         return 0;
 243 }
 244
 245 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 246                               u64 *spte, const void *pte)
 247 {
 248         pt_element_t gpte;
 249         unsigned pte_access;
 250         pfn_t pfn;
 251         int largepage = vcpu->arch.update_pte.largepage;
 252
 253         gpte = *(const pt_element_t *)pte;
 254         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 255                 if (!is_present_gpte(gpte))
 256                         __set_spte(spte, shadow_notrap_nonpresent_pte);
 257                 return;
 258         }
 259         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 260         pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
 261         if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
 262                 return;
 263         pfn = vcpu->arch.update_pte.pfn;
 264         if (is_error_pfn(pfn))
 265                 return;
 266         if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
 267                 return;
 268         kvm_get_pfn(pfn);
 269         mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
 270                      gpte & PT_DIRTY_MASK, NULL, largepage,
 271                      gpte_to_gfn(gpte), pfn, true);
 272 }
 273
 274 /*
 275  * Fetch a shadow pte for a specific level in the paging hierarchy.
 276  */
 277 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 278                          struct guest_walker *gw,
 279                          int user_fault, int write_fault, int largepage,
 280                          int *ptwrite, pfn_t pfn)
 281 {
 282         unsigned access = gw->pt_access;
 283         struct kvm_mmu_page *shadow_page;
 284         u64 spte, *sptep = NULL;
 285         int direct;
 286         gfn_t table_gfn;
 287         int r;
 288         int level;
 289         pt_element_t curr_pte;
 290         struct kvm_shadow_walk_iterator iterator;
 291
 292         if (!is_present_gpte(gw->ptes[gw->level - 1]))
 293                 return NULL;
 294
 295         for_each_shadow_entry(vcpu, addr, iterator) {
 296                 level = iterator.level;
 297                 sptep = iterator.sptep;
 298                 if (level == PT_PAGE_TABLE_LEVEL
 299                     || (largepage && level == PT_DIRECTORY_LEVEL)) {
 300                         mmu_set_spte(vcpu, sptep, access,
 301                                      gw->pte_access & access,
 302                                      user_fault, write_fault,
 303                                      gw->ptes[gw->level-1] & PT_DIRTY_MASK,
 304                                      ptwrite, largepage,
 305                                      gw->gfn, pfn, false);
 306                         break;
 307                 }
 308
 309                 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
 310                         continue;
 311
 312                 if (is_large_pte(*sptep)) {
 313                         rmap_remove(vcpu->kvm, sptep);
 314                         __set_spte(sptep, shadow_trap_nonpresent_pte);
 315                         kvm_flush_remote_tlbs(vcpu->kvm);
 316                 }
 317
 318                 if (level == PT_DIRECTORY_LEVEL
 319                     && gw->level == PT_DIRECTORY_LEVEL) {
 320                         direct = 1;
 321                         if (!is_dirty_gpte(gw->ptes[level - 1]))
 322                                 access &= ~ACC_WRITE_MASK;
 323                         table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
 324                 } else {
 325                         direct = 0;
 326                         table_gfn = gw->table_gfn[level - 2];
 327                 }
 328                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 329                                                direct, access, sptep);
 330                 if (!direct) {
 331                         r = kvm_read_guest_atomic(vcpu->kvm,
 332                                                   gw->pte_gpa[level - 2],
 333                                                   &curr_pte, sizeof(curr_pte));
 334                         if (r || curr_pte != gw->ptes[level - 2]) {
 335                                 kvm_mmu_put_page(shadow_page, sptep);
 336                                 kvm_release_pfn_clean(pfn);
 337                                 sptep = NULL;
 338                                 break;
 339                         }
 340                 }
 341
 342                 spte = __pa(shadow_page->spt)
 343                         | PT_PRESENT_MASK | PT_ACCESSED_MASK
 344                         | PT_WRITABLE_MASK | PT_USER_MASK;
 345                 *sptep = spte;
 346         }
 347
 348         return sptep;
 349 }
 350
 351 /*
 352  * Page fault handler.  There are several causes for a page fault:
 353  *   - there is no shadow pte for the guest pte
 354  *   - write access through a shadow pte marked read only so that we can set
 355  *     the dirty bit
 356  *   - write access to a shadow pte marked read only so we can update the page
 357  *     dirty bitmap, when userspace requests it
 358  *   - mmio access; in this case we will never install a present shadow pte
 359  *   - normal guest page fault due to the guest pte marked not present, not
 360  *     writable, or not executable
 361  *
 362  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 363  *           a negative value on error.
 364  */
 365 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 366                                u32 error_code)
 367 {
 368         int write_fault = error_code & PFERR_WRITE_MASK;
 369         int user_fault = error_code & PFERR_USER_MASK;
 370         int fetch_fault = error_code & PFERR_FETCH_MASK;
 371         struct guest_walker walker;
 372         u64 *sptep;
 373         int write_pt = 0;
 374         int r;
 375         pfn_t pfn;
 376         int largepage = 0;
 377         unsigned long mmu_seq;
 378
 379         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 380         kvm_mmu_audit(vcpu, "pre page fault");
 381
 382         r = mmu_topup_memory_caches(vcpu);
 383         if (r)
 384                 return r;
 385
 386         /*
 387          * Look up the guest pte for the faulting address.
 388          */
 389         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 390                              fetch_fault);
 391
 392         /*
 393          * The page is not mapped by the guest.  Let the guest handle it.
 394          */
 395         if (!r) {
 396                 pgprintk("%s: guest page fault\n", __func__);
 397                 inject_page_fault(vcpu, addr, walker.error_code);
 398                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 399                 return 0;
 400         }
 401
 402         if (walker.level == PT_DIRECTORY_LEVEL) {
 403                 gfn_t large_gfn;
 404                 large_gfn = walker.gfn &
 405                         ~(KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL) - 1);
 406                 if (is_largepage_backed(vcpu, large_gfn)) {
 407                         walker.gfn = large_gfn;
 408                         largepage = 1;
 409                 }
 410         }
 411         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 412         smp_rmb();
 413         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
 414
 415         /* mmio */
 416         if (is_error_pfn(pfn)) {
 417                 pgprintk("gfn %lx is mmio\n", walker.gfn);
 418                 kvm_release_pfn_clean(pfn);
 419                 return 1;
 420         }
 421
 422         spin_lock(&vcpu->kvm->mmu_lock);
 423         if (mmu_notifier_retry(vcpu, mmu_seq))
 424                 goto out_unlock;
 425         kvm_mmu_free_some_pages(vcpu);
 426         sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 427                              largepage, &write_pt, pfn);
 428
 429         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
 430                  sptep, *sptep, write_pt);
 431
 432         if (!write_pt)
 433                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 434
 435         ++vcpu->stat.pf_fixed;
 436         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 437         spin_unlock(&vcpu->kvm->mmu_lock);
 438
 439         return write_pt;
 440
 441 out_unlock:
 442         spin_unlock(&vcpu->kvm->mmu_lock);
 443         kvm_release_pfn_clean(pfn);
 444         return 0;
 445 }
 446
 447 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 448 {
 449         struct kvm_shadow_walk_iterator iterator;
 450         pt_element_t gpte;
 451         gpa_t pte_gpa = -1;
 452         int level;
 453         u64 *sptep;
 454         int need_flush = 0;
 455
 456         spin_lock(&vcpu->kvm->mmu_lock);
 457
 458         for_each_shadow_entry(vcpu, gva, iterator) {
 459                 level = iterator.level;
 460                 sptep = iterator.sptep;
 461
 462                 /* FIXME: properly handle invlpg on large guest pages */
 463                 if (level == PT_PAGE_TABLE_LEVEL ||
 464                     ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
 465                         struct kvm_mmu_page *sp = page_header(__pa(sptep));
 466
 467                         pte_gpa = (sp->gfn << PAGE_SHIFT);
 468                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 469
 470                         if (is_shadow_present_pte(*sptep)) {
 471                                 rmap_remove(vcpu->kvm, sptep);
 472                                 if (is_large_pte(*sptep))
 473                                         --vcpu->kvm->stat.lpages;
 474                                 need_flush = 1;
 475                         }
 476                         __set_spte(sptep, shadow_trap_nonpresent_pte);
 477                         break;
 478                 }
 479
 480                 if (!is_shadow_present_pte(*sptep))
 481                         break;
 482         }
 483
 484         if (need_flush)
 485                 kvm_flush_remote_tlbs(vcpu->kvm);
 486         spin_unlock(&vcpu->kvm->mmu_lock);
 487
 488         if (pte_gpa == -1)
 489                 return;
 490         if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 491                                   sizeof(pt_element_t)))
 492                 return;
 493         if (is_present_gpte(gpte) && (gpte & PT_ACCESSED_MASK)) {
 494                 if (mmu_topup_memory_caches(vcpu))
 495                         return;
 496                 kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
 497                                   sizeof(pt_element_t), 0);
 498         }
 499 }
 500
 501 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 502 {
 503         struct guest_walker walker;
 504         gpa_t gpa = UNMAPPED_GVA;
 505         int r;
 506
 507         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 508
 509         if (r) {
 510                 gpa = gfn_to_gpa(walker.gfn);
 511                 gpa |= vaddr & ~PAGE_MASK;
 512         }
 513
 514         return gpa;
 515 }
 516
 517 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 518                                  struct kvm_mmu_page *sp)
 519 {
 520         int i, j, offset, r;
 521         pt_element_t pt[256 / sizeof(pt_element_t)];
 522         gpa_t pte_gpa;
 523
 524         if (sp->role.direct
 525             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 526                 nonpaging_prefetch_page(vcpu, sp);
 527                 return;
 528         }
 529
 530         pte_gpa = gfn_to_gpa(sp->gfn);
 531         if (PTTYPE == 32) {
 532                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 533                 pte_gpa += offset * sizeof(pt_element_t);
 534         }
 535
 536         for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
 537                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
 538                 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
 539                 for (j = 0; j < ARRAY_SIZE(pt); ++j)
 540                         if (r || is_present_gpte(pt[j]))
 541                                 sp->spt[i+j] = shadow_trap_nonpresent_pte;
 542                         else
 543                                 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
 544         }
 545 }
 546
 547 /*
 548  * Using the cached information from sp->gfns is safe because:
 549  * - The spte has a reference to the struct page, so the pfn for a given gfn
 550  *   can't change unless all sptes pointing to it are nuked first.
 551  * - Alias changes zap the entire shadow cache.
 552  */
 553 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 554 {
 555         int i, offset, nr_present;
 556
 557         offset = nr_present = 0;
 558
 559         if (PTTYPE == 32)
 560                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 561
 562         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
 563                 unsigned pte_access;
 564                 pt_element_t gpte;
 565                 gpa_t pte_gpa;
 566                 gfn_t gfn = sp->gfns[i];
 567
 568                 if (!is_shadow_present_pte(sp->spt[i]))
 569                         continue;
 570
 571                 pte_gpa = gfn_to_gpa(sp->gfn);
 572                 pte_gpa += (i+offset) * sizeof(pt_element_t);
 573
 574                 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 575                                           sizeof(pt_element_t)))
 576                         return -EINVAL;
 577
 578                 if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
 579                     !(gpte & PT_ACCESSED_MASK)) {
 580                         u64 nonpresent;
 581
 582                         rmap_remove(vcpu->kvm, &sp->spt[i]);
 583                         if (is_present_gpte(gpte))
 584                                 nonpresent = shadow_trap_nonpresent_pte;
 585                         else
 586                                 nonpresent = shadow_notrap_nonpresent_pte;
 587                         __set_spte(&sp->spt[i], nonpresent);
 588                         continue;
 589                 }
 590
 591                 nr_present++;
 592                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 593                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
 594                          is_dirty_gpte(gpte), 0, gfn,
 595                          spte_to_pfn(sp->spt[i]), true, false);
 596         }
 597
 598         return !nr_present;
 599 }
 600
 601 #undef pt_element_t
 602 #undef guest_walker
 603 #undef FNAME
 604 #undef PT_BASE_ADDR_MASK
 605 #undef PT_INDEX
 606 #undef PT_LEVEL_MASK
 607 #undef PT_DIR_BASE_ADDR_MASK
 608 #undef PT_LEVEL_BITS
 609 #undef PT_MAX_FULL_LEVELS
 610 #undef gpte_to_gfn
 611 #undef gpte_to_gfn_pde
 612 #undef CMPXCHG