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[deliverable/linux.git] / arch / x86 / kvm / paging_tmpl.h
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #ifdef CONFIG_X86_64
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
39 #else
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
42 #endif
43 #elif PTTYPE == 32
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
55 #else
56 #error Invalid PTTYPE value
57 #endif
58
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61
62 /*
63 * The guest_walker structure emulates the behavior of the hardware page
64 * table walker.
65 */
66 struct guest_walker {
67 int level;
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
72 unsigned pt_access;
73 unsigned pte_access;
74 gfn_t gfn;
75 struct x86_exception fault;
76 };
77
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
79 {
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 }
82
83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
86 {
87 pt_element_t ret;
88 pt_element_t *table;
89 struct page *page;
90
91 page = gfn_to_page(kvm, table_gfn);
92
93 table = kmap_atomic(page, KM_USER0);
94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
95 kunmap_atomic(table, KM_USER0);
96
97 kvm_release_page_dirty(page);
98
99 return (ret != orig_pte);
100 }
101
102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
103 {
104 unsigned access;
105
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107 #if PTTYPE == 64
108 if (vcpu->arch.mmu.nx)
109 access &= ~(gpte >> PT64_NX_SHIFT);
110 #endif
111 return access;
112 }
113
114 /*
115 * Fetch a guest pte for a guest virtual address
116 */
117 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
119 gva_t addr, u32 access)
120 {
121 pt_element_t pte;
122 gfn_t table_gfn;
123 unsigned index, pt_access, uninitialized_var(pte_access);
124 gpa_t pte_gpa;
125 bool eperm, present, rsvd_fault;
126 int offset, write_fault, user_fault, fetch_fault;
127
128 write_fault = access & PFERR_WRITE_MASK;
129 user_fault = access & PFERR_USER_MASK;
130 fetch_fault = access & PFERR_FETCH_MASK;
131
132 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
133 fetch_fault);
134 walk:
135 present = true;
136 eperm = rsvd_fault = false;
137 walker->level = mmu->root_level;
138 pte = mmu->get_cr3(vcpu);
139
140 #if PTTYPE == 64
141 if (walker->level == PT32E_ROOT_LEVEL) {
142 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
143 trace_kvm_mmu_paging_element(pte, walker->level);
144 if (!is_present_gpte(pte)) {
145 present = false;
146 goto error;
147 }
148 --walker->level;
149 }
150 #endif
151 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
152 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
153
154 pt_access = ACC_ALL;
155
156 for (;;) {
157 index = PT_INDEX(addr, walker->level);
158
159 table_gfn = gpte_to_gfn(pte);
160 offset = index * sizeof(pt_element_t);
161 pte_gpa = gfn_to_gpa(table_gfn) + offset;
162 walker->table_gfn[walker->level - 1] = table_gfn;
163 walker->pte_gpa[walker->level - 1] = pte_gpa;
164
165 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
166 offset, sizeof(pte),
167 PFERR_USER_MASK|PFERR_WRITE_MASK)) {
168 present = false;
169 break;
170 }
171
172 trace_kvm_mmu_paging_element(pte, walker->level);
173
174 if (!is_present_gpte(pte)) {
175 present = false;
176 break;
177 }
178
179 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
180 rsvd_fault = true;
181 break;
182 }
183
184 if (write_fault && !is_writable_pte(pte))
185 if (user_fault || is_write_protection(vcpu))
186 eperm = true;
187
188 if (user_fault && !(pte & PT_USER_MASK))
189 eperm = true;
190
191 #if PTTYPE == 64
192 if (fetch_fault && (pte & PT64_NX_MASK))
193 eperm = true;
194 #endif
195
196 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
197 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
198 sizeof(pte));
199 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
200 index, pte, pte|PT_ACCESSED_MASK))
201 goto walk;
202 mark_page_dirty(vcpu->kvm, table_gfn);
203 pte |= PT_ACCESSED_MASK;
204 }
205
206 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
207
208 walker->ptes[walker->level - 1] = pte;
209
210 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
211 ((walker->level == PT_DIRECTORY_LEVEL) &&
212 is_large_pte(pte) &&
213 (PTTYPE == 64 || is_pse(vcpu))) ||
214 ((walker->level == PT_PDPE_LEVEL) &&
215 is_large_pte(pte) &&
216 mmu->root_level == PT64_ROOT_LEVEL)) {
217 int lvl = walker->level;
218 gpa_t real_gpa;
219 gfn_t gfn;
220 u32 ac;
221
222 gfn = gpte_to_gfn_lvl(pte, lvl);
223 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
224
225 if (PTTYPE == 32 &&
226 walker->level == PT_DIRECTORY_LEVEL &&
227 is_cpuid_PSE36())
228 gfn += pse36_gfn_delta(pte);
229
230 ac = write_fault | fetch_fault | user_fault;
231
232 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
233 ac);
234 if (real_gpa == UNMAPPED_GVA)
235 return 0;
236
237 walker->gfn = real_gpa >> PAGE_SHIFT;
238
239 break;
240 }
241
242 pt_access = pte_access;
243 --walker->level;
244 }
245
246 if (!present || eperm || rsvd_fault)
247 goto error;
248
249 if (write_fault && !is_dirty_gpte(pte)) {
250 bool ret;
251
252 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
253 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
254 pte|PT_DIRTY_MASK);
255 if (ret)
256 goto walk;
257 mark_page_dirty(vcpu->kvm, table_gfn);
258 pte |= PT_DIRTY_MASK;
259 walker->ptes[walker->level - 1] = pte;
260 }
261
262 walker->pt_access = pt_access;
263 walker->pte_access = pte_access;
264 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
265 __func__, (u64)pte, pte_access, pt_access);
266 return 1;
267
268 error:
269 walker->fault.vector = PF_VECTOR;
270 walker->fault.error_code_valid = true;
271 walker->fault.error_code = 0;
272 if (present)
273 walker->fault.error_code |= PFERR_PRESENT_MASK;
274
275 walker->fault.error_code |= write_fault | user_fault;
276
277 if (fetch_fault && mmu->nx)
278 walker->fault.error_code |= PFERR_FETCH_MASK;
279 if (rsvd_fault)
280 walker->fault.error_code |= PFERR_RSVD_MASK;
281
282 walker->fault.address = addr;
283 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
284
285 trace_kvm_mmu_walker_error(walker->fault.error_code);
286 return 0;
287 }
288
289 static int FNAME(walk_addr)(struct guest_walker *walker,
290 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
291 {
292 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
293 access);
294 }
295
296 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
297 struct kvm_vcpu *vcpu, gva_t addr,
298 u32 access)
299 {
300 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
301 addr, access);
302 }
303
304 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
305 struct kvm_mmu_page *sp, u64 *spte,
306 pt_element_t gpte)
307 {
308 u64 nonpresent = shadow_trap_nonpresent_pte;
309
310 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
311 goto no_present;
312
313 if (!is_present_gpte(gpte)) {
314 if (!sp->unsync)
315 nonpresent = shadow_notrap_nonpresent_pte;
316 goto no_present;
317 }
318
319 if (!(gpte & PT_ACCESSED_MASK))
320 goto no_present;
321
322 return false;
323
324 no_present:
325 drop_spte(vcpu->kvm, spte, nonpresent);
326 return true;
327 }
328
329 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
330 u64 *spte, const void *pte)
331 {
332 pt_element_t gpte;
333 unsigned pte_access;
334 pfn_t pfn;
335
336 gpte = *(const pt_element_t *)pte;
337 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
338 return;
339
340 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
341 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
342 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
343 return;
344 pfn = vcpu->arch.update_pte.pfn;
345 if (is_error_pfn(pfn))
346 return;
347 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
348 return;
349 kvm_get_pfn(pfn);
350 /*
351 * we call mmu_set_spte() with host_writable = true beacuse that
352 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
353 */
354 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
355 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
356 gpte_to_gfn(gpte), pfn, true, true);
357 }
358
359 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
360 struct guest_walker *gw, int level)
361 {
362 pt_element_t curr_pte;
363 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
364 u64 mask;
365 int r, index;
366
367 if (level == PT_PAGE_TABLE_LEVEL) {
368 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
369 base_gpa = pte_gpa & ~mask;
370 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
371
372 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
373 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
374 curr_pte = gw->prefetch_ptes[index];
375 } else
376 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
377 &curr_pte, sizeof(curr_pte));
378
379 return r || curr_pte != gw->ptes[level - 1];
380 }
381
382 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
383 u64 *sptep)
384 {
385 struct kvm_mmu_page *sp;
386 pt_element_t *gptep = gw->prefetch_ptes;
387 u64 *spte;
388 int i;
389
390 sp = page_header(__pa(sptep));
391
392 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
393 return;
394
395 if (sp->role.direct)
396 return __direct_pte_prefetch(vcpu, sp, sptep);
397
398 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
399 spte = sp->spt + i;
400
401 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
402 pt_element_t gpte;
403 unsigned pte_access;
404 gfn_t gfn;
405 pfn_t pfn;
406 bool dirty;
407
408 if (spte == sptep)
409 continue;
410
411 if (*spte != shadow_trap_nonpresent_pte)
412 continue;
413
414 gpte = gptep[i];
415
416 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
417 continue;
418
419 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
420 gfn = gpte_to_gfn(gpte);
421 dirty = is_dirty_gpte(gpte);
422 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
423 (pte_access & ACC_WRITE_MASK) && dirty);
424 if (is_error_pfn(pfn)) {
425 kvm_release_pfn_clean(pfn);
426 break;
427 }
428
429 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
430 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
431 pfn, true, true);
432 }
433 }
434
435 /*
436 * Fetch a shadow pte for a specific level in the paging hierarchy.
437 */
438 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
439 struct guest_walker *gw,
440 int user_fault, int write_fault, int hlevel,
441 int *ptwrite, pfn_t pfn, bool map_writable,
442 bool prefault)
443 {
444 unsigned access = gw->pt_access;
445 struct kvm_mmu_page *sp = NULL;
446 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
447 int top_level;
448 unsigned direct_access;
449 struct kvm_shadow_walk_iterator it;
450
451 if (!is_present_gpte(gw->ptes[gw->level - 1]))
452 return NULL;
453
454 direct_access = gw->pt_access & gw->pte_access;
455 if (!dirty)
456 direct_access &= ~ACC_WRITE_MASK;
457
458 top_level = vcpu->arch.mmu.root_level;
459 if (top_level == PT32E_ROOT_LEVEL)
460 top_level = PT32_ROOT_LEVEL;
461 /*
462 * Verify that the top-level gpte is still there. Since the page
463 * is a root page, it is either write protected (and cannot be
464 * changed from now on) or it is invalid (in which case, we don't
465 * really care if it changes underneath us after this point).
466 */
467 if (FNAME(gpte_changed)(vcpu, gw, top_level))
468 goto out_gpte_changed;
469
470 for (shadow_walk_init(&it, vcpu, addr);
471 shadow_walk_okay(&it) && it.level > gw->level;
472 shadow_walk_next(&it)) {
473 gfn_t table_gfn;
474
475 drop_large_spte(vcpu, it.sptep);
476
477 sp = NULL;
478 if (!is_shadow_present_pte(*it.sptep)) {
479 table_gfn = gw->table_gfn[it.level - 2];
480 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
481 false, access, it.sptep);
482 }
483
484 /*
485 * Verify that the gpte in the page we've just write
486 * protected is still there.
487 */
488 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
489 goto out_gpte_changed;
490
491 if (sp)
492 link_shadow_page(it.sptep, sp);
493 }
494
495 for (;
496 shadow_walk_okay(&it) && it.level > hlevel;
497 shadow_walk_next(&it)) {
498 gfn_t direct_gfn;
499
500 validate_direct_spte(vcpu, it.sptep, direct_access);
501
502 drop_large_spte(vcpu, it.sptep);
503
504 if (is_shadow_present_pte(*it.sptep))
505 continue;
506
507 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
508
509 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
510 true, direct_access, it.sptep);
511 link_shadow_page(it.sptep, sp);
512 }
513
514 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
515 user_fault, write_fault, dirty, ptwrite, it.level,
516 gw->gfn, pfn, prefault, map_writable);
517 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
518
519 return it.sptep;
520
521 out_gpte_changed:
522 if (sp)
523 kvm_mmu_put_page(sp, it.sptep);
524 kvm_release_pfn_clean(pfn);
525 return NULL;
526 }
527
528 /*
529 * Page fault handler. There are several causes for a page fault:
530 * - there is no shadow pte for the guest pte
531 * - write access through a shadow pte marked read only so that we can set
532 * the dirty bit
533 * - write access to a shadow pte marked read only so we can update the page
534 * dirty bitmap, when userspace requests it
535 * - mmio access; in this case we will never install a present shadow pte
536 * - normal guest page fault due to the guest pte marked not present, not
537 * writable, or not executable
538 *
539 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
540 * a negative value on error.
541 */
542 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
543 bool prefault)
544 {
545 int write_fault = error_code & PFERR_WRITE_MASK;
546 int user_fault = error_code & PFERR_USER_MASK;
547 struct guest_walker walker;
548 u64 *sptep;
549 int write_pt = 0;
550 int r;
551 pfn_t pfn;
552 int level = PT_PAGE_TABLE_LEVEL;
553 int force_pt_level;
554 unsigned long mmu_seq;
555 bool map_writable;
556
557 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
558
559 r = mmu_topup_memory_caches(vcpu);
560 if (r)
561 return r;
562
563 /*
564 * Look up the guest pte for the faulting address.
565 */
566 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
567
568 /*
569 * The page is not mapped by the guest. Let the guest handle it.
570 */
571 if (!r) {
572 pgprintk("%s: guest page fault\n", __func__);
573 if (!prefault) {
574 inject_page_fault(vcpu, &walker.fault);
575 /* reset fork detector */
576 vcpu->arch.last_pt_write_count = 0;
577 }
578 return 0;
579 }
580
581 if (walker.level >= PT_DIRECTORY_LEVEL)
582 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
583 else
584 force_pt_level = 1;
585 if (!force_pt_level) {
586 level = min(walker.level, mapping_level(vcpu, walker.gfn));
587 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
588 }
589
590 mmu_seq = vcpu->kvm->mmu_notifier_seq;
591 smp_rmb();
592
593 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
594 &map_writable))
595 return 0;
596
597 /* mmio */
598 if (is_error_pfn(pfn))
599 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
600
601 spin_lock(&vcpu->kvm->mmu_lock);
602 if (mmu_notifier_retry(vcpu, mmu_seq))
603 goto out_unlock;
604
605 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
606 kvm_mmu_free_some_pages(vcpu);
607 if (!force_pt_level)
608 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
609 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
610 level, &write_pt, pfn, map_writable, prefault);
611 (void)sptep;
612 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
613 sptep, *sptep, write_pt);
614
615 if (!write_pt)
616 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
617
618 ++vcpu->stat.pf_fixed;
619 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
620 spin_unlock(&vcpu->kvm->mmu_lock);
621
622 return write_pt;
623
624 out_unlock:
625 spin_unlock(&vcpu->kvm->mmu_lock);
626 kvm_release_pfn_clean(pfn);
627 return 0;
628 }
629
630 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
631 {
632 struct kvm_shadow_walk_iterator iterator;
633 struct kvm_mmu_page *sp;
634 gpa_t pte_gpa = -1;
635 int level;
636 u64 *sptep;
637 int need_flush = 0;
638
639 spin_lock(&vcpu->kvm->mmu_lock);
640
641 for_each_shadow_entry(vcpu, gva, iterator) {
642 level = iterator.level;
643 sptep = iterator.sptep;
644
645 sp = page_header(__pa(sptep));
646 if (is_last_spte(*sptep, level)) {
647 int offset, shift;
648
649 if (!sp->unsync)
650 break;
651
652 shift = PAGE_SHIFT -
653 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
654 offset = sp->role.quadrant << shift;
655
656 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
657 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
658
659 if (is_shadow_present_pte(*sptep)) {
660 if (is_large_pte(*sptep))
661 --vcpu->kvm->stat.lpages;
662 drop_spte(vcpu->kvm, sptep,
663 shadow_trap_nonpresent_pte);
664 need_flush = 1;
665 } else
666 __set_spte(sptep, shadow_trap_nonpresent_pte);
667 break;
668 }
669
670 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
671 break;
672 }
673
674 if (need_flush)
675 kvm_flush_remote_tlbs(vcpu->kvm);
676
677 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
678
679 spin_unlock(&vcpu->kvm->mmu_lock);
680
681 if (pte_gpa == -1)
682 return;
683
684 if (mmu_topup_memory_caches(vcpu))
685 return;
686 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
687 }
688
689 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
690 struct x86_exception *exception)
691 {
692 struct guest_walker walker;
693 gpa_t gpa = UNMAPPED_GVA;
694 int r;
695
696 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
697
698 if (r) {
699 gpa = gfn_to_gpa(walker.gfn);
700 gpa |= vaddr & ~PAGE_MASK;
701 } else if (exception)
702 *exception = walker.fault;
703
704 return gpa;
705 }
706
707 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
708 u32 access,
709 struct x86_exception *exception)
710 {
711 struct guest_walker walker;
712 gpa_t gpa = UNMAPPED_GVA;
713 int r;
714
715 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
716
717 if (r) {
718 gpa = gfn_to_gpa(walker.gfn);
719 gpa |= vaddr & ~PAGE_MASK;
720 } else if (exception)
721 *exception = walker.fault;
722
723 return gpa;
724 }
725
726 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
727 struct kvm_mmu_page *sp)
728 {
729 int i, j, offset, r;
730 pt_element_t pt[256 / sizeof(pt_element_t)];
731 gpa_t pte_gpa;
732
733 if (sp->role.direct
734 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
735 nonpaging_prefetch_page(vcpu, sp);
736 return;
737 }
738
739 pte_gpa = gfn_to_gpa(sp->gfn);
740 if (PTTYPE == 32) {
741 offset = sp->role.quadrant << PT64_LEVEL_BITS;
742 pte_gpa += offset * sizeof(pt_element_t);
743 }
744
745 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
746 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
747 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
748 for (j = 0; j < ARRAY_SIZE(pt); ++j)
749 if (r || is_present_gpte(pt[j]))
750 sp->spt[i+j] = shadow_trap_nonpresent_pte;
751 else
752 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
753 }
754 }
755
756 /*
757 * Using the cached information from sp->gfns is safe because:
758 * - The spte has a reference to the struct page, so the pfn for a given gfn
759 * can't change unless all sptes pointing to it are nuked first.
760 *
761 * Note:
762 * We should flush all tlbs if spte is dropped even though guest is
763 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
764 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
765 * used by guest then tlbs are not flushed, so guest is allowed to access the
766 * freed pages.
767 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
768 */
769 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
770 {
771 int i, offset, nr_present;
772 bool host_writable;
773 gpa_t first_pte_gpa;
774
775 offset = nr_present = 0;
776
777 /* direct kvm_mmu_page can not be unsync. */
778 BUG_ON(sp->role.direct);
779
780 if (PTTYPE == 32)
781 offset = sp->role.quadrant << PT64_LEVEL_BITS;
782
783 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
784
785 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
786 unsigned pte_access;
787 pt_element_t gpte;
788 gpa_t pte_gpa;
789 gfn_t gfn;
790
791 if (!is_shadow_present_pte(sp->spt[i]))
792 continue;
793
794 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
795
796 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
797 sizeof(pt_element_t)))
798 return -EINVAL;
799
800 gfn = gpte_to_gfn(gpte);
801
802 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
803 vcpu->kvm->tlbs_dirty++;
804 continue;
805 }
806
807 if (gfn != sp->gfns[i]) {
808 drop_spte(vcpu->kvm, &sp->spt[i],
809 shadow_trap_nonpresent_pte);
810 vcpu->kvm->tlbs_dirty++;
811 continue;
812 }
813
814 nr_present++;
815 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
816 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
817
818 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
819 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
820 spte_to_pfn(sp->spt[i]), true, false,
821 host_writable);
822 }
823
824 return !nr_present;
825 }
826
827 #undef pt_element_t
828 #undef guest_walker
829 #undef FNAME
830 #undef PT_BASE_ADDR_MASK
831 #undef PT_INDEX
832 #undef PT_LEVEL_MASK
833 #undef PT_LVL_ADDR_MASK
834 #undef PT_LVL_OFFSET_MASK
835 #undef PT_LEVEL_BITS
836 #undef PT_MAX_FULL_LEVELS
837 #undef gpte_to_gfn
838 #undef gpte_to_gfn_lvl
839 #undef CMPXCHG
Linux kernel - Deliverables
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