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KVM: MMU: Clean up the error handling of walk_addr_generic()
[deliverable/linux.git] / arch / x86 / kvm / paging_tmpl.h
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
53 #else
54 #error Invalid PTTYPE value
55 #endif
56
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
59
60 /*
61 * The guest_walker structure emulates the behavior of the hardware page
62 * table walker.
63 */
64 struct guest_walker {
65 int level;
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
70 unsigned pt_access;
71 unsigned pte_access;
72 gfn_t gfn;
73 struct x86_exception fault;
74 };
75
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
77 {
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
79 }
80
81 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
82 pt_element_t __user *ptep_user, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
84 {
85 int npages;
86 pt_element_t ret;
87 pt_element_t *table;
88 struct page *page;
89
90 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
91 /* Check if the user is doing something meaningless. */
92 if (unlikely(npages != 1))
93 return -EFAULT;
94
95 table = kmap_atomic(page, KM_USER0);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
97 kunmap_atomic(table, KM_USER0);
98
99 kvm_release_page_dirty(page);
100
101 return (ret != orig_pte);
102 }
103
104 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
105 {
106 unsigned access;
107
108 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
109 #if PTTYPE == 64
110 if (vcpu->arch.mmu.nx)
111 access &= ~(gpte >> PT64_NX_SHIFT);
112 #endif
113 return access;
114 }
115
116 /*
117 * Fetch a guest pte for a guest virtual address
118 */
119 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
120 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
121 gva_t addr, u32 access)
122 {
123 pt_element_t pte;
124 pt_element_t __user *uninitialized_var(ptep_user);
125 gfn_t table_gfn;
126 unsigned index, pt_access, uninitialized_var(pte_access);
127 gpa_t pte_gpa;
128 bool eperm;
129 int offset;
130 const int write_fault = access & PFERR_WRITE_MASK;
131 const int user_fault = access & PFERR_USER_MASK;
132 const int fetch_fault = access & PFERR_FETCH_MASK;
133 u16 errcode = 0;
134
135 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
136 fetch_fault);
137 walk:
138 eperm = false;
139 walker->level = mmu->root_level;
140 pte = mmu->get_cr3(vcpu);
141
142 #if PTTYPE == 64
143 if (walker->level == PT32E_ROOT_LEVEL) {
144 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
145 trace_kvm_mmu_paging_element(pte, walker->level);
146 if (!is_present_gpte(pte))
147 goto error;
148 --walker->level;
149 }
150 #endif
151 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
152 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
153
154 pt_access = ACC_ALL;
155
156 for (;;) {
157 gfn_t real_gfn;
158 unsigned long host_addr;
159
160 index = PT_INDEX(addr, walker->level);
161
162 table_gfn = gpte_to_gfn(pte);
163 offset = index * sizeof(pt_element_t);
164 pte_gpa = gfn_to_gpa(table_gfn) + offset;
165 walker->table_gfn[walker->level - 1] = table_gfn;
166 walker->pte_gpa[walker->level - 1] = pte_gpa;
167
168 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
169 PFERR_USER_MASK|PFERR_WRITE_MASK);
170 if (unlikely(real_gfn == UNMAPPED_GVA))
171 goto error;
172 real_gfn = gpa_to_gfn(real_gfn);
173
174 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
175 if (unlikely(kvm_is_error_hva(host_addr)))
176 goto error;
177
178 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
179 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
180 goto error;
181
182 trace_kvm_mmu_paging_element(pte, walker->level);
183
184 if (unlikely(!is_present_gpte(pte)))
185 goto error;
186
187 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
188 walker->level))) {
189 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
190 goto error;
191 }
192
193 if (unlikely(write_fault && !is_writable_pte(pte)
194 && (user_fault || is_write_protection(vcpu))))
195 eperm = true;
196
197 if (unlikely(user_fault && !(pte & PT_USER_MASK)))
198 eperm = true;
199
200 #if PTTYPE == 64
201 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
202 eperm = true;
203 #endif
204
205 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
206 int ret;
207 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
208 sizeof(pte));
209 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
210 pte, pte|PT_ACCESSED_MASK);
211 if (unlikely(ret < 0))
212 goto error;
213 else if (ret)
214 goto walk;
215
216 mark_page_dirty(vcpu->kvm, table_gfn);
217 pte |= PT_ACCESSED_MASK;
218 }
219
220 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
221
222 walker->ptes[walker->level - 1] = pte;
223
224 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
225 ((walker->level == PT_DIRECTORY_LEVEL) &&
226 is_large_pte(pte) &&
227 (PTTYPE == 64 || is_pse(vcpu))) ||
228 ((walker->level == PT_PDPE_LEVEL) &&
229 is_large_pte(pte) &&
230 mmu->root_level == PT64_ROOT_LEVEL)) {
231 int lvl = walker->level;
232 gpa_t real_gpa;
233 gfn_t gfn;
234 u32 ac;
235
236 /* check if the kernel is fetching from user page */
237 if (unlikely(pte_access & PT_USER_MASK) &&
238 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
239 if (fetch_fault && !user_fault)
240 eperm = true;
241
242 gfn = gpte_to_gfn_lvl(pte, lvl);
243 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
244
245 if (PTTYPE == 32 &&
246 walker->level == PT_DIRECTORY_LEVEL &&
247 is_cpuid_PSE36())
248 gfn += pse36_gfn_delta(pte);
249
250 ac = write_fault | fetch_fault | user_fault;
251
252 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
253 ac);
254 if (real_gpa == UNMAPPED_GVA)
255 return 0;
256
257 walker->gfn = real_gpa >> PAGE_SHIFT;
258
259 break;
260 }
261
262 pt_access = pte_access;
263 --walker->level;
264 }
265
266 if (unlikely(eperm)) {
267 errcode |= PFERR_PRESENT_MASK;
268 goto error;
269 }
270
271 if (write_fault && unlikely(!is_dirty_gpte(pte))) {
272 int ret;
273
274 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
275 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
276 pte, pte|PT_DIRTY_MASK);
277 if (unlikely(ret < 0))
278 goto error;
279 else if (ret)
280 goto walk;
281
282 mark_page_dirty(vcpu->kvm, table_gfn);
283 pte |= PT_DIRTY_MASK;
284 walker->ptes[walker->level - 1] = pte;
285 }
286
287 walker->pt_access = pt_access;
288 walker->pte_access = pte_access;
289 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
290 __func__, (u64)pte, pte_access, pt_access);
291 return 1;
292
293 error:
294 errcode |= write_fault | user_fault;
295 if (fetch_fault && (mmu->nx ||
296 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
297 errcode |= PFERR_FETCH_MASK;
298
299 walker->fault.vector = PF_VECTOR;
300 walker->fault.error_code_valid = true;
301 walker->fault.error_code = errcode;
302 walker->fault.address = addr;
303 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
304
305 trace_kvm_mmu_walker_error(walker->fault.error_code);
306 return 0;
307 }
308
309 static int FNAME(walk_addr)(struct guest_walker *walker,
310 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
311 {
312 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
313 access);
314 }
315
316 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
317 struct kvm_vcpu *vcpu, gva_t addr,
318 u32 access)
319 {
320 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
321 addr, access);
322 }
323
324 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
325 struct kvm_mmu_page *sp, u64 *spte,
326 pt_element_t gpte)
327 {
328 u64 nonpresent = shadow_trap_nonpresent_pte;
329
330 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
331 goto no_present;
332
333 if (!is_present_gpte(gpte)) {
334 if (!sp->unsync)
335 nonpresent = shadow_notrap_nonpresent_pte;
336 goto no_present;
337 }
338
339 if (!(gpte & PT_ACCESSED_MASK))
340 goto no_present;
341
342 return false;
343
344 no_present:
345 drop_spte(vcpu->kvm, spte, nonpresent);
346 return true;
347 }
348
349 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
350 u64 *spte, const void *pte)
351 {
352 pt_element_t gpte;
353 unsigned pte_access;
354 pfn_t pfn;
355
356 gpte = *(const pt_element_t *)pte;
357 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
358 return;
359
360 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
361 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
362 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
363 if (is_error_pfn(pfn)) {
364 kvm_release_pfn_clean(pfn);
365 return;
366 }
367
368 /*
369 * we call mmu_set_spte() with host_writable = true because that
370 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
371 */
372 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
373 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
374 gpte_to_gfn(gpte), pfn, true, true);
375 }
376
377 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
378 struct guest_walker *gw, int level)
379 {
380 pt_element_t curr_pte;
381 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
382 u64 mask;
383 int r, index;
384
385 if (level == PT_PAGE_TABLE_LEVEL) {
386 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
387 base_gpa = pte_gpa & ~mask;
388 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
389
390 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
391 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
392 curr_pte = gw->prefetch_ptes[index];
393 } else
394 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
395 &curr_pte, sizeof(curr_pte));
396
397 return r || curr_pte != gw->ptes[level - 1];
398 }
399
400 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
401 u64 *sptep)
402 {
403 struct kvm_mmu_page *sp;
404 pt_element_t *gptep = gw->prefetch_ptes;
405 u64 *spte;
406 int i;
407
408 sp = page_header(__pa(sptep));
409
410 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
411 return;
412
413 if (sp->role.direct)
414 return __direct_pte_prefetch(vcpu, sp, sptep);
415
416 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
417 spte = sp->spt + i;
418
419 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
420 pt_element_t gpte;
421 unsigned pte_access;
422 gfn_t gfn;
423 pfn_t pfn;
424 bool dirty;
425
426 if (spte == sptep)
427 continue;
428
429 if (*spte != shadow_trap_nonpresent_pte)
430 continue;
431
432 gpte = gptep[i];
433
434 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
435 continue;
436
437 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
438 gfn = gpte_to_gfn(gpte);
439 dirty = is_dirty_gpte(gpte);
440 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
441 (pte_access & ACC_WRITE_MASK) && dirty);
442 if (is_error_pfn(pfn)) {
443 kvm_release_pfn_clean(pfn);
444 break;
445 }
446
447 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
448 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
449 pfn, true, true);
450 }
451 }
452
453 /*
454 * Fetch a shadow pte for a specific level in the paging hierarchy.
455 */
456 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
457 struct guest_walker *gw,
458 int user_fault, int write_fault, int hlevel,
459 int *ptwrite, pfn_t pfn, bool map_writable,
460 bool prefault)
461 {
462 unsigned access = gw->pt_access;
463 struct kvm_mmu_page *sp = NULL;
464 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
465 int top_level;
466 unsigned direct_access;
467 struct kvm_shadow_walk_iterator it;
468
469 if (!is_present_gpte(gw->ptes[gw->level - 1]))
470 return NULL;
471
472 direct_access = gw->pt_access & gw->pte_access;
473 if (!dirty)
474 direct_access &= ~ACC_WRITE_MASK;
475
476 top_level = vcpu->arch.mmu.root_level;
477 if (top_level == PT32E_ROOT_LEVEL)
478 top_level = PT32_ROOT_LEVEL;
479 /*
480 * Verify that the top-level gpte is still there. Since the page
481 * is a root page, it is either write protected (and cannot be
482 * changed from now on) or it is invalid (in which case, we don't
483 * really care if it changes underneath us after this point).
484 */
485 if (FNAME(gpte_changed)(vcpu, gw, top_level))
486 goto out_gpte_changed;
487
488 for (shadow_walk_init(&it, vcpu, addr);
489 shadow_walk_okay(&it) && it.level > gw->level;
490 shadow_walk_next(&it)) {
491 gfn_t table_gfn;
492
493 drop_large_spte(vcpu, it.sptep);
494
495 sp = NULL;
496 if (!is_shadow_present_pte(*it.sptep)) {
497 table_gfn = gw->table_gfn[it.level - 2];
498 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
499 false, access, it.sptep);
500 }
501
502 /*
503 * Verify that the gpte in the page we've just write
504 * protected is still there.
505 */
506 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
507 goto out_gpte_changed;
508
509 if (sp)
510 link_shadow_page(it.sptep, sp);
511 }
512
513 for (;
514 shadow_walk_okay(&it) && it.level > hlevel;
515 shadow_walk_next(&it)) {
516 gfn_t direct_gfn;
517
518 validate_direct_spte(vcpu, it.sptep, direct_access);
519
520 drop_large_spte(vcpu, it.sptep);
521
522 if (is_shadow_present_pte(*it.sptep))
523 continue;
524
525 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
526
527 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
528 true, direct_access, it.sptep);
529 link_shadow_page(it.sptep, sp);
530 }
531
532 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
533 user_fault, write_fault, dirty, ptwrite, it.level,
534 gw->gfn, pfn, prefault, map_writable);
535 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
536
537 return it.sptep;
538
539 out_gpte_changed:
540 if (sp)
541 kvm_mmu_put_page(sp, it.sptep);
542 kvm_release_pfn_clean(pfn);
543 return NULL;
544 }
545
546 /*
547 * Page fault handler. There are several causes for a page fault:
548 * - there is no shadow pte for the guest pte
549 * - write access through a shadow pte marked read only so that we can set
550 * the dirty bit
551 * - write access to a shadow pte marked read only so we can update the page
552 * dirty bitmap, when userspace requests it
553 * - mmio access; in this case we will never install a present shadow pte
554 * - normal guest page fault due to the guest pte marked not present, not
555 * writable, or not executable
556 *
557 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
558 * a negative value on error.
559 */
560 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
561 bool prefault)
562 {
563 int write_fault = error_code & PFERR_WRITE_MASK;
564 int user_fault = error_code & PFERR_USER_MASK;
565 struct guest_walker walker;
566 u64 *sptep;
567 int write_pt = 0;
568 int r;
569 pfn_t pfn;
570 int level = PT_PAGE_TABLE_LEVEL;
571 int force_pt_level;
572 unsigned long mmu_seq;
573 bool map_writable;
574
575 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
576
577 r = mmu_topup_memory_caches(vcpu);
578 if (r)
579 return r;
580
581 /*
582 * Look up the guest pte for the faulting address.
583 */
584 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
585
586 /*
587 * The page is not mapped by the guest. Let the guest handle it.
588 */
589 if (!r) {
590 pgprintk("%s: guest page fault\n", __func__);
591 if (!prefault) {
592 inject_page_fault(vcpu, &walker.fault);
593 /* reset fork detector */
594 vcpu->arch.last_pt_write_count = 0;
595 }
596 return 0;
597 }
598
599 if (walker.level >= PT_DIRECTORY_LEVEL)
600 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
601 else
602 force_pt_level = 1;
603 if (!force_pt_level) {
604 level = min(walker.level, mapping_level(vcpu, walker.gfn));
605 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
606 }
607
608 mmu_seq = vcpu->kvm->mmu_notifier_seq;
609 smp_rmb();
610
611 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
612 &map_writable))
613 return 0;
614
615 /* mmio */
616 if (is_error_pfn(pfn))
617 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
618
619 spin_lock(&vcpu->kvm->mmu_lock);
620 if (mmu_notifier_retry(vcpu, mmu_seq))
621 goto out_unlock;
622
623 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
624 kvm_mmu_free_some_pages(vcpu);
625 if (!force_pt_level)
626 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
627 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
628 level, &write_pt, pfn, map_writable, prefault);
629 (void)sptep;
630 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
631 sptep, *sptep, write_pt);
632
633 if (!write_pt)
634 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
635
636 ++vcpu->stat.pf_fixed;
637 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
638 spin_unlock(&vcpu->kvm->mmu_lock);
639
640 return write_pt;
641
642 out_unlock:
643 spin_unlock(&vcpu->kvm->mmu_lock);
644 kvm_release_pfn_clean(pfn);
645 return 0;
646 }
647
648 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
649 {
650 struct kvm_shadow_walk_iterator iterator;
651 struct kvm_mmu_page *sp;
652 gpa_t pte_gpa = -1;
653 int level;
654 u64 *sptep;
655 int need_flush = 0;
656
657 spin_lock(&vcpu->kvm->mmu_lock);
658
659 for_each_shadow_entry(vcpu, gva, iterator) {
660 level = iterator.level;
661 sptep = iterator.sptep;
662
663 sp = page_header(__pa(sptep));
664 if (is_last_spte(*sptep, level)) {
665 int offset, shift;
666
667 if (!sp->unsync)
668 break;
669
670 shift = PAGE_SHIFT -
671 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
672 offset = sp->role.quadrant << shift;
673
674 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
675 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
676
677 if (is_shadow_present_pte(*sptep)) {
678 if (is_large_pte(*sptep))
679 --vcpu->kvm->stat.lpages;
680 drop_spte(vcpu->kvm, sptep,
681 shadow_trap_nonpresent_pte);
682 need_flush = 1;
683 } else
684 __set_spte(sptep, shadow_trap_nonpresent_pte);
685 break;
686 }
687
688 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
689 break;
690 }
691
692 if (need_flush)
693 kvm_flush_remote_tlbs(vcpu->kvm);
694
695 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
696
697 spin_unlock(&vcpu->kvm->mmu_lock);
698
699 if (pte_gpa == -1)
700 return;
701
702 if (mmu_topup_memory_caches(vcpu))
703 return;
704 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
705 }
706
707 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
708 struct x86_exception *exception)
709 {
710 struct guest_walker walker;
711 gpa_t gpa = UNMAPPED_GVA;
712 int r;
713
714 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
715
716 if (r) {
717 gpa = gfn_to_gpa(walker.gfn);
718 gpa |= vaddr & ~PAGE_MASK;
719 } else if (exception)
720 *exception = walker.fault;
721
722 return gpa;
723 }
724
725 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
726 u32 access,
727 struct x86_exception *exception)
728 {
729 struct guest_walker walker;
730 gpa_t gpa = UNMAPPED_GVA;
731 int r;
732
733 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
734
735 if (r) {
736 gpa = gfn_to_gpa(walker.gfn);
737 gpa |= vaddr & ~PAGE_MASK;
738 } else if (exception)
739 *exception = walker.fault;
740
741 return gpa;
742 }
743
744 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
745 struct kvm_mmu_page *sp)
746 {
747 int i, j, offset, r;
748 pt_element_t pt[256 / sizeof(pt_element_t)];
749 gpa_t pte_gpa;
750
751 if (sp->role.direct
752 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
753 nonpaging_prefetch_page(vcpu, sp);
754 return;
755 }
756
757 pte_gpa = gfn_to_gpa(sp->gfn);
758 if (PTTYPE == 32) {
759 offset = sp->role.quadrant << PT64_LEVEL_BITS;
760 pte_gpa += offset * sizeof(pt_element_t);
761 }
762
763 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
764 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
765 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
766 for (j = 0; j < ARRAY_SIZE(pt); ++j)
767 if (r || is_present_gpte(pt[j]))
768 sp->spt[i+j] = shadow_trap_nonpresent_pte;
769 else
770 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
771 }
772 }
773
774 /*
775 * Using the cached information from sp->gfns is safe because:
776 * - The spte has a reference to the struct page, so the pfn for a given gfn
777 * can't change unless all sptes pointing to it are nuked first.
778 *
779 * Note:
780 * We should flush all tlbs if spte is dropped even though guest is
781 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
782 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
783 * used by guest then tlbs are not flushed, so guest is allowed to access the
784 * freed pages.
785 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
786 */
787 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
788 {
789 int i, offset, nr_present;
790 bool host_writable;
791 gpa_t first_pte_gpa;
792
793 offset = nr_present = 0;
794
795 /* direct kvm_mmu_page can not be unsync. */
796 BUG_ON(sp->role.direct);
797
798 if (PTTYPE == 32)
799 offset = sp->role.quadrant << PT64_LEVEL_BITS;
800
801 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
802
803 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
804 unsigned pte_access;
805 pt_element_t gpte;
806 gpa_t pte_gpa;
807 gfn_t gfn;
808
809 if (!is_shadow_present_pte(sp->spt[i]))
810 continue;
811
812 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
813
814 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
815 sizeof(pt_element_t)))
816 return -EINVAL;
817
818 gfn = gpte_to_gfn(gpte);
819
820 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
821 vcpu->kvm->tlbs_dirty++;
822 continue;
823 }
824
825 if (gfn != sp->gfns[i]) {
826 drop_spte(vcpu->kvm, &sp->spt[i],
827 shadow_trap_nonpresent_pte);
828 vcpu->kvm->tlbs_dirty++;
829 continue;
830 }
831
832 nr_present++;
833 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
834 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
835
836 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
837 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
838 spte_to_pfn(sp->spt[i]), true, false,
839 host_writable);
840 }
841
842 return !nr_present;
843 }
844
845 #undef pt_element_t
846 #undef guest_walker
847 #undef FNAME
848 #undef PT_BASE_ADDR_MASK
849 #undef PT_INDEX
850 #undef PT_LVL_ADDR_MASK
851 #undef PT_LVL_OFFSET_MASK
852 #undef PT_LEVEL_BITS
853 #undef PT_MAX_FULL_LEVELS
854 #undef gpte_to_gfn
855 #undef gpte_to_gfn_lvl
856 #undef CMPXCHG
Linux kernel - Deliverables
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