arch/x86/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  * Copyright 2010 Red Hat, Inc. and/or its affilates.
  11  *
  12  * Authors:
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Avi Kivity   <avi@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  */
  20
  21 /*
  22  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  23  * so the code in this file is compiled twice, once per pte size.
  24  */
  25
  26 #if PTTYPE == 64
  27         #define pt_element_t u64
  28         #define guest_walker guest_walker64
  29         #define FNAME(name) paging##64_##name
  30         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  31         #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
  32         #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
  33         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  34         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  35         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  36         #ifdef CONFIG_X86_64
  37         #define PT_MAX_FULL_LEVELS 4
  38         #define CMPXCHG cmpxchg
  39         #else
  40         #define CMPXCHG cmpxchg64
  41         #define PT_MAX_FULL_LEVELS 2
  42         #endif
  43 #elif PTTYPE == 32
  44         #define pt_element_t u32
  45         #define guest_walker guest_walker32
  46         #define FNAME(name) paging##32_##name
  47         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  48         #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
  49         #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
  50         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  51         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  52         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  53         #define PT_MAX_FULL_LEVELS 2
  54         #define CMPXCHG cmpxchg
  55 #else
  56         #error Invalid PTTYPE value
  57 #endif
  58
  59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
  60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
  61
  62 /*
  63  * The guest_walker structure emulates the behavior of the hardware page
  64  * table walker.
  65  */
  66 struct guest_walker {
  67         int level;
  68         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  69         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  70         pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
  71         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  72         unsigned pt_access;
  73         unsigned pte_access;
  74         gfn_t gfn;
  75         u32 error_code;
  76 };
  77
  78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
  79 {
  80         return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
  81 }
  82
  83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
  84                          gfn_t table_gfn, unsigned index,
  85                          pt_element_t orig_pte, pt_element_t new_pte)
  86 {
  87         pt_element_t ret;
  88         pt_element_t *table;
  89         struct page *page;
  90
  91         page = gfn_to_page(kvm, table_gfn);
  92
  93         table = kmap_atomic(page, KM_USER0);
  94         ret = CMPXCHG(&table[index], orig_pte, new_pte);
  95         kunmap_atomic(table, KM_USER0);
  96
  97         kvm_release_page_dirty(page);
  98
  99         return (ret != orig_pte);
 100 }
 101
 102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
 103 {
 104         unsigned access;
 105
 106         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
 107 #if PTTYPE == 64
 108         if (is_nx(vcpu))
 109                 access &= ~(gpte >> PT64_NX_SHIFT);
 110 #endif
 111         return access;
 112 }
 113
 114 /*
 115  * Fetch a guest pte for a guest virtual address
 116  */
 117 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
 118                                     struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 119                                     gva_t addr, int write_fault,
 120                                     int user_fault, int fetch_fault)
 121 {
 122         pt_element_t pte;
 123         gfn_t table_gfn;
 124         unsigned index, pt_access, uninitialized_var(pte_access);
 125         gpa_t pte_gpa;
 126         bool eperm, present, rsvd_fault;
 127         int offset;
 128         u32 access = 0;
 129
 130         trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
 131                                      fetch_fault);
 132 walk:
 133         present = true;
 134         eperm = rsvd_fault = false;
 135         walker->level = mmu->root_level;
 136         pte           = mmu->get_cr3(vcpu);
 137
 138 #if PTTYPE == 64
 139         if (walker->level == PT32E_ROOT_LEVEL) {
 140                 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
 141                 trace_kvm_mmu_paging_element(pte, walker->level);
 142                 if (!is_present_gpte(pte)) {
 143                         present = false;
 144                         goto error;
 145                 }
 146                 --walker->level;
 147         }
 148 #endif
 149         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 150                (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
 151
 152         pt_access = ACC_ALL;
 153
 154         for (;;) {
 155                 index = PT_INDEX(addr, walker->level);
 156
 157                 table_gfn = gpte_to_gfn(pte);
 158                 offset    = index * sizeof(pt_element_t);
 159                 pte_gpa   = gfn_to_gpa(table_gfn) + offset;
 160                 walker->table_gfn[walker->level - 1] = table_gfn;
 161                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 162
 163                 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
 164                                             offset, sizeof(pte),
 165                                             PFERR_USER_MASK|PFERR_WRITE_MASK)) {
 166                         present = false;
 167                         break;
 168                 }
 169
 170                 trace_kvm_mmu_paging_element(pte, walker->level);
 171
 172                 if (!is_present_gpte(pte)) {
 173                         present = false;
 174                         break;
 175                 }
 176
 177                 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
 178                         rsvd_fault = true;
 179                         break;
 180                 }
 181
 182                 if (write_fault && !is_writable_pte(pte))
 183                         if (user_fault || is_write_protection(vcpu))
 184                                 eperm = true;
 185
 186                 if (user_fault && !(pte & PT_USER_MASK))
 187                         eperm = true;
 188
 189 #if PTTYPE == 64
 190                 if (fetch_fault && (pte & PT64_NX_MASK))
 191                         eperm = true;
 192 #endif
 193
 194                 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
 195                         trace_kvm_mmu_set_accessed_bit(table_gfn, index,
 196                                                        sizeof(pte));
 197                         if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
 198                             index, pte, pte|PT_ACCESSED_MASK))
 199                                 goto walk;
 200                         mark_page_dirty(vcpu->kvm, table_gfn);
 201                         pte |= PT_ACCESSED_MASK;
 202                 }
 203
 204                 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
 205
 206                 walker->ptes[walker->level - 1] = pte;
 207
 208                 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
 209                     ((walker->level == PT_DIRECTORY_LEVEL) &&
 210                                 is_large_pte(pte) &&
 211                                 (PTTYPE == 64 || is_pse(vcpu))) ||
 212                     ((walker->level == PT_PDPE_LEVEL) &&
 213                                 is_large_pte(pte) &&
 214                                 mmu->root_level == PT64_ROOT_LEVEL)) {
 215                         int lvl = walker->level;
 216                         gpa_t real_gpa;
 217                         gfn_t gfn;
 218
 219                         gfn = gpte_to_gfn_lvl(pte, lvl);
 220                         gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
 221
 222                         if (PTTYPE == 32 &&
 223                             walker->level == PT_DIRECTORY_LEVEL &&
 224                             is_cpuid_PSE36())
 225                                 gfn += pse36_gfn_delta(pte);
 226
 227                         access |= write_fault ? PFERR_WRITE_MASK : 0;
 228                         access |= fetch_fault ? PFERR_FETCH_MASK : 0;
 229                         access |= user_fault  ? PFERR_USER_MASK  : 0;
 230
 231                         real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
 232                                                       access);
 233                         if (real_gpa == UNMAPPED_GVA)
 234                                 return 0;
 235
 236                         walker->gfn = real_gpa >> PAGE_SHIFT;
 237
 238                         break;
 239                 }
 240
 241                 pt_access = pte_access;
 242                 --walker->level;
 243         }
 244
 245         if (!present || eperm || rsvd_fault)
 246                 goto error;
 247
 248         if (write_fault && !is_dirty_gpte(pte)) {
 249                 bool ret;
 250
 251                 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
 252                 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
 253                             pte|PT_DIRTY_MASK);
 254                 if (ret)
 255                         goto walk;
 256                 mark_page_dirty(vcpu->kvm, table_gfn);
 257                 pte |= PT_DIRTY_MASK;
 258                 walker->ptes[walker->level - 1] = pte;
 259         }
 260
 261         walker->pt_access = pt_access;
 262         walker->pte_access = pte_access;
 263         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 264                  __func__, (u64)pte, pte_access, pt_access);
 265         return 1;
 266
 267 error:
 268         walker->error_code = 0;
 269         if (present)
 270                 walker->error_code |= PFERR_PRESENT_MASK;
 271         if (write_fault)
 272                 walker->error_code |= PFERR_WRITE_MASK;
 273         if (user_fault)
 274                 walker->error_code |= PFERR_USER_MASK;
 275         if (fetch_fault && is_nx(vcpu))
 276                 walker->error_code |= PFERR_FETCH_MASK;
 277         if (rsvd_fault)
 278                 walker->error_code |= PFERR_RSVD_MASK;
 279
 280         vcpu->arch.fault.address    = addr;
 281         vcpu->arch.fault.error_code = walker->error_code;
 282
 283         trace_kvm_mmu_walker_error(walker->error_code);
 284         return 0;
 285 }
 286
 287 static int FNAME(walk_addr)(struct guest_walker *walker,
 288                             struct kvm_vcpu *vcpu, gva_t addr,
 289                             int write_fault, int user_fault, int fetch_fault)
 290 {
 291         return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
 292                                         write_fault, user_fault, fetch_fault);
 293 }
 294
 295 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
 296                                    struct kvm_vcpu *vcpu, gva_t addr,
 297                                    int write_fault, int user_fault,
 298                                    int fetch_fault)
 299 {
 300         return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
 301                                         addr, write_fault, user_fault,
 302                                         fetch_fault);
 303 }
 304
 305 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 306                               u64 *spte, const void *pte)
 307 {
 308         pt_element_t gpte;
 309         unsigned pte_access;
 310         pfn_t pfn;
 311         u64 new_spte;
 312
 313         gpte = *(const pt_element_t *)pte;
 314         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 315                 if (!is_present_gpte(gpte)) {
 316                         if (sp->unsync)
 317                                 new_spte = shadow_trap_nonpresent_pte;
 318                         else
 319                                 new_spte = shadow_notrap_nonpresent_pte;
 320                         __set_spte(spte, new_spte);
 321                 }
 322                 return;
 323         }
 324         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 325         pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 326         if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
 327                 return;
 328         pfn = vcpu->arch.update_pte.pfn;
 329         if (is_error_pfn(pfn))
 330                 return;
 331         if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
 332                 return;
 333         kvm_get_pfn(pfn);
 334         /*
 335          * we call mmu_set_spte() with reset_host_protection = true beacuse that
 336          * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
 337          */
 338         mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
 339                      is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
 340                      gpte_to_gfn(gpte), pfn, true, true);
 341 }
 342
 343 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
 344                                 struct guest_walker *gw, int level)
 345 {
 346         pt_element_t curr_pte;
 347         gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
 348         u64 mask;
 349         int r, index;
 350
 351         if (level == PT_PAGE_TABLE_LEVEL) {
 352                 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
 353                 base_gpa = pte_gpa & ~mask;
 354                 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
 355
 356                 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
 357                                 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
 358                 curr_pte = gw->prefetch_ptes[index];
 359         } else
 360                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
 361                                   &curr_pte, sizeof(curr_pte));
 362
 363         return r || curr_pte != gw->ptes[level - 1];
 364 }
 365
 366 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
 367                                 u64 *sptep)
 368 {
 369         struct kvm_mmu_page *sp;
 370         struct kvm_mmu *mmu = &vcpu->arch.mmu;
 371         pt_element_t *gptep = gw->prefetch_ptes;
 372         u64 *spte;
 373         int i;
 374
 375         sp = page_header(__pa(sptep));
 376
 377         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
 378                 return;
 379
 380         if (sp->role.direct)
 381                 return __direct_pte_prefetch(vcpu, sp, sptep);
 382
 383         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
 384         spte = sp->spt + i;
 385
 386         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
 387                 pt_element_t gpte;
 388                 unsigned pte_access;
 389                 gfn_t gfn;
 390                 pfn_t pfn;
 391                 bool dirty;
 392
 393                 if (spte == sptep)
 394                         continue;
 395
 396                 if (*spte != shadow_trap_nonpresent_pte)
 397                         continue;
 398
 399                 gpte = gptep[i];
 400
 401                 if (!is_present_gpte(gpte) ||
 402                       is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) {
 403                         if (!sp->unsync)
 404                                 __set_spte(spte, shadow_notrap_nonpresent_pte);
 405                         continue;
 406                 }
 407
 408                 if (!(gpte & PT_ACCESSED_MASK))
 409                         continue;
 410
 411                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 412                 gfn = gpte_to_gfn(gpte);
 413                 dirty = is_dirty_gpte(gpte);
 414                 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
 415                                       (pte_access & ACC_WRITE_MASK) && dirty);
 416                 if (is_error_pfn(pfn)) {
 417                         kvm_release_pfn_clean(pfn);
 418                         break;
 419                 }
 420
 421                 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
 422                              dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
 423                              pfn, true, true);
 424         }
 425 }
 426
 427 /*
 428  * Fetch a shadow pte for a specific level in the paging hierarchy.
 429  */
 430 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 431                          struct guest_walker *gw,
 432                          int user_fault, int write_fault, int hlevel,
 433                          int *ptwrite, pfn_t pfn)
 434 {
 435         unsigned access = gw->pt_access;
 436         struct kvm_mmu_page *sp = NULL;
 437         bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
 438         int top_level;
 439         unsigned direct_access;
 440         struct kvm_shadow_walk_iterator it;
 441
 442         if (!is_present_gpte(gw->ptes[gw->level - 1]))
 443                 return NULL;
 444
 445         direct_access = gw->pt_access & gw->pte_access;
 446         if (!dirty)
 447                 direct_access &= ~ACC_WRITE_MASK;
 448
 449         top_level = vcpu->arch.mmu.root_level;
 450         if (top_level == PT32E_ROOT_LEVEL)
 451                 top_level = PT32_ROOT_LEVEL;
 452         /*
 453          * Verify that the top-level gpte is still there.  Since the page
 454          * is a root page, it is either write protected (and cannot be
 455          * changed from now on) or it is invalid (in which case, we don't
 456          * really care if it changes underneath us after this point).
 457          */
 458         if (FNAME(gpte_changed)(vcpu, gw, top_level))
 459                 goto out_gpte_changed;
 460
 461         for (shadow_walk_init(&it, vcpu, addr);
 462              shadow_walk_okay(&it) && it.level > gw->level;
 463              shadow_walk_next(&it)) {
 464                 gfn_t table_gfn;
 465
 466                 drop_large_spte(vcpu, it.sptep);
 467
 468                 sp = NULL;
 469                 if (!is_shadow_present_pte(*it.sptep)) {
 470                         table_gfn = gw->table_gfn[it.level - 2];
 471                         sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
 472                                               false, access, it.sptep);
 473                 }
 474
 475                 /*
 476                  * Verify that the gpte in the page we've just write
 477                  * protected is still there.
 478                  */
 479                 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
 480                         goto out_gpte_changed;
 481
 482                 if (sp)
 483                         link_shadow_page(it.sptep, sp);
 484         }
 485
 486         for (;
 487              shadow_walk_okay(&it) && it.level > hlevel;
 488              shadow_walk_next(&it)) {
 489                 gfn_t direct_gfn;
 490
 491                 validate_direct_spte(vcpu, it.sptep, direct_access);
 492
 493                 drop_large_spte(vcpu, it.sptep);
 494
 495                 if (is_shadow_present_pte(*it.sptep))
 496                         continue;
 497
 498                 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
 499
 500                 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
 501                                       true, direct_access, it.sptep);
 502                 link_shadow_page(it.sptep, sp);
 503         }
 504
 505         mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
 506                      user_fault, write_fault, dirty, ptwrite, it.level,
 507                      gw->gfn, pfn, false, true);
 508         FNAME(pte_prefetch)(vcpu, gw, it.sptep);
 509
 510         return it.sptep;
 511
 512 out_gpte_changed:
 513         if (sp)
 514                 kvm_mmu_put_page(sp, it.sptep);
 515         kvm_release_pfn_clean(pfn);
 516         return NULL;
 517 }
 518
 519 /*
 520  * Page fault handler.  There are several causes for a page fault:
 521  *   - there is no shadow pte for the guest pte
 522  *   - write access through a shadow pte marked read only so that we can set
 523  *     the dirty bit
 524  *   - write access to a shadow pte marked read only so we can update the page
 525  *     dirty bitmap, when userspace requests it
 526  *   - mmio access; in this case we will never install a present shadow pte
 527  *   - normal guest page fault due to the guest pte marked not present, not
 528  *     writable, or not executable
 529  *
 530  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 531  *           a negative value on error.
 532  */
 533 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 534                                u32 error_code)
 535 {
 536         int write_fault = error_code & PFERR_WRITE_MASK;
 537         int user_fault = error_code & PFERR_USER_MASK;
 538         int fetch_fault = error_code & PFERR_FETCH_MASK;
 539         struct guest_walker walker;
 540         u64 *sptep;
 541         int write_pt = 0;
 542         int r;
 543         pfn_t pfn;
 544         int level = PT_PAGE_TABLE_LEVEL;
 545         unsigned long mmu_seq;
 546
 547         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 548
 549         r = mmu_topup_memory_caches(vcpu);
 550         if (r)
 551                 return r;
 552
 553         /*
 554          * Look up the guest pte for the faulting address.
 555          */
 556         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 557                              fetch_fault);
 558
 559         /*
 560          * The page is not mapped by the guest.  Let the guest handle it.
 561          */
 562         if (!r) {
 563                 pgprintk("%s: guest page fault\n", __func__);
 564                 inject_page_fault(vcpu);
 565                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 566                 return 0;
 567         }
 568
 569         if (walker.level >= PT_DIRECTORY_LEVEL) {
 570                 level = min(walker.level, mapping_level(vcpu, walker.gfn));
 571                 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
 572         }
 573
 574         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 575         smp_rmb();
 576         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
 577
 578         /* mmio */
 579         if (is_error_pfn(pfn))
 580                 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
 581
 582         spin_lock(&vcpu->kvm->mmu_lock);
 583         if (mmu_notifier_retry(vcpu, mmu_seq))
 584                 goto out_unlock;
 585
 586         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
 587         kvm_mmu_free_some_pages(vcpu);
 588         sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 589                              level, &write_pt, pfn);
 590         (void)sptep;
 591         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
 592                  sptep, *sptep, write_pt);
 593
 594         if (!write_pt)
 595                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 596
 597         ++vcpu->stat.pf_fixed;
 598         trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
 599         spin_unlock(&vcpu->kvm->mmu_lock);
 600
 601         return write_pt;
 602
 603 out_unlock:
 604         spin_unlock(&vcpu->kvm->mmu_lock);
 605         kvm_release_pfn_clean(pfn);
 606         return 0;
 607 }
 608
 609 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 610 {
 611         struct kvm_shadow_walk_iterator iterator;
 612         struct kvm_mmu_page *sp;
 613         gpa_t pte_gpa = -1;
 614         int level;
 615         u64 *sptep;
 616         int need_flush = 0;
 617
 618         spin_lock(&vcpu->kvm->mmu_lock);
 619
 620         for_each_shadow_entry(vcpu, gva, iterator) {
 621                 level = iterator.level;
 622                 sptep = iterator.sptep;
 623
 624                 sp = page_header(__pa(sptep));
 625                 if (is_last_spte(*sptep, level)) {
 626                         int offset, shift;
 627
 628                         if (!sp->unsync)
 629                                 break;
 630
 631                         shift = PAGE_SHIFT -
 632                                   (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
 633                         offset = sp->role.quadrant << shift;
 634
 635                         pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
 636                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 637
 638                         if (is_shadow_present_pte(*sptep)) {
 639                                 if (is_large_pte(*sptep))
 640                                         --vcpu->kvm->stat.lpages;
 641                                 drop_spte(vcpu->kvm, sptep,
 642                                           shadow_trap_nonpresent_pte);
 643                                 need_flush = 1;
 644                         } else
 645                                 __set_spte(sptep, shadow_trap_nonpresent_pte);
 646                         break;
 647                 }
 648
 649                 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
 650                         break;
 651         }
 652
 653         if (need_flush)
 654                 kvm_flush_remote_tlbs(vcpu->kvm);
 655
 656         atomic_inc(&vcpu->kvm->arch.invlpg_counter);
 657
 658         spin_unlock(&vcpu->kvm->mmu_lock);
 659
 660         if (pte_gpa == -1)
 661                 return;
 662
 663         if (mmu_topup_memory_caches(vcpu))
 664                 return;
 665         kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
 666 }
 667
 668 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
 669                                u32 *error)
 670 {
 671         struct guest_walker walker;
 672         gpa_t gpa = UNMAPPED_GVA;
 673         int r;
 674
 675         r = FNAME(walk_addr)(&walker, vcpu, vaddr,
 676                              !!(access & PFERR_WRITE_MASK),
 677                              !!(access & PFERR_USER_MASK),
 678                              !!(access & PFERR_FETCH_MASK));
 679
 680         if (r) {
 681                 gpa = gfn_to_gpa(walker.gfn);
 682                 gpa |= vaddr & ~PAGE_MASK;
 683         } else if (error)
 684                 *error = walker.error_code;
 685
 686         return gpa;
 687 }
 688
 689 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
 690                                       u32 access, u32 *error)
 691 {
 692         struct guest_walker walker;
 693         gpa_t gpa = UNMAPPED_GVA;
 694         int r;
 695
 696         r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr,
 697                                     access & PFERR_WRITE_MASK,
 698                                     access & PFERR_USER_MASK,
 699                                     access & PFERR_FETCH_MASK);
 700
 701         if (r) {
 702                 gpa = gfn_to_gpa(walker.gfn);
 703                 gpa |= vaddr & ~PAGE_MASK;
 704         } else if (error)
 705                 *error = walker.error_code;
 706
 707         return gpa;
 708 }
 709
 710 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 711                                  struct kvm_mmu_page *sp)
 712 {
 713         int i, j, offset, r;
 714         pt_element_t pt[256 / sizeof(pt_element_t)];
 715         gpa_t pte_gpa;
 716
 717         if (sp->role.direct
 718             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 719                 nonpaging_prefetch_page(vcpu, sp);
 720                 return;
 721         }
 722
 723         pte_gpa = gfn_to_gpa(sp->gfn);
 724         if (PTTYPE == 32) {
 725                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 726                 pte_gpa += offset * sizeof(pt_element_t);
 727         }
 728
 729         for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
 730                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
 731                 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
 732                 for (j = 0; j < ARRAY_SIZE(pt); ++j)
 733                         if (r || is_present_gpte(pt[j]))
 734                                 sp->spt[i+j] = shadow_trap_nonpresent_pte;
 735                         else
 736                                 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
 737         }
 738 }
 739
 740 /*
 741  * Using the cached information from sp->gfns is safe because:
 742  * - The spte has a reference to the struct page, so the pfn for a given gfn
 743  *   can't change unless all sptes pointing to it are nuked first.
 744  */
 745 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 746                             bool clear_unsync)
 747 {
 748         int i, offset, nr_present;
 749         bool reset_host_protection;
 750         gpa_t first_pte_gpa;
 751
 752         offset = nr_present = 0;
 753
 754         /* direct kvm_mmu_page can not be unsync. */
 755         BUG_ON(sp->role.direct);
 756
 757         if (PTTYPE == 32)
 758                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 759
 760         first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
 761
 762         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
 763                 unsigned pte_access;
 764                 pt_element_t gpte;
 765                 gpa_t pte_gpa;
 766                 gfn_t gfn;
 767
 768                 if (!is_shadow_present_pte(sp->spt[i]))
 769                         continue;
 770
 771                 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
 772
 773                 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 774                                           sizeof(pt_element_t)))
 775                         return -EINVAL;
 776
 777                 gfn = gpte_to_gfn(gpte);
 778                 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)
 779                       || gfn != sp->gfns[i] || !is_present_gpte(gpte)
 780                       || !(gpte & PT_ACCESSED_MASK)) {
 781                         u64 nonpresent;
 782
 783                         if (is_present_gpte(gpte) || !clear_unsync)
 784                                 nonpresent = shadow_trap_nonpresent_pte;
 785                         else
 786                                 nonpresent = shadow_notrap_nonpresent_pte;
 787                         drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
 788                         continue;
 789                 }
 790
 791                 nr_present++;
 792                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 793                 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
 794                         pte_access &= ~ACC_WRITE_MASK;
 795                         reset_host_protection = 0;
 796                 } else {
 797                         reset_host_protection = 1;
 798                 }
 799                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
 800                          is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
 801                          spte_to_pfn(sp->spt[i]), true, false,
 802                          reset_host_protection);
 803         }
 804
 805         return !nr_present;
 806 }
 807
 808 #undef pt_element_t
 809 #undef guest_walker
 810 #undef FNAME
 811 #undef PT_BASE_ADDR_MASK
 812 #undef PT_INDEX
 813 #undef PT_LEVEL_MASK
 814 #undef PT_LVL_ADDR_MASK
 815 #undef PT_LVL_OFFSET_MASK
 816 #undef PT_LEVEL_BITS
 817 #undef PT_MAX_FULL_LEVELS
 818 #undef gpte_to_gfn
 819 #undef gpte_to_gfn_lvl
 820 #undef CMPXCHG