arch/x86/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Avi Kivity   <avi@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  */
  20
  21 /*
  22  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  23  * so the code in this file is compiled twice, once per pte size.
  24  */
  25
  26 #if PTTYPE == 64
  27         #define pt_element_t u64
  28         #define guest_walker guest_walker64
  29         #define FNAME(name) paging##64_##name
  30         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  31         #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
  32         #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
  33         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #define CMPXCHG cmpxchg
  38         #else
  39         #define CMPXCHG cmpxchg64
  40         #define PT_MAX_FULL_LEVELS 2
  41         #endif
  42 #elif PTTYPE == 32
  43         #define pt_element_t u32
  44         #define guest_walker guest_walker32
  45         #define FNAME(name) paging##32_##name
  46         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  47         #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
  48         #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
  49         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  50         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  51         #define PT_MAX_FULL_LEVELS 2
  52         #define CMPXCHG cmpxchg
  53 #else
  54         #error Invalid PTTYPE value
  55 #endif
  56
  57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
  58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
  59
  60 /*
  61  * The guest_walker structure emulates the behavior of the hardware page
  62  * table walker.
  63  */
  64 struct guest_walker {
  65         int level;
  66         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  67         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  68         pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
  69         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  70         unsigned pt_access;
  71         unsigned pte_access;
  72         gfn_t gfn;
  73         struct x86_exception fault;
  74 };
  75
  76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
  77 {
  78         return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
  79 }
  80
  81 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
  82                                pt_element_t __user *ptep_user, unsigned index,
  83                                pt_element_t orig_pte, pt_element_t new_pte)
  84 {
  85         int npages;
  86         pt_element_t ret;
  87         pt_element_t *table;
  88         struct page *page;
  89
  90         npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
  91         /* Check if the user is doing something meaningless. */
  92         if (unlikely(npages != 1))
  93                 return -EFAULT;
  94
  95         table = kmap_atomic(page);
  96         ret = CMPXCHG(&table[index], orig_pte, new_pte);
  97         kunmap_atomic(table);
  98
  99         kvm_release_page_dirty(page);
 100
 101         return (ret != orig_pte);
 102 }
 103
 104 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte,
 105                                    bool last)
 106 {
 107         unsigned access;
 108
 109         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
 110         if (last && !is_dirty_gpte(gpte))
 111                 access &= ~ACC_WRITE_MASK;
 112
 113 #if PTTYPE == 64
 114         if (vcpu->arch.mmu.nx)
 115                 access &= ~(gpte >> PT64_NX_SHIFT);
 116 #endif
 117         return access;
 118 }
 119
 120 static bool FNAME(is_last_gpte)(struct guest_walker *walker,
 121                                 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 122                                 pt_element_t gpte)
 123 {
 124         if (walker->level == PT_PAGE_TABLE_LEVEL)
 125                 return true;
 126
 127         if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) &&
 128             (PTTYPE == 64 || is_pse(vcpu)))
 129                 return true;
 130
 131         if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) &&
 132             (mmu->root_level == PT64_ROOT_LEVEL))
 133                 return true;
 134
 135         return false;
 136 }
 137
 138 /*
 139  * Fetch a guest pte for a guest virtual address
 140  */
 141 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
 142                                     struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 143                                     gva_t addr, u32 access)
 144 {
 145         pt_element_t pte;
 146         pt_element_t __user *uninitialized_var(ptep_user);
 147         gfn_t table_gfn;
 148         unsigned index, pt_access, uninitialized_var(pte_access);
 149         gpa_t pte_gpa;
 150         bool eperm, last_gpte;
 151         int offset;
 152         const int write_fault = access & PFERR_WRITE_MASK;
 153         const int user_fault  = access & PFERR_USER_MASK;
 154         const int fetch_fault = access & PFERR_FETCH_MASK;
 155         u16 errcode = 0;
 156
 157         trace_kvm_mmu_pagetable_walk(addr, access);
 158 retry_walk:
 159         eperm = false;
 160         walker->level = mmu->root_level;
 161         pte           = mmu->get_cr3(vcpu);
 162
 163 #if PTTYPE == 64
 164         if (walker->level == PT32E_ROOT_LEVEL) {
 165                 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
 166                 trace_kvm_mmu_paging_element(pte, walker->level);
 167                 if (!is_present_gpte(pte))
 168                         goto error;
 169                 --walker->level;
 170         }
 171 #endif
 172         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 173                (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
 174
 175         pt_access = ACC_ALL;
 176
 177         for (;;) {
 178                 gfn_t real_gfn;
 179                 unsigned long host_addr;
 180
 181                 index = PT_INDEX(addr, walker->level);
 182
 183                 table_gfn = gpte_to_gfn(pte);
 184                 offset    = index * sizeof(pt_element_t);
 185                 pte_gpa   = gfn_to_gpa(table_gfn) + offset;
 186                 walker->table_gfn[walker->level - 1] = table_gfn;
 187                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 188
 189                 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
 190                                               PFERR_USER_MASK|PFERR_WRITE_MASK);
 191                 if (unlikely(real_gfn == UNMAPPED_GVA))
 192                         goto error;
 193                 real_gfn = gpa_to_gfn(real_gfn);
 194
 195                 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
 196                 if (unlikely(kvm_is_error_hva(host_addr)))
 197                         goto error;
 198
 199                 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
 200                 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
 201                         goto error;
 202
 203                 trace_kvm_mmu_paging_element(pte, walker->level);
 204
 205                 if (unlikely(!is_present_gpte(pte)))
 206                         goto error;
 207
 208                 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
 209                                               walker->level))) {
 210                         errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
 211                         goto error;
 212                 }
 213
 214                 if (!check_write_user_access(vcpu, write_fault, user_fault,
 215                                           pte))
 216                         eperm = true;
 217
 218 #if PTTYPE == 64
 219                 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
 220                         eperm = true;
 221 #endif
 222
 223                 last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte);
 224                 if (last_gpte) {
 225                         pte_access = pt_access &
 226                                      FNAME(gpte_access)(vcpu, pte, true);
 227                         /* check if the kernel is fetching from user page */
 228                         if (unlikely(pte_access & PT_USER_MASK) &&
 229                             kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
 230                                 if (fetch_fault && !user_fault)
 231                                         eperm = true;
 232                 }
 233
 234                 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
 235                         int ret;
 236                         trace_kvm_mmu_set_accessed_bit(table_gfn, index,
 237                                                        sizeof(pte));
 238                         ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
 239                                                   pte, pte|PT_ACCESSED_MASK);
 240                         if (unlikely(ret < 0))
 241                                 goto error;
 242                         else if (ret)
 243                                 goto retry_walk;
 244
 245                         mark_page_dirty(vcpu->kvm, table_gfn);
 246                         pte |= PT_ACCESSED_MASK;
 247                 }
 248
 249                 walker->ptes[walker->level - 1] = pte;
 250
 251                 if (last_gpte) {
 252                         int lvl = walker->level;
 253                         gpa_t real_gpa;
 254                         gfn_t gfn;
 255                         u32 ac;
 256
 257                         gfn = gpte_to_gfn_lvl(pte, lvl);
 258                         gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
 259
 260                         if (PTTYPE == 32 &&
 261                             walker->level == PT_DIRECTORY_LEVEL &&
 262                             is_cpuid_PSE36())
 263                                 gfn += pse36_gfn_delta(pte);
 264
 265                         ac = write_fault | fetch_fault | user_fault;
 266
 267                         real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
 268                                                       ac);
 269                         if (real_gpa == UNMAPPED_GVA)
 270                                 return 0;
 271
 272                         walker->gfn = real_gpa >> PAGE_SHIFT;
 273
 274                         break;
 275                 }
 276
 277                 pt_access &= FNAME(gpte_access)(vcpu, pte, false);
 278                 --walker->level;
 279         }
 280
 281         if (unlikely(eperm)) {
 282                 errcode |= PFERR_PRESENT_MASK;
 283                 goto error;
 284         }
 285
 286         if (write_fault && unlikely(!is_dirty_gpte(pte))) {
 287                 int ret;
 288
 289                 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
 290                 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
 291                                           pte, pte|PT_DIRTY_MASK);
 292                 if (unlikely(ret < 0))
 293                         goto error;
 294                 else if (ret)
 295                         goto retry_walk;
 296
 297                 mark_page_dirty(vcpu->kvm, table_gfn);
 298                 pte |= PT_DIRTY_MASK;
 299                 walker->ptes[walker->level - 1] = pte;
 300         }
 301
 302         walker->pt_access = pt_access;
 303         walker->pte_access = pte_access;
 304         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 305                  __func__, (u64)pte, pte_access, pt_access);
 306         return 1;
 307
 308 error:
 309         errcode |= write_fault | user_fault;
 310         if (fetch_fault && (mmu->nx ||
 311                             kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
 312                 errcode |= PFERR_FETCH_MASK;
 313
 314         walker->fault.vector = PF_VECTOR;
 315         walker->fault.error_code_valid = true;
 316         walker->fault.error_code = errcode;
 317         walker->fault.address = addr;
 318         walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
 319
 320         trace_kvm_mmu_walker_error(walker->fault.error_code);
 321         return 0;
 322 }
 323
 324 static int FNAME(walk_addr)(struct guest_walker *walker,
 325                             struct kvm_vcpu *vcpu, gva_t addr, u32 access)
 326 {
 327         return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
 328                                         access);
 329 }
 330
 331 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
 332                                    struct kvm_vcpu *vcpu, gva_t addr,
 333                                    u32 access)
 334 {
 335         return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
 336                                         addr, access);
 337 }
 338
 339 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
 340                                     struct kvm_mmu_page *sp, u64 *spte,
 341                                     pt_element_t gpte)
 342 {
 343         if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
 344                 goto no_present;
 345
 346         if (!is_present_gpte(gpte))
 347                 goto no_present;
 348
 349         if (!(gpte & PT_ACCESSED_MASK))
 350                 goto no_present;
 351
 352         return false;
 353
 354 no_present:
 355         drop_spte(vcpu->kvm, spte);
 356         return true;
 357 }
 358
 359 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 360                               u64 *spte, const void *pte)
 361 {
 362         pt_element_t gpte;
 363         unsigned pte_access;
 364         pfn_t pfn;
 365
 366         gpte = *(const pt_element_t *)pte;
 367         if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
 368                 return;
 369
 370         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 371         pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true);
 372         pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
 373         if (mmu_invalid_pfn(pfn)) {
 374                 kvm_release_pfn_clean(pfn);
 375                 return;
 376         }
 377
 378         /*
 379          * we call mmu_set_spte() with host_writable = true because that
 380          * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
 381          */
 382         mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
 383                      NULL, PT_PAGE_TABLE_LEVEL,
 384                      gpte_to_gfn(gpte), pfn, true, true);
 385 }
 386
 387 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
 388                                 struct guest_walker *gw, int level)
 389 {
 390         pt_element_t curr_pte;
 391         gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
 392         u64 mask;
 393         int r, index;
 394
 395         if (level == PT_PAGE_TABLE_LEVEL) {
 396                 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
 397                 base_gpa = pte_gpa & ~mask;
 398                 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
 399
 400                 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
 401                                 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
 402                 curr_pte = gw->prefetch_ptes[index];
 403         } else
 404                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
 405                                   &curr_pte, sizeof(curr_pte));
 406
 407         return r || curr_pte != gw->ptes[level - 1];
 408 }
 409
 410 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
 411                                 u64 *sptep)
 412 {
 413         struct kvm_mmu_page *sp;
 414         pt_element_t *gptep = gw->prefetch_ptes;
 415         u64 *spte;
 416         int i;
 417
 418         sp = page_header(__pa(sptep));
 419
 420         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
 421                 return;
 422
 423         if (sp->role.direct)
 424                 return __direct_pte_prefetch(vcpu, sp, sptep);
 425
 426         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
 427         spte = sp->spt + i;
 428
 429         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
 430                 pt_element_t gpte;
 431                 unsigned pte_access;
 432                 gfn_t gfn;
 433                 pfn_t pfn;
 434
 435                 if (spte == sptep)
 436                         continue;
 437
 438                 if (is_shadow_present_pte(*spte))
 439                         continue;
 440
 441                 gpte = gptep[i];
 442
 443                 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
 444                         continue;
 445
 446                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte,
 447                                                                   true);
 448                 gfn = gpte_to_gfn(gpte);
 449                 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
 450                                       pte_access & ACC_WRITE_MASK);
 451                 if (mmu_invalid_pfn(pfn)) {
 452                         kvm_release_pfn_clean(pfn);
 453                         break;
 454                 }
 455
 456                 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
 457                              NULL, PT_PAGE_TABLE_LEVEL, gfn,
 458                              pfn, true, true);
 459         }
 460 }
 461
 462 /*
 463  * Fetch a shadow pte for a specific level in the paging hierarchy.
 464  */
 465 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 466                          struct guest_walker *gw,
 467                          int user_fault, int write_fault, int hlevel,
 468                          int *emulate, pfn_t pfn, bool map_writable,
 469                          bool prefault)
 470 {
 471         unsigned access = gw->pt_access;
 472         struct kvm_mmu_page *sp = NULL;
 473         int top_level;
 474         unsigned direct_access;
 475         struct kvm_shadow_walk_iterator it;
 476
 477         if (!is_present_gpte(gw->ptes[gw->level - 1]))
 478                 return NULL;
 479
 480         direct_access = gw->pte_access;
 481
 482         top_level = vcpu->arch.mmu.root_level;
 483         if (top_level == PT32E_ROOT_LEVEL)
 484                 top_level = PT32_ROOT_LEVEL;
 485         /*
 486          * Verify that the top-level gpte is still there.  Since the page
 487          * is a root page, it is either write protected (and cannot be
 488          * changed from now on) or it is invalid (in which case, we don't
 489          * really care if it changes underneath us after this point).
 490          */
 491         if (FNAME(gpte_changed)(vcpu, gw, top_level))
 492                 goto out_gpte_changed;
 493
 494         for (shadow_walk_init(&it, vcpu, addr);
 495              shadow_walk_okay(&it) && it.level > gw->level;
 496              shadow_walk_next(&it)) {
 497                 gfn_t table_gfn;
 498
 499                 clear_sp_write_flooding_count(it.sptep);
 500                 drop_large_spte(vcpu, it.sptep);
 501
 502                 sp = NULL;
 503                 if (!is_shadow_present_pte(*it.sptep)) {
 504                         table_gfn = gw->table_gfn[it.level - 2];
 505                         sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
 506                                               false, access, it.sptep);
 507                 }
 508
 509                 /*
 510                  * Verify that the gpte in the page we've just write
 511                  * protected is still there.
 512                  */
 513                 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
 514                         goto out_gpte_changed;
 515
 516                 if (sp)
 517                         link_shadow_page(it.sptep, sp);
 518         }
 519
 520         for (;
 521              shadow_walk_okay(&it) && it.level > hlevel;
 522              shadow_walk_next(&it)) {
 523                 gfn_t direct_gfn;
 524
 525                 clear_sp_write_flooding_count(it.sptep);
 526                 validate_direct_spte(vcpu, it.sptep, direct_access);
 527
 528                 drop_large_spte(vcpu, it.sptep);
 529
 530                 if (is_shadow_present_pte(*it.sptep))
 531                         continue;
 532
 533                 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
 534
 535                 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
 536                                       true, direct_access, it.sptep);
 537                 link_shadow_page(it.sptep, sp);
 538         }
 539
 540         clear_sp_write_flooding_count(it.sptep);
 541         mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
 542                      user_fault, write_fault, emulate, it.level,
 543                      gw->gfn, pfn, prefault, map_writable);
 544         FNAME(pte_prefetch)(vcpu, gw, it.sptep);
 545
 546         return it.sptep;
 547
 548 out_gpte_changed:
 549         if (sp)
 550                 kvm_mmu_put_page(sp, it.sptep);
 551         kvm_release_pfn_clean(pfn);
 552         return NULL;
 553 }
 554
 555 /*
 556  * Page fault handler.  There are several causes for a page fault:
 557  *   - there is no shadow pte for the guest pte
 558  *   - write access through a shadow pte marked read only so that we can set
 559  *     the dirty bit
 560  *   - write access to a shadow pte marked read only so we can update the page
 561  *     dirty bitmap, when userspace requests it
 562  *   - mmio access; in this case we will never install a present shadow pte
 563  *   - normal guest page fault due to the guest pte marked not present, not
 564  *     writable, or not executable
 565  *
 566  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 567  *           a negative value on error.
 568  */
 569 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
 570                              bool prefault)
 571 {
 572         int write_fault = error_code & PFERR_WRITE_MASK;
 573         int user_fault = error_code & PFERR_USER_MASK;
 574         struct guest_walker walker;
 575         u64 *sptep;
 576         int emulate = 0;
 577         int r;
 578         pfn_t pfn;
 579         int level = PT_PAGE_TABLE_LEVEL;
 580         int force_pt_level;
 581         unsigned long mmu_seq;
 582         bool map_writable;
 583
 584         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 585
 586         if (unlikely(error_code & PFERR_RSVD_MASK))
 587                 return handle_mmio_page_fault(vcpu, addr, error_code,
 588                                               mmu_is_nested(vcpu));
 589
 590         r = mmu_topup_memory_caches(vcpu);
 591         if (r)
 592                 return r;
 593
 594         /*
 595          * Look up the guest pte for the faulting address.
 596          */
 597         r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
 598
 599         /*
 600          * The page is not mapped by the guest.  Let the guest handle it.
 601          */
 602         if (!r) {
 603                 pgprintk("%s: guest page fault\n", __func__);
 604                 if (!prefault)
 605                         inject_page_fault(vcpu, &walker.fault);
 606
 607                 return 0;
 608         }
 609
 610         if (walker.level >= PT_DIRECTORY_LEVEL)
 611                 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
 612         else
 613                 force_pt_level = 1;
 614         if (!force_pt_level) {
 615                 level = min(walker.level, mapping_level(vcpu, walker.gfn));
 616                 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
 617         }
 618
 619         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 620         smp_rmb();
 621
 622         if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
 623                          &map_writable))
 624                 return 0;
 625
 626         if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
 627                                 walker.gfn, pfn, walker.pte_access, &r))
 628                 return r;
 629
 630         spin_lock(&vcpu->kvm->mmu_lock);
 631         if (mmu_notifier_retry(vcpu, mmu_seq))
 632                 goto out_unlock;
 633
 634         kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
 635         kvm_mmu_free_some_pages(vcpu);
 636         if (!force_pt_level)
 637                 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
 638         sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 639                              level, &emulate, pfn, map_writable, prefault);
 640         (void)sptep;
 641         pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
 642                  sptep, *sptep, emulate);
 643
 644         ++vcpu->stat.pf_fixed;
 645         kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
 646         spin_unlock(&vcpu->kvm->mmu_lock);
 647
 648         return emulate;
 649
 650 out_unlock:
 651         spin_unlock(&vcpu->kvm->mmu_lock);
 652         kvm_release_pfn_clean(pfn);
 653         return 0;
 654 }
 655
 656 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
 657 {
 658         int offset = 0;
 659
 660         WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
 661
 662         if (PTTYPE == 32)
 663                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 664
 665         return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
 666 }
 667
 668 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 669 {
 670         struct kvm_shadow_walk_iterator iterator;
 671         struct kvm_mmu_page *sp;
 672         int level;
 673         u64 *sptep;
 674
 675         vcpu_clear_mmio_info(vcpu, gva);
 676
 677         /*
 678          * No need to check return value here, rmap_can_add() can
 679          * help us to skip pte prefetch later.
 680          */
 681         mmu_topup_memory_caches(vcpu);
 682
 683         spin_lock(&vcpu->kvm->mmu_lock);
 684         for_each_shadow_entry(vcpu, gva, iterator) {
 685                 level = iterator.level;
 686                 sptep = iterator.sptep;
 687
 688                 sp = page_header(__pa(sptep));
 689                 if (is_last_spte(*sptep, level)) {
 690                         pt_element_t gpte;
 691                         gpa_t pte_gpa;
 692
 693                         if (!sp->unsync)
 694                                 break;
 695
 696                         pte_gpa = FNAME(get_level1_sp_gpa)(sp);
 697                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 698
 699                         if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
 700                                 kvm_flush_remote_tlbs(vcpu->kvm);
 701
 702                         if (!rmap_can_add(vcpu))
 703                                 break;
 704
 705                         if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 706                                                   sizeof(pt_element_t)))
 707                                 break;
 708
 709                         FNAME(update_pte)(vcpu, sp, sptep, &gpte);
 710                 }
 711
 712                 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
 713                         break;
 714         }
 715         spin_unlock(&vcpu->kvm->mmu_lock);
 716 }
 717
 718 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
 719                                struct x86_exception *exception)
 720 {
 721         struct guest_walker walker;
 722         gpa_t gpa = UNMAPPED_GVA;
 723         int r;
 724
 725         r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
 726
 727         if (r) {
 728                 gpa = gfn_to_gpa(walker.gfn);
 729                 gpa |= vaddr & ~PAGE_MASK;
 730         } else if (exception)
 731                 *exception = walker.fault;
 732
 733         return gpa;
 734 }
 735
 736 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
 737                                       u32 access,
 738                                       struct x86_exception *exception)
 739 {
 740         struct guest_walker walker;
 741         gpa_t gpa = UNMAPPED_GVA;
 742         int r;
 743
 744         r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
 745
 746         if (r) {
 747                 gpa = gfn_to_gpa(walker.gfn);
 748                 gpa |= vaddr & ~PAGE_MASK;
 749         } else if (exception)
 750                 *exception = walker.fault;
 751
 752         return gpa;
 753 }
 754
 755 /*
 756  * Using the cached information from sp->gfns is safe because:
 757  * - The spte has a reference to the struct page, so the pfn for a given gfn
 758  *   can't change unless all sptes pointing to it are nuked first.
 759  *
 760  * Note:
 761  *   We should flush all tlbs if spte is dropped even though guest is
 762  *   responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
 763  *   and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
 764  *   used by guest then tlbs are not flushed, so guest is allowed to access the
 765  *   freed pages.
 766  *   And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
 767  */
 768 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 769 {
 770         int i, nr_present = 0;
 771         bool host_writable;
 772         gpa_t first_pte_gpa;
 773
 774         /* direct kvm_mmu_page can not be unsync. */
 775         BUG_ON(sp->role.direct);
 776
 777         first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
 778
 779         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
 780                 unsigned pte_access;
 781                 pt_element_t gpte;
 782                 gpa_t pte_gpa;
 783                 gfn_t gfn;
 784
 785                 if (!sp->spt[i])
 786                         continue;
 787
 788                 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
 789
 790                 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 791                                           sizeof(pt_element_t)))
 792                         return -EINVAL;
 793
 794                 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
 795                         vcpu->kvm->tlbs_dirty++;
 796                         continue;
 797                 }
 798
 799                 gfn = gpte_to_gfn(gpte);
 800                 pte_access = sp->role.access;
 801                 pte_access &= FNAME(gpte_access)(vcpu, gpte, true);
 802
 803                 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
 804                         continue;
 805
 806                 if (gfn != sp->gfns[i]) {
 807                         drop_spte(vcpu->kvm, &sp->spt[i]);
 808                         vcpu->kvm->tlbs_dirty++;
 809                         continue;
 810                 }
 811
 812                 nr_present++;
 813
 814                 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
 815
 816                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
 817                          PT_PAGE_TABLE_LEVEL, gfn,
 818                          spte_to_pfn(sp->spt[i]), true, false,
 819                          host_writable);
 820         }
 821
 822         return !nr_present;
 823 }
 824
 825 #undef pt_element_t
 826 #undef guest_walker
 827 #undef FNAME
 828 #undef PT_BASE_ADDR_MASK
 829 #undef PT_INDEX
 830 #undef PT_LVL_ADDR_MASK
 831 #undef PT_LVL_OFFSET_MASK
 832 #undef PT_LEVEL_BITS
 833 #undef PT_MAX_FULL_LEVELS
 834 #undef gpte_to_gfn
 835 #undef gpte_to_gfn_lvl
 836 #undef CMPXCHG