2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
66 static bool erratum_383_found __read_mostly
;
68 static const u32 host_save_user_msrs
[] = {
70 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
73 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
86 /* These are the merged vectors */
89 /* gpa pointers to the real vectors */
93 /* A VMEXIT is required but not yet emulated */
97 * If we vmexit during an instruction emulation we need this to restore
98 * the l1 guest rip after the emulation
100 unsigned long vmexit_rip
;
101 unsigned long vmexit_rsp
;
102 unsigned long vmexit_rax
;
104 /* cache for intercepts of the guest */
107 u32 intercept_exceptions
;
110 /* Nested Paging related state */
114 #define MSRPM_OFFSETS 16
115 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
118 struct kvm_vcpu vcpu
;
120 unsigned long vmcb_pa
;
121 struct svm_cpu_data
*svm_data
;
122 uint64_t asid_generation
;
123 uint64_t sysenter_esp
;
124 uint64_t sysenter_eip
;
128 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
138 struct nested_state nested
;
142 unsigned int3_injected
;
143 unsigned long int3_rip
;
147 #define MSR_INVALID 0xffffffffU
149 static struct svm_direct_access_msrs
{
150 u32 index
; /* Index of the MSR */
151 bool always
; /* True if intercept is always on */
152 } direct_access_msrs
[] = {
153 { .index
= MSR_STAR
, .always
= true },
154 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
156 { .index
= MSR_GS_BASE
, .always
= true },
157 { .index
= MSR_FS_BASE
, .always
= true },
158 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
159 { .index
= MSR_LSTAR
, .always
= true },
160 { .index
= MSR_CSTAR
, .always
= true },
161 { .index
= MSR_SYSCALL_MASK
, .always
= true },
163 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
164 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
165 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
166 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
167 { .index
= MSR_INVALID
, .always
= false },
170 /* enable NPT for AMD64 and X86 with PAE */
171 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
172 static bool npt_enabled
= true;
174 static bool npt_enabled
;
178 module_param(npt
, int, S_IRUGO
);
180 static int nested
= 1;
181 module_param(nested
, int, S_IRUGO
);
183 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
184 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
186 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
187 static int nested_svm_intercept(struct vcpu_svm
*svm
);
188 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
189 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
190 bool has_error_code
, u32 error_code
);
193 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
194 pause filter count */
195 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
196 VMCB_ASID
, /* ASID */
197 VMCB_INTR
, /* int_ctl, int_vector */
198 VMCB_NPT
, /* npt_en, nCR3, gPAT */
199 VMCB_CR
, /* CR0, CR3, CR4, EFER */
200 VMCB_DR
, /* DR6, DR7 */
201 VMCB_DT
, /* GDT, IDT */
202 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
203 VMCB_CR2
, /* CR2 only */
204 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
208 /* TPR and CR2 are always written before VMRUN */
209 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
211 static inline void mark_all_dirty(struct vmcb
*vmcb
)
213 vmcb
->control
.clean
= 0;
216 static inline void mark_all_clean(struct vmcb
*vmcb
)
218 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
219 & ~VMCB_ALWAYS_DIRTY_MASK
;
222 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
224 vmcb
->control
.clean
&= ~(1 << bit
);
227 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
229 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
232 static void recalc_intercepts(struct vcpu_svm
*svm
)
234 struct vmcb_control_area
*c
, *h
;
235 struct nested_state
*g
;
237 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
239 if (!is_guest_mode(&svm
->vcpu
))
242 c
= &svm
->vmcb
->control
;
243 h
= &svm
->nested
.hsave
->control
;
246 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
247 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
248 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
249 c
->intercept
= h
->intercept
| g
->intercept
;
252 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
254 if (is_guest_mode(&svm
->vcpu
))
255 return svm
->nested
.hsave
;
260 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
262 struct vmcb
*vmcb
= get_host_vmcb(svm
);
264 vmcb
->control
.intercept_cr
|= (1U << bit
);
266 recalc_intercepts(svm
);
269 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
271 struct vmcb
*vmcb
= get_host_vmcb(svm
);
273 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
275 recalc_intercepts(svm
);
278 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
280 struct vmcb
*vmcb
= get_host_vmcb(svm
);
282 return vmcb
->control
.intercept_cr
& (1U << bit
);
285 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
287 struct vmcb
*vmcb
= get_host_vmcb(svm
);
289 vmcb
->control
.intercept_dr
|= (1U << bit
);
291 recalc_intercepts(svm
);
294 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
296 struct vmcb
*vmcb
= get_host_vmcb(svm
);
298 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
300 recalc_intercepts(svm
);
303 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
305 struct vmcb
*vmcb
= get_host_vmcb(svm
);
307 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
309 recalc_intercepts(svm
);
312 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
314 struct vmcb
*vmcb
= get_host_vmcb(svm
);
316 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
318 recalc_intercepts(svm
);
321 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
323 struct vmcb
*vmcb
= get_host_vmcb(svm
);
325 vmcb
->control
.intercept
|= (1ULL << bit
);
327 recalc_intercepts(svm
);
330 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
332 struct vmcb
*vmcb
= get_host_vmcb(svm
);
334 vmcb
->control
.intercept
&= ~(1ULL << bit
);
336 recalc_intercepts(svm
);
339 static inline void enable_gif(struct vcpu_svm
*svm
)
341 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
344 static inline void disable_gif(struct vcpu_svm
*svm
)
346 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
349 static inline bool gif_set(struct vcpu_svm
*svm
)
351 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
354 static unsigned long iopm_base
;
356 struct kvm_ldttss_desc
{
359 unsigned base1
:8, type
:5, dpl
:2, p
:1;
360 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
363 } __attribute__((packed
));
365 struct svm_cpu_data
{
371 struct kvm_ldttss_desc
*tss_desc
;
373 struct page
*save_area
;
376 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
377 static uint32_t svm_features
;
379 struct svm_init_data
{
384 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
386 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
387 #define MSRS_RANGE_SIZE 2048
388 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
390 static u32
svm_msrpm_offset(u32 msr
)
395 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
396 if (msr
< msrpm_ranges
[i
] ||
397 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
400 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
401 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
403 /* Now we have the u8 offset - but need the u32 offset */
407 /* MSR not in any range */
411 #define MAX_INST_SIZE 15
413 static inline void clgi(void)
415 asm volatile (__ex(SVM_CLGI
));
418 static inline void stgi(void)
420 asm volatile (__ex(SVM_STGI
));
423 static inline void invlpga(unsigned long addr
, u32 asid
)
425 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
428 static int get_npt_level(void)
431 return PT64_ROOT_LEVEL
;
433 return PT32E_ROOT_LEVEL
;
437 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
439 vcpu
->arch
.efer
= efer
;
440 if (!npt_enabled
&& !(efer
& EFER_LMA
))
443 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
444 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
447 static int is_external_interrupt(u32 info
)
449 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
450 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
453 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
455 struct vcpu_svm
*svm
= to_svm(vcpu
);
458 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
459 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
463 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
465 struct vcpu_svm
*svm
= to_svm(vcpu
);
468 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
470 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
474 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
476 struct vcpu_svm
*svm
= to_svm(vcpu
);
478 if (svm
->vmcb
->control
.next_rip
!= 0)
479 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
481 if (!svm
->next_rip
) {
482 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
484 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
487 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
488 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
489 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
491 kvm_rip_write(vcpu
, svm
->next_rip
);
492 svm_set_interrupt_shadow(vcpu
, 0);
495 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
496 bool has_error_code
, u32 error_code
,
499 struct vcpu_svm
*svm
= to_svm(vcpu
);
502 * If we are within a nested VM we'd better #VMEXIT and let the guest
503 * handle the exception
506 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
509 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
510 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
513 * For guest debugging where we have to reinject #BP if some
514 * INT3 is guest-owned:
515 * Emulate nRIP by moving RIP forward. Will fail if injection
516 * raises a fault that is not intercepted. Still better than
517 * failing in all cases.
519 skip_emulated_instruction(&svm
->vcpu
);
520 rip
= kvm_rip_read(&svm
->vcpu
);
521 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
522 svm
->int3_injected
= rip
- old_rip
;
525 svm
->vmcb
->control
.event_inj
= nr
527 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
528 | SVM_EVTINJ_TYPE_EXEPT
;
529 svm
->vmcb
->control
.event_inj_err
= error_code
;
532 static void svm_init_erratum_383(void)
538 if (!cpu_has_amd_erratum(amd_erratum_383
))
541 /* Use _safe variants to not break nested virtualization */
542 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
548 low
= lower_32_bits(val
);
549 high
= upper_32_bits(val
);
551 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
553 erratum_383_found
= true;
556 static int has_svm(void)
560 if (!cpu_has_svm(&msg
)) {
561 printk(KERN_INFO
"has_svm: %s\n", msg
);
568 static void svm_hardware_disable(void *garbage
)
573 static int svm_hardware_enable(void *garbage
)
576 struct svm_cpu_data
*sd
;
578 struct desc_ptr gdt_descr
;
579 struct desc_struct
*gdt
;
580 int me
= raw_smp_processor_id();
582 rdmsrl(MSR_EFER
, efer
);
583 if (efer
& EFER_SVME
)
587 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
591 sd
= per_cpu(svm_data
, me
);
594 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
599 sd
->asid_generation
= 1;
600 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
601 sd
->next_asid
= sd
->max_asid
+ 1;
603 native_store_gdt(&gdt_descr
);
604 gdt
= (struct desc_struct
*)gdt_descr
.address
;
605 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
607 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
609 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
611 svm_init_erratum_383();
616 static void svm_cpu_uninit(int cpu
)
618 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
623 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
624 __free_page(sd
->save_area
);
628 static int svm_cpu_init(int cpu
)
630 struct svm_cpu_data
*sd
;
633 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
637 sd
->save_area
= alloc_page(GFP_KERNEL
);
642 per_cpu(svm_data
, cpu
) = sd
;
652 static bool valid_msr_intercept(u32 index
)
656 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
657 if (direct_access_msrs
[i
].index
== index
)
663 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
666 u8 bit_read
, bit_write
;
671 * If this warning triggers extend the direct_access_msrs list at the
672 * beginning of the file
674 WARN_ON(!valid_msr_intercept(msr
));
676 offset
= svm_msrpm_offset(msr
);
677 bit_read
= 2 * (msr
& 0x0f);
678 bit_write
= 2 * (msr
& 0x0f) + 1;
681 BUG_ON(offset
== MSR_INVALID
);
683 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
684 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
689 static void svm_vcpu_init_msrpm(u32
*msrpm
)
693 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
695 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
696 if (!direct_access_msrs
[i
].always
)
699 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
703 static void add_msr_offset(u32 offset
)
707 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
709 /* Offset already in list? */
710 if (msrpm_offsets
[i
] == offset
)
713 /* Slot used by another offset? */
714 if (msrpm_offsets
[i
] != MSR_INVALID
)
717 /* Add offset to list */
718 msrpm_offsets
[i
] = offset
;
724 * If this BUG triggers the msrpm_offsets table has an overflow. Just
725 * increase MSRPM_OFFSETS in this case.
730 static void init_msrpm_offsets(void)
734 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
736 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
739 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
740 BUG_ON(offset
== MSR_INVALID
);
742 add_msr_offset(offset
);
746 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
748 u32
*msrpm
= svm
->msrpm
;
750 svm
->vmcb
->control
.lbr_ctl
= 1;
751 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
752 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
753 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
754 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
757 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
759 u32
*msrpm
= svm
->msrpm
;
761 svm
->vmcb
->control
.lbr_ctl
= 0;
762 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
763 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
764 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
765 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
768 static __init
int svm_hardware_setup(void)
771 struct page
*iopm_pages
;
775 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
780 iopm_va
= page_address(iopm_pages
);
781 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
782 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
784 init_msrpm_offsets();
786 if (boot_cpu_has(X86_FEATURE_NX
))
787 kvm_enable_efer_bits(EFER_NX
);
789 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
790 kvm_enable_efer_bits(EFER_FFXSR
);
793 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
794 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
797 for_each_possible_cpu(cpu
) {
798 r
= svm_cpu_init(cpu
);
803 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
805 if (!boot_cpu_has(X86_FEATURE_NPT
))
808 if (npt_enabled
&& !npt
) {
809 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
814 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
822 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
827 static __exit
void svm_hardware_unsetup(void)
831 for_each_possible_cpu(cpu
)
834 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
838 static void init_seg(struct vmcb_seg
*seg
)
841 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
842 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
847 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
850 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
855 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
857 struct vcpu_svm
*svm
= to_svm(vcpu
);
858 u64 g_tsc_offset
= 0;
860 if (is_guest_mode(vcpu
)) {
861 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
862 svm
->nested
.hsave
->control
.tsc_offset
;
863 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
866 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
868 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
871 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
873 struct vcpu_svm
*svm
= to_svm(vcpu
);
875 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
876 if (is_guest_mode(vcpu
))
877 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
878 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
881 static void init_vmcb(struct vcpu_svm
*svm
)
883 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
884 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
886 svm
->vcpu
.fpu_active
= 1;
887 svm
->vcpu
.arch
.hflags
= 0;
889 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
890 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
891 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
892 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
893 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
894 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
895 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
897 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
898 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
899 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
900 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
901 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
902 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
903 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
904 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
906 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
907 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
908 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
909 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
910 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
911 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
912 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
913 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
915 set_exception_intercept(svm
, PF_VECTOR
);
916 set_exception_intercept(svm
, UD_VECTOR
);
917 set_exception_intercept(svm
, MC_VECTOR
);
919 set_intercept(svm
, INTERCEPT_INTR
);
920 set_intercept(svm
, INTERCEPT_NMI
);
921 set_intercept(svm
, INTERCEPT_SMI
);
922 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
923 set_intercept(svm
, INTERCEPT_CPUID
);
924 set_intercept(svm
, INTERCEPT_INVD
);
925 set_intercept(svm
, INTERCEPT_HLT
);
926 set_intercept(svm
, INTERCEPT_INVLPG
);
927 set_intercept(svm
, INTERCEPT_INVLPGA
);
928 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
929 set_intercept(svm
, INTERCEPT_MSR_PROT
);
930 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
931 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
932 set_intercept(svm
, INTERCEPT_VMRUN
);
933 set_intercept(svm
, INTERCEPT_VMMCALL
);
934 set_intercept(svm
, INTERCEPT_VMLOAD
);
935 set_intercept(svm
, INTERCEPT_VMSAVE
);
936 set_intercept(svm
, INTERCEPT_STGI
);
937 set_intercept(svm
, INTERCEPT_CLGI
);
938 set_intercept(svm
, INTERCEPT_SKINIT
);
939 set_intercept(svm
, INTERCEPT_WBINVD
);
940 set_intercept(svm
, INTERCEPT_MONITOR
);
941 set_intercept(svm
, INTERCEPT_MWAIT
);
942 set_intercept(svm
, INTERCEPT_XSETBV
);
944 control
->iopm_base_pa
= iopm_base
;
945 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
946 control
->int_ctl
= V_INTR_MASKING_MASK
;
954 save
->cs
.selector
= 0xf000;
955 /* Executable/Readable Code Segment */
956 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
957 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
958 save
->cs
.limit
= 0xffff;
960 * cs.base should really be 0xffff0000, but vmx can't handle that, so
961 * be consistent with it.
963 * Replace when we have real mode working for vmx.
965 save
->cs
.base
= 0xf0000;
967 save
->gdtr
.limit
= 0xffff;
968 save
->idtr
.limit
= 0xffff;
970 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
971 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
973 svm_set_efer(&svm
->vcpu
, 0);
974 save
->dr6
= 0xffff0ff0;
977 save
->rip
= 0x0000fff0;
978 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
981 * This is the guest-visible cr0 value.
982 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
984 svm
->vcpu
.arch
.cr0
= 0;
985 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
987 save
->cr4
= X86_CR4_PAE
;
991 /* Setup VMCB for Nested Paging */
992 control
->nested_ctl
= 1;
993 clr_intercept(svm
, INTERCEPT_TASK_SWITCH
);
994 clr_intercept(svm
, INTERCEPT_INVLPG
);
995 clr_exception_intercept(svm
, PF_VECTOR
);
996 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
997 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
998 save
->g_pat
= 0x0007040600070406ULL
;
1002 svm
->asid_generation
= 0;
1004 svm
->nested
.vmcb
= 0;
1005 svm
->vcpu
.arch
.hflags
= 0;
1007 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1008 control
->pause_filter_count
= 3000;
1009 set_intercept(svm
, INTERCEPT_PAUSE
);
1012 mark_all_dirty(svm
->vmcb
);
1017 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1019 struct vcpu_svm
*svm
= to_svm(vcpu
);
1023 if (!kvm_vcpu_is_bsp(vcpu
)) {
1024 kvm_rip_write(vcpu
, 0);
1025 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1026 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1028 vcpu
->arch
.regs_avail
= ~0;
1029 vcpu
->arch
.regs_dirty
= ~0;
1034 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1036 struct vcpu_svm
*svm
;
1038 struct page
*msrpm_pages
;
1039 struct page
*hsave_page
;
1040 struct page
*nested_msrpm_pages
;
1043 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1049 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1054 page
= alloc_page(GFP_KERNEL
);
1058 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1062 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1063 if (!nested_msrpm_pages
)
1066 hsave_page
= alloc_page(GFP_KERNEL
);
1070 svm
->nested
.hsave
= page_address(hsave_page
);
1072 svm
->msrpm
= page_address(msrpm_pages
);
1073 svm_vcpu_init_msrpm(svm
->msrpm
);
1075 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1076 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1078 svm
->vmcb
= page_address(page
);
1079 clear_page(svm
->vmcb
);
1080 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1081 svm
->asid_generation
= 0;
1083 kvm_write_tsc(&svm
->vcpu
, 0);
1085 err
= fx_init(&svm
->vcpu
);
1089 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1090 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1091 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1096 __free_page(hsave_page
);
1098 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1100 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1104 kvm_vcpu_uninit(&svm
->vcpu
);
1106 kmem_cache_free(kvm_vcpu_cache
, svm
);
1108 return ERR_PTR(err
);
1111 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1113 struct vcpu_svm
*svm
= to_svm(vcpu
);
1115 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1116 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1117 __free_page(virt_to_page(svm
->nested
.hsave
));
1118 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1119 kvm_vcpu_uninit(vcpu
);
1120 kmem_cache_free(kvm_vcpu_cache
, svm
);
1123 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1125 struct vcpu_svm
*svm
= to_svm(vcpu
);
1128 if (unlikely(cpu
!= vcpu
->cpu
)) {
1129 svm
->asid_generation
= 0;
1130 mark_all_dirty(svm
->vmcb
);
1133 #ifdef CONFIG_X86_64
1134 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1136 savesegment(fs
, svm
->host
.fs
);
1137 savesegment(gs
, svm
->host
.gs
);
1138 svm
->host
.ldt
= kvm_read_ldt();
1140 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1141 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1144 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1146 struct vcpu_svm
*svm
= to_svm(vcpu
);
1149 ++vcpu
->stat
.host_state_reload
;
1150 kvm_load_ldt(svm
->host
.ldt
);
1151 #ifdef CONFIG_X86_64
1152 loadsegment(fs
, svm
->host
.fs
);
1153 load_gs_index(svm
->host
.gs
);
1154 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1156 loadsegment(gs
, svm
->host
.gs
);
1158 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1159 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1162 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1164 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1167 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1169 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1172 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1175 case VCPU_EXREG_PDPTR
:
1176 BUG_ON(!npt_enabled
);
1177 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1184 static void svm_set_vintr(struct vcpu_svm
*svm
)
1186 set_intercept(svm
, INTERCEPT_VINTR
);
1189 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1191 clr_intercept(svm
, INTERCEPT_VINTR
);
1194 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1196 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1199 case VCPU_SREG_CS
: return &save
->cs
;
1200 case VCPU_SREG_DS
: return &save
->ds
;
1201 case VCPU_SREG_ES
: return &save
->es
;
1202 case VCPU_SREG_FS
: return &save
->fs
;
1203 case VCPU_SREG_GS
: return &save
->gs
;
1204 case VCPU_SREG_SS
: return &save
->ss
;
1205 case VCPU_SREG_TR
: return &save
->tr
;
1206 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1212 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1214 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1219 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1220 struct kvm_segment
*var
, int seg
)
1222 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1224 var
->base
= s
->base
;
1225 var
->limit
= s
->limit
;
1226 var
->selector
= s
->selector
;
1227 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1228 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1229 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1230 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1231 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1232 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1233 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1234 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1237 * AMD's VMCB does not have an explicit unusable field, so emulate it
1238 * for cross vendor migration purposes by "not present"
1240 var
->unusable
= !var
->present
|| (var
->type
== 0);
1245 * SVM always stores 0 for the 'G' bit in the CS selector in
1246 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1247 * Intel's VMENTRY has a check on the 'G' bit.
1249 var
->g
= s
->limit
> 0xfffff;
1253 * Work around a bug where the busy flag in the tr selector
1263 * The accessed bit must always be set in the segment
1264 * descriptor cache, although it can be cleared in the
1265 * descriptor, the cached bit always remains at 1. Since
1266 * Intel has a check on this, set it here to support
1267 * cross-vendor migration.
1274 * On AMD CPUs sometimes the DB bit in the segment
1275 * descriptor is left as 1, although the whole segment has
1276 * been made unusable. Clear it here to pass an Intel VMX
1277 * entry check when cross vendor migrating.
1285 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1287 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1292 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1294 struct vcpu_svm
*svm
= to_svm(vcpu
);
1296 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1297 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1300 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1302 struct vcpu_svm
*svm
= to_svm(vcpu
);
1304 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1305 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1306 mark_dirty(svm
->vmcb
, VMCB_DT
);
1309 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1311 struct vcpu_svm
*svm
= to_svm(vcpu
);
1313 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1314 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1317 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1319 struct vcpu_svm
*svm
= to_svm(vcpu
);
1321 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1322 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1323 mark_dirty(svm
->vmcb
, VMCB_DT
);
1326 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1330 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1334 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1338 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1340 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1341 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1343 if (!svm
->vcpu
.fpu_active
)
1344 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1346 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1347 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1349 mark_dirty(svm
->vmcb
, VMCB_CR
);
1351 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1352 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1353 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1355 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1356 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1360 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1362 struct vcpu_svm
*svm
= to_svm(vcpu
);
1364 if (is_guest_mode(vcpu
)) {
1366 * We are here because we run in nested mode, the host kvm
1367 * intercepts cr0 writes but the l1 hypervisor does not.
1368 * But the L1 hypervisor may intercept selective cr0 writes.
1369 * This needs to be checked here.
1371 unsigned long old
, new;
1373 /* Remove bits that would trigger a real cr0 write intercept */
1374 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1375 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1378 /* cr0 write with ts and mp unchanged */
1379 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1380 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1381 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1382 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1383 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1389 #ifdef CONFIG_X86_64
1390 if (vcpu
->arch
.efer
& EFER_LME
) {
1391 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1392 vcpu
->arch
.efer
|= EFER_LMA
;
1393 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1396 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1397 vcpu
->arch
.efer
&= ~EFER_LMA
;
1398 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1402 vcpu
->arch
.cr0
= cr0
;
1405 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1407 if (!vcpu
->fpu_active
)
1410 * re-enable caching here because the QEMU bios
1411 * does not do it - this results in some delay at
1414 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1415 svm
->vmcb
->save
.cr0
= cr0
;
1416 mark_dirty(svm
->vmcb
, VMCB_CR
);
1417 update_cr0_intercept(svm
);
1420 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1422 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1423 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1425 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1426 svm_flush_tlb(vcpu
);
1428 vcpu
->arch
.cr4
= cr4
;
1431 cr4
|= host_cr4_mce
;
1432 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1433 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1436 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1437 struct kvm_segment
*var
, int seg
)
1439 struct vcpu_svm
*svm
= to_svm(vcpu
);
1440 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1442 s
->base
= var
->base
;
1443 s
->limit
= var
->limit
;
1444 s
->selector
= var
->selector
;
1448 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1449 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1450 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1451 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1452 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1453 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1454 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1455 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1457 if (seg
== VCPU_SREG_CS
)
1459 = (svm
->vmcb
->save
.cs
.attrib
1460 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1462 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1465 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1467 struct vcpu_svm
*svm
= to_svm(vcpu
);
1469 clr_exception_intercept(svm
, DB_VECTOR
);
1470 clr_exception_intercept(svm
, BP_VECTOR
);
1472 if (svm
->nmi_singlestep
)
1473 set_exception_intercept(svm
, DB_VECTOR
);
1475 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1476 if (vcpu
->guest_debug
&
1477 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1478 set_exception_intercept(svm
, DB_VECTOR
);
1479 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1480 set_exception_intercept(svm
, BP_VECTOR
);
1482 vcpu
->guest_debug
= 0;
1485 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1487 struct vcpu_svm
*svm
= to_svm(vcpu
);
1489 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1490 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1492 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1494 mark_dirty(svm
->vmcb
, VMCB_DR
);
1496 update_db_intercept(vcpu
);
1499 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1501 if (sd
->next_asid
> sd
->max_asid
) {
1502 ++sd
->asid_generation
;
1504 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1507 svm
->asid_generation
= sd
->asid_generation
;
1508 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1510 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1513 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1515 struct vcpu_svm
*svm
= to_svm(vcpu
);
1517 svm
->vmcb
->save
.dr7
= value
;
1518 mark_dirty(svm
->vmcb
, VMCB_DR
);
1521 static int pf_interception(struct vcpu_svm
*svm
)
1523 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1527 switch (svm
->apf_reason
) {
1529 error_code
= svm
->vmcb
->control
.exit_info_1
;
1531 trace_kvm_page_fault(fault_address
, error_code
);
1532 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1533 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1534 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1535 svm
->vmcb
->control
.insn_bytes
,
1536 svm
->vmcb
->control
.insn_len
);
1538 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1539 svm
->apf_reason
= 0;
1540 local_irq_disable();
1541 kvm_async_pf_task_wait(fault_address
);
1544 case KVM_PV_REASON_PAGE_READY
:
1545 svm
->apf_reason
= 0;
1546 local_irq_disable();
1547 kvm_async_pf_task_wake(fault_address
);
1554 static int db_interception(struct vcpu_svm
*svm
)
1556 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1558 if (!(svm
->vcpu
.guest_debug
&
1559 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1560 !svm
->nmi_singlestep
) {
1561 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1565 if (svm
->nmi_singlestep
) {
1566 svm
->nmi_singlestep
= false;
1567 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1568 svm
->vmcb
->save
.rflags
&=
1569 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1570 update_db_intercept(&svm
->vcpu
);
1573 if (svm
->vcpu
.guest_debug
&
1574 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1575 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1576 kvm_run
->debug
.arch
.pc
=
1577 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1578 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1585 static int bp_interception(struct vcpu_svm
*svm
)
1587 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1589 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1590 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1591 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1595 static int ud_interception(struct vcpu_svm
*svm
)
1599 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1600 if (er
!= EMULATE_DONE
)
1601 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1605 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1607 struct vcpu_svm
*svm
= to_svm(vcpu
);
1609 clr_exception_intercept(svm
, NM_VECTOR
);
1611 svm
->vcpu
.fpu_active
= 1;
1612 update_cr0_intercept(svm
);
1615 static int nm_interception(struct vcpu_svm
*svm
)
1617 svm_fpu_activate(&svm
->vcpu
);
1621 static bool is_erratum_383(void)
1626 if (!erratum_383_found
)
1629 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1633 /* Bit 62 may or may not be set for this mce */
1634 value
&= ~(1ULL << 62);
1636 if (value
!= 0xb600000000010015ULL
)
1639 /* Clear MCi_STATUS registers */
1640 for (i
= 0; i
< 6; ++i
)
1641 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1643 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1647 value
&= ~(1ULL << 2);
1648 low
= lower_32_bits(value
);
1649 high
= upper_32_bits(value
);
1651 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1654 /* Flush tlb to evict multi-match entries */
1660 static void svm_handle_mce(struct vcpu_svm
*svm
)
1662 if (is_erratum_383()) {
1664 * Erratum 383 triggered. Guest state is corrupt so kill the
1667 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1669 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1675 * On an #MC intercept the MCE handler is not called automatically in
1676 * the host. So do it by hand here.
1680 /* not sure if we ever come back to this point */
1685 static int mc_interception(struct vcpu_svm
*svm
)
1690 static int shutdown_interception(struct vcpu_svm
*svm
)
1692 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1695 * VMCB is undefined after a SHUTDOWN intercept
1696 * so reinitialize it.
1698 clear_page(svm
->vmcb
);
1701 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1705 static int io_interception(struct vcpu_svm
*svm
)
1707 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1708 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1709 int size
, in
, string
;
1712 ++svm
->vcpu
.stat
.io_exits
;
1713 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1714 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1716 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
1718 port
= io_info
>> 16;
1719 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1720 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1721 skip_emulated_instruction(&svm
->vcpu
);
1723 return kvm_fast_pio_out(vcpu
, size
, port
);
1726 static int nmi_interception(struct vcpu_svm
*svm
)
1731 static int intr_interception(struct vcpu_svm
*svm
)
1733 ++svm
->vcpu
.stat
.irq_exits
;
1737 static int nop_on_interception(struct vcpu_svm
*svm
)
1742 static int halt_interception(struct vcpu_svm
*svm
)
1744 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1745 skip_emulated_instruction(&svm
->vcpu
);
1746 return kvm_emulate_halt(&svm
->vcpu
);
1749 static int vmmcall_interception(struct vcpu_svm
*svm
)
1751 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1752 skip_emulated_instruction(&svm
->vcpu
);
1753 kvm_emulate_hypercall(&svm
->vcpu
);
1757 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1759 struct vcpu_svm
*svm
= to_svm(vcpu
);
1761 return svm
->nested
.nested_cr3
;
1764 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1767 struct vcpu_svm
*svm
= to_svm(vcpu
);
1769 svm
->vmcb
->control
.nested_cr3
= root
;
1770 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1771 svm_flush_tlb(vcpu
);
1774 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1775 struct x86_exception
*fault
)
1777 struct vcpu_svm
*svm
= to_svm(vcpu
);
1779 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1780 svm
->vmcb
->control
.exit_code_hi
= 0;
1781 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1782 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1784 nested_svm_vmexit(svm
);
1787 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1791 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1793 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1794 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1795 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1796 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1797 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1802 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1804 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1807 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1809 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1810 || !is_paging(&svm
->vcpu
)) {
1811 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1815 if (svm
->vmcb
->save
.cpl
) {
1816 kvm_inject_gp(&svm
->vcpu
, 0);
1823 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1824 bool has_error_code
, u32 error_code
)
1828 if (!is_guest_mode(&svm
->vcpu
))
1831 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1832 svm
->vmcb
->control
.exit_code_hi
= 0;
1833 svm
->vmcb
->control
.exit_info_1
= error_code
;
1834 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1836 vmexit
= nested_svm_intercept(svm
);
1837 if (vmexit
== NESTED_EXIT_DONE
)
1838 svm
->nested
.exit_required
= true;
1843 /* This function returns true if it is save to enable the irq window */
1844 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1846 if (!is_guest_mode(&svm
->vcpu
))
1849 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1852 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1856 * if vmexit was already requested (by intercepted exception
1857 * for instance) do not overwrite it with "external interrupt"
1860 if (svm
->nested
.exit_required
)
1863 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1864 svm
->vmcb
->control
.exit_info_1
= 0;
1865 svm
->vmcb
->control
.exit_info_2
= 0;
1867 if (svm
->nested
.intercept
& 1ULL) {
1869 * The #vmexit can't be emulated here directly because this
1870 * code path runs with irqs and preemtion disabled. A
1871 * #vmexit emulation might sleep. Only signal request for
1874 svm
->nested
.exit_required
= true;
1875 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1882 /* This function returns true if it is save to enable the nmi window */
1883 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1885 if (!is_guest_mode(&svm
->vcpu
))
1888 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1891 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1892 svm
->nested
.exit_required
= true;
1897 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1903 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1904 if (is_error_page(page
))
1912 kvm_release_page_clean(page
);
1913 kvm_inject_gp(&svm
->vcpu
, 0);
1918 static void nested_svm_unmap(struct page
*page
)
1921 kvm_release_page_dirty(page
);
1924 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1930 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1931 return NESTED_EXIT_HOST
;
1933 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1934 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1938 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1941 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1944 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1946 u32 offset
, msr
, value
;
1949 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1950 return NESTED_EXIT_HOST
;
1952 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1953 offset
= svm_msrpm_offset(msr
);
1954 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1955 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1957 if (offset
== MSR_INVALID
)
1958 return NESTED_EXIT_DONE
;
1960 /* Offset is in 32 bit units but need in 8 bit units */
1963 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1964 return NESTED_EXIT_DONE
;
1966 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1969 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1971 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1973 switch (exit_code
) {
1976 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1977 return NESTED_EXIT_HOST
;
1979 /* For now we are always handling NPFs when using them */
1981 return NESTED_EXIT_HOST
;
1983 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1984 /* When we're shadowing, trap PFs, but not async PF */
1985 if (!npt_enabled
&& svm
->apf_reason
== 0)
1986 return NESTED_EXIT_HOST
;
1988 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1989 nm_interception(svm
);
1995 return NESTED_EXIT_CONTINUE
;
1999 * If this function returns true, this #vmexit was already handled
2001 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2003 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2004 int vmexit
= NESTED_EXIT_HOST
;
2006 switch (exit_code
) {
2008 vmexit
= nested_svm_exit_handled_msr(svm
);
2011 vmexit
= nested_svm_intercept_ioio(svm
);
2013 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2014 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2015 if (svm
->nested
.intercept_cr
& bit
)
2016 vmexit
= NESTED_EXIT_DONE
;
2019 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2020 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2021 if (svm
->nested
.intercept_dr
& bit
)
2022 vmexit
= NESTED_EXIT_DONE
;
2025 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2026 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2027 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2028 vmexit
= NESTED_EXIT_DONE
;
2029 /* async page fault always cause vmexit */
2030 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2031 svm
->apf_reason
!= 0)
2032 vmexit
= NESTED_EXIT_DONE
;
2035 case SVM_EXIT_ERR
: {
2036 vmexit
= NESTED_EXIT_DONE
;
2040 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2041 if (svm
->nested
.intercept
& exit_bits
)
2042 vmexit
= NESTED_EXIT_DONE
;
2049 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2053 vmexit
= nested_svm_intercept(svm
);
2055 if (vmexit
== NESTED_EXIT_DONE
)
2056 nested_svm_vmexit(svm
);
2061 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2063 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2064 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2066 dst
->intercept_cr
= from
->intercept_cr
;
2067 dst
->intercept_dr
= from
->intercept_dr
;
2068 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2069 dst
->intercept
= from
->intercept
;
2070 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2071 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2072 dst
->tsc_offset
= from
->tsc_offset
;
2073 dst
->asid
= from
->asid
;
2074 dst
->tlb_ctl
= from
->tlb_ctl
;
2075 dst
->int_ctl
= from
->int_ctl
;
2076 dst
->int_vector
= from
->int_vector
;
2077 dst
->int_state
= from
->int_state
;
2078 dst
->exit_code
= from
->exit_code
;
2079 dst
->exit_code_hi
= from
->exit_code_hi
;
2080 dst
->exit_info_1
= from
->exit_info_1
;
2081 dst
->exit_info_2
= from
->exit_info_2
;
2082 dst
->exit_int_info
= from
->exit_int_info
;
2083 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2084 dst
->nested_ctl
= from
->nested_ctl
;
2085 dst
->event_inj
= from
->event_inj
;
2086 dst
->event_inj_err
= from
->event_inj_err
;
2087 dst
->nested_cr3
= from
->nested_cr3
;
2088 dst
->lbr_ctl
= from
->lbr_ctl
;
2091 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2093 struct vmcb
*nested_vmcb
;
2094 struct vmcb
*hsave
= svm
->nested
.hsave
;
2095 struct vmcb
*vmcb
= svm
->vmcb
;
2098 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2099 vmcb
->control
.exit_info_1
,
2100 vmcb
->control
.exit_info_2
,
2101 vmcb
->control
.exit_int_info
,
2102 vmcb
->control
.exit_int_info_err
);
2104 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2108 /* Exit Guest-Mode */
2109 leave_guest_mode(&svm
->vcpu
);
2110 svm
->nested
.vmcb
= 0;
2112 /* Give the current vmcb to the guest */
2115 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2116 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2117 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2118 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2119 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2120 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2121 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2122 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2123 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2124 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2125 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2126 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
2127 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2128 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2129 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2130 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2131 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2132 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2134 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2135 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2136 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2137 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2138 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2139 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2140 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2141 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2142 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2143 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2146 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2147 * to make sure that we do not lose injected events. So check event_inj
2148 * here and copy it to exit_int_info if it is valid.
2149 * Exit_int_info and event_inj can't be both valid because the case
2150 * below only happens on a VMRUN instruction intercept which has
2151 * no valid exit_int_info set.
2153 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2154 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2156 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2157 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2160 nested_vmcb
->control
.tlb_ctl
= 0;
2161 nested_vmcb
->control
.event_inj
= 0;
2162 nested_vmcb
->control
.event_inj_err
= 0;
2164 /* We always set V_INTR_MASKING and remember the old value in hflags */
2165 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2166 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2168 /* Restore the original control entries */
2169 copy_vmcb_control_area(vmcb
, hsave
);
2171 kvm_clear_exception_queue(&svm
->vcpu
);
2172 kvm_clear_interrupt_queue(&svm
->vcpu
);
2174 svm
->nested
.nested_cr3
= 0;
2176 /* Restore selected save entries */
2177 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2178 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2179 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2180 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2181 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2182 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2183 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
2184 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2185 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2186 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2188 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2189 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2191 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2193 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2194 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2195 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2196 svm
->vmcb
->save
.dr7
= 0;
2197 svm
->vmcb
->save
.cpl
= 0;
2198 svm
->vmcb
->control
.exit_int_info
= 0;
2200 mark_all_dirty(svm
->vmcb
);
2202 nested_svm_unmap(page
);
2204 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2205 kvm_mmu_reset_context(&svm
->vcpu
);
2206 kvm_mmu_load(&svm
->vcpu
);
2211 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2214 * This function merges the msr permission bitmaps of kvm and the
2215 * nested vmcb. It is omptimized in that it only merges the parts where
2216 * the kvm msr permission bitmap may contain zero bits
2220 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2223 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2227 if (msrpm_offsets
[i
] == 0xffffffff)
2230 p
= msrpm_offsets
[i
];
2231 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2233 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2236 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2239 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2244 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2246 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2249 if (vmcb
->control
.asid
== 0)
2252 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2258 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2260 struct vmcb
*nested_vmcb
;
2261 struct vmcb
*hsave
= svm
->nested
.hsave
;
2262 struct vmcb
*vmcb
= svm
->vmcb
;
2266 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2268 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2272 if (!nested_vmcb_checks(nested_vmcb
)) {
2273 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2274 nested_vmcb
->control
.exit_code_hi
= 0;
2275 nested_vmcb
->control
.exit_info_1
= 0;
2276 nested_vmcb
->control
.exit_info_2
= 0;
2278 nested_svm_unmap(page
);
2283 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2284 nested_vmcb
->save
.rip
,
2285 nested_vmcb
->control
.int_ctl
,
2286 nested_vmcb
->control
.event_inj
,
2287 nested_vmcb
->control
.nested_ctl
);
2289 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2290 nested_vmcb
->control
.intercept_cr
>> 16,
2291 nested_vmcb
->control
.intercept_exceptions
,
2292 nested_vmcb
->control
.intercept
);
2294 /* Clear internal status */
2295 kvm_clear_exception_queue(&svm
->vcpu
);
2296 kvm_clear_interrupt_queue(&svm
->vcpu
);
2299 * Save the old vmcb, so we don't need to pick what we save, but can
2300 * restore everything when a VMEXIT occurs
2302 hsave
->save
.es
= vmcb
->save
.es
;
2303 hsave
->save
.cs
= vmcb
->save
.cs
;
2304 hsave
->save
.ss
= vmcb
->save
.ss
;
2305 hsave
->save
.ds
= vmcb
->save
.ds
;
2306 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2307 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2308 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2309 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2310 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2311 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2312 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2313 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2314 hsave
->save
.rax
= vmcb
->save
.rax
;
2316 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2318 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2320 copy_vmcb_control_area(hsave
, vmcb
);
2322 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2323 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2325 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2327 if (nested_vmcb
->control
.nested_ctl
) {
2328 kvm_mmu_unload(&svm
->vcpu
);
2329 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2330 nested_svm_init_mmu_context(&svm
->vcpu
);
2333 /* Load the nested guest state */
2334 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2335 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2336 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2337 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2338 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2339 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2340 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2341 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2342 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2343 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2345 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2346 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2348 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2350 /* Guest paging mode is active - reset mmu */
2351 kvm_mmu_reset_context(&svm
->vcpu
);
2353 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2354 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2355 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2356 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2358 /* In case we don't even reach vcpu_run, the fields are not updated */
2359 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2360 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2361 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2362 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2363 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2364 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2366 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2367 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2369 /* cache intercepts */
2370 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2371 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2372 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2373 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2375 svm_flush_tlb(&svm
->vcpu
);
2376 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2377 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2378 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2380 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2382 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2383 /* We only want the cr8 intercept bits of the guest */
2384 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2385 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2388 /* We don't want to see VMMCALLs from a nested guest */
2389 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2391 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2392 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2393 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2394 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2395 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2396 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2398 nested_svm_unmap(page
);
2400 /* Enter Guest-Mode */
2401 enter_guest_mode(&svm
->vcpu
);
2404 * Merge guest and host intercepts - must be called with vcpu in
2405 * guest-mode to take affect here
2407 recalc_intercepts(svm
);
2409 svm
->nested
.vmcb
= vmcb_gpa
;
2413 mark_all_dirty(svm
->vmcb
);
2418 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2420 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2421 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2422 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2423 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2424 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2425 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2426 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2427 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2428 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2429 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2430 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2431 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2434 static int vmload_interception(struct vcpu_svm
*svm
)
2436 struct vmcb
*nested_vmcb
;
2439 if (nested_svm_check_permissions(svm
))
2442 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2443 skip_emulated_instruction(&svm
->vcpu
);
2445 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2449 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2450 nested_svm_unmap(page
);
2455 static int vmsave_interception(struct vcpu_svm
*svm
)
2457 struct vmcb
*nested_vmcb
;
2460 if (nested_svm_check_permissions(svm
))
2463 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2464 skip_emulated_instruction(&svm
->vcpu
);
2466 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2470 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2471 nested_svm_unmap(page
);
2476 static int vmrun_interception(struct vcpu_svm
*svm
)
2478 if (nested_svm_check_permissions(svm
))
2481 /* Save rip after vmrun instruction */
2482 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2484 if (!nested_svm_vmrun(svm
))
2487 if (!nested_svm_vmrun_msrpm(svm
))
2494 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2495 svm
->vmcb
->control
.exit_code_hi
= 0;
2496 svm
->vmcb
->control
.exit_info_1
= 0;
2497 svm
->vmcb
->control
.exit_info_2
= 0;
2499 nested_svm_vmexit(svm
);
2504 static int stgi_interception(struct vcpu_svm
*svm
)
2506 if (nested_svm_check_permissions(svm
))
2509 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2510 skip_emulated_instruction(&svm
->vcpu
);
2511 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2518 static int clgi_interception(struct vcpu_svm
*svm
)
2520 if (nested_svm_check_permissions(svm
))
2523 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2524 skip_emulated_instruction(&svm
->vcpu
);
2528 /* After a CLGI no interrupts should come */
2529 svm_clear_vintr(svm
);
2530 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2532 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2537 static int invlpga_interception(struct vcpu_svm
*svm
)
2539 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2541 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2542 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2544 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2545 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2547 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2548 skip_emulated_instruction(&svm
->vcpu
);
2552 static int skinit_interception(struct vcpu_svm
*svm
)
2554 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2556 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2560 static int xsetbv_interception(struct vcpu_svm
*svm
)
2562 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2563 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2565 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2566 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2567 skip_emulated_instruction(&svm
->vcpu
);
2573 static int invalid_op_interception(struct vcpu_svm
*svm
)
2575 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2579 static int task_switch_interception(struct vcpu_svm
*svm
)
2583 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2584 SVM_EXITINTINFO_TYPE_MASK
;
2585 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2587 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2589 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2590 bool has_error_code
= false;
2593 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2595 if (svm
->vmcb
->control
.exit_info_2
&
2596 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2597 reason
= TASK_SWITCH_IRET
;
2598 else if (svm
->vmcb
->control
.exit_info_2
&
2599 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2600 reason
= TASK_SWITCH_JMP
;
2602 reason
= TASK_SWITCH_GATE
;
2604 reason
= TASK_SWITCH_CALL
;
2606 if (reason
== TASK_SWITCH_GATE
) {
2608 case SVM_EXITINTINFO_TYPE_NMI
:
2609 svm
->vcpu
.arch
.nmi_injected
= false;
2611 case SVM_EXITINTINFO_TYPE_EXEPT
:
2612 if (svm
->vmcb
->control
.exit_info_2
&
2613 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2614 has_error_code
= true;
2616 (u32
)svm
->vmcb
->control
.exit_info_2
;
2618 kvm_clear_exception_queue(&svm
->vcpu
);
2620 case SVM_EXITINTINFO_TYPE_INTR
:
2621 kvm_clear_interrupt_queue(&svm
->vcpu
);
2628 if (reason
!= TASK_SWITCH_GATE
||
2629 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2630 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2631 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2632 skip_emulated_instruction(&svm
->vcpu
);
2634 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2635 has_error_code
, error_code
) == EMULATE_FAIL
) {
2636 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2637 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2638 svm
->vcpu
.run
->internal
.ndata
= 0;
2644 static int cpuid_interception(struct vcpu_svm
*svm
)
2646 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2647 kvm_emulate_cpuid(&svm
->vcpu
);
2651 static int iret_interception(struct vcpu_svm
*svm
)
2653 ++svm
->vcpu
.stat
.nmi_window_exits
;
2654 clr_intercept(svm
, INTERCEPT_IRET
);
2655 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2659 static int invlpg_interception(struct vcpu_svm
*svm
)
2661 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2662 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2664 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2665 skip_emulated_instruction(&svm
->vcpu
);
2669 static int emulate_on_interception(struct vcpu_svm
*svm
)
2671 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2674 #define CR_VALID (1ULL << 63)
2676 static int cr_interception(struct vcpu_svm
*svm
)
2682 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2683 return emulate_on_interception(svm
);
2685 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2686 return emulate_on_interception(svm
);
2688 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2689 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2692 if (cr
>= 16) { /* mov to cr */
2694 val
= kvm_register_read(&svm
->vcpu
, reg
);
2697 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2700 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2703 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2706 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2709 WARN(1, "unhandled write to CR%d", cr
);
2710 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2713 } else { /* mov from cr */
2716 val
= kvm_read_cr0(&svm
->vcpu
);
2719 val
= svm
->vcpu
.arch
.cr2
;
2722 val
= kvm_read_cr3(&svm
->vcpu
);
2725 val
= kvm_read_cr4(&svm
->vcpu
);
2728 val
= kvm_get_cr8(&svm
->vcpu
);
2731 WARN(1, "unhandled read from CR%d", cr
);
2732 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2735 kvm_register_write(&svm
->vcpu
, reg
, val
);
2737 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2742 static int cr0_write_interception(struct vcpu_svm
*svm
)
2744 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2747 r
= cr_interception(svm
);
2749 if (svm
->nested
.vmexit_rip
) {
2750 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2751 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2752 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2753 svm
->nested
.vmexit_rip
= 0;
2759 static int dr_interception(struct vcpu_svm
*svm
)
2765 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2766 return emulate_on_interception(svm
);
2768 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2769 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2771 if (dr
>= 16) { /* mov to DRn */
2772 val
= kvm_register_read(&svm
->vcpu
, reg
);
2773 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
2775 err
= kvm_get_dr(&svm
->vcpu
, dr
, &val
);
2777 kvm_register_write(&svm
->vcpu
, reg
, val
);
2783 static int cr8_write_interception(struct vcpu_svm
*svm
)
2785 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2788 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2789 /* instruction emulation calls kvm_set_cr8() */
2790 r
= cr_interception(svm
);
2791 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2792 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2795 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2797 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2801 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2803 struct vcpu_svm
*svm
= to_svm(vcpu
);
2806 case MSR_IA32_TSC
: {
2807 struct vmcb
*vmcb
= get_host_vmcb(svm
);
2809 *data
= vmcb
->control
.tsc_offset
+ native_read_tsc();
2813 *data
= svm
->vmcb
->save
.star
;
2815 #ifdef CONFIG_X86_64
2817 *data
= svm
->vmcb
->save
.lstar
;
2820 *data
= svm
->vmcb
->save
.cstar
;
2822 case MSR_KERNEL_GS_BASE
:
2823 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2825 case MSR_SYSCALL_MASK
:
2826 *data
= svm
->vmcb
->save
.sfmask
;
2829 case MSR_IA32_SYSENTER_CS
:
2830 *data
= svm
->vmcb
->save
.sysenter_cs
;
2832 case MSR_IA32_SYSENTER_EIP
:
2833 *data
= svm
->sysenter_eip
;
2835 case MSR_IA32_SYSENTER_ESP
:
2836 *data
= svm
->sysenter_esp
;
2839 * Nobody will change the following 5 values in the VMCB so we can
2840 * safely return them on rdmsr. They will always be 0 until LBRV is
2843 case MSR_IA32_DEBUGCTLMSR
:
2844 *data
= svm
->vmcb
->save
.dbgctl
;
2846 case MSR_IA32_LASTBRANCHFROMIP
:
2847 *data
= svm
->vmcb
->save
.br_from
;
2849 case MSR_IA32_LASTBRANCHTOIP
:
2850 *data
= svm
->vmcb
->save
.br_to
;
2852 case MSR_IA32_LASTINTFROMIP
:
2853 *data
= svm
->vmcb
->save
.last_excp_from
;
2855 case MSR_IA32_LASTINTTOIP
:
2856 *data
= svm
->vmcb
->save
.last_excp_to
;
2858 case MSR_VM_HSAVE_PA
:
2859 *data
= svm
->nested
.hsave_msr
;
2862 *data
= svm
->nested
.vm_cr_msr
;
2864 case MSR_IA32_UCODE_REV
:
2868 return kvm_get_msr_common(vcpu
, ecx
, data
);
2873 static int rdmsr_interception(struct vcpu_svm
*svm
)
2875 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2878 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2879 trace_kvm_msr_read_ex(ecx
);
2880 kvm_inject_gp(&svm
->vcpu
, 0);
2882 trace_kvm_msr_read(ecx
, data
);
2884 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2885 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2886 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2887 skip_emulated_instruction(&svm
->vcpu
);
2892 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2894 struct vcpu_svm
*svm
= to_svm(vcpu
);
2895 int svm_dis
, chg_mask
;
2897 if (data
& ~SVM_VM_CR_VALID_MASK
)
2900 chg_mask
= SVM_VM_CR_VALID_MASK
;
2902 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2903 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2905 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2906 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2908 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2910 /* check for svm_disable while efer.svme is set */
2911 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2917 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2919 struct vcpu_svm
*svm
= to_svm(vcpu
);
2923 kvm_write_tsc(vcpu
, data
);
2926 svm
->vmcb
->save
.star
= data
;
2928 #ifdef CONFIG_X86_64
2930 svm
->vmcb
->save
.lstar
= data
;
2933 svm
->vmcb
->save
.cstar
= data
;
2935 case MSR_KERNEL_GS_BASE
:
2936 svm
->vmcb
->save
.kernel_gs_base
= data
;
2938 case MSR_SYSCALL_MASK
:
2939 svm
->vmcb
->save
.sfmask
= data
;
2942 case MSR_IA32_SYSENTER_CS
:
2943 svm
->vmcb
->save
.sysenter_cs
= data
;
2945 case MSR_IA32_SYSENTER_EIP
:
2946 svm
->sysenter_eip
= data
;
2947 svm
->vmcb
->save
.sysenter_eip
= data
;
2949 case MSR_IA32_SYSENTER_ESP
:
2950 svm
->sysenter_esp
= data
;
2951 svm
->vmcb
->save
.sysenter_esp
= data
;
2953 case MSR_IA32_DEBUGCTLMSR
:
2954 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2955 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2959 if (data
& DEBUGCTL_RESERVED_BITS
)
2962 svm
->vmcb
->save
.dbgctl
= data
;
2963 mark_dirty(svm
->vmcb
, VMCB_LBR
);
2964 if (data
& (1ULL<<0))
2965 svm_enable_lbrv(svm
);
2967 svm_disable_lbrv(svm
);
2969 case MSR_VM_HSAVE_PA
:
2970 svm
->nested
.hsave_msr
= data
;
2973 return svm_set_vm_cr(vcpu
, data
);
2975 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2978 return kvm_set_msr_common(vcpu
, ecx
, data
);
2983 static int wrmsr_interception(struct vcpu_svm
*svm
)
2985 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2986 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2987 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2990 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2991 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2992 trace_kvm_msr_write_ex(ecx
, data
);
2993 kvm_inject_gp(&svm
->vcpu
, 0);
2995 trace_kvm_msr_write(ecx
, data
);
2996 skip_emulated_instruction(&svm
->vcpu
);
3001 static int msr_interception(struct vcpu_svm
*svm
)
3003 if (svm
->vmcb
->control
.exit_info_1
)
3004 return wrmsr_interception(svm
);
3006 return rdmsr_interception(svm
);
3009 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3011 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3013 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3014 svm_clear_vintr(svm
);
3015 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3016 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3018 * If the user space waits to inject interrupts, exit as soon as
3021 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
3022 kvm_run
->request_interrupt_window
&&
3023 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
3024 ++svm
->vcpu
.stat
.irq_window_exits
;
3025 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3032 static int pause_interception(struct vcpu_svm
*svm
)
3034 kvm_vcpu_on_spin(&(svm
->vcpu
));
3038 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3039 [SVM_EXIT_READ_CR0
] = cr_interception
,
3040 [SVM_EXIT_READ_CR3
] = cr_interception
,
3041 [SVM_EXIT_READ_CR4
] = cr_interception
,
3042 [SVM_EXIT_READ_CR8
] = cr_interception
,
3043 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
3044 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
3045 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3046 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3047 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3048 [SVM_EXIT_READ_DR0
] = dr_interception
,
3049 [SVM_EXIT_READ_DR1
] = dr_interception
,
3050 [SVM_EXIT_READ_DR2
] = dr_interception
,
3051 [SVM_EXIT_READ_DR3
] = dr_interception
,
3052 [SVM_EXIT_READ_DR4
] = dr_interception
,
3053 [SVM_EXIT_READ_DR5
] = dr_interception
,
3054 [SVM_EXIT_READ_DR6
] = dr_interception
,
3055 [SVM_EXIT_READ_DR7
] = dr_interception
,
3056 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3057 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3058 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3059 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3060 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3061 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3062 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3063 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3064 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3065 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3066 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3067 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3068 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3069 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3070 [SVM_EXIT_INTR
] = intr_interception
,
3071 [SVM_EXIT_NMI
] = nmi_interception
,
3072 [SVM_EXIT_SMI
] = nop_on_interception
,
3073 [SVM_EXIT_INIT
] = nop_on_interception
,
3074 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3075 [SVM_EXIT_CPUID
] = cpuid_interception
,
3076 [SVM_EXIT_IRET
] = iret_interception
,
3077 [SVM_EXIT_INVD
] = emulate_on_interception
,
3078 [SVM_EXIT_PAUSE
] = pause_interception
,
3079 [SVM_EXIT_HLT
] = halt_interception
,
3080 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3081 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3082 [SVM_EXIT_IOIO
] = io_interception
,
3083 [SVM_EXIT_MSR
] = msr_interception
,
3084 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3085 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3086 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3087 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3088 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3089 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3090 [SVM_EXIT_STGI
] = stgi_interception
,
3091 [SVM_EXIT_CLGI
] = clgi_interception
,
3092 [SVM_EXIT_SKINIT
] = skinit_interception
,
3093 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
3094 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
3095 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
3096 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3097 [SVM_EXIT_NPF
] = pf_interception
,
3100 void dump_vmcb(struct kvm_vcpu
*vcpu
)
3102 struct vcpu_svm
*svm
= to_svm(vcpu
);
3103 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3104 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3106 pr_err("VMCB Control Area:\n");
3107 pr_err("cr_read: %04x\n", control
->intercept_cr
& 0xffff);
3108 pr_err("cr_write: %04x\n", control
->intercept_cr
>> 16);
3109 pr_err("dr_read: %04x\n", control
->intercept_dr
& 0xffff);
3110 pr_err("dr_write: %04x\n", control
->intercept_dr
>> 16);
3111 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
3112 pr_err("intercepts: %016llx\n", control
->intercept
);
3113 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
3114 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
3115 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
3116 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
3117 pr_err("asid: %d\n", control
->asid
);
3118 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
3119 pr_err("int_ctl: %08x\n", control
->int_ctl
);
3120 pr_err("int_vector: %08x\n", control
->int_vector
);
3121 pr_err("int_state: %08x\n", control
->int_state
);
3122 pr_err("exit_code: %08x\n", control
->exit_code
);
3123 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
3124 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
3125 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
3126 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
3127 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
3128 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
3129 pr_err("event_inj: %08x\n", control
->event_inj
);
3130 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
3131 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
3132 pr_err("next_rip: %016llx\n", control
->next_rip
);
3133 pr_err("VMCB State Save Area:\n");
3134 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3135 save
->es
.selector
, save
->es
.attrib
,
3136 save
->es
.limit
, save
->es
.base
);
3137 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3138 save
->cs
.selector
, save
->cs
.attrib
,
3139 save
->cs
.limit
, save
->cs
.base
);
3140 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3141 save
->ss
.selector
, save
->ss
.attrib
,
3142 save
->ss
.limit
, save
->ss
.base
);
3143 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3144 save
->ds
.selector
, save
->ds
.attrib
,
3145 save
->ds
.limit
, save
->ds
.base
);
3146 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3147 save
->fs
.selector
, save
->fs
.attrib
,
3148 save
->fs
.limit
, save
->fs
.base
);
3149 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3150 save
->gs
.selector
, save
->gs
.attrib
,
3151 save
->gs
.limit
, save
->gs
.base
);
3152 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3153 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3154 save
->gdtr
.limit
, save
->gdtr
.base
);
3155 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3156 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3157 save
->ldtr
.limit
, save
->ldtr
.base
);
3158 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3159 save
->idtr
.selector
, save
->idtr
.attrib
,
3160 save
->idtr
.limit
, save
->idtr
.base
);
3161 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3162 save
->tr
.selector
, save
->tr
.attrib
,
3163 save
->tr
.limit
, save
->tr
.base
);
3164 pr_err("cpl: %d efer: %016llx\n",
3165 save
->cpl
, save
->efer
);
3166 pr_err("cr0: %016llx cr2: %016llx\n",
3167 save
->cr0
, save
->cr2
);
3168 pr_err("cr3: %016llx cr4: %016llx\n",
3169 save
->cr3
, save
->cr4
);
3170 pr_err("dr6: %016llx dr7: %016llx\n",
3171 save
->dr6
, save
->dr7
);
3172 pr_err("rip: %016llx rflags: %016llx\n",
3173 save
->rip
, save
->rflags
);
3174 pr_err("rsp: %016llx rax: %016llx\n",
3175 save
->rsp
, save
->rax
);
3176 pr_err("star: %016llx lstar: %016llx\n",
3177 save
->star
, save
->lstar
);
3178 pr_err("cstar: %016llx sfmask: %016llx\n",
3179 save
->cstar
, save
->sfmask
);
3180 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3181 save
->kernel_gs_base
, save
->sysenter_cs
);
3182 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3183 save
->sysenter_esp
, save
->sysenter_eip
);
3184 pr_err("gpat: %016llx dbgctl: %016llx\n",
3185 save
->g_pat
, save
->dbgctl
);
3186 pr_err("br_from: %016llx br_to: %016llx\n",
3187 save
->br_from
, save
->br_to
);
3188 pr_err("excp_from: %016llx excp_to: %016llx\n",
3189 save
->last_excp_from
, save
->last_excp_to
);
3193 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3195 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3197 *info1
= control
->exit_info_1
;
3198 *info2
= control
->exit_info_2
;
3201 static int handle_exit(struct kvm_vcpu
*vcpu
)
3203 struct vcpu_svm
*svm
= to_svm(vcpu
);
3204 struct kvm_run
*kvm_run
= vcpu
->run
;
3205 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3207 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3209 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3210 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3212 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3214 if (unlikely(svm
->nested
.exit_required
)) {
3215 nested_svm_vmexit(svm
);
3216 svm
->nested
.exit_required
= false;
3221 if (is_guest_mode(vcpu
)) {
3224 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3225 svm
->vmcb
->control
.exit_info_1
,
3226 svm
->vmcb
->control
.exit_info_2
,
3227 svm
->vmcb
->control
.exit_int_info
,
3228 svm
->vmcb
->control
.exit_int_info_err
);
3230 vmexit
= nested_svm_exit_special(svm
);
3232 if (vmexit
== NESTED_EXIT_CONTINUE
)
3233 vmexit
= nested_svm_exit_handled(svm
);
3235 if (vmexit
== NESTED_EXIT_DONE
)
3239 svm_complete_interrupts(svm
);
3241 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3242 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3243 kvm_run
->fail_entry
.hardware_entry_failure_reason
3244 = svm
->vmcb
->control
.exit_code
;
3245 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3250 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3251 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3252 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3253 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3254 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3256 __func__
, svm
->vmcb
->control
.exit_int_info
,
3259 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3260 || !svm_exit_handlers
[exit_code
]) {
3261 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3262 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3266 return svm_exit_handlers
[exit_code
](svm
);
3269 static void reload_tss(struct kvm_vcpu
*vcpu
)
3271 int cpu
= raw_smp_processor_id();
3273 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3274 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3278 static void pre_svm_run(struct vcpu_svm
*svm
)
3280 int cpu
= raw_smp_processor_id();
3282 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3284 /* FIXME: handle wraparound of asid_generation */
3285 if (svm
->asid_generation
!= sd
->asid_generation
)
3289 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3291 struct vcpu_svm
*svm
= to_svm(vcpu
);
3293 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3294 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3295 set_intercept(svm
, INTERCEPT_IRET
);
3296 ++vcpu
->stat
.nmi_injections
;
3299 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3301 struct vmcb_control_area
*control
;
3303 control
= &svm
->vmcb
->control
;
3304 control
->int_vector
= irq
;
3305 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3306 control
->int_ctl
|= V_IRQ_MASK
|
3307 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3308 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3311 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3313 struct vcpu_svm
*svm
= to_svm(vcpu
);
3315 BUG_ON(!(gif_set(svm
)));
3317 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3318 ++vcpu
->stat
.irq_injections
;
3320 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3321 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3324 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3326 struct vcpu_svm
*svm
= to_svm(vcpu
);
3328 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3335 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3338 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3340 struct vcpu_svm
*svm
= to_svm(vcpu
);
3341 struct vmcb
*vmcb
= svm
->vmcb
;
3343 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3344 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3345 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3350 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3352 struct vcpu_svm
*svm
= to_svm(vcpu
);
3354 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3357 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3359 struct vcpu_svm
*svm
= to_svm(vcpu
);
3362 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3363 set_intercept(svm
, INTERCEPT_IRET
);
3365 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3366 clr_intercept(svm
, INTERCEPT_IRET
);
3370 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3372 struct vcpu_svm
*svm
= to_svm(vcpu
);
3373 struct vmcb
*vmcb
= svm
->vmcb
;
3376 if (!gif_set(svm
) ||
3377 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3380 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3382 if (is_guest_mode(vcpu
))
3383 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3388 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3390 struct vcpu_svm
*svm
= to_svm(vcpu
);
3393 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3394 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3395 * get that intercept, this function will be called again though and
3396 * we'll get the vintr intercept.
3398 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3400 svm_inject_irq(svm
, 0x0);
3404 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3406 struct vcpu_svm
*svm
= to_svm(vcpu
);
3408 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3410 return; /* IRET will cause a vm exit */
3413 * Something prevents NMI from been injected. Single step over possible
3414 * problem (IRET or exception injection or interrupt shadow)
3416 svm
->nmi_singlestep
= true;
3417 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3418 update_db_intercept(vcpu
);
3421 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3426 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3428 struct vcpu_svm
*svm
= to_svm(vcpu
);
3430 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3431 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3433 svm
->asid_generation
--;
3436 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3440 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3442 struct vcpu_svm
*svm
= to_svm(vcpu
);
3444 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3447 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3448 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3449 kvm_set_cr8(vcpu
, cr8
);
3453 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3455 struct vcpu_svm
*svm
= to_svm(vcpu
);
3458 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3461 cr8
= kvm_get_cr8(vcpu
);
3462 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3463 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3466 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3470 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3471 unsigned int3_injected
= svm
->int3_injected
;
3473 svm
->int3_injected
= 0;
3475 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) {
3476 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3477 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3480 svm
->vcpu
.arch
.nmi_injected
= false;
3481 kvm_clear_exception_queue(&svm
->vcpu
);
3482 kvm_clear_interrupt_queue(&svm
->vcpu
);
3484 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3487 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3489 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3490 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3493 case SVM_EXITINTINFO_TYPE_NMI
:
3494 svm
->vcpu
.arch
.nmi_injected
= true;
3496 case SVM_EXITINTINFO_TYPE_EXEPT
:
3498 * In case of software exceptions, do not reinject the vector,
3499 * but re-execute the instruction instead. Rewind RIP first
3500 * if we emulated INT3 before.
3502 if (kvm_exception_is_soft(vector
)) {
3503 if (vector
== BP_VECTOR
&& int3_injected
&&
3504 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3505 kvm_rip_write(&svm
->vcpu
,
3506 kvm_rip_read(&svm
->vcpu
) -
3510 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3511 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3512 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3515 kvm_requeue_exception(&svm
->vcpu
, vector
);
3517 case SVM_EXITINTINFO_TYPE_INTR
:
3518 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3525 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3527 struct vcpu_svm
*svm
= to_svm(vcpu
);
3528 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3530 control
->exit_int_info
= control
->event_inj
;
3531 control
->exit_int_info_err
= control
->event_inj_err
;
3532 control
->event_inj
= 0;
3533 svm_complete_interrupts(svm
);
3536 #ifdef CONFIG_X86_64
3542 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3544 struct vcpu_svm
*svm
= to_svm(vcpu
);
3546 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3547 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3548 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3551 * A vmexit emulation is required before the vcpu can be executed
3554 if (unlikely(svm
->nested
.exit_required
))
3559 sync_lapic_to_cr8(vcpu
);
3561 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3568 "push %%"R
"bp; \n\t"
3569 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3570 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3571 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3572 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3573 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3574 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3575 #ifdef CONFIG_X86_64
3576 "mov %c[r8](%[svm]), %%r8 \n\t"
3577 "mov %c[r9](%[svm]), %%r9 \n\t"
3578 "mov %c[r10](%[svm]), %%r10 \n\t"
3579 "mov %c[r11](%[svm]), %%r11 \n\t"
3580 "mov %c[r12](%[svm]), %%r12 \n\t"
3581 "mov %c[r13](%[svm]), %%r13 \n\t"
3582 "mov %c[r14](%[svm]), %%r14 \n\t"
3583 "mov %c[r15](%[svm]), %%r15 \n\t"
3586 /* Enter guest mode */
3588 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3589 __ex(SVM_VMLOAD
) "\n\t"
3590 __ex(SVM_VMRUN
) "\n\t"
3591 __ex(SVM_VMSAVE
) "\n\t"
3594 /* Save guest registers, load host registers */
3595 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3596 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3597 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3598 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3599 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3600 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3601 #ifdef CONFIG_X86_64
3602 "mov %%r8, %c[r8](%[svm]) \n\t"
3603 "mov %%r9, %c[r9](%[svm]) \n\t"
3604 "mov %%r10, %c[r10](%[svm]) \n\t"
3605 "mov %%r11, %c[r11](%[svm]) \n\t"
3606 "mov %%r12, %c[r12](%[svm]) \n\t"
3607 "mov %%r13, %c[r13](%[svm]) \n\t"
3608 "mov %%r14, %c[r14](%[svm]) \n\t"
3609 "mov %%r15, %c[r15](%[svm]) \n\t"
3614 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3615 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3616 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3617 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3618 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3619 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3620 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3621 #ifdef CONFIG_X86_64
3622 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3623 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3624 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3625 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3626 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3627 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3628 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3629 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3632 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3633 #ifdef CONFIG_X86_64
3634 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3638 #ifdef CONFIG_X86_64
3639 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3641 loadsegment(fs
, svm
->host
.fs
);
3646 local_irq_disable();
3650 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3651 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3652 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3653 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3655 sync_cr8_to_lapic(vcpu
);
3659 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3661 /* if exit due to PF check for async PF */
3662 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3663 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3666 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3667 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3671 * We need to handle MC intercepts here before the vcpu has a chance to
3672 * change the physical cpu
3674 if (unlikely(svm
->vmcb
->control
.exit_code
==
3675 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3676 svm_handle_mce(svm
);
3678 mark_all_clean(svm
->vmcb
);
3683 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3685 struct vcpu_svm
*svm
= to_svm(vcpu
);
3687 svm
->vmcb
->save
.cr3
= root
;
3688 mark_dirty(svm
->vmcb
, VMCB_CR
);
3689 svm_flush_tlb(vcpu
);
3692 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3694 struct vcpu_svm
*svm
= to_svm(vcpu
);
3696 svm
->vmcb
->control
.nested_cr3
= root
;
3697 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3699 /* Also sync guest cr3 here in case we live migrate */
3700 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
3701 mark_dirty(svm
->vmcb
, VMCB_CR
);
3703 svm_flush_tlb(vcpu
);
3706 static int is_disabled(void)
3710 rdmsrl(MSR_VM_CR
, vm_cr
);
3711 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3718 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3721 * Patch in the VMMCALL instruction:
3723 hypercall
[0] = 0x0f;
3724 hypercall
[1] = 0x01;
3725 hypercall
[2] = 0xd9;
3728 static void svm_check_processor_compat(void *rtn
)
3733 static bool svm_cpu_has_accelerated_tpr(void)
3738 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3743 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3747 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3752 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3755 entry
->eax
= 1; /* SVM revision 1 */
3756 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3757 ASID emulation to nested SVM */
3758 entry
->ecx
= 0; /* Reserved */
3759 entry
->edx
= 0; /* Per default do not support any
3760 additional features */
3762 /* Support next_rip if host supports it */
3763 if (boot_cpu_has(X86_FEATURE_NRIPS
))
3764 entry
->edx
|= SVM_FEATURE_NRIP
;
3766 /* Support NPT for the guest if enabled */
3768 entry
->edx
|= SVM_FEATURE_NPT
;
3774 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3775 { SVM_EXIT_READ_CR0
, "read_cr0" },
3776 { SVM_EXIT_READ_CR3
, "read_cr3" },
3777 { SVM_EXIT_READ_CR4
, "read_cr4" },
3778 { SVM_EXIT_READ_CR8
, "read_cr8" },
3779 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3780 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3781 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3782 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3783 { SVM_EXIT_READ_DR0
, "read_dr0" },
3784 { SVM_EXIT_READ_DR1
, "read_dr1" },
3785 { SVM_EXIT_READ_DR2
, "read_dr2" },
3786 { SVM_EXIT_READ_DR3
, "read_dr3" },
3787 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3788 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3789 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3790 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3791 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3792 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3793 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3794 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3795 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3796 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3797 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3798 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3799 { SVM_EXIT_INTR
, "interrupt" },
3800 { SVM_EXIT_NMI
, "nmi" },
3801 { SVM_EXIT_SMI
, "smi" },
3802 { SVM_EXIT_INIT
, "init" },
3803 { SVM_EXIT_VINTR
, "vintr" },
3804 { SVM_EXIT_CPUID
, "cpuid" },
3805 { SVM_EXIT_INVD
, "invd" },
3806 { SVM_EXIT_HLT
, "hlt" },
3807 { SVM_EXIT_INVLPG
, "invlpg" },
3808 { SVM_EXIT_INVLPGA
, "invlpga" },
3809 { SVM_EXIT_IOIO
, "io" },
3810 { SVM_EXIT_MSR
, "msr" },
3811 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3812 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3813 { SVM_EXIT_VMRUN
, "vmrun" },
3814 { SVM_EXIT_VMMCALL
, "hypercall" },
3815 { SVM_EXIT_VMLOAD
, "vmload" },
3816 { SVM_EXIT_VMSAVE
, "vmsave" },
3817 { SVM_EXIT_STGI
, "stgi" },
3818 { SVM_EXIT_CLGI
, "clgi" },
3819 { SVM_EXIT_SKINIT
, "skinit" },
3820 { SVM_EXIT_WBINVD
, "wbinvd" },
3821 { SVM_EXIT_MONITOR
, "monitor" },
3822 { SVM_EXIT_MWAIT
, "mwait" },
3823 { SVM_EXIT_XSETBV
, "xsetbv" },
3824 { SVM_EXIT_NPF
, "npf" },
3828 static int svm_get_lpage_level(void)
3830 return PT_PDPE_LEVEL
;
3833 static bool svm_rdtscp_supported(void)
3838 static bool svm_has_wbinvd_exit(void)
3843 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3845 struct vcpu_svm
*svm
= to_svm(vcpu
);
3847 set_exception_intercept(svm
, NM_VECTOR
);
3848 update_cr0_intercept(svm
);
3851 static struct kvm_x86_ops svm_x86_ops
= {
3852 .cpu_has_kvm_support
= has_svm
,
3853 .disabled_by_bios
= is_disabled
,
3854 .hardware_setup
= svm_hardware_setup
,
3855 .hardware_unsetup
= svm_hardware_unsetup
,
3856 .check_processor_compatibility
= svm_check_processor_compat
,
3857 .hardware_enable
= svm_hardware_enable
,
3858 .hardware_disable
= svm_hardware_disable
,
3859 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3861 .vcpu_create
= svm_create_vcpu
,
3862 .vcpu_free
= svm_free_vcpu
,
3863 .vcpu_reset
= svm_vcpu_reset
,
3865 .prepare_guest_switch
= svm_prepare_guest_switch
,
3866 .vcpu_load
= svm_vcpu_load
,
3867 .vcpu_put
= svm_vcpu_put
,
3869 .set_guest_debug
= svm_guest_debug
,
3870 .get_msr
= svm_get_msr
,
3871 .set_msr
= svm_set_msr
,
3872 .get_segment_base
= svm_get_segment_base
,
3873 .get_segment
= svm_get_segment
,
3874 .set_segment
= svm_set_segment
,
3875 .get_cpl
= svm_get_cpl
,
3876 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3877 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3878 .decache_cr3
= svm_decache_cr3
,
3879 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3880 .set_cr0
= svm_set_cr0
,
3881 .set_cr3
= svm_set_cr3
,
3882 .set_cr4
= svm_set_cr4
,
3883 .set_efer
= svm_set_efer
,
3884 .get_idt
= svm_get_idt
,
3885 .set_idt
= svm_set_idt
,
3886 .get_gdt
= svm_get_gdt
,
3887 .set_gdt
= svm_set_gdt
,
3888 .set_dr7
= svm_set_dr7
,
3889 .cache_reg
= svm_cache_reg
,
3890 .get_rflags
= svm_get_rflags
,
3891 .set_rflags
= svm_set_rflags
,
3892 .fpu_activate
= svm_fpu_activate
,
3893 .fpu_deactivate
= svm_fpu_deactivate
,
3895 .tlb_flush
= svm_flush_tlb
,
3897 .run
= svm_vcpu_run
,
3898 .handle_exit
= handle_exit
,
3899 .skip_emulated_instruction
= skip_emulated_instruction
,
3900 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3901 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3902 .patch_hypercall
= svm_patch_hypercall
,
3903 .set_irq
= svm_set_irq
,
3904 .set_nmi
= svm_inject_nmi
,
3905 .queue_exception
= svm_queue_exception
,
3906 .cancel_injection
= svm_cancel_injection
,
3907 .interrupt_allowed
= svm_interrupt_allowed
,
3908 .nmi_allowed
= svm_nmi_allowed
,
3909 .get_nmi_mask
= svm_get_nmi_mask
,
3910 .set_nmi_mask
= svm_set_nmi_mask
,
3911 .enable_nmi_window
= enable_nmi_window
,
3912 .enable_irq_window
= enable_irq_window
,
3913 .update_cr8_intercept
= update_cr8_intercept
,
3915 .set_tss_addr
= svm_set_tss_addr
,
3916 .get_tdp_level
= get_npt_level
,
3917 .get_mt_mask
= svm_get_mt_mask
,
3919 .get_exit_info
= svm_get_exit_info
,
3920 .exit_reasons_str
= svm_exit_reasons_str
,
3922 .get_lpage_level
= svm_get_lpage_level
,
3924 .cpuid_update
= svm_cpuid_update
,
3926 .rdtscp_supported
= svm_rdtscp_supported
,
3928 .set_supported_cpuid
= svm_set_supported_cpuid
,
3930 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3932 .write_tsc_offset
= svm_write_tsc_offset
,
3933 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3935 .set_tdp_cr3
= set_tdp_cr3
,
3938 static int __init
svm_init(void)
3940 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3941 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3944 static void __exit
svm_exit(void)
3949 module_init(svm_init
)
3950 module_exit(svm_exit
)