2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
37 #include <asm/kvm_para.h>
39 #include <asm/virtext.h>
42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44 MODULE_AUTHOR("Qumranet");
45 MODULE_LICENSE("GPL");
47 static const struct x86_cpu_id svm_cpu_id
[] = {
48 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
51 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
53 #define IOPM_ALLOC_ORDER 2
54 #define MSRPM_ALLOC_ORDER 1
56 #define SEG_TYPE_LDT 2
57 #define SEG_TYPE_BUSY_TSS16 3
59 #define SVM_FEATURE_NPT (1 << 0)
60 #define SVM_FEATURE_LBRV (1 << 1)
61 #define SVM_FEATURE_SVML (1 << 2)
62 #define SVM_FEATURE_NRIP (1 << 3)
63 #define SVM_FEATURE_TSC_RATE (1 << 4)
64 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
65 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
66 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
67 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
69 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
70 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
71 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
76 #define TSC_RATIO_MIN 0x0000000000000001ULL
77 #define TSC_RATIO_MAX 0x000000ffffffffffULL
79 static bool erratum_383_found __read_mostly
;
81 static const u32 host_save_user_msrs
[] = {
83 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
86 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
99 /* These are the merged vectors */
102 /* gpa pointers to the real vectors */
106 /* A VMEXIT is required but not yet emulated */
109 /* cache for intercepts of the guest */
112 u32 intercept_exceptions
;
115 /* Nested Paging related state */
119 #define MSRPM_OFFSETS 16
120 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
123 * Set osvw_len to higher value when updated Revision Guides
124 * are published and we know what the new status bits are
126 static uint64_t osvw_len
= 4, osvw_status
;
129 struct kvm_vcpu vcpu
;
131 unsigned long vmcb_pa
;
132 struct svm_cpu_data
*svm_data
;
133 uint64_t asid_generation
;
134 uint64_t sysenter_esp
;
135 uint64_t sysenter_eip
;
139 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
151 struct nested_state nested
;
155 unsigned int3_injected
;
156 unsigned long int3_rip
;
162 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
163 #define TSC_RATIO_DEFAULT 0x0100000000ULL
165 #define MSR_INVALID 0xffffffffU
167 static const struct svm_direct_access_msrs
{
168 u32 index
; /* Index of the MSR */
169 bool always
; /* True if intercept is always on */
170 } direct_access_msrs
[] = {
171 { .index
= MSR_STAR
, .always
= true },
172 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
174 { .index
= MSR_GS_BASE
, .always
= true },
175 { .index
= MSR_FS_BASE
, .always
= true },
176 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
177 { .index
= MSR_LSTAR
, .always
= true },
178 { .index
= MSR_CSTAR
, .always
= true },
179 { .index
= MSR_SYSCALL_MASK
, .always
= true },
181 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
182 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
183 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
184 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
185 { .index
= MSR_INVALID
, .always
= false },
188 /* enable NPT for AMD64 and X86 with PAE */
189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
190 static bool npt_enabled
= true;
192 static bool npt_enabled
;
195 /* allow nested paging (virtualized MMU) for all guests */
196 static int npt
= true;
197 module_param(npt
, int, S_IRUGO
);
199 /* allow nested virtualization in KVM/SVM */
200 static int nested
= true;
201 module_param(nested
, int, S_IRUGO
);
203 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
204 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
206 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
207 static int nested_svm_intercept(struct vcpu_svm
*svm
);
208 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
209 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
210 bool has_error_code
, u32 error_code
);
211 static u64
__scale_tsc(u64 ratio
, u64 tsc
);
214 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
215 pause filter count */
216 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
217 VMCB_ASID
, /* ASID */
218 VMCB_INTR
, /* int_ctl, int_vector */
219 VMCB_NPT
, /* npt_en, nCR3, gPAT */
220 VMCB_CR
, /* CR0, CR3, CR4, EFER */
221 VMCB_DR
, /* DR6, DR7 */
222 VMCB_DT
, /* GDT, IDT */
223 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
224 VMCB_CR2
, /* CR2 only */
225 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
229 /* TPR and CR2 are always written before VMRUN */
230 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
232 static inline void mark_all_dirty(struct vmcb
*vmcb
)
234 vmcb
->control
.clean
= 0;
237 static inline void mark_all_clean(struct vmcb
*vmcb
)
239 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
240 & ~VMCB_ALWAYS_DIRTY_MASK
;
243 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
245 vmcb
->control
.clean
&= ~(1 << bit
);
248 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
250 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
253 static void recalc_intercepts(struct vcpu_svm
*svm
)
255 struct vmcb_control_area
*c
, *h
;
256 struct nested_state
*g
;
258 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
260 if (!is_guest_mode(&svm
->vcpu
))
263 c
= &svm
->vmcb
->control
;
264 h
= &svm
->nested
.hsave
->control
;
267 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
268 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
269 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
270 c
->intercept
= h
->intercept
| g
->intercept
;
273 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
275 if (is_guest_mode(&svm
->vcpu
))
276 return svm
->nested
.hsave
;
281 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
283 struct vmcb
*vmcb
= get_host_vmcb(svm
);
285 vmcb
->control
.intercept_cr
|= (1U << bit
);
287 recalc_intercepts(svm
);
290 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
292 struct vmcb
*vmcb
= get_host_vmcb(svm
);
294 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
296 recalc_intercepts(svm
);
299 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
301 struct vmcb
*vmcb
= get_host_vmcb(svm
);
303 return vmcb
->control
.intercept_cr
& (1U << bit
);
306 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
308 struct vmcb
*vmcb
= get_host_vmcb(svm
);
310 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
311 | (1 << INTERCEPT_DR1_READ
)
312 | (1 << INTERCEPT_DR2_READ
)
313 | (1 << INTERCEPT_DR3_READ
)
314 | (1 << INTERCEPT_DR4_READ
)
315 | (1 << INTERCEPT_DR5_READ
)
316 | (1 << INTERCEPT_DR6_READ
)
317 | (1 << INTERCEPT_DR7_READ
)
318 | (1 << INTERCEPT_DR0_WRITE
)
319 | (1 << INTERCEPT_DR1_WRITE
)
320 | (1 << INTERCEPT_DR2_WRITE
)
321 | (1 << INTERCEPT_DR3_WRITE
)
322 | (1 << INTERCEPT_DR4_WRITE
)
323 | (1 << INTERCEPT_DR5_WRITE
)
324 | (1 << INTERCEPT_DR6_WRITE
)
325 | (1 << INTERCEPT_DR7_WRITE
);
327 recalc_intercepts(svm
);
330 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
332 struct vmcb
*vmcb
= get_host_vmcb(svm
);
334 vmcb
->control
.intercept_dr
= 0;
336 recalc_intercepts(svm
);
339 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
341 struct vmcb
*vmcb
= get_host_vmcb(svm
);
343 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
345 recalc_intercepts(svm
);
348 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
350 struct vmcb
*vmcb
= get_host_vmcb(svm
);
352 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
354 recalc_intercepts(svm
);
357 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
359 struct vmcb
*vmcb
= get_host_vmcb(svm
);
361 vmcb
->control
.intercept
|= (1ULL << bit
);
363 recalc_intercepts(svm
);
366 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
368 struct vmcb
*vmcb
= get_host_vmcb(svm
);
370 vmcb
->control
.intercept
&= ~(1ULL << bit
);
372 recalc_intercepts(svm
);
375 static inline void enable_gif(struct vcpu_svm
*svm
)
377 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
380 static inline void disable_gif(struct vcpu_svm
*svm
)
382 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
385 static inline bool gif_set(struct vcpu_svm
*svm
)
387 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
390 static unsigned long iopm_base
;
392 struct kvm_ldttss_desc
{
395 unsigned base1
:8, type
:5, dpl
:2, p
:1;
396 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
399 } __attribute__((packed
));
401 struct svm_cpu_data
{
407 struct kvm_ldttss_desc
*tss_desc
;
409 struct page
*save_area
;
412 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
414 struct svm_init_data
{
419 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
421 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
422 #define MSRS_RANGE_SIZE 2048
423 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
425 static u32
svm_msrpm_offset(u32 msr
)
430 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
431 if (msr
< msrpm_ranges
[i
] ||
432 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
435 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
436 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
438 /* Now we have the u8 offset - but need the u32 offset */
442 /* MSR not in any range */
446 #define MAX_INST_SIZE 15
448 static inline void clgi(void)
450 asm volatile (__ex(SVM_CLGI
));
453 static inline void stgi(void)
455 asm volatile (__ex(SVM_STGI
));
458 static inline void invlpga(unsigned long addr
, u32 asid
)
460 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
463 static int get_npt_level(void)
466 return PT64_ROOT_LEVEL
;
468 return PT32E_ROOT_LEVEL
;
472 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
474 vcpu
->arch
.efer
= efer
;
475 if (!npt_enabled
&& !(efer
& EFER_LMA
))
478 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
479 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
482 static int is_external_interrupt(u32 info
)
484 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
485 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
488 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
490 struct vcpu_svm
*svm
= to_svm(vcpu
);
493 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
494 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
498 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
500 struct vcpu_svm
*svm
= to_svm(vcpu
);
503 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
505 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
509 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
511 struct vcpu_svm
*svm
= to_svm(vcpu
);
513 if (svm
->vmcb
->control
.next_rip
!= 0)
514 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
516 if (!svm
->next_rip
) {
517 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
519 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
522 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
523 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
524 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
526 kvm_rip_write(vcpu
, svm
->next_rip
);
527 svm_set_interrupt_shadow(vcpu
, 0);
530 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
531 bool has_error_code
, u32 error_code
,
534 struct vcpu_svm
*svm
= to_svm(vcpu
);
537 * If we are within a nested VM we'd better #VMEXIT and let the guest
538 * handle the exception
541 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
544 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
545 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
548 * For guest debugging where we have to reinject #BP if some
549 * INT3 is guest-owned:
550 * Emulate nRIP by moving RIP forward. Will fail if injection
551 * raises a fault that is not intercepted. Still better than
552 * failing in all cases.
554 skip_emulated_instruction(&svm
->vcpu
);
555 rip
= kvm_rip_read(&svm
->vcpu
);
556 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
557 svm
->int3_injected
= rip
- old_rip
;
560 svm
->vmcb
->control
.event_inj
= nr
562 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
563 | SVM_EVTINJ_TYPE_EXEPT
;
564 svm
->vmcb
->control
.event_inj_err
= error_code
;
567 static void svm_init_erratum_383(void)
573 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
576 /* Use _safe variants to not break nested virtualization */
577 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
583 low
= lower_32_bits(val
);
584 high
= upper_32_bits(val
);
586 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
588 erratum_383_found
= true;
591 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
594 * Guests should see errata 400 and 415 as fixed (assuming that
595 * HLT and IO instructions are intercepted).
597 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
598 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
601 * By increasing VCPU's osvw.length to 3 we are telling the guest that
602 * all osvw.status bits inside that length, including bit 0 (which is
603 * reserved for erratum 298), are valid. However, if host processor's
604 * osvw_len is 0 then osvw_status[0] carries no information. We need to
605 * be conservative here and therefore we tell the guest that erratum 298
606 * is present (because we really don't know).
608 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
609 vcpu
->arch
.osvw
.status
|= 1;
612 static int has_svm(void)
616 if (!cpu_has_svm(&msg
)) {
617 printk(KERN_INFO
"has_svm: %s\n", msg
);
624 static void svm_hardware_disable(void *garbage
)
626 /* Make sure we clean up behind us */
627 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
628 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
632 amd_pmu_disable_virt();
635 static int svm_hardware_enable(void *garbage
)
638 struct svm_cpu_data
*sd
;
640 struct desc_ptr gdt_descr
;
641 struct desc_struct
*gdt
;
642 int me
= raw_smp_processor_id();
644 rdmsrl(MSR_EFER
, efer
);
645 if (efer
& EFER_SVME
)
649 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
652 sd
= per_cpu(svm_data
, me
);
654 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
658 sd
->asid_generation
= 1;
659 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
660 sd
->next_asid
= sd
->max_asid
+ 1;
662 native_store_gdt(&gdt_descr
);
663 gdt
= (struct desc_struct
*)gdt_descr
.address
;
664 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
666 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
668 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
670 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
671 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
672 __get_cpu_var(current_tsc_ratio
) = TSC_RATIO_DEFAULT
;
679 * Note that it is possible to have a system with mixed processor
680 * revisions and therefore different OSVW bits. If bits are not the same
681 * on different processors then choose the worst case (i.e. if erratum
682 * is present on one processor and not on another then assume that the
683 * erratum is present everywhere).
685 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
686 uint64_t len
, status
= 0;
689 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
691 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
695 osvw_status
= osvw_len
= 0;
699 osvw_status
|= status
;
700 osvw_status
&= (1ULL << osvw_len
) - 1;
703 osvw_status
= osvw_len
= 0;
705 svm_init_erratum_383();
707 amd_pmu_enable_virt();
712 static void svm_cpu_uninit(int cpu
)
714 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
719 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
720 __free_page(sd
->save_area
);
724 static int svm_cpu_init(int cpu
)
726 struct svm_cpu_data
*sd
;
729 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
733 sd
->save_area
= alloc_page(GFP_KERNEL
);
738 per_cpu(svm_data
, cpu
) = sd
;
748 static bool valid_msr_intercept(u32 index
)
752 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
753 if (direct_access_msrs
[i
].index
== index
)
759 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
762 u8 bit_read
, bit_write
;
767 * If this warning triggers extend the direct_access_msrs list at the
768 * beginning of the file
770 WARN_ON(!valid_msr_intercept(msr
));
772 offset
= svm_msrpm_offset(msr
);
773 bit_read
= 2 * (msr
& 0x0f);
774 bit_write
= 2 * (msr
& 0x0f) + 1;
777 BUG_ON(offset
== MSR_INVALID
);
779 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
780 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
785 static void svm_vcpu_init_msrpm(u32
*msrpm
)
789 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
791 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
792 if (!direct_access_msrs
[i
].always
)
795 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
799 static void add_msr_offset(u32 offset
)
803 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
805 /* Offset already in list? */
806 if (msrpm_offsets
[i
] == offset
)
809 /* Slot used by another offset? */
810 if (msrpm_offsets
[i
] != MSR_INVALID
)
813 /* Add offset to list */
814 msrpm_offsets
[i
] = offset
;
820 * If this BUG triggers the msrpm_offsets table has an overflow. Just
821 * increase MSRPM_OFFSETS in this case.
826 static void init_msrpm_offsets(void)
830 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
832 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
835 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
836 BUG_ON(offset
== MSR_INVALID
);
838 add_msr_offset(offset
);
842 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
844 u32
*msrpm
= svm
->msrpm
;
846 svm
->vmcb
->control
.lbr_ctl
= 1;
847 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
848 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
849 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
850 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
853 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
855 u32
*msrpm
= svm
->msrpm
;
857 svm
->vmcb
->control
.lbr_ctl
= 0;
858 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
859 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
860 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
861 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
864 static __init
int svm_hardware_setup(void)
867 struct page
*iopm_pages
;
871 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
876 iopm_va
= page_address(iopm_pages
);
877 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
878 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
880 init_msrpm_offsets();
882 if (boot_cpu_has(X86_FEATURE_NX
))
883 kvm_enable_efer_bits(EFER_NX
);
885 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
886 kvm_enable_efer_bits(EFER_FFXSR
);
888 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
891 kvm_has_tsc_control
= true;
894 * Make sure the user can only configure tsc_khz values that
895 * fit into a signed integer.
896 * A min value is not calculated needed because it will always
897 * be 1 on all machines and a value of 0 is used to disable
898 * tsc-scaling for the vcpu.
900 max
= min(0x7fffffffULL
, __scale_tsc(tsc_khz
, TSC_RATIO_MAX
));
902 kvm_max_guest_tsc_khz
= max
;
906 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
907 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
910 for_each_possible_cpu(cpu
) {
911 r
= svm_cpu_init(cpu
);
916 if (!boot_cpu_has(X86_FEATURE_NPT
))
919 if (npt_enabled
&& !npt
) {
920 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
925 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
933 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
938 static __exit
void svm_hardware_unsetup(void)
942 for_each_possible_cpu(cpu
)
945 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
949 static void init_seg(struct vmcb_seg
*seg
)
952 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
953 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
958 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
961 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
966 static u64
__scale_tsc(u64 ratio
, u64 tsc
)
968 u64 mult
, frac
, _tsc
;
971 frac
= ratio
& ((1ULL << 32) - 1);
975 _tsc
+= (tsc
>> 32) * frac
;
976 _tsc
+= ((tsc
& ((1ULL << 32) - 1)) * frac
) >> 32;
981 static u64
svm_scale_tsc(struct kvm_vcpu
*vcpu
, u64 tsc
)
983 struct vcpu_svm
*svm
= to_svm(vcpu
);
986 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
987 _tsc
= __scale_tsc(svm
->tsc_ratio
, tsc
);
992 static void svm_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
994 struct vcpu_svm
*svm
= to_svm(vcpu
);
998 /* Guest TSC same frequency as host TSC? */
1000 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1004 /* TSC scaling supported? */
1005 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1006 if (user_tsc_khz
> tsc_khz
) {
1007 vcpu
->arch
.tsc_catchup
= 1;
1008 vcpu
->arch
.tsc_always_catchup
= 1;
1010 WARN(1, "user requested TSC rate below hardware speed\n");
1016 /* TSC scaling required - calculate ratio */
1018 do_div(ratio
, tsc_khz
);
1020 if (ratio
== 0 || ratio
& TSC_RATIO_RSVD
) {
1021 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1025 svm
->tsc_ratio
= ratio
;
1028 static u64
svm_read_tsc_offset(struct kvm_vcpu
*vcpu
)
1030 struct vcpu_svm
*svm
= to_svm(vcpu
);
1032 return svm
->vmcb
->control
.tsc_offset
;
1035 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1037 struct vcpu_svm
*svm
= to_svm(vcpu
);
1038 u64 g_tsc_offset
= 0;
1040 if (is_guest_mode(vcpu
)) {
1041 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1042 svm
->nested
.hsave
->control
.tsc_offset
;
1043 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1045 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1046 svm
->vmcb
->control
.tsc_offset
,
1049 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1051 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1054 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1056 struct vcpu_svm
*svm
= to_svm(vcpu
);
1058 WARN_ON(adjustment
< 0);
1060 adjustment
= svm_scale_tsc(vcpu
, adjustment
);
1062 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
1063 if (is_guest_mode(vcpu
))
1064 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
1066 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1067 svm
->vmcb
->control
.tsc_offset
- adjustment
,
1068 svm
->vmcb
->control
.tsc_offset
);
1070 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1073 static u64
svm_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1077 tsc
= svm_scale_tsc(vcpu
, native_read_tsc());
1079 return target_tsc
- tsc
;
1082 static void init_vmcb(struct vcpu_svm
*svm
)
1084 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1085 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1087 svm
->vcpu
.fpu_active
= 1;
1088 svm
->vcpu
.arch
.hflags
= 0;
1090 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1091 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1092 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1093 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1094 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1095 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1096 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1098 set_dr_intercepts(svm
);
1100 set_exception_intercept(svm
, PF_VECTOR
);
1101 set_exception_intercept(svm
, UD_VECTOR
);
1102 set_exception_intercept(svm
, MC_VECTOR
);
1104 set_intercept(svm
, INTERCEPT_INTR
);
1105 set_intercept(svm
, INTERCEPT_NMI
);
1106 set_intercept(svm
, INTERCEPT_SMI
);
1107 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1108 set_intercept(svm
, INTERCEPT_RDPMC
);
1109 set_intercept(svm
, INTERCEPT_CPUID
);
1110 set_intercept(svm
, INTERCEPT_INVD
);
1111 set_intercept(svm
, INTERCEPT_HLT
);
1112 set_intercept(svm
, INTERCEPT_INVLPG
);
1113 set_intercept(svm
, INTERCEPT_INVLPGA
);
1114 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1115 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1116 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1117 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1118 set_intercept(svm
, INTERCEPT_VMRUN
);
1119 set_intercept(svm
, INTERCEPT_VMMCALL
);
1120 set_intercept(svm
, INTERCEPT_VMLOAD
);
1121 set_intercept(svm
, INTERCEPT_VMSAVE
);
1122 set_intercept(svm
, INTERCEPT_STGI
);
1123 set_intercept(svm
, INTERCEPT_CLGI
);
1124 set_intercept(svm
, INTERCEPT_SKINIT
);
1125 set_intercept(svm
, INTERCEPT_WBINVD
);
1126 set_intercept(svm
, INTERCEPT_MONITOR
);
1127 set_intercept(svm
, INTERCEPT_MWAIT
);
1128 set_intercept(svm
, INTERCEPT_XSETBV
);
1130 control
->iopm_base_pa
= iopm_base
;
1131 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1132 control
->int_ctl
= V_INTR_MASKING_MASK
;
1134 init_seg(&save
->es
);
1135 init_seg(&save
->ss
);
1136 init_seg(&save
->ds
);
1137 init_seg(&save
->fs
);
1138 init_seg(&save
->gs
);
1140 save
->cs
.selector
= 0xf000;
1141 save
->cs
.base
= 0xffff0000;
1142 /* Executable/Readable Code Segment */
1143 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1144 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1145 save
->cs
.limit
= 0xffff;
1147 save
->gdtr
.limit
= 0xffff;
1148 save
->idtr
.limit
= 0xffff;
1150 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1151 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1153 svm_set_efer(&svm
->vcpu
, 0);
1154 save
->dr6
= 0xffff0ff0;
1155 kvm_set_rflags(&svm
->vcpu
, 2);
1156 save
->rip
= 0x0000fff0;
1157 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1160 * This is the guest-visible cr0 value.
1161 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1163 svm
->vcpu
.arch
.cr0
= 0;
1164 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1166 save
->cr4
= X86_CR4_PAE
;
1170 /* Setup VMCB for Nested Paging */
1171 control
->nested_ctl
= 1;
1172 clr_intercept(svm
, INTERCEPT_INVLPG
);
1173 clr_exception_intercept(svm
, PF_VECTOR
);
1174 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1175 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1176 save
->g_pat
= 0x0007040600070406ULL
;
1180 svm
->asid_generation
= 0;
1182 svm
->nested
.vmcb
= 0;
1183 svm
->vcpu
.arch
.hflags
= 0;
1185 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1186 control
->pause_filter_count
= 3000;
1187 set_intercept(svm
, INTERCEPT_PAUSE
);
1190 mark_all_dirty(svm
->vmcb
);
1195 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1197 struct vcpu_svm
*svm
= to_svm(vcpu
);
1203 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
);
1204 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1207 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1209 struct vcpu_svm
*svm
;
1211 struct page
*msrpm_pages
;
1212 struct page
*hsave_page
;
1213 struct page
*nested_msrpm_pages
;
1216 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1222 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1224 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1229 page
= alloc_page(GFP_KERNEL
);
1233 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1237 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1238 if (!nested_msrpm_pages
)
1241 hsave_page
= alloc_page(GFP_KERNEL
);
1245 svm
->nested
.hsave
= page_address(hsave_page
);
1247 svm
->msrpm
= page_address(msrpm_pages
);
1248 svm_vcpu_init_msrpm(svm
->msrpm
);
1250 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1251 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1253 svm
->vmcb
= page_address(page
);
1254 clear_page(svm
->vmcb
);
1255 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1256 svm
->asid_generation
= 0;
1259 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1260 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1261 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1263 svm_init_osvw(&svm
->vcpu
);
1268 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1270 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1274 kvm_vcpu_uninit(&svm
->vcpu
);
1276 kmem_cache_free(kvm_vcpu_cache
, svm
);
1278 return ERR_PTR(err
);
1281 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1283 struct vcpu_svm
*svm
= to_svm(vcpu
);
1285 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1286 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1287 __free_page(virt_to_page(svm
->nested
.hsave
));
1288 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1289 kvm_vcpu_uninit(vcpu
);
1290 kmem_cache_free(kvm_vcpu_cache
, svm
);
1293 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1295 struct vcpu_svm
*svm
= to_svm(vcpu
);
1298 if (unlikely(cpu
!= vcpu
->cpu
)) {
1299 svm
->asid_generation
= 0;
1300 mark_all_dirty(svm
->vmcb
);
1303 #ifdef CONFIG_X86_64
1304 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1306 savesegment(fs
, svm
->host
.fs
);
1307 savesegment(gs
, svm
->host
.gs
);
1308 svm
->host
.ldt
= kvm_read_ldt();
1310 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1311 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1313 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
) &&
1314 svm
->tsc_ratio
!= __get_cpu_var(current_tsc_ratio
)) {
1315 __get_cpu_var(current_tsc_ratio
) = svm
->tsc_ratio
;
1316 wrmsrl(MSR_AMD64_TSC_RATIO
, svm
->tsc_ratio
);
1320 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1322 struct vcpu_svm
*svm
= to_svm(vcpu
);
1325 ++vcpu
->stat
.host_state_reload
;
1326 kvm_load_ldt(svm
->host
.ldt
);
1327 #ifdef CONFIG_X86_64
1328 loadsegment(fs
, svm
->host
.fs
);
1329 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1330 load_gs_index(svm
->host
.gs
);
1332 #ifdef CONFIG_X86_32_LAZY_GS
1333 loadsegment(gs
, svm
->host
.gs
);
1336 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1337 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1340 static void svm_update_cpl(struct kvm_vcpu
*vcpu
)
1342 struct vcpu_svm
*svm
= to_svm(vcpu
);
1345 if (!is_protmode(vcpu
))
1347 else if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_VM
)
1350 cpl
= svm
->vmcb
->save
.cs
.selector
& 0x3;
1352 svm
->vmcb
->save
.cpl
= cpl
;
1355 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1357 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1360 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1362 unsigned long old_rflags
= to_svm(vcpu
)->vmcb
->save
.rflags
;
1364 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1365 if ((old_rflags
^ rflags
) & X86_EFLAGS_VM
)
1366 svm_update_cpl(vcpu
);
1369 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1372 case VCPU_EXREG_PDPTR
:
1373 BUG_ON(!npt_enabled
);
1374 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1381 static void svm_set_vintr(struct vcpu_svm
*svm
)
1383 set_intercept(svm
, INTERCEPT_VINTR
);
1386 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1388 clr_intercept(svm
, INTERCEPT_VINTR
);
1391 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1393 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1396 case VCPU_SREG_CS
: return &save
->cs
;
1397 case VCPU_SREG_DS
: return &save
->ds
;
1398 case VCPU_SREG_ES
: return &save
->es
;
1399 case VCPU_SREG_FS
: return &save
->fs
;
1400 case VCPU_SREG_GS
: return &save
->gs
;
1401 case VCPU_SREG_SS
: return &save
->ss
;
1402 case VCPU_SREG_TR
: return &save
->tr
;
1403 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1409 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1411 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1416 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1417 struct kvm_segment
*var
, int seg
)
1419 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1421 var
->base
= s
->base
;
1422 var
->limit
= s
->limit
;
1423 var
->selector
= s
->selector
;
1424 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1425 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1426 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1427 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1428 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1429 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1430 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1431 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1434 * AMD's VMCB does not have an explicit unusable field, so emulate it
1435 * for cross vendor migration purposes by "not present"
1437 var
->unusable
= !var
->present
|| (var
->type
== 0);
1442 * SVM always stores 0 for the 'G' bit in the CS selector in
1443 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1444 * Intel's VMENTRY has a check on the 'G' bit.
1446 var
->g
= s
->limit
> 0xfffff;
1450 * Work around a bug where the busy flag in the tr selector
1460 * The accessed bit must always be set in the segment
1461 * descriptor cache, although it can be cleared in the
1462 * descriptor, the cached bit always remains at 1. Since
1463 * Intel has a check on this, set it here to support
1464 * cross-vendor migration.
1471 * On AMD CPUs sometimes the DB bit in the segment
1472 * descriptor is left as 1, although the whole segment has
1473 * been made unusable. Clear it here to pass an Intel VMX
1474 * entry check when cross vendor migrating.
1482 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1484 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1489 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1491 struct vcpu_svm
*svm
= to_svm(vcpu
);
1493 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1494 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1497 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1499 struct vcpu_svm
*svm
= to_svm(vcpu
);
1501 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1502 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1503 mark_dirty(svm
->vmcb
, VMCB_DT
);
1506 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1508 struct vcpu_svm
*svm
= to_svm(vcpu
);
1510 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1511 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1514 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1516 struct vcpu_svm
*svm
= to_svm(vcpu
);
1518 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1519 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1520 mark_dirty(svm
->vmcb
, VMCB_DT
);
1523 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1527 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1531 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1535 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1537 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1538 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1540 if (!svm
->vcpu
.fpu_active
)
1541 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1543 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1544 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1546 mark_dirty(svm
->vmcb
, VMCB_CR
);
1548 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1549 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1550 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1552 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1553 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1557 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1559 struct vcpu_svm
*svm
= to_svm(vcpu
);
1561 #ifdef CONFIG_X86_64
1562 if (vcpu
->arch
.efer
& EFER_LME
) {
1563 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1564 vcpu
->arch
.efer
|= EFER_LMA
;
1565 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1568 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1569 vcpu
->arch
.efer
&= ~EFER_LMA
;
1570 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1574 vcpu
->arch
.cr0
= cr0
;
1577 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1579 if (!vcpu
->fpu_active
)
1582 * re-enable caching here because the QEMU bios
1583 * does not do it - this results in some delay at
1586 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1587 svm
->vmcb
->save
.cr0
= cr0
;
1588 mark_dirty(svm
->vmcb
, VMCB_CR
);
1589 update_cr0_intercept(svm
);
1592 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1594 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1595 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1597 if (cr4
& X86_CR4_VMXE
)
1600 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1601 svm_flush_tlb(vcpu
);
1603 vcpu
->arch
.cr4
= cr4
;
1606 cr4
|= host_cr4_mce
;
1607 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1608 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1612 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1613 struct kvm_segment
*var
, int seg
)
1615 struct vcpu_svm
*svm
= to_svm(vcpu
);
1616 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1618 s
->base
= var
->base
;
1619 s
->limit
= var
->limit
;
1620 s
->selector
= var
->selector
;
1624 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1625 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1626 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1627 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1628 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1629 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1630 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1631 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1633 if (seg
== VCPU_SREG_CS
)
1634 svm_update_cpl(vcpu
);
1636 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1639 static void update_db_bp_intercept(struct kvm_vcpu
*vcpu
)
1641 struct vcpu_svm
*svm
= to_svm(vcpu
);
1643 clr_exception_intercept(svm
, DB_VECTOR
);
1644 clr_exception_intercept(svm
, BP_VECTOR
);
1646 if (svm
->nmi_singlestep
)
1647 set_exception_intercept(svm
, DB_VECTOR
);
1649 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1650 if (vcpu
->guest_debug
&
1651 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1652 set_exception_intercept(svm
, DB_VECTOR
);
1653 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1654 set_exception_intercept(svm
, BP_VECTOR
);
1656 vcpu
->guest_debug
= 0;
1659 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1661 if (sd
->next_asid
> sd
->max_asid
) {
1662 ++sd
->asid_generation
;
1664 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1667 svm
->asid_generation
= sd
->asid_generation
;
1668 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1670 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1673 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
1675 return to_svm(vcpu
)->vmcb
->save
.dr6
;
1678 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
1680 struct vcpu_svm
*svm
= to_svm(vcpu
);
1682 svm
->vmcb
->save
.dr6
= value
;
1683 mark_dirty(svm
->vmcb
, VMCB_DR
);
1686 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1688 struct vcpu_svm
*svm
= to_svm(vcpu
);
1690 svm
->vmcb
->save
.dr7
= value
;
1691 mark_dirty(svm
->vmcb
, VMCB_DR
);
1694 static int pf_interception(struct vcpu_svm
*svm
)
1696 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1700 switch (svm
->apf_reason
) {
1702 error_code
= svm
->vmcb
->control
.exit_info_1
;
1704 trace_kvm_page_fault(fault_address
, error_code
);
1705 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1706 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1707 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1708 svm
->vmcb
->control
.insn_bytes
,
1709 svm
->vmcb
->control
.insn_len
);
1711 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1712 svm
->apf_reason
= 0;
1713 local_irq_disable();
1714 kvm_async_pf_task_wait(fault_address
);
1717 case KVM_PV_REASON_PAGE_READY
:
1718 svm
->apf_reason
= 0;
1719 local_irq_disable();
1720 kvm_async_pf_task_wake(fault_address
);
1727 static int db_interception(struct vcpu_svm
*svm
)
1729 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1731 if (!(svm
->vcpu
.guest_debug
&
1732 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1733 !svm
->nmi_singlestep
) {
1734 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1738 if (svm
->nmi_singlestep
) {
1739 svm
->nmi_singlestep
= false;
1740 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1741 svm
->vmcb
->save
.rflags
&=
1742 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1743 update_db_bp_intercept(&svm
->vcpu
);
1746 if (svm
->vcpu
.guest_debug
&
1747 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1748 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1749 kvm_run
->debug
.arch
.pc
=
1750 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1751 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1758 static int bp_interception(struct vcpu_svm
*svm
)
1760 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1762 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1763 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1764 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1768 static int ud_interception(struct vcpu_svm
*svm
)
1772 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1773 if (er
!= EMULATE_DONE
)
1774 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1778 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1780 struct vcpu_svm
*svm
= to_svm(vcpu
);
1782 clr_exception_intercept(svm
, NM_VECTOR
);
1784 svm
->vcpu
.fpu_active
= 1;
1785 update_cr0_intercept(svm
);
1788 static int nm_interception(struct vcpu_svm
*svm
)
1790 svm_fpu_activate(&svm
->vcpu
);
1794 static bool is_erratum_383(void)
1799 if (!erratum_383_found
)
1802 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1806 /* Bit 62 may or may not be set for this mce */
1807 value
&= ~(1ULL << 62);
1809 if (value
!= 0xb600000000010015ULL
)
1812 /* Clear MCi_STATUS registers */
1813 for (i
= 0; i
< 6; ++i
)
1814 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1816 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1820 value
&= ~(1ULL << 2);
1821 low
= lower_32_bits(value
);
1822 high
= upper_32_bits(value
);
1824 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1827 /* Flush tlb to evict multi-match entries */
1833 static void svm_handle_mce(struct vcpu_svm
*svm
)
1835 if (is_erratum_383()) {
1837 * Erratum 383 triggered. Guest state is corrupt so kill the
1840 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1842 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1848 * On an #MC intercept the MCE handler is not called automatically in
1849 * the host. So do it by hand here.
1853 /* not sure if we ever come back to this point */
1858 static int mc_interception(struct vcpu_svm
*svm
)
1863 static int shutdown_interception(struct vcpu_svm
*svm
)
1865 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1868 * VMCB is undefined after a SHUTDOWN intercept
1869 * so reinitialize it.
1871 clear_page(svm
->vmcb
);
1874 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1878 static int io_interception(struct vcpu_svm
*svm
)
1880 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1881 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1882 int size
, in
, string
;
1885 ++svm
->vcpu
.stat
.io_exits
;
1886 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1887 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1889 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
1891 port
= io_info
>> 16;
1892 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1893 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1894 skip_emulated_instruction(&svm
->vcpu
);
1896 return kvm_fast_pio_out(vcpu
, size
, port
);
1899 static int nmi_interception(struct vcpu_svm
*svm
)
1904 static int intr_interception(struct vcpu_svm
*svm
)
1906 ++svm
->vcpu
.stat
.irq_exits
;
1910 static int nop_on_interception(struct vcpu_svm
*svm
)
1915 static int halt_interception(struct vcpu_svm
*svm
)
1917 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1918 skip_emulated_instruction(&svm
->vcpu
);
1919 return kvm_emulate_halt(&svm
->vcpu
);
1922 static int vmmcall_interception(struct vcpu_svm
*svm
)
1924 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1925 skip_emulated_instruction(&svm
->vcpu
);
1926 kvm_emulate_hypercall(&svm
->vcpu
);
1930 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1932 struct vcpu_svm
*svm
= to_svm(vcpu
);
1934 return svm
->nested
.nested_cr3
;
1937 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
1939 struct vcpu_svm
*svm
= to_svm(vcpu
);
1940 u64 cr3
= svm
->nested
.nested_cr3
;
1944 ret
= kvm_read_guest_page(vcpu
->kvm
, gpa_to_gfn(cr3
), &pdpte
,
1945 offset_in_page(cr3
) + index
* 8, 8);
1951 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1954 struct vcpu_svm
*svm
= to_svm(vcpu
);
1956 svm
->vmcb
->control
.nested_cr3
= root
;
1957 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1958 svm_flush_tlb(vcpu
);
1961 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1962 struct x86_exception
*fault
)
1964 struct vcpu_svm
*svm
= to_svm(vcpu
);
1966 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1967 svm
->vmcb
->control
.exit_code_hi
= 0;
1968 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1969 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1971 nested_svm_vmexit(svm
);
1974 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1976 kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1978 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1979 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1980 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
1981 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1982 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1983 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1986 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1988 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1991 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1993 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1994 || !is_paging(&svm
->vcpu
)) {
1995 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1999 if (svm
->vmcb
->save
.cpl
) {
2000 kvm_inject_gp(&svm
->vcpu
, 0);
2007 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2008 bool has_error_code
, u32 error_code
)
2012 if (!is_guest_mode(&svm
->vcpu
))
2015 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2016 svm
->vmcb
->control
.exit_code_hi
= 0;
2017 svm
->vmcb
->control
.exit_info_1
= error_code
;
2018 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2020 vmexit
= nested_svm_intercept(svm
);
2021 if (vmexit
== NESTED_EXIT_DONE
)
2022 svm
->nested
.exit_required
= true;
2027 /* This function returns true if it is save to enable the irq window */
2028 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2030 if (!is_guest_mode(&svm
->vcpu
))
2033 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2036 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2040 * if vmexit was already requested (by intercepted exception
2041 * for instance) do not overwrite it with "external interrupt"
2044 if (svm
->nested
.exit_required
)
2047 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2048 svm
->vmcb
->control
.exit_info_1
= 0;
2049 svm
->vmcb
->control
.exit_info_2
= 0;
2051 if (svm
->nested
.intercept
& 1ULL) {
2053 * The #vmexit can't be emulated here directly because this
2054 * code path runs with irqs and preemption disabled. A
2055 * #vmexit emulation might sleep. Only signal request for
2058 svm
->nested
.exit_required
= true;
2059 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2066 /* This function returns true if it is save to enable the nmi window */
2067 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2069 if (!is_guest_mode(&svm
->vcpu
))
2072 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2075 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2076 svm
->nested
.exit_required
= true;
2081 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2087 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
2088 if (is_error_page(page
))
2096 kvm_inject_gp(&svm
->vcpu
, 0);
2101 static void nested_svm_unmap(struct page
*page
)
2104 kvm_release_page_dirty(page
);
2107 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2113 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2114 return NESTED_EXIT_HOST
;
2116 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2117 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2121 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
2124 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2127 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2129 u32 offset
, msr
, value
;
2132 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2133 return NESTED_EXIT_HOST
;
2135 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2136 offset
= svm_msrpm_offset(msr
);
2137 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2138 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2140 if (offset
== MSR_INVALID
)
2141 return NESTED_EXIT_DONE
;
2143 /* Offset is in 32 bit units but need in 8 bit units */
2146 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2147 return NESTED_EXIT_DONE
;
2149 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2152 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2154 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2156 switch (exit_code
) {
2159 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2160 return NESTED_EXIT_HOST
;
2162 /* For now we are always handling NPFs when using them */
2164 return NESTED_EXIT_HOST
;
2166 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2167 /* When we're shadowing, trap PFs, but not async PF */
2168 if (!npt_enabled
&& svm
->apf_reason
== 0)
2169 return NESTED_EXIT_HOST
;
2171 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2172 nm_interception(svm
);
2178 return NESTED_EXIT_CONTINUE
;
2182 * If this function returns true, this #vmexit was already handled
2184 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2186 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2187 int vmexit
= NESTED_EXIT_HOST
;
2189 switch (exit_code
) {
2191 vmexit
= nested_svm_exit_handled_msr(svm
);
2194 vmexit
= nested_svm_intercept_ioio(svm
);
2196 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2197 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2198 if (svm
->nested
.intercept_cr
& bit
)
2199 vmexit
= NESTED_EXIT_DONE
;
2202 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2203 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2204 if (svm
->nested
.intercept_dr
& bit
)
2205 vmexit
= NESTED_EXIT_DONE
;
2208 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2209 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2210 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2211 vmexit
= NESTED_EXIT_DONE
;
2212 /* async page fault always cause vmexit */
2213 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2214 svm
->apf_reason
!= 0)
2215 vmexit
= NESTED_EXIT_DONE
;
2218 case SVM_EXIT_ERR
: {
2219 vmexit
= NESTED_EXIT_DONE
;
2223 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2224 if (svm
->nested
.intercept
& exit_bits
)
2225 vmexit
= NESTED_EXIT_DONE
;
2232 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2236 vmexit
= nested_svm_intercept(svm
);
2238 if (vmexit
== NESTED_EXIT_DONE
)
2239 nested_svm_vmexit(svm
);
2244 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2246 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2247 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2249 dst
->intercept_cr
= from
->intercept_cr
;
2250 dst
->intercept_dr
= from
->intercept_dr
;
2251 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2252 dst
->intercept
= from
->intercept
;
2253 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2254 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2255 dst
->tsc_offset
= from
->tsc_offset
;
2256 dst
->asid
= from
->asid
;
2257 dst
->tlb_ctl
= from
->tlb_ctl
;
2258 dst
->int_ctl
= from
->int_ctl
;
2259 dst
->int_vector
= from
->int_vector
;
2260 dst
->int_state
= from
->int_state
;
2261 dst
->exit_code
= from
->exit_code
;
2262 dst
->exit_code_hi
= from
->exit_code_hi
;
2263 dst
->exit_info_1
= from
->exit_info_1
;
2264 dst
->exit_info_2
= from
->exit_info_2
;
2265 dst
->exit_int_info
= from
->exit_int_info
;
2266 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2267 dst
->nested_ctl
= from
->nested_ctl
;
2268 dst
->event_inj
= from
->event_inj
;
2269 dst
->event_inj_err
= from
->event_inj_err
;
2270 dst
->nested_cr3
= from
->nested_cr3
;
2271 dst
->lbr_ctl
= from
->lbr_ctl
;
2274 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2276 struct vmcb
*nested_vmcb
;
2277 struct vmcb
*hsave
= svm
->nested
.hsave
;
2278 struct vmcb
*vmcb
= svm
->vmcb
;
2281 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2282 vmcb
->control
.exit_info_1
,
2283 vmcb
->control
.exit_info_2
,
2284 vmcb
->control
.exit_int_info
,
2285 vmcb
->control
.exit_int_info_err
,
2288 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2292 /* Exit Guest-Mode */
2293 leave_guest_mode(&svm
->vcpu
);
2294 svm
->nested
.vmcb
= 0;
2296 /* Give the current vmcb to the guest */
2299 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2300 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2301 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2302 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2303 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2304 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2305 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2306 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2307 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2308 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2309 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2310 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2311 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2312 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2313 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2314 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2315 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2316 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2318 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2319 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2320 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2321 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2322 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2323 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2324 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2325 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2326 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2327 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2330 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2331 * to make sure that we do not lose injected events. So check event_inj
2332 * here and copy it to exit_int_info if it is valid.
2333 * Exit_int_info and event_inj can't be both valid because the case
2334 * below only happens on a VMRUN instruction intercept which has
2335 * no valid exit_int_info set.
2337 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2338 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2340 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2341 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2344 nested_vmcb
->control
.tlb_ctl
= 0;
2345 nested_vmcb
->control
.event_inj
= 0;
2346 nested_vmcb
->control
.event_inj_err
= 0;
2348 /* We always set V_INTR_MASKING and remember the old value in hflags */
2349 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2350 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2352 /* Restore the original control entries */
2353 copy_vmcb_control_area(vmcb
, hsave
);
2355 kvm_clear_exception_queue(&svm
->vcpu
);
2356 kvm_clear_interrupt_queue(&svm
->vcpu
);
2358 svm
->nested
.nested_cr3
= 0;
2360 /* Restore selected save entries */
2361 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2362 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2363 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2364 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2365 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2366 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2367 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2368 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2369 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2370 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2372 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2373 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2375 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2377 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2378 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2379 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2380 svm
->vmcb
->save
.dr7
= 0;
2381 svm
->vmcb
->save
.cpl
= 0;
2382 svm
->vmcb
->control
.exit_int_info
= 0;
2384 mark_all_dirty(svm
->vmcb
);
2386 nested_svm_unmap(page
);
2388 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2389 kvm_mmu_reset_context(&svm
->vcpu
);
2390 kvm_mmu_load(&svm
->vcpu
);
2395 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2398 * This function merges the msr permission bitmaps of kvm and the
2399 * nested vmcb. It is optimized in that it only merges the parts where
2400 * the kvm msr permission bitmap may contain zero bits
2404 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2407 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2411 if (msrpm_offsets
[i
] == 0xffffffff)
2414 p
= msrpm_offsets
[i
];
2415 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2417 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2420 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2423 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2428 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2430 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2433 if (vmcb
->control
.asid
== 0)
2436 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2442 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2444 struct vmcb
*nested_vmcb
;
2445 struct vmcb
*hsave
= svm
->nested
.hsave
;
2446 struct vmcb
*vmcb
= svm
->vmcb
;
2450 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2452 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2456 if (!nested_vmcb_checks(nested_vmcb
)) {
2457 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2458 nested_vmcb
->control
.exit_code_hi
= 0;
2459 nested_vmcb
->control
.exit_info_1
= 0;
2460 nested_vmcb
->control
.exit_info_2
= 0;
2462 nested_svm_unmap(page
);
2467 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2468 nested_vmcb
->save
.rip
,
2469 nested_vmcb
->control
.int_ctl
,
2470 nested_vmcb
->control
.event_inj
,
2471 nested_vmcb
->control
.nested_ctl
);
2473 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2474 nested_vmcb
->control
.intercept_cr
>> 16,
2475 nested_vmcb
->control
.intercept_exceptions
,
2476 nested_vmcb
->control
.intercept
);
2478 /* Clear internal status */
2479 kvm_clear_exception_queue(&svm
->vcpu
);
2480 kvm_clear_interrupt_queue(&svm
->vcpu
);
2483 * Save the old vmcb, so we don't need to pick what we save, but can
2484 * restore everything when a VMEXIT occurs
2486 hsave
->save
.es
= vmcb
->save
.es
;
2487 hsave
->save
.cs
= vmcb
->save
.cs
;
2488 hsave
->save
.ss
= vmcb
->save
.ss
;
2489 hsave
->save
.ds
= vmcb
->save
.ds
;
2490 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2491 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2492 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2493 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2494 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2495 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2496 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2497 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2498 hsave
->save
.rax
= vmcb
->save
.rax
;
2500 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2502 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2504 copy_vmcb_control_area(hsave
, vmcb
);
2506 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2507 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2509 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2511 if (nested_vmcb
->control
.nested_ctl
) {
2512 kvm_mmu_unload(&svm
->vcpu
);
2513 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2514 nested_svm_init_mmu_context(&svm
->vcpu
);
2517 /* Load the nested guest state */
2518 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2519 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2520 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2521 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2522 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2523 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2524 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2525 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2526 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2527 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2529 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2530 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2532 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2534 /* Guest paging mode is active - reset mmu */
2535 kvm_mmu_reset_context(&svm
->vcpu
);
2537 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2538 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2539 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2540 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2542 /* In case we don't even reach vcpu_run, the fields are not updated */
2543 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2544 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2545 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2546 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2547 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2548 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2550 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2551 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2553 /* cache intercepts */
2554 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2555 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2556 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2557 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2559 svm_flush_tlb(&svm
->vcpu
);
2560 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2561 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2562 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2564 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2566 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2567 /* We only want the cr8 intercept bits of the guest */
2568 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2569 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2572 /* We don't want to see VMMCALLs from a nested guest */
2573 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2575 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2576 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2577 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2578 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2579 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2580 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2582 nested_svm_unmap(page
);
2584 /* Enter Guest-Mode */
2585 enter_guest_mode(&svm
->vcpu
);
2588 * Merge guest and host intercepts - must be called with vcpu in
2589 * guest-mode to take affect here
2591 recalc_intercepts(svm
);
2593 svm
->nested
.vmcb
= vmcb_gpa
;
2597 mark_all_dirty(svm
->vmcb
);
2602 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2604 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2605 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2606 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2607 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2608 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2609 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2610 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2611 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2612 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2613 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2614 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2615 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2618 static int vmload_interception(struct vcpu_svm
*svm
)
2620 struct vmcb
*nested_vmcb
;
2623 if (nested_svm_check_permissions(svm
))
2626 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2630 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2631 skip_emulated_instruction(&svm
->vcpu
);
2633 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2634 nested_svm_unmap(page
);
2639 static int vmsave_interception(struct vcpu_svm
*svm
)
2641 struct vmcb
*nested_vmcb
;
2644 if (nested_svm_check_permissions(svm
))
2647 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2651 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2652 skip_emulated_instruction(&svm
->vcpu
);
2654 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2655 nested_svm_unmap(page
);
2660 static int vmrun_interception(struct vcpu_svm
*svm
)
2662 if (nested_svm_check_permissions(svm
))
2665 /* Save rip after vmrun instruction */
2666 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2668 if (!nested_svm_vmrun(svm
))
2671 if (!nested_svm_vmrun_msrpm(svm
))
2678 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2679 svm
->vmcb
->control
.exit_code_hi
= 0;
2680 svm
->vmcb
->control
.exit_info_1
= 0;
2681 svm
->vmcb
->control
.exit_info_2
= 0;
2683 nested_svm_vmexit(svm
);
2688 static int stgi_interception(struct vcpu_svm
*svm
)
2690 if (nested_svm_check_permissions(svm
))
2693 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2694 skip_emulated_instruction(&svm
->vcpu
);
2695 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2702 static int clgi_interception(struct vcpu_svm
*svm
)
2704 if (nested_svm_check_permissions(svm
))
2707 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2708 skip_emulated_instruction(&svm
->vcpu
);
2712 /* After a CLGI no interrupts should come */
2713 svm_clear_vintr(svm
);
2714 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2716 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2721 static int invlpga_interception(struct vcpu_svm
*svm
)
2723 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2725 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2726 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2728 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2729 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2731 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2732 skip_emulated_instruction(&svm
->vcpu
);
2736 static int skinit_interception(struct vcpu_svm
*svm
)
2738 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2740 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2744 static int xsetbv_interception(struct vcpu_svm
*svm
)
2746 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2747 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2749 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2750 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2751 skip_emulated_instruction(&svm
->vcpu
);
2757 static int invalid_op_interception(struct vcpu_svm
*svm
)
2759 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2763 static int task_switch_interception(struct vcpu_svm
*svm
)
2767 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2768 SVM_EXITINTINFO_TYPE_MASK
;
2769 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2771 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2773 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2774 bool has_error_code
= false;
2777 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2779 if (svm
->vmcb
->control
.exit_info_2
&
2780 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2781 reason
= TASK_SWITCH_IRET
;
2782 else if (svm
->vmcb
->control
.exit_info_2
&
2783 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2784 reason
= TASK_SWITCH_JMP
;
2786 reason
= TASK_SWITCH_GATE
;
2788 reason
= TASK_SWITCH_CALL
;
2790 if (reason
== TASK_SWITCH_GATE
) {
2792 case SVM_EXITINTINFO_TYPE_NMI
:
2793 svm
->vcpu
.arch
.nmi_injected
= false;
2795 case SVM_EXITINTINFO_TYPE_EXEPT
:
2796 if (svm
->vmcb
->control
.exit_info_2
&
2797 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2798 has_error_code
= true;
2800 (u32
)svm
->vmcb
->control
.exit_info_2
;
2802 kvm_clear_exception_queue(&svm
->vcpu
);
2804 case SVM_EXITINTINFO_TYPE_INTR
:
2805 kvm_clear_interrupt_queue(&svm
->vcpu
);
2812 if (reason
!= TASK_SWITCH_GATE
||
2813 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2814 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2815 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2816 skip_emulated_instruction(&svm
->vcpu
);
2818 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2821 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
2822 has_error_code
, error_code
) == EMULATE_FAIL
) {
2823 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2824 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2825 svm
->vcpu
.run
->internal
.ndata
= 0;
2831 static int cpuid_interception(struct vcpu_svm
*svm
)
2833 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2834 kvm_emulate_cpuid(&svm
->vcpu
);
2838 static int iret_interception(struct vcpu_svm
*svm
)
2840 ++svm
->vcpu
.stat
.nmi_window_exits
;
2841 clr_intercept(svm
, INTERCEPT_IRET
);
2842 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2843 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2844 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2848 static int invlpg_interception(struct vcpu_svm
*svm
)
2850 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2851 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2853 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2854 skip_emulated_instruction(&svm
->vcpu
);
2858 static int emulate_on_interception(struct vcpu_svm
*svm
)
2860 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2863 static int rdpmc_interception(struct vcpu_svm
*svm
)
2867 if (!static_cpu_has(X86_FEATURE_NRIPS
))
2868 return emulate_on_interception(svm
);
2870 err
= kvm_rdpmc(&svm
->vcpu
);
2871 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2876 bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
, unsigned long val
)
2878 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
2882 intercept
= svm
->nested
.intercept
;
2884 if (!is_guest_mode(&svm
->vcpu
) ||
2885 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
2888 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2889 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2892 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2893 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2899 #define CR_VALID (1ULL << 63)
2901 static int cr_interception(struct vcpu_svm
*svm
)
2907 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2908 return emulate_on_interception(svm
);
2910 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2911 return emulate_on_interception(svm
);
2913 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2914 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2917 if (cr
>= 16) { /* mov to cr */
2919 val
= kvm_register_read(&svm
->vcpu
, reg
);
2922 if (!check_selective_cr0_intercepted(svm
, val
))
2923 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2929 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2932 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2935 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2938 WARN(1, "unhandled write to CR%d", cr
);
2939 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2942 } else { /* mov from cr */
2945 val
= kvm_read_cr0(&svm
->vcpu
);
2948 val
= svm
->vcpu
.arch
.cr2
;
2951 val
= kvm_read_cr3(&svm
->vcpu
);
2954 val
= kvm_read_cr4(&svm
->vcpu
);
2957 val
= kvm_get_cr8(&svm
->vcpu
);
2960 WARN(1, "unhandled read from CR%d", cr
);
2961 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2964 kvm_register_write(&svm
->vcpu
, reg
, val
);
2966 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2971 static int dr_interception(struct vcpu_svm
*svm
)
2977 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2978 return emulate_on_interception(svm
);
2980 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2981 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2983 if (dr
>= 16) { /* mov to DRn */
2984 val
= kvm_register_read(&svm
->vcpu
, reg
);
2985 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
2987 err
= kvm_get_dr(&svm
->vcpu
, dr
, &val
);
2989 kvm_register_write(&svm
->vcpu
, reg
, val
);
2992 skip_emulated_instruction(&svm
->vcpu
);
2997 static int cr8_write_interception(struct vcpu_svm
*svm
)
2999 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3002 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3003 /* instruction emulation calls kvm_set_cr8() */
3004 r
= cr_interception(svm
);
3005 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
3006 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3009 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3011 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3015 u64
svm_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
3017 struct vmcb
*vmcb
= get_host_vmcb(to_svm(vcpu
));
3018 return vmcb
->control
.tsc_offset
+
3019 svm_scale_tsc(vcpu
, host_tsc
);
3022 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
3024 struct vcpu_svm
*svm
= to_svm(vcpu
);
3027 case MSR_IA32_TSC
: {
3028 *data
= svm
->vmcb
->control
.tsc_offset
+
3029 svm_scale_tsc(vcpu
, native_read_tsc());
3034 *data
= svm
->vmcb
->save
.star
;
3036 #ifdef CONFIG_X86_64
3038 *data
= svm
->vmcb
->save
.lstar
;
3041 *data
= svm
->vmcb
->save
.cstar
;
3043 case MSR_KERNEL_GS_BASE
:
3044 *data
= svm
->vmcb
->save
.kernel_gs_base
;
3046 case MSR_SYSCALL_MASK
:
3047 *data
= svm
->vmcb
->save
.sfmask
;
3050 case MSR_IA32_SYSENTER_CS
:
3051 *data
= svm
->vmcb
->save
.sysenter_cs
;
3053 case MSR_IA32_SYSENTER_EIP
:
3054 *data
= svm
->sysenter_eip
;
3056 case MSR_IA32_SYSENTER_ESP
:
3057 *data
= svm
->sysenter_esp
;
3060 * Nobody will change the following 5 values in the VMCB so we can
3061 * safely return them on rdmsr. They will always be 0 until LBRV is
3064 case MSR_IA32_DEBUGCTLMSR
:
3065 *data
= svm
->vmcb
->save
.dbgctl
;
3067 case MSR_IA32_LASTBRANCHFROMIP
:
3068 *data
= svm
->vmcb
->save
.br_from
;
3070 case MSR_IA32_LASTBRANCHTOIP
:
3071 *data
= svm
->vmcb
->save
.br_to
;
3073 case MSR_IA32_LASTINTFROMIP
:
3074 *data
= svm
->vmcb
->save
.last_excp_from
;
3076 case MSR_IA32_LASTINTTOIP
:
3077 *data
= svm
->vmcb
->save
.last_excp_to
;
3079 case MSR_VM_HSAVE_PA
:
3080 *data
= svm
->nested
.hsave_msr
;
3083 *data
= svm
->nested
.vm_cr_msr
;
3085 case MSR_IA32_UCODE_REV
:
3089 return kvm_get_msr_common(vcpu
, ecx
, data
);
3094 static int rdmsr_interception(struct vcpu_svm
*svm
)
3096 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3099 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
3100 trace_kvm_msr_read_ex(ecx
);
3101 kvm_inject_gp(&svm
->vcpu
, 0);
3103 trace_kvm_msr_read(ecx
, data
);
3105 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
3106 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
3107 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3108 skip_emulated_instruction(&svm
->vcpu
);
3113 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3115 struct vcpu_svm
*svm
= to_svm(vcpu
);
3116 int svm_dis
, chg_mask
;
3118 if (data
& ~SVM_VM_CR_VALID_MASK
)
3121 chg_mask
= SVM_VM_CR_VALID_MASK
;
3123 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3124 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3126 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3127 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3129 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3131 /* check for svm_disable while efer.svme is set */
3132 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3138 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3140 struct vcpu_svm
*svm
= to_svm(vcpu
);
3142 u32 ecx
= msr
->index
;
3143 u64 data
= msr
->data
;
3146 kvm_write_tsc(vcpu
, msr
);
3149 svm
->vmcb
->save
.star
= data
;
3151 #ifdef CONFIG_X86_64
3153 svm
->vmcb
->save
.lstar
= data
;
3156 svm
->vmcb
->save
.cstar
= data
;
3158 case MSR_KERNEL_GS_BASE
:
3159 svm
->vmcb
->save
.kernel_gs_base
= data
;
3161 case MSR_SYSCALL_MASK
:
3162 svm
->vmcb
->save
.sfmask
= data
;
3165 case MSR_IA32_SYSENTER_CS
:
3166 svm
->vmcb
->save
.sysenter_cs
= data
;
3168 case MSR_IA32_SYSENTER_EIP
:
3169 svm
->sysenter_eip
= data
;
3170 svm
->vmcb
->save
.sysenter_eip
= data
;
3172 case MSR_IA32_SYSENTER_ESP
:
3173 svm
->sysenter_esp
= data
;
3174 svm
->vmcb
->save
.sysenter_esp
= data
;
3176 case MSR_IA32_DEBUGCTLMSR
:
3177 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3178 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3182 if (data
& DEBUGCTL_RESERVED_BITS
)
3185 svm
->vmcb
->save
.dbgctl
= data
;
3186 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3187 if (data
& (1ULL<<0))
3188 svm_enable_lbrv(svm
);
3190 svm_disable_lbrv(svm
);
3192 case MSR_VM_HSAVE_PA
:
3193 svm
->nested
.hsave_msr
= data
;
3196 return svm_set_vm_cr(vcpu
, data
);
3198 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3201 return kvm_set_msr_common(vcpu
, msr
);
3206 static int wrmsr_interception(struct vcpu_svm
*svm
)
3208 struct msr_data msr
;
3209 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3210 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
3211 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3215 msr
.host_initiated
= false;
3217 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3218 if (svm_set_msr(&svm
->vcpu
, &msr
)) {
3219 trace_kvm_msr_write_ex(ecx
, data
);
3220 kvm_inject_gp(&svm
->vcpu
, 0);
3222 trace_kvm_msr_write(ecx
, data
);
3223 skip_emulated_instruction(&svm
->vcpu
);
3228 static int msr_interception(struct vcpu_svm
*svm
)
3230 if (svm
->vmcb
->control
.exit_info_1
)
3231 return wrmsr_interception(svm
);
3233 return rdmsr_interception(svm
);
3236 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3238 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3240 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3241 svm_clear_vintr(svm
);
3242 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3243 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3244 ++svm
->vcpu
.stat
.irq_window_exits
;
3246 * If the user space waits to inject interrupts, exit as soon as
3249 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
3250 kvm_run
->request_interrupt_window
&&
3251 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
3252 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3259 static int pause_interception(struct vcpu_svm
*svm
)
3261 kvm_vcpu_on_spin(&(svm
->vcpu
));
3265 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3266 [SVM_EXIT_READ_CR0
] = cr_interception
,
3267 [SVM_EXIT_READ_CR3
] = cr_interception
,
3268 [SVM_EXIT_READ_CR4
] = cr_interception
,
3269 [SVM_EXIT_READ_CR8
] = cr_interception
,
3270 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
3271 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3272 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3273 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3274 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3275 [SVM_EXIT_READ_DR0
] = dr_interception
,
3276 [SVM_EXIT_READ_DR1
] = dr_interception
,
3277 [SVM_EXIT_READ_DR2
] = dr_interception
,
3278 [SVM_EXIT_READ_DR3
] = dr_interception
,
3279 [SVM_EXIT_READ_DR4
] = dr_interception
,
3280 [SVM_EXIT_READ_DR5
] = dr_interception
,
3281 [SVM_EXIT_READ_DR6
] = dr_interception
,
3282 [SVM_EXIT_READ_DR7
] = dr_interception
,
3283 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3284 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3285 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3286 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3287 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3288 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3289 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3290 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3291 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3292 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3293 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3294 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3295 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3296 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3297 [SVM_EXIT_INTR
] = intr_interception
,
3298 [SVM_EXIT_NMI
] = nmi_interception
,
3299 [SVM_EXIT_SMI
] = nop_on_interception
,
3300 [SVM_EXIT_INIT
] = nop_on_interception
,
3301 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3302 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3303 [SVM_EXIT_CPUID
] = cpuid_interception
,
3304 [SVM_EXIT_IRET
] = iret_interception
,
3305 [SVM_EXIT_INVD
] = emulate_on_interception
,
3306 [SVM_EXIT_PAUSE
] = pause_interception
,
3307 [SVM_EXIT_HLT
] = halt_interception
,
3308 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3309 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3310 [SVM_EXIT_IOIO
] = io_interception
,
3311 [SVM_EXIT_MSR
] = msr_interception
,
3312 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3313 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3314 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3315 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3316 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3317 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3318 [SVM_EXIT_STGI
] = stgi_interception
,
3319 [SVM_EXIT_CLGI
] = clgi_interception
,
3320 [SVM_EXIT_SKINIT
] = skinit_interception
,
3321 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
3322 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
3323 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
3324 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3325 [SVM_EXIT_NPF
] = pf_interception
,
3328 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3330 struct vcpu_svm
*svm
= to_svm(vcpu
);
3331 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3332 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3334 pr_err("VMCB Control Area:\n");
3335 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
3336 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
3337 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
3338 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
3339 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
3340 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
3341 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3342 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3343 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3344 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3345 pr_err("%-20s%d\n", "asid:", control
->asid
);
3346 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3347 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3348 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3349 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3350 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3351 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3352 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3353 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3354 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3355 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3356 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3357 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3358 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3359 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
3360 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3361 pr_err("VMCB State Save Area:\n");
3362 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3364 save
->es
.selector
, save
->es
.attrib
,
3365 save
->es
.limit
, save
->es
.base
);
3366 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3368 save
->cs
.selector
, save
->cs
.attrib
,
3369 save
->cs
.limit
, save
->cs
.base
);
3370 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3372 save
->ss
.selector
, save
->ss
.attrib
,
3373 save
->ss
.limit
, save
->ss
.base
);
3374 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3376 save
->ds
.selector
, save
->ds
.attrib
,
3377 save
->ds
.limit
, save
->ds
.base
);
3378 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3380 save
->fs
.selector
, save
->fs
.attrib
,
3381 save
->fs
.limit
, save
->fs
.base
);
3382 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3384 save
->gs
.selector
, save
->gs
.attrib
,
3385 save
->gs
.limit
, save
->gs
.base
);
3386 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3388 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3389 save
->gdtr
.limit
, save
->gdtr
.base
);
3390 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3392 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3393 save
->ldtr
.limit
, save
->ldtr
.base
);
3394 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3396 save
->idtr
.selector
, save
->idtr
.attrib
,
3397 save
->idtr
.limit
, save
->idtr
.base
);
3398 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3400 save
->tr
.selector
, save
->tr
.attrib
,
3401 save
->tr
.limit
, save
->tr
.base
);
3402 pr_err("cpl: %d efer: %016llx\n",
3403 save
->cpl
, save
->efer
);
3404 pr_err("%-15s %016llx %-13s %016llx\n",
3405 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3406 pr_err("%-15s %016llx %-13s %016llx\n",
3407 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3408 pr_err("%-15s %016llx %-13s %016llx\n",
3409 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "rip:", save
->rip
, "rflags:", save
->rflags
);
3412 pr_err("%-15s %016llx %-13s %016llx\n",
3413 "rsp:", save
->rsp
, "rax:", save
->rax
);
3414 pr_err("%-15s %016llx %-13s %016llx\n",
3415 "star:", save
->star
, "lstar:", save
->lstar
);
3416 pr_err("%-15s %016llx %-13s %016llx\n",
3417 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "kernel_gs_base:", save
->kernel_gs_base
,
3420 "sysenter_cs:", save
->sysenter_cs
);
3421 pr_err("%-15s %016llx %-13s %016llx\n",
3422 "sysenter_esp:", save
->sysenter_esp
,
3423 "sysenter_eip:", save
->sysenter_eip
);
3424 pr_err("%-15s %016llx %-13s %016llx\n",
3425 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3426 pr_err("%-15s %016llx %-13s %016llx\n",
3427 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3428 pr_err("%-15s %016llx %-13s %016llx\n",
3429 "excp_from:", save
->last_excp_from
,
3430 "excp_to:", save
->last_excp_to
);
3433 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3435 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3437 *info1
= control
->exit_info_1
;
3438 *info2
= control
->exit_info_2
;
3441 static int handle_exit(struct kvm_vcpu
*vcpu
)
3443 struct vcpu_svm
*svm
= to_svm(vcpu
);
3444 struct kvm_run
*kvm_run
= vcpu
->run
;
3445 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3447 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3448 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3450 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3452 if (unlikely(svm
->nested
.exit_required
)) {
3453 nested_svm_vmexit(svm
);
3454 svm
->nested
.exit_required
= false;
3459 if (is_guest_mode(vcpu
)) {
3462 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3463 svm
->vmcb
->control
.exit_info_1
,
3464 svm
->vmcb
->control
.exit_info_2
,
3465 svm
->vmcb
->control
.exit_int_info
,
3466 svm
->vmcb
->control
.exit_int_info_err
,
3469 vmexit
= nested_svm_exit_special(svm
);
3471 if (vmexit
== NESTED_EXIT_CONTINUE
)
3472 vmexit
= nested_svm_exit_handled(svm
);
3474 if (vmexit
== NESTED_EXIT_DONE
)
3478 svm_complete_interrupts(svm
);
3480 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3481 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3482 kvm_run
->fail_entry
.hardware_entry_failure_reason
3483 = svm
->vmcb
->control
.exit_code
;
3484 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3489 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3490 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3491 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3492 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3493 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
3495 __func__
, svm
->vmcb
->control
.exit_int_info
,
3498 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3499 || !svm_exit_handlers
[exit_code
]) {
3500 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3501 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3505 return svm_exit_handlers
[exit_code
](svm
);
3508 static void reload_tss(struct kvm_vcpu
*vcpu
)
3510 int cpu
= raw_smp_processor_id();
3512 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3513 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3517 static void pre_svm_run(struct vcpu_svm
*svm
)
3519 int cpu
= raw_smp_processor_id();
3521 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3523 /* FIXME: handle wraparound of asid_generation */
3524 if (svm
->asid_generation
!= sd
->asid_generation
)
3528 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3530 struct vcpu_svm
*svm
= to_svm(vcpu
);
3532 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3533 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3534 set_intercept(svm
, INTERCEPT_IRET
);
3535 ++vcpu
->stat
.nmi_injections
;
3538 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3540 struct vmcb_control_area
*control
;
3542 control
= &svm
->vmcb
->control
;
3543 control
->int_vector
= irq
;
3544 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3545 control
->int_ctl
|= V_IRQ_MASK
|
3546 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3547 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3550 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3552 struct vcpu_svm
*svm
= to_svm(vcpu
);
3554 BUG_ON(!(gif_set(svm
)));
3556 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3557 ++vcpu
->stat
.irq_injections
;
3559 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3560 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3563 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3565 struct vcpu_svm
*svm
= to_svm(vcpu
);
3567 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3574 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3577 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
3582 static int svm_vm_has_apicv(struct kvm
*kvm
)
3587 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
3592 static void svm_hwapic_isr_update(struct kvm
*kvm
, int isr
)
3597 static void svm_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
3602 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3604 struct vcpu_svm
*svm
= to_svm(vcpu
);
3605 struct vmcb
*vmcb
= svm
->vmcb
;
3607 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3608 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3609 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3614 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3616 struct vcpu_svm
*svm
= to_svm(vcpu
);
3618 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3621 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3623 struct vcpu_svm
*svm
= to_svm(vcpu
);
3626 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3627 set_intercept(svm
, INTERCEPT_IRET
);
3629 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3630 clr_intercept(svm
, INTERCEPT_IRET
);
3634 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3636 struct vcpu_svm
*svm
= to_svm(vcpu
);
3637 struct vmcb
*vmcb
= svm
->vmcb
;
3640 if (!gif_set(svm
) ||
3641 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3644 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
3646 if (is_guest_mode(vcpu
))
3647 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3652 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3654 struct vcpu_svm
*svm
= to_svm(vcpu
);
3657 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3658 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3659 * get that intercept, this function will be called again though and
3660 * we'll get the vintr intercept.
3662 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3664 svm_inject_irq(svm
, 0x0);
3668 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3670 struct vcpu_svm
*svm
= to_svm(vcpu
);
3672 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3674 return; /* IRET will cause a vm exit */
3677 * Something prevents NMI from been injected. Single step over possible
3678 * problem (IRET or exception injection or interrupt shadow)
3680 svm
->nmi_singlestep
= true;
3681 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3682 update_db_bp_intercept(vcpu
);
3685 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3690 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3692 struct vcpu_svm
*svm
= to_svm(vcpu
);
3694 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3695 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3697 svm
->asid_generation
--;
3700 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3704 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3706 struct vcpu_svm
*svm
= to_svm(vcpu
);
3708 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3711 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3712 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3713 kvm_set_cr8(vcpu
, cr8
);
3717 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3719 struct vcpu_svm
*svm
= to_svm(vcpu
);
3722 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3725 cr8
= kvm_get_cr8(vcpu
);
3726 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3727 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3730 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3734 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3735 unsigned int3_injected
= svm
->int3_injected
;
3737 svm
->int3_injected
= 0;
3740 * If we've made progress since setting HF_IRET_MASK, we've
3741 * executed an IRET and can allow NMI injection.
3743 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3744 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
3745 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3746 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3749 svm
->vcpu
.arch
.nmi_injected
= false;
3750 kvm_clear_exception_queue(&svm
->vcpu
);
3751 kvm_clear_interrupt_queue(&svm
->vcpu
);
3753 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3756 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3758 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3759 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3762 case SVM_EXITINTINFO_TYPE_NMI
:
3763 svm
->vcpu
.arch
.nmi_injected
= true;
3765 case SVM_EXITINTINFO_TYPE_EXEPT
:
3767 * In case of software exceptions, do not reinject the vector,
3768 * but re-execute the instruction instead. Rewind RIP first
3769 * if we emulated INT3 before.
3771 if (kvm_exception_is_soft(vector
)) {
3772 if (vector
== BP_VECTOR
&& int3_injected
&&
3773 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3774 kvm_rip_write(&svm
->vcpu
,
3775 kvm_rip_read(&svm
->vcpu
) -
3779 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3780 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3781 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3784 kvm_requeue_exception(&svm
->vcpu
, vector
);
3786 case SVM_EXITINTINFO_TYPE_INTR
:
3787 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3794 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3796 struct vcpu_svm
*svm
= to_svm(vcpu
);
3797 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3799 control
->exit_int_info
= control
->event_inj
;
3800 control
->exit_int_info_err
= control
->event_inj_err
;
3801 control
->event_inj
= 0;
3802 svm_complete_interrupts(svm
);
3805 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3807 struct vcpu_svm
*svm
= to_svm(vcpu
);
3809 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3810 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3811 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3814 * A vmexit emulation is required before the vcpu can be executed
3817 if (unlikely(svm
->nested
.exit_required
))
3822 sync_lapic_to_cr8(vcpu
);
3824 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3831 "push %%" _ASM_BP
"; \n\t"
3832 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
3833 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
3834 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
3835 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
3836 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
3837 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
3838 #ifdef CONFIG_X86_64
3839 "mov %c[r8](%[svm]), %%r8 \n\t"
3840 "mov %c[r9](%[svm]), %%r9 \n\t"
3841 "mov %c[r10](%[svm]), %%r10 \n\t"
3842 "mov %c[r11](%[svm]), %%r11 \n\t"
3843 "mov %c[r12](%[svm]), %%r12 \n\t"
3844 "mov %c[r13](%[svm]), %%r13 \n\t"
3845 "mov %c[r14](%[svm]), %%r14 \n\t"
3846 "mov %c[r15](%[svm]), %%r15 \n\t"
3849 /* Enter guest mode */
3850 "push %%" _ASM_AX
" \n\t"
3851 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
3852 __ex(SVM_VMLOAD
) "\n\t"
3853 __ex(SVM_VMRUN
) "\n\t"
3854 __ex(SVM_VMSAVE
) "\n\t"
3855 "pop %%" _ASM_AX
" \n\t"
3857 /* Save guest registers, load host registers */
3858 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
3859 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
3860 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
3861 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
3862 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
3863 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
3864 #ifdef CONFIG_X86_64
3865 "mov %%r8, %c[r8](%[svm]) \n\t"
3866 "mov %%r9, %c[r9](%[svm]) \n\t"
3867 "mov %%r10, %c[r10](%[svm]) \n\t"
3868 "mov %%r11, %c[r11](%[svm]) \n\t"
3869 "mov %%r12, %c[r12](%[svm]) \n\t"
3870 "mov %%r13, %c[r13](%[svm]) \n\t"
3871 "mov %%r14, %c[r14](%[svm]) \n\t"
3872 "mov %%r15, %c[r15](%[svm]) \n\t"
3877 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3878 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3879 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3880 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3881 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3882 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3883 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3884 #ifdef CONFIG_X86_64
3885 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3886 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3887 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3888 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3889 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3890 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3891 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3892 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3895 #ifdef CONFIG_X86_64
3896 , "rbx", "rcx", "rdx", "rsi", "rdi"
3897 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3899 , "ebx", "ecx", "edx", "esi", "edi"
3903 #ifdef CONFIG_X86_64
3904 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3906 loadsegment(fs
, svm
->host
.fs
);
3907 #ifndef CONFIG_X86_32_LAZY_GS
3908 loadsegment(gs
, svm
->host
.gs
);
3914 local_irq_disable();
3916 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3917 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3918 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3919 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3921 trace_kvm_exit(svm
->vmcb
->control
.exit_code
, vcpu
, KVM_ISA_SVM
);
3923 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3924 kvm_before_handle_nmi(&svm
->vcpu
);
3928 /* Any pending NMI will happen here */
3930 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3931 kvm_after_handle_nmi(&svm
->vcpu
);
3933 sync_cr8_to_lapic(vcpu
);
3937 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3939 /* if exit due to PF check for async PF */
3940 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3941 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3944 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3945 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3949 * We need to handle MC intercepts here before the vcpu has a chance to
3950 * change the physical cpu
3952 if (unlikely(svm
->vmcb
->control
.exit_code
==
3953 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3954 svm_handle_mce(svm
);
3956 mark_all_clean(svm
->vmcb
);
3959 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3961 struct vcpu_svm
*svm
= to_svm(vcpu
);
3963 svm
->vmcb
->save
.cr3
= root
;
3964 mark_dirty(svm
->vmcb
, VMCB_CR
);
3965 svm_flush_tlb(vcpu
);
3968 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3970 struct vcpu_svm
*svm
= to_svm(vcpu
);
3972 svm
->vmcb
->control
.nested_cr3
= root
;
3973 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3975 /* Also sync guest cr3 here in case we live migrate */
3976 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
3977 mark_dirty(svm
->vmcb
, VMCB_CR
);
3979 svm_flush_tlb(vcpu
);
3982 static int is_disabled(void)
3986 rdmsrl(MSR_VM_CR
, vm_cr
);
3987 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3994 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3997 * Patch in the VMMCALL instruction:
3999 hypercall
[0] = 0x0f;
4000 hypercall
[1] = 0x01;
4001 hypercall
[2] = 0xd9;
4004 static void svm_check_processor_compat(void *rtn
)
4009 static bool svm_cpu_has_accelerated_tpr(void)
4014 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4019 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
4023 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4028 entry
->ecx
|= (1 << 2); /* Set SVM bit */
4031 entry
->eax
= 1; /* SVM revision 1 */
4032 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
4033 ASID emulation to nested SVM */
4034 entry
->ecx
= 0; /* Reserved */
4035 entry
->edx
= 0; /* Per default do not support any
4036 additional features */
4038 /* Support next_rip if host supports it */
4039 if (boot_cpu_has(X86_FEATURE_NRIPS
))
4040 entry
->edx
|= SVM_FEATURE_NRIP
;
4042 /* Support NPT for the guest if enabled */
4044 entry
->edx
|= SVM_FEATURE_NPT
;
4050 static int svm_get_lpage_level(void)
4052 return PT_PDPE_LEVEL
;
4055 static bool svm_rdtscp_supported(void)
4060 static bool svm_invpcid_supported(void)
4065 static bool svm_has_wbinvd_exit(void)
4070 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
4072 struct vcpu_svm
*svm
= to_svm(vcpu
);
4074 set_exception_intercept(svm
, NM_VECTOR
);
4075 update_cr0_intercept(svm
);
4078 #define PRE_EX(exit) { .exit_code = (exit), \
4079 .stage = X86_ICPT_PRE_EXCEPT, }
4080 #define POST_EX(exit) { .exit_code = (exit), \
4081 .stage = X86_ICPT_POST_EXCEPT, }
4082 #define POST_MEM(exit) { .exit_code = (exit), \
4083 .stage = X86_ICPT_POST_MEMACCESS, }
4085 static const struct __x86_intercept
{
4087 enum x86_intercept_stage stage
;
4088 } x86_intercept_map
[] = {
4089 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4090 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4091 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4092 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4093 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4094 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4095 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4096 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4097 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4098 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4099 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4100 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4101 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4102 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4103 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4104 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4105 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4106 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4107 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4108 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4109 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4110 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4111 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4112 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4113 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4114 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4115 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4116 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4117 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4118 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4119 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4120 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4121 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4122 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4123 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4124 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4125 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4126 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4127 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4128 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4129 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4130 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4131 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4132 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4133 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4134 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4141 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4142 struct x86_instruction_info
*info
,
4143 enum x86_intercept_stage stage
)
4145 struct vcpu_svm
*svm
= to_svm(vcpu
);
4146 int vmexit
, ret
= X86EMUL_CONTINUE
;
4147 struct __x86_intercept icpt_info
;
4148 struct vmcb
*vmcb
= svm
->vmcb
;
4150 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4153 icpt_info
= x86_intercept_map
[info
->intercept
];
4155 if (stage
!= icpt_info
.stage
)
4158 switch (icpt_info
.exit_code
) {
4159 case SVM_EXIT_READ_CR0
:
4160 if (info
->intercept
== x86_intercept_cr_read
)
4161 icpt_info
.exit_code
+= info
->modrm_reg
;
4163 case SVM_EXIT_WRITE_CR0
: {
4164 unsigned long cr0
, val
;
4167 if (info
->intercept
== x86_intercept_cr_write
)
4168 icpt_info
.exit_code
+= info
->modrm_reg
;
4170 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
)
4173 intercept
= svm
->nested
.intercept
;
4175 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
4178 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4179 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4181 if (info
->intercept
== x86_intercept_lmsw
) {
4184 /* lmsw can't clear PE - catch this here */
4185 if (cr0
& X86_CR0_PE
)
4190 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4194 case SVM_EXIT_READ_DR0
:
4195 case SVM_EXIT_WRITE_DR0
:
4196 icpt_info
.exit_code
+= info
->modrm_reg
;
4199 if (info
->intercept
== x86_intercept_wrmsr
)
4200 vmcb
->control
.exit_info_1
= 1;
4202 vmcb
->control
.exit_info_1
= 0;
4204 case SVM_EXIT_PAUSE
:
4206 * We get this for NOP only, but pause
4207 * is rep not, check this here
4209 if (info
->rep_prefix
!= REPE_PREFIX
)
4211 case SVM_EXIT_IOIO
: {
4215 exit_info
= (vcpu
->arch
.regs
[VCPU_REGS_RDX
] & 0xffff) << 16;
4217 if (info
->intercept
== x86_intercept_in
||
4218 info
->intercept
== x86_intercept_ins
) {
4219 exit_info
|= SVM_IOIO_TYPE_MASK
;
4220 bytes
= info
->src_bytes
;
4222 bytes
= info
->dst_bytes
;
4225 if (info
->intercept
== x86_intercept_outs
||
4226 info
->intercept
== x86_intercept_ins
)
4227 exit_info
|= SVM_IOIO_STR_MASK
;
4229 if (info
->rep_prefix
)
4230 exit_info
|= SVM_IOIO_REP_MASK
;
4232 bytes
= min(bytes
, 4u);
4234 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4236 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4238 vmcb
->control
.exit_info_1
= exit_info
;
4239 vmcb
->control
.exit_info_2
= info
->next_rip
;
4247 vmcb
->control
.next_rip
= info
->next_rip
;
4248 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4249 vmexit
= nested_svm_exit_handled(svm
);
4251 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4258 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
4263 static struct kvm_x86_ops svm_x86_ops
= {
4264 .cpu_has_kvm_support
= has_svm
,
4265 .disabled_by_bios
= is_disabled
,
4266 .hardware_setup
= svm_hardware_setup
,
4267 .hardware_unsetup
= svm_hardware_unsetup
,
4268 .check_processor_compatibility
= svm_check_processor_compat
,
4269 .hardware_enable
= svm_hardware_enable
,
4270 .hardware_disable
= svm_hardware_disable
,
4271 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4273 .vcpu_create
= svm_create_vcpu
,
4274 .vcpu_free
= svm_free_vcpu
,
4275 .vcpu_reset
= svm_vcpu_reset
,
4277 .prepare_guest_switch
= svm_prepare_guest_switch
,
4278 .vcpu_load
= svm_vcpu_load
,
4279 .vcpu_put
= svm_vcpu_put
,
4281 .update_db_bp_intercept
= update_db_bp_intercept
,
4282 .get_msr
= svm_get_msr
,
4283 .set_msr
= svm_set_msr
,
4284 .get_segment_base
= svm_get_segment_base
,
4285 .get_segment
= svm_get_segment
,
4286 .set_segment
= svm_set_segment
,
4287 .get_cpl
= svm_get_cpl
,
4288 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4289 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
4290 .decache_cr3
= svm_decache_cr3
,
4291 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
4292 .set_cr0
= svm_set_cr0
,
4293 .set_cr3
= svm_set_cr3
,
4294 .set_cr4
= svm_set_cr4
,
4295 .set_efer
= svm_set_efer
,
4296 .get_idt
= svm_get_idt
,
4297 .set_idt
= svm_set_idt
,
4298 .get_gdt
= svm_get_gdt
,
4299 .set_gdt
= svm_set_gdt
,
4300 .get_dr6
= svm_get_dr6
,
4301 .set_dr6
= svm_set_dr6
,
4302 .set_dr7
= svm_set_dr7
,
4303 .cache_reg
= svm_cache_reg
,
4304 .get_rflags
= svm_get_rflags
,
4305 .set_rflags
= svm_set_rflags
,
4306 .fpu_activate
= svm_fpu_activate
,
4307 .fpu_deactivate
= svm_fpu_deactivate
,
4309 .tlb_flush
= svm_flush_tlb
,
4311 .run
= svm_vcpu_run
,
4312 .handle_exit
= handle_exit
,
4313 .skip_emulated_instruction
= skip_emulated_instruction
,
4314 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4315 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4316 .patch_hypercall
= svm_patch_hypercall
,
4317 .set_irq
= svm_set_irq
,
4318 .set_nmi
= svm_inject_nmi
,
4319 .queue_exception
= svm_queue_exception
,
4320 .cancel_injection
= svm_cancel_injection
,
4321 .interrupt_allowed
= svm_interrupt_allowed
,
4322 .nmi_allowed
= svm_nmi_allowed
,
4323 .get_nmi_mask
= svm_get_nmi_mask
,
4324 .set_nmi_mask
= svm_set_nmi_mask
,
4325 .enable_nmi_window
= enable_nmi_window
,
4326 .enable_irq_window
= enable_irq_window
,
4327 .update_cr8_intercept
= update_cr8_intercept
,
4328 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
4329 .vm_has_apicv
= svm_vm_has_apicv
,
4330 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
4331 .hwapic_isr_update
= svm_hwapic_isr_update
,
4332 .sync_pir_to_irr
= svm_sync_pir_to_irr
,
4334 .set_tss_addr
= svm_set_tss_addr
,
4335 .get_tdp_level
= get_npt_level
,
4336 .get_mt_mask
= svm_get_mt_mask
,
4338 .get_exit_info
= svm_get_exit_info
,
4340 .get_lpage_level
= svm_get_lpage_level
,
4342 .cpuid_update
= svm_cpuid_update
,
4344 .rdtscp_supported
= svm_rdtscp_supported
,
4345 .invpcid_supported
= svm_invpcid_supported
,
4347 .set_supported_cpuid
= svm_set_supported_cpuid
,
4349 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4351 .set_tsc_khz
= svm_set_tsc_khz
,
4352 .read_tsc_offset
= svm_read_tsc_offset
,
4353 .write_tsc_offset
= svm_write_tsc_offset
,
4354 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
4355 .compute_tsc_offset
= svm_compute_tsc_offset
,
4356 .read_l1_tsc
= svm_read_l1_tsc
,
4358 .set_tdp_cr3
= set_tdp_cr3
,
4360 .check_intercept
= svm_check_intercept
,
4361 .handle_external_intr
= svm_handle_external_intr
,
4364 static int __init
svm_init(void)
4366 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
4367 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4370 static void __exit
svm_exit(void)
4375 module_init(svm_init
)
4376 module_exit(svm_exit
)