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KVM: Pull extra page fault information into struct x86_exception
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
108 /* Nested Paging related state */
109 u64 nested_cr3;
110 };
111
112 #define MSRPM_OFFSETS 16
113 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
115 struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
127 struct {
128 u16 fs;
129 u16 gs;
130 u16 ldt;
131 u64 gs_base;
132 } host;
133
134 u32 *msrpm;
135
136 struct nested_state nested;
137
138 bool nmi_singlestep;
139
140 unsigned int3_injected;
141 unsigned long int3_rip;
142 u32 apf_reason;
143 };
144
145 #define MSR_INVALID 0xffffffffU
146
147 static struct svm_direct_access_msrs {
148 u32 index; /* Index of the MSR */
149 bool always; /* True if intercept is always on */
150 } direct_access_msrs[] = {
151 { .index = MSR_STAR, .always = true },
152 { .index = MSR_IA32_SYSENTER_CS, .always = true },
153 #ifdef CONFIG_X86_64
154 { .index = MSR_GS_BASE, .always = true },
155 { .index = MSR_FS_BASE, .always = true },
156 { .index = MSR_KERNEL_GS_BASE, .always = true },
157 { .index = MSR_LSTAR, .always = true },
158 { .index = MSR_CSTAR, .always = true },
159 { .index = MSR_SYSCALL_MASK, .always = true },
160 #endif
161 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
162 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
163 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
164 { .index = MSR_IA32_LASTINTTOIP, .always = false },
165 { .index = MSR_INVALID, .always = false },
166 };
167
168 /* enable NPT for AMD64 and X86 with PAE */
169 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
170 static bool npt_enabled = true;
171 #else
172 static bool npt_enabled;
173 #endif
174 static int npt = 1;
175
176 module_param(npt, int, S_IRUGO);
177
178 static int nested = 1;
179 module_param(nested, int, S_IRUGO);
180
181 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
182 static void svm_complete_interrupts(struct vcpu_svm *svm);
183
184 static int nested_svm_exit_handled(struct vcpu_svm *svm);
185 static int nested_svm_intercept(struct vcpu_svm *svm);
186 static int nested_svm_vmexit(struct vcpu_svm *svm);
187 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
188 bool has_error_code, u32 error_code);
189
190 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
191 {
192 return container_of(vcpu, struct vcpu_svm, vcpu);
193 }
194
195 static inline bool is_nested(struct vcpu_svm *svm)
196 {
197 return svm->nested.vmcb;
198 }
199
200 static inline void enable_gif(struct vcpu_svm *svm)
201 {
202 svm->vcpu.arch.hflags |= HF_GIF_MASK;
203 }
204
205 static inline void disable_gif(struct vcpu_svm *svm)
206 {
207 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
208 }
209
210 static inline bool gif_set(struct vcpu_svm *svm)
211 {
212 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
213 }
214
215 static unsigned long iopm_base;
216
217 struct kvm_ldttss_desc {
218 u16 limit0;
219 u16 base0;
220 unsigned base1:8, type:5, dpl:2, p:1;
221 unsigned limit1:4, zero0:3, g:1, base2:8;
222 u32 base3;
223 u32 zero1;
224 } __attribute__((packed));
225
226 struct svm_cpu_data {
227 int cpu;
228
229 u64 asid_generation;
230 u32 max_asid;
231 u32 next_asid;
232 struct kvm_ldttss_desc *tss_desc;
233
234 struct page *save_area;
235 };
236
237 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
238 static uint32_t svm_features;
239
240 struct svm_init_data {
241 int cpu;
242 int r;
243 };
244
245 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
246
247 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
248 #define MSRS_RANGE_SIZE 2048
249 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
250
251 static u32 svm_msrpm_offset(u32 msr)
252 {
253 u32 offset;
254 int i;
255
256 for (i = 0; i < NUM_MSR_MAPS; i++) {
257 if (msr < msrpm_ranges[i] ||
258 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
259 continue;
260
261 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
262 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
263
264 /* Now we have the u8 offset - but need the u32 offset */
265 return offset / 4;
266 }
267
268 /* MSR not in any range */
269 return MSR_INVALID;
270 }
271
272 #define MAX_INST_SIZE 15
273
274 static inline void clgi(void)
275 {
276 asm volatile (__ex(SVM_CLGI));
277 }
278
279 static inline void stgi(void)
280 {
281 asm volatile (__ex(SVM_STGI));
282 }
283
284 static inline void invlpga(unsigned long addr, u32 asid)
285 {
286 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
287 }
288
289 static inline void force_new_asid(struct kvm_vcpu *vcpu)
290 {
291 to_svm(vcpu)->asid_generation--;
292 }
293
294 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
295 {
296 force_new_asid(vcpu);
297 }
298
299 static int get_npt_level(void)
300 {
301 #ifdef CONFIG_X86_64
302 return PT64_ROOT_LEVEL;
303 #else
304 return PT32E_ROOT_LEVEL;
305 #endif
306 }
307
308 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
309 {
310 vcpu->arch.efer = efer;
311 if (!npt_enabled && !(efer & EFER_LMA))
312 efer &= ~EFER_LME;
313
314 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
315 }
316
317 static int is_external_interrupt(u32 info)
318 {
319 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
320 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
321 }
322
323 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
324 {
325 struct vcpu_svm *svm = to_svm(vcpu);
326 u32 ret = 0;
327
328 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
329 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
330 return ret & mask;
331 }
332
333 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
334 {
335 struct vcpu_svm *svm = to_svm(vcpu);
336
337 if (mask == 0)
338 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
339 else
340 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
341
342 }
343
344 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
345 {
346 struct vcpu_svm *svm = to_svm(vcpu);
347
348 if (svm->vmcb->control.next_rip != 0)
349 svm->next_rip = svm->vmcb->control.next_rip;
350
351 if (!svm->next_rip) {
352 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
353 EMULATE_DONE)
354 printk(KERN_DEBUG "%s: NOP\n", __func__);
355 return;
356 }
357 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
358 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
359 __func__, kvm_rip_read(vcpu), svm->next_rip);
360
361 kvm_rip_write(vcpu, svm->next_rip);
362 svm_set_interrupt_shadow(vcpu, 0);
363 }
364
365 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
366 bool has_error_code, u32 error_code,
367 bool reinject)
368 {
369 struct vcpu_svm *svm = to_svm(vcpu);
370
371 /*
372 * If we are within a nested VM we'd better #VMEXIT and let the guest
373 * handle the exception
374 */
375 if (!reinject &&
376 nested_svm_check_exception(svm, nr, has_error_code, error_code))
377 return;
378
379 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
380 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
381
382 /*
383 * For guest debugging where we have to reinject #BP if some
384 * INT3 is guest-owned:
385 * Emulate nRIP by moving RIP forward. Will fail if injection
386 * raises a fault that is not intercepted. Still better than
387 * failing in all cases.
388 */
389 skip_emulated_instruction(&svm->vcpu);
390 rip = kvm_rip_read(&svm->vcpu);
391 svm->int3_rip = rip + svm->vmcb->save.cs.base;
392 svm->int3_injected = rip - old_rip;
393 }
394
395 svm->vmcb->control.event_inj = nr
396 | SVM_EVTINJ_VALID
397 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
398 | SVM_EVTINJ_TYPE_EXEPT;
399 svm->vmcb->control.event_inj_err = error_code;
400 }
401
402 static void svm_init_erratum_383(void)
403 {
404 u32 low, high;
405 int err;
406 u64 val;
407
408 if (!cpu_has_amd_erratum(amd_erratum_383))
409 return;
410
411 /* Use _safe variants to not break nested virtualization */
412 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
413 if (err)
414 return;
415
416 val |= (1ULL << 47);
417
418 low = lower_32_bits(val);
419 high = upper_32_bits(val);
420
421 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
422
423 erratum_383_found = true;
424 }
425
426 static int has_svm(void)
427 {
428 const char *msg;
429
430 if (!cpu_has_svm(&msg)) {
431 printk(KERN_INFO "has_svm: %s\n", msg);
432 return 0;
433 }
434
435 return 1;
436 }
437
438 static void svm_hardware_disable(void *garbage)
439 {
440 cpu_svm_disable();
441 }
442
443 static int svm_hardware_enable(void *garbage)
444 {
445
446 struct svm_cpu_data *sd;
447 uint64_t efer;
448 struct desc_ptr gdt_descr;
449 struct desc_struct *gdt;
450 int me = raw_smp_processor_id();
451
452 rdmsrl(MSR_EFER, efer);
453 if (efer & EFER_SVME)
454 return -EBUSY;
455
456 if (!has_svm()) {
457 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
458 me);
459 return -EINVAL;
460 }
461 sd = per_cpu(svm_data, me);
462
463 if (!sd) {
464 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
465 me);
466 return -EINVAL;
467 }
468
469 sd->asid_generation = 1;
470 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
471 sd->next_asid = sd->max_asid + 1;
472
473 native_store_gdt(&gdt_descr);
474 gdt = (struct desc_struct *)gdt_descr.address;
475 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
476
477 wrmsrl(MSR_EFER, efer | EFER_SVME);
478
479 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
480
481 svm_init_erratum_383();
482
483 return 0;
484 }
485
486 static void svm_cpu_uninit(int cpu)
487 {
488 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
489
490 if (!sd)
491 return;
492
493 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
494 __free_page(sd->save_area);
495 kfree(sd);
496 }
497
498 static int svm_cpu_init(int cpu)
499 {
500 struct svm_cpu_data *sd;
501 int r;
502
503 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
504 if (!sd)
505 return -ENOMEM;
506 sd->cpu = cpu;
507 sd->save_area = alloc_page(GFP_KERNEL);
508 r = -ENOMEM;
509 if (!sd->save_area)
510 goto err_1;
511
512 per_cpu(svm_data, cpu) = sd;
513
514 return 0;
515
516 err_1:
517 kfree(sd);
518 return r;
519
520 }
521
522 static bool valid_msr_intercept(u32 index)
523 {
524 int i;
525
526 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
527 if (direct_access_msrs[i].index == index)
528 return true;
529
530 return false;
531 }
532
533 static void set_msr_interception(u32 *msrpm, unsigned msr,
534 int read, int write)
535 {
536 u8 bit_read, bit_write;
537 unsigned long tmp;
538 u32 offset;
539
540 /*
541 * If this warning triggers extend the direct_access_msrs list at the
542 * beginning of the file
543 */
544 WARN_ON(!valid_msr_intercept(msr));
545
546 offset = svm_msrpm_offset(msr);
547 bit_read = 2 * (msr & 0x0f);
548 bit_write = 2 * (msr & 0x0f) + 1;
549 tmp = msrpm[offset];
550
551 BUG_ON(offset == MSR_INVALID);
552
553 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
554 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
555
556 msrpm[offset] = tmp;
557 }
558
559 static void svm_vcpu_init_msrpm(u32 *msrpm)
560 {
561 int i;
562
563 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
564
565 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
566 if (!direct_access_msrs[i].always)
567 continue;
568
569 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
570 }
571 }
572
573 static void add_msr_offset(u32 offset)
574 {
575 int i;
576
577 for (i = 0; i < MSRPM_OFFSETS; ++i) {
578
579 /* Offset already in list? */
580 if (msrpm_offsets[i] == offset)
581 return;
582
583 /* Slot used by another offset? */
584 if (msrpm_offsets[i] != MSR_INVALID)
585 continue;
586
587 /* Add offset to list */
588 msrpm_offsets[i] = offset;
589
590 return;
591 }
592
593 /*
594 * If this BUG triggers the msrpm_offsets table has an overflow. Just
595 * increase MSRPM_OFFSETS in this case.
596 */
597 BUG();
598 }
599
600 static void init_msrpm_offsets(void)
601 {
602 int i;
603
604 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
605
606 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
607 u32 offset;
608
609 offset = svm_msrpm_offset(direct_access_msrs[i].index);
610 BUG_ON(offset == MSR_INVALID);
611
612 add_msr_offset(offset);
613 }
614 }
615
616 static void svm_enable_lbrv(struct vcpu_svm *svm)
617 {
618 u32 *msrpm = svm->msrpm;
619
620 svm->vmcb->control.lbr_ctl = 1;
621 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
622 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
623 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
624 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
625 }
626
627 static void svm_disable_lbrv(struct vcpu_svm *svm)
628 {
629 u32 *msrpm = svm->msrpm;
630
631 svm->vmcb->control.lbr_ctl = 0;
632 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
633 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
634 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
635 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
636 }
637
638 static __init int svm_hardware_setup(void)
639 {
640 int cpu;
641 struct page *iopm_pages;
642 void *iopm_va;
643 int r;
644
645 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
646
647 if (!iopm_pages)
648 return -ENOMEM;
649
650 iopm_va = page_address(iopm_pages);
651 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
652 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
653
654 init_msrpm_offsets();
655
656 if (boot_cpu_has(X86_FEATURE_NX))
657 kvm_enable_efer_bits(EFER_NX);
658
659 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
660 kvm_enable_efer_bits(EFER_FFXSR);
661
662 if (nested) {
663 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
664 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
665 }
666
667 for_each_possible_cpu(cpu) {
668 r = svm_cpu_init(cpu);
669 if (r)
670 goto err;
671 }
672
673 svm_features = cpuid_edx(SVM_CPUID_FUNC);
674
675 if (!boot_cpu_has(X86_FEATURE_NPT))
676 npt_enabled = false;
677
678 if (npt_enabled && !npt) {
679 printk(KERN_INFO "kvm: Nested Paging disabled\n");
680 npt_enabled = false;
681 }
682
683 if (npt_enabled) {
684 printk(KERN_INFO "kvm: Nested Paging enabled\n");
685 kvm_enable_tdp();
686 } else
687 kvm_disable_tdp();
688
689 return 0;
690
691 err:
692 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
693 iopm_base = 0;
694 return r;
695 }
696
697 static __exit void svm_hardware_unsetup(void)
698 {
699 int cpu;
700
701 for_each_possible_cpu(cpu)
702 svm_cpu_uninit(cpu);
703
704 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
705 iopm_base = 0;
706 }
707
708 static void init_seg(struct vmcb_seg *seg)
709 {
710 seg->selector = 0;
711 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
712 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
713 seg->limit = 0xffff;
714 seg->base = 0;
715 }
716
717 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
718 {
719 seg->selector = 0;
720 seg->attrib = SVM_SELECTOR_P_MASK | type;
721 seg->limit = 0xffff;
722 seg->base = 0;
723 }
724
725 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
726 {
727 struct vcpu_svm *svm = to_svm(vcpu);
728 u64 g_tsc_offset = 0;
729
730 if (is_nested(svm)) {
731 g_tsc_offset = svm->vmcb->control.tsc_offset -
732 svm->nested.hsave->control.tsc_offset;
733 svm->nested.hsave->control.tsc_offset = offset;
734 }
735
736 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
737 }
738
739 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
740 {
741 struct vcpu_svm *svm = to_svm(vcpu);
742
743 svm->vmcb->control.tsc_offset += adjustment;
744 if (is_nested(svm))
745 svm->nested.hsave->control.tsc_offset += adjustment;
746 }
747
748 static void init_vmcb(struct vcpu_svm *svm)
749 {
750 struct vmcb_control_area *control = &svm->vmcb->control;
751 struct vmcb_save_area *save = &svm->vmcb->save;
752
753 svm->vcpu.fpu_active = 1;
754
755 control->intercept_cr_read = INTERCEPT_CR0_MASK |
756 INTERCEPT_CR3_MASK |
757 INTERCEPT_CR4_MASK;
758
759 control->intercept_cr_write = INTERCEPT_CR0_MASK |
760 INTERCEPT_CR3_MASK |
761 INTERCEPT_CR4_MASK |
762 INTERCEPT_CR8_MASK;
763
764 control->intercept_dr_read = INTERCEPT_DR0_MASK |
765 INTERCEPT_DR1_MASK |
766 INTERCEPT_DR2_MASK |
767 INTERCEPT_DR3_MASK |
768 INTERCEPT_DR4_MASK |
769 INTERCEPT_DR5_MASK |
770 INTERCEPT_DR6_MASK |
771 INTERCEPT_DR7_MASK;
772
773 control->intercept_dr_write = INTERCEPT_DR0_MASK |
774 INTERCEPT_DR1_MASK |
775 INTERCEPT_DR2_MASK |
776 INTERCEPT_DR3_MASK |
777 INTERCEPT_DR4_MASK |
778 INTERCEPT_DR5_MASK |
779 INTERCEPT_DR6_MASK |
780 INTERCEPT_DR7_MASK;
781
782 control->intercept_exceptions = (1 << PF_VECTOR) |
783 (1 << UD_VECTOR) |
784 (1 << MC_VECTOR);
785
786
787 control->intercept = (1ULL << INTERCEPT_INTR) |
788 (1ULL << INTERCEPT_NMI) |
789 (1ULL << INTERCEPT_SMI) |
790 (1ULL << INTERCEPT_SELECTIVE_CR0) |
791 (1ULL << INTERCEPT_CPUID) |
792 (1ULL << INTERCEPT_INVD) |
793 (1ULL << INTERCEPT_HLT) |
794 (1ULL << INTERCEPT_INVLPG) |
795 (1ULL << INTERCEPT_INVLPGA) |
796 (1ULL << INTERCEPT_IOIO_PROT) |
797 (1ULL << INTERCEPT_MSR_PROT) |
798 (1ULL << INTERCEPT_TASK_SWITCH) |
799 (1ULL << INTERCEPT_SHUTDOWN) |
800 (1ULL << INTERCEPT_VMRUN) |
801 (1ULL << INTERCEPT_VMMCALL) |
802 (1ULL << INTERCEPT_VMLOAD) |
803 (1ULL << INTERCEPT_VMSAVE) |
804 (1ULL << INTERCEPT_STGI) |
805 (1ULL << INTERCEPT_CLGI) |
806 (1ULL << INTERCEPT_SKINIT) |
807 (1ULL << INTERCEPT_WBINVD) |
808 (1ULL << INTERCEPT_MONITOR) |
809 (1ULL << INTERCEPT_MWAIT);
810
811 control->iopm_base_pa = iopm_base;
812 control->msrpm_base_pa = __pa(svm->msrpm);
813 control->int_ctl = V_INTR_MASKING_MASK;
814
815 init_seg(&save->es);
816 init_seg(&save->ss);
817 init_seg(&save->ds);
818 init_seg(&save->fs);
819 init_seg(&save->gs);
820
821 save->cs.selector = 0xf000;
822 /* Executable/Readable Code Segment */
823 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
824 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
825 save->cs.limit = 0xffff;
826 /*
827 * cs.base should really be 0xffff0000, but vmx can't handle that, so
828 * be consistent with it.
829 *
830 * Replace when we have real mode working for vmx.
831 */
832 save->cs.base = 0xf0000;
833
834 save->gdtr.limit = 0xffff;
835 save->idtr.limit = 0xffff;
836
837 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
838 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
839
840 svm_set_efer(&svm->vcpu, 0);
841 save->dr6 = 0xffff0ff0;
842 save->dr7 = 0x400;
843 save->rflags = 2;
844 save->rip = 0x0000fff0;
845 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
846
847 /*
848 * This is the guest-visible cr0 value.
849 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
850 */
851 svm->vcpu.arch.cr0 = 0;
852 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
853
854 save->cr4 = X86_CR4_PAE;
855 /* rdx = ?? */
856
857 if (npt_enabled) {
858 /* Setup VMCB for Nested Paging */
859 control->nested_ctl = 1;
860 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
861 (1ULL << INTERCEPT_INVLPG));
862 control->intercept_exceptions &= ~(1 << PF_VECTOR);
863 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
864 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
865 save->g_pat = 0x0007040600070406ULL;
866 save->cr3 = 0;
867 save->cr4 = 0;
868 }
869 force_new_asid(&svm->vcpu);
870
871 svm->nested.vmcb = 0;
872 svm->vcpu.arch.hflags = 0;
873
874 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
875 control->pause_filter_count = 3000;
876 control->intercept |= (1ULL << INTERCEPT_PAUSE);
877 }
878
879 enable_gif(svm);
880 }
881
882 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
883 {
884 struct vcpu_svm *svm = to_svm(vcpu);
885
886 init_vmcb(svm);
887
888 if (!kvm_vcpu_is_bsp(vcpu)) {
889 kvm_rip_write(vcpu, 0);
890 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
891 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
892 }
893 vcpu->arch.regs_avail = ~0;
894 vcpu->arch.regs_dirty = ~0;
895
896 return 0;
897 }
898
899 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
900 {
901 struct vcpu_svm *svm;
902 struct page *page;
903 struct page *msrpm_pages;
904 struct page *hsave_page;
905 struct page *nested_msrpm_pages;
906 int err;
907
908 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
909 if (!svm) {
910 err = -ENOMEM;
911 goto out;
912 }
913
914 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
915 if (err)
916 goto free_svm;
917
918 err = -ENOMEM;
919 page = alloc_page(GFP_KERNEL);
920 if (!page)
921 goto uninit;
922
923 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
924 if (!msrpm_pages)
925 goto free_page1;
926
927 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
928 if (!nested_msrpm_pages)
929 goto free_page2;
930
931 hsave_page = alloc_page(GFP_KERNEL);
932 if (!hsave_page)
933 goto free_page3;
934
935 svm->nested.hsave = page_address(hsave_page);
936
937 svm->msrpm = page_address(msrpm_pages);
938 svm_vcpu_init_msrpm(svm->msrpm);
939
940 svm->nested.msrpm = page_address(nested_msrpm_pages);
941 svm_vcpu_init_msrpm(svm->nested.msrpm);
942
943 svm->vmcb = page_address(page);
944 clear_page(svm->vmcb);
945 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
946 svm->asid_generation = 0;
947 init_vmcb(svm);
948 kvm_write_tsc(&svm->vcpu, 0);
949
950 err = fx_init(&svm->vcpu);
951 if (err)
952 goto free_page4;
953
954 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
955 if (kvm_vcpu_is_bsp(&svm->vcpu))
956 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
957
958 return &svm->vcpu;
959
960 free_page4:
961 __free_page(hsave_page);
962 free_page3:
963 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
964 free_page2:
965 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
966 free_page1:
967 __free_page(page);
968 uninit:
969 kvm_vcpu_uninit(&svm->vcpu);
970 free_svm:
971 kmem_cache_free(kvm_vcpu_cache, svm);
972 out:
973 return ERR_PTR(err);
974 }
975
976 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
977 {
978 struct vcpu_svm *svm = to_svm(vcpu);
979
980 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
981 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
982 __free_page(virt_to_page(svm->nested.hsave));
983 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
984 kvm_vcpu_uninit(vcpu);
985 kmem_cache_free(kvm_vcpu_cache, svm);
986 }
987
988 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
989 {
990 struct vcpu_svm *svm = to_svm(vcpu);
991 int i;
992
993 if (unlikely(cpu != vcpu->cpu)) {
994 svm->asid_generation = 0;
995 }
996
997 #ifdef CONFIG_X86_64
998 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
999 #endif
1000 savesegment(fs, svm->host.fs);
1001 savesegment(gs, svm->host.gs);
1002 svm->host.ldt = kvm_read_ldt();
1003
1004 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1005 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1006 }
1007
1008 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1009 {
1010 struct vcpu_svm *svm = to_svm(vcpu);
1011 int i;
1012
1013 ++vcpu->stat.host_state_reload;
1014 kvm_load_ldt(svm->host.ldt);
1015 #ifdef CONFIG_X86_64
1016 loadsegment(fs, svm->host.fs);
1017 load_gs_index(svm->host.gs);
1018 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1019 #else
1020 loadsegment(gs, svm->host.gs);
1021 #endif
1022 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1023 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1024 }
1025
1026 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1027 {
1028 return to_svm(vcpu)->vmcb->save.rflags;
1029 }
1030
1031 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1032 {
1033 to_svm(vcpu)->vmcb->save.rflags = rflags;
1034 }
1035
1036 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1037 {
1038 switch (reg) {
1039 case VCPU_EXREG_PDPTR:
1040 BUG_ON(!npt_enabled);
1041 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1042 break;
1043 default:
1044 BUG();
1045 }
1046 }
1047
1048 static void svm_set_vintr(struct vcpu_svm *svm)
1049 {
1050 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1051 }
1052
1053 static void svm_clear_vintr(struct vcpu_svm *svm)
1054 {
1055 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1056 }
1057
1058 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1059 {
1060 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1061
1062 switch (seg) {
1063 case VCPU_SREG_CS: return &save->cs;
1064 case VCPU_SREG_DS: return &save->ds;
1065 case VCPU_SREG_ES: return &save->es;
1066 case VCPU_SREG_FS: return &save->fs;
1067 case VCPU_SREG_GS: return &save->gs;
1068 case VCPU_SREG_SS: return &save->ss;
1069 case VCPU_SREG_TR: return &save->tr;
1070 case VCPU_SREG_LDTR: return &save->ldtr;
1071 }
1072 BUG();
1073 return NULL;
1074 }
1075
1076 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1077 {
1078 struct vmcb_seg *s = svm_seg(vcpu, seg);
1079
1080 return s->base;
1081 }
1082
1083 static void svm_get_segment(struct kvm_vcpu *vcpu,
1084 struct kvm_segment *var, int seg)
1085 {
1086 struct vmcb_seg *s = svm_seg(vcpu, seg);
1087
1088 var->base = s->base;
1089 var->limit = s->limit;
1090 var->selector = s->selector;
1091 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1092 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1093 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1094 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1095 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1096 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1097 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1098 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1099
1100 /*
1101 * AMD's VMCB does not have an explicit unusable field, so emulate it
1102 * for cross vendor migration purposes by "not present"
1103 */
1104 var->unusable = !var->present || (var->type == 0);
1105
1106 switch (seg) {
1107 case VCPU_SREG_CS:
1108 /*
1109 * SVM always stores 0 for the 'G' bit in the CS selector in
1110 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1111 * Intel's VMENTRY has a check on the 'G' bit.
1112 */
1113 var->g = s->limit > 0xfffff;
1114 break;
1115 case VCPU_SREG_TR:
1116 /*
1117 * Work around a bug where the busy flag in the tr selector
1118 * isn't exposed
1119 */
1120 var->type |= 0x2;
1121 break;
1122 case VCPU_SREG_DS:
1123 case VCPU_SREG_ES:
1124 case VCPU_SREG_FS:
1125 case VCPU_SREG_GS:
1126 /*
1127 * The accessed bit must always be set in the segment
1128 * descriptor cache, although it can be cleared in the
1129 * descriptor, the cached bit always remains at 1. Since
1130 * Intel has a check on this, set it here to support
1131 * cross-vendor migration.
1132 */
1133 if (!var->unusable)
1134 var->type |= 0x1;
1135 break;
1136 case VCPU_SREG_SS:
1137 /*
1138 * On AMD CPUs sometimes the DB bit in the segment
1139 * descriptor is left as 1, although the whole segment has
1140 * been made unusable. Clear it here to pass an Intel VMX
1141 * entry check when cross vendor migrating.
1142 */
1143 if (var->unusable)
1144 var->db = 0;
1145 break;
1146 }
1147 }
1148
1149 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1150 {
1151 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1152
1153 return save->cpl;
1154 }
1155
1156 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1157 {
1158 struct vcpu_svm *svm = to_svm(vcpu);
1159
1160 dt->size = svm->vmcb->save.idtr.limit;
1161 dt->address = svm->vmcb->save.idtr.base;
1162 }
1163
1164 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1165 {
1166 struct vcpu_svm *svm = to_svm(vcpu);
1167
1168 svm->vmcb->save.idtr.limit = dt->size;
1169 svm->vmcb->save.idtr.base = dt->address ;
1170 }
1171
1172 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1173 {
1174 struct vcpu_svm *svm = to_svm(vcpu);
1175
1176 dt->size = svm->vmcb->save.gdtr.limit;
1177 dt->address = svm->vmcb->save.gdtr.base;
1178 }
1179
1180 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1181 {
1182 struct vcpu_svm *svm = to_svm(vcpu);
1183
1184 svm->vmcb->save.gdtr.limit = dt->size;
1185 svm->vmcb->save.gdtr.base = dt->address ;
1186 }
1187
1188 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1189 {
1190 }
1191
1192 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1193 {
1194 }
1195
1196 static void update_cr0_intercept(struct vcpu_svm *svm)
1197 {
1198 struct vmcb *vmcb = svm->vmcb;
1199 ulong gcr0 = svm->vcpu.arch.cr0;
1200 u64 *hcr0 = &svm->vmcb->save.cr0;
1201
1202 if (!svm->vcpu.fpu_active)
1203 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1204 else
1205 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1206 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1207
1208
1209 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1210 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1211 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1212 if (is_nested(svm)) {
1213 struct vmcb *hsave = svm->nested.hsave;
1214
1215 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1216 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1217 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1218 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1219 }
1220 } else {
1221 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1222 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1223 if (is_nested(svm)) {
1224 struct vmcb *hsave = svm->nested.hsave;
1225
1226 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1227 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1228 }
1229 }
1230 }
1231
1232 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1233 {
1234 struct vcpu_svm *svm = to_svm(vcpu);
1235
1236 if (is_nested(svm)) {
1237 /*
1238 * We are here because we run in nested mode, the host kvm
1239 * intercepts cr0 writes but the l1 hypervisor does not.
1240 * But the L1 hypervisor may intercept selective cr0 writes.
1241 * This needs to be checked here.
1242 */
1243 unsigned long old, new;
1244
1245 /* Remove bits that would trigger a real cr0 write intercept */
1246 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1247 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1248
1249 if (old == new) {
1250 /* cr0 write with ts and mp unchanged */
1251 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1252 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1253 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1254 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1255 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1256 return;
1257 }
1258 }
1259 }
1260
1261 #ifdef CONFIG_X86_64
1262 if (vcpu->arch.efer & EFER_LME) {
1263 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1264 vcpu->arch.efer |= EFER_LMA;
1265 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1266 }
1267
1268 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1269 vcpu->arch.efer &= ~EFER_LMA;
1270 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1271 }
1272 }
1273 #endif
1274 vcpu->arch.cr0 = cr0;
1275
1276 if (!npt_enabled)
1277 cr0 |= X86_CR0_PG | X86_CR0_WP;
1278
1279 if (!vcpu->fpu_active)
1280 cr0 |= X86_CR0_TS;
1281 /*
1282 * re-enable caching here because the QEMU bios
1283 * does not do it - this results in some delay at
1284 * reboot
1285 */
1286 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1287 svm->vmcb->save.cr0 = cr0;
1288 update_cr0_intercept(svm);
1289 }
1290
1291 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1292 {
1293 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1294 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1295
1296 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1297 force_new_asid(vcpu);
1298
1299 vcpu->arch.cr4 = cr4;
1300 if (!npt_enabled)
1301 cr4 |= X86_CR4_PAE;
1302 cr4 |= host_cr4_mce;
1303 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1304 }
1305
1306 static void svm_set_segment(struct kvm_vcpu *vcpu,
1307 struct kvm_segment *var, int seg)
1308 {
1309 struct vcpu_svm *svm = to_svm(vcpu);
1310 struct vmcb_seg *s = svm_seg(vcpu, seg);
1311
1312 s->base = var->base;
1313 s->limit = var->limit;
1314 s->selector = var->selector;
1315 if (var->unusable)
1316 s->attrib = 0;
1317 else {
1318 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1319 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1320 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1321 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1322 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1323 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1324 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1325 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1326 }
1327 if (seg == VCPU_SREG_CS)
1328 svm->vmcb->save.cpl
1329 = (svm->vmcb->save.cs.attrib
1330 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1331
1332 }
1333
1334 static void update_db_intercept(struct kvm_vcpu *vcpu)
1335 {
1336 struct vcpu_svm *svm = to_svm(vcpu);
1337
1338 svm->vmcb->control.intercept_exceptions &=
1339 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1340
1341 if (svm->nmi_singlestep)
1342 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1343
1344 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1345 if (vcpu->guest_debug &
1346 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1347 svm->vmcb->control.intercept_exceptions |=
1348 1 << DB_VECTOR;
1349 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1350 svm->vmcb->control.intercept_exceptions |=
1351 1 << BP_VECTOR;
1352 } else
1353 vcpu->guest_debug = 0;
1354 }
1355
1356 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1357 {
1358 struct vcpu_svm *svm = to_svm(vcpu);
1359
1360 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1361 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1362 else
1363 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1364
1365 update_db_intercept(vcpu);
1366 }
1367
1368 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1369 {
1370 if (sd->next_asid > sd->max_asid) {
1371 ++sd->asid_generation;
1372 sd->next_asid = 1;
1373 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1374 }
1375
1376 svm->asid_generation = sd->asid_generation;
1377 svm->vmcb->control.asid = sd->next_asid++;
1378 }
1379
1380 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1381 {
1382 struct vcpu_svm *svm = to_svm(vcpu);
1383
1384 svm->vmcb->save.dr7 = value;
1385 }
1386
1387 static int pf_interception(struct vcpu_svm *svm)
1388 {
1389 u64 fault_address = svm->vmcb->control.exit_info_2;
1390 u32 error_code;
1391 int r = 1;
1392
1393 switch (svm->apf_reason) {
1394 default:
1395 error_code = svm->vmcb->control.exit_info_1;
1396
1397 trace_kvm_page_fault(fault_address, error_code);
1398 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1399 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1400 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1401 break;
1402 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1403 svm->apf_reason = 0;
1404 local_irq_disable();
1405 kvm_async_pf_task_wait(fault_address);
1406 local_irq_enable();
1407 break;
1408 case KVM_PV_REASON_PAGE_READY:
1409 svm->apf_reason = 0;
1410 local_irq_disable();
1411 kvm_async_pf_task_wake(fault_address);
1412 local_irq_enable();
1413 break;
1414 }
1415 return r;
1416 }
1417
1418 static int db_interception(struct vcpu_svm *svm)
1419 {
1420 struct kvm_run *kvm_run = svm->vcpu.run;
1421
1422 if (!(svm->vcpu.guest_debug &
1423 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1424 !svm->nmi_singlestep) {
1425 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1426 return 1;
1427 }
1428
1429 if (svm->nmi_singlestep) {
1430 svm->nmi_singlestep = false;
1431 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1432 svm->vmcb->save.rflags &=
1433 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1434 update_db_intercept(&svm->vcpu);
1435 }
1436
1437 if (svm->vcpu.guest_debug &
1438 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1439 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1440 kvm_run->debug.arch.pc =
1441 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1442 kvm_run->debug.arch.exception = DB_VECTOR;
1443 return 0;
1444 }
1445
1446 return 1;
1447 }
1448
1449 static int bp_interception(struct vcpu_svm *svm)
1450 {
1451 struct kvm_run *kvm_run = svm->vcpu.run;
1452
1453 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1454 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1455 kvm_run->debug.arch.exception = BP_VECTOR;
1456 return 0;
1457 }
1458
1459 static int ud_interception(struct vcpu_svm *svm)
1460 {
1461 int er;
1462
1463 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1464 if (er != EMULATE_DONE)
1465 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1466 return 1;
1467 }
1468
1469 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1470 {
1471 struct vcpu_svm *svm = to_svm(vcpu);
1472 u32 excp;
1473
1474 if (is_nested(svm)) {
1475 u32 h_excp, n_excp;
1476
1477 h_excp = svm->nested.hsave->control.intercept_exceptions;
1478 n_excp = svm->nested.intercept_exceptions;
1479 h_excp &= ~(1 << NM_VECTOR);
1480 excp = h_excp | n_excp;
1481 } else {
1482 excp = svm->vmcb->control.intercept_exceptions;
1483 excp &= ~(1 << NM_VECTOR);
1484 }
1485
1486 svm->vmcb->control.intercept_exceptions = excp;
1487
1488 svm->vcpu.fpu_active = 1;
1489 update_cr0_intercept(svm);
1490 }
1491
1492 static int nm_interception(struct vcpu_svm *svm)
1493 {
1494 svm_fpu_activate(&svm->vcpu);
1495 return 1;
1496 }
1497
1498 static bool is_erratum_383(void)
1499 {
1500 int err, i;
1501 u64 value;
1502
1503 if (!erratum_383_found)
1504 return false;
1505
1506 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1507 if (err)
1508 return false;
1509
1510 /* Bit 62 may or may not be set for this mce */
1511 value &= ~(1ULL << 62);
1512
1513 if (value != 0xb600000000010015ULL)
1514 return false;
1515
1516 /* Clear MCi_STATUS registers */
1517 for (i = 0; i < 6; ++i)
1518 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1519
1520 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1521 if (!err) {
1522 u32 low, high;
1523
1524 value &= ~(1ULL << 2);
1525 low = lower_32_bits(value);
1526 high = upper_32_bits(value);
1527
1528 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1529 }
1530
1531 /* Flush tlb to evict multi-match entries */
1532 __flush_tlb_all();
1533
1534 return true;
1535 }
1536
1537 static void svm_handle_mce(struct vcpu_svm *svm)
1538 {
1539 if (is_erratum_383()) {
1540 /*
1541 * Erratum 383 triggered. Guest state is corrupt so kill the
1542 * guest.
1543 */
1544 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1545
1546 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1547
1548 return;
1549 }
1550
1551 /*
1552 * On an #MC intercept the MCE handler is not called automatically in
1553 * the host. So do it by hand here.
1554 */
1555 asm volatile (
1556 "int $0x12\n");
1557 /* not sure if we ever come back to this point */
1558
1559 return;
1560 }
1561
1562 static int mc_interception(struct vcpu_svm *svm)
1563 {
1564 return 1;
1565 }
1566
1567 static int shutdown_interception(struct vcpu_svm *svm)
1568 {
1569 struct kvm_run *kvm_run = svm->vcpu.run;
1570
1571 /*
1572 * VMCB is undefined after a SHUTDOWN intercept
1573 * so reinitialize it.
1574 */
1575 clear_page(svm->vmcb);
1576 init_vmcb(svm);
1577
1578 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1579 return 0;
1580 }
1581
1582 static int io_interception(struct vcpu_svm *svm)
1583 {
1584 struct kvm_vcpu *vcpu = &svm->vcpu;
1585 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1586 int size, in, string;
1587 unsigned port;
1588
1589 ++svm->vcpu.stat.io_exits;
1590 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1591 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1592 if (string || in)
1593 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1594
1595 port = io_info >> 16;
1596 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1597 svm->next_rip = svm->vmcb->control.exit_info_2;
1598 skip_emulated_instruction(&svm->vcpu);
1599
1600 return kvm_fast_pio_out(vcpu, size, port);
1601 }
1602
1603 static int nmi_interception(struct vcpu_svm *svm)
1604 {
1605 return 1;
1606 }
1607
1608 static int intr_interception(struct vcpu_svm *svm)
1609 {
1610 ++svm->vcpu.stat.irq_exits;
1611 return 1;
1612 }
1613
1614 static int nop_on_interception(struct vcpu_svm *svm)
1615 {
1616 return 1;
1617 }
1618
1619 static int halt_interception(struct vcpu_svm *svm)
1620 {
1621 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1622 skip_emulated_instruction(&svm->vcpu);
1623 return kvm_emulate_halt(&svm->vcpu);
1624 }
1625
1626 static int vmmcall_interception(struct vcpu_svm *svm)
1627 {
1628 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1629 skip_emulated_instruction(&svm->vcpu);
1630 kvm_emulate_hypercall(&svm->vcpu);
1631 return 1;
1632 }
1633
1634 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1635 {
1636 struct vcpu_svm *svm = to_svm(vcpu);
1637
1638 return svm->nested.nested_cr3;
1639 }
1640
1641 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1642 unsigned long root)
1643 {
1644 struct vcpu_svm *svm = to_svm(vcpu);
1645
1646 svm->vmcb->control.nested_cr3 = root;
1647 force_new_asid(vcpu);
1648 }
1649
1650 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1651 struct x86_exception *fault)
1652 {
1653 struct vcpu_svm *svm = to_svm(vcpu);
1654
1655 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1656 svm->vmcb->control.exit_code_hi = 0;
1657 svm->vmcb->control.exit_info_1 = fault->error_code;
1658 svm->vmcb->control.exit_info_2 = fault->address;
1659
1660 nested_svm_vmexit(svm);
1661 }
1662
1663 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1664 {
1665 int r;
1666
1667 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1668
1669 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1670 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1671 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1672 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1673 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1674
1675 return r;
1676 }
1677
1678 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1679 {
1680 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1681 }
1682
1683 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1684 {
1685 if (!(svm->vcpu.arch.efer & EFER_SVME)
1686 || !is_paging(&svm->vcpu)) {
1687 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1688 return 1;
1689 }
1690
1691 if (svm->vmcb->save.cpl) {
1692 kvm_inject_gp(&svm->vcpu, 0);
1693 return 1;
1694 }
1695
1696 return 0;
1697 }
1698
1699 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1700 bool has_error_code, u32 error_code)
1701 {
1702 int vmexit;
1703
1704 if (!is_nested(svm))
1705 return 0;
1706
1707 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1708 svm->vmcb->control.exit_code_hi = 0;
1709 svm->vmcb->control.exit_info_1 = error_code;
1710 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1711
1712 vmexit = nested_svm_intercept(svm);
1713 if (vmexit == NESTED_EXIT_DONE)
1714 svm->nested.exit_required = true;
1715
1716 return vmexit;
1717 }
1718
1719 /* This function returns true if it is save to enable the irq window */
1720 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1721 {
1722 if (!is_nested(svm))
1723 return true;
1724
1725 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1726 return true;
1727
1728 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1729 return false;
1730
1731 /*
1732 * if vmexit was already requested (by intercepted exception
1733 * for instance) do not overwrite it with "external interrupt"
1734 * vmexit.
1735 */
1736 if (svm->nested.exit_required)
1737 return false;
1738
1739 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1740 svm->vmcb->control.exit_info_1 = 0;
1741 svm->vmcb->control.exit_info_2 = 0;
1742
1743 if (svm->nested.intercept & 1ULL) {
1744 /*
1745 * The #vmexit can't be emulated here directly because this
1746 * code path runs with irqs and preemtion disabled. A
1747 * #vmexit emulation might sleep. Only signal request for
1748 * the #vmexit here.
1749 */
1750 svm->nested.exit_required = true;
1751 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1752 return false;
1753 }
1754
1755 return true;
1756 }
1757
1758 /* This function returns true if it is save to enable the nmi window */
1759 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1760 {
1761 if (!is_nested(svm))
1762 return true;
1763
1764 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1765 return true;
1766
1767 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1768 svm->nested.exit_required = true;
1769
1770 return false;
1771 }
1772
1773 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1774 {
1775 struct page *page;
1776
1777 might_sleep();
1778
1779 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1780 if (is_error_page(page))
1781 goto error;
1782
1783 *_page = page;
1784
1785 return kmap(page);
1786
1787 error:
1788 kvm_release_page_clean(page);
1789 kvm_inject_gp(&svm->vcpu, 0);
1790
1791 return NULL;
1792 }
1793
1794 static void nested_svm_unmap(struct page *page)
1795 {
1796 kunmap(page);
1797 kvm_release_page_dirty(page);
1798 }
1799
1800 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1801 {
1802 unsigned port;
1803 u8 val, bit;
1804 u64 gpa;
1805
1806 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1807 return NESTED_EXIT_HOST;
1808
1809 port = svm->vmcb->control.exit_info_1 >> 16;
1810 gpa = svm->nested.vmcb_iopm + (port / 8);
1811 bit = port % 8;
1812 val = 0;
1813
1814 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1815 val &= (1 << bit);
1816
1817 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1818 }
1819
1820 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1821 {
1822 u32 offset, msr, value;
1823 int write, mask;
1824
1825 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1826 return NESTED_EXIT_HOST;
1827
1828 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1829 offset = svm_msrpm_offset(msr);
1830 write = svm->vmcb->control.exit_info_1 & 1;
1831 mask = 1 << ((2 * (msr & 0xf)) + write);
1832
1833 if (offset == MSR_INVALID)
1834 return NESTED_EXIT_DONE;
1835
1836 /* Offset is in 32 bit units but need in 8 bit units */
1837 offset *= 4;
1838
1839 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1840 return NESTED_EXIT_DONE;
1841
1842 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1843 }
1844
1845 static int nested_svm_exit_special(struct vcpu_svm *svm)
1846 {
1847 u32 exit_code = svm->vmcb->control.exit_code;
1848
1849 switch (exit_code) {
1850 case SVM_EXIT_INTR:
1851 case SVM_EXIT_NMI:
1852 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1853 return NESTED_EXIT_HOST;
1854 case SVM_EXIT_NPF:
1855 /* For now we are always handling NPFs when using them */
1856 if (npt_enabled)
1857 return NESTED_EXIT_HOST;
1858 break;
1859 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1860 /* When we're shadowing, trap PFs, but not async PF */
1861 if (!npt_enabled && svm->apf_reason == 0)
1862 return NESTED_EXIT_HOST;
1863 break;
1864 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1865 nm_interception(svm);
1866 break;
1867 default:
1868 break;
1869 }
1870
1871 return NESTED_EXIT_CONTINUE;
1872 }
1873
1874 /*
1875 * If this function returns true, this #vmexit was already handled
1876 */
1877 static int nested_svm_intercept(struct vcpu_svm *svm)
1878 {
1879 u32 exit_code = svm->vmcb->control.exit_code;
1880 int vmexit = NESTED_EXIT_HOST;
1881
1882 switch (exit_code) {
1883 case SVM_EXIT_MSR:
1884 vmexit = nested_svm_exit_handled_msr(svm);
1885 break;
1886 case SVM_EXIT_IOIO:
1887 vmexit = nested_svm_intercept_ioio(svm);
1888 break;
1889 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1890 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1891 if (svm->nested.intercept_cr_read & cr_bits)
1892 vmexit = NESTED_EXIT_DONE;
1893 break;
1894 }
1895 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1896 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1897 if (svm->nested.intercept_cr_write & cr_bits)
1898 vmexit = NESTED_EXIT_DONE;
1899 break;
1900 }
1901 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1902 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1903 if (svm->nested.intercept_dr_read & dr_bits)
1904 vmexit = NESTED_EXIT_DONE;
1905 break;
1906 }
1907 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1908 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1909 if (svm->nested.intercept_dr_write & dr_bits)
1910 vmexit = NESTED_EXIT_DONE;
1911 break;
1912 }
1913 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1914 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1915 if (svm->nested.intercept_exceptions & excp_bits)
1916 vmexit = NESTED_EXIT_DONE;
1917 /* async page fault always cause vmexit */
1918 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1919 svm->apf_reason != 0)
1920 vmexit = NESTED_EXIT_DONE;
1921 break;
1922 }
1923 case SVM_EXIT_ERR: {
1924 vmexit = NESTED_EXIT_DONE;
1925 break;
1926 }
1927 default: {
1928 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1929 if (svm->nested.intercept & exit_bits)
1930 vmexit = NESTED_EXIT_DONE;
1931 }
1932 }
1933
1934 return vmexit;
1935 }
1936
1937 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1938 {
1939 int vmexit;
1940
1941 vmexit = nested_svm_intercept(svm);
1942
1943 if (vmexit == NESTED_EXIT_DONE)
1944 nested_svm_vmexit(svm);
1945
1946 return vmexit;
1947 }
1948
1949 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1950 {
1951 struct vmcb_control_area *dst = &dst_vmcb->control;
1952 struct vmcb_control_area *from = &from_vmcb->control;
1953
1954 dst->intercept_cr_read = from->intercept_cr_read;
1955 dst->intercept_cr_write = from->intercept_cr_write;
1956 dst->intercept_dr_read = from->intercept_dr_read;
1957 dst->intercept_dr_write = from->intercept_dr_write;
1958 dst->intercept_exceptions = from->intercept_exceptions;
1959 dst->intercept = from->intercept;
1960 dst->iopm_base_pa = from->iopm_base_pa;
1961 dst->msrpm_base_pa = from->msrpm_base_pa;
1962 dst->tsc_offset = from->tsc_offset;
1963 dst->asid = from->asid;
1964 dst->tlb_ctl = from->tlb_ctl;
1965 dst->int_ctl = from->int_ctl;
1966 dst->int_vector = from->int_vector;
1967 dst->int_state = from->int_state;
1968 dst->exit_code = from->exit_code;
1969 dst->exit_code_hi = from->exit_code_hi;
1970 dst->exit_info_1 = from->exit_info_1;
1971 dst->exit_info_2 = from->exit_info_2;
1972 dst->exit_int_info = from->exit_int_info;
1973 dst->exit_int_info_err = from->exit_int_info_err;
1974 dst->nested_ctl = from->nested_ctl;
1975 dst->event_inj = from->event_inj;
1976 dst->event_inj_err = from->event_inj_err;
1977 dst->nested_cr3 = from->nested_cr3;
1978 dst->lbr_ctl = from->lbr_ctl;
1979 }
1980
1981 static int nested_svm_vmexit(struct vcpu_svm *svm)
1982 {
1983 struct vmcb *nested_vmcb;
1984 struct vmcb *hsave = svm->nested.hsave;
1985 struct vmcb *vmcb = svm->vmcb;
1986 struct page *page;
1987
1988 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1989 vmcb->control.exit_info_1,
1990 vmcb->control.exit_info_2,
1991 vmcb->control.exit_int_info,
1992 vmcb->control.exit_int_info_err);
1993
1994 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1995 if (!nested_vmcb)
1996 return 1;
1997
1998 /* Exit nested SVM mode */
1999 svm->nested.vmcb = 0;
2000
2001 /* Give the current vmcb to the guest */
2002 disable_gif(svm);
2003
2004 nested_vmcb->save.es = vmcb->save.es;
2005 nested_vmcb->save.cs = vmcb->save.cs;
2006 nested_vmcb->save.ss = vmcb->save.ss;
2007 nested_vmcb->save.ds = vmcb->save.ds;
2008 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2009 nested_vmcb->save.idtr = vmcb->save.idtr;
2010 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2011 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2012 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2013 nested_vmcb->save.cr2 = vmcb->save.cr2;
2014 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2015 nested_vmcb->save.rflags = vmcb->save.rflags;
2016 nested_vmcb->save.rip = vmcb->save.rip;
2017 nested_vmcb->save.rsp = vmcb->save.rsp;
2018 nested_vmcb->save.rax = vmcb->save.rax;
2019 nested_vmcb->save.dr7 = vmcb->save.dr7;
2020 nested_vmcb->save.dr6 = vmcb->save.dr6;
2021 nested_vmcb->save.cpl = vmcb->save.cpl;
2022
2023 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2024 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2025 nested_vmcb->control.int_state = vmcb->control.int_state;
2026 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2027 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2028 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2029 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2030 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2031 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2032 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2033
2034 /*
2035 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2036 * to make sure that we do not lose injected events. So check event_inj
2037 * here and copy it to exit_int_info if it is valid.
2038 * Exit_int_info and event_inj can't be both valid because the case
2039 * below only happens on a VMRUN instruction intercept which has
2040 * no valid exit_int_info set.
2041 */
2042 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2043 struct vmcb_control_area *nc = &nested_vmcb->control;
2044
2045 nc->exit_int_info = vmcb->control.event_inj;
2046 nc->exit_int_info_err = vmcb->control.event_inj_err;
2047 }
2048
2049 nested_vmcb->control.tlb_ctl = 0;
2050 nested_vmcb->control.event_inj = 0;
2051 nested_vmcb->control.event_inj_err = 0;
2052
2053 /* We always set V_INTR_MASKING and remember the old value in hflags */
2054 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2055 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2056
2057 /* Restore the original control entries */
2058 copy_vmcb_control_area(vmcb, hsave);
2059
2060 kvm_clear_exception_queue(&svm->vcpu);
2061 kvm_clear_interrupt_queue(&svm->vcpu);
2062
2063 svm->nested.nested_cr3 = 0;
2064
2065 /* Restore selected save entries */
2066 svm->vmcb->save.es = hsave->save.es;
2067 svm->vmcb->save.cs = hsave->save.cs;
2068 svm->vmcb->save.ss = hsave->save.ss;
2069 svm->vmcb->save.ds = hsave->save.ds;
2070 svm->vmcb->save.gdtr = hsave->save.gdtr;
2071 svm->vmcb->save.idtr = hsave->save.idtr;
2072 svm->vmcb->save.rflags = hsave->save.rflags;
2073 svm_set_efer(&svm->vcpu, hsave->save.efer);
2074 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2075 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2076 if (npt_enabled) {
2077 svm->vmcb->save.cr3 = hsave->save.cr3;
2078 svm->vcpu.arch.cr3 = hsave->save.cr3;
2079 } else {
2080 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2081 }
2082 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2083 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2084 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2085 svm->vmcb->save.dr7 = 0;
2086 svm->vmcb->save.cpl = 0;
2087 svm->vmcb->control.exit_int_info = 0;
2088
2089 nested_svm_unmap(page);
2090
2091 nested_svm_uninit_mmu_context(&svm->vcpu);
2092 kvm_mmu_reset_context(&svm->vcpu);
2093 kvm_mmu_load(&svm->vcpu);
2094
2095 return 0;
2096 }
2097
2098 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2099 {
2100 /*
2101 * This function merges the msr permission bitmaps of kvm and the
2102 * nested vmcb. It is omptimized in that it only merges the parts where
2103 * the kvm msr permission bitmap may contain zero bits
2104 */
2105 int i;
2106
2107 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2108 return true;
2109
2110 for (i = 0; i < MSRPM_OFFSETS; i++) {
2111 u32 value, p;
2112 u64 offset;
2113
2114 if (msrpm_offsets[i] == 0xffffffff)
2115 break;
2116
2117 p = msrpm_offsets[i];
2118 offset = svm->nested.vmcb_msrpm + (p * 4);
2119
2120 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2121 return false;
2122
2123 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2124 }
2125
2126 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2127
2128 return true;
2129 }
2130
2131 static bool nested_vmcb_checks(struct vmcb *vmcb)
2132 {
2133 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2134 return false;
2135
2136 if (vmcb->control.asid == 0)
2137 return false;
2138
2139 if (vmcb->control.nested_ctl && !npt_enabled)
2140 return false;
2141
2142 return true;
2143 }
2144
2145 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2146 {
2147 struct vmcb *nested_vmcb;
2148 struct vmcb *hsave = svm->nested.hsave;
2149 struct vmcb *vmcb = svm->vmcb;
2150 struct page *page;
2151 u64 vmcb_gpa;
2152
2153 vmcb_gpa = svm->vmcb->save.rax;
2154
2155 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2156 if (!nested_vmcb)
2157 return false;
2158
2159 if (!nested_vmcb_checks(nested_vmcb)) {
2160 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2161 nested_vmcb->control.exit_code_hi = 0;
2162 nested_vmcb->control.exit_info_1 = 0;
2163 nested_vmcb->control.exit_info_2 = 0;
2164
2165 nested_svm_unmap(page);
2166
2167 return false;
2168 }
2169
2170 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2171 nested_vmcb->save.rip,
2172 nested_vmcb->control.int_ctl,
2173 nested_vmcb->control.event_inj,
2174 nested_vmcb->control.nested_ctl);
2175
2176 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2177 nested_vmcb->control.intercept_cr_write,
2178 nested_vmcb->control.intercept_exceptions,
2179 nested_vmcb->control.intercept);
2180
2181 /* Clear internal status */
2182 kvm_clear_exception_queue(&svm->vcpu);
2183 kvm_clear_interrupt_queue(&svm->vcpu);
2184
2185 /*
2186 * Save the old vmcb, so we don't need to pick what we save, but can
2187 * restore everything when a VMEXIT occurs
2188 */
2189 hsave->save.es = vmcb->save.es;
2190 hsave->save.cs = vmcb->save.cs;
2191 hsave->save.ss = vmcb->save.ss;
2192 hsave->save.ds = vmcb->save.ds;
2193 hsave->save.gdtr = vmcb->save.gdtr;
2194 hsave->save.idtr = vmcb->save.idtr;
2195 hsave->save.efer = svm->vcpu.arch.efer;
2196 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2197 hsave->save.cr4 = svm->vcpu.arch.cr4;
2198 hsave->save.rflags = vmcb->save.rflags;
2199 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2200 hsave->save.rsp = vmcb->save.rsp;
2201 hsave->save.rax = vmcb->save.rax;
2202 if (npt_enabled)
2203 hsave->save.cr3 = vmcb->save.cr3;
2204 else
2205 hsave->save.cr3 = svm->vcpu.arch.cr3;
2206
2207 copy_vmcb_control_area(hsave, vmcb);
2208
2209 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2210 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2211 else
2212 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2213
2214 if (nested_vmcb->control.nested_ctl) {
2215 kvm_mmu_unload(&svm->vcpu);
2216 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2217 nested_svm_init_mmu_context(&svm->vcpu);
2218 }
2219
2220 /* Load the nested guest state */
2221 svm->vmcb->save.es = nested_vmcb->save.es;
2222 svm->vmcb->save.cs = nested_vmcb->save.cs;
2223 svm->vmcb->save.ss = nested_vmcb->save.ss;
2224 svm->vmcb->save.ds = nested_vmcb->save.ds;
2225 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2226 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2227 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2228 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2229 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2230 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2231 if (npt_enabled) {
2232 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2233 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2234 } else
2235 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2236
2237 /* Guest paging mode is active - reset mmu */
2238 kvm_mmu_reset_context(&svm->vcpu);
2239
2240 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2241 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2242 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2243 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2244
2245 /* In case we don't even reach vcpu_run, the fields are not updated */
2246 svm->vmcb->save.rax = nested_vmcb->save.rax;
2247 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2248 svm->vmcb->save.rip = nested_vmcb->save.rip;
2249 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2250 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2251 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2252
2253 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2254 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2255
2256 /* cache intercepts */
2257 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2258 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2259 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2260 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2261 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2262 svm->nested.intercept = nested_vmcb->control.intercept;
2263
2264 force_new_asid(&svm->vcpu);
2265 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2266 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2267 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2268 else
2269 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2270
2271 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2272 /* We only want the cr8 intercept bits of the guest */
2273 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2274 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2275 }
2276
2277 /* We don't want to see VMMCALLs from a nested guest */
2278 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2279
2280 /*
2281 * We don't want a nested guest to be more powerful than the guest, so
2282 * all intercepts are ORed
2283 */
2284 svm->vmcb->control.intercept_cr_read |=
2285 nested_vmcb->control.intercept_cr_read;
2286 svm->vmcb->control.intercept_cr_write |=
2287 nested_vmcb->control.intercept_cr_write;
2288 svm->vmcb->control.intercept_dr_read |=
2289 nested_vmcb->control.intercept_dr_read;
2290 svm->vmcb->control.intercept_dr_write |=
2291 nested_vmcb->control.intercept_dr_write;
2292 svm->vmcb->control.intercept_exceptions |=
2293 nested_vmcb->control.intercept_exceptions;
2294
2295 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2296
2297 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2298 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2299 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2300 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2301 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2302 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2303
2304 nested_svm_unmap(page);
2305
2306 /* nested_vmcb is our indicator if nested SVM is activated */
2307 svm->nested.vmcb = vmcb_gpa;
2308
2309 enable_gif(svm);
2310
2311 return true;
2312 }
2313
2314 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2315 {
2316 to_vmcb->save.fs = from_vmcb->save.fs;
2317 to_vmcb->save.gs = from_vmcb->save.gs;
2318 to_vmcb->save.tr = from_vmcb->save.tr;
2319 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2320 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2321 to_vmcb->save.star = from_vmcb->save.star;
2322 to_vmcb->save.lstar = from_vmcb->save.lstar;
2323 to_vmcb->save.cstar = from_vmcb->save.cstar;
2324 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2325 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2326 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2327 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2328 }
2329
2330 static int vmload_interception(struct vcpu_svm *svm)
2331 {
2332 struct vmcb *nested_vmcb;
2333 struct page *page;
2334
2335 if (nested_svm_check_permissions(svm))
2336 return 1;
2337
2338 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2339 skip_emulated_instruction(&svm->vcpu);
2340
2341 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2342 if (!nested_vmcb)
2343 return 1;
2344
2345 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2346 nested_svm_unmap(page);
2347
2348 return 1;
2349 }
2350
2351 static int vmsave_interception(struct vcpu_svm *svm)
2352 {
2353 struct vmcb *nested_vmcb;
2354 struct page *page;
2355
2356 if (nested_svm_check_permissions(svm))
2357 return 1;
2358
2359 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2360 skip_emulated_instruction(&svm->vcpu);
2361
2362 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2363 if (!nested_vmcb)
2364 return 1;
2365
2366 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2367 nested_svm_unmap(page);
2368
2369 return 1;
2370 }
2371
2372 static int vmrun_interception(struct vcpu_svm *svm)
2373 {
2374 if (nested_svm_check_permissions(svm))
2375 return 1;
2376
2377 /* Save rip after vmrun instruction */
2378 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2379
2380 if (!nested_svm_vmrun(svm))
2381 return 1;
2382
2383 if (!nested_svm_vmrun_msrpm(svm))
2384 goto failed;
2385
2386 return 1;
2387
2388 failed:
2389
2390 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2391 svm->vmcb->control.exit_code_hi = 0;
2392 svm->vmcb->control.exit_info_1 = 0;
2393 svm->vmcb->control.exit_info_2 = 0;
2394
2395 nested_svm_vmexit(svm);
2396
2397 return 1;
2398 }
2399
2400 static int stgi_interception(struct vcpu_svm *svm)
2401 {
2402 if (nested_svm_check_permissions(svm))
2403 return 1;
2404
2405 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2406 skip_emulated_instruction(&svm->vcpu);
2407 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2408
2409 enable_gif(svm);
2410
2411 return 1;
2412 }
2413
2414 static int clgi_interception(struct vcpu_svm *svm)
2415 {
2416 if (nested_svm_check_permissions(svm))
2417 return 1;
2418
2419 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2420 skip_emulated_instruction(&svm->vcpu);
2421
2422 disable_gif(svm);
2423
2424 /* After a CLGI no interrupts should come */
2425 svm_clear_vintr(svm);
2426 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2427
2428 return 1;
2429 }
2430
2431 static int invlpga_interception(struct vcpu_svm *svm)
2432 {
2433 struct kvm_vcpu *vcpu = &svm->vcpu;
2434
2435 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2436 vcpu->arch.regs[VCPU_REGS_RAX]);
2437
2438 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2439 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2440
2441 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2442 skip_emulated_instruction(&svm->vcpu);
2443 return 1;
2444 }
2445
2446 static int skinit_interception(struct vcpu_svm *svm)
2447 {
2448 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2449
2450 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2451 return 1;
2452 }
2453
2454 static int invalid_op_interception(struct vcpu_svm *svm)
2455 {
2456 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2457 return 1;
2458 }
2459
2460 static int task_switch_interception(struct vcpu_svm *svm)
2461 {
2462 u16 tss_selector;
2463 int reason;
2464 int int_type = svm->vmcb->control.exit_int_info &
2465 SVM_EXITINTINFO_TYPE_MASK;
2466 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2467 uint32_t type =
2468 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2469 uint32_t idt_v =
2470 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2471 bool has_error_code = false;
2472 u32 error_code = 0;
2473
2474 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2475
2476 if (svm->vmcb->control.exit_info_2 &
2477 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2478 reason = TASK_SWITCH_IRET;
2479 else if (svm->vmcb->control.exit_info_2 &
2480 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2481 reason = TASK_SWITCH_JMP;
2482 else if (idt_v)
2483 reason = TASK_SWITCH_GATE;
2484 else
2485 reason = TASK_SWITCH_CALL;
2486
2487 if (reason == TASK_SWITCH_GATE) {
2488 switch (type) {
2489 case SVM_EXITINTINFO_TYPE_NMI:
2490 svm->vcpu.arch.nmi_injected = false;
2491 break;
2492 case SVM_EXITINTINFO_TYPE_EXEPT:
2493 if (svm->vmcb->control.exit_info_2 &
2494 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2495 has_error_code = true;
2496 error_code =
2497 (u32)svm->vmcb->control.exit_info_2;
2498 }
2499 kvm_clear_exception_queue(&svm->vcpu);
2500 break;
2501 case SVM_EXITINTINFO_TYPE_INTR:
2502 kvm_clear_interrupt_queue(&svm->vcpu);
2503 break;
2504 default:
2505 break;
2506 }
2507 }
2508
2509 if (reason != TASK_SWITCH_GATE ||
2510 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2511 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2512 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2513 skip_emulated_instruction(&svm->vcpu);
2514
2515 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2516 has_error_code, error_code) == EMULATE_FAIL) {
2517 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2518 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2519 svm->vcpu.run->internal.ndata = 0;
2520 return 0;
2521 }
2522 return 1;
2523 }
2524
2525 static int cpuid_interception(struct vcpu_svm *svm)
2526 {
2527 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2528 kvm_emulate_cpuid(&svm->vcpu);
2529 return 1;
2530 }
2531
2532 static int iret_interception(struct vcpu_svm *svm)
2533 {
2534 ++svm->vcpu.stat.nmi_window_exits;
2535 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2536 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2537 return 1;
2538 }
2539
2540 static int invlpg_interception(struct vcpu_svm *svm)
2541 {
2542 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2543 }
2544
2545 static int emulate_on_interception(struct vcpu_svm *svm)
2546 {
2547 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2548 }
2549
2550 static int cr0_write_interception(struct vcpu_svm *svm)
2551 {
2552 struct kvm_vcpu *vcpu = &svm->vcpu;
2553 int r;
2554
2555 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2556
2557 if (svm->nested.vmexit_rip) {
2558 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2559 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2560 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2561 svm->nested.vmexit_rip = 0;
2562 }
2563
2564 return r == EMULATE_DONE;
2565 }
2566
2567 static int cr8_write_interception(struct vcpu_svm *svm)
2568 {
2569 struct kvm_run *kvm_run = svm->vcpu.run;
2570
2571 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2572 /* instruction emulation calls kvm_set_cr8() */
2573 emulate_instruction(&svm->vcpu, 0, 0, 0);
2574 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2575 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2576 return 1;
2577 }
2578 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2579 return 1;
2580 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2581 return 0;
2582 }
2583
2584 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2585 {
2586 struct vcpu_svm *svm = to_svm(vcpu);
2587
2588 switch (ecx) {
2589 case MSR_IA32_TSC: {
2590 u64 tsc_offset;
2591
2592 if (is_nested(svm))
2593 tsc_offset = svm->nested.hsave->control.tsc_offset;
2594 else
2595 tsc_offset = svm->vmcb->control.tsc_offset;
2596
2597 *data = tsc_offset + native_read_tsc();
2598 break;
2599 }
2600 case MSR_STAR:
2601 *data = svm->vmcb->save.star;
2602 break;
2603 #ifdef CONFIG_X86_64
2604 case MSR_LSTAR:
2605 *data = svm->vmcb->save.lstar;
2606 break;
2607 case MSR_CSTAR:
2608 *data = svm->vmcb->save.cstar;
2609 break;
2610 case MSR_KERNEL_GS_BASE:
2611 *data = svm->vmcb->save.kernel_gs_base;
2612 break;
2613 case MSR_SYSCALL_MASK:
2614 *data = svm->vmcb->save.sfmask;
2615 break;
2616 #endif
2617 case MSR_IA32_SYSENTER_CS:
2618 *data = svm->vmcb->save.sysenter_cs;
2619 break;
2620 case MSR_IA32_SYSENTER_EIP:
2621 *data = svm->sysenter_eip;
2622 break;
2623 case MSR_IA32_SYSENTER_ESP:
2624 *data = svm->sysenter_esp;
2625 break;
2626 /*
2627 * Nobody will change the following 5 values in the VMCB so we can
2628 * safely return them on rdmsr. They will always be 0 until LBRV is
2629 * implemented.
2630 */
2631 case MSR_IA32_DEBUGCTLMSR:
2632 *data = svm->vmcb->save.dbgctl;
2633 break;
2634 case MSR_IA32_LASTBRANCHFROMIP:
2635 *data = svm->vmcb->save.br_from;
2636 break;
2637 case MSR_IA32_LASTBRANCHTOIP:
2638 *data = svm->vmcb->save.br_to;
2639 break;
2640 case MSR_IA32_LASTINTFROMIP:
2641 *data = svm->vmcb->save.last_excp_from;
2642 break;
2643 case MSR_IA32_LASTINTTOIP:
2644 *data = svm->vmcb->save.last_excp_to;
2645 break;
2646 case MSR_VM_HSAVE_PA:
2647 *data = svm->nested.hsave_msr;
2648 break;
2649 case MSR_VM_CR:
2650 *data = svm->nested.vm_cr_msr;
2651 break;
2652 case MSR_IA32_UCODE_REV:
2653 *data = 0x01000065;
2654 break;
2655 default:
2656 return kvm_get_msr_common(vcpu, ecx, data);
2657 }
2658 return 0;
2659 }
2660
2661 static int rdmsr_interception(struct vcpu_svm *svm)
2662 {
2663 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2664 u64 data;
2665
2666 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2667 trace_kvm_msr_read_ex(ecx);
2668 kvm_inject_gp(&svm->vcpu, 0);
2669 } else {
2670 trace_kvm_msr_read(ecx, data);
2671
2672 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2673 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2674 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2675 skip_emulated_instruction(&svm->vcpu);
2676 }
2677 return 1;
2678 }
2679
2680 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2681 {
2682 struct vcpu_svm *svm = to_svm(vcpu);
2683 int svm_dis, chg_mask;
2684
2685 if (data & ~SVM_VM_CR_VALID_MASK)
2686 return 1;
2687
2688 chg_mask = SVM_VM_CR_VALID_MASK;
2689
2690 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2691 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2692
2693 svm->nested.vm_cr_msr &= ~chg_mask;
2694 svm->nested.vm_cr_msr |= (data & chg_mask);
2695
2696 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2697
2698 /* check for svm_disable while efer.svme is set */
2699 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2700 return 1;
2701
2702 return 0;
2703 }
2704
2705 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2706 {
2707 struct vcpu_svm *svm = to_svm(vcpu);
2708
2709 switch (ecx) {
2710 case MSR_IA32_TSC:
2711 kvm_write_tsc(vcpu, data);
2712 break;
2713 case MSR_STAR:
2714 svm->vmcb->save.star = data;
2715 break;
2716 #ifdef CONFIG_X86_64
2717 case MSR_LSTAR:
2718 svm->vmcb->save.lstar = data;
2719 break;
2720 case MSR_CSTAR:
2721 svm->vmcb->save.cstar = data;
2722 break;
2723 case MSR_KERNEL_GS_BASE:
2724 svm->vmcb->save.kernel_gs_base = data;
2725 break;
2726 case MSR_SYSCALL_MASK:
2727 svm->vmcb->save.sfmask = data;
2728 break;
2729 #endif
2730 case MSR_IA32_SYSENTER_CS:
2731 svm->vmcb->save.sysenter_cs = data;
2732 break;
2733 case MSR_IA32_SYSENTER_EIP:
2734 svm->sysenter_eip = data;
2735 svm->vmcb->save.sysenter_eip = data;
2736 break;
2737 case MSR_IA32_SYSENTER_ESP:
2738 svm->sysenter_esp = data;
2739 svm->vmcb->save.sysenter_esp = data;
2740 break;
2741 case MSR_IA32_DEBUGCTLMSR:
2742 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2743 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2744 __func__, data);
2745 break;
2746 }
2747 if (data & DEBUGCTL_RESERVED_BITS)
2748 return 1;
2749
2750 svm->vmcb->save.dbgctl = data;
2751 if (data & (1ULL<<0))
2752 svm_enable_lbrv(svm);
2753 else
2754 svm_disable_lbrv(svm);
2755 break;
2756 case MSR_VM_HSAVE_PA:
2757 svm->nested.hsave_msr = data;
2758 break;
2759 case MSR_VM_CR:
2760 return svm_set_vm_cr(vcpu, data);
2761 case MSR_VM_IGNNE:
2762 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2763 break;
2764 default:
2765 return kvm_set_msr_common(vcpu, ecx, data);
2766 }
2767 return 0;
2768 }
2769
2770 static int wrmsr_interception(struct vcpu_svm *svm)
2771 {
2772 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2773 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2774 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2775
2776
2777 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2778 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2779 trace_kvm_msr_write_ex(ecx, data);
2780 kvm_inject_gp(&svm->vcpu, 0);
2781 } else {
2782 trace_kvm_msr_write(ecx, data);
2783 skip_emulated_instruction(&svm->vcpu);
2784 }
2785 return 1;
2786 }
2787
2788 static int msr_interception(struct vcpu_svm *svm)
2789 {
2790 if (svm->vmcb->control.exit_info_1)
2791 return wrmsr_interception(svm);
2792 else
2793 return rdmsr_interception(svm);
2794 }
2795
2796 static int interrupt_window_interception(struct vcpu_svm *svm)
2797 {
2798 struct kvm_run *kvm_run = svm->vcpu.run;
2799
2800 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2801 svm_clear_vintr(svm);
2802 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2803 /*
2804 * If the user space waits to inject interrupts, exit as soon as
2805 * possible
2806 */
2807 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2808 kvm_run->request_interrupt_window &&
2809 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2810 ++svm->vcpu.stat.irq_window_exits;
2811 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2812 return 0;
2813 }
2814
2815 return 1;
2816 }
2817
2818 static int pause_interception(struct vcpu_svm *svm)
2819 {
2820 kvm_vcpu_on_spin(&(svm->vcpu));
2821 return 1;
2822 }
2823
2824 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2825 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2826 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2827 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2828 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2829 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2830 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2831 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2832 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2833 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2834 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2835 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2836 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2837 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2838 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2839 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2840 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2841 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2842 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2843 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2844 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2845 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2846 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2847 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2848 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2849 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2850 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2851 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2852 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2853 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2854 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2855 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2856 [SVM_EXIT_INTR] = intr_interception,
2857 [SVM_EXIT_NMI] = nmi_interception,
2858 [SVM_EXIT_SMI] = nop_on_interception,
2859 [SVM_EXIT_INIT] = nop_on_interception,
2860 [SVM_EXIT_VINTR] = interrupt_window_interception,
2861 [SVM_EXIT_CPUID] = cpuid_interception,
2862 [SVM_EXIT_IRET] = iret_interception,
2863 [SVM_EXIT_INVD] = emulate_on_interception,
2864 [SVM_EXIT_PAUSE] = pause_interception,
2865 [SVM_EXIT_HLT] = halt_interception,
2866 [SVM_EXIT_INVLPG] = invlpg_interception,
2867 [SVM_EXIT_INVLPGA] = invlpga_interception,
2868 [SVM_EXIT_IOIO] = io_interception,
2869 [SVM_EXIT_MSR] = msr_interception,
2870 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2871 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2872 [SVM_EXIT_VMRUN] = vmrun_interception,
2873 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2874 [SVM_EXIT_VMLOAD] = vmload_interception,
2875 [SVM_EXIT_VMSAVE] = vmsave_interception,
2876 [SVM_EXIT_STGI] = stgi_interception,
2877 [SVM_EXIT_CLGI] = clgi_interception,
2878 [SVM_EXIT_SKINIT] = skinit_interception,
2879 [SVM_EXIT_WBINVD] = emulate_on_interception,
2880 [SVM_EXIT_MONITOR] = invalid_op_interception,
2881 [SVM_EXIT_MWAIT] = invalid_op_interception,
2882 [SVM_EXIT_NPF] = pf_interception,
2883 };
2884
2885 void dump_vmcb(struct kvm_vcpu *vcpu)
2886 {
2887 struct vcpu_svm *svm = to_svm(vcpu);
2888 struct vmcb_control_area *control = &svm->vmcb->control;
2889 struct vmcb_save_area *save = &svm->vmcb->save;
2890
2891 pr_err("VMCB Control Area:\n");
2892 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2893 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2894 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2895 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2896 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2897 pr_err("intercepts: %016llx\n", control->intercept);
2898 pr_err("pause filter count: %d\n", control->pause_filter_count);
2899 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2900 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2901 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2902 pr_err("asid: %d\n", control->asid);
2903 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2904 pr_err("int_ctl: %08x\n", control->int_ctl);
2905 pr_err("int_vector: %08x\n", control->int_vector);
2906 pr_err("int_state: %08x\n", control->int_state);
2907 pr_err("exit_code: %08x\n", control->exit_code);
2908 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2909 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2910 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2911 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2912 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2913 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2914 pr_err("event_inj: %08x\n", control->event_inj);
2915 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2916 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2917 pr_err("next_rip: %016llx\n", control->next_rip);
2918 pr_err("VMCB State Save Area:\n");
2919 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2920 save->es.selector, save->es.attrib,
2921 save->es.limit, save->es.base);
2922 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2923 save->cs.selector, save->cs.attrib,
2924 save->cs.limit, save->cs.base);
2925 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2926 save->ss.selector, save->ss.attrib,
2927 save->ss.limit, save->ss.base);
2928 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2929 save->ds.selector, save->ds.attrib,
2930 save->ds.limit, save->ds.base);
2931 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2932 save->fs.selector, save->fs.attrib,
2933 save->fs.limit, save->fs.base);
2934 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2935 save->gs.selector, save->gs.attrib,
2936 save->gs.limit, save->gs.base);
2937 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2938 save->gdtr.selector, save->gdtr.attrib,
2939 save->gdtr.limit, save->gdtr.base);
2940 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2941 save->ldtr.selector, save->ldtr.attrib,
2942 save->ldtr.limit, save->ldtr.base);
2943 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2944 save->idtr.selector, save->idtr.attrib,
2945 save->idtr.limit, save->idtr.base);
2946 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2947 save->tr.selector, save->tr.attrib,
2948 save->tr.limit, save->tr.base);
2949 pr_err("cpl: %d efer: %016llx\n",
2950 save->cpl, save->efer);
2951 pr_err("cr0: %016llx cr2: %016llx\n",
2952 save->cr0, save->cr2);
2953 pr_err("cr3: %016llx cr4: %016llx\n",
2954 save->cr3, save->cr4);
2955 pr_err("dr6: %016llx dr7: %016llx\n",
2956 save->dr6, save->dr7);
2957 pr_err("rip: %016llx rflags: %016llx\n",
2958 save->rip, save->rflags);
2959 pr_err("rsp: %016llx rax: %016llx\n",
2960 save->rsp, save->rax);
2961 pr_err("star: %016llx lstar: %016llx\n",
2962 save->star, save->lstar);
2963 pr_err("cstar: %016llx sfmask: %016llx\n",
2964 save->cstar, save->sfmask);
2965 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2966 save->kernel_gs_base, save->sysenter_cs);
2967 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2968 save->sysenter_esp, save->sysenter_eip);
2969 pr_err("gpat: %016llx dbgctl: %016llx\n",
2970 save->g_pat, save->dbgctl);
2971 pr_err("br_from: %016llx br_to: %016llx\n",
2972 save->br_from, save->br_to);
2973 pr_err("excp_from: %016llx excp_to: %016llx\n",
2974 save->last_excp_from, save->last_excp_to);
2975
2976 }
2977
2978 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2979 {
2980 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2981
2982 *info1 = control->exit_info_1;
2983 *info2 = control->exit_info_2;
2984 }
2985
2986 static int handle_exit(struct kvm_vcpu *vcpu)
2987 {
2988 struct vcpu_svm *svm = to_svm(vcpu);
2989 struct kvm_run *kvm_run = vcpu->run;
2990 u32 exit_code = svm->vmcb->control.exit_code;
2991
2992 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2993
2994 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2995 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2996 if (npt_enabled)
2997 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2998
2999 if (unlikely(svm->nested.exit_required)) {
3000 nested_svm_vmexit(svm);
3001 svm->nested.exit_required = false;
3002
3003 return 1;
3004 }
3005
3006 if (is_nested(svm)) {
3007 int vmexit;
3008
3009 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3010 svm->vmcb->control.exit_info_1,
3011 svm->vmcb->control.exit_info_2,
3012 svm->vmcb->control.exit_int_info,
3013 svm->vmcb->control.exit_int_info_err);
3014
3015 vmexit = nested_svm_exit_special(svm);
3016
3017 if (vmexit == NESTED_EXIT_CONTINUE)
3018 vmexit = nested_svm_exit_handled(svm);
3019
3020 if (vmexit == NESTED_EXIT_DONE)
3021 return 1;
3022 }
3023
3024 svm_complete_interrupts(svm);
3025
3026 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3027 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3028 kvm_run->fail_entry.hardware_entry_failure_reason
3029 = svm->vmcb->control.exit_code;
3030 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3031 dump_vmcb(vcpu);
3032 return 0;
3033 }
3034
3035 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3036 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3037 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3038 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3039 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3040 "exit_code 0x%x\n",
3041 __func__, svm->vmcb->control.exit_int_info,
3042 exit_code);
3043
3044 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3045 || !svm_exit_handlers[exit_code]) {
3046 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3047 kvm_run->hw.hardware_exit_reason = exit_code;
3048 return 0;
3049 }
3050
3051 return svm_exit_handlers[exit_code](svm);
3052 }
3053
3054 static void reload_tss(struct kvm_vcpu *vcpu)
3055 {
3056 int cpu = raw_smp_processor_id();
3057
3058 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3059 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3060 load_TR_desc();
3061 }
3062
3063 static void pre_svm_run(struct vcpu_svm *svm)
3064 {
3065 int cpu = raw_smp_processor_id();
3066
3067 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3068
3069 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3070 /* FIXME: handle wraparound of asid_generation */
3071 if (svm->asid_generation != sd->asid_generation)
3072 new_asid(svm, sd);
3073 }
3074
3075 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3076 {
3077 struct vcpu_svm *svm = to_svm(vcpu);
3078
3079 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3080 vcpu->arch.hflags |= HF_NMI_MASK;
3081 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3082 ++vcpu->stat.nmi_injections;
3083 }
3084
3085 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3086 {
3087 struct vmcb_control_area *control;
3088
3089 control = &svm->vmcb->control;
3090 control->int_vector = irq;
3091 control->int_ctl &= ~V_INTR_PRIO_MASK;
3092 control->int_ctl |= V_IRQ_MASK |
3093 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3094 }
3095
3096 static void svm_set_irq(struct kvm_vcpu *vcpu)
3097 {
3098 struct vcpu_svm *svm = to_svm(vcpu);
3099
3100 BUG_ON(!(gif_set(svm)));
3101
3102 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3103 ++vcpu->stat.irq_injections;
3104
3105 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3106 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3107 }
3108
3109 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3110 {
3111 struct vcpu_svm *svm = to_svm(vcpu);
3112
3113 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3114 return;
3115
3116 if (irr == -1)
3117 return;
3118
3119 if (tpr >= irr)
3120 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3121 }
3122
3123 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3124 {
3125 struct vcpu_svm *svm = to_svm(vcpu);
3126 struct vmcb *vmcb = svm->vmcb;
3127 int ret;
3128 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3129 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3130 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3131
3132 return ret;
3133 }
3134
3135 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3136 {
3137 struct vcpu_svm *svm = to_svm(vcpu);
3138
3139 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3140 }
3141
3142 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3143 {
3144 struct vcpu_svm *svm = to_svm(vcpu);
3145
3146 if (masked) {
3147 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3148 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3149 } else {
3150 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3151 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3152 }
3153 }
3154
3155 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3156 {
3157 struct vcpu_svm *svm = to_svm(vcpu);
3158 struct vmcb *vmcb = svm->vmcb;
3159 int ret;
3160
3161 if (!gif_set(svm) ||
3162 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3163 return 0;
3164
3165 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3166
3167 if (is_nested(svm))
3168 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3169
3170 return ret;
3171 }
3172
3173 static void enable_irq_window(struct kvm_vcpu *vcpu)
3174 {
3175 struct vcpu_svm *svm = to_svm(vcpu);
3176
3177 /*
3178 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3179 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3180 * get that intercept, this function will be called again though and
3181 * we'll get the vintr intercept.
3182 */
3183 if (gif_set(svm) && nested_svm_intr(svm)) {
3184 svm_set_vintr(svm);
3185 svm_inject_irq(svm, 0x0);
3186 }
3187 }
3188
3189 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3190 {
3191 struct vcpu_svm *svm = to_svm(vcpu);
3192
3193 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3194 == HF_NMI_MASK)
3195 return; /* IRET will cause a vm exit */
3196
3197 /*
3198 * Something prevents NMI from been injected. Single step over possible
3199 * problem (IRET or exception injection or interrupt shadow)
3200 */
3201 svm->nmi_singlestep = true;
3202 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3203 update_db_intercept(vcpu);
3204 }
3205
3206 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3207 {
3208 return 0;
3209 }
3210
3211 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3212 {
3213 force_new_asid(vcpu);
3214 }
3215
3216 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3217 {
3218 }
3219
3220 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3221 {
3222 struct vcpu_svm *svm = to_svm(vcpu);
3223
3224 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3225 return;
3226
3227 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3228 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3229 kvm_set_cr8(vcpu, cr8);
3230 }
3231 }
3232
3233 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3234 {
3235 struct vcpu_svm *svm = to_svm(vcpu);
3236 u64 cr8;
3237
3238 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3239 return;
3240
3241 cr8 = kvm_get_cr8(vcpu);
3242 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3243 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3244 }
3245
3246 static void svm_complete_interrupts(struct vcpu_svm *svm)
3247 {
3248 u8 vector;
3249 int type;
3250 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3251 unsigned int3_injected = svm->int3_injected;
3252
3253 svm->int3_injected = 0;
3254
3255 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3256 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3257 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3258 }
3259
3260 svm->vcpu.arch.nmi_injected = false;
3261 kvm_clear_exception_queue(&svm->vcpu);
3262 kvm_clear_interrupt_queue(&svm->vcpu);
3263
3264 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3265 return;
3266
3267 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3268
3269 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3270 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3271
3272 switch (type) {
3273 case SVM_EXITINTINFO_TYPE_NMI:
3274 svm->vcpu.arch.nmi_injected = true;
3275 break;
3276 case SVM_EXITINTINFO_TYPE_EXEPT:
3277 /*
3278 * In case of software exceptions, do not reinject the vector,
3279 * but re-execute the instruction instead. Rewind RIP first
3280 * if we emulated INT3 before.
3281 */
3282 if (kvm_exception_is_soft(vector)) {
3283 if (vector == BP_VECTOR && int3_injected &&
3284 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3285 kvm_rip_write(&svm->vcpu,
3286 kvm_rip_read(&svm->vcpu) -
3287 int3_injected);
3288 break;
3289 }
3290 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3291 u32 err = svm->vmcb->control.exit_int_info_err;
3292 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3293
3294 } else
3295 kvm_requeue_exception(&svm->vcpu, vector);
3296 break;
3297 case SVM_EXITINTINFO_TYPE_INTR:
3298 kvm_queue_interrupt(&svm->vcpu, vector, false);
3299 break;
3300 default:
3301 break;
3302 }
3303 }
3304
3305 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3306 {
3307 struct vcpu_svm *svm = to_svm(vcpu);
3308 struct vmcb_control_area *control = &svm->vmcb->control;
3309
3310 control->exit_int_info = control->event_inj;
3311 control->exit_int_info_err = control->event_inj_err;
3312 control->event_inj = 0;
3313 svm_complete_interrupts(svm);
3314 }
3315
3316 #ifdef CONFIG_X86_64
3317 #define R "r"
3318 #else
3319 #define R "e"
3320 #endif
3321
3322 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3323 {
3324 struct vcpu_svm *svm = to_svm(vcpu);
3325
3326 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3327 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3328 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3329
3330 /*
3331 * A vmexit emulation is required before the vcpu can be executed
3332 * again.
3333 */
3334 if (unlikely(svm->nested.exit_required))
3335 return;
3336
3337 pre_svm_run(svm);
3338
3339 sync_lapic_to_cr8(vcpu);
3340
3341 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3342
3343 clgi();
3344
3345 local_irq_enable();
3346
3347 asm volatile (
3348 "push %%"R"bp; \n\t"
3349 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3350 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3351 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3352 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3353 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3354 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3355 #ifdef CONFIG_X86_64
3356 "mov %c[r8](%[svm]), %%r8 \n\t"
3357 "mov %c[r9](%[svm]), %%r9 \n\t"
3358 "mov %c[r10](%[svm]), %%r10 \n\t"
3359 "mov %c[r11](%[svm]), %%r11 \n\t"
3360 "mov %c[r12](%[svm]), %%r12 \n\t"
3361 "mov %c[r13](%[svm]), %%r13 \n\t"
3362 "mov %c[r14](%[svm]), %%r14 \n\t"
3363 "mov %c[r15](%[svm]), %%r15 \n\t"
3364 #endif
3365
3366 /* Enter guest mode */
3367 "push %%"R"ax \n\t"
3368 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3369 __ex(SVM_VMLOAD) "\n\t"
3370 __ex(SVM_VMRUN) "\n\t"
3371 __ex(SVM_VMSAVE) "\n\t"
3372 "pop %%"R"ax \n\t"
3373
3374 /* Save guest registers, load host registers */
3375 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3376 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3377 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3378 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3379 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3380 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3381 #ifdef CONFIG_X86_64
3382 "mov %%r8, %c[r8](%[svm]) \n\t"
3383 "mov %%r9, %c[r9](%[svm]) \n\t"
3384 "mov %%r10, %c[r10](%[svm]) \n\t"
3385 "mov %%r11, %c[r11](%[svm]) \n\t"
3386 "mov %%r12, %c[r12](%[svm]) \n\t"
3387 "mov %%r13, %c[r13](%[svm]) \n\t"
3388 "mov %%r14, %c[r14](%[svm]) \n\t"
3389 "mov %%r15, %c[r15](%[svm]) \n\t"
3390 #endif
3391 "pop %%"R"bp"
3392 :
3393 : [svm]"a"(svm),
3394 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3395 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3396 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3397 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3398 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3399 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3400 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3401 #ifdef CONFIG_X86_64
3402 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3403 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3404 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3405 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3406 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3407 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3408 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3409 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3410 #endif
3411 : "cc", "memory"
3412 , R"bx", R"cx", R"dx", R"si", R"di"
3413 #ifdef CONFIG_X86_64
3414 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3415 #endif
3416 );
3417
3418 #ifdef CONFIG_X86_64
3419 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3420 #else
3421 loadsegment(fs, svm->host.fs);
3422 #endif
3423
3424 reload_tss(vcpu);
3425
3426 local_irq_disable();
3427
3428 stgi();
3429
3430 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3431 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3432 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3433 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3434
3435 sync_cr8_to_lapic(vcpu);
3436
3437 svm->next_rip = 0;
3438
3439 /* if exit due to PF check for async PF */
3440 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3441 svm->apf_reason = kvm_read_and_reset_pf_reason();
3442
3443 if (npt_enabled) {
3444 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3445 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3446 }
3447
3448 /*
3449 * We need to handle MC intercepts here before the vcpu has a chance to
3450 * change the physical cpu
3451 */
3452 if (unlikely(svm->vmcb->control.exit_code ==
3453 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3454 svm_handle_mce(svm);
3455 }
3456
3457 #undef R
3458
3459 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3460 {
3461 struct vcpu_svm *svm = to_svm(vcpu);
3462
3463 svm->vmcb->save.cr3 = root;
3464 force_new_asid(vcpu);
3465 }
3466
3467 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3468 {
3469 struct vcpu_svm *svm = to_svm(vcpu);
3470
3471 svm->vmcb->control.nested_cr3 = root;
3472
3473 /* Also sync guest cr3 here in case we live migrate */
3474 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3475
3476 force_new_asid(vcpu);
3477 }
3478
3479 static int is_disabled(void)
3480 {
3481 u64 vm_cr;
3482
3483 rdmsrl(MSR_VM_CR, vm_cr);
3484 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3485 return 1;
3486
3487 return 0;
3488 }
3489
3490 static void
3491 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3492 {
3493 /*
3494 * Patch in the VMMCALL instruction:
3495 */
3496 hypercall[0] = 0x0f;
3497 hypercall[1] = 0x01;
3498 hypercall[2] = 0xd9;
3499 }
3500
3501 static void svm_check_processor_compat(void *rtn)
3502 {
3503 *(int *)rtn = 0;
3504 }
3505
3506 static bool svm_cpu_has_accelerated_tpr(void)
3507 {
3508 return false;
3509 }
3510
3511 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3512 {
3513 return 0;
3514 }
3515
3516 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3517 {
3518 }
3519
3520 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3521 {
3522 switch (func) {
3523 case 0x00000001:
3524 /* Mask out xsave bit as long as it is not supported by SVM */
3525 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3526 break;
3527 case 0x80000001:
3528 if (nested)
3529 entry->ecx |= (1 << 2); /* Set SVM bit */
3530 break;
3531 case 0x8000000A:
3532 entry->eax = 1; /* SVM revision 1 */
3533 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3534 ASID emulation to nested SVM */
3535 entry->ecx = 0; /* Reserved */
3536 entry->edx = 0; /* Per default do not support any
3537 additional features */
3538
3539 /* Support next_rip if host supports it */
3540 if (boot_cpu_has(X86_FEATURE_NRIPS))
3541 entry->edx |= SVM_FEATURE_NRIP;
3542
3543 /* Support NPT for the guest if enabled */
3544 if (npt_enabled)
3545 entry->edx |= SVM_FEATURE_NPT;
3546
3547 break;
3548 }
3549 }
3550
3551 static const struct trace_print_flags svm_exit_reasons_str[] = {
3552 { SVM_EXIT_READ_CR0, "read_cr0" },
3553 { SVM_EXIT_READ_CR3, "read_cr3" },
3554 { SVM_EXIT_READ_CR4, "read_cr4" },
3555 { SVM_EXIT_READ_CR8, "read_cr8" },
3556 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3557 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3558 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3559 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3560 { SVM_EXIT_READ_DR0, "read_dr0" },
3561 { SVM_EXIT_READ_DR1, "read_dr1" },
3562 { SVM_EXIT_READ_DR2, "read_dr2" },
3563 { SVM_EXIT_READ_DR3, "read_dr3" },
3564 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3565 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3566 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3567 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3568 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3569 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3570 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3571 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3572 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3573 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3574 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3575 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3576 { SVM_EXIT_INTR, "interrupt" },
3577 { SVM_EXIT_NMI, "nmi" },
3578 { SVM_EXIT_SMI, "smi" },
3579 { SVM_EXIT_INIT, "init" },
3580 { SVM_EXIT_VINTR, "vintr" },
3581 { SVM_EXIT_CPUID, "cpuid" },
3582 { SVM_EXIT_INVD, "invd" },
3583 { SVM_EXIT_HLT, "hlt" },
3584 { SVM_EXIT_INVLPG, "invlpg" },
3585 { SVM_EXIT_INVLPGA, "invlpga" },
3586 { SVM_EXIT_IOIO, "io" },
3587 { SVM_EXIT_MSR, "msr" },
3588 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3589 { SVM_EXIT_SHUTDOWN, "shutdown" },
3590 { SVM_EXIT_VMRUN, "vmrun" },
3591 { SVM_EXIT_VMMCALL, "hypercall" },
3592 { SVM_EXIT_VMLOAD, "vmload" },
3593 { SVM_EXIT_VMSAVE, "vmsave" },
3594 { SVM_EXIT_STGI, "stgi" },
3595 { SVM_EXIT_CLGI, "clgi" },
3596 { SVM_EXIT_SKINIT, "skinit" },
3597 { SVM_EXIT_WBINVD, "wbinvd" },
3598 { SVM_EXIT_MONITOR, "monitor" },
3599 { SVM_EXIT_MWAIT, "mwait" },
3600 { SVM_EXIT_NPF, "npf" },
3601 { -1, NULL }
3602 };
3603
3604 static int svm_get_lpage_level(void)
3605 {
3606 return PT_PDPE_LEVEL;
3607 }
3608
3609 static bool svm_rdtscp_supported(void)
3610 {
3611 return false;
3612 }
3613
3614 static bool svm_has_wbinvd_exit(void)
3615 {
3616 return true;
3617 }
3618
3619 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3620 {
3621 struct vcpu_svm *svm = to_svm(vcpu);
3622
3623 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3624 if (is_nested(svm))
3625 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3626 update_cr0_intercept(svm);
3627 }
3628
3629 static struct kvm_x86_ops svm_x86_ops = {
3630 .cpu_has_kvm_support = has_svm,
3631 .disabled_by_bios = is_disabled,
3632 .hardware_setup = svm_hardware_setup,
3633 .hardware_unsetup = svm_hardware_unsetup,
3634 .check_processor_compatibility = svm_check_processor_compat,
3635 .hardware_enable = svm_hardware_enable,
3636 .hardware_disable = svm_hardware_disable,
3637 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3638
3639 .vcpu_create = svm_create_vcpu,
3640 .vcpu_free = svm_free_vcpu,
3641 .vcpu_reset = svm_vcpu_reset,
3642
3643 .prepare_guest_switch = svm_prepare_guest_switch,
3644 .vcpu_load = svm_vcpu_load,
3645 .vcpu_put = svm_vcpu_put,
3646
3647 .set_guest_debug = svm_guest_debug,
3648 .get_msr = svm_get_msr,
3649 .set_msr = svm_set_msr,
3650 .get_segment_base = svm_get_segment_base,
3651 .get_segment = svm_get_segment,
3652 .set_segment = svm_set_segment,
3653 .get_cpl = svm_get_cpl,
3654 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3655 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3656 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3657 .set_cr0 = svm_set_cr0,
3658 .set_cr3 = svm_set_cr3,
3659 .set_cr4 = svm_set_cr4,
3660 .set_efer = svm_set_efer,
3661 .get_idt = svm_get_idt,
3662 .set_idt = svm_set_idt,
3663 .get_gdt = svm_get_gdt,
3664 .set_gdt = svm_set_gdt,
3665 .set_dr7 = svm_set_dr7,
3666 .cache_reg = svm_cache_reg,
3667 .get_rflags = svm_get_rflags,
3668 .set_rflags = svm_set_rflags,
3669 .fpu_activate = svm_fpu_activate,
3670 .fpu_deactivate = svm_fpu_deactivate,
3671
3672 .tlb_flush = svm_flush_tlb,
3673
3674 .run = svm_vcpu_run,
3675 .handle_exit = handle_exit,
3676 .skip_emulated_instruction = skip_emulated_instruction,
3677 .set_interrupt_shadow = svm_set_interrupt_shadow,
3678 .get_interrupt_shadow = svm_get_interrupt_shadow,
3679 .patch_hypercall = svm_patch_hypercall,
3680 .set_irq = svm_set_irq,
3681 .set_nmi = svm_inject_nmi,
3682 .queue_exception = svm_queue_exception,
3683 .cancel_injection = svm_cancel_injection,
3684 .interrupt_allowed = svm_interrupt_allowed,
3685 .nmi_allowed = svm_nmi_allowed,
3686 .get_nmi_mask = svm_get_nmi_mask,
3687 .set_nmi_mask = svm_set_nmi_mask,
3688 .enable_nmi_window = enable_nmi_window,
3689 .enable_irq_window = enable_irq_window,
3690 .update_cr8_intercept = update_cr8_intercept,
3691
3692 .set_tss_addr = svm_set_tss_addr,
3693 .get_tdp_level = get_npt_level,
3694 .get_mt_mask = svm_get_mt_mask,
3695
3696 .get_exit_info = svm_get_exit_info,
3697 .exit_reasons_str = svm_exit_reasons_str,
3698
3699 .get_lpage_level = svm_get_lpage_level,
3700
3701 .cpuid_update = svm_cpuid_update,
3702
3703 .rdtscp_supported = svm_rdtscp_supported,
3704
3705 .set_supported_cpuid = svm_set_supported_cpuid,
3706
3707 .has_wbinvd_exit = svm_has_wbinvd_exit,
3708
3709 .write_tsc_offset = svm_write_tsc_offset,
3710 .adjust_tsc_offset = svm_adjust_tsc_offset,
3711
3712 .set_tdp_cr3 = set_tdp_cr3,
3713 };
3714
3715 static int __init svm_init(void)
3716 {
3717 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3718 __alignof__(struct vcpu_svm), THIS_MODULE);
3719 }
3720
3721 static void __exit svm_exit(void)
3722 {
3723 kvm_exit();
3724 }
3725
3726 module_init(svm_init)
3727 module_exit(svm_exit)
Linux kernel - Deliverables
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