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KVM: x86: add functions to get the cpl of vcpu
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/vmalloc.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27
28 #include <asm/desc.h>
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 #define IOPM_ALLOC_ORDER 2
34 #define MSRPM_ALLOC_ORDER 1
35
36 #define DB_VECTOR 1
37 #define UD_VECTOR 6
38 #define GP_VECTOR 13
39
40 #define DR7_GD_MASK (1 << 13)
41 #define DR6_BD_MASK (1 << 13)
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_DEATURE_SVML (1 << 2)
49
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
52 /* enable NPT for AMD64 and X86 with PAE */
53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
54 static bool npt_enabled = true;
55 #else
56 static bool npt_enabled = false;
57 #endif
58 static int npt = 1;
59
60 module_param(npt, int, S_IRUGO);
61
62 static void kvm_reput_irq(struct vcpu_svm *svm);
63
64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
65 {
66 return container_of(vcpu, struct vcpu_svm, vcpu);
67 }
68
69 static unsigned long iopm_base;
70
71 struct kvm_ldttss_desc {
72 u16 limit0;
73 u16 base0;
74 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
75 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
76 u32 base3;
77 u32 zero1;
78 } __attribute__((packed));
79
80 struct svm_cpu_data {
81 int cpu;
82
83 u64 asid_generation;
84 u32 max_asid;
85 u32 next_asid;
86 struct kvm_ldttss_desc *tss_desc;
87
88 struct page *save_area;
89 };
90
91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
92 static uint32_t svm_features;
93
94 struct svm_init_data {
95 int cpu;
96 int r;
97 };
98
99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
100
101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
102 #define MSRS_RANGE_SIZE 2048
103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
104
105 #define MAX_INST_SIZE 15
106
107 static inline u32 svm_has(u32 feat)
108 {
109 return svm_features & feat;
110 }
111
112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
113 {
114 int word_index = __ffs(vcpu->arch.irq_summary);
115 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
116 int irq = word_index * BITS_PER_LONG + bit_index;
117
118 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
119 if (!vcpu->arch.irq_pending[word_index])
120 clear_bit(word_index, &vcpu->arch.irq_summary);
121 return irq;
122 }
123
124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
125 {
126 set_bit(irq, vcpu->arch.irq_pending);
127 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
128 }
129
130 static inline void clgi(void)
131 {
132 asm volatile (SVM_CLGI);
133 }
134
135 static inline void stgi(void)
136 {
137 asm volatile (SVM_STGI);
138 }
139
140 static inline void invlpga(unsigned long addr, u32 asid)
141 {
142 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
143 }
144
145 static inline unsigned long kvm_read_cr2(void)
146 {
147 unsigned long cr2;
148
149 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
150 return cr2;
151 }
152
153 static inline void kvm_write_cr2(unsigned long val)
154 {
155 asm volatile ("mov %0, %%cr2" :: "r" (val));
156 }
157
158 static inline unsigned long read_dr6(void)
159 {
160 unsigned long dr6;
161
162 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
163 return dr6;
164 }
165
166 static inline void write_dr6(unsigned long val)
167 {
168 asm volatile ("mov %0, %%dr6" :: "r" (val));
169 }
170
171 static inline unsigned long read_dr7(void)
172 {
173 unsigned long dr7;
174
175 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
176 return dr7;
177 }
178
179 static inline void write_dr7(unsigned long val)
180 {
181 asm volatile ("mov %0, %%dr7" :: "r" (val));
182 }
183
184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
185 {
186 to_svm(vcpu)->asid_generation--;
187 }
188
189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
190 {
191 force_new_asid(vcpu);
192 }
193
194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
195 {
196 if (!npt_enabled && !(efer & EFER_LMA))
197 efer &= ~EFER_LME;
198
199 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
200 vcpu->arch.shadow_efer = efer;
201 }
202
203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
204 bool has_error_code, u32 error_code)
205 {
206 struct vcpu_svm *svm = to_svm(vcpu);
207
208 svm->vmcb->control.event_inj = nr
209 | SVM_EVTINJ_VALID
210 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
211 | SVM_EVTINJ_TYPE_EXEPT;
212 svm->vmcb->control.event_inj_err = error_code;
213 }
214
215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
216 {
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
220 }
221
222 static int is_external_interrupt(u32 info)
223 {
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226 }
227
228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229 {
230 struct vcpu_svm *svm = to_svm(vcpu);
231
232 if (!svm->next_rip) {
233 printk(KERN_DEBUG "%s: NOP\n", __func__);
234 return;
235 }
236 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
237 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
238 __func__,
239 svm->vmcb->save.rip,
240 svm->next_rip);
241
242 vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
244
245 vcpu->arch.interrupt_window_open = 1;
246 }
247
248 static int has_svm(void)
249 {
250 uint32_t eax, ebx, ecx, edx;
251
252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
253 printk(KERN_INFO "has_svm: not amd\n");
254 return 0;
255 }
256
257 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
258 if (eax < SVM_CPUID_FUNC) {
259 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
260 return 0;
261 }
262
263 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
264 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
265 printk(KERN_DEBUG "has_svm: svm not available\n");
266 return 0;
267 }
268 return 1;
269 }
270
271 static void svm_hardware_disable(void *garbage)
272 {
273 struct svm_cpu_data *svm_data
274 = per_cpu(svm_data, raw_smp_processor_id());
275
276 if (svm_data) {
277 uint64_t efer;
278
279 wrmsrl(MSR_VM_HSAVE_PA, 0);
280 rdmsrl(MSR_EFER, efer);
281 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
283 __free_page(svm_data->save_area);
284 kfree(svm_data);
285 }
286 }
287
288 static void svm_hardware_enable(void *garbage)
289 {
290
291 struct svm_cpu_data *svm_data;
292 uint64_t efer;
293 struct desc_ptr gdt_descr;
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
296
297 if (!has_svm()) {
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
299 return;
300 }
301 svm_data = per_cpu(svm_data, me);
302
303 if (!svm_data) {
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
305 me);
306 return;
307 }
308
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312
313 asm volatile ("sgdt %0" : "=m"(gdt_descr));
314 gdt = (struct desc_struct *)gdt_descr.address;
315 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
316
317 rdmsrl(MSR_EFER, efer);
318 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
319
320 wrmsrl(MSR_VM_HSAVE_PA,
321 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
322 }
323
324 static int svm_cpu_init(int cpu)
325 {
326 struct svm_cpu_data *svm_data;
327 int r;
328
329 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
330 if (!svm_data)
331 return -ENOMEM;
332 svm_data->cpu = cpu;
333 svm_data->save_area = alloc_page(GFP_KERNEL);
334 r = -ENOMEM;
335 if (!svm_data->save_area)
336 goto err_1;
337
338 per_cpu(svm_data, cpu) = svm_data;
339
340 return 0;
341
342 err_1:
343 kfree(svm_data);
344 return r;
345
346 }
347
348 static void set_msr_interception(u32 *msrpm, unsigned msr,
349 int read, int write)
350 {
351 int i;
352
353 for (i = 0; i < NUM_MSR_MAPS; i++) {
354 if (msr >= msrpm_ranges[i] &&
355 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
356 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
357 msrpm_ranges[i]) * 2;
358
359 u32 *base = msrpm + (msr_offset / 32);
360 u32 msr_shift = msr_offset % 32;
361 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
362 *base = (*base & ~(0x3 << msr_shift)) |
363 (mask << msr_shift);
364 return;
365 }
366 }
367 BUG();
368 }
369
370 static void svm_vcpu_init_msrpm(u32 *msrpm)
371 {
372 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
373
374 #ifdef CONFIG_X86_64
375 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
376 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
377 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
378 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
379 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
380 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
381 #endif
382 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
383 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
386 }
387
388 static void svm_enable_lbrv(struct vcpu_svm *svm)
389 {
390 u32 *msrpm = svm->msrpm;
391
392 svm->vmcb->control.lbr_ctl = 1;
393 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
395 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
397 }
398
399 static void svm_disable_lbrv(struct vcpu_svm *svm)
400 {
401 u32 *msrpm = svm->msrpm;
402
403 svm->vmcb->control.lbr_ctl = 0;
404 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
405 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
406 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
407 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
408 }
409
410 static __init int svm_hardware_setup(void)
411 {
412 int cpu;
413 struct page *iopm_pages;
414 void *iopm_va;
415 int r;
416
417 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
418
419 if (!iopm_pages)
420 return -ENOMEM;
421
422 iopm_va = page_address(iopm_pages);
423 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
424 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
425 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
426
427 if (boot_cpu_has(X86_FEATURE_NX))
428 kvm_enable_efer_bits(EFER_NX);
429
430 for_each_online_cpu(cpu) {
431 r = svm_cpu_init(cpu);
432 if (r)
433 goto err;
434 }
435
436 svm_features = cpuid_edx(SVM_CPUID_FUNC);
437
438 if (!svm_has(SVM_FEATURE_NPT))
439 npt_enabled = false;
440
441 if (npt_enabled && !npt) {
442 printk(KERN_INFO "kvm: Nested Paging disabled\n");
443 npt_enabled = false;
444 }
445
446 if (npt_enabled) {
447 printk(KERN_INFO "kvm: Nested Paging enabled\n");
448 kvm_enable_tdp();
449 }
450
451 return 0;
452
453 err:
454 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
455 iopm_base = 0;
456 return r;
457 }
458
459 static __exit void svm_hardware_unsetup(void)
460 {
461 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
462 iopm_base = 0;
463 }
464
465 static void init_seg(struct vmcb_seg *seg)
466 {
467 seg->selector = 0;
468 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
469 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
470 seg->limit = 0xffff;
471 seg->base = 0;
472 }
473
474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
475 {
476 seg->selector = 0;
477 seg->attrib = SVM_SELECTOR_P_MASK | type;
478 seg->limit = 0xffff;
479 seg->base = 0;
480 }
481
482 static void init_vmcb(struct vcpu_svm *svm)
483 {
484 struct vmcb_control_area *control = &svm->vmcb->control;
485 struct vmcb_save_area *save = &svm->vmcb->save;
486
487 control->intercept_cr_read = INTERCEPT_CR0_MASK |
488 INTERCEPT_CR3_MASK |
489 INTERCEPT_CR4_MASK |
490 INTERCEPT_CR8_MASK;
491
492 control->intercept_cr_write = INTERCEPT_CR0_MASK |
493 INTERCEPT_CR3_MASK |
494 INTERCEPT_CR4_MASK |
495 INTERCEPT_CR8_MASK;
496
497 control->intercept_dr_read = INTERCEPT_DR0_MASK |
498 INTERCEPT_DR1_MASK |
499 INTERCEPT_DR2_MASK |
500 INTERCEPT_DR3_MASK;
501
502 control->intercept_dr_write = INTERCEPT_DR0_MASK |
503 INTERCEPT_DR1_MASK |
504 INTERCEPT_DR2_MASK |
505 INTERCEPT_DR3_MASK |
506 INTERCEPT_DR5_MASK |
507 INTERCEPT_DR7_MASK;
508
509 control->intercept_exceptions = (1 << PF_VECTOR) |
510 (1 << UD_VECTOR);
511
512
513 control->intercept = (1ULL << INTERCEPT_INTR) |
514 (1ULL << INTERCEPT_NMI) |
515 (1ULL << INTERCEPT_SMI) |
516 /*
517 * selective cr0 intercept bug?
518 * 0: 0f 22 d8 mov %eax,%cr3
519 * 3: 0f 20 c0 mov %cr0,%eax
520 * 6: 0d 00 00 00 80 or $0x80000000,%eax
521 * b: 0f 22 c0 mov %eax,%cr0
522 * set cr3 ->interception
523 * get cr0 ->interception
524 * set cr0 -> no interception
525 */
526 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
527 (1ULL << INTERCEPT_CPUID) |
528 (1ULL << INTERCEPT_INVD) |
529 (1ULL << INTERCEPT_HLT) |
530 (1ULL << INTERCEPT_INVLPGA) |
531 (1ULL << INTERCEPT_IOIO_PROT) |
532 (1ULL << INTERCEPT_MSR_PROT) |
533 (1ULL << INTERCEPT_TASK_SWITCH) |
534 (1ULL << INTERCEPT_SHUTDOWN) |
535 (1ULL << INTERCEPT_VMRUN) |
536 (1ULL << INTERCEPT_VMMCALL) |
537 (1ULL << INTERCEPT_VMLOAD) |
538 (1ULL << INTERCEPT_VMSAVE) |
539 (1ULL << INTERCEPT_STGI) |
540 (1ULL << INTERCEPT_CLGI) |
541 (1ULL << INTERCEPT_SKINIT) |
542 (1ULL << INTERCEPT_WBINVD) |
543 (1ULL << INTERCEPT_MONITOR) |
544 (1ULL << INTERCEPT_MWAIT);
545
546 control->iopm_base_pa = iopm_base;
547 control->msrpm_base_pa = __pa(svm->msrpm);
548 control->tsc_offset = 0;
549 control->int_ctl = V_INTR_MASKING_MASK;
550
551 init_seg(&save->es);
552 init_seg(&save->ss);
553 init_seg(&save->ds);
554 init_seg(&save->fs);
555 init_seg(&save->gs);
556
557 save->cs.selector = 0xf000;
558 /* Executable/Readable Code Segment */
559 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
560 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
561 save->cs.limit = 0xffff;
562 /*
563 * cs.base should really be 0xffff0000, but vmx can't handle that, so
564 * be consistent with it.
565 *
566 * Replace when we have real mode working for vmx.
567 */
568 save->cs.base = 0xf0000;
569
570 save->gdtr.limit = 0xffff;
571 save->idtr.limit = 0xffff;
572
573 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
574 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
575
576 save->efer = MSR_EFER_SVME_MASK;
577 save->dr6 = 0xffff0ff0;
578 save->dr7 = 0x400;
579 save->rflags = 2;
580 save->rip = 0x0000fff0;
581
582 /*
583 * cr0 val on cpu init should be 0x60000010, we enable cpu
584 * cache by default. the orderly way is to enable cache in bios.
585 */
586 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
587 save->cr4 = X86_CR4_PAE;
588 /* rdx = ?? */
589
590 if (npt_enabled) {
591 /* Setup VMCB for Nested Paging */
592 control->nested_ctl = 1;
593 control->intercept_exceptions &= ~(1 << PF_VECTOR);
594 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
595 INTERCEPT_CR3_MASK);
596 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
597 INTERCEPT_CR3_MASK);
598 save->g_pat = 0x0007040600070406ULL;
599 /* enable caching because the QEMU Bios doesn't enable it */
600 save->cr0 = X86_CR0_ET;
601 save->cr3 = 0;
602 save->cr4 = 0;
603 }
604
605 }
606
607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
608 {
609 struct vcpu_svm *svm = to_svm(vcpu);
610
611 init_vmcb(svm);
612
613 if (vcpu->vcpu_id != 0) {
614 svm->vmcb->save.rip = 0;
615 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
616 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
617 }
618
619 return 0;
620 }
621
622 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
623 {
624 struct vcpu_svm *svm;
625 struct page *page;
626 struct page *msrpm_pages;
627 int err;
628
629 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
630 if (!svm) {
631 err = -ENOMEM;
632 goto out;
633 }
634
635 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
636 if (err)
637 goto free_svm;
638
639 page = alloc_page(GFP_KERNEL);
640 if (!page) {
641 err = -ENOMEM;
642 goto uninit;
643 }
644
645 err = -ENOMEM;
646 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
647 if (!msrpm_pages)
648 goto uninit;
649 svm->msrpm = page_address(msrpm_pages);
650 svm_vcpu_init_msrpm(svm->msrpm);
651
652 svm->vmcb = page_address(page);
653 clear_page(svm->vmcb);
654 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
655 svm->asid_generation = 0;
656 memset(svm->db_regs, 0, sizeof(svm->db_regs));
657 init_vmcb(svm);
658
659 fx_init(&svm->vcpu);
660 svm->vcpu.fpu_active = 1;
661 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
662 if (svm->vcpu.vcpu_id == 0)
663 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
664
665 return &svm->vcpu;
666
667 uninit:
668 kvm_vcpu_uninit(&svm->vcpu);
669 free_svm:
670 kmem_cache_free(kvm_vcpu_cache, svm);
671 out:
672 return ERR_PTR(err);
673 }
674
675 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
676 {
677 struct vcpu_svm *svm = to_svm(vcpu);
678
679 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
680 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
681 kvm_vcpu_uninit(vcpu);
682 kmem_cache_free(kvm_vcpu_cache, svm);
683 }
684
685 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
686 {
687 struct vcpu_svm *svm = to_svm(vcpu);
688 int i;
689
690 if (unlikely(cpu != vcpu->cpu)) {
691 u64 tsc_this, delta;
692
693 /*
694 * Make sure that the guest sees a monotonically
695 * increasing TSC.
696 */
697 rdtscll(tsc_this);
698 delta = vcpu->arch.host_tsc - tsc_this;
699 svm->vmcb->control.tsc_offset += delta;
700 vcpu->cpu = cpu;
701 kvm_migrate_apic_timer(vcpu);
702 }
703
704 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
705 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
706 }
707
708 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
709 {
710 struct vcpu_svm *svm = to_svm(vcpu);
711 int i;
712
713 ++vcpu->stat.host_state_reload;
714 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
715 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
716
717 rdtscll(vcpu->arch.host_tsc);
718 }
719
720 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
721 {
722 }
723
724 static void svm_cache_regs(struct kvm_vcpu *vcpu)
725 {
726 struct vcpu_svm *svm = to_svm(vcpu);
727
728 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
729 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
730 vcpu->arch.rip = svm->vmcb->save.rip;
731 }
732
733 static void svm_decache_regs(struct kvm_vcpu *vcpu)
734 {
735 struct vcpu_svm *svm = to_svm(vcpu);
736 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
737 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
738 svm->vmcb->save.rip = vcpu->arch.rip;
739 }
740
741 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
742 {
743 return to_svm(vcpu)->vmcb->save.rflags;
744 }
745
746 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
747 {
748 to_svm(vcpu)->vmcb->save.rflags = rflags;
749 }
750
751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
752 {
753 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
754
755 switch (seg) {
756 case VCPU_SREG_CS: return &save->cs;
757 case VCPU_SREG_DS: return &save->ds;
758 case VCPU_SREG_ES: return &save->es;
759 case VCPU_SREG_FS: return &save->fs;
760 case VCPU_SREG_GS: return &save->gs;
761 case VCPU_SREG_SS: return &save->ss;
762 case VCPU_SREG_TR: return &save->tr;
763 case VCPU_SREG_LDTR: return &save->ldtr;
764 }
765 BUG();
766 return NULL;
767 }
768
769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
770 {
771 struct vmcb_seg *s = svm_seg(vcpu, seg);
772
773 return s->base;
774 }
775
776 static void svm_get_segment(struct kvm_vcpu *vcpu,
777 struct kvm_segment *var, int seg)
778 {
779 struct vmcb_seg *s = svm_seg(vcpu, seg);
780
781 var->base = s->base;
782 var->limit = s->limit;
783 var->selector = s->selector;
784 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
785 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
786 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
787 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
788 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
789 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
790 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
791 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
792 var->unusable = !var->present;
793 }
794
795 static int svm_get_cpl(struct kvm_vcpu *vcpu)
796 {
797 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
798
799 return save->cpl;
800 }
801
802 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
803 {
804 struct vcpu_svm *svm = to_svm(vcpu);
805
806 dt->limit = svm->vmcb->save.idtr.limit;
807 dt->base = svm->vmcb->save.idtr.base;
808 }
809
810 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
811 {
812 struct vcpu_svm *svm = to_svm(vcpu);
813
814 svm->vmcb->save.idtr.limit = dt->limit;
815 svm->vmcb->save.idtr.base = dt->base ;
816 }
817
818 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
819 {
820 struct vcpu_svm *svm = to_svm(vcpu);
821
822 dt->limit = svm->vmcb->save.gdtr.limit;
823 dt->base = svm->vmcb->save.gdtr.base;
824 }
825
826 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
827 {
828 struct vcpu_svm *svm = to_svm(vcpu);
829
830 svm->vmcb->save.gdtr.limit = dt->limit;
831 svm->vmcb->save.gdtr.base = dt->base ;
832 }
833
834 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
835 {
836 }
837
838 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
839 {
840 struct vcpu_svm *svm = to_svm(vcpu);
841
842 #ifdef CONFIG_X86_64
843 if (vcpu->arch.shadow_efer & EFER_LME) {
844 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
845 vcpu->arch.shadow_efer |= EFER_LMA;
846 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
847 }
848
849 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
850 vcpu->arch.shadow_efer &= ~EFER_LMA;
851 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
852 }
853 }
854 #endif
855 if (npt_enabled)
856 goto set;
857
858 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
859 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
860 vcpu->fpu_active = 1;
861 }
862
863 vcpu->arch.cr0 = cr0;
864 cr0 |= X86_CR0_PG | X86_CR0_WP;
865 if (!vcpu->fpu_active) {
866 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
867 cr0 |= X86_CR0_TS;
868 }
869 set:
870 /*
871 * re-enable caching here because the QEMU bios
872 * does not do it - this results in some delay at
873 * reboot
874 */
875 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
876 svm->vmcb->save.cr0 = cr0;
877 }
878
879 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
880 {
881 vcpu->arch.cr4 = cr4;
882 if (!npt_enabled)
883 cr4 |= X86_CR4_PAE;
884 to_svm(vcpu)->vmcb->save.cr4 = cr4;
885 }
886
887 static void svm_set_segment(struct kvm_vcpu *vcpu,
888 struct kvm_segment *var, int seg)
889 {
890 struct vcpu_svm *svm = to_svm(vcpu);
891 struct vmcb_seg *s = svm_seg(vcpu, seg);
892
893 s->base = var->base;
894 s->limit = var->limit;
895 s->selector = var->selector;
896 if (var->unusable)
897 s->attrib = 0;
898 else {
899 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
900 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
901 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
902 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
903 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
904 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
905 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
906 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
907 }
908 if (seg == VCPU_SREG_CS)
909 svm->vmcb->save.cpl
910 = (svm->vmcb->save.cs.attrib
911 >> SVM_SELECTOR_DPL_SHIFT) & 3;
912
913 }
914
915 /* FIXME:
916
917 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
918 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
919
920 */
921
922 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
923 {
924 return -EOPNOTSUPP;
925 }
926
927 static int svm_get_irq(struct kvm_vcpu *vcpu)
928 {
929 struct vcpu_svm *svm = to_svm(vcpu);
930 u32 exit_int_info = svm->vmcb->control.exit_int_info;
931
932 if (is_external_interrupt(exit_int_info))
933 return exit_int_info & SVM_EVTINJ_VEC_MASK;
934 return -1;
935 }
936
937 static void load_host_msrs(struct kvm_vcpu *vcpu)
938 {
939 #ifdef CONFIG_X86_64
940 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
941 #endif
942 }
943
944 static void save_host_msrs(struct kvm_vcpu *vcpu)
945 {
946 #ifdef CONFIG_X86_64
947 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
948 #endif
949 }
950
951 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
952 {
953 if (svm_data->next_asid > svm_data->max_asid) {
954 ++svm_data->asid_generation;
955 svm_data->next_asid = 1;
956 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
957 }
958
959 svm->vcpu.cpu = svm_data->cpu;
960 svm->asid_generation = svm_data->asid_generation;
961 svm->vmcb->control.asid = svm_data->next_asid++;
962 }
963
964 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
965 {
966 return to_svm(vcpu)->db_regs[dr];
967 }
968
969 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
970 int *exception)
971 {
972 struct vcpu_svm *svm = to_svm(vcpu);
973
974 *exception = 0;
975
976 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
977 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
978 svm->vmcb->save.dr6 |= DR6_BD_MASK;
979 *exception = DB_VECTOR;
980 return;
981 }
982
983 switch (dr) {
984 case 0 ... 3:
985 svm->db_regs[dr] = value;
986 return;
987 case 4 ... 5:
988 if (vcpu->arch.cr4 & X86_CR4_DE) {
989 *exception = UD_VECTOR;
990 return;
991 }
992 case 7: {
993 if (value & ~((1ULL << 32) - 1)) {
994 *exception = GP_VECTOR;
995 return;
996 }
997 svm->vmcb->save.dr7 = value;
998 return;
999 }
1000 default:
1001 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1002 __func__, dr);
1003 *exception = UD_VECTOR;
1004 return;
1005 }
1006 }
1007
1008 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1009 {
1010 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1011 struct kvm *kvm = svm->vcpu.kvm;
1012 u64 fault_address;
1013 u32 error_code;
1014
1015 if (!irqchip_in_kernel(kvm) &&
1016 is_external_interrupt(exit_int_info))
1017 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1018
1019 fault_address = svm->vmcb->control.exit_info_2;
1020 error_code = svm->vmcb->control.exit_info_1;
1021 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1022 }
1023
1024 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1025 {
1026 int er;
1027
1028 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1029 if (er != EMULATE_DONE)
1030 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1031 return 1;
1032 }
1033
1034 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1037 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1038 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1039 svm->vcpu.fpu_active = 1;
1040
1041 return 1;
1042 }
1043
1044 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046 /*
1047 * VMCB is undefined after a SHUTDOWN intercept
1048 * so reinitialize it.
1049 */
1050 clear_page(svm->vmcb);
1051 init_vmcb(svm);
1052
1053 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1054 return 0;
1055 }
1056
1057 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1060 int size, down, in, string, rep;
1061 unsigned port;
1062
1063 ++svm->vcpu.stat.io_exits;
1064
1065 svm->next_rip = svm->vmcb->control.exit_info_2;
1066
1067 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1068
1069 if (string) {
1070 if (emulate_instruction(&svm->vcpu,
1071 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1072 return 0;
1073 return 1;
1074 }
1075
1076 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1077 port = io_info >> 16;
1078 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1079 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1080 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1081
1082 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1083 }
1084
1085 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1086 {
1087 return 1;
1088 }
1089
1090 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1091 {
1092 svm->next_rip = svm->vmcb->save.rip + 1;
1093 skip_emulated_instruction(&svm->vcpu);
1094 return kvm_emulate_halt(&svm->vcpu);
1095 }
1096
1097 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1098 {
1099 svm->next_rip = svm->vmcb->save.rip + 3;
1100 skip_emulated_instruction(&svm->vcpu);
1101 kvm_emulate_hypercall(&svm->vcpu);
1102 return 1;
1103 }
1104
1105 static int invalid_op_interception(struct vcpu_svm *svm,
1106 struct kvm_run *kvm_run)
1107 {
1108 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1109 return 1;
1110 }
1111
1112 static int task_switch_interception(struct vcpu_svm *svm,
1113 struct kvm_run *kvm_run)
1114 {
1115 pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __func__);
1116 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1117 return 0;
1118 }
1119
1120 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1121 {
1122 svm->next_rip = svm->vmcb->save.rip + 2;
1123 kvm_emulate_cpuid(&svm->vcpu);
1124 return 1;
1125 }
1126
1127 static int emulate_on_interception(struct vcpu_svm *svm,
1128 struct kvm_run *kvm_run)
1129 {
1130 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1131 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1132 return 1;
1133 }
1134
1135 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1136 {
1137 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1138 if (irqchip_in_kernel(svm->vcpu.kvm))
1139 return 1;
1140 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1141 return 0;
1142 }
1143
1144 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1145 {
1146 struct vcpu_svm *svm = to_svm(vcpu);
1147
1148 switch (ecx) {
1149 case MSR_IA32_TIME_STAMP_COUNTER: {
1150 u64 tsc;
1151
1152 rdtscll(tsc);
1153 *data = svm->vmcb->control.tsc_offset + tsc;
1154 break;
1155 }
1156 case MSR_K6_STAR:
1157 *data = svm->vmcb->save.star;
1158 break;
1159 #ifdef CONFIG_X86_64
1160 case MSR_LSTAR:
1161 *data = svm->vmcb->save.lstar;
1162 break;
1163 case MSR_CSTAR:
1164 *data = svm->vmcb->save.cstar;
1165 break;
1166 case MSR_KERNEL_GS_BASE:
1167 *data = svm->vmcb->save.kernel_gs_base;
1168 break;
1169 case MSR_SYSCALL_MASK:
1170 *data = svm->vmcb->save.sfmask;
1171 break;
1172 #endif
1173 case MSR_IA32_SYSENTER_CS:
1174 *data = svm->vmcb->save.sysenter_cs;
1175 break;
1176 case MSR_IA32_SYSENTER_EIP:
1177 *data = svm->vmcb->save.sysenter_eip;
1178 break;
1179 case MSR_IA32_SYSENTER_ESP:
1180 *data = svm->vmcb->save.sysenter_esp;
1181 break;
1182 /* Nobody will change the following 5 values in the VMCB so
1183 we can safely return them on rdmsr. They will always be 0
1184 until LBRV is implemented. */
1185 case MSR_IA32_DEBUGCTLMSR:
1186 *data = svm->vmcb->save.dbgctl;
1187 break;
1188 case MSR_IA32_LASTBRANCHFROMIP:
1189 *data = svm->vmcb->save.br_from;
1190 break;
1191 case MSR_IA32_LASTBRANCHTOIP:
1192 *data = svm->vmcb->save.br_to;
1193 break;
1194 case MSR_IA32_LASTINTFROMIP:
1195 *data = svm->vmcb->save.last_excp_from;
1196 break;
1197 case MSR_IA32_LASTINTTOIP:
1198 *data = svm->vmcb->save.last_excp_to;
1199 break;
1200 default:
1201 return kvm_get_msr_common(vcpu, ecx, data);
1202 }
1203 return 0;
1204 }
1205
1206 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1207 {
1208 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1209 u64 data;
1210
1211 if (svm_get_msr(&svm->vcpu, ecx, &data))
1212 kvm_inject_gp(&svm->vcpu, 0);
1213 else {
1214 svm->vmcb->save.rax = data & 0xffffffff;
1215 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1216 svm->next_rip = svm->vmcb->save.rip + 2;
1217 skip_emulated_instruction(&svm->vcpu);
1218 }
1219 return 1;
1220 }
1221
1222 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1223 {
1224 struct vcpu_svm *svm = to_svm(vcpu);
1225
1226 switch (ecx) {
1227 case MSR_IA32_TIME_STAMP_COUNTER: {
1228 u64 tsc;
1229
1230 rdtscll(tsc);
1231 svm->vmcb->control.tsc_offset = data - tsc;
1232 break;
1233 }
1234 case MSR_K6_STAR:
1235 svm->vmcb->save.star = data;
1236 break;
1237 #ifdef CONFIG_X86_64
1238 case MSR_LSTAR:
1239 svm->vmcb->save.lstar = data;
1240 break;
1241 case MSR_CSTAR:
1242 svm->vmcb->save.cstar = data;
1243 break;
1244 case MSR_KERNEL_GS_BASE:
1245 svm->vmcb->save.kernel_gs_base = data;
1246 break;
1247 case MSR_SYSCALL_MASK:
1248 svm->vmcb->save.sfmask = data;
1249 break;
1250 #endif
1251 case MSR_IA32_SYSENTER_CS:
1252 svm->vmcb->save.sysenter_cs = data;
1253 break;
1254 case MSR_IA32_SYSENTER_EIP:
1255 svm->vmcb->save.sysenter_eip = data;
1256 break;
1257 case MSR_IA32_SYSENTER_ESP:
1258 svm->vmcb->save.sysenter_esp = data;
1259 break;
1260 case MSR_IA32_DEBUGCTLMSR:
1261 if (!svm_has(SVM_FEATURE_LBRV)) {
1262 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1263 __func__, data);
1264 break;
1265 }
1266 if (data & DEBUGCTL_RESERVED_BITS)
1267 return 1;
1268
1269 svm->vmcb->save.dbgctl = data;
1270 if (data & (1ULL<<0))
1271 svm_enable_lbrv(svm);
1272 else
1273 svm_disable_lbrv(svm);
1274 break;
1275 case MSR_K7_EVNTSEL0:
1276 case MSR_K7_EVNTSEL1:
1277 case MSR_K7_EVNTSEL2:
1278 case MSR_K7_EVNTSEL3:
1279 /*
1280 * only support writing 0 to the performance counters for now
1281 * to make Windows happy. Should be replaced by a real
1282 * performance counter emulation later.
1283 */
1284 if (data != 0)
1285 goto unhandled;
1286 break;
1287 default:
1288 unhandled:
1289 return kvm_set_msr_common(vcpu, ecx, data);
1290 }
1291 return 0;
1292 }
1293
1294 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1295 {
1296 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1297 u64 data = (svm->vmcb->save.rax & -1u)
1298 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1299 svm->next_rip = svm->vmcb->save.rip + 2;
1300 if (svm_set_msr(&svm->vcpu, ecx, data))
1301 kvm_inject_gp(&svm->vcpu, 0);
1302 else
1303 skip_emulated_instruction(&svm->vcpu);
1304 return 1;
1305 }
1306
1307 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1308 {
1309 if (svm->vmcb->control.exit_info_1)
1310 return wrmsr_interception(svm, kvm_run);
1311 else
1312 return rdmsr_interception(svm, kvm_run);
1313 }
1314
1315 static int interrupt_window_interception(struct vcpu_svm *svm,
1316 struct kvm_run *kvm_run)
1317 {
1318 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1319 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1320 /*
1321 * If the user space waits to inject interrupts, exit as soon as
1322 * possible
1323 */
1324 if (kvm_run->request_interrupt_window &&
1325 !svm->vcpu.arch.irq_summary) {
1326 ++svm->vcpu.stat.irq_window_exits;
1327 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1328 return 0;
1329 }
1330
1331 return 1;
1332 }
1333
1334 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1335 struct kvm_run *kvm_run) = {
1336 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1337 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1338 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1339 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1340 /* for now: */
1341 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1342 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1343 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1344 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1345 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1346 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1347 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1348 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1349 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1350 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1351 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1352 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1353 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1354 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1355 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1356 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1357 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1358 [SVM_EXIT_INTR] = nop_on_interception,
1359 [SVM_EXIT_NMI] = nop_on_interception,
1360 [SVM_EXIT_SMI] = nop_on_interception,
1361 [SVM_EXIT_INIT] = nop_on_interception,
1362 [SVM_EXIT_VINTR] = interrupt_window_interception,
1363 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1364 [SVM_EXIT_CPUID] = cpuid_interception,
1365 [SVM_EXIT_INVD] = emulate_on_interception,
1366 [SVM_EXIT_HLT] = halt_interception,
1367 [SVM_EXIT_INVLPG] = emulate_on_interception,
1368 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1369 [SVM_EXIT_IOIO] = io_interception,
1370 [SVM_EXIT_MSR] = msr_interception,
1371 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1372 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1373 [SVM_EXIT_VMRUN] = invalid_op_interception,
1374 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1375 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1376 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1377 [SVM_EXIT_STGI] = invalid_op_interception,
1378 [SVM_EXIT_CLGI] = invalid_op_interception,
1379 [SVM_EXIT_SKINIT] = invalid_op_interception,
1380 [SVM_EXIT_WBINVD] = emulate_on_interception,
1381 [SVM_EXIT_MONITOR] = invalid_op_interception,
1382 [SVM_EXIT_MWAIT] = invalid_op_interception,
1383 [SVM_EXIT_NPF] = pf_interception,
1384 };
1385
1386 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1387 {
1388 struct vcpu_svm *svm = to_svm(vcpu);
1389 u32 exit_code = svm->vmcb->control.exit_code;
1390
1391 if (npt_enabled) {
1392 int mmu_reload = 0;
1393 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1394 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1395 mmu_reload = 1;
1396 }
1397 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1398 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1399 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1400 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1401 kvm_inject_gp(vcpu, 0);
1402 return 1;
1403 }
1404 }
1405 if (mmu_reload) {
1406 kvm_mmu_reset_context(vcpu);
1407 kvm_mmu_load(vcpu);
1408 }
1409 }
1410
1411 kvm_reput_irq(svm);
1412
1413 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1414 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1415 kvm_run->fail_entry.hardware_entry_failure_reason
1416 = svm->vmcb->control.exit_code;
1417 return 0;
1418 }
1419
1420 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1421 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1422 exit_code != SVM_EXIT_NPF)
1423 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1424 "exit_code 0x%x\n",
1425 __func__, svm->vmcb->control.exit_int_info,
1426 exit_code);
1427
1428 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1429 || !svm_exit_handlers[exit_code]) {
1430 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1431 kvm_run->hw.hardware_exit_reason = exit_code;
1432 return 0;
1433 }
1434
1435 return svm_exit_handlers[exit_code](svm, kvm_run);
1436 }
1437
1438 static void reload_tss(struct kvm_vcpu *vcpu)
1439 {
1440 int cpu = raw_smp_processor_id();
1441
1442 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1443 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1444 load_TR_desc();
1445 }
1446
1447 static void pre_svm_run(struct vcpu_svm *svm)
1448 {
1449 int cpu = raw_smp_processor_id();
1450
1451 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1452
1453 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1454 if (svm->vcpu.cpu != cpu ||
1455 svm->asid_generation != svm_data->asid_generation)
1456 new_asid(svm, svm_data);
1457 }
1458
1459
1460 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1461 {
1462 struct vmcb_control_area *control;
1463
1464 control = &svm->vmcb->control;
1465 control->int_vector = irq;
1466 control->int_ctl &= ~V_INTR_PRIO_MASK;
1467 control->int_ctl |= V_IRQ_MASK |
1468 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1469 }
1470
1471 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1472 {
1473 struct vcpu_svm *svm = to_svm(vcpu);
1474
1475 svm_inject_irq(svm, irq);
1476 }
1477
1478 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1479 {
1480 struct vcpu_svm *svm = to_svm(vcpu);
1481 struct vmcb *vmcb = svm->vmcb;
1482 int intr_vector = -1;
1483
1484 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1485 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1486 intr_vector = vmcb->control.exit_int_info &
1487 SVM_EVTINJ_VEC_MASK;
1488 vmcb->control.exit_int_info = 0;
1489 svm_inject_irq(svm, intr_vector);
1490 return;
1491 }
1492
1493 if (vmcb->control.int_ctl & V_IRQ_MASK)
1494 return;
1495
1496 if (!kvm_cpu_has_interrupt(vcpu))
1497 return;
1498
1499 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1500 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1501 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1502 /* unable to deliver irq, set pending irq */
1503 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1504 svm_inject_irq(svm, 0x0);
1505 return;
1506 }
1507 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1508 intr_vector = kvm_cpu_get_interrupt(vcpu);
1509 svm_inject_irq(svm, intr_vector);
1510 kvm_timer_intr_post(vcpu, intr_vector);
1511 }
1512
1513 static void kvm_reput_irq(struct vcpu_svm *svm)
1514 {
1515 struct vmcb_control_area *control = &svm->vmcb->control;
1516
1517 if ((control->int_ctl & V_IRQ_MASK)
1518 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1519 control->int_ctl &= ~V_IRQ_MASK;
1520 push_irq(&svm->vcpu, control->int_vector);
1521 }
1522
1523 svm->vcpu.arch.interrupt_window_open =
1524 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1525 }
1526
1527 static void svm_do_inject_vector(struct vcpu_svm *svm)
1528 {
1529 struct kvm_vcpu *vcpu = &svm->vcpu;
1530 int word_index = __ffs(vcpu->arch.irq_summary);
1531 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1532 int irq = word_index * BITS_PER_LONG + bit_index;
1533
1534 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1535 if (!vcpu->arch.irq_pending[word_index])
1536 clear_bit(word_index, &vcpu->arch.irq_summary);
1537 svm_inject_irq(svm, irq);
1538 }
1539
1540 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1541 struct kvm_run *kvm_run)
1542 {
1543 struct vcpu_svm *svm = to_svm(vcpu);
1544 struct vmcb_control_area *control = &svm->vmcb->control;
1545
1546 svm->vcpu.arch.interrupt_window_open =
1547 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1548 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1549
1550 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1551 /*
1552 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1553 */
1554 svm_do_inject_vector(svm);
1555
1556 /*
1557 * Interrupts blocked. Wait for unblock.
1558 */
1559 if (!svm->vcpu.arch.interrupt_window_open &&
1560 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1561 control->intercept |= 1ULL << INTERCEPT_VINTR;
1562 else
1563 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1564 }
1565
1566 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1567 {
1568 return 0;
1569 }
1570
1571 static void save_db_regs(unsigned long *db_regs)
1572 {
1573 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1574 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1575 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1576 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1577 }
1578
1579 static void load_db_regs(unsigned long *db_regs)
1580 {
1581 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1582 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1583 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1584 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1585 }
1586
1587 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1588 {
1589 force_new_asid(vcpu);
1590 }
1591
1592 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1593 {
1594 }
1595
1596 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1597 {
1598 struct vcpu_svm *svm = to_svm(vcpu);
1599 u16 fs_selector;
1600 u16 gs_selector;
1601 u16 ldt_selector;
1602
1603 pre_svm_run(svm);
1604
1605 save_host_msrs(vcpu);
1606 fs_selector = read_fs();
1607 gs_selector = read_gs();
1608 ldt_selector = read_ldt();
1609 svm->host_cr2 = kvm_read_cr2();
1610 svm->host_dr6 = read_dr6();
1611 svm->host_dr7 = read_dr7();
1612 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1613 /* required for live migration with NPT */
1614 if (npt_enabled)
1615 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1616
1617 if (svm->vmcb->save.dr7 & 0xff) {
1618 write_dr7(0);
1619 save_db_regs(svm->host_db_regs);
1620 load_db_regs(svm->db_regs);
1621 }
1622
1623 clgi();
1624
1625 local_irq_enable();
1626
1627 asm volatile (
1628 #ifdef CONFIG_X86_64
1629 "push %%rbp; \n\t"
1630 #else
1631 "push %%ebp; \n\t"
1632 #endif
1633
1634 #ifdef CONFIG_X86_64
1635 "mov %c[rbx](%[svm]), %%rbx \n\t"
1636 "mov %c[rcx](%[svm]), %%rcx \n\t"
1637 "mov %c[rdx](%[svm]), %%rdx \n\t"
1638 "mov %c[rsi](%[svm]), %%rsi \n\t"
1639 "mov %c[rdi](%[svm]), %%rdi \n\t"
1640 "mov %c[rbp](%[svm]), %%rbp \n\t"
1641 "mov %c[r8](%[svm]), %%r8 \n\t"
1642 "mov %c[r9](%[svm]), %%r9 \n\t"
1643 "mov %c[r10](%[svm]), %%r10 \n\t"
1644 "mov %c[r11](%[svm]), %%r11 \n\t"
1645 "mov %c[r12](%[svm]), %%r12 \n\t"
1646 "mov %c[r13](%[svm]), %%r13 \n\t"
1647 "mov %c[r14](%[svm]), %%r14 \n\t"
1648 "mov %c[r15](%[svm]), %%r15 \n\t"
1649 #else
1650 "mov %c[rbx](%[svm]), %%ebx \n\t"
1651 "mov %c[rcx](%[svm]), %%ecx \n\t"
1652 "mov %c[rdx](%[svm]), %%edx \n\t"
1653 "mov %c[rsi](%[svm]), %%esi \n\t"
1654 "mov %c[rdi](%[svm]), %%edi \n\t"
1655 "mov %c[rbp](%[svm]), %%ebp \n\t"
1656 #endif
1657
1658 #ifdef CONFIG_X86_64
1659 /* Enter guest mode */
1660 "push %%rax \n\t"
1661 "mov %c[vmcb](%[svm]), %%rax \n\t"
1662 SVM_VMLOAD "\n\t"
1663 SVM_VMRUN "\n\t"
1664 SVM_VMSAVE "\n\t"
1665 "pop %%rax \n\t"
1666 #else
1667 /* Enter guest mode */
1668 "push %%eax \n\t"
1669 "mov %c[vmcb](%[svm]), %%eax \n\t"
1670 SVM_VMLOAD "\n\t"
1671 SVM_VMRUN "\n\t"
1672 SVM_VMSAVE "\n\t"
1673 "pop %%eax \n\t"
1674 #endif
1675
1676 /* Save guest registers, load host registers */
1677 #ifdef CONFIG_X86_64
1678 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1679 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1680 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1681 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1682 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1683 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1684 "mov %%r8, %c[r8](%[svm]) \n\t"
1685 "mov %%r9, %c[r9](%[svm]) \n\t"
1686 "mov %%r10, %c[r10](%[svm]) \n\t"
1687 "mov %%r11, %c[r11](%[svm]) \n\t"
1688 "mov %%r12, %c[r12](%[svm]) \n\t"
1689 "mov %%r13, %c[r13](%[svm]) \n\t"
1690 "mov %%r14, %c[r14](%[svm]) \n\t"
1691 "mov %%r15, %c[r15](%[svm]) \n\t"
1692
1693 "pop %%rbp; \n\t"
1694 #else
1695 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1696 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1697 "mov %%edx, %c[rdx](%[svm]) \n\t"
1698 "mov %%esi, %c[rsi](%[svm]) \n\t"
1699 "mov %%edi, %c[rdi](%[svm]) \n\t"
1700 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1701
1702 "pop %%ebp; \n\t"
1703 #endif
1704 :
1705 : [svm]"a"(svm),
1706 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1707 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1708 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1709 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1710 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1711 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1712 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1713 #ifdef CONFIG_X86_64
1714 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1715 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1716 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1717 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1718 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1719 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1720 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1721 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1722 #endif
1723 : "cc", "memory"
1724 #ifdef CONFIG_X86_64
1725 , "rbx", "rcx", "rdx", "rsi", "rdi"
1726 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1727 #else
1728 , "ebx", "ecx", "edx" , "esi", "edi"
1729 #endif
1730 );
1731
1732 if ((svm->vmcb->save.dr7 & 0xff))
1733 load_db_regs(svm->host_db_regs);
1734
1735 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1736
1737 write_dr6(svm->host_dr6);
1738 write_dr7(svm->host_dr7);
1739 kvm_write_cr2(svm->host_cr2);
1740
1741 load_fs(fs_selector);
1742 load_gs(gs_selector);
1743 load_ldt(ldt_selector);
1744 load_host_msrs(vcpu);
1745
1746 reload_tss(vcpu);
1747
1748 local_irq_disable();
1749
1750 stgi();
1751
1752 svm->next_rip = 0;
1753 }
1754
1755 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1756 {
1757 struct vcpu_svm *svm = to_svm(vcpu);
1758
1759 if (npt_enabled) {
1760 svm->vmcb->control.nested_cr3 = root;
1761 force_new_asid(vcpu);
1762 return;
1763 }
1764
1765 svm->vmcb->save.cr3 = root;
1766 force_new_asid(vcpu);
1767
1768 if (vcpu->fpu_active) {
1769 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1770 svm->vmcb->save.cr0 |= X86_CR0_TS;
1771 vcpu->fpu_active = 0;
1772 }
1773 }
1774
1775 static int is_disabled(void)
1776 {
1777 u64 vm_cr;
1778
1779 rdmsrl(MSR_VM_CR, vm_cr);
1780 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1781 return 1;
1782
1783 return 0;
1784 }
1785
1786 static void
1787 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1788 {
1789 /*
1790 * Patch in the VMMCALL instruction:
1791 */
1792 hypercall[0] = 0x0f;
1793 hypercall[1] = 0x01;
1794 hypercall[2] = 0xd9;
1795 }
1796
1797 static void svm_check_processor_compat(void *rtn)
1798 {
1799 *(int *)rtn = 0;
1800 }
1801
1802 static bool svm_cpu_has_accelerated_tpr(void)
1803 {
1804 return false;
1805 }
1806
1807 static struct kvm_x86_ops svm_x86_ops = {
1808 .cpu_has_kvm_support = has_svm,
1809 .disabled_by_bios = is_disabled,
1810 .hardware_setup = svm_hardware_setup,
1811 .hardware_unsetup = svm_hardware_unsetup,
1812 .check_processor_compatibility = svm_check_processor_compat,
1813 .hardware_enable = svm_hardware_enable,
1814 .hardware_disable = svm_hardware_disable,
1815 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1816
1817 .vcpu_create = svm_create_vcpu,
1818 .vcpu_free = svm_free_vcpu,
1819 .vcpu_reset = svm_vcpu_reset,
1820
1821 .prepare_guest_switch = svm_prepare_guest_switch,
1822 .vcpu_load = svm_vcpu_load,
1823 .vcpu_put = svm_vcpu_put,
1824 .vcpu_decache = svm_vcpu_decache,
1825
1826 .set_guest_debug = svm_guest_debug,
1827 .get_msr = svm_get_msr,
1828 .set_msr = svm_set_msr,
1829 .get_segment_base = svm_get_segment_base,
1830 .get_segment = svm_get_segment,
1831 .set_segment = svm_set_segment,
1832 .get_cpl = svm_get_cpl,
1833 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1834 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1835 .set_cr0 = svm_set_cr0,
1836 .set_cr3 = svm_set_cr3,
1837 .set_cr4 = svm_set_cr4,
1838 .set_efer = svm_set_efer,
1839 .get_idt = svm_get_idt,
1840 .set_idt = svm_set_idt,
1841 .get_gdt = svm_get_gdt,
1842 .set_gdt = svm_set_gdt,
1843 .get_dr = svm_get_dr,
1844 .set_dr = svm_set_dr,
1845 .cache_regs = svm_cache_regs,
1846 .decache_regs = svm_decache_regs,
1847 .get_rflags = svm_get_rflags,
1848 .set_rflags = svm_set_rflags,
1849
1850 .tlb_flush = svm_flush_tlb,
1851
1852 .run = svm_vcpu_run,
1853 .handle_exit = handle_exit,
1854 .skip_emulated_instruction = skip_emulated_instruction,
1855 .patch_hypercall = svm_patch_hypercall,
1856 .get_irq = svm_get_irq,
1857 .set_irq = svm_set_irq,
1858 .queue_exception = svm_queue_exception,
1859 .exception_injected = svm_exception_injected,
1860 .inject_pending_irq = svm_intr_assist,
1861 .inject_pending_vectors = do_interrupt_requests,
1862
1863 .set_tss_addr = svm_set_tss_addr,
1864 };
1865
1866 static int __init svm_init(void)
1867 {
1868 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1869 THIS_MODULE);
1870 }
1871
1872 static void __exit svm_exit(void)
1873 {
1874 kvm_exit();
1875 }
1876
1877 module_init(svm_init)
1878 module_exit(svm_exit)
Linux kernel - Deliverables
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