projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: SVM: indent svm_set_cr4 with tabs instead of spaces
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/vmalloc.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27
28 #include <asm/desc.h>
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 #define IOPM_ALLOC_ORDER 2
34 #define MSRPM_ALLOC_ORDER 1
35
36 #define DB_VECTOR 1
37 #define UD_VECTOR 6
38 #define GP_VECTOR 13
39
40 #define DR7_GD_MASK (1 << 13)
41 #define DR6_BD_MASK (1 << 13)
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_DEATURE_SVML (1 << 2)
49
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
52 /* enable NPT for AMD64 and X86 with PAE */
53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
54 static bool npt_enabled = true;
55 #else
56 static bool npt_enabled = false;
57 #endif
58 static int npt = 1;
59
60 module_param(npt, int, S_IRUGO);
61
62 static void kvm_reput_irq(struct vcpu_svm *svm);
63
64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
65 {
66 return container_of(vcpu, struct vcpu_svm, vcpu);
67 }
68
69 static unsigned long iopm_base;
70
71 struct kvm_ldttss_desc {
72 u16 limit0;
73 u16 base0;
74 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
75 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
76 u32 base3;
77 u32 zero1;
78 } __attribute__((packed));
79
80 struct svm_cpu_data {
81 int cpu;
82
83 u64 asid_generation;
84 u32 max_asid;
85 u32 next_asid;
86 struct kvm_ldttss_desc *tss_desc;
87
88 struct page *save_area;
89 };
90
91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
92 static uint32_t svm_features;
93
94 struct svm_init_data {
95 int cpu;
96 int r;
97 };
98
99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
100
101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
102 #define MSRS_RANGE_SIZE 2048
103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
104
105 #define MAX_INST_SIZE 15
106
107 static inline u32 svm_has(u32 feat)
108 {
109 return svm_features & feat;
110 }
111
112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
113 {
114 int word_index = __ffs(vcpu->arch.irq_summary);
115 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
116 int irq = word_index * BITS_PER_LONG + bit_index;
117
118 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
119 if (!vcpu->arch.irq_pending[word_index])
120 clear_bit(word_index, &vcpu->arch.irq_summary);
121 return irq;
122 }
123
124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
125 {
126 set_bit(irq, vcpu->arch.irq_pending);
127 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
128 }
129
130 static inline void clgi(void)
131 {
132 asm volatile (SVM_CLGI);
133 }
134
135 static inline void stgi(void)
136 {
137 asm volatile (SVM_STGI);
138 }
139
140 static inline void invlpga(unsigned long addr, u32 asid)
141 {
142 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
143 }
144
145 static inline unsigned long kvm_read_cr2(void)
146 {
147 unsigned long cr2;
148
149 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
150 return cr2;
151 }
152
153 static inline void kvm_write_cr2(unsigned long val)
154 {
155 asm volatile ("mov %0, %%cr2" :: "r" (val));
156 }
157
158 static inline unsigned long read_dr6(void)
159 {
160 unsigned long dr6;
161
162 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
163 return dr6;
164 }
165
166 static inline void write_dr6(unsigned long val)
167 {
168 asm volatile ("mov %0, %%dr6" :: "r" (val));
169 }
170
171 static inline unsigned long read_dr7(void)
172 {
173 unsigned long dr7;
174
175 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
176 return dr7;
177 }
178
179 static inline void write_dr7(unsigned long val)
180 {
181 asm volatile ("mov %0, %%dr7" :: "r" (val));
182 }
183
184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
185 {
186 to_svm(vcpu)->asid_generation--;
187 }
188
189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
190 {
191 force_new_asid(vcpu);
192 }
193
194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
195 {
196 if (!npt_enabled && !(efer & EFER_LMA))
197 efer &= ~EFER_LME;
198
199 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
200 vcpu->arch.shadow_efer = efer;
201 }
202
203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
204 bool has_error_code, u32 error_code)
205 {
206 struct vcpu_svm *svm = to_svm(vcpu);
207
208 svm->vmcb->control.event_inj = nr
209 | SVM_EVTINJ_VALID
210 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
211 | SVM_EVTINJ_TYPE_EXEPT;
212 svm->vmcb->control.event_inj_err = error_code;
213 }
214
215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
216 {
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
220 }
221
222 static int is_external_interrupt(u32 info)
223 {
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226 }
227
228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229 {
230 struct vcpu_svm *svm = to_svm(vcpu);
231
232 if (!svm->next_rip) {
233 printk(KERN_DEBUG "%s: NOP\n", __func__);
234 return;
235 }
236 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
237 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
238 __func__,
239 svm->vmcb->save.rip,
240 svm->next_rip);
241
242 vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
244
245 vcpu->arch.interrupt_window_open = 1;
246 }
247
248 static int has_svm(void)
249 {
250 uint32_t eax, ebx, ecx, edx;
251
252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
253 printk(KERN_INFO "has_svm: not amd\n");
254 return 0;
255 }
256
257 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
258 if (eax < SVM_CPUID_FUNC) {
259 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
260 return 0;
261 }
262
263 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
264 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
265 printk(KERN_DEBUG "has_svm: svm not available\n");
266 return 0;
267 }
268 return 1;
269 }
270
271 static void svm_hardware_disable(void *garbage)
272 {
273 struct svm_cpu_data *svm_data
274 = per_cpu(svm_data, raw_smp_processor_id());
275
276 if (svm_data) {
277 uint64_t efer;
278
279 wrmsrl(MSR_VM_HSAVE_PA, 0);
280 rdmsrl(MSR_EFER, efer);
281 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
283 __free_page(svm_data->save_area);
284 kfree(svm_data);
285 }
286 }
287
288 static void svm_hardware_enable(void *garbage)
289 {
290
291 struct svm_cpu_data *svm_data;
292 uint64_t efer;
293 struct desc_ptr gdt_descr;
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
296
297 if (!has_svm()) {
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
299 return;
300 }
301 svm_data = per_cpu(svm_data, me);
302
303 if (!svm_data) {
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
305 me);
306 return;
307 }
308
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312
313 asm volatile ("sgdt %0" : "=m"(gdt_descr));
314 gdt = (struct desc_struct *)gdt_descr.address;
315 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
316
317 rdmsrl(MSR_EFER, efer);
318 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
319
320 wrmsrl(MSR_VM_HSAVE_PA,
321 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
322 }
323
324 static int svm_cpu_init(int cpu)
325 {
326 struct svm_cpu_data *svm_data;
327 int r;
328
329 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
330 if (!svm_data)
331 return -ENOMEM;
332 svm_data->cpu = cpu;
333 svm_data->save_area = alloc_page(GFP_KERNEL);
334 r = -ENOMEM;
335 if (!svm_data->save_area)
336 goto err_1;
337
338 per_cpu(svm_data, cpu) = svm_data;
339
340 return 0;
341
342 err_1:
343 kfree(svm_data);
344 return r;
345
346 }
347
348 static void set_msr_interception(u32 *msrpm, unsigned msr,
349 int read, int write)
350 {
351 int i;
352
353 for (i = 0; i < NUM_MSR_MAPS; i++) {
354 if (msr >= msrpm_ranges[i] &&
355 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
356 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
357 msrpm_ranges[i]) * 2;
358
359 u32 *base = msrpm + (msr_offset / 32);
360 u32 msr_shift = msr_offset % 32;
361 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
362 *base = (*base & ~(0x3 << msr_shift)) |
363 (mask << msr_shift);
364 return;
365 }
366 }
367 BUG();
368 }
369
370 static void svm_vcpu_init_msrpm(u32 *msrpm)
371 {
372 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
373
374 #ifdef CONFIG_X86_64
375 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
376 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
377 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
378 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
379 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
380 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
381 #endif
382 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
383 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
386 }
387
388 static void svm_enable_lbrv(struct vcpu_svm *svm)
389 {
390 u32 *msrpm = svm->msrpm;
391
392 svm->vmcb->control.lbr_ctl = 1;
393 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
395 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
397 }
398
399 static void svm_disable_lbrv(struct vcpu_svm *svm)
400 {
401 u32 *msrpm = svm->msrpm;
402
403 svm->vmcb->control.lbr_ctl = 0;
404 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
405 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
406 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
407 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
408 }
409
410 static __init int svm_hardware_setup(void)
411 {
412 int cpu;
413 struct page *iopm_pages;
414 void *iopm_va;
415 int r;
416
417 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
418
419 if (!iopm_pages)
420 return -ENOMEM;
421
422 iopm_va = page_address(iopm_pages);
423 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
424 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
425 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
426
427 if (boot_cpu_has(X86_FEATURE_NX))
428 kvm_enable_efer_bits(EFER_NX);
429
430 for_each_online_cpu(cpu) {
431 r = svm_cpu_init(cpu);
432 if (r)
433 goto err;
434 }
435
436 svm_features = cpuid_edx(SVM_CPUID_FUNC);
437
438 if (!svm_has(SVM_FEATURE_NPT))
439 npt_enabled = false;
440
441 if (npt_enabled && !npt) {
442 printk(KERN_INFO "kvm: Nested Paging disabled\n");
443 npt_enabled = false;
444 }
445
446 if (npt_enabled) {
447 printk(KERN_INFO "kvm: Nested Paging enabled\n");
448 kvm_enable_tdp();
449 }
450
451 return 0;
452
453 err:
454 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
455 iopm_base = 0;
456 return r;
457 }
458
459 static __exit void svm_hardware_unsetup(void)
460 {
461 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
462 iopm_base = 0;
463 }
464
465 static void init_seg(struct vmcb_seg *seg)
466 {
467 seg->selector = 0;
468 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
469 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
470 seg->limit = 0xffff;
471 seg->base = 0;
472 }
473
474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
475 {
476 seg->selector = 0;
477 seg->attrib = SVM_SELECTOR_P_MASK | type;
478 seg->limit = 0xffff;
479 seg->base = 0;
480 }
481
482 static void init_vmcb(struct vcpu_svm *svm)
483 {
484 struct vmcb_control_area *control = &svm->vmcb->control;
485 struct vmcb_save_area *save = &svm->vmcb->save;
486
487 control->intercept_cr_read = INTERCEPT_CR0_MASK |
488 INTERCEPT_CR3_MASK |
489 INTERCEPT_CR4_MASK |
490 INTERCEPT_CR8_MASK;
491
492 control->intercept_cr_write = INTERCEPT_CR0_MASK |
493 INTERCEPT_CR3_MASK |
494 INTERCEPT_CR4_MASK |
495 INTERCEPT_CR8_MASK;
496
497 control->intercept_dr_read = INTERCEPT_DR0_MASK |
498 INTERCEPT_DR1_MASK |
499 INTERCEPT_DR2_MASK |
500 INTERCEPT_DR3_MASK;
501
502 control->intercept_dr_write = INTERCEPT_DR0_MASK |
503 INTERCEPT_DR1_MASK |
504 INTERCEPT_DR2_MASK |
505 INTERCEPT_DR3_MASK |
506 INTERCEPT_DR5_MASK |
507 INTERCEPT_DR7_MASK;
508
509 control->intercept_exceptions = (1 << PF_VECTOR) |
510 (1 << UD_VECTOR);
511
512
513 control->intercept = (1ULL << INTERCEPT_INTR) |
514 (1ULL << INTERCEPT_NMI) |
515 (1ULL << INTERCEPT_SMI) |
516 /*
517 * selective cr0 intercept bug?
518 * 0: 0f 22 d8 mov %eax,%cr3
519 * 3: 0f 20 c0 mov %cr0,%eax
520 * 6: 0d 00 00 00 80 or $0x80000000,%eax
521 * b: 0f 22 c0 mov %eax,%cr0
522 * set cr3 ->interception
523 * get cr0 ->interception
524 * set cr0 -> no interception
525 */
526 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
527 (1ULL << INTERCEPT_CPUID) |
528 (1ULL << INTERCEPT_INVD) |
529 (1ULL << INTERCEPT_HLT) |
530 (1ULL << INTERCEPT_INVLPGA) |
531 (1ULL << INTERCEPT_IOIO_PROT) |
532 (1ULL << INTERCEPT_MSR_PROT) |
533 (1ULL << INTERCEPT_TASK_SWITCH) |
534 (1ULL << INTERCEPT_SHUTDOWN) |
535 (1ULL << INTERCEPT_VMRUN) |
536 (1ULL << INTERCEPT_VMMCALL) |
537 (1ULL << INTERCEPT_VMLOAD) |
538 (1ULL << INTERCEPT_VMSAVE) |
539 (1ULL << INTERCEPT_STGI) |
540 (1ULL << INTERCEPT_CLGI) |
541 (1ULL << INTERCEPT_SKINIT) |
542 (1ULL << INTERCEPT_WBINVD) |
543 (1ULL << INTERCEPT_MONITOR) |
544 (1ULL << INTERCEPT_MWAIT);
545
546 control->iopm_base_pa = iopm_base;
547 control->msrpm_base_pa = __pa(svm->msrpm);
548 control->tsc_offset = 0;
549 control->int_ctl = V_INTR_MASKING_MASK;
550
551 init_seg(&save->es);
552 init_seg(&save->ss);
553 init_seg(&save->ds);
554 init_seg(&save->fs);
555 init_seg(&save->gs);
556
557 save->cs.selector = 0xf000;
558 /* Executable/Readable Code Segment */
559 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
560 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
561 save->cs.limit = 0xffff;
562 /*
563 * cs.base should really be 0xffff0000, but vmx can't handle that, so
564 * be consistent with it.
565 *
566 * Replace when we have real mode working for vmx.
567 */
568 save->cs.base = 0xf0000;
569
570 save->gdtr.limit = 0xffff;
571 save->idtr.limit = 0xffff;
572
573 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
574 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
575
576 save->efer = MSR_EFER_SVME_MASK;
577 save->dr6 = 0xffff0ff0;
578 save->dr7 = 0x400;
579 save->rflags = 2;
580 save->rip = 0x0000fff0;
581
582 /*
583 * cr0 val on cpu init should be 0x60000010, we enable cpu
584 * cache by default. the orderly way is to enable cache in bios.
585 */
586 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
587 save->cr4 = X86_CR4_PAE;
588 /* rdx = ?? */
589
590 if (npt_enabled) {
591 /* Setup VMCB for Nested Paging */
592 control->nested_ctl = 1;
593 control->intercept_exceptions &= ~(1 << PF_VECTOR);
594 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
595 INTERCEPT_CR3_MASK);
596 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
597 INTERCEPT_CR3_MASK);
598 save->g_pat = 0x0007040600070406ULL;
599 /* enable caching because the QEMU Bios doesn't enable it */
600 save->cr0 = X86_CR0_ET;
601 save->cr3 = 0;
602 save->cr4 = 0;
603 }
604
605 }
606
607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
608 {
609 struct vcpu_svm *svm = to_svm(vcpu);
610
611 init_vmcb(svm);
612
613 if (vcpu->vcpu_id != 0) {
614 svm->vmcb->save.rip = 0;
615 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
616 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
617 }
618
619 return 0;
620 }
621
622 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
623 {
624 struct vcpu_svm *svm;
625 struct page *page;
626 struct page *msrpm_pages;
627 int err;
628
629 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
630 if (!svm) {
631 err = -ENOMEM;
632 goto out;
633 }
634
635 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
636 if (err)
637 goto free_svm;
638
639 page = alloc_page(GFP_KERNEL);
640 if (!page) {
641 err = -ENOMEM;
642 goto uninit;
643 }
644
645 err = -ENOMEM;
646 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
647 if (!msrpm_pages)
648 goto uninit;
649 svm->msrpm = page_address(msrpm_pages);
650 svm_vcpu_init_msrpm(svm->msrpm);
651
652 svm->vmcb = page_address(page);
653 clear_page(svm->vmcb);
654 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
655 svm->asid_generation = 0;
656 memset(svm->db_regs, 0, sizeof(svm->db_regs));
657 init_vmcb(svm);
658
659 fx_init(&svm->vcpu);
660 svm->vcpu.fpu_active = 1;
661 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
662 if (svm->vcpu.vcpu_id == 0)
663 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
664
665 return &svm->vcpu;
666
667 uninit:
668 kvm_vcpu_uninit(&svm->vcpu);
669 free_svm:
670 kmem_cache_free(kvm_vcpu_cache, svm);
671 out:
672 return ERR_PTR(err);
673 }
674
675 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
676 {
677 struct vcpu_svm *svm = to_svm(vcpu);
678
679 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
680 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
681 kvm_vcpu_uninit(vcpu);
682 kmem_cache_free(kvm_vcpu_cache, svm);
683 }
684
685 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
686 {
687 struct vcpu_svm *svm = to_svm(vcpu);
688 int i;
689
690 if (unlikely(cpu != vcpu->cpu)) {
691 u64 tsc_this, delta;
692
693 /*
694 * Make sure that the guest sees a monotonically
695 * increasing TSC.
696 */
697 rdtscll(tsc_this);
698 delta = vcpu->arch.host_tsc - tsc_this;
699 svm->vmcb->control.tsc_offset += delta;
700 vcpu->cpu = cpu;
701 kvm_migrate_apic_timer(vcpu);
702 }
703
704 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
705 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
706 }
707
708 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
709 {
710 struct vcpu_svm *svm = to_svm(vcpu);
711 int i;
712
713 ++vcpu->stat.host_state_reload;
714 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
715 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
716
717 rdtscll(vcpu->arch.host_tsc);
718 }
719
720 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
721 {
722 }
723
724 static void svm_cache_regs(struct kvm_vcpu *vcpu)
725 {
726 struct vcpu_svm *svm = to_svm(vcpu);
727
728 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
729 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
730 vcpu->arch.rip = svm->vmcb->save.rip;
731 }
732
733 static void svm_decache_regs(struct kvm_vcpu *vcpu)
734 {
735 struct vcpu_svm *svm = to_svm(vcpu);
736 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
737 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
738 svm->vmcb->save.rip = vcpu->arch.rip;
739 }
740
741 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
742 {
743 return to_svm(vcpu)->vmcb->save.rflags;
744 }
745
746 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
747 {
748 to_svm(vcpu)->vmcb->save.rflags = rflags;
749 }
750
751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
752 {
753 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
754
755 switch (seg) {
756 case VCPU_SREG_CS: return &save->cs;
757 case VCPU_SREG_DS: return &save->ds;
758 case VCPU_SREG_ES: return &save->es;
759 case VCPU_SREG_FS: return &save->fs;
760 case VCPU_SREG_GS: return &save->gs;
761 case VCPU_SREG_SS: return &save->ss;
762 case VCPU_SREG_TR: return &save->tr;
763 case VCPU_SREG_LDTR: return &save->ldtr;
764 }
765 BUG();
766 return NULL;
767 }
768
769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
770 {
771 struct vmcb_seg *s = svm_seg(vcpu, seg);
772
773 return s->base;
774 }
775
776 static void svm_get_segment(struct kvm_vcpu *vcpu,
777 struct kvm_segment *var, int seg)
778 {
779 struct vmcb_seg *s = svm_seg(vcpu, seg);
780
781 var->base = s->base;
782 var->limit = s->limit;
783 var->selector = s->selector;
784 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
785 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
786 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
787 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
788 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
789 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
790 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
791 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
792 var->unusable = !var->present;
793 }
794
795 static int svm_get_cpl(struct kvm_vcpu *vcpu)
796 {
797 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
798
799 return save->cpl;
800 }
801
802 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
803 {
804 struct vcpu_svm *svm = to_svm(vcpu);
805
806 dt->limit = svm->vmcb->save.idtr.limit;
807 dt->base = svm->vmcb->save.idtr.base;
808 }
809
810 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
811 {
812 struct vcpu_svm *svm = to_svm(vcpu);
813
814 svm->vmcb->save.idtr.limit = dt->limit;
815 svm->vmcb->save.idtr.base = dt->base ;
816 }
817
818 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
819 {
820 struct vcpu_svm *svm = to_svm(vcpu);
821
822 dt->limit = svm->vmcb->save.gdtr.limit;
823 dt->base = svm->vmcb->save.gdtr.base;
824 }
825
826 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
827 {
828 struct vcpu_svm *svm = to_svm(vcpu);
829
830 svm->vmcb->save.gdtr.limit = dt->limit;
831 svm->vmcb->save.gdtr.base = dt->base ;
832 }
833
834 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
835 {
836 }
837
838 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
839 {
840 struct vcpu_svm *svm = to_svm(vcpu);
841
842 #ifdef CONFIG_X86_64
843 if (vcpu->arch.shadow_efer & EFER_LME) {
844 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
845 vcpu->arch.shadow_efer |= EFER_LMA;
846 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
847 }
848
849 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
850 vcpu->arch.shadow_efer &= ~EFER_LMA;
851 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
852 }
853 }
854 #endif
855 if (npt_enabled)
856 goto set;
857
858 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
859 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
860 vcpu->fpu_active = 1;
861 }
862
863 vcpu->arch.cr0 = cr0;
864 cr0 |= X86_CR0_PG | X86_CR0_WP;
865 if (!vcpu->fpu_active) {
866 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
867 cr0 |= X86_CR0_TS;
868 }
869 set:
870 /*
871 * re-enable caching here because the QEMU bios
872 * does not do it - this results in some delay at
873 * reboot
874 */
875 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
876 svm->vmcb->save.cr0 = cr0;
877 }
878
879 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
880 {
881 vcpu->arch.cr4 = cr4;
882 if (!npt_enabled)
883 cr4 |= X86_CR4_PAE;
884 to_svm(vcpu)->vmcb->save.cr4 = cr4;
885 }
886
887 static void svm_set_segment(struct kvm_vcpu *vcpu,
888 struct kvm_segment *var, int seg)
889 {
890 struct vcpu_svm *svm = to_svm(vcpu);
891 struct vmcb_seg *s = svm_seg(vcpu, seg);
892
893 s->base = var->base;
894 s->limit = var->limit;
895 s->selector = var->selector;
896 if (var->unusable)
897 s->attrib = 0;
898 else {
899 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
900 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
901 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
902 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
903 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
904 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
905 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
906 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
907 }
908 if (seg == VCPU_SREG_CS)
909 svm->vmcb->save.cpl
910 = (svm->vmcb->save.cs.attrib
911 >> SVM_SELECTOR_DPL_SHIFT) & 3;
912
913 }
914
915 /* FIXME:
916
917 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
918 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
919
920 */
921
922 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
923 {
924 return -EOPNOTSUPP;
925 }
926
927 static int svm_get_irq(struct kvm_vcpu *vcpu)
928 {
929 struct vcpu_svm *svm = to_svm(vcpu);
930 u32 exit_int_info = svm->vmcb->control.exit_int_info;
931
932 if (is_external_interrupt(exit_int_info))
933 return exit_int_info & SVM_EVTINJ_VEC_MASK;
934 return -1;
935 }
936
937 static void load_host_msrs(struct kvm_vcpu *vcpu)
938 {
939 #ifdef CONFIG_X86_64
940 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
941 #endif
942 }
943
944 static void save_host_msrs(struct kvm_vcpu *vcpu)
945 {
946 #ifdef CONFIG_X86_64
947 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
948 #endif
949 }
950
951 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
952 {
953 if (svm_data->next_asid > svm_data->max_asid) {
954 ++svm_data->asid_generation;
955 svm_data->next_asid = 1;
956 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
957 }
958
959 svm->vcpu.cpu = svm_data->cpu;
960 svm->asid_generation = svm_data->asid_generation;
961 svm->vmcb->control.asid = svm_data->next_asid++;
962 }
963
964 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
965 {
966 return to_svm(vcpu)->db_regs[dr];
967 }
968
969 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
970 int *exception)
971 {
972 struct vcpu_svm *svm = to_svm(vcpu);
973
974 *exception = 0;
975
976 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
977 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
978 svm->vmcb->save.dr6 |= DR6_BD_MASK;
979 *exception = DB_VECTOR;
980 return;
981 }
982
983 switch (dr) {
984 case 0 ... 3:
985 svm->db_regs[dr] = value;
986 return;
987 case 4 ... 5:
988 if (vcpu->arch.cr4 & X86_CR4_DE) {
989 *exception = UD_VECTOR;
990 return;
991 }
992 case 7: {
993 if (value & ~((1ULL << 32) - 1)) {
994 *exception = GP_VECTOR;
995 return;
996 }
997 svm->vmcb->save.dr7 = value;
998 return;
999 }
1000 default:
1001 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1002 __func__, dr);
1003 *exception = UD_VECTOR;
1004 return;
1005 }
1006 }
1007
1008 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1009 {
1010 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1011 struct kvm *kvm = svm->vcpu.kvm;
1012 u64 fault_address;
1013 u32 error_code;
1014
1015 if (!irqchip_in_kernel(kvm) &&
1016 is_external_interrupt(exit_int_info))
1017 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1018
1019 fault_address = svm->vmcb->control.exit_info_2;
1020 error_code = svm->vmcb->control.exit_info_1;
1021 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1022 }
1023
1024 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1025 {
1026 int er;
1027
1028 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1029 if (er != EMULATE_DONE)
1030 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1031 return 1;
1032 }
1033
1034 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1037 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1038 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1039 svm->vcpu.fpu_active = 1;
1040
1041 return 1;
1042 }
1043
1044 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046 /*
1047 * VMCB is undefined after a SHUTDOWN intercept
1048 * so reinitialize it.
1049 */
1050 clear_page(svm->vmcb);
1051 init_vmcb(svm);
1052
1053 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1054 return 0;
1055 }
1056
1057 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1060 int size, down, in, string, rep;
1061 unsigned port;
1062
1063 ++svm->vcpu.stat.io_exits;
1064
1065 svm->next_rip = svm->vmcb->control.exit_info_2;
1066
1067 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1068
1069 if (string) {
1070 if (emulate_instruction(&svm->vcpu,
1071 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1072 return 0;
1073 return 1;
1074 }
1075
1076 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1077 port = io_info >> 16;
1078 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1079 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1080 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1081
1082 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1083 }
1084
1085 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1086 {
1087 return 1;
1088 }
1089
1090 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1091 {
1092 svm->next_rip = svm->vmcb->save.rip + 1;
1093 skip_emulated_instruction(&svm->vcpu);
1094 return kvm_emulate_halt(&svm->vcpu);
1095 }
1096
1097 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1098 {
1099 svm->next_rip = svm->vmcb->save.rip + 3;
1100 skip_emulated_instruction(&svm->vcpu);
1101 kvm_emulate_hypercall(&svm->vcpu);
1102 return 1;
1103 }
1104
1105 static int invalid_op_interception(struct vcpu_svm *svm,
1106 struct kvm_run *kvm_run)
1107 {
1108 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1109 return 1;
1110 }
1111
1112 static int task_switch_interception(struct vcpu_svm *svm,
1113 struct kvm_run *kvm_run)
1114 {
1115 u16 tss_selector;
1116
1117 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1118 if (svm->vmcb->control.exit_info_2 &
1119 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1120 return kvm_task_switch(&svm->vcpu, tss_selector,
1121 TASK_SWITCH_IRET);
1122 if (svm->vmcb->control.exit_info_2 &
1123 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1124 return kvm_task_switch(&svm->vcpu, tss_selector,
1125 TASK_SWITCH_JMP);
1126 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1127 }
1128
1129 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1130 {
1131 svm->next_rip = svm->vmcb->save.rip + 2;
1132 kvm_emulate_cpuid(&svm->vcpu);
1133 return 1;
1134 }
1135
1136 static int emulate_on_interception(struct vcpu_svm *svm,
1137 struct kvm_run *kvm_run)
1138 {
1139 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1140 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1141 return 1;
1142 }
1143
1144 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1145 {
1146 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1147 if (irqchip_in_kernel(svm->vcpu.kvm))
1148 return 1;
1149 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1150 return 0;
1151 }
1152
1153 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1154 {
1155 struct vcpu_svm *svm = to_svm(vcpu);
1156
1157 switch (ecx) {
1158 case MSR_IA32_TIME_STAMP_COUNTER: {
1159 u64 tsc;
1160
1161 rdtscll(tsc);
1162 *data = svm->vmcb->control.tsc_offset + tsc;
1163 break;
1164 }
1165 case MSR_K6_STAR:
1166 *data = svm->vmcb->save.star;
1167 break;
1168 #ifdef CONFIG_X86_64
1169 case MSR_LSTAR:
1170 *data = svm->vmcb->save.lstar;
1171 break;
1172 case MSR_CSTAR:
1173 *data = svm->vmcb->save.cstar;
1174 break;
1175 case MSR_KERNEL_GS_BASE:
1176 *data = svm->vmcb->save.kernel_gs_base;
1177 break;
1178 case MSR_SYSCALL_MASK:
1179 *data = svm->vmcb->save.sfmask;
1180 break;
1181 #endif
1182 case MSR_IA32_SYSENTER_CS:
1183 *data = svm->vmcb->save.sysenter_cs;
1184 break;
1185 case MSR_IA32_SYSENTER_EIP:
1186 *data = svm->vmcb->save.sysenter_eip;
1187 break;
1188 case MSR_IA32_SYSENTER_ESP:
1189 *data = svm->vmcb->save.sysenter_esp;
1190 break;
1191 /* Nobody will change the following 5 values in the VMCB so
1192 we can safely return them on rdmsr. They will always be 0
1193 until LBRV is implemented. */
1194 case MSR_IA32_DEBUGCTLMSR:
1195 *data = svm->vmcb->save.dbgctl;
1196 break;
1197 case MSR_IA32_LASTBRANCHFROMIP:
1198 *data = svm->vmcb->save.br_from;
1199 break;
1200 case MSR_IA32_LASTBRANCHTOIP:
1201 *data = svm->vmcb->save.br_to;
1202 break;
1203 case MSR_IA32_LASTINTFROMIP:
1204 *data = svm->vmcb->save.last_excp_from;
1205 break;
1206 case MSR_IA32_LASTINTTOIP:
1207 *data = svm->vmcb->save.last_excp_to;
1208 break;
1209 default:
1210 return kvm_get_msr_common(vcpu, ecx, data);
1211 }
1212 return 0;
1213 }
1214
1215 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1216 {
1217 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1218 u64 data;
1219
1220 if (svm_get_msr(&svm->vcpu, ecx, &data))
1221 kvm_inject_gp(&svm->vcpu, 0);
1222 else {
1223 svm->vmcb->save.rax = data & 0xffffffff;
1224 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1225 svm->next_rip = svm->vmcb->save.rip + 2;
1226 skip_emulated_instruction(&svm->vcpu);
1227 }
1228 return 1;
1229 }
1230
1231 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1232 {
1233 struct vcpu_svm *svm = to_svm(vcpu);
1234
1235 switch (ecx) {
1236 case MSR_IA32_TIME_STAMP_COUNTER: {
1237 u64 tsc;
1238
1239 rdtscll(tsc);
1240 svm->vmcb->control.tsc_offset = data - tsc;
1241 break;
1242 }
1243 case MSR_K6_STAR:
1244 svm->vmcb->save.star = data;
1245 break;
1246 #ifdef CONFIG_X86_64
1247 case MSR_LSTAR:
1248 svm->vmcb->save.lstar = data;
1249 break;
1250 case MSR_CSTAR:
1251 svm->vmcb->save.cstar = data;
1252 break;
1253 case MSR_KERNEL_GS_BASE:
1254 svm->vmcb->save.kernel_gs_base = data;
1255 break;
1256 case MSR_SYSCALL_MASK:
1257 svm->vmcb->save.sfmask = data;
1258 break;
1259 #endif
1260 case MSR_IA32_SYSENTER_CS:
1261 svm->vmcb->save.sysenter_cs = data;
1262 break;
1263 case MSR_IA32_SYSENTER_EIP:
1264 svm->vmcb->save.sysenter_eip = data;
1265 break;
1266 case MSR_IA32_SYSENTER_ESP:
1267 svm->vmcb->save.sysenter_esp = data;
1268 break;
1269 case MSR_IA32_DEBUGCTLMSR:
1270 if (!svm_has(SVM_FEATURE_LBRV)) {
1271 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1272 __func__, data);
1273 break;
1274 }
1275 if (data & DEBUGCTL_RESERVED_BITS)
1276 return 1;
1277
1278 svm->vmcb->save.dbgctl = data;
1279 if (data & (1ULL<<0))
1280 svm_enable_lbrv(svm);
1281 else
1282 svm_disable_lbrv(svm);
1283 break;
1284 case MSR_K7_EVNTSEL0:
1285 case MSR_K7_EVNTSEL1:
1286 case MSR_K7_EVNTSEL2:
1287 case MSR_K7_EVNTSEL3:
1288 /*
1289 * only support writing 0 to the performance counters for now
1290 * to make Windows happy. Should be replaced by a real
1291 * performance counter emulation later.
1292 */
1293 if (data != 0)
1294 goto unhandled;
1295 break;
1296 default:
1297 unhandled:
1298 return kvm_set_msr_common(vcpu, ecx, data);
1299 }
1300 return 0;
1301 }
1302
1303 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1304 {
1305 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1306 u64 data = (svm->vmcb->save.rax & -1u)
1307 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1308 svm->next_rip = svm->vmcb->save.rip + 2;
1309 if (svm_set_msr(&svm->vcpu, ecx, data))
1310 kvm_inject_gp(&svm->vcpu, 0);
1311 else
1312 skip_emulated_instruction(&svm->vcpu);
1313 return 1;
1314 }
1315
1316 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1317 {
1318 if (svm->vmcb->control.exit_info_1)
1319 return wrmsr_interception(svm, kvm_run);
1320 else
1321 return rdmsr_interception(svm, kvm_run);
1322 }
1323
1324 static int interrupt_window_interception(struct vcpu_svm *svm,
1325 struct kvm_run *kvm_run)
1326 {
1327 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1328 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1329 /*
1330 * If the user space waits to inject interrupts, exit as soon as
1331 * possible
1332 */
1333 if (kvm_run->request_interrupt_window &&
1334 !svm->vcpu.arch.irq_summary) {
1335 ++svm->vcpu.stat.irq_window_exits;
1336 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1337 return 0;
1338 }
1339
1340 return 1;
1341 }
1342
1343 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1344 struct kvm_run *kvm_run) = {
1345 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1346 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1347 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1348 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1349 /* for now: */
1350 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1351 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1352 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1353 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1354 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1355 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1356 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1357 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1358 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1359 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1360 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1361 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1362 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1363 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1364 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1365 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1366 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1367 [SVM_EXIT_INTR] = nop_on_interception,
1368 [SVM_EXIT_NMI] = nop_on_interception,
1369 [SVM_EXIT_SMI] = nop_on_interception,
1370 [SVM_EXIT_INIT] = nop_on_interception,
1371 [SVM_EXIT_VINTR] = interrupt_window_interception,
1372 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1373 [SVM_EXIT_CPUID] = cpuid_interception,
1374 [SVM_EXIT_INVD] = emulate_on_interception,
1375 [SVM_EXIT_HLT] = halt_interception,
1376 [SVM_EXIT_INVLPG] = emulate_on_interception,
1377 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1378 [SVM_EXIT_IOIO] = io_interception,
1379 [SVM_EXIT_MSR] = msr_interception,
1380 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1381 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1382 [SVM_EXIT_VMRUN] = invalid_op_interception,
1383 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1384 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1385 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1386 [SVM_EXIT_STGI] = invalid_op_interception,
1387 [SVM_EXIT_CLGI] = invalid_op_interception,
1388 [SVM_EXIT_SKINIT] = invalid_op_interception,
1389 [SVM_EXIT_WBINVD] = emulate_on_interception,
1390 [SVM_EXIT_MONITOR] = invalid_op_interception,
1391 [SVM_EXIT_MWAIT] = invalid_op_interception,
1392 [SVM_EXIT_NPF] = pf_interception,
1393 };
1394
1395 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1396 {
1397 struct vcpu_svm *svm = to_svm(vcpu);
1398 u32 exit_code = svm->vmcb->control.exit_code;
1399
1400 if (npt_enabled) {
1401 int mmu_reload = 0;
1402 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1403 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1404 mmu_reload = 1;
1405 }
1406 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1407 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1408 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1409 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1410 kvm_inject_gp(vcpu, 0);
1411 return 1;
1412 }
1413 }
1414 if (mmu_reload) {
1415 kvm_mmu_reset_context(vcpu);
1416 kvm_mmu_load(vcpu);
1417 }
1418 }
1419
1420 kvm_reput_irq(svm);
1421
1422 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1423 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1424 kvm_run->fail_entry.hardware_entry_failure_reason
1425 = svm->vmcb->control.exit_code;
1426 return 0;
1427 }
1428
1429 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1430 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1431 exit_code != SVM_EXIT_NPF)
1432 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1433 "exit_code 0x%x\n",
1434 __func__, svm->vmcb->control.exit_int_info,
1435 exit_code);
1436
1437 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1438 || !svm_exit_handlers[exit_code]) {
1439 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1440 kvm_run->hw.hardware_exit_reason = exit_code;
1441 return 0;
1442 }
1443
1444 return svm_exit_handlers[exit_code](svm, kvm_run);
1445 }
1446
1447 static void reload_tss(struct kvm_vcpu *vcpu)
1448 {
1449 int cpu = raw_smp_processor_id();
1450
1451 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1452 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1453 load_TR_desc();
1454 }
1455
1456 static void pre_svm_run(struct vcpu_svm *svm)
1457 {
1458 int cpu = raw_smp_processor_id();
1459
1460 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1461
1462 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1463 if (svm->vcpu.cpu != cpu ||
1464 svm->asid_generation != svm_data->asid_generation)
1465 new_asid(svm, svm_data);
1466 }
1467
1468
1469 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1470 {
1471 struct vmcb_control_area *control;
1472
1473 control = &svm->vmcb->control;
1474 control->int_vector = irq;
1475 control->int_ctl &= ~V_INTR_PRIO_MASK;
1476 control->int_ctl |= V_IRQ_MASK |
1477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1478 }
1479
1480 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1481 {
1482 struct vcpu_svm *svm = to_svm(vcpu);
1483
1484 svm_inject_irq(svm, irq);
1485 }
1486
1487 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1488 {
1489 struct vcpu_svm *svm = to_svm(vcpu);
1490 struct vmcb *vmcb = svm->vmcb;
1491 int intr_vector = -1;
1492
1493 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1494 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1495 intr_vector = vmcb->control.exit_int_info &
1496 SVM_EVTINJ_VEC_MASK;
1497 vmcb->control.exit_int_info = 0;
1498 svm_inject_irq(svm, intr_vector);
1499 return;
1500 }
1501
1502 if (vmcb->control.int_ctl & V_IRQ_MASK)
1503 return;
1504
1505 if (!kvm_cpu_has_interrupt(vcpu))
1506 return;
1507
1508 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1509 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1510 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1511 /* unable to deliver irq, set pending irq */
1512 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1513 svm_inject_irq(svm, 0x0);
1514 return;
1515 }
1516 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1517 intr_vector = kvm_cpu_get_interrupt(vcpu);
1518 svm_inject_irq(svm, intr_vector);
1519 kvm_timer_intr_post(vcpu, intr_vector);
1520 }
1521
1522 static void kvm_reput_irq(struct vcpu_svm *svm)
1523 {
1524 struct vmcb_control_area *control = &svm->vmcb->control;
1525
1526 if ((control->int_ctl & V_IRQ_MASK)
1527 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1528 control->int_ctl &= ~V_IRQ_MASK;
1529 push_irq(&svm->vcpu, control->int_vector);
1530 }
1531
1532 svm->vcpu.arch.interrupt_window_open =
1533 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1534 }
1535
1536 static void svm_do_inject_vector(struct vcpu_svm *svm)
1537 {
1538 struct kvm_vcpu *vcpu = &svm->vcpu;
1539 int word_index = __ffs(vcpu->arch.irq_summary);
1540 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1541 int irq = word_index * BITS_PER_LONG + bit_index;
1542
1543 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1544 if (!vcpu->arch.irq_pending[word_index])
1545 clear_bit(word_index, &vcpu->arch.irq_summary);
1546 svm_inject_irq(svm, irq);
1547 }
1548
1549 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1550 struct kvm_run *kvm_run)
1551 {
1552 struct vcpu_svm *svm = to_svm(vcpu);
1553 struct vmcb_control_area *control = &svm->vmcb->control;
1554
1555 svm->vcpu.arch.interrupt_window_open =
1556 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1557 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1558
1559 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1560 /*
1561 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1562 */
1563 svm_do_inject_vector(svm);
1564
1565 /*
1566 * Interrupts blocked. Wait for unblock.
1567 */
1568 if (!svm->vcpu.arch.interrupt_window_open &&
1569 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1570 control->intercept |= 1ULL << INTERCEPT_VINTR;
1571 else
1572 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1573 }
1574
1575 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1576 {
1577 return 0;
1578 }
1579
1580 static void save_db_regs(unsigned long *db_regs)
1581 {
1582 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1583 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1584 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1585 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1586 }
1587
1588 static void load_db_regs(unsigned long *db_regs)
1589 {
1590 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1591 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1592 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1593 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1594 }
1595
1596 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1597 {
1598 force_new_asid(vcpu);
1599 }
1600
1601 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1602 {
1603 }
1604
1605 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1606 {
1607 struct vcpu_svm *svm = to_svm(vcpu);
1608 u16 fs_selector;
1609 u16 gs_selector;
1610 u16 ldt_selector;
1611
1612 pre_svm_run(svm);
1613
1614 save_host_msrs(vcpu);
1615 fs_selector = read_fs();
1616 gs_selector = read_gs();
1617 ldt_selector = read_ldt();
1618 svm->host_cr2 = kvm_read_cr2();
1619 svm->host_dr6 = read_dr6();
1620 svm->host_dr7 = read_dr7();
1621 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1622 /* required for live migration with NPT */
1623 if (npt_enabled)
1624 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1625
1626 if (svm->vmcb->save.dr7 & 0xff) {
1627 write_dr7(0);
1628 save_db_regs(svm->host_db_regs);
1629 load_db_regs(svm->db_regs);
1630 }
1631
1632 clgi();
1633
1634 local_irq_enable();
1635
1636 asm volatile (
1637 #ifdef CONFIG_X86_64
1638 "push %%rbp; \n\t"
1639 #else
1640 "push %%ebp; \n\t"
1641 #endif
1642
1643 #ifdef CONFIG_X86_64
1644 "mov %c[rbx](%[svm]), %%rbx \n\t"
1645 "mov %c[rcx](%[svm]), %%rcx \n\t"
1646 "mov %c[rdx](%[svm]), %%rdx \n\t"
1647 "mov %c[rsi](%[svm]), %%rsi \n\t"
1648 "mov %c[rdi](%[svm]), %%rdi \n\t"
1649 "mov %c[rbp](%[svm]), %%rbp \n\t"
1650 "mov %c[r8](%[svm]), %%r8 \n\t"
1651 "mov %c[r9](%[svm]), %%r9 \n\t"
1652 "mov %c[r10](%[svm]), %%r10 \n\t"
1653 "mov %c[r11](%[svm]), %%r11 \n\t"
1654 "mov %c[r12](%[svm]), %%r12 \n\t"
1655 "mov %c[r13](%[svm]), %%r13 \n\t"
1656 "mov %c[r14](%[svm]), %%r14 \n\t"
1657 "mov %c[r15](%[svm]), %%r15 \n\t"
1658 #else
1659 "mov %c[rbx](%[svm]), %%ebx \n\t"
1660 "mov %c[rcx](%[svm]), %%ecx \n\t"
1661 "mov %c[rdx](%[svm]), %%edx \n\t"
1662 "mov %c[rsi](%[svm]), %%esi \n\t"
1663 "mov %c[rdi](%[svm]), %%edi \n\t"
1664 "mov %c[rbp](%[svm]), %%ebp \n\t"
1665 #endif
1666
1667 #ifdef CONFIG_X86_64
1668 /* Enter guest mode */
1669 "push %%rax \n\t"
1670 "mov %c[vmcb](%[svm]), %%rax \n\t"
1671 SVM_VMLOAD "\n\t"
1672 SVM_VMRUN "\n\t"
1673 SVM_VMSAVE "\n\t"
1674 "pop %%rax \n\t"
1675 #else
1676 /* Enter guest mode */
1677 "push %%eax \n\t"
1678 "mov %c[vmcb](%[svm]), %%eax \n\t"
1679 SVM_VMLOAD "\n\t"
1680 SVM_VMRUN "\n\t"
1681 SVM_VMSAVE "\n\t"
1682 "pop %%eax \n\t"
1683 #endif
1684
1685 /* Save guest registers, load host registers */
1686 #ifdef CONFIG_X86_64
1687 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1688 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1689 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1690 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1691 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1692 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1693 "mov %%r8, %c[r8](%[svm]) \n\t"
1694 "mov %%r9, %c[r9](%[svm]) \n\t"
1695 "mov %%r10, %c[r10](%[svm]) \n\t"
1696 "mov %%r11, %c[r11](%[svm]) \n\t"
1697 "mov %%r12, %c[r12](%[svm]) \n\t"
1698 "mov %%r13, %c[r13](%[svm]) \n\t"
1699 "mov %%r14, %c[r14](%[svm]) \n\t"
1700 "mov %%r15, %c[r15](%[svm]) \n\t"
1701
1702 "pop %%rbp; \n\t"
1703 #else
1704 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1705 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1706 "mov %%edx, %c[rdx](%[svm]) \n\t"
1707 "mov %%esi, %c[rsi](%[svm]) \n\t"
1708 "mov %%edi, %c[rdi](%[svm]) \n\t"
1709 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1710
1711 "pop %%ebp; \n\t"
1712 #endif
1713 :
1714 : [svm]"a"(svm),
1715 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1716 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1717 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1718 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1719 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1720 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1721 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1722 #ifdef CONFIG_X86_64
1723 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1724 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1725 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1726 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1727 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1728 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1729 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1730 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1731 #endif
1732 : "cc", "memory"
1733 #ifdef CONFIG_X86_64
1734 , "rbx", "rcx", "rdx", "rsi", "rdi"
1735 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1736 #else
1737 , "ebx", "ecx", "edx" , "esi", "edi"
1738 #endif
1739 );
1740
1741 if ((svm->vmcb->save.dr7 & 0xff))
1742 load_db_regs(svm->host_db_regs);
1743
1744 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1745
1746 write_dr6(svm->host_dr6);
1747 write_dr7(svm->host_dr7);
1748 kvm_write_cr2(svm->host_cr2);
1749
1750 load_fs(fs_selector);
1751 load_gs(gs_selector);
1752 load_ldt(ldt_selector);
1753 load_host_msrs(vcpu);
1754
1755 reload_tss(vcpu);
1756
1757 local_irq_disable();
1758
1759 stgi();
1760
1761 svm->next_rip = 0;
1762 }
1763
1764 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1765 {
1766 struct vcpu_svm *svm = to_svm(vcpu);
1767
1768 if (npt_enabled) {
1769 svm->vmcb->control.nested_cr3 = root;
1770 force_new_asid(vcpu);
1771 return;
1772 }
1773
1774 svm->vmcb->save.cr3 = root;
1775 force_new_asid(vcpu);
1776
1777 if (vcpu->fpu_active) {
1778 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1779 svm->vmcb->save.cr0 |= X86_CR0_TS;
1780 vcpu->fpu_active = 0;
1781 }
1782 }
1783
1784 static int is_disabled(void)
1785 {
1786 u64 vm_cr;
1787
1788 rdmsrl(MSR_VM_CR, vm_cr);
1789 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1790 return 1;
1791
1792 return 0;
1793 }
1794
1795 static void
1796 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1797 {
1798 /*
1799 * Patch in the VMMCALL instruction:
1800 */
1801 hypercall[0] = 0x0f;
1802 hypercall[1] = 0x01;
1803 hypercall[2] = 0xd9;
1804 }
1805
1806 static void svm_check_processor_compat(void *rtn)
1807 {
1808 *(int *)rtn = 0;
1809 }
1810
1811 static bool svm_cpu_has_accelerated_tpr(void)
1812 {
1813 return false;
1814 }
1815
1816 static struct kvm_x86_ops svm_x86_ops = {
1817 .cpu_has_kvm_support = has_svm,
1818 .disabled_by_bios = is_disabled,
1819 .hardware_setup = svm_hardware_setup,
1820 .hardware_unsetup = svm_hardware_unsetup,
1821 .check_processor_compatibility = svm_check_processor_compat,
1822 .hardware_enable = svm_hardware_enable,
1823 .hardware_disable = svm_hardware_disable,
1824 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1825
1826 .vcpu_create = svm_create_vcpu,
1827 .vcpu_free = svm_free_vcpu,
1828 .vcpu_reset = svm_vcpu_reset,
1829
1830 .prepare_guest_switch = svm_prepare_guest_switch,
1831 .vcpu_load = svm_vcpu_load,
1832 .vcpu_put = svm_vcpu_put,
1833 .vcpu_decache = svm_vcpu_decache,
1834
1835 .set_guest_debug = svm_guest_debug,
1836 .get_msr = svm_get_msr,
1837 .set_msr = svm_set_msr,
1838 .get_segment_base = svm_get_segment_base,
1839 .get_segment = svm_get_segment,
1840 .set_segment = svm_set_segment,
1841 .get_cpl = svm_get_cpl,
1842 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1843 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1844 .set_cr0 = svm_set_cr0,
1845 .set_cr3 = svm_set_cr3,
1846 .set_cr4 = svm_set_cr4,
1847 .set_efer = svm_set_efer,
1848 .get_idt = svm_get_idt,
1849 .set_idt = svm_set_idt,
1850 .get_gdt = svm_get_gdt,
1851 .set_gdt = svm_set_gdt,
1852 .get_dr = svm_get_dr,
1853 .set_dr = svm_set_dr,
1854 .cache_regs = svm_cache_regs,
1855 .decache_regs = svm_decache_regs,
1856 .get_rflags = svm_get_rflags,
1857 .set_rflags = svm_set_rflags,
1858
1859 .tlb_flush = svm_flush_tlb,
1860
1861 .run = svm_vcpu_run,
1862 .handle_exit = handle_exit,
1863 .skip_emulated_instruction = skip_emulated_instruction,
1864 .patch_hypercall = svm_patch_hypercall,
1865 .get_irq = svm_get_irq,
1866 .set_irq = svm_set_irq,
1867 .queue_exception = svm_queue_exception,
1868 .exception_injected = svm_exception_injected,
1869 .inject_pending_irq = svm_intr_assist,
1870 .inject_pending_vectors = do_interrupt_requests,
1871
1872 .set_tss_addr = svm_set_tss_addr,
1873 };
1874
1875 static int __init svm_init(void)
1876 {
1877 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1878 THIS_MODULE);
1879 }
1880
1881 static void __exit svm_exit(void)
1882 {
1883 kvm_exit();
1884 }
1885
1886 module_init(svm_init)
1887 module_exit(svm_exit)
Linux kernel - Deliverables
This page took 0.281606 seconds and 5 git commands to generate.