2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
62 static bool erratum_383_found __read_mostly
;
64 static const u32 host_save_user_msrs
[] = {
66 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
69 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
82 /* These are the merged vectors */
85 /* gpa pointers to the real vectors */
89 /* A VMEXIT is required but not yet emulated */
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
96 unsigned long vmexit_rip
;
97 unsigned long vmexit_rsp
;
98 unsigned long vmexit_rax
;
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions
;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
114 struct kvm_vcpu vcpu
;
116 unsigned long vmcb_pa
;
117 struct svm_cpu_data
*svm_data
;
118 uint64_t asid_generation
;
119 uint64_t sysenter_esp
;
120 uint64_t sysenter_eip
;
124 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
134 struct nested_state nested
;
138 unsigned int3_injected
;
139 unsigned long int3_rip
;
143 #define MSR_INVALID 0xffffffffU
145 static struct svm_direct_access_msrs
{
146 u32 index
; /* Index of the MSR */
147 bool always
; /* True if intercept is always on */
148 } direct_access_msrs
[] = {
149 { .index
= MSR_STAR
, .always
= true },
150 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
152 { .index
= MSR_GS_BASE
, .always
= true },
153 { .index
= MSR_FS_BASE
, .always
= true },
154 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
155 { .index
= MSR_LSTAR
, .always
= true },
156 { .index
= MSR_CSTAR
, .always
= true },
157 { .index
= MSR_SYSCALL_MASK
, .always
= true },
159 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
160 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
161 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
162 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
163 { .index
= MSR_INVALID
, .always
= false },
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled
= true;
170 static bool npt_enabled
;
174 module_param(npt
, int, S_IRUGO
);
176 static int nested
= 1;
177 module_param(nested
, int, S_IRUGO
);
179 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
180 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
182 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
183 static int nested_svm_intercept(struct vcpu_svm
*svm
);
184 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
185 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
186 bool has_error_code
, u32 error_code
);
189 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
192 VMCB_ASID
, /* ASID */
193 VMCB_INTR
, /* int_ctl, int_vector */
194 VMCB_NPT
, /* npt_en, nCR3, gPAT */
195 VMCB_CR
, /* CR0, CR3, CR4, EFER */
196 VMCB_DR
, /* DR6, DR7 */
197 VMCB_DT
, /* GDT, IDT */
198 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
199 VMCB_CR2
, /* CR2 only */
203 /* TPR and CR2 are always written before VMRUN */
204 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
206 static inline void mark_all_dirty(struct vmcb
*vmcb
)
208 vmcb
->control
.clean
= 0;
211 static inline void mark_all_clean(struct vmcb
*vmcb
)
213 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
214 & ~VMCB_ALWAYS_DIRTY_MASK
;
217 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
219 vmcb
->control
.clean
&= ~(1 << bit
);
222 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
224 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
227 static void recalc_intercepts(struct vcpu_svm
*svm
)
229 struct vmcb_control_area
*c
, *h
;
230 struct nested_state
*g
;
232 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
234 if (!is_guest_mode(&svm
->vcpu
))
237 c
= &svm
->vmcb
->control
;
238 h
= &svm
->nested
.hsave
->control
;
241 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
242 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
243 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
244 c
->intercept
= h
->intercept
| g
->intercept
;
247 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
249 if (is_guest_mode(&svm
->vcpu
))
250 return svm
->nested
.hsave
;
255 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
257 struct vmcb
*vmcb
= get_host_vmcb(svm
);
259 vmcb
->control
.intercept_cr
|= (1U << bit
);
261 recalc_intercepts(svm
);
264 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
266 struct vmcb
*vmcb
= get_host_vmcb(svm
);
268 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
270 recalc_intercepts(svm
);
273 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
275 struct vmcb
*vmcb
= get_host_vmcb(svm
);
277 return vmcb
->control
.intercept_cr
& (1U << bit
);
280 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
282 struct vmcb
*vmcb
= get_host_vmcb(svm
);
284 vmcb
->control
.intercept_dr
|= (1U << bit
);
286 recalc_intercepts(svm
);
289 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
291 struct vmcb
*vmcb
= get_host_vmcb(svm
);
293 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
295 recalc_intercepts(svm
);
298 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
300 struct vmcb
*vmcb
= get_host_vmcb(svm
);
302 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
304 recalc_intercepts(svm
);
307 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
309 struct vmcb
*vmcb
= get_host_vmcb(svm
);
311 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
313 recalc_intercepts(svm
);
316 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
318 struct vmcb
*vmcb
= get_host_vmcb(svm
);
320 vmcb
->control
.intercept
|= (1ULL << bit
);
322 recalc_intercepts(svm
);
325 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
327 struct vmcb
*vmcb
= get_host_vmcb(svm
);
329 vmcb
->control
.intercept
&= ~(1ULL << bit
);
331 recalc_intercepts(svm
);
334 static inline void enable_gif(struct vcpu_svm
*svm
)
336 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
339 static inline void disable_gif(struct vcpu_svm
*svm
)
341 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
344 static inline bool gif_set(struct vcpu_svm
*svm
)
346 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
349 static unsigned long iopm_base
;
351 struct kvm_ldttss_desc
{
354 unsigned base1
:8, type
:5, dpl
:2, p
:1;
355 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
358 } __attribute__((packed
));
360 struct svm_cpu_data
{
366 struct kvm_ldttss_desc
*tss_desc
;
368 struct page
*save_area
;
371 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
372 static uint32_t svm_features
;
374 struct svm_init_data
{
379 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
381 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
382 #define MSRS_RANGE_SIZE 2048
383 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
385 static u32
svm_msrpm_offset(u32 msr
)
390 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
391 if (msr
< msrpm_ranges
[i
] ||
392 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
395 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
396 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
398 /* Now we have the u8 offset - but need the u32 offset */
402 /* MSR not in any range */
406 #define MAX_INST_SIZE 15
408 static inline void clgi(void)
410 asm volatile (__ex(SVM_CLGI
));
413 static inline void stgi(void)
415 asm volatile (__ex(SVM_STGI
));
418 static inline void invlpga(unsigned long addr
, u32 asid
)
420 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
423 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
425 to_svm(vcpu
)->asid_generation
--;
428 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
430 force_new_asid(vcpu
);
433 static int get_npt_level(void)
436 return PT64_ROOT_LEVEL
;
438 return PT32E_ROOT_LEVEL
;
442 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
444 vcpu
->arch
.efer
= efer
;
445 if (!npt_enabled
&& !(efer
& EFER_LMA
))
448 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
449 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
452 static int is_external_interrupt(u32 info
)
454 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
455 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
458 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
460 struct vcpu_svm
*svm
= to_svm(vcpu
);
463 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
464 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
468 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
470 struct vcpu_svm
*svm
= to_svm(vcpu
);
473 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
475 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
479 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
481 struct vcpu_svm
*svm
= to_svm(vcpu
);
483 if (svm
->vmcb
->control
.next_rip
!= 0)
484 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
486 if (!svm
->next_rip
) {
487 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
489 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
492 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
493 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
494 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
496 kvm_rip_write(vcpu
, svm
->next_rip
);
497 svm_set_interrupt_shadow(vcpu
, 0);
500 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
501 bool has_error_code
, u32 error_code
,
504 struct vcpu_svm
*svm
= to_svm(vcpu
);
507 * If we are within a nested VM we'd better #VMEXIT and let the guest
508 * handle the exception
511 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
514 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
515 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
518 * For guest debugging where we have to reinject #BP if some
519 * INT3 is guest-owned:
520 * Emulate nRIP by moving RIP forward. Will fail if injection
521 * raises a fault that is not intercepted. Still better than
522 * failing in all cases.
524 skip_emulated_instruction(&svm
->vcpu
);
525 rip
= kvm_rip_read(&svm
->vcpu
);
526 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
527 svm
->int3_injected
= rip
- old_rip
;
530 svm
->vmcb
->control
.event_inj
= nr
532 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
533 | SVM_EVTINJ_TYPE_EXEPT
;
534 svm
->vmcb
->control
.event_inj_err
= error_code
;
537 static void svm_init_erratum_383(void)
543 if (!cpu_has_amd_erratum(amd_erratum_383
))
546 /* Use _safe variants to not break nested virtualization */
547 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
553 low
= lower_32_bits(val
);
554 high
= upper_32_bits(val
);
556 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
558 erratum_383_found
= true;
561 static int has_svm(void)
565 if (!cpu_has_svm(&msg
)) {
566 printk(KERN_INFO
"has_svm: %s\n", msg
);
573 static void svm_hardware_disable(void *garbage
)
578 static int svm_hardware_enable(void *garbage
)
581 struct svm_cpu_data
*sd
;
583 struct desc_ptr gdt_descr
;
584 struct desc_struct
*gdt
;
585 int me
= raw_smp_processor_id();
587 rdmsrl(MSR_EFER
, efer
);
588 if (efer
& EFER_SVME
)
592 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
596 sd
= per_cpu(svm_data
, me
);
599 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
604 sd
->asid_generation
= 1;
605 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
606 sd
->next_asid
= sd
->max_asid
+ 1;
608 native_store_gdt(&gdt_descr
);
609 gdt
= (struct desc_struct
*)gdt_descr
.address
;
610 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
612 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
614 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
616 svm_init_erratum_383();
621 static void svm_cpu_uninit(int cpu
)
623 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
628 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
629 __free_page(sd
->save_area
);
633 static int svm_cpu_init(int cpu
)
635 struct svm_cpu_data
*sd
;
638 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
642 sd
->save_area
= alloc_page(GFP_KERNEL
);
647 per_cpu(svm_data
, cpu
) = sd
;
657 static bool valid_msr_intercept(u32 index
)
661 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
662 if (direct_access_msrs
[i
].index
== index
)
668 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
671 u8 bit_read
, bit_write
;
676 * If this warning triggers extend the direct_access_msrs list at the
677 * beginning of the file
679 WARN_ON(!valid_msr_intercept(msr
));
681 offset
= svm_msrpm_offset(msr
);
682 bit_read
= 2 * (msr
& 0x0f);
683 bit_write
= 2 * (msr
& 0x0f) + 1;
686 BUG_ON(offset
== MSR_INVALID
);
688 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
689 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
694 static void svm_vcpu_init_msrpm(u32
*msrpm
)
698 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
700 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
701 if (!direct_access_msrs
[i
].always
)
704 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
708 static void add_msr_offset(u32 offset
)
712 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
714 /* Offset already in list? */
715 if (msrpm_offsets
[i
] == offset
)
718 /* Slot used by another offset? */
719 if (msrpm_offsets
[i
] != MSR_INVALID
)
722 /* Add offset to list */
723 msrpm_offsets
[i
] = offset
;
729 * If this BUG triggers the msrpm_offsets table has an overflow. Just
730 * increase MSRPM_OFFSETS in this case.
735 static void init_msrpm_offsets(void)
739 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
741 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
744 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
745 BUG_ON(offset
== MSR_INVALID
);
747 add_msr_offset(offset
);
751 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
753 u32
*msrpm
= svm
->msrpm
;
755 svm
->vmcb
->control
.lbr_ctl
= 1;
756 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
757 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
758 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
759 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
762 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
764 u32
*msrpm
= svm
->msrpm
;
766 svm
->vmcb
->control
.lbr_ctl
= 0;
767 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
768 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
769 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
770 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
773 static __init
int svm_hardware_setup(void)
776 struct page
*iopm_pages
;
780 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
785 iopm_va
= page_address(iopm_pages
);
786 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
787 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
789 init_msrpm_offsets();
791 if (boot_cpu_has(X86_FEATURE_NX
))
792 kvm_enable_efer_bits(EFER_NX
);
794 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
795 kvm_enable_efer_bits(EFER_FFXSR
);
798 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
799 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
802 for_each_possible_cpu(cpu
) {
803 r
= svm_cpu_init(cpu
);
808 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
810 if (!boot_cpu_has(X86_FEATURE_NPT
))
813 if (npt_enabled
&& !npt
) {
814 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
819 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
827 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
832 static __exit
void svm_hardware_unsetup(void)
836 for_each_possible_cpu(cpu
)
839 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
843 static void init_seg(struct vmcb_seg
*seg
)
846 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
847 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
852 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
855 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
860 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
862 struct vcpu_svm
*svm
= to_svm(vcpu
);
863 u64 g_tsc_offset
= 0;
865 if (is_guest_mode(vcpu
)) {
866 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
867 svm
->nested
.hsave
->control
.tsc_offset
;
868 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
871 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
873 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
876 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
878 struct vcpu_svm
*svm
= to_svm(vcpu
);
880 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
881 if (is_guest_mode(vcpu
))
882 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
883 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
886 static void init_vmcb(struct vcpu_svm
*svm
)
888 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
889 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
891 svm
->vcpu
.fpu_active
= 1;
892 svm
->vcpu
.arch
.hflags
= 0;
894 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
895 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
896 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
897 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
898 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
899 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
900 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
902 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
903 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
904 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
905 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
906 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
907 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
908 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
909 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
911 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
912 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
913 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
914 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
915 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
916 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
917 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
918 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
920 set_exception_intercept(svm
, PF_VECTOR
);
921 set_exception_intercept(svm
, UD_VECTOR
);
922 set_exception_intercept(svm
, MC_VECTOR
);
924 set_intercept(svm
, INTERCEPT_INTR
);
925 set_intercept(svm
, INTERCEPT_NMI
);
926 set_intercept(svm
, INTERCEPT_SMI
);
927 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
928 set_intercept(svm
, INTERCEPT_CPUID
);
929 set_intercept(svm
, INTERCEPT_INVD
);
930 set_intercept(svm
, INTERCEPT_HLT
);
931 set_intercept(svm
, INTERCEPT_INVLPG
);
932 set_intercept(svm
, INTERCEPT_INVLPGA
);
933 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
934 set_intercept(svm
, INTERCEPT_MSR_PROT
);
935 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
936 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
937 set_intercept(svm
, INTERCEPT_VMRUN
);
938 set_intercept(svm
, INTERCEPT_VMMCALL
);
939 set_intercept(svm
, INTERCEPT_VMLOAD
);
940 set_intercept(svm
, INTERCEPT_VMSAVE
);
941 set_intercept(svm
, INTERCEPT_STGI
);
942 set_intercept(svm
, INTERCEPT_CLGI
);
943 set_intercept(svm
, INTERCEPT_SKINIT
);
944 set_intercept(svm
, INTERCEPT_WBINVD
);
945 set_intercept(svm
, INTERCEPT_MONITOR
);
946 set_intercept(svm
, INTERCEPT_MWAIT
);
948 control
->iopm_base_pa
= iopm_base
;
949 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
950 control
->int_ctl
= V_INTR_MASKING_MASK
;
958 save
->cs
.selector
= 0xf000;
959 /* Executable/Readable Code Segment */
960 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
961 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
962 save
->cs
.limit
= 0xffff;
964 * cs.base should really be 0xffff0000, but vmx can't handle that, so
965 * be consistent with it.
967 * Replace when we have real mode working for vmx.
969 save
->cs
.base
= 0xf0000;
971 save
->gdtr
.limit
= 0xffff;
972 save
->idtr
.limit
= 0xffff;
974 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
975 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
977 svm_set_efer(&svm
->vcpu
, 0);
978 save
->dr6
= 0xffff0ff0;
981 save
->rip
= 0x0000fff0;
982 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
985 * This is the guest-visible cr0 value.
986 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
988 svm
->vcpu
.arch
.cr0
= 0;
989 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
991 save
->cr4
= X86_CR4_PAE
;
995 /* Setup VMCB for Nested Paging */
996 control
->nested_ctl
= 1;
997 clr_intercept(svm
, INTERCEPT_TASK_SWITCH
);
998 clr_intercept(svm
, INTERCEPT_INVLPG
);
999 clr_exception_intercept(svm
, PF_VECTOR
);
1000 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1001 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1002 save
->g_pat
= 0x0007040600070406ULL
;
1006 force_new_asid(&svm
->vcpu
);
1008 svm
->nested
.vmcb
= 0;
1009 svm
->vcpu
.arch
.hflags
= 0;
1011 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1012 control
->pause_filter_count
= 3000;
1013 set_intercept(svm
, INTERCEPT_PAUSE
);
1016 mark_all_dirty(svm
->vmcb
);
1021 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1023 struct vcpu_svm
*svm
= to_svm(vcpu
);
1027 if (!kvm_vcpu_is_bsp(vcpu
)) {
1028 kvm_rip_write(vcpu
, 0);
1029 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1030 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1032 vcpu
->arch
.regs_avail
= ~0;
1033 vcpu
->arch
.regs_dirty
= ~0;
1038 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1040 struct vcpu_svm
*svm
;
1042 struct page
*msrpm_pages
;
1043 struct page
*hsave_page
;
1044 struct page
*nested_msrpm_pages
;
1047 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1053 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1058 page
= alloc_page(GFP_KERNEL
);
1062 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1066 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1067 if (!nested_msrpm_pages
)
1070 hsave_page
= alloc_page(GFP_KERNEL
);
1074 svm
->nested
.hsave
= page_address(hsave_page
);
1076 svm
->msrpm
= page_address(msrpm_pages
);
1077 svm_vcpu_init_msrpm(svm
->msrpm
);
1079 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1080 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1082 svm
->vmcb
= page_address(page
);
1083 clear_page(svm
->vmcb
);
1084 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1085 svm
->asid_generation
= 0;
1087 kvm_write_tsc(&svm
->vcpu
, 0);
1089 err
= fx_init(&svm
->vcpu
);
1093 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1094 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1095 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1100 __free_page(hsave_page
);
1102 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1104 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1108 kvm_vcpu_uninit(&svm
->vcpu
);
1110 kmem_cache_free(kvm_vcpu_cache
, svm
);
1112 return ERR_PTR(err
);
1115 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1117 struct vcpu_svm
*svm
= to_svm(vcpu
);
1119 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1120 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1121 __free_page(virt_to_page(svm
->nested
.hsave
));
1122 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1123 kvm_vcpu_uninit(vcpu
);
1124 kmem_cache_free(kvm_vcpu_cache
, svm
);
1127 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1129 struct vcpu_svm
*svm
= to_svm(vcpu
);
1132 if (unlikely(cpu
!= vcpu
->cpu
)) {
1133 svm
->asid_generation
= 0;
1134 mark_all_dirty(svm
->vmcb
);
1137 #ifdef CONFIG_X86_64
1138 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1140 savesegment(fs
, svm
->host
.fs
);
1141 savesegment(gs
, svm
->host
.gs
);
1142 svm
->host
.ldt
= kvm_read_ldt();
1144 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1145 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1148 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1150 struct vcpu_svm
*svm
= to_svm(vcpu
);
1153 ++vcpu
->stat
.host_state_reload
;
1154 kvm_load_ldt(svm
->host
.ldt
);
1155 #ifdef CONFIG_X86_64
1156 loadsegment(fs
, svm
->host
.fs
);
1157 load_gs_index(svm
->host
.gs
);
1158 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1160 loadsegment(gs
, svm
->host
.gs
);
1162 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1163 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1166 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1168 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1171 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1173 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1176 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1179 case VCPU_EXREG_PDPTR
:
1180 BUG_ON(!npt_enabled
);
1181 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, vcpu
->arch
.cr3
);
1188 static void svm_set_vintr(struct vcpu_svm
*svm
)
1190 set_intercept(svm
, INTERCEPT_VINTR
);
1193 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1195 clr_intercept(svm
, INTERCEPT_VINTR
);
1198 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1200 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1203 case VCPU_SREG_CS
: return &save
->cs
;
1204 case VCPU_SREG_DS
: return &save
->ds
;
1205 case VCPU_SREG_ES
: return &save
->es
;
1206 case VCPU_SREG_FS
: return &save
->fs
;
1207 case VCPU_SREG_GS
: return &save
->gs
;
1208 case VCPU_SREG_SS
: return &save
->ss
;
1209 case VCPU_SREG_TR
: return &save
->tr
;
1210 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1216 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1218 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1223 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1224 struct kvm_segment
*var
, int seg
)
1226 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1228 var
->base
= s
->base
;
1229 var
->limit
= s
->limit
;
1230 var
->selector
= s
->selector
;
1231 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1232 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1233 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1234 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1235 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1236 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1237 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1238 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1241 * AMD's VMCB does not have an explicit unusable field, so emulate it
1242 * for cross vendor migration purposes by "not present"
1244 var
->unusable
= !var
->present
|| (var
->type
== 0);
1249 * SVM always stores 0 for the 'G' bit in the CS selector in
1250 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1251 * Intel's VMENTRY has a check on the 'G' bit.
1253 var
->g
= s
->limit
> 0xfffff;
1257 * Work around a bug where the busy flag in the tr selector
1267 * The accessed bit must always be set in the segment
1268 * descriptor cache, although it can be cleared in the
1269 * descriptor, the cached bit always remains at 1. Since
1270 * Intel has a check on this, set it here to support
1271 * cross-vendor migration.
1278 * On AMD CPUs sometimes the DB bit in the segment
1279 * descriptor is left as 1, although the whole segment has
1280 * been made unusable. Clear it here to pass an Intel VMX
1281 * entry check when cross vendor migrating.
1289 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1291 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1296 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1298 struct vcpu_svm
*svm
= to_svm(vcpu
);
1300 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1301 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1304 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1306 struct vcpu_svm
*svm
= to_svm(vcpu
);
1308 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1309 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1310 mark_dirty(svm
->vmcb
, VMCB_DT
);
1313 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1315 struct vcpu_svm
*svm
= to_svm(vcpu
);
1317 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1318 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1321 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1323 struct vcpu_svm
*svm
= to_svm(vcpu
);
1325 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1326 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1327 mark_dirty(svm
->vmcb
, VMCB_DT
);
1330 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1334 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1338 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1340 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1341 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1343 if (!svm
->vcpu
.fpu_active
)
1344 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1346 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1347 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1349 mark_dirty(svm
->vmcb
, VMCB_CR
);
1351 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1352 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1353 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1355 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1356 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1360 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1362 struct vcpu_svm
*svm
= to_svm(vcpu
);
1364 if (is_guest_mode(vcpu
)) {
1366 * We are here because we run in nested mode, the host kvm
1367 * intercepts cr0 writes but the l1 hypervisor does not.
1368 * But the L1 hypervisor may intercept selective cr0 writes.
1369 * This needs to be checked here.
1371 unsigned long old
, new;
1373 /* Remove bits that would trigger a real cr0 write intercept */
1374 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1375 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1378 /* cr0 write with ts and mp unchanged */
1379 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1380 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1381 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1382 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1383 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1389 #ifdef CONFIG_X86_64
1390 if (vcpu
->arch
.efer
& EFER_LME
) {
1391 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1392 vcpu
->arch
.efer
|= EFER_LMA
;
1393 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1396 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1397 vcpu
->arch
.efer
&= ~EFER_LMA
;
1398 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1402 vcpu
->arch
.cr0
= cr0
;
1405 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1407 if (!vcpu
->fpu_active
)
1410 * re-enable caching here because the QEMU bios
1411 * does not do it - this results in some delay at
1414 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1415 svm
->vmcb
->save
.cr0
= cr0
;
1416 mark_dirty(svm
->vmcb
, VMCB_CR
);
1417 update_cr0_intercept(svm
);
1420 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1422 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1423 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1425 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1426 force_new_asid(vcpu
);
1428 vcpu
->arch
.cr4
= cr4
;
1431 cr4
|= host_cr4_mce
;
1432 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1433 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1436 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1437 struct kvm_segment
*var
, int seg
)
1439 struct vcpu_svm
*svm
= to_svm(vcpu
);
1440 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1442 s
->base
= var
->base
;
1443 s
->limit
= var
->limit
;
1444 s
->selector
= var
->selector
;
1448 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1449 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1450 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1451 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1452 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1453 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1454 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1455 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1457 if (seg
== VCPU_SREG_CS
)
1459 = (svm
->vmcb
->save
.cs
.attrib
1460 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1462 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1465 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1467 struct vcpu_svm
*svm
= to_svm(vcpu
);
1469 clr_exception_intercept(svm
, DB_VECTOR
);
1470 clr_exception_intercept(svm
, BP_VECTOR
);
1472 if (svm
->nmi_singlestep
)
1473 set_exception_intercept(svm
, DB_VECTOR
);
1475 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1476 if (vcpu
->guest_debug
&
1477 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1478 set_exception_intercept(svm
, DB_VECTOR
);
1479 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1480 set_exception_intercept(svm
, BP_VECTOR
);
1482 vcpu
->guest_debug
= 0;
1485 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1487 struct vcpu_svm
*svm
= to_svm(vcpu
);
1489 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1490 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1492 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1494 mark_dirty(svm
->vmcb
, VMCB_DR
);
1496 update_db_intercept(vcpu
);
1499 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1501 if (sd
->next_asid
> sd
->max_asid
) {
1502 ++sd
->asid_generation
;
1504 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1507 svm
->asid_generation
= sd
->asid_generation
;
1508 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1510 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1513 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1515 struct vcpu_svm
*svm
= to_svm(vcpu
);
1517 svm
->vmcb
->save
.dr7
= value
;
1518 mark_dirty(svm
->vmcb
, VMCB_DR
);
1521 static int pf_interception(struct vcpu_svm
*svm
)
1523 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1527 switch (svm
->apf_reason
) {
1529 error_code
= svm
->vmcb
->control
.exit_info_1
;
1531 trace_kvm_page_fault(fault_address
, error_code
);
1532 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1533 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1534 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1536 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1537 svm
->apf_reason
= 0;
1538 local_irq_disable();
1539 kvm_async_pf_task_wait(fault_address
);
1542 case KVM_PV_REASON_PAGE_READY
:
1543 svm
->apf_reason
= 0;
1544 local_irq_disable();
1545 kvm_async_pf_task_wake(fault_address
);
1552 static int db_interception(struct vcpu_svm
*svm
)
1554 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1556 if (!(svm
->vcpu
.guest_debug
&
1557 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1558 !svm
->nmi_singlestep
) {
1559 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1563 if (svm
->nmi_singlestep
) {
1564 svm
->nmi_singlestep
= false;
1565 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1566 svm
->vmcb
->save
.rflags
&=
1567 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1568 update_db_intercept(&svm
->vcpu
);
1571 if (svm
->vcpu
.guest_debug
&
1572 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1573 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1574 kvm_run
->debug
.arch
.pc
=
1575 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1576 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1583 static int bp_interception(struct vcpu_svm
*svm
)
1585 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1587 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1588 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1589 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1593 static int ud_interception(struct vcpu_svm
*svm
)
1597 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1598 if (er
!= EMULATE_DONE
)
1599 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1603 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1605 struct vcpu_svm
*svm
= to_svm(vcpu
);
1607 clr_exception_intercept(svm
, NM_VECTOR
);
1609 svm
->vcpu
.fpu_active
= 1;
1610 update_cr0_intercept(svm
);
1613 static int nm_interception(struct vcpu_svm
*svm
)
1615 svm_fpu_activate(&svm
->vcpu
);
1619 static bool is_erratum_383(void)
1624 if (!erratum_383_found
)
1627 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1631 /* Bit 62 may or may not be set for this mce */
1632 value
&= ~(1ULL << 62);
1634 if (value
!= 0xb600000000010015ULL
)
1637 /* Clear MCi_STATUS registers */
1638 for (i
= 0; i
< 6; ++i
)
1639 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1641 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1645 value
&= ~(1ULL << 2);
1646 low
= lower_32_bits(value
);
1647 high
= upper_32_bits(value
);
1649 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1652 /* Flush tlb to evict multi-match entries */
1658 static void svm_handle_mce(struct vcpu_svm
*svm
)
1660 if (is_erratum_383()) {
1662 * Erratum 383 triggered. Guest state is corrupt so kill the
1665 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1667 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1673 * On an #MC intercept the MCE handler is not called automatically in
1674 * the host. So do it by hand here.
1678 /* not sure if we ever come back to this point */
1683 static int mc_interception(struct vcpu_svm
*svm
)
1688 static int shutdown_interception(struct vcpu_svm
*svm
)
1690 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1693 * VMCB is undefined after a SHUTDOWN intercept
1694 * so reinitialize it.
1696 clear_page(svm
->vmcb
);
1699 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1703 static int io_interception(struct vcpu_svm
*svm
)
1705 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1706 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1707 int size
, in
, string
;
1710 ++svm
->vcpu
.stat
.io_exits
;
1711 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1712 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1714 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1716 port
= io_info
>> 16;
1717 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1718 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1719 skip_emulated_instruction(&svm
->vcpu
);
1721 return kvm_fast_pio_out(vcpu
, size
, port
);
1724 static int nmi_interception(struct vcpu_svm
*svm
)
1729 static int intr_interception(struct vcpu_svm
*svm
)
1731 ++svm
->vcpu
.stat
.irq_exits
;
1735 static int nop_on_interception(struct vcpu_svm
*svm
)
1740 static int halt_interception(struct vcpu_svm
*svm
)
1742 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1743 skip_emulated_instruction(&svm
->vcpu
);
1744 return kvm_emulate_halt(&svm
->vcpu
);
1747 static int vmmcall_interception(struct vcpu_svm
*svm
)
1749 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1750 skip_emulated_instruction(&svm
->vcpu
);
1751 kvm_emulate_hypercall(&svm
->vcpu
);
1755 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1757 struct vcpu_svm
*svm
= to_svm(vcpu
);
1759 return svm
->nested
.nested_cr3
;
1762 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1765 struct vcpu_svm
*svm
= to_svm(vcpu
);
1767 svm
->vmcb
->control
.nested_cr3
= root
;
1768 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1769 force_new_asid(vcpu
);
1772 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1773 struct x86_exception
*fault
)
1775 struct vcpu_svm
*svm
= to_svm(vcpu
);
1777 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1778 svm
->vmcb
->control
.exit_code_hi
= 0;
1779 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1780 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1782 nested_svm_vmexit(svm
);
1785 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1789 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1791 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1792 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1793 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1794 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1795 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1800 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1802 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1805 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1807 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1808 || !is_paging(&svm
->vcpu
)) {
1809 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1813 if (svm
->vmcb
->save
.cpl
) {
1814 kvm_inject_gp(&svm
->vcpu
, 0);
1821 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1822 bool has_error_code
, u32 error_code
)
1826 if (!is_guest_mode(&svm
->vcpu
))
1829 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1830 svm
->vmcb
->control
.exit_code_hi
= 0;
1831 svm
->vmcb
->control
.exit_info_1
= error_code
;
1832 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1834 vmexit
= nested_svm_intercept(svm
);
1835 if (vmexit
== NESTED_EXIT_DONE
)
1836 svm
->nested
.exit_required
= true;
1841 /* This function returns true if it is save to enable the irq window */
1842 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1844 if (!is_guest_mode(&svm
->vcpu
))
1847 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1850 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1854 * if vmexit was already requested (by intercepted exception
1855 * for instance) do not overwrite it with "external interrupt"
1858 if (svm
->nested
.exit_required
)
1861 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1862 svm
->vmcb
->control
.exit_info_1
= 0;
1863 svm
->vmcb
->control
.exit_info_2
= 0;
1865 if (svm
->nested
.intercept
& 1ULL) {
1867 * The #vmexit can't be emulated here directly because this
1868 * code path runs with irqs and preemtion disabled. A
1869 * #vmexit emulation might sleep. Only signal request for
1872 svm
->nested
.exit_required
= true;
1873 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1880 /* This function returns true if it is save to enable the nmi window */
1881 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1883 if (!is_guest_mode(&svm
->vcpu
))
1886 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1889 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1890 svm
->nested
.exit_required
= true;
1895 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1901 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1902 if (is_error_page(page
))
1910 kvm_release_page_clean(page
);
1911 kvm_inject_gp(&svm
->vcpu
, 0);
1916 static void nested_svm_unmap(struct page
*page
)
1919 kvm_release_page_dirty(page
);
1922 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1928 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1929 return NESTED_EXIT_HOST
;
1931 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1932 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1936 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1939 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1942 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1944 u32 offset
, msr
, value
;
1947 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1948 return NESTED_EXIT_HOST
;
1950 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1951 offset
= svm_msrpm_offset(msr
);
1952 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1953 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1955 if (offset
== MSR_INVALID
)
1956 return NESTED_EXIT_DONE
;
1958 /* Offset is in 32 bit units but need in 8 bit units */
1961 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1962 return NESTED_EXIT_DONE
;
1964 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1967 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1969 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1971 switch (exit_code
) {
1974 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1975 return NESTED_EXIT_HOST
;
1977 /* For now we are always handling NPFs when using them */
1979 return NESTED_EXIT_HOST
;
1981 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1982 /* When we're shadowing, trap PFs, but not async PF */
1983 if (!npt_enabled
&& svm
->apf_reason
== 0)
1984 return NESTED_EXIT_HOST
;
1986 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1987 nm_interception(svm
);
1993 return NESTED_EXIT_CONTINUE
;
1997 * If this function returns true, this #vmexit was already handled
1999 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2001 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2002 int vmexit
= NESTED_EXIT_HOST
;
2004 switch (exit_code
) {
2006 vmexit
= nested_svm_exit_handled_msr(svm
);
2009 vmexit
= nested_svm_intercept_ioio(svm
);
2011 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2012 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2013 if (svm
->nested
.intercept_cr
& bit
)
2014 vmexit
= NESTED_EXIT_DONE
;
2017 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2018 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2019 if (svm
->nested
.intercept_dr
& bit
)
2020 vmexit
= NESTED_EXIT_DONE
;
2023 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2024 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2025 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2026 vmexit
= NESTED_EXIT_DONE
;
2027 /* async page fault always cause vmexit */
2028 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2029 svm
->apf_reason
!= 0)
2030 vmexit
= NESTED_EXIT_DONE
;
2033 case SVM_EXIT_ERR
: {
2034 vmexit
= NESTED_EXIT_DONE
;
2038 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2039 if (svm
->nested
.intercept
& exit_bits
)
2040 vmexit
= NESTED_EXIT_DONE
;
2047 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2051 vmexit
= nested_svm_intercept(svm
);
2053 if (vmexit
== NESTED_EXIT_DONE
)
2054 nested_svm_vmexit(svm
);
2059 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2061 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2062 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2064 dst
->intercept_cr
= from
->intercept_cr
;
2065 dst
->intercept_dr
= from
->intercept_dr
;
2066 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2067 dst
->intercept
= from
->intercept
;
2068 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2069 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2070 dst
->tsc_offset
= from
->tsc_offset
;
2071 dst
->asid
= from
->asid
;
2072 dst
->tlb_ctl
= from
->tlb_ctl
;
2073 dst
->int_ctl
= from
->int_ctl
;
2074 dst
->int_vector
= from
->int_vector
;
2075 dst
->int_state
= from
->int_state
;
2076 dst
->exit_code
= from
->exit_code
;
2077 dst
->exit_code_hi
= from
->exit_code_hi
;
2078 dst
->exit_info_1
= from
->exit_info_1
;
2079 dst
->exit_info_2
= from
->exit_info_2
;
2080 dst
->exit_int_info
= from
->exit_int_info
;
2081 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2082 dst
->nested_ctl
= from
->nested_ctl
;
2083 dst
->event_inj
= from
->event_inj
;
2084 dst
->event_inj_err
= from
->event_inj_err
;
2085 dst
->nested_cr3
= from
->nested_cr3
;
2086 dst
->lbr_ctl
= from
->lbr_ctl
;
2089 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2091 struct vmcb
*nested_vmcb
;
2092 struct vmcb
*hsave
= svm
->nested
.hsave
;
2093 struct vmcb
*vmcb
= svm
->vmcb
;
2096 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2097 vmcb
->control
.exit_info_1
,
2098 vmcb
->control
.exit_info_2
,
2099 vmcb
->control
.exit_int_info
,
2100 vmcb
->control
.exit_int_info_err
);
2102 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2106 /* Exit Guest-Mode */
2107 leave_guest_mode(&svm
->vcpu
);
2108 svm
->nested
.vmcb
= 0;
2110 /* Give the current vmcb to the guest */
2113 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2114 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2115 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2116 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2117 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2118 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2119 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2120 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2121 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2122 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2123 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2124 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
2125 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2126 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2127 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2128 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2129 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2130 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2132 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2133 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2134 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2135 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2136 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2137 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2138 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2139 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2140 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2141 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2144 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2145 * to make sure that we do not lose injected events. So check event_inj
2146 * here and copy it to exit_int_info if it is valid.
2147 * Exit_int_info and event_inj can't be both valid because the case
2148 * below only happens on a VMRUN instruction intercept which has
2149 * no valid exit_int_info set.
2151 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2152 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2154 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2155 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2158 nested_vmcb
->control
.tlb_ctl
= 0;
2159 nested_vmcb
->control
.event_inj
= 0;
2160 nested_vmcb
->control
.event_inj_err
= 0;
2162 /* We always set V_INTR_MASKING and remember the old value in hflags */
2163 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2164 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2166 /* Restore the original control entries */
2167 copy_vmcb_control_area(vmcb
, hsave
);
2169 kvm_clear_exception_queue(&svm
->vcpu
);
2170 kvm_clear_interrupt_queue(&svm
->vcpu
);
2172 svm
->nested
.nested_cr3
= 0;
2174 /* Restore selected save entries */
2175 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2176 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2177 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2178 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2179 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2180 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2181 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
2182 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2183 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2184 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2186 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2187 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2189 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2191 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2192 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2193 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2194 svm
->vmcb
->save
.dr7
= 0;
2195 svm
->vmcb
->save
.cpl
= 0;
2196 svm
->vmcb
->control
.exit_int_info
= 0;
2198 mark_all_dirty(svm
->vmcb
);
2200 nested_svm_unmap(page
);
2202 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2203 kvm_mmu_reset_context(&svm
->vcpu
);
2204 kvm_mmu_load(&svm
->vcpu
);
2209 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2212 * This function merges the msr permission bitmaps of kvm and the
2213 * nested vmcb. It is omptimized in that it only merges the parts where
2214 * the kvm msr permission bitmap may contain zero bits
2218 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2221 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2225 if (msrpm_offsets
[i
] == 0xffffffff)
2228 p
= msrpm_offsets
[i
];
2229 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2231 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2234 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2237 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2242 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2244 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2247 if (vmcb
->control
.asid
== 0)
2250 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2256 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2258 struct vmcb
*nested_vmcb
;
2259 struct vmcb
*hsave
= svm
->nested
.hsave
;
2260 struct vmcb
*vmcb
= svm
->vmcb
;
2264 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2266 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2270 if (!nested_vmcb_checks(nested_vmcb
)) {
2271 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2272 nested_vmcb
->control
.exit_code_hi
= 0;
2273 nested_vmcb
->control
.exit_info_1
= 0;
2274 nested_vmcb
->control
.exit_info_2
= 0;
2276 nested_svm_unmap(page
);
2281 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2282 nested_vmcb
->save
.rip
,
2283 nested_vmcb
->control
.int_ctl
,
2284 nested_vmcb
->control
.event_inj
,
2285 nested_vmcb
->control
.nested_ctl
);
2287 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2288 nested_vmcb
->control
.intercept_cr
>> 16,
2289 nested_vmcb
->control
.intercept_exceptions
,
2290 nested_vmcb
->control
.intercept
);
2292 /* Clear internal status */
2293 kvm_clear_exception_queue(&svm
->vcpu
);
2294 kvm_clear_interrupt_queue(&svm
->vcpu
);
2297 * Save the old vmcb, so we don't need to pick what we save, but can
2298 * restore everything when a VMEXIT occurs
2300 hsave
->save
.es
= vmcb
->save
.es
;
2301 hsave
->save
.cs
= vmcb
->save
.cs
;
2302 hsave
->save
.ss
= vmcb
->save
.ss
;
2303 hsave
->save
.ds
= vmcb
->save
.ds
;
2304 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2305 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2306 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2307 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2308 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2309 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2310 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2311 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2312 hsave
->save
.rax
= vmcb
->save
.rax
;
2314 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2316 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2318 copy_vmcb_control_area(hsave
, vmcb
);
2320 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2321 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2323 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2325 if (nested_vmcb
->control
.nested_ctl
) {
2326 kvm_mmu_unload(&svm
->vcpu
);
2327 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2328 nested_svm_init_mmu_context(&svm
->vcpu
);
2331 /* Load the nested guest state */
2332 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2333 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2334 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2335 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2336 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2337 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2338 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2339 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2340 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2341 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2343 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2344 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2346 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2348 /* Guest paging mode is active - reset mmu */
2349 kvm_mmu_reset_context(&svm
->vcpu
);
2351 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2352 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2353 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2354 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2356 /* In case we don't even reach vcpu_run, the fields are not updated */
2357 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2358 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2359 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2360 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2361 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2362 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2364 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2365 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2367 /* cache intercepts */
2368 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2369 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2370 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2371 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2373 force_new_asid(&svm
->vcpu
);
2374 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2375 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2376 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2378 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2380 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2381 /* We only want the cr8 intercept bits of the guest */
2382 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2383 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2386 /* We don't want to see VMMCALLs from a nested guest */
2387 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2389 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2390 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2391 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2392 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2393 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2394 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2396 nested_svm_unmap(page
);
2398 /* Enter Guest-Mode */
2399 enter_guest_mode(&svm
->vcpu
);
2402 * Merge guest and host intercepts - must be called with vcpu in
2403 * guest-mode to take affect here
2405 recalc_intercepts(svm
);
2407 svm
->nested
.vmcb
= vmcb_gpa
;
2411 mark_all_dirty(svm
->vmcb
);
2416 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2418 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2419 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2420 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2421 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2422 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2423 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2424 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2425 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2426 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2427 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2428 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2429 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2432 static int vmload_interception(struct vcpu_svm
*svm
)
2434 struct vmcb
*nested_vmcb
;
2437 if (nested_svm_check_permissions(svm
))
2440 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2441 skip_emulated_instruction(&svm
->vcpu
);
2443 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2447 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2448 nested_svm_unmap(page
);
2453 static int vmsave_interception(struct vcpu_svm
*svm
)
2455 struct vmcb
*nested_vmcb
;
2458 if (nested_svm_check_permissions(svm
))
2461 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2462 skip_emulated_instruction(&svm
->vcpu
);
2464 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2468 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2469 nested_svm_unmap(page
);
2474 static int vmrun_interception(struct vcpu_svm
*svm
)
2476 if (nested_svm_check_permissions(svm
))
2479 /* Save rip after vmrun instruction */
2480 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2482 if (!nested_svm_vmrun(svm
))
2485 if (!nested_svm_vmrun_msrpm(svm
))
2492 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2493 svm
->vmcb
->control
.exit_code_hi
= 0;
2494 svm
->vmcb
->control
.exit_info_1
= 0;
2495 svm
->vmcb
->control
.exit_info_2
= 0;
2497 nested_svm_vmexit(svm
);
2502 static int stgi_interception(struct vcpu_svm
*svm
)
2504 if (nested_svm_check_permissions(svm
))
2507 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2508 skip_emulated_instruction(&svm
->vcpu
);
2509 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2516 static int clgi_interception(struct vcpu_svm
*svm
)
2518 if (nested_svm_check_permissions(svm
))
2521 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2522 skip_emulated_instruction(&svm
->vcpu
);
2526 /* After a CLGI no interrupts should come */
2527 svm_clear_vintr(svm
);
2528 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2530 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2535 static int invlpga_interception(struct vcpu_svm
*svm
)
2537 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2539 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2540 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2542 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2543 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2545 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2546 skip_emulated_instruction(&svm
->vcpu
);
2550 static int skinit_interception(struct vcpu_svm
*svm
)
2552 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2554 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2558 static int invalid_op_interception(struct vcpu_svm
*svm
)
2560 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2564 static int task_switch_interception(struct vcpu_svm
*svm
)
2568 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2569 SVM_EXITINTINFO_TYPE_MASK
;
2570 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2572 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2574 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2575 bool has_error_code
= false;
2578 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2580 if (svm
->vmcb
->control
.exit_info_2
&
2581 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2582 reason
= TASK_SWITCH_IRET
;
2583 else if (svm
->vmcb
->control
.exit_info_2
&
2584 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2585 reason
= TASK_SWITCH_JMP
;
2587 reason
= TASK_SWITCH_GATE
;
2589 reason
= TASK_SWITCH_CALL
;
2591 if (reason
== TASK_SWITCH_GATE
) {
2593 case SVM_EXITINTINFO_TYPE_NMI
:
2594 svm
->vcpu
.arch
.nmi_injected
= false;
2596 case SVM_EXITINTINFO_TYPE_EXEPT
:
2597 if (svm
->vmcb
->control
.exit_info_2
&
2598 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2599 has_error_code
= true;
2601 (u32
)svm
->vmcb
->control
.exit_info_2
;
2603 kvm_clear_exception_queue(&svm
->vcpu
);
2605 case SVM_EXITINTINFO_TYPE_INTR
:
2606 kvm_clear_interrupt_queue(&svm
->vcpu
);
2613 if (reason
!= TASK_SWITCH_GATE
||
2614 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2615 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2616 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2617 skip_emulated_instruction(&svm
->vcpu
);
2619 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2620 has_error_code
, error_code
) == EMULATE_FAIL
) {
2621 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2622 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2623 svm
->vcpu
.run
->internal
.ndata
= 0;
2629 static int cpuid_interception(struct vcpu_svm
*svm
)
2631 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2632 kvm_emulate_cpuid(&svm
->vcpu
);
2636 static int iret_interception(struct vcpu_svm
*svm
)
2638 ++svm
->vcpu
.stat
.nmi_window_exits
;
2639 clr_intercept(svm
, INTERCEPT_IRET
);
2640 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2644 static int invlpg_interception(struct vcpu_svm
*svm
)
2646 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2649 static int emulate_on_interception(struct vcpu_svm
*svm
)
2651 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2654 static int cr0_write_interception(struct vcpu_svm
*svm
)
2656 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2659 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2661 if (svm
->nested
.vmexit_rip
) {
2662 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2663 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2664 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2665 svm
->nested
.vmexit_rip
= 0;
2668 return r
== EMULATE_DONE
;
2671 static int cr8_write_interception(struct vcpu_svm
*svm
)
2673 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2675 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2676 /* instruction emulation calls kvm_set_cr8() */
2677 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2678 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2679 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2682 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2684 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2688 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2690 struct vcpu_svm
*svm
= to_svm(vcpu
);
2693 case MSR_IA32_TSC
: {
2694 struct vmcb
*vmcb
= get_host_vmcb(svm
);
2696 *data
= vmcb
->control
.tsc_offset
+ native_read_tsc();
2700 *data
= svm
->vmcb
->save
.star
;
2702 #ifdef CONFIG_X86_64
2704 *data
= svm
->vmcb
->save
.lstar
;
2707 *data
= svm
->vmcb
->save
.cstar
;
2709 case MSR_KERNEL_GS_BASE
:
2710 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2712 case MSR_SYSCALL_MASK
:
2713 *data
= svm
->vmcb
->save
.sfmask
;
2716 case MSR_IA32_SYSENTER_CS
:
2717 *data
= svm
->vmcb
->save
.sysenter_cs
;
2719 case MSR_IA32_SYSENTER_EIP
:
2720 *data
= svm
->sysenter_eip
;
2722 case MSR_IA32_SYSENTER_ESP
:
2723 *data
= svm
->sysenter_esp
;
2726 * Nobody will change the following 5 values in the VMCB so we can
2727 * safely return them on rdmsr. They will always be 0 until LBRV is
2730 case MSR_IA32_DEBUGCTLMSR
:
2731 *data
= svm
->vmcb
->save
.dbgctl
;
2733 case MSR_IA32_LASTBRANCHFROMIP
:
2734 *data
= svm
->vmcb
->save
.br_from
;
2736 case MSR_IA32_LASTBRANCHTOIP
:
2737 *data
= svm
->vmcb
->save
.br_to
;
2739 case MSR_IA32_LASTINTFROMIP
:
2740 *data
= svm
->vmcb
->save
.last_excp_from
;
2742 case MSR_IA32_LASTINTTOIP
:
2743 *data
= svm
->vmcb
->save
.last_excp_to
;
2745 case MSR_VM_HSAVE_PA
:
2746 *data
= svm
->nested
.hsave_msr
;
2749 *data
= svm
->nested
.vm_cr_msr
;
2751 case MSR_IA32_UCODE_REV
:
2755 return kvm_get_msr_common(vcpu
, ecx
, data
);
2760 static int rdmsr_interception(struct vcpu_svm
*svm
)
2762 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2765 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2766 trace_kvm_msr_read_ex(ecx
);
2767 kvm_inject_gp(&svm
->vcpu
, 0);
2769 trace_kvm_msr_read(ecx
, data
);
2771 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2772 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2773 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2774 skip_emulated_instruction(&svm
->vcpu
);
2779 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2781 struct vcpu_svm
*svm
= to_svm(vcpu
);
2782 int svm_dis
, chg_mask
;
2784 if (data
& ~SVM_VM_CR_VALID_MASK
)
2787 chg_mask
= SVM_VM_CR_VALID_MASK
;
2789 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2790 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2792 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2793 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2795 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2797 /* check for svm_disable while efer.svme is set */
2798 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2804 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2806 struct vcpu_svm
*svm
= to_svm(vcpu
);
2810 kvm_write_tsc(vcpu
, data
);
2813 svm
->vmcb
->save
.star
= data
;
2815 #ifdef CONFIG_X86_64
2817 svm
->vmcb
->save
.lstar
= data
;
2820 svm
->vmcb
->save
.cstar
= data
;
2822 case MSR_KERNEL_GS_BASE
:
2823 svm
->vmcb
->save
.kernel_gs_base
= data
;
2825 case MSR_SYSCALL_MASK
:
2826 svm
->vmcb
->save
.sfmask
= data
;
2829 case MSR_IA32_SYSENTER_CS
:
2830 svm
->vmcb
->save
.sysenter_cs
= data
;
2832 case MSR_IA32_SYSENTER_EIP
:
2833 svm
->sysenter_eip
= data
;
2834 svm
->vmcb
->save
.sysenter_eip
= data
;
2836 case MSR_IA32_SYSENTER_ESP
:
2837 svm
->sysenter_esp
= data
;
2838 svm
->vmcb
->save
.sysenter_esp
= data
;
2840 case MSR_IA32_DEBUGCTLMSR
:
2841 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2842 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2846 if (data
& DEBUGCTL_RESERVED_BITS
)
2849 svm
->vmcb
->save
.dbgctl
= data
;
2850 if (data
& (1ULL<<0))
2851 svm_enable_lbrv(svm
);
2853 svm_disable_lbrv(svm
);
2855 case MSR_VM_HSAVE_PA
:
2856 svm
->nested
.hsave_msr
= data
;
2859 return svm_set_vm_cr(vcpu
, data
);
2861 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2864 return kvm_set_msr_common(vcpu
, ecx
, data
);
2869 static int wrmsr_interception(struct vcpu_svm
*svm
)
2871 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2872 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2873 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2876 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2877 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2878 trace_kvm_msr_write_ex(ecx
, data
);
2879 kvm_inject_gp(&svm
->vcpu
, 0);
2881 trace_kvm_msr_write(ecx
, data
);
2882 skip_emulated_instruction(&svm
->vcpu
);
2887 static int msr_interception(struct vcpu_svm
*svm
)
2889 if (svm
->vmcb
->control
.exit_info_1
)
2890 return wrmsr_interception(svm
);
2892 return rdmsr_interception(svm
);
2895 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2897 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2899 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2900 svm_clear_vintr(svm
);
2901 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2902 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2904 * If the user space waits to inject interrupts, exit as soon as
2907 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2908 kvm_run
->request_interrupt_window
&&
2909 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2910 ++svm
->vcpu
.stat
.irq_window_exits
;
2911 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2918 static int pause_interception(struct vcpu_svm
*svm
)
2920 kvm_vcpu_on_spin(&(svm
->vcpu
));
2924 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2925 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2926 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2927 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2928 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2929 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2930 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
2931 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2932 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2933 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2934 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2935 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2936 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2937 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2938 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2939 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2940 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2941 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2942 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2943 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2944 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2945 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2946 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2947 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2948 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2949 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2950 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2951 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2952 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2953 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2954 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2955 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2956 [SVM_EXIT_INTR
] = intr_interception
,
2957 [SVM_EXIT_NMI
] = nmi_interception
,
2958 [SVM_EXIT_SMI
] = nop_on_interception
,
2959 [SVM_EXIT_INIT
] = nop_on_interception
,
2960 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2961 [SVM_EXIT_CPUID
] = cpuid_interception
,
2962 [SVM_EXIT_IRET
] = iret_interception
,
2963 [SVM_EXIT_INVD
] = emulate_on_interception
,
2964 [SVM_EXIT_PAUSE
] = pause_interception
,
2965 [SVM_EXIT_HLT
] = halt_interception
,
2966 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2967 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2968 [SVM_EXIT_IOIO
] = io_interception
,
2969 [SVM_EXIT_MSR
] = msr_interception
,
2970 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2971 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2972 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2973 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2974 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2975 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2976 [SVM_EXIT_STGI
] = stgi_interception
,
2977 [SVM_EXIT_CLGI
] = clgi_interception
,
2978 [SVM_EXIT_SKINIT
] = skinit_interception
,
2979 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2980 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2981 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2982 [SVM_EXIT_NPF
] = pf_interception
,
2985 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2987 struct vcpu_svm
*svm
= to_svm(vcpu
);
2988 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2989 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2991 pr_err("VMCB Control Area:\n");
2992 pr_err("cr_read: %04x\n", control
->intercept_cr
& 0xffff);
2993 pr_err("cr_write: %04x\n", control
->intercept_cr
>> 16);
2994 pr_err("dr_read: %04x\n", control
->intercept_dr
& 0xffff);
2995 pr_err("dr_write: %04x\n", control
->intercept_dr
>> 16);
2996 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
2997 pr_err("intercepts: %016llx\n", control
->intercept
);
2998 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
2999 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
3000 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
3001 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
3002 pr_err("asid: %d\n", control
->asid
);
3003 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
3004 pr_err("int_ctl: %08x\n", control
->int_ctl
);
3005 pr_err("int_vector: %08x\n", control
->int_vector
);
3006 pr_err("int_state: %08x\n", control
->int_state
);
3007 pr_err("exit_code: %08x\n", control
->exit_code
);
3008 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
3009 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
3010 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
3011 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
3012 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
3013 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
3014 pr_err("event_inj: %08x\n", control
->event_inj
);
3015 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
3016 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
3017 pr_err("next_rip: %016llx\n", control
->next_rip
);
3018 pr_err("VMCB State Save Area:\n");
3019 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3020 save
->es
.selector
, save
->es
.attrib
,
3021 save
->es
.limit
, save
->es
.base
);
3022 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3023 save
->cs
.selector
, save
->cs
.attrib
,
3024 save
->cs
.limit
, save
->cs
.base
);
3025 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3026 save
->ss
.selector
, save
->ss
.attrib
,
3027 save
->ss
.limit
, save
->ss
.base
);
3028 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3029 save
->ds
.selector
, save
->ds
.attrib
,
3030 save
->ds
.limit
, save
->ds
.base
);
3031 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3032 save
->fs
.selector
, save
->fs
.attrib
,
3033 save
->fs
.limit
, save
->fs
.base
);
3034 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3035 save
->gs
.selector
, save
->gs
.attrib
,
3036 save
->gs
.limit
, save
->gs
.base
);
3037 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3038 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3039 save
->gdtr
.limit
, save
->gdtr
.base
);
3040 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3041 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3042 save
->ldtr
.limit
, save
->ldtr
.base
);
3043 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3044 save
->idtr
.selector
, save
->idtr
.attrib
,
3045 save
->idtr
.limit
, save
->idtr
.base
);
3046 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3047 save
->tr
.selector
, save
->tr
.attrib
,
3048 save
->tr
.limit
, save
->tr
.base
);
3049 pr_err("cpl: %d efer: %016llx\n",
3050 save
->cpl
, save
->efer
);
3051 pr_err("cr0: %016llx cr2: %016llx\n",
3052 save
->cr0
, save
->cr2
);
3053 pr_err("cr3: %016llx cr4: %016llx\n",
3054 save
->cr3
, save
->cr4
);
3055 pr_err("dr6: %016llx dr7: %016llx\n",
3056 save
->dr6
, save
->dr7
);
3057 pr_err("rip: %016llx rflags: %016llx\n",
3058 save
->rip
, save
->rflags
);
3059 pr_err("rsp: %016llx rax: %016llx\n",
3060 save
->rsp
, save
->rax
);
3061 pr_err("star: %016llx lstar: %016llx\n",
3062 save
->star
, save
->lstar
);
3063 pr_err("cstar: %016llx sfmask: %016llx\n",
3064 save
->cstar
, save
->sfmask
);
3065 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3066 save
->kernel_gs_base
, save
->sysenter_cs
);
3067 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3068 save
->sysenter_esp
, save
->sysenter_eip
);
3069 pr_err("gpat: %016llx dbgctl: %016llx\n",
3070 save
->g_pat
, save
->dbgctl
);
3071 pr_err("br_from: %016llx br_to: %016llx\n",
3072 save
->br_from
, save
->br_to
);
3073 pr_err("excp_from: %016llx excp_to: %016llx\n",
3074 save
->last_excp_from
, save
->last_excp_to
);
3078 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3080 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3082 *info1
= control
->exit_info_1
;
3083 *info2
= control
->exit_info_2
;
3086 static int handle_exit(struct kvm_vcpu
*vcpu
)
3088 struct vcpu_svm
*svm
= to_svm(vcpu
);
3089 struct kvm_run
*kvm_run
= vcpu
->run
;
3090 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3092 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3094 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3095 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3097 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3099 if (unlikely(svm
->nested
.exit_required
)) {
3100 nested_svm_vmexit(svm
);
3101 svm
->nested
.exit_required
= false;
3106 if (is_guest_mode(vcpu
)) {
3109 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3110 svm
->vmcb
->control
.exit_info_1
,
3111 svm
->vmcb
->control
.exit_info_2
,
3112 svm
->vmcb
->control
.exit_int_info
,
3113 svm
->vmcb
->control
.exit_int_info_err
);
3115 vmexit
= nested_svm_exit_special(svm
);
3117 if (vmexit
== NESTED_EXIT_CONTINUE
)
3118 vmexit
= nested_svm_exit_handled(svm
);
3120 if (vmexit
== NESTED_EXIT_DONE
)
3124 svm_complete_interrupts(svm
);
3126 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3127 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3128 kvm_run
->fail_entry
.hardware_entry_failure_reason
3129 = svm
->vmcb
->control
.exit_code
;
3130 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3135 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3136 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3137 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3138 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3139 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3141 __func__
, svm
->vmcb
->control
.exit_int_info
,
3144 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3145 || !svm_exit_handlers
[exit_code
]) {
3146 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3147 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3151 return svm_exit_handlers
[exit_code
](svm
);
3154 static void reload_tss(struct kvm_vcpu
*vcpu
)
3156 int cpu
= raw_smp_processor_id();
3158 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3159 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3163 static void pre_svm_run(struct vcpu_svm
*svm
)
3165 int cpu
= raw_smp_processor_id();
3167 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3169 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3170 /* FIXME: handle wraparound of asid_generation */
3171 if (svm
->asid_generation
!= sd
->asid_generation
)
3175 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3177 struct vcpu_svm
*svm
= to_svm(vcpu
);
3179 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3180 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3181 set_intercept(svm
, INTERCEPT_IRET
);
3182 ++vcpu
->stat
.nmi_injections
;
3185 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3187 struct vmcb_control_area
*control
;
3189 control
= &svm
->vmcb
->control
;
3190 control
->int_vector
= irq
;
3191 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3192 control
->int_ctl
|= V_IRQ_MASK
|
3193 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3194 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3197 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3199 struct vcpu_svm
*svm
= to_svm(vcpu
);
3201 BUG_ON(!(gif_set(svm
)));
3203 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3204 ++vcpu
->stat
.irq_injections
;
3206 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3207 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3210 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3212 struct vcpu_svm
*svm
= to_svm(vcpu
);
3214 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3221 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3224 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3226 struct vcpu_svm
*svm
= to_svm(vcpu
);
3227 struct vmcb
*vmcb
= svm
->vmcb
;
3229 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3230 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3231 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3236 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3238 struct vcpu_svm
*svm
= to_svm(vcpu
);
3240 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3243 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3245 struct vcpu_svm
*svm
= to_svm(vcpu
);
3248 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3249 set_intercept(svm
, INTERCEPT_IRET
);
3251 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3252 clr_intercept(svm
, INTERCEPT_IRET
);
3256 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3258 struct vcpu_svm
*svm
= to_svm(vcpu
);
3259 struct vmcb
*vmcb
= svm
->vmcb
;
3262 if (!gif_set(svm
) ||
3263 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3266 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3268 if (is_guest_mode(vcpu
))
3269 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3274 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3276 struct vcpu_svm
*svm
= to_svm(vcpu
);
3279 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3280 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3281 * get that intercept, this function will be called again though and
3282 * we'll get the vintr intercept.
3284 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3286 svm_inject_irq(svm
, 0x0);
3290 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3292 struct vcpu_svm
*svm
= to_svm(vcpu
);
3294 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3296 return; /* IRET will cause a vm exit */
3299 * Something prevents NMI from been injected. Single step over possible
3300 * problem (IRET or exception injection or interrupt shadow)
3302 svm
->nmi_singlestep
= true;
3303 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3304 update_db_intercept(vcpu
);
3307 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3312 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3314 force_new_asid(vcpu
);
3317 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3321 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3323 struct vcpu_svm
*svm
= to_svm(vcpu
);
3325 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3328 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3329 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3330 kvm_set_cr8(vcpu
, cr8
);
3334 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3336 struct vcpu_svm
*svm
= to_svm(vcpu
);
3339 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3342 cr8
= kvm_get_cr8(vcpu
);
3343 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3344 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3347 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3351 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3352 unsigned int3_injected
= svm
->int3_injected
;
3354 svm
->int3_injected
= 0;
3356 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) {
3357 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3358 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3361 svm
->vcpu
.arch
.nmi_injected
= false;
3362 kvm_clear_exception_queue(&svm
->vcpu
);
3363 kvm_clear_interrupt_queue(&svm
->vcpu
);
3365 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3368 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3370 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3371 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3374 case SVM_EXITINTINFO_TYPE_NMI
:
3375 svm
->vcpu
.arch
.nmi_injected
= true;
3377 case SVM_EXITINTINFO_TYPE_EXEPT
:
3379 * In case of software exceptions, do not reinject the vector,
3380 * but re-execute the instruction instead. Rewind RIP first
3381 * if we emulated INT3 before.
3383 if (kvm_exception_is_soft(vector
)) {
3384 if (vector
== BP_VECTOR
&& int3_injected
&&
3385 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3386 kvm_rip_write(&svm
->vcpu
,
3387 kvm_rip_read(&svm
->vcpu
) -
3391 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3392 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3393 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3396 kvm_requeue_exception(&svm
->vcpu
, vector
);
3398 case SVM_EXITINTINFO_TYPE_INTR
:
3399 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3406 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3408 struct vcpu_svm
*svm
= to_svm(vcpu
);
3409 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3411 control
->exit_int_info
= control
->event_inj
;
3412 control
->exit_int_info_err
= control
->event_inj_err
;
3413 control
->event_inj
= 0;
3414 svm_complete_interrupts(svm
);
3417 #ifdef CONFIG_X86_64
3423 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3425 struct vcpu_svm
*svm
= to_svm(vcpu
);
3427 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3428 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3429 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3432 * A vmexit emulation is required before the vcpu can be executed
3435 if (unlikely(svm
->nested
.exit_required
))
3440 sync_lapic_to_cr8(vcpu
);
3442 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3449 "push %%"R
"bp; \n\t"
3450 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3451 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3452 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3453 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3454 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3455 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3456 #ifdef CONFIG_X86_64
3457 "mov %c[r8](%[svm]), %%r8 \n\t"
3458 "mov %c[r9](%[svm]), %%r9 \n\t"
3459 "mov %c[r10](%[svm]), %%r10 \n\t"
3460 "mov %c[r11](%[svm]), %%r11 \n\t"
3461 "mov %c[r12](%[svm]), %%r12 \n\t"
3462 "mov %c[r13](%[svm]), %%r13 \n\t"
3463 "mov %c[r14](%[svm]), %%r14 \n\t"
3464 "mov %c[r15](%[svm]), %%r15 \n\t"
3467 /* Enter guest mode */
3469 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3470 __ex(SVM_VMLOAD
) "\n\t"
3471 __ex(SVM_VMRUN
) "\n\t"
3472 __ex(SVM_VMSAVE
) "\n\t"
3475 /* Save guest registers, load host registers */
3476 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3477 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3478 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3479 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3480 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3481 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3482 #ifdef CONFIG_X86_64
3483 "mov %%r8, %c[r8](%[svm]) \n\t"
3484 "mov %%r9, %c[r9](%[svm]) \n\t"
3485 "mov %%r10, %c[r10](%[svm]) \n\t"
3486 "mov %%r11, %c[r11](%[svm]) \n\t"
3487 "mov %%r12, %c[r12](%[svm]) \n\t"
3488 "mov %%r13, %c[r13](%[svm]) \n\t"
3489 "mov %%r14, %c[r14](%[svm]) \n\t"
3490 "mov %%r15, %c[r15](%[svm]) \n\t"
3495 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3496 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3497 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3498 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3499 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3500 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3501 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3502 #ifdef CONFIG_X86_64
3503 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3504 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3505 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3506 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3507 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3508 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3509 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3510 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3513 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3514 #ifdef CONFIG_X86_64
3515 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3519 #ifdef CONFIG_X86_64
3520 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3522 loadsegment(fs
, svm
->host
.fs
);
3527 local_irq_disable();
3531 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3532 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3533 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3534 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3536 sync_cr8_to_lapic(vcpu
);
3540 /* if exit due to PF check for async PF */
3541 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3542 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3545 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3546 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3550 * We need to handle MC intercepts here before the vcpu has a chance to
3551 * change the physical cpu
3553 if (unlikely(svm
->vmcb
->control
.exit_code
==
3554 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3555 svm_handle_mce(svm
);
3557 mark_all_clean(svm
->vmcb
);
3562 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3564 struct vcpu_svm
*svm
= to_svm(vcpu
);
3566 svm
->vmcb
->save
.cr3
= root
;
3567 mark_dirty(svm
->vmcb
, VMCB_CR
);
3568 force_new_asid(vcpu
);
3571 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3573 struct vcpu_svm
*svm
= to_svm(vcpu
);
3575 svm
->vmcb
->control
.nested_cr3
= root
;
3576 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3578 /* Also sync guest cr3 here in case we live migrate */
3579 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3580 mark_dirty(svm
->vmcb
, VMCB_CR
);
3582 force_new_asid(vcpu
);
3585 static int is_disabled(void)
3589 rdmsrl(MSR_VM_CR
, vm_cr
);
3590 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3597 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3600 * Patch in the VMMCALL instruction:
3602 hypercall
[0] = 0x0f;
3603 hypercall
[1] = 0x01;
3604 hypercall
[2] = 0xd9;
3607 static void svm_check_processor_compat(void *rtn
)
3612 static bool svm_cpu_has_accelerated_tpr(void)
3617 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3622 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3626 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3630 /* Mask out xsave bit as long as it is not supported by SVM */
3631 entry
->ecx
&= ~(bit(X86_FEATURE_XSAVE
));
3635 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3638 entry
->eax
= 1; /* SVM revision 1 */
3639 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3640 ASID emulation to nested SVM */
3641 entry
->ecx
= 0; /* Reserved */
3642 entry
->edx
= 0; /* Per default do not support any
3643 additional features */
3645 /* Support next_rip if host supports it */
3646 if (boot_cpu_has(X86_FEATURE_NRIPS
))
3647 entry
->edx
|= SVM_FEATURE_NRIP
;
3649 /* Support NPT for the guest if enabled */
3651 entry
->edx
|= SVM_FEATURE_NPT
;
3657 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3658 { SVM_EXIT_READ_CR0
, "read_cr0" },
3659 { SVM_EXIT_READ_CR3
, "read_cr3" },
3660 { SVM_EXIT_READ_CR4
, "read_cr4" },
3661 { SVM_EXIT_READ_CR8
, "read_cr8" },
3662 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3663 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3664 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3665 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3666 { SVM_EXIT_READ_DR0
, "read_dr0" },
3667 { SVM_EXIT_READ_DR1
, "read_dr1" },
3668 { SVM_EXIT_READ_DR2
, "read_dr2" },
3669 { SVM_EXIT_READ_DR3
, "read_dr3" },
3670 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3671 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3672 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3673 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3674 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3675 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3676 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3677 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3678 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3679 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3680 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3681 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3682 { SVM_EXIT_INTR
, "interrupt" },
3683 { SVM_EXIT_NMI
, "nmi" },
3684 { SVM_EXIT_SMI
, "smi" },
3685 { SVM_EXIT_INIT
, "init" },
3686 { SVM_EXIT_VINTR
, "vintr" },
3687 { SVM_EXIT_CPUID
, "cpuid" },
3688 { SVM_EXIT_INVD
, "invd" },
3689 { SVM_EXIT_HLT
, "hlt" },
3690 { SVM_EXIT_INVLPG
, "invlpg" },
3691 { SVM_EXIT_INVLPGA
, "invlpga" },
3692 { SVM_EXIT_IOIO
, "io" },
3693 { SVM_EXIT_MSR
, "msr" },
3694 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3695 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3696 { SVM_EXIT_VMRUN
, "vmrun" },
3697 { SVM_EXIT_VMMCALL
, "hypercall" },
3698 { SVM_EXIT_VMLOAD
, "vmload" },
3699 { SVM_EXIT_VMSAVE
, "vmsave" },
3700 { SVM_EXIT_STGI
, "stgi" },
3701 { SVM_EXIT_CLGI
, "clgi" },
3702 { SVM_EXIT_SKINIT
, "skinit" },
3703 { SVM_EXIT_WBINVD
, "wbinvd" },
3704 { SVM_EXIT_MONITOR
, "monitor" },
3705 { SVM_EXIT_MWAIT
, "mwait" },
3706 { SVM_EXIT_NPF
, "npf" },
3710 static int svm_get_lpage_level(void)
3712 return PT_PDPE_LEVEL
;
3715 static bool svm_rdtscp_supported(void)
3720 static bool svm_has_wbinvd_exit(void)
3725 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3727 struct vcpu_svm
*svm
= to_svm(vcpu
);
3729 set_exception_intercept(svm
, NM_VECTOR
);
3730 update_cr0_intercept(svm
);
3733 static struct kvm_x86_ops svm_x86_ops
= {
3734 .cpu_has_kvm_support
= has_svm
,
3735 .disabled_by_bios
= is_disabled
,
3736 .hardware_setup
= svm_hardware_setup
,
3737 .hardware_unsetup
= svm_hardware_unsetup
,
3738 .check_processor_compatibility
= svm_check_processor_compat
,
3739 .hardware_enable
= svm_hardware_enable
,
3740 .hardware_disable
= svm_hardware_disable
,
3741 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3743 .vcpu_create
= svm_create_vcpu
,
3744 .vcpu_free
= svm_free_vcpu
,
3745 .vcpu_reset
= svm_vcpu_reset
,
3747 .prepare_guest_switch
= svm_prepare_guest_switch
,
3748 .vcpu_load
= svm_vcpu_load
,
3749 .vcpu_put
= svm_vcpu_put
,
3751 .set_guest_debug
= svm_guest_debug
,
3752 .get_msr
= svm_get_msr
,
3753 .set_msr
= svm_set_msr
,
3754 .get_segment_base
= svm_get_segment_base
,
3755 .get_segment
= svm_get_segment
,
3756 .set_segment
= svm_set_segment
,
3757 .get_cpl
= svm_get_cpl
,
3758 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3759 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3760 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3761 .set_cr0
= svm_set_cr0
,
3762 .set_cr3
= svm_set_cr3
,
3763 .set_cr4
= svm_set_cr4
,
3764 .set_efer
= svm_set_efer
,
3765 .get_idt
= svm_get_idt
,
3766 .set_idt
= svm_set_idt
,
3767 .get_gdt
= svm_get_gdt
,
3768 .set_gdt
= svm_set_gdt
,
3769 .set_dr7
= svm_set_dr7
,
3770 .cache_reg
= svm_cache_reg
,
3771 .get_rflags
= svm_get_rflags
,
3772 .set_rflags
= svm_set_rflags
,
3773 .fpu_activate
= svm_fpu_activate
,
3774 .fpu_deactivate
= svm_fpu_deactivate
,
3776 .tlb_flush
= svm_flush_tlb
,
3778 .run
= svm_vcpu_run
,
3779 .handle_exit
= handle_exit
,
3780 .skip_emulated_instruction
= skip_emulated_instruction
,
3781 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3782 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3783 .patch_hypercall
= svm_patch_hypercall
,
3784 .set_irq
= svm_set_irq
,
3785 .set_nmi
= svm_inject_nmi
,
3786 .queue_exception
= svm_queue_exception
,
3787 .cancel_injection
= svm_cancel_injection
,
3788 .interrupt_allowed
= svm_interrupt_allowed
,
3789 .nmi_allowed
= svm_nmi_allowed
,
3790 .get_nmi_mask
= svm_get_nmi_mask
,
3791 .set_nmi_mask
= svm_set_nmi_mask
,
3792 .enable_nmi_window
= enable_nmi_window
,
3793 .enable_irq_window
= enable_irq_window
,
3794 .update_cr8_intercept
= update_cr8_intercept
,
3796 .set_tss_addr
= svm_set_tss_addr
,
3797 .get_tdp_level
= get_npt_level
,
3798 .get_mt_mask
= svm_get_mt_mask
,
3800 .get_exit_info
= svm_get_exit_info
,
3801 .exit_reasons_str
= svm_exit_reasons_str
,
3803 .get_lpage_level
= svm_get_lpage_level
,
3805 .cpuid_update
= svm_cpuid_update
,
3807 .rdtscp_supported
= svm_rdtscp_supported
,
3809 .set_supported_cpuid
= svm_set_supported_cpuid
,
3811 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3813 .write_tsc_offset
= svm_write_tsc_offset
,
3814 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3816 .set_tdp_cr3
= set_tdp_cr3
,
3819 static int __init
svm_init(void)
3821 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3822 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3825 static void __exit
svm_exit(void)
3830 module_init(svm_init
)
3831 module_exit(svm_exit
)