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KVM: SVM: Add clean-bit for Segements and CPL
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_CR, /* CR0, CR3, CR4, EFER */
196 VMCB_DR, /* DR6, DR7 */
197 VMCB_DT, /* GDT, IDT */
198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
199 VMCB_DIRTY_MAX,
200 };
201
202 /* TPR is always written before VMRUN */
203 #define VMCB_ALWAYS_DIRTY_MASK (1U << VMCB_INTR)
204
205 static inline void mark_all_dirty(struct vmcb *vmcb)
206 {
207 vmcb->control.clean = 0;
208 }
209
210 static inline void mark_all_clean(struct vmcb *vmcb)
211 {
212 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
213 & ~VMCB_ALWAYS_DIRTY_MASK;
214 }
215
216 static inline void mark_dirty(struct vmcb *vmcb, int bit)
217 {
218 vmcb->control.clean &= ~(1 << bit);
219 }
220
221 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
222 {
223 return container_of(vcpu, struct vcpu_svm, vcpu);
224 }
225
226 static void recalc_intercepts(struct vcpu_svm *svm)
227 {
228 struct vmcb_control_area *c, *h;
229 struct nested_state *g;
230
231 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
232
233 if (!is_guest_mode(&svm->vcpu))
234 return;
235
236 c = &svm->vmcb->control;
237 h = &svm->nested.hsave->control;
238 g = &svm->nested;
239
240 c->intercept_cr = h->intercept_cr | g->intercept_cr;
241 c->intercept_dr = h->intercept_dr | g->intercept_dr;
242 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
243 c->intercept = h->intercept | g->intercept;
244 }
245
246 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
247 {
248 if (is_guest_mode(&svm->vcpu))
249 return svm->nested.hsave;
250 else
251 return svm->vmcb;
252 }
253
254 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
255 {
256 struct vmcb *vmcb = get_host_vmcb(svm);
257
258 vmcb->control.intercept_cr |= (1U << bit);
259
260 recalc_intercepts(svm);
261 }
262
263 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
264 {
265 struct vmcb *vmcb = get_host_vmcb(svm);
266
267 vmcb->control.intercept_cr &= ~(1U << bit);
268
269 recalc_intercepts(svm);
270 }
271
272 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
273 {
274 struct vmcb *vmcb = get_host_vmcb(svm);
275
276 return vmcb->control.intercept_cr & (1U << bit);
277 }
278
279 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
280 {
281 struct vmcb *vmcb = get_host_vmcb(svm);
282
283 vmcb->control.intercept_dr |= (1U << bit);
284
285 recalc_intercepts(svm);
286 }
287
288 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
289 {
290 struct vmcb *vmcb = get_host_vmcb(svm);
291
292 vmcb->control.intercept_dr &= ~(1U << bit);
293
294 recalc_intercepts(svm);
295 }
296
297 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
298 {
299 struct vmcb *vmcb = get_host_vmcb(svm);
300
301 vmcb->control.intercept_exceptions |= (1U << bit);
302
303 recalc_intercepts(svm);
304 }
305
306 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
307 {
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept_exceptions &= ~(1U << bit);
311
312 recalc_intercepts(svm);
313 }
314
315 static inline void set_intercept(struct vcpu_svm *svm, int bit)
316 {
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept |= (1ULL << bit);
320
321 recalc_intercepts(svm);
322 }
323
324 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
325 {
326 struct vmcb *vmcb = get_host_vmcb(svm);
327
328 vmcb->control.intercept &= ~(1ULL << bit);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void enable_gif(struct vcpu_svm *svm)
334 {
335 svm->vcpu.arch.hflags |= HF_GIF_MASK;
336 }
337
338 static inline void disable_gif(struct vcpu_svm *svm)
339 {
340 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
341 }
342
343 static inline bool gif_set(struct vcpu_svm *svm)
344 {
345 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
346 }
347
348 static unsigned long iopm_base;
349
350 struct kvm_ldttss_desc {
351 u16 limit0;
352 u16 base0;
353 unsigned base1:8, type:5, dpl:2, p:1;
354 unsigned limit1:4, zero0:3, g:1, base2:8;
355 u32 base3;
356 u32 zero1;
357 } __attribute__((packed));
358
359 struct svm_cpu_data {
360 int cpu;
361
362 u64 asid_generation;
363 u32 max_asid;
364 u32 next_asid;
365 struct kvm_ldttss_desc *tss_desc;
366
367 struct page *save_area;
368 };
369
370 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
371 static uint32_t svm_features;
372
373 struct svm_init_data {
374 int cpu;
375 int r;
376 };
377
378 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
379
380 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
381 #define MSRS_RANGE_SIZE 2048
382 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
383
384 static u32 svm_msrpm_offset(u32 msr)
385 {
386 u32 offset;
387 int i;
388
389 for (i = 0; i < NUM_MSR_MAPS; i++) {
390 if (msr < msrpm_ranges[i] ||
391 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
392 continue;
393
394 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
395 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
396
397 /* Now we have the u8 offset - but need the u32 offset */
398 return offset / 4;
399 }
400
401 /* MSR not in any range */
402 return MSR_INVALID;
403 }
404
405 #define MAX_INST_SIZE 15
406
407 static inline void clgi(void)
408 {
409 asm volatile (__ex(SVM_CLGI));
410 }
411
412 static inline void stgi(void)
413 {
414 asm volatile (__ex(SVM_STGI));
415 }
416
417 static inline void invlpga(unsigned long addr, u32 asid)
418 {
419 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
420 }
421
422 static inline void force_new_asid(struct kvm_vcpu *vcpu)
423 {
424 to_svm(vcpu)->asid_generation--;
425 }
426
427 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
428 {
429 force_new_asid(vcpu);
430 }
431
432 static int get_npt_level(void)
433 {
434 #ifdef CONFIG_X86_64
435 return PT64_ROOT_LEVEL;
436 #else
437 return PT32E_ROOT_LEVEL;
438 #endif
439 }
440
441 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
442 {
443 vcpu->arch.efer = efer;
444 if (!npt_enabled && !(efer & EFER_LMA))
445 efer &= ~EFER_LME;
446
447 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
448 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
449 }
450
451 static int is_external_interrupt(u32 info)
452 {
453 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
454 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
455 }
456
457 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
458 {
459 struct vcpu_svm *svm = to_svm(vcpu);
460 u32 ret = 0;
461
462 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
463 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
464 return ret & mask;
465 }
466
467 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
468 {
469 struct vcpu_svm *svm = to_svm(vcpu);
470
471 if (mask == 0)
472 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
473 else
474 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
475
476 }
477
478 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
479 {
480 struct vcpu_svm *svm = to_svm(vcpu);
481
482 if (svm->vmcb->control.next_rip != 0)
483 svm->next_rip = svm->vmcb->control.next_rip;
484
485 if (!svm->next_rip) {
486 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
487 EMULATE_DONE)
488 printk(KERN_DEBUG "%s: NOP\n", __func__);
489 return;
490 }
491 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
492 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
493 __func__, kvm_rip_read(vcpu), svm->next_rip);
494
495 kvm_rip_write(vcpu, svm->next_rip);
496 svm_set_interrupt_shadow(vcpu, 0);
497 }
498
499 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
500 bool has_error_code, u32 error_code,
501 bool reinject)
502 {
503 struct vcpu_svm *svm = to_svm(vcpu);
504
505 /*
506 * If we are within a nested VM we'd better #VMEXIT and let the guest
507 * handle the exception
508 */
509 if (!reinject &&
510 nested_svm_check_exception(svm, nr, has_error_code, error_code))
511 return;
512
513 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
514 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
515
516 /*
517 * For guest debugging where we have to reinject #BP if some
518 * INT3 is guest-owned:
519 * Emulate nRIP by moving RIP forward. Will fail if injection
520 * raises a fault that is not intercepted. Still better than
521 * failing in all cases.
522 */
523 skip_emulated_instruction(&svm->vcpu);
524 rip = kvm_rip_read(&svm->vcpu);
525 svm->int3_rip = rip + svm->vmcb->save.cs.base;
526 svm->int3_injected = rip - old_rip;
527 }
528
529 svm->vmcb->control.event_inj = nr
530 | SVM_EVTINJ_VALID
531 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
532 | SVM_EVTINJ_TYPE_EXEPT;
533 svm->vmcb->control.event_inj_err = error_code;
534 }
535
536 static void svm_init_erratum_383(void)
537 {
538 u32 low, high;
539 int err;
540 u64 val;
541
542 if (!cpu_has_amd_erratum(amd_erratum_383))
543 return;
544
545 /* Use _safe variants to not break nested virtualization */
546 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
547 if (err)
548 return;
549
550 val |= (1ULL << 47);
551
552 low = lower_32_bits(val);
553 high = upper_32_bits(val);
554
555 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
556
557 erratum_383_found = true;
558 }
559
560 static int has_svm(void)
561 {
562 const char *msg;
563
564 if (!cpu_has_svm(&msg)) {
565 printk(KERN_INFO "has_svm: %s\n", msg);
566 return 0;
567 }
568
569 return 1;
570 }
571
572 static void svm_hardware_disable(void *garbage)
573 {
574 cpu_svm_disable();
575 }
576
577 static int svm_hardware_enable(void *garbage)
578 {
579
580 struct svm_cpu_data *sd;
581 uint64_t efer;
582 struct desc_ptr gdt_descr;
583 struct desc_struct *gdt;
584 int me = raw_smp_processor_id();
585
586 rdmsrl(MSR_EFER, efer);
587 if (efer & EFER_SVME)
588 return -EBUSY;
589
590 if (!has_svm()) {
591 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
592 me);
593 return -EINVAL;
594 }
595 sd = per_cpu(svm_data, me);
596
597 if (!sd) {
598 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
599 me);
600 return -EINVAL;
601 }
602
603 sd->asid_generation = 1;
604 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
605 sd->next_asid = sd->max_asid + 1;
606
607 native_store_gdt(&gdt_descr);
608 gdt = (struct desc_struct *)gdt_descr.address;
609 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
610
611 wrmsrl(MSR_EFER, efer | EFER_SVME);
612
613 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
614
615 svm_init_erratum_383();
616
617 return 0;
618 }
619
620 static void svm_cpu_uninit(int cpu)
621 {
622 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
623
624 if (!sd)
625 return;
626
627 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
628 __free_page(sd->save_area);
629 kfree(sd);
630 }
631
632 static int svm_cpu_init(int cpu)
633 {
634 struct svm_cpu_data *sd;
635 int r;
636
637 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
638 if (!sd)
639 return -ENOMEM;
640 sd->cpu = cpu;
641 sd->save_area = alloc_page(GFP_KERNEL);
642 r = -ENOMEM;
643 if (!sd->save_area)
644 goto err_1;
645
646 per_cpu(svm_data, cpu) = sd;
647
648 return 0;
649
650 err_1:
651 kfree(sd);
652 return r;
653
654 }
655
656 static bool valid_msr_intercept(u32 index)
657 {
658 int i;
659
660 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
661 if (direct_access_msrs[i].index == index)
662 return true;
663
664 return false;
665 }
666
667 static void set_msr_interception(u32 *msrpm, unsigned msr,
668 int read, int write)
669 {
670 u8 bit_read, bit_write;
671 unsigned long tmp;
672 u32 offset;
673
674 /*
675 * If this warning triggers extend the direct_access_msrs list at the
676 * beginning of the file
677 */
678 WARN_ON(!valid_msr_intercept(msr));
679
680 offset = svm_msrpm_offset(msr);
681 bit_read = 2 * (msr & 0x0f);
682 bit_write = 2 * (msr & 0x0f) + 1;
683 tmp = msrpm[offset];
684
685 BUG_ON(offset == MSR_INVALID);
686
687 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
688 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
689
690 msrpm[offset] = tmp;
691 }
692
693 static void svm_vcpu_init_msrpm(u32 *msrpm)
694 {
695 int i;
696
697 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
698
699 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
700 if (!direct_access_msrs[i].always)
701 continue;
702
703 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
704 }
705 }
706
707 static void add_msr_offset(u32 offset)
708 {
709 int i;
710
711 for (i = 0; i < MSRPM_OFFSETS; ++i) {
712
713 /* Offset already in list? */
714 if (msrpm_offsets[i] == offset)
715 return;
716
717 /* Slot used by another offset? */
718 if (msrpm_offsets[i] != MSR_INVALID)
719 continue;
720
721 /* Add offset to list */
722 msrpm_offsets[i] = offset;
723
724 return;
725 }
726
727 /*
728 * If this BUG triggers the msrpm_offsets table has an overflow. Just
729 * increase MSRPM_OFFSETS in this case.
730 */
731 BUG();
732 }
733
734 static void init_msrpm_offsets(void)
735 {
736 int i;
737
738 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
739
740 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
741 u32 offset;
742
743 offset = svm_msrpm_offset(direct_access_msrs[i].index);
744 BUG_ON(offset == MSR_INVALID);
745
746 add_msr_offset(offset);
747 }
748 }
749
750 static void svm_enable_lbrv(struct vcpu_svm *svm)
751 {
752 u32 *msrpm = svm->msrpm;
753
754 svm->vmcb->control.lbr_ctl = 1;
755 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
756 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
757 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
758 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
759 }
760
761 static void svm_disable_lbrv(struct vcpu_svm *svm)
762 {
763 u32 *msrpm = svm->msrpm;
764
765 svm->vmcb->control.lbr_ctl = 0;
766 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
767 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
768 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
769 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
770 }
771
772 static __init int svm_hardware_setup(void)
773 {
774 int cpu;
775 struct page *iopm_pages;
776 void *iopm_va;
777 int r;
778
779 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
780
781 if (!iopm_pages)
782 return -ENOMEM;
783
784 iopm_va = page_address(iopm_pages);
785 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
786 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
787
788 init_msrpm_offsets();
789
790 if (boot_cpu_has(X86_FEATURE_NX))
791 kvm_enable_efer_bits(EFER_NX);
792
793 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
794 kvm_enable_efer_bits(EFER_FFXSR);
795
796 if (nested) {
797 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
798 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
799 }
800
801 for_each_possible_cpu(cpu) {
802 r = svm_cpu_init(cpu);
803 if (r)
804 goto err;
805 }
806
807 svm_features = cpuid_edx(SVM_CPUID_FUNC);
808
809 if (!boot_cpu_has(X86_FEATURE_NPT))
810 npt_enabled = false;
811
812 if (npt_enabled && !npt) {
813 printk(KERN_INFO "kvm: Nested Paging disabled\n");
814 npt_enabled = false;
815 }
816
817 if (npt_enabled) {
818 printk(KERN_INFO "kvm: Nested Paging enabled\n");
819 kvm_enable_tdp();
820 } else
821 kvm_disable_tdp();
822
823 return 0;
824
825 err:
826 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
827 iopm_base = 0;
828 return r;
829 }
830
831 static __exit void svm_hardware_unsetup(void)
832 {
833 int cpu;
834
835 for_each_possible_cpu(cpu)
836 svm_cpu_uninit(cpu);
837
838 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
839 iopm_base = 0;
840 }
841
842 static void init_seg(struct vmcb_seg *seg)
843 {
844 seg->selector = 0;
845 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
846 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
847 seg->limit = 0xffff;
848 seg->base = 0;
849 }
850
851 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
852 {
853 seg->selector = 0;
854 seg->attrib = SVM_SELECTOR_P_MASK | type;
855 seg->limit = 0xffff;
856 seg->base = 0;
857 }
858
859 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
860 {
861 struct vcpu_svm *svm = to_svm(vcpu);
862 u64 g_tsc_offset = 0;
863
864 if (is_guest_mode(vcpu)) {
865 g_tsc_offset = svm->vmcb->control.tsc_offset -
866 svm->nested.hsave->control.tsc_offset;
867 svm->nested.hsave->control.tsc_offset = offset;
868 }
869
870 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
871
872 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
873 }
874
875 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
876 {
877 struct vcpu_svm *svm = to_svm(vcpu);
878
879 svm->vmcb->control.tsc_offset += adjustment;
880 if (is_guest_mode(vcpu))
881 svm->nested.hsave->control.tsc_offset += adjustment;
882 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
883 }
884
885 static void init_vmcb(struct vcpu_svm *svm)
886 {
887 struct vmcb_control_area *control = &svm->vmcb->control;
888 struct vmcb_save_area *save = &svm->vmcb->save;
889
890 svm->vcpu.fpu_active = 1;
891 svm->vcpu.arch.hflags = 0;
892
893 set_cr_intercept(svm, INTERCEPT_CR0_READ);
894 set_cr_intercept(svm, INTERCEPT_CR3_READ);
895 set_cr_intercept(svm, INTERCEPT_CR4_READ);
896 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
897 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
898 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
899 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
900
901 set_dr_intercept(svm, INTERCEPT_DR0_READ);
902 set_dr_intercept(svm, INTERCEPT_DR1_READ);
903 set_dr_intercept(svm, INTERCEPT_DR2_READ);
904 set_dr_intercept(svm, INTERCEPT_DR3_READ);
905 set_dr_intercept(svm, INTERCEPT_DR4_READ);
906 set_dr_intercept(svm, INTERCEPT_DR5_READ);
907 set_dr_intercept(svm, INTERCEPT_DR6_READ);
908 set_dr_intercept(svm, INTERCEPT_DR7_READ);
909
910 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
914 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
915 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
916 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
917 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
918
919 set_exception_intercept(svm, PF_VECTOR);
920 set_exception_intercept(svm, UD_VECTOR);
921 set_exception_intercept(svm, MC_VECTOR);
922
923 set_intercept(svm, INTERCEPT_INTR);
924 set_intercept(svm, INTERCEPT_NMI);
925 set_intercept(svm, INTERCEPT_SMI);
926 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
927 set_intercept(svm, INTERCEPT_CPUID);
928 set_intercept(svm, INTERCEPT_INVD);
929 set_intercept(svm, INTERCEPT_HLT);
930 set_intercept(svm, INTERCEPT_INVLPG);
931 set_intercept(svm, INTERCEPT_INVLPGA);
932 set_intercept(svm, INTERCEPT_IOIO_PROT);
933 set_intercept(svm, INTERCEPT_MSR_PROT);
934 set_intercept(svm, INTERCEPT_TASK_SWITCH);
935 set_intercept(svm, INTERCEPT_SHUTDOWN);
936 set_intercept(svm, INTERCEPT_VMRUN);
937 set_intercept(svm, INTERCEPT_VMMCALL);
938 set_intercept(svm, INTERCEPT_VMLOAD);
939 set_intercept(svm, INTERCEPT_VMSAVE);
940 set_intercept(svm, INTERCEPT_STGI);
941 set_intercept(svm, INTERCEPT_CLGI);
942 set_intercept(svm, INTERCEPT_SKINIT);
943 set_intercept(svm, INTERCEPT_WBINVD);
944 set_intercept(svm, INTERCEPT_MONITOR);
945 set_intercept(svm, INTERCEPT_MWAIT);
946
947 control->iopm_base_pa = iopm_base;
948 control->msrpm_base_pa = __pa(svm->msrpm);
949 control->int_ctl = V_INTR_MASKING_MASK;
950
951 init_seg(&save->es);
952 init_seg(&save->ss);
953 init_seg(&save->ds);
954 init_seg(&save->fs);
955 init_seg(&save->gs);
956
957 save->cs.selector = 0xf000;
958 /* Executable/Readable Code Segment */
959 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
960 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
961 save->cs.limit = 0xffff;
962 /*
963 * cs.base should really be 0xffff0000, but vmx can't handle that, so
964 * be consistent with it.
965 *
966 * Replace when we have real mode working for vmx.
967 */
968 save->cs.base = 0xf0000;
969
970 save->gdtr.limit = 0xffff;
971 save->idtr.limit = 0xffff;
972
973 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
974 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
975
976 svm_set_efer(&svm->vcpu, 0);
977 save->dr6 = 0xffff0ff0;
978 save->dr7 = 0x400;
979 save->rflags = 2;
980 save->rip = 0x0000fff0;
981 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
982
983 /*
984 * This is the guest-visible cr0 value.
985 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
986 */
987 svm->vcpu.arch.cr0 = 0;
988 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
989
990 save->cr4 = X86_CR4_PAE;
991 /* rdx = ?? */
992
993 if (npt_enabled) {
994 /* Setup VMCB for Nested Paging */
995 control->nested_ctl = 1;
996 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
997 clr_intercept(svm, INTERCEPT_INVLPG);
998 clr_exception_intercept(svm, PF_VECTOR);
999 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1000 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1001 save->g_pat = 0x0007040600070406ULL;
1002 save->cr3 = 0;
1003 save->cr4 = 0;
1004 }
1005 force_new_asid(&svm->vcpu);
1006
1007 svm->nested.vmcb = 0;
1008 svm->vcpu.arch.hflags = 0;
1009
1010 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1011 control->pause_filter_count = 3000;
1012 set_intercept(svm, INTERCEPT_PAUSE);
1013 }
1014
1015 mark_all_dirty(svm->vmcb);
1016
1017 enable_gif(svm);
1018 }
1019
1020 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1021 {
1022 struct vcpu_svm *svm = to_svm(vcpu);
1023
1024 init_vmcb(svm);
1025
1026 if (!kvm_vcpu_is_bsp(vcpu)) {
1027 kvm_rip_write(vcpu, 0);
1028 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1029 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1030 }
1031 vcpu->arch.regs_avail = ~0;
1032 vcpu->arch.regs_dirty = ~0;
1033
1034 return 0;
1035 }
1036
1037 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1038 {
1039 struct vcpu_svm *svm;
1040 struct page *page;
1041 struct page *msrpm_pages;
1042 struct page *hsave_page;
1043 struct page *nested_msrpm_pages;
1044 int err;
1045
1046 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1047 if (!svm) {
1048 err = -ENOMEM;
1049 goto out;
1050 }
1051
1052 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1053 if (err)
1054 goto free_svm;
1055
1056 err = -ENOMEM;
1057 page = alloc_page(GFP_KERNEL);
1058 if (!page)
1059 goto uninit;
1060
1061 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1062 if (!msrpm_pages)
1063 goto free_page1;
1064
1065 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1066 if (!nested_msrpm_pages)
1067 goto free_page2;
1068
1069 hsave_page = alloc_page(GFP_KERNEL);
1070 if (!hsave_page)
1071 goto free_page3;
1072
1073 svm->nested.hsave = page_address(hsave_page);
1074
1075 svm->msrpm = page_address(msrpm_pages);
1076 svm_vcpu_init_msrpm(svm->msrpm);
1077
1078 svm->nested.msrpm = page_address(nested_msrpm_pages);
1079 svm_vcpu_init_msrpm(svm->nested.msrpm);
1080
1081 svm->vmcb = page_address(page);
1082 clear_page(svm->vmcb);
1083 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1084 svm->asid_generation = 0;
1085 init_vmcb(svm);
1086 kvm_write_tsc(&svm->vcpu, 0);
1087
1088 err = fx_init(&svm->vcpu);
1089 if (err)
1090 goto free_page4;
1091
1092 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1093 if (kvm_vcpu_is_bsp(&svm->vcpu))
1094 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1095
1096 return &svm->vcpu;
1097
1098 free_page4:
1099 __free_page(hsave_page);
1100 free_page3:
1101 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1102 free_page2:
1103 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1104 free_page1:
1105 __free_page(page);
1106 uninit:
1107 kvm_vcpu_uninit(&svm->vcpu);
1108 free_svm:
1109 kmem_cache_free(kvm_vcpu_cache, svm);
1110 out:
1111 return ERR_PTR(err);
1112 }
1113
1114 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1115 {
1116 struct vcpu_svm *svm = to_svm(vcpu);
1117
1118 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1119 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1120 __free_page(virt_to_page(svm->nested.hsave));
1121 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1122 kvm_vcpu_uninit(vcpu);
1123 kmem_cache_free(kvm_vcpu_cache, svm);
1124 }
1125
1126 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1127 {
1128 struct vcpu_svm *svm = to_svm(vcpu);
1129 int i;
1130
1131 if (unlikely(cpu != vcpu->cpu)) {
1132 svm->asid_generation = 0;
1133 mark_all_dirty(svm->vmcb);
1134 }
1135
1136 #ifdef CONFIG_X86_64
1137 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1138 #endif
1139 savesegment(fs, svm->host.fs);
1140 savesegment(gs, svm->host.gs);
1141 svm->host.ldt = kvm_read_ldt();
1142
1143 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1144 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1145 }
1146
1147 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1148 {
1149 struct vcpu_svm *svm = to_svm(vcpu);
1150 int i;
1151
1152 ++vcpu->stat.host_state_reload;
1153 kvm_load_ldt(svm->host.ldt);
1154 #ifdef CONFIG_X86_64
1155 loadsegment(fs, svm->host.fs);
1156 load_gs_index(svm->host.gs);
1157 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1158 #else
1159 loadsegment(gs, svm->host.gs);
1160 #endif
1161 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1162 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1163 }
1164
1165 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1166 {
1167 return to_svm(vcpu)->vmcb->save.rflags;
1168 }
1169
1170 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1171 {
1172 to_svm(vcpu)->vmcb->save.rflags = rflags;
1173 }
1174
1175 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1176 {
1177 switch (reg) {
1178 case VCPU_EXREG_PDPTR:
1179 BUG_ON(!npt_enabled);
1180 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1181 break;
1182 default:
1183 BUG();
1184 }
1185 }
1186
1187 static void svm_set_vintr(struct vcpu_svm *svm)
1188 {
1189 set_intercept(svm, INTERCEPT_VINTR);
1190 }
1191
1192 static void svm_clear_vintr(struct vcpu_svm *svm)
1193 {
1194 clr_intercept(svm, INTERCEPT_VINTR);
1195 }
1196
1197 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1198 {
1199 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1200
1201 switch (seg) {
1202 case VCPU_SREG_CS: return &save->cs;
1203 case VCPU_SREG_DS: return &save->ds;
1204 case VCPU_SREG_ES: return &save->es;
1205 case VCPU_SREG_FS: return &save->fs;
1206 case VCPU_SREG_GS: return &save->gs;
1207 case VCPU_SREG_SS: return &save->ss;
1208 case VCPU_SREG_TR: return &save->tr;
1209 case VCPU_SREG_LDTR: return &save->ldtr;
1210 }
1211 BUG();
1212 return NULL;
1213 }
1214
1215 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1216 {
1217 struct vmcb_seg *s = svm_seg(vcpu, seg);
1218
1219 return s->base;
1220 }
1221
1222 static void svm_get_segment(struct kvm_vcpu *vcpu,
1223 struct kvm_segment *var, int seg)
1224 {
1225 struct vmcb_seg *s = svm_seg(vcpu, seg);
1226
1227 var->base = s->base;
1228 var->limit = s->limit;
1229 var->selector = s->selector;
1230 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1231 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1232 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1233 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1234 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1235 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1236 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1237 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1238
1239 /*
1240 * AMD's VMCB does not have an explicit unusable field, so emulate it
1241 * for cross vendor migration purposes by "not present"
1242 */
1243 var->unusable = !var->present || (var->type == 0);
1244
1245 switch (seg) {
1246 case VCPU_SREG_CS:
1247 /*
1248 * SVM always stores 0 for the 'G' bit in the CS selector in
1249 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1250 * Intel's VMENTRY has a check on the 'G' bit.
1251 */
1252 var->g = s->limit > 0xfffff;
1253 break;
1254 case VCPU_SREG_TR:
1255 /*
1256 * Work around a bug where the busy flag in the tr selector
1257 * isn't exposed
1258 */
1259 var->type |= 0x2;
1260 break;
1261 case VCPU_SREG_DS:
1262 case VCPU_SREG_ES:
1263 case VCPU_SREG_FS:
1264 case VCPU_SREG_GS:
1265 /*
1266 * The accessed bit must always be set in the segment
1267 * descriptor cache, although it can be cleared in the
1268 * descriptor, the cached bit always remains at 1. Since
1269 * Intel has a check on this, set it here to support
1270 * cross-vendor migration.
1271 */
1272 if (!var->unusable)
1273 var->type |= 0x1;
1274 break;
1275 case VCPU_SREG_SS:
1276 /*
1277 * On AMD CPUs sometimes the DB bit in the segment
1278 * descriptor is left as 1, although the whole segment has
1279 * been made unusable. Clear it here to pass an Intel VMX
1280 * entry check when cross vendor migrating.
1281 */
1282 if (var->unusable)
1283 var->db = 0;
1284 break;
1285 }
1286 }
1287
1288 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1289 {
1290 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1291
1292 return save->cpl;
1293 }
1294
1295 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1296 {
1297 struct vcpu_svm *svm = to_svm(vcpu);
1298
1299 dt->size = svm->vmcb->save.idtr.limit;
1300 dt->address = svm->vmcb->save.idtr.base;
1301 }
1302
1303 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1304 {
1305 struct vcpu_svm *svm = to_svm(vcpu);
1306
1307 svm->vmcb->save.idtr.limit = dt->size;
1308 svm->vmcb->save.idtr.base = dt->address ;
1309 mark_dirty(svm->vmcb, VMCB_DT);
1310 }
1311
1312 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1313 {
1314 struct vcpu_svm *svm = to_svm(vcpu);
1315
1316 dt->size = svm->vmcb->save.gdtr.limit;
1317 dt->address = svm->vmcb->save.gdtr.base;
1318 }
1319
1320 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1321 {
1322 struct vcpu_svm *svm = to_svm(vcpu);
1323
1324 svm->vmcb->save.gdtr.limit = dt->size;
1325 svm->vmcb->save.gdtr.base = dt->address ;
1326 mark_dirty(svm->vmcb, VMCB_DT);
1327 }
1328
1329 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1330 {
1331 }
1332
1333 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1334 {
1335 }
1336
1337 static void update_cr0_intercept(struct vcpu_svm *svm)
1338 {
1339 ulong gcr0 = svm->vcpu.arch.cr0;
1340 u64 *hcr0 = &svm->vmcb->save.cr0;
1341
1342 if (!svm->vcpu.fpu_active)
1343 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1344 else
1345 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1346 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1347
1348 mark_dirty(svm->vmcb, VMCB_CR);
1349
1350 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1351 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1352 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1353 } else {
1354 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1355 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1356 }
1357 }
1358
1359 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1360 {
1361 struct vcpu_svm *svm = to_svm(vcpu);
1362
1363 if (is_guest_mode(vcpu)) {
1364 /*
1365 * We are here because we run in nested mode, the host kvm
1366 * intercepts cr0 writes but the l1 hypervisor does not.
1367 * But the L1 hypervisor may intercept selective cr0 writes.
1368 * This needs to be checked here.
1369 */
1370 unsigned long old, new;
1371
1372 /* Remove bits that would trigger a real cr0 write intercept */
1373 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1374 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1375
1376 if (old == new) {
1377 /* cr0 write with ts and mp unchanged */
1378 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1379 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1380 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1381 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1382 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1383 return;
1384 }
1385 }
1386 }
1387
1388 #ifdef CONFIG_X86_64
1389 if (vcpu->arch.efer & EFER_LME) {
1390 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1391 vcpu->arch.efer |= EFER_LMA;
1392 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1393 }
1394
1395 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1396 vcpu->arch.efer &= ~EFER_LMA;
1397 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1398 }
1399 }
1400 #endif
1401 vcpu->arch.cr0 = cr0;
1402
1403 if (!npt_enabled)
1404 cr0 |= X86_CR0_PG | X86_CR0_WP;
1405
1406 if (!vcpu->fpu_active)
1407 cr0 |= X86_CR0_TS;
1408 /*
1409 * re-enable caching here because the QEMU bios
1410 * does not do it - this results in some delay at
1411 * reboot
1412 */
1413 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1414 svm->vmcb->save.cr0 = cr0;
1415 mark_dirty(svm->vmcb, VMCB_CR);
1416 update_cr0_intercept(svm);
1417 }
1418
1419 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1420 {
1421 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1422 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1423
1424 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1425 force_new_asid(vcpu);
1426
1427 vcpu->arch.cr4 = cr4;
1428 if (!npt_enabled)
1429 cr4 |= X86_CR4_PAE;
1430 cr4 |= host_cr4_mce;
1431 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1432 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1433 }
1434
1435 static void svm_set_segment(struct kvm_vcpu *vcpu,
1436 struct kvm_segment *var, int seg)
1437 {
1438 struct vcpu_svm *svm = to_svm(vcpu);
1439 struct vmcb_seg *s = svm_seg(vcpu, seg);
1440
1441 s->base = var->base;
1442 s->limit = var->limit;
1443 s->selector = var->selector;
1444 if (var->unusable)
1445 s->attrib = 0;
1446 else {
1447 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1448 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1449 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1450 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1451 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1452 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1453 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1454 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1455 }
1456 if (seg == VCPU_SREG_CS)
1457 svm->vmcb->save.cpl
1458 = (svm->vmcb->save.cs.attrib
1459 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1460
1461 mark_dirty(svm->vmcb, VMCB_SEG);
1462 }
1463
1464 static void update_db_intercept(struct kvm_vcpu *vcpu)
1465 {
1466 struct vcpu_svm *svm = to_svm(vcpu);
1467
1468 clr_exception_intercept(svm, DB_VECTOR);
1469 clr_exception_intercept(svm, BP_VECTOR);
1470
1471 if (svm->nmi_singlestep)
1472 set_exception_intercept(svm, DB_VECTOR);
1473
1474 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1475 if (vcpu->guest_debug &
1476 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1477 set_exception_intercept(svm, DB_VECTOR);
1478 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1479 set_exception_intercept(svm, BP_VECTOR);
1480 } else
1481 vcpu->guest_debug = 0;
1482 }
1483
1484 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1485 {
1486 struct vcpu_svm *svm = to_svm(vcpu);
1487
1488 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1489 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1490 else
1491 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1492
1493 mark_dirty(svm->vmcb, VMCB_DR);
1494
1495 update_db_intercept(vcpu);
1496 }
1497
1498 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1499 {
1500 if (sd->next_asid > sd->max_asid) {
1501 ++sd->asid_generation;
1502 sd->next_asid = 1;
1503 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1504 }
1505
1506 svm->asid_generation = sd->asid_generation;
1507 svm->vmcb->control.asid = sd->next_asid++;
1508
1509 mark_dirty(svm->vmcb, VMCB_ASID);
1510 }
1511
1512 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1513 {
1514 struct vcpu_svm *svm = to_svm(vcpu);
1515
1516 svm->vmcb->save.dr7 = value;
1517 mark_dirty(svm->vmcb, VMCB_DR);
1518 }
1519
1520 static int pf_interception(struct vcpu_svm *svm)
1521 {
1522 u64 fault_address = svm->vmcb->control.exit_info_2;
1523 u32 error_code;
1524 int r = 1;
1525
1526 switch (svm->apf_reason) {
1527 default:
1528 error_code = svm->vmcb->control.exit_info_1;
1529
1530 trace_kvm_page_fault(fault_address, error_code);
1531 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1532 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1533 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1534 break;
1535 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1536 svm->apf_reason = 0;
1537 local_irq_disable();
1538 kvm_async_pf_task_wait(fault_address);
1539 local_irq_enable();
1540 break;
1541 case KVM_PV_REASON_PAGE_READY:
1542 svm->apf_reason = 0;
1543 local_irq_disable();
1544 kvm_async_pf_task_wake(fault_address);
1545 local_irq_enable();
1546 break;
1547 }
1548 return r;
1549 }
1550
1551 static int db_interception(struct vcpu_svm *svm)
1552 {
1553 struct kvm_run *kvm_run = svm->vcpu.run;
1554
1555 if (!(svm->vcpu.guest_debug &
1556 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1557 !svm->nmi_singlestep) {
1558 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1559 return 1;
1560 }
1561
1562 if (svm->nmi_singlestep) {
1563 svm->nmi_singlestep = false;
1564 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1565 svm->vmcb->save.rflags &=
1566 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1567 update_db_intercept(&svm->vcpu);
1568 }
1569
1570 if (svm->vcpu.guest_debug &
1571 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1572 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1573 kvm_run->debug.arch.pc =
1574 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1575 kvm_run->debug.arch.exception = DB_VECTOR;
1576 return 0;
1577 }
1578
1579 return 1;
1580 }
1581
1582 static int bp_interception(struct vcpu_svm *svm)
1583 {
1584 struct kvm_run *kvm_run = svm->vcpu.run;
1585
1586 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1587 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1588 kvm_run->debug.arch.exception = BP_VECTOR;
1589 return 0;
1590 }
1591
1592 static int ud_interception(struct vcpu_svm *svm)
1593 {
1594 int er;
1595
1596 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1597 if (er != EMULATE_DONE)
1598 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1599 return 1;
1600 }
1601
1602 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1603 {
1604 struct vcpu_svm *svm = to_svm(vcpu);
1605
1606 clr_exception_intercept(svm, NM_VECTOR);
1607
1608 svm->vcpu.fpu_active = 1;
1609 update_cr0_intercept(svm);
1610 }
1611
1612 static int nm_interception(struct vcpu_svm *svm)
1613 {
1614 svm_fpu_activate(&svm->vcpu);
1615 return 1;
1616 }
1617
1618 static bool is_erratum_383(void)
1619 {
1620 int err, i;
1621 u64 value;
1622
1623 if (!erratum_383_found)
1624 return false;
1625
1626 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1627 if (err)
1628 return false;
1629
1630 /* Bit 62 may or may not be set for this mce */
1631 value &= ~(1ULL << 62);
1632
1633 if (value != 0xb600000000010015ULL)
1634 return false;
1635
1636 /* Clear MCi_STATUS registers */
1637 for (i = 0; i < 6; ++i)
1638 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1639
1640 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1641 if (!err) {
1642 u32 low, high;
1643
1644 value &= ~(1ULL << 2);
1645 low = lower_32_bits(value);
1646 high = upper_32_bits(value);
1647
1648 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1649 }
1650
1651 /* Flush tlb to evict multi-match entries */
1652 __flush_tlb_all();
1653
1654 return true;
1655 }
1656
1657 static void svm_handle_mce(struct vcpu_svm *svm)
1658 {
1659 if (is_erratum_383()) {
1660 /*
1661 * Erratum 383 triggered. Guest state is corrupt so kill the
1662 * guest.
1663 */
1664 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1665
1666 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1667
1668 return;
1669 }
1670
1671 /*
1672 * On an #MC intercept the MCE handler is not called automatically in
1673 * the host. So do it by hand here.
1674 */
1675 asm volatile (
1676 "int $0x12\n");
1677 /* not sure if we ever come back to this point */
1678
1679 return;
1680 }
1681
1682 static int mc_interception(struct vcpu_svm *svm)
1683 {
1684 return 1;
1685 }
1686
1687 static int shutdown_interception(struct vcpu_svm *svm)
1688 {
1689 struct kvm_run *kvm_run = svm->vcpu.run;
1690
1691 /*
1692 * VMCB is undefined after a SHUTDOWN intercept
1693 * so reinitialize it.
1694 */
1695 clear_page(svm->vmcb);
1696 init_vmcb(svm);
1697
1698 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1699 return 0;
1700 }
1701
1702 static int io_interception(struct vcpu_svm *svm)
1703 {
1704 struct kvm_vcpu *vcpu = &svm->vcpu;
1705 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1706 int size, in, string;
1707 unsigned port;
1708
1709 ++svm->vcpu.stat.io_exits;
1710 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1711 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1712 if (string || in)
1713 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1714
1715 port = io_info >> 16;
1716 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1717 svm->next_rip = svm->vmcb->control.exit_info_2;
1718 skip_emulated_instruction(&svm->vcpu);
1719
1720 return kvm_fast_pio_out(vcpu, size, port);
1721 }
1722
1723 static int nmi_interception(struct vcpu_svm *svm)
1724 {
1725 return 1;
1726 }
1727
1728 static int intr_interception(struct vcpu_svm *svm)
1729 {
1730 ++svm->vcpu.stat.irq_exits;
1731 return 1;
1732 }
1733
1734 static int nop_on_interception(struct vcpu_svm *svm)
1735 {
1736 return 1;
1737 }
1738
1739 static int halt_interception(struct vcpu_svm *svm)
1740 {
1741 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1742 skip_emulated_instruction(&svm->vcpu);
1743 return kvm_emulate_halt(&svm->vcpu);
1744 }
1745
1746 static int vmmcall_interception(struct vcpu_svm *svm)
1747 {
1748 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1749 skip_emulated_instruction(&svm->vcpu);
1750 kvm_emulate_hypercall(&svm->vcpu);
1751 return 1;
1752 }
1753
1754 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1755 {
1756 struct vcpu_svm *svm = to_svm(vcpu);
1757
1758 return svm->nested.nested_cr3;
1759 }
1760
1761 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1762 unsigned long root)
1763 {
1764 struct vcpu_svm *svm = to_svm(vcpu);
1765
1766 svm->vmcb->control.nested_cr3 = root;
1767 mark_dirty(svm->vmcb, VMCB_NPT);
1768 force_new_asid(vcpu);
1769 }
1770
1771 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1772 struct x86_exception *fault)
1773 {
1774 struct vcpu_svm *svm = to_svm(vcpu);
1775
1776 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1777 svm->vmcb->control.exit_code_hi = 0;
1778 svm->vmcb->control.exit_info_1 = fault->error_code;
1779 svm->vmcb->control.exit_info_2 = fault->address;
1780
1781 nested_svm_vmexit(svm);
1782 }
1783
1784 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1785 {
1786 int r;
1787
1788 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1789
1790 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1791 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1792 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1793 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1794 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1795
1796 return r;
1797 }
1798
1799 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1800 {
1801 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1802 }
1803
1804 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1805 {
1806 if (!(svm->vcpu.arch.efer & EFER_SVME)
1807 || !is_paging(&svm->vcpu)) {
1808 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1809 return 1;
1810 }
1811
1812 if (svm->vmcb->save.cpl) {
1813 kvm_inject_gp(&svm->vcpu, 0);
1814 return 1;
1815 }
1816
1817 return 0;
1818 }
1819
1820 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1821 bool has_error_code, u32 error_code)
1822 {
1823 int vmexit;
1824
1825 if (!is_guest_mode(&svm->vcpu))
1826 return 0;
1827
1828 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1829 svm->vmcb->control.exit_code_hi = 0;
1830 svm->vmcb->control.exit_info_1 = error_code;
1831 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1832
1833 vmexit = nested_svm_intercept(svm);
1834 if (vmexit == NESTED_EXIT_DONE)
1835 svm->nested.exit_required = true;
1836
1837 return vmexit;
1838 }
1839
1840 /* This function returns true if it is save to enable the irq window */
1841 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1842 {
1843 if (!is_guest_mode(&svm->vcpu))
1844 return true;
1845
1846 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1847 return true;
1848
1849 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1850 return false;
1851
1852 /*
1853 * if vmexit was already requested (by intercepted exception
1854 * for instance) do not overwrite it with "external interrupt"
1855 * vmexit.
1856 */
1857 if (svm->nested.exit_required)
1858 return false;
1859
1860 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1861 svm->vmcb->control.exit_info_1 = 0;
1862 svm->vmcb->control.exit_info_2 = 0;
1863
1864 if (svm->nested.intercept & 1ULL) {
1865 /*
1866 * The #vmexit can't be emulated here directly because this
1867 * code path runs with irqs and preemtion disabled. A
1868 * #vmexit emulation might sleep. Only signal request for
1869 * the #vmexit here.
1870 */
1871 svm->nested.exit_required = true;
1872 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1873 return false;
1874 }
1875
1876 return true;
1877 }
1878
1879 /* This function returns true if it is save to enable the nmi window */
1880 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1881 {
1882 if (!is_guest_mode(&svm->vcpu))
1883 return true;
1884
1885 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1886 return true;
1887
1888 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1889 svm->nested.exit_required = true;
1890
1891 return false;
1892 }
1893
1894 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1895 {
1896 struct page *page;
1897
1898 might_sleep();
1899
1900 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1901 if (is_error_page(page))
1902 goto error;
1903
1904 *_page = page;
1905
1906 return kmap(page);
1907
1908 error:
1909 kvm_release_page_clean(page);
1910 kvm_inject_gp(&svm->vcpu, 0);
1911
1912 return NULL;
1913 }
1914
1915 static void nested_svm_unmap(struct page *page)
1916 {
1917 kunmap(page);
1918 kvm_release_page_dirty(page);
1919 }
1920
1921 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1922 {
1923 unsigned port;
1924 u8 val, bit;
1925 u64 gpa;
1926
1927 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1928 return NESTED_EXIT_HOST;
1929
1930 port = svm->vmcb->control.exit_info_1 >> 16;
1931 gpa = svm->nested.vmcb_iopm + (port / 8);
1932 bit = port % 8;
1933 val = 0;
1934
1935 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1936 val &= (1 << bit);
1937
1938 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1939 }
1940
1941 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1942 {
1943 u32 offset, msr, value;
1944 int write, mask;
1945
1946 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1947 return NESTED_EXIT_HOST;
1948
1949 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1950 offset = svm_msrpm_offset(msr);
1951 write = svm->vmcb->control.exit_info_1 & 1;
1952 mask = 1 << ((2 * (msr & 0xf)) + write);
1953
1954 if (offset == MSR_INVALID)
1955 return NESTED_EXIT_DONE;
1956
1957 /* Offset is in 32 bit units but need in 8 bit units */
1958 offset *= 4;
1959
1960 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1961 return NESTED_EXIT_DONE;
1962
1963 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1964 }
1965
1966 static int nested_svm_exit_special(struct vcpu_svm *svm)
1967 {
1968 u32 exit_code = svm->vmcb->control.exit_code;
1969
1970 switch (exit_code) {
1971 case SVM_EXIT_INTR:
1972 case SVM_EXIT_NMI:
1973 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1974 return NESTED_EXIT_HOST;
1975 case SVM_EXIT_NPF:
1976 /* For now we are always handling NPFs when using them */
1977 if (npt_enabled)
1978 return NESTED_EXIT_HOST;
1979 break;
1980 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1981 /* When we're shadowing, trap PFs, but not async PF */
1982 if (!npt_enabled && svm->apf_reason == 0)
1983 return NESTED_EXIT_HOST;
1984 break;
1985 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1986 nm_interception(svm);
1987 break;
1988 default:
1989 break;
1990 }
1991
1992 return NESTED_EXIT_CONTINUE;
1993 }
1994
1995 /*
1996 * If this function returns true, this #vmexit was already handled
1997 */
1998 static int nested_svm_intercept(struct vcpu_svm *svm)
1999 {
2000 u32 exit_code = svm->vmcb->control.exit_code;
2001 int vmexit = NESTED_EXIT_HOST;
2002
2003 switch (exit_code) {
2004 case SVM_EXIT_MSR:
2005 vmexit = nested_svm_exit_handled_msr(svm);
2006 break;
2007 case SVM_EXIT_IOIO:
2008 vmexit = nested_svm_intercept_ioio(svm);
2009 break;
2010 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2011 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2012 if (svm->nested.intercept_cr & bit)
2013 vmexit = NESTED_EXIT_DONE;
2014 break;
2015 }
2016 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2017 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2018 if (svm->nested.intercept_dr & bit)
2019 vmexit = NESTED_EXIT_DONE;
2020 break;
2021 }
2022 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2023 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2024 if (svm->nested.intercept_exceptions & excp_bits)
2025 vmexit = NESTED_EXIT_DONE;
2026 /* async page fault always cause vmexit */
2027 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2028 svm->apf_reason != 0)
2029 vmexit = NESTED_EXIT_DONE;
2030 break;
2031 }
2032 case SVM_EXIT_ERR: {
2033 vmexit = NESTED_EXIT_DONE;
2034 break;
2035 }
2036 default: {
2037 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2038 if (svm->nested.intercept & exit_bits)
2039 vmexit = NESTED_EXIT_DONE;
2040 }
2041 }
2042
2043 return vmexit;
2044 }
2045
2046 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2047 {
2048 int vmexit;
2049
2050 vmexit = nested_svm_intercept(svm);
2051
2052 if (vmexit == NESTED_EXIT_DONE)
2053 nested_svm_vmexit(svm);
2054
2055 return vmexit;
2056 }
2057
2058 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2059 {
2060 struct vmcb_control_area *dst = &dst_vmcb->control;
2061 struct vmcb_control_area *from = &from_vmcb->control;
2062
2063 dst->intercept_cr = from->intercept_cr;
2064 dst->intercept_dr = from->intercept_dr;
2065 dst->intercept_exceptions = from->intercept_exceptions;
2066 dst->intercept = from->intercept;
2067 dst->iopm_base_pa = from->iopm_base_pa;
2068 dst->msrpm_base_pa = from->msrpm_base_pa;
2069 dst->tsc_offset = from->tsc_offset;
2070 dst->asid = from->asid;
2071 dst->tlb_ctl = from->tlb_ctl;
2072 dst->int_ctl = from->int_ctl;
2073 dst->int_vector = from->int_vector;
2074 dst->int_state = from->int_state;
2075 dst->exit_code = from->exit_code;
2076 dst->exit_code_hi = from->exit_code_hi;
2077 dst->exit_info_1 = from->exit_info_1;
2078 dst->exit_info_2 = from->exit_info_2;
2079 dst->exit_int_info = from->exit_int_info;
2080 dst->exit_int_info_err = from->exit_int_info_err;
2081 dst->nested_ctl = from->nested_ctl;
2082 dst->event_inj = from->event_inj;
2083 dst->event_inj_err = from->event_inj_err;
2084 dst->nested_cr3 = from->nested_cr3;
2085 dst->lbr_ctl = from->lbr_ctl;
2086 }
2087
2088 static int nested_svm_vmexit(struct vcpu_svm *svm)
2089 {
2090 struct vmcb *nested_vmcb;
2091 struct vmcb *hsave = svm->nested.hsave;
2092 struct vmcb *vmcb = svm->vmcb;
2093 struct page *page;
2094
2095 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2096 vmcb->control.exit_info_1,
2097 vmcb->control.exit_info_2,
2098 vmcb->control.exit_int_info,
2099 vmcb->control.exit_int_info_err);
2100
2101 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2102 if (!nested_vmcb)
2103 return 1;
2104
2105 /* Exit Guest-Mode */
2106 leave_guest_mode(&svm->vcpu);
2107 svm->nested.vmcb = 0;
2108
2109 /* Give the current vmcb to the guest */
2110 disable_gif(svm);
2111
2112 nested_vmcb->save.es = vmcb->save.es;
2113 nested_vmcb->save.cs = vmcb->save.cs;
2114 nested_vmcb->save.ss = vmcb->save.ss;
2115 nested_vmcb->save.ds = vmcb->save.ds;
2116 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2117 nested_vmcb->save.idtr = vmcb->save.idtr;
2118 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2119 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2120 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2121 nested_vmcb->save.cr2 = vmcb->save.cr2;
2122 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2123 nested_vmcb->save.rflags = vmcb->save.rflags;
2124 nested_vmcb->save.rip = vmcb->save.rip;
2125 nested_vmcb->save.rsp = vmcb->save.rsp;
2126 nested_vmcb->save.rax = vmcb->save.rax;
2127 nested_vmcb->save.dr7 = vmcb->save.dr7;
2128 nested_vmcb->save.dr6 = vmcb->save.dr6;
2129 nested_vmcb->save.cpl = vmcb->save.cpl;
2130
2131 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2132 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2133 nested_vmcb->control.int_state = vmcb->control.int_state;
2134 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2135 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2136 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2137 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2138 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2139 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2140 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2141
2142 /*
2143 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2144 * to make sure that we do not lose injected events. So check event_inj
2145 * here and copy it to exit_int_info if it is valid.
2146 * Exit_int_info and event_inj can't be both valid because the case
2147 * below only happens on a VMRUN instruction intercept which has
2148 * no valid exit_int_info set.
2149 */
2150 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2151 struct vmcb_control_area *nc = &nested_vmcb->control;
2152
2153 nc->exit_int_info = vmcb->control.event_inj;
2154 nc->exit_int_info_err = vmcb->control.event_inj_err;
2155 }
2156
2157 nested_vmcb->control.tlb_ctl = 0;
2158 nested_vmcb->control.event_inj = 0;
2159 nested_vmcb->control.event_inj_err = 0;
2160
2161 /* We always set V_INTR_MASKING and remember the old value in hflags */
2162 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2163 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2164
2165 /* Restore the original control entries */
2166 copy_vmcb_control_area(vmcb, hsave);
2167
2168 kvm_clear_exception_queue(&svm->vcpu);
2169 kvm_clear_interrupt_queue(&svm->vcpu);
2170
2171 svm->nested.nested_cr3 = 0;
2172
2173 /* Restore selected save entries */
2174 svm->vmcb->save.es = hsave->save.es;
2175 svm->vmcb->save.cs = hsave->save.cs;
2176 svm->vmcb->save.ss = hsave->save.ss;
2177 svm->vmcb->save.ds = hsave->save.ds;
2178 svm->vmcb->save.gdtr = hsave->save.gdtr;
2179 svm->vmcb->save.idtr = hsave->save.idtr;
2180 svm->vmcb->save.rflags = hsave->save.rflags;
2181 svm_set_efer(&svm->vcpu, hsave->save.efer);
2182 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2183 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2184 if (npt_enabled) {
2185 svm->vmcb->save.cr3 = hsave->save.cr3;
2186 svm->vcpu.arch.cr3 = hsave->save.cr3;
2187 } else {
2188 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2189 }
2190 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2191 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2192 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2193 svm->vmcb->save.dr7 = 0;
2194 svm->vmcb->save.cpl = 0;
2195 svm->vmcb->control.exit_int_info = 0;
2196
2197 mark_all_dirty(svm->vmcb);
2198
2199 nested_svm_unmap(page);
2200
2201 nested_svm_uninit_mmu_context(&svm->vcpu);
2202 kvm_mmu_reset_context(&svm->vcpu);
2203 kvm_mmu_load(&svm->vcpu);
2204
2205 return 0;
2206 }
2207
2208 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2209 {
2210 /*
2211 * This function merges the msr permission bitmaps of kvm and the
2212 * nested vmcb. It is omptimized in that it only merges the parts where
2213 * the kvm msr permission bitmap may contain zero bits
2214 */
2215 int i;
2216
2217 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2218 return true;
2219
2220 for (i = 0; i < MSRPM_OFFSETS; i++) {
2221 u32 value, p;
2222 u64 offset;
2223
2224 if (msrpm_offsets[i] == 0xffffffff)
2225 break;
2226
2227 p = msrpm_offsets[i];
2228 offset = svm->nested.vmcb_msrpm + (p * 4);
2229
2230 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2231 return false;
2232
2233 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2234 }
2235
2236 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2237
2238 return true;
2239 }
2240
2241 static bool nested_vmcb_checks(struct vmcb *vmcb)
2242 {
2243 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2244 return false;
2245
2246 if (vmcb->control.asid == 0)
2247 return false;
2248
2249 if (vmcb->control.nested_ctl && !npt_enabled)
2250 return false;
2251
2252 return true;
2253 }
2254
2255 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2256 {
2257 struct vmcb *nested_vmcb;
2258 struct vmcb *hsave = svm->nested.hsave;
2259 struct vmcb *vmcb = svm->vmcb;
2260 struct page *page;
2261 u64 vmcb_gpa;
2262
2263 vmcb_gpa = svm->vmcb->save.rax;
2264
2265 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2266 if (!nested_vmcb)
2267 return false;
2268
2269 if (!nested_vmcb_checks(nested_vmcb)) {
2270 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2271 nested_vmcb->control.exit_code_hi = 0;
2272 nested_vmcb->control.exit_info_1 = 0;
2273 nested_vmcb->control.exit_info_2 = 0;
2274
2275 nested_svm_unmap(page);
2276
2277 return false;
2278 }
2279
2280 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2281 nested_vmcb->save.rip,
2282 nested_vmcb->control.int_ctl,
2283 nested_vmcb->control.event_inj,
2284 nested_vmcb->control.nested_ctl);
2285
2286 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2287 nested_vmcb->control.intercept_cr >> 16,
2288 nested_vmcb->control.intercept_exceptions,
2289 nested_vmcb->control.intercept);
2290
2291 /* Clear internal status */
2292 kvm_clear_exception_queue(&svm->vcpu);
2293 kvm_clear_interrupt_queue(&svm->vcpu);
2294
2295 /*
2296 * Save the old vmcb, so we don't need to pick what we save, but can
2297 * restore everything when a VMEXIT occurs
2298 */
2299 hsave->save.es = vmcb->save.es;
2300 hsave->save.cs = vmcb->save.cs;
2301 hsave->save.ss = vmcb->save.ss;
2302 hsave->save.ds = vmcb->save.ds;
2303 hsave->save.gdtr = vmcb->save.gdtr;
2304 hsave->save.idtr = vmcb->save.idtr;
2305 hsave->save.efer = svm->vcpu.arch.efer;
2306 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2307 hsave->save.cr4 = svm->vcpu.arch.cr4;
2308 hsave->save.rflags = vmcb->save.rflags;
2309 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2310 hsave->save.rsp = vmcb->save.rsp;
2311 hsave->save.rax = vmcb->save.rax;
2312 if (npt_enabled)
2313 hsave->save.cr3 = vmcb->save.cr3;
2314 else
2315 hsave->save.cr3 = svm->vcpu.arch.cr3;
2316
2317 copy_vmcb_control_area(hsave, vmcb);
2318
2319 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2320 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2321 else
2322 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2323
2324 if (nested_vmcb->control.nested_ctl) {
2325 kvm_mmu_unload(&svm->vcpu);
2326 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2327 nested_svm_init_mmu_context(&svm->vcpu);
2328 }
2329
2330 /* Load the nested guest state */
2331 svm->vmcb->save.es = nested_vmcb->save.es;
2332 svm->vmcb->save.cs = nested_vmcb->save.cs;
2333 svm->vmcb->save.ss = nested_vmcb->save.ss;
2334 svm->vmcb->save.ds = nested_vmcb->save.ds;
2335 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2336 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2337 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2338 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2339 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2340 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2341 if (npt_enabled) {
2342 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2343 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2344 } else
2345 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2346
2347 /* Guest paging mode is active - reset mmu */
2348 kvm_mmu_reset_context(&svm->vcpu);
2349
2350 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2351 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2352 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2353 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2354
2355 /* In case we don't even reach vcpu_run, the fields are not updated */
2356 svm->vmcb->save.rax = nested_vmcb->save.rax;
2357 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2358 svm->vmcb->save.rip = nested_vmcb->save.rip;
2359 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2360 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2361 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2362
2363 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2364 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2365
2366 /* cache intercepts */
2367 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2368 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2369 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2370 svm->nested.intercept = nested_vmcb->control.intercept;
2371
2372 force_new_asid(&svm->vcpu);
2373 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2374 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2375 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2376 else
2377 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2378
2379 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2380 /* We only want the cr8 intercept bits of the guest */
2381 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2382 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2383 }
2384
2385 /* We don't want to see VMMCALLs from a nested guest */
2386 clr_intercept(svm, INTERCEPT_VMMCALL);
2387
2388 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2389 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2390 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2391 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2392 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2393 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2394
2395 nested_svm_unmap(page);
2396
2397 /* Enter Guest-Mode */
2398 enter_guest_mode(&svm->vcpu);
2399
2400 /*
2401 * Merge guest and host intercepts - must be called with vcpu in
2402 * guest-mode to take affect here
2403 */
2404 recalc_intercepts(svm);
2405
2406 svm->nested.vmcb = vmcb_gpa;
2407
2408 enable_gif(svm);
2409
2410 mark_all_dirty(svm->vmcb);
2411
2412 return true;
2413 }
2414
2415 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2416 {
2417 to_vmcb->save.fs = from_vmcb->save.fs;
2418 to_vmcb->save.gs = from_vmcb->save.gs;
2419 to_vmcb->save.tr = from_vmcb->save.tr;
2420 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2421 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2422 to_vmcb->save.star = from_vmcb->save.star;
2423 to_vmcb->save.lstar = from_vmcb->save.lstar;
2424 to_vmcb->save.cstar = from_vmcb->save.cstar;
2425 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2426 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2427 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2428 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2429 }
2430
2431 static int vmload_interception(struct vcpu_svm *svm)
2432 {
2433 struct vmcb *nested_vmcb;
2434 struct page *page;
2435
2436 if (nested_svm_check_permissions(svm))
2437 return 1;
2438
2439 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2440 skip_emulated_instruction(&svm->vcpu);
2441
2442 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2443 if (!nested_vmcb)
2444 return 1;
2445
2446 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2447 nested_svm_unmap(page);
2448
2449 return 1;
2450 }
2451
2452 static int vmsave_interception(struct vcpu_svm *svm)
2453 {
2454 struct vmcb *nested_vmcb;
2455 struct page *page;
2456
2457 if (nested_svm_check_permissions(svm))
2458 return 1;
2459
2460 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2461 skip_emulated_instruction(&svm->vcpu);
2462
2463 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2464 if (!nested_vmcb)
2465 return 1;
2466
2467 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2468 nested_svm_unmap(page);
2469
2470 return 1;
2471 }
2472
2473 static int vmrun_interception(struct vcpu_svm *svm)
2474 {
2475 if (nested_svm_check_permissions(svm))
2476 return 1;
2477
2478 /* Save rip after vmrun instruction */
2479 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2480
2481 if (!nested_svm_vmrun(svm))
2482 return 1;
2483
2484 if (!nested_svm_vmrun_msrpm(svm))
2485 goto failed;
2486
2487 return 1;
2488
2489 failed:
2490
2491 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2492 svm->vmcb->control.exit_code_hi = 0;
2493 svm->vmcb->control.exit_info_1 = 0;
2494 svm->vmcb->control.exit_info_2 = 0;
2495
2496 nested_svm_vmexit(svm);
2497
2498 return 1;
2499 }
2500
2501 static int stgi_interception(struct vcpu_svm *svm)
2502 {
2503 if (nested_svm_check_permissions(svm))
2504 return 1;
2505
2506 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2507 skip_emulated_instruction(&svm->vcpu);
2508 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2509
2510 enable_gif(svm);
2511
2512 return 1;
2513 }
2514
2515 static int clgi_interception(struct vcpu_svm *svm)
2516 {
2517 if (nested_svm_check_permissions(svm))
2518 return 1;
2519
2520 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2521 skip_emulated_instruction(&svm->vcpu);
2522
2523 disable_gif(svm);
2524
2525 /* After a CLGI no interrupts should come */
2526 svm_clear_vintr(svm);
2527 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2528
2529 mark_dirty(svm->vmcb, VMCB_INTR);
2530
2531 return 1;
2532 }
2533
2534 static int invlpga_interception(struct vcpu_svm *svm)
2535 {
2536 struct kvm_vcpu *vcpu = &svm->vcpu;
2537
2538 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2539 vcpu->arch.regs[VCPU_REGS_RAX]);
2540
2541 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2542 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2543
2544 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2545 skip_emulated_instruction(&svm->vcpu);
2546 return 1;
2547 }
2548
2549 static int skinit_interception(struct vcpu_svm *svm)
2550 {
2551 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2552
2553 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2554 return 1;
2555 }
2556
2557 static int invalid_op_interception(struct vcpu_svm *svm)
2558 {
2559 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2560 return 1;
2561 }
2562
2563 static int task_switch_interception(struct vcpu_svm *svm)
2564 {
2565 u16 tss_selector;
2566 int reason;
2567 int int_type = svm->vmcb->control.exit_int_info &
2568 SVM_EXITINTINFO_TYPE_MASK;
2569 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2570 uint32_t type =
2571 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2572 uint32_t idt_v =
2573 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2574 bool has_error_code = false;
2575 u32 error_code = 0;
2576
2577 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2578
2579 if (svm->vmcb->control.exit_info_2 &
2580 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2581 reason = TASK_SWITCH_IRET;
2582 else if (svm->vmcb->control.exit_info_2 &
2583 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2584 reason = TASK_SWITCH_JMP;
2585 else if (idt_v)
2586 reason = TASK_SWITCH_GATE;
2587 else
2588 reason = TASK_SWITCH_CALL;
2589
2590 if (reason == TASK_SWITCH_GATE) {
2591 switch (type) {
2592 case SVM_EXITINTINFO_TYPE_NMI:
2593 svm->vcpu.arch.nmi_injected = false;
2594 break;
2595 case SVM_EXITINTINFO_TYPE_EXEPT:
2596 if (svm->vmcb->control.exit_info_2 &
2597 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2598 has_error_code = true;
2599 error_code =
2600 (u32)svm->vmcb->control.exit_info_2;
2601 }
2602 kvm_clear_exception_queue(&svm->vcpu);
2603 break;
2604 case SVM_EXITINTINFO_TYPE_INTR:
2605 kvm_clear_interrupt_queue(&svm->vcpu);
2606 break;
2607 default:
2608 break;
2609 }
2610 }
2611
2612 if (reason != TASK_SWITCH_GATE ||
2613 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2614 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2615 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2616 skip_emulated_instruction(&svm->vcpu);
2617
2618 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2619 has_error_code, error_code) == EMULATE_FAIL) {
2620 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2621 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2622 svm->vcpu.run->internal.ndata = 0;
2623 return 0;
2624 }
2625 return 1;
2626 }
2627
2628 static int cpuid_interception(struct vcpu_svm *svm)
2629 {
2630 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2631 kvm_emulate_cpuid(&svm->vcpu);
2632 return 1;
2633 }
2634
2635 static int iret_interception(struct vcpu_svm *svm)
2636 {
2637 ++svm->vcpu.stat.nmi_window_exits;
2638 clr_intercept(svm, INTERCEPT_IRET);
2639 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2640 return 1;
2641 }
2642
2643 static int invlpg_interception(struct vcpu_svm *svm)
2644 {
2645 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2646 }
2647
2648 static int emulate_on_interception(struct vcpu_svm *svm)
2649 {
2650 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2651 }
2652
2653 static int cr0_write_interception(struct vcpu_svm *svm)
2654 {
2655 struct kvm_vcpu *vcpu = &svm->vcpu;
2656 int r;
2657
2658 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2659
2660 if (svm->nested.vmexit_rip) {
2661 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2662 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2663 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2664 svm->nested.vmexit_rip = 0;
2665 }
2666
2667 return r == EMULATE_DONE;
2668 }
2669
2670 static int cr8_write_interception(struct vcpu_svm *svm)
2671 {
2672 struct kvm_run *kvm_run = svm->vcpu.run;
2673
2674 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2675 /* instruction emulation calls kvm_set_cr8() */
2676 emulate_instruction(&svm->vcpu, 0, 0, 0);
2677 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2678 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2679 return 1;
2680 }
2681 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2682 return 1;
2683 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2684 return 0;
2685 }
2686
2687 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2688 {
2689 struct vcpu_svm *svm = to_svm(vcpu);
2690
2691 switch (ecx) {
2692 case MSR_IA32_TSC: {
2693 struct vmcb *vmcb = get_host_vmcb(svm);
2694
2695 *data = vmcb->control.tsc_offset + native_read_tsc();
2696 break;
2697 }
2698 case MSR_STAR:
2699 *data = svm->vmcb->save.star;
2700 break;
2701 #ifdef CONFIG_X86_64
2702 case MSR_LSTAR:
2703 *data = svm->vmcb->save.lstar;
2704 break;
2705 case MSR_CSTAR:
2706 *data = svm->vmcb->save.cstar;
2707 break;
2708 case MSR_KERNEL_GS_BASE:
2709 *data = svm->vmcb->save.kernel_gs_base;
2710 break;
2711 case MSR_SYSCALL_MASK:
2712 *data = svm->vmcb->save.sfmask;
2713 break;
2714 #endif
2715 case MSR_IA32_SYSENTER_CS:
2716 *data = svm->vmcb->save.sysenter_cs;
2717 break;
2718 case MSR_IA32_SYSENTER_EIP:
2719 *data = svm->sysenter_eip;
2720 break;
2721 case MSR_IA32_SYSENTER_ESP:
2722 *data = svm->sysenter_esp;
2723 break;
2724 /*
2725 * Nobody will change the following 5 values in the VMCB so we can
2726 * safely return them on rdmsr. They will always be 0 until LBRV is
2727 * implemented.
2728 */
2729 case MSR_IA32_DEBUGCTLMSR:
2730 *data = svm->vmcb->save.dbgctl;
2731 break;
2732 case MSR_IA32_LASTBRANCHFROMIP:
2733 *data = svm->vmcb->save.br_from;
2734 break;
2735 case MSR_IA32_LASTBRANCHTOIP:
2736 *data = svm->vmcb->save.br_to;
2737 break;
2738 case MSR_IA32_LASTINTFROMIP:
2739 *data = svm->vmcb->save.last_excp_from;
2740 break;
2741 case MSR_IA32_LASTINTTOIP:
2742 *data = svm->vmcb->save.last_excp_to;
2743 break;
2744 case MSR_VM_HSAVE_PA:
2745 *data = svm->nested.hsave_msr;
2746 break;
2747 case MSR_VM_CR:
2748 *data = svm->nested.vm_cr_msr;
2749 break;
2750 case MSR_IA32_UCODE_REV:
2751 *data = 0x01000065;
2752 break;
2753 default:
2754 return kvm_get_msr_common(vcpu, ecx, data);
2755 }
2756 return 0;
2757 }
2758
2759 static int rdmsr_interception(struct vcpu_svm *svm)
2760 {
2761 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2762 u64 data;
2763
2764 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2765 trace_kvm_msr_read_ex(ecx);
2766 kvm_inject_gp(&svm->vcpu, 0);
2767 } else {
2768 trace_kvm_msr_read(ecx, data);
2769
2770 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2771 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2772 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2773 skip_emulated_instruction(&svm->vcpu);
2774 }
2775 return 1;
2776 }
2777
2778 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2779 {
2780 struct vcpu_svm *svm = to_svm(vcpu);
2781 int svm_dis, chg_mask;
2782
2783 if (data & ~SVM_VM_CR_VALID_MASK)
2784 return 1;
2785
2786 chg_mask = SVM_VM_CR_VALID_MASK;
2787
2788 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2789 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2790
2791 svm->nested.vm_cr_msr &= ~chg_mask;
2792 svm->nested.vm_cr_msr |= (data & chg_mask);
2793
2794 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2795
2796 /* check for svm_disable while efer.svme is set */
2797 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2798 return 1;
2799
2800 return 0;
2801 }
2802
2803 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2804 {
2805 struct vcpu_svm *svm = to_svm(vcpu);
2806
2807 switch (ecx) {
2808 case MSR_IA32_TSC:
2809 kvm_write_tsc(vcpu, data);
2810 break;
2811 case MSR_STAR:
2812 svm->vmcb->save.star = data;
2813 break;
2814 #ifdef CONFIG_X86_64
2815 case MSR_LSTAR:
2816 svm->vmcb->save.lstar = data;
2817 break;
2818 case MSR_CSTAR:
2819 svm->vmcb->save.cstar = data;
2820 break;
2821 case MSR_KERNEL_GS_BASE:
2822 svm->vmcb->save.kernel_gs_base = data;
2823 break;
2824 case MSR_SYSCALL_MASK:
2825 svm->vmcb->save.sfmask = data;
2826 break;
2827 #endif
2828 case MSR_IA32_SYSENTER_CS:
2829 svm->vmcb->save.sysenter_cs = data;
2830 break;
2831 case MSR_IA32_SYSENTER_EIP:
2832 svm->sysenter_eip = data;
2833 svm->vmcb->save.sysenter_eip = data;
2834 break;
2835 case MSR_IA32_SYSENTER_ESP:
2836 svm->sysenter_esp = data;
2837 svm->vmcb->save.sysenter_esp = data;
2838 break;
2839 case MSR_IA32_DEBUGCTLMSR:
2840 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2841 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2842 __func__, data);
2843 break;
2844 }
2845 if (data & DEBUGCTL_RESERVED_BITS)
2846 return 1;
2847
2848 svm->vmcb->save.dbgctl = data;
2849 if (data & (1ULL<<0))
2850 svm_enable_lbrv(svm);
2851 else
2852 svm_disable_lbrv(svm);
2853 break;
2854 case MSR_VM_HSAVE_PA:
2855 svm->nested.hsave_msr = data;
2856 break;
2857 case MSR_VM_CR:
2858 return svm_set_vm_cr(vcpu, data);
2859 case MSR_VM_IGNNE:
2860 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2861 break;
2862 default:
2863 return kvm_set_msr_common(vcpu, ecx, data);
2864 }
2865 return 0;
2866 }
2867
2868 static int wrmsr_interception(struct vcpu_svm *svm)
2869 {
2870 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2871 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2872 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2873
2874
2875 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2876 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2877 trace_kvm_msr_write_ex(ecx, data);
2878 kvm_inject_gp(&svm->vcpu, 0);
2879 } else {
2880 trace_kvm_msr_write(ecx, data);
2881 skip_emulated_instruction(&svm->vcpu);
2882 }
2883 return 1;
2884 }
2885
2886 static int msr_interception(struct vcpu_svm *svm)
2887 {
2888 if (svm->vmcb->control.exit_info_1)
2889 return wrmsr_interception(svm);
2890 else
2891 return rdmsr_interception(svm);
2892 }
2893
2894 static int interrupt_window_interception(struct vcpu_svm *svm)
2895 {
2896 struct kvm_run *kvm_run = svm->vcpu.run;
2897
2898 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2899 svm_clear_vintr(svm);
2900 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2901 mark_dirty(svm->vmcb, VMCB_INTR);
2902 /*
2903 * If the user space waits to inject interrupts, exit as soon as
2904 * possible
2905 */
2906 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2907 kvm_run->request_interrupt_window &&
2908 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2909 ++svm->vcpu.stat.irq_window_exits;
2910 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2911 return 0;
2912 }
2913
2914 return 1;
2915 }
2916
2917 static int pause_interception(struct vcpu_svm *svm)
2918 {
2919 kvm_vcpu_on_spin(&(svm->vcpu));
2920 return 1;
2921 }
2922
2923 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2924 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2925 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2926 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2927 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2928 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2929 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2930 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2931 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2932 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2933 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2934 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2935 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2936 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2937 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2938 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2939 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2940 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2941 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2942 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2943 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2944 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2945 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2946 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2947 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2948 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2949 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2950 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2951 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2952 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2953 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2954 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2955 [SVM_EXIT_INTR] = intr_interception,
2956 [SVM_EXIT_NMI] = nmi_interception,
2957 [SVM_EXIT_SMI] = nop_on_interception,
2958 [SVM_EXIT_INIT] = nop_on_interception,
2959 [SVM_EXIT_VINTR] = interrupt_window_interception,
2960 [SVM_EXIT_CPUID] = cpuid_interception,
2961 [SVM_EXIT_IRET] = iret_interception,
2962 [SVM_EXIT_INVD] = emulate_on_interception,
2963 [SVM_EXIT_PAUSE] = pause_interception,
2964 [SVM_EXIT_HLT] = halt_interception,
2965 [SVM_EXIT_INVLPG] = invlpg_interception,
2966 [SVM_EXIT_INVLPGA] = invlpga_interception,
2967 [SVM_EXIT_IOIO] = io_interception,
2968 [SVM_EXIT_MSR] = msr_interception,
2969 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2970 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2971 [SVM_EXIT_VMRUN] = vmrun_interception,
2972 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2973 [SVM_EXIT_VMLOAD] = vmload_interception,
2974 [SVM_EXIT_VMSAVE] = vmsave_interception,
2975 [SVM_EXIT_STGI] = stgi_interception,
2976 [SVM_EXIT_CLGI] = clgi_interception,
2977 [SVM_EXIT_SKINIT] = skinit_interception,
2978 [SVM_EXIT_WBINVD] = emulate_on_interception,
2979 [SVM_EXIT_MONITOR] = invalid_op_interception,
2980 [SVM_EXIT_MWAIT] = invalid_op_interception,
2981 [SVM_EXIT_NPF] = pf_interception,
2982 };
2983
2984 void dump_vmcb(struct kvm_vcpu *vcpu)
2985 {
2986 struct vcpu_svm *svm = to_svm(vcpu);
2987 struct vmcb_control_area *control = &svm->vmcb->control;
2988 struct vmcb_save_area *save = &svm->vmcb->save;
2989
2990 pr_err("VMCB Control Area:\n");
2991 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2992 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2993 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2994 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2995 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2996 pr_err("intercepts: %016llx\n", control->intercept);
2997 pr_err("pause filter count: %d\n", control->pause_filter_count);
2998 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2999 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
3000 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
3001 pr_err("asid: %d\n", control->asid);
3002 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3003 pr_err("int_ctl: %08x\n", control->int_ctl);
3004 pr_err("int_vector: %08x\n", control->int_vector);
3005 pr_err("int_state: %08x\n", control->int_state);
3006 pr_err("exit_code: %08x\n", control->exit_code);
3007 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3008 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3009 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3010 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3011 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3012 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3013 pr_err("event_inj: %08x\n", control->event_inj);
3014 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3015 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3016 pr_err("next_rip: %016llx\n", control->next_rip);
3017 pr_err("VMCB State Save Area:\n");
3018 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3019 save->es.selector, save->es.attrib,
3020 save->es.limit, save->es.base);
3021 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3022 save->cs.selector, save->cs.attrib,
3023 save->cs.limit, save->cs.base);
3024 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3025 save->ss.selector, save->ss.attrib,
3026 save->ss.limit, save->ss.base);
3027 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3028 save->ds.selector, save->ds.attrib,
3029 save->ds.limit, save->ds.base);
3030 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3031 save->fs.selector, save->fs.attrib,
3032 save->fs.limit, save->fs.base);
3033 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3034 save->gs.selector, save->gs.attrib,
3035 save->gs.limit, save->gs.base);
3036 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3037 save->gdtr.selector, save->gdtr.attrib,
3038 save->gdtr.limit, save->gdtr.base);
3039 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3040 save->ldtr.selector, save->ldtr.attrib,
3041 save->ldtr.limit, save->ldtr.base);
3042 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3043 save->idtr.selector, save->idtr.attrib,
3044 save->idtr.limit, save->idtr.base);
3045 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3046 save->tr.selector, save->tr.attrib,
3047 save->tr.limit, save->tr.base);
3048 pr_err("cpl: %d efer: %016llx\n",
3049 save->cpl, save->efer);
3050 pr_err("cr0: %016llx cr2: %016llx\n",
3051 save->cr0, save->cr2);
3052 pr_err("cr3: %016llx cr4: %016llx\n",
3053 save->cr3, save->cr4);
3054 pr_err("dr6: %016llx dr7: %016llx\n",
3055 save->dr6, save->dr7);
3056 pr_err("rip: %016llx rflags: %016llx\n",
3057 save->rip, save->rflags);
3058 pr_err("rsp: %016llx rax: %016llx\n",
3059 save->rsp, save->rax);
3060 pr_err("star: %016llx lstar: %016llx\n",
3061 save->star, save->lstar);
3062 pr_err("cstar: %016llx sfmask: %016llx\n",
3063 save->cstar, save->sfmask);
3064 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3065 save->kernel_gs_base, save->sysenter_cs);
3066 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3067 save->sysenter_esp, save->sysenter_eip);
3068 pr_err("gpat: %016llx dbgctl: %016llx\n",
3069 save->g_pat, save->dbgctl);
3070 pr_err("br_from: %016llx br_to: %016llx\n",
3071 save->br_from, save->br_to);
3072 pr_err("excp_from: %016llx excp_to: %016llx\n",
3073 save->last_excp_from, save->last_excp_to);
3074
3075 }
3076
3077 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3078 {
3079 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3080
3081 *info1 = control->exit_info_1;
3082 *info2 = control->exit_info_2;
3083 }
3084
3085 static int handle_exit(struct kvm_vcpu *vcpu)
3086 {
3087 struct vcpu_svm *svm = to_svm(vcpu);
3088 struct kvm_run *kvm_run = vcpu->run;
3089 u32 exit_code = svm->vmcb->control.exit_code;
3090
3091 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3092
3093 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3094 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3095 if (npt_enabled)
3096 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3097
3098 if (unlikely(svm->nested.exit_required)) {
3099 nested_svm_vmexit(svm);
3100 svm->nested.exit_required = false;
3101
3102 return 1;
3103 }
3104
3105 if (is_guest_mode(vcpu)) {
3106 int vmexit;
3107
3108 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3109 svm->vmcb->control.exit_info_1,
3110 svm->vmcb->control.exit_info_2,
3111 svm->vmcb->control.exit_int_info,
3112 svm->vmcb->control.exit_int_info_err);
3113
3114 vmexit = nested_svm_exit_special(svm);
3115
3116 if (vmexit == NESTED_EXIT_CONTINUE)
3117 vmexit = nested_svm_exit_handled(svm);
3118
3119 if (vmexit == NESTED_EXIT_DONE)
3120 return 1;
3121 }
3122
3123 svm_complete_interrupts(svm);
3124
3125 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3126 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3127 kvm_run->fail_entry.hardware_entry_failure_reason
3128 = svm->vmcb->control.exit_code;
3129 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3130 dump_vmcb(vcpu);
3131 return 0;
3132 }
3133
3134 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3135 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3136 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3137 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3138 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3139 "exit_code 0x%x\n",
3140 __func__, svm->vmcb->control.exit_int_info,
3141 exit_code);
3142
3143 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3144 || !svm_exit_handlers[exit_code]) {
3145 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3146 kvm_run->hw.hardware_exit_reason = exit_code;
3147 return 0;
3148 }
3149
3150 return svm_exit_handlers[exit_code](svm);
3151 }
3152
3153 static void reload_tss(struct kvm_vcpu *vcpu)
3154 {
3155 int cpu = raw_smp_processor_id();
3156
3157 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3158 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3159 load_TR_desc();
3160 }
3161
3162 static void pre_svm_run(struct vcpu_svm *svm)
3163 {
3164 int cpu = raw_smp_processor_id();
3165
3166 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3167
3168 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3169 /* FIXME: handle wraparound of asid_generation */
3170 if (svm->asid_generation != sd->asid_generation)
3171 new_asid(svm, sd);
3172 }
3173
3174 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3175 {
3176 struct vcpu_svm *svm = to_svm(vcpu);
3177
3178 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3179 vcpu->arch.hflags |= HF_NMI_MASK;
3180 set_intercept(svm, INTERCEPT_IRET);
3181 ++vcpu->stat.nmi_injections;
3182 }
3183
3184 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3185 {
3186 struct vmcb_control_area *control;
3187
3188 control = &svm->vmcb->control;
3189 control->int_vector = irq;
3190 control->int_ctl &= ~V_INTR_PRIO_MASK;
3191 control->int_ctl |= V_IRQ_MASK |
3192 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3193 mark_dirty(svm->vmcb, VMCB_INTR);
3194 }
3195
3196 static void svm_set_irq(struct kvm_vcpu *vcpu)
3197 {
3198 struct vcpu_svm *svm = to_svm(vcpu);
3199
3200 BUG_ON(!(gif_set(svm)));
3201
3202 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3203 ++vcpu->stat.irq_injections;
3204
3205 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3206 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3207 }
3208
3209 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3210 {
3211 struct vcpu_svm *svm = to_svm(vcpu);
3212
3213 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3214 return;
3215
3216 if (irr == -1)
3217 return;
3218
3219 if (tpr >= irr)
3220 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3221 }
3222
3223 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3224 {
3225 struct vcpu_svm *svm = to_svm(vcpu);
3226 struct vmcb *vmcb = svm->vmcb;
3227 int ret;
3228 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3229 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3230 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3231
3232 return ret;
3233 }
3234
3235 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3236 {
3237 struct vcpu_svm *svm = to_svm(vcpu);
3238
3239 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3240 }
3241
3242 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3243 {
3244 struct vcpu_svm *svm = to_svm(vcpu);
3245
3246 if (masked) {
3247 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3248 set_intercept(svm, INTERCEPT_IRET);
3249 } else {
3250 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3251 clr_intercept(svm, INTERCEPT_IRET);
3252 }
3253 }
3254
3255 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3256 {
3257 struct vcpu_svm *svm = to_svm(vcpu);
3258 struct vmcb *vmcb = svm->vmcb;
3259 int ret;
3260
3261 if (!gif_set(svm) ||
3262 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3263 return 0;
3264
3265 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3266
3267 if (is_guest_mode(vcpu))
3268 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3269
3270 return ret;
3271 }
3272
3273 static void enable_irq_window(struct kvm_vcpu *vcpu)
3274 {
3275 struct vcpu_svm *svm = to_svm(vcpu);
3276
3277 /*
3278 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3279 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3280 * get that intercept, this function will be called again though and
3281 * we'll get the vintr intercept.
3282 */
3283 if (gif_set(svm) && nested_svm_intr(svm)) {
3284 svm_set_vintr(svm);
3285 svm_inject_irq(svm, 0x0);
3286 }
3287 }
3288
3289 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3290 {
3291 struct vcpu_svm *svm = to_svm(vcpu);
3292
3293 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3294 == HF_NMI_MASK)
3295 return; /* IRET will cause a vm exit */
3296
3297 /*
3298 * Something prevents NMI from been injected. Single step over possible
3299 * problem (IRET or exception injection or interrupt shadow)
3300 */
3301 svm->nmi_singlestep = true;
3302 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3303 update_db_intercept(vcpu);
3304 }
3305
3306 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3307 {
3308 return 0;
3309 }
3310
3311 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3312 {
3313 force_new_asid(vcpu);
3314 }
3315
3316 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3317 {
3318 }
3319
3320 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3321 {
3322 struct vcpu_svm *svm = to_svm(vcpu);
3323
3324 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3325 return;
3326
3327 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3328 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3329 kvm_set_cr8(vcpu, cr8);
3330 }
3331 }
3332
3333 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3334 {
3335 struct vcpu_svm *svm = to_svm(vcpu);
3336 u64 cr8;
3337
3338 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3339 return;
3340
3341 cr8 = kvm_get_cr8(vcpu);
3342 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3343 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3344 }
3345
3346 static void svm_complete_interrupts(struct vcpu_svm *svm)
3347 {
3348 u8 vector;
3349 int type;
3350 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3351 unsigned int3_injected = svm->int3_injected;
3352
3353 svm->int3_injected = 0;
3354
3355 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3356 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3357 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3358 }
3359
3360 svm->vcpu.arch.nmi_injected = false;
3361 kvm_clear_exception_queue(&svm->vcpu);
3362 kvm_clear_interrupt_queue(&svm->vcpu);
3363
3364 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3365 return;
3366
3367 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3368
3369 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3370 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3371
3372 switch (type) {
3373 case SVM_EXITINTINFO_TYPE_NMI:
3374 svm->vcpu.arch.nmi_injected = true;
3375 break;
3376 case SVM_EXITINTINFO_TYPE_EXEPT:
3377 /*
3378 * In case of software exceptions, do not reinject the vector,
3379 * but re-execute the instruction instead. Rewind RIP first
3380 * if we emulated INT3 before.
3381 */
3382 if (kvm_exception_is_soft(vector)) {
3383 if (vector == BP_VECTOR && int3_injected &&
3384 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3385 kvm_rip_write(&svm->vcpu,
3386 kvm_rip_read(&svm->vcpu) -
3387 int3_injected);
3388 break;
3389 }
3390 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3391 u32 err = svm->vmcb->control.exit_int_info_err;
3392 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3393
3394 } else
3395 kvm_requeue_exception(&svm->vcpu, vector);
3396 break;
3397 case SVM_EXITINTINFO_TYPE_INTR:
3398 kvm_queue_interrupt(&svm->vcpu, vector, false);
3399 break;
3400 default:
3401 break;
3402 }
3403 }
3404
3405 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3406 {
3407 struct vcpu_svm *svm = to_svm(vcpu);
3408 struct vmcb_control_area *control = &svm->vmcb->control;
3409
3410 control->exit_int_info = control->event_inj;
3411 control->exit_int_info_err = control->event_inj_err;
3412 control->event_inj = 0;
3413 svm_complete_interrupts(svm);
3414 }
3415
3416 #ifdef CONFIG_X86_64
3417 #define R "r"
3418 #else
3419 #define R "e"
3420 #endif
3421
3422 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3423 {
3424 struct vcpu_svm *svm = to_svm(vcpu);
3425
3426 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3427 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3428 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3429
3430 /*
3431 * A vmexit emulation is required before the vcpu can be executed
3432 * again.
3433 */
3434 if (unlikely(svm->nested.exit_required))
3435 return;
3436
3437 pre_svm_run(svm);
3438
3439 sync_lapic_to_cr8(vcpu);
3440
3441 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3442
3443 clgi();
3444
3445 local_irq_enable();
3446
3447 asm volatile (
3448 "push %%"R"bp; \n\t"
3449 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3450 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3451 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3452 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3453 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3454 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3455 #ifdef CONFIG_X86_64
3456 "mov %c[r8](%[svm]), %%r8 \n\t"
3457 "mov %c[r9](%[svm]), %%r9 \n\t"
3458 "mov %c[r10](%[svm]), %%r10 \n\t"
3459 "mov %c[r11](%[svm]), %%r11 \n\t"
3460 "mov %c[r12](%[svm]), %%r12 \n\t"
3461 "mov %c[r13](%[svm]), %%r13 \n\t"
3462 "mov %c[r14](%[svm]), %%r14 \n\t"
3463 "mov %c[r15](%[svm]), %%r15 \n\t"
3464 #endif
3465
3466 /* Enter guest mode */
3467 "push %%"R"ax \n\t"
3468 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3469 __ex(SVM_VMLOAD) "\n\t"
3470 __ex(SVM_VMRUN) "\n\t"
3471 __ex(SVM_VMSAVE) "\n\t"
3472 "pop %%"R"ax \n\t"
3473
3474 /* Save guest registers, load host registers */
3475 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3476 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3477 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3478 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3479 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3480 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3481 #ifdef CONFIG_X86_64
3482 "mov %%r8, %c[r8](%[svm]) \n\t"
3483 "mov %%r9, %c[r9](%[svm]) \n\t"
3484 "mov %%r10, %c[r10](%[svm]) \n\t"
3485 "mov %%r11, %c[r11](%[svm]) \n\t"
3486 "mov %%r12, %c[r12](%[svm]) \n\t"
3487 "mov %%r13, %c[r13](%[svm]) \n\t"
3488 "mov %%r14, %c[r14](%[svm]) \n\t"
3489 "mov %%r15, %c[r15](%[svm]) \n\t"
3490 #endif
3491 "pop %%"R"bp"
3492 :
3493 : [svm]"a"(svm),
3494 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3495 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3496 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3497 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3498 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3499 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3500 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3501 #ifdef CONFIG_X86_64
3502 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3503 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3504 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3505 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3506 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3507 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3508 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3509 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3510 #endif
3511 : "cc", "memory"
3512 , R"bx", R"cx", R"dx", R"si", R"di"
3513 #ifdef CONFIG_X86_64
3514 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3515 #endif
3516 );
3517
3518 #ifdef CONFIG_X86_64
3519 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3520 #else
3521 loadsegment(fs, svm->host.fs);
3522 #endif
3523
3524 reload_tss(vcpu);
3525
3526 local_irq_disable();
3527
3528 stgi();
3529
3530 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3531 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3532 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3533 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3534
3535 sync_cr8_to_lapic(vcpu);
3536
3537 svm->next_rip = 0;
3538
3539 /* if exit due to PF check for async PF */
3540 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3541 svm->apf_reason = kvm_read_and_reset_pf_reason();
3542
3543 if (npt_enabled) {
3544 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3545 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3546 }
3547
3548 /*
3549 * We need to handle MC intercepts here before the vcpu has a chance to
3550 * change the physical cpu
3551 */
3552 if (unlikely(svm->vmcb->control.exit_code ==
3553 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3554 svm_handle_mce(svm);
3555
3556 mark_all_clean(svm->vmcb);
3557 }
3558
3559 #undef R
3560
3561 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3562 {
3563 struct vcpu_svm *svm = to_svm(vcpu);
3564
3565 svm->vmcb->save.cr3 = root;
3566 mark_dirty(svm->vmcb, VMCB_CR);
3567 force_new_asid(vcpu);
3568 }
3569
3570 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3571 {
3572 struct vcpu_svm *svm = to_svm(vcpu);
3573
3574 svm->vmcb->control.nested_cr3 = root;
3575 mark_dirty(svm->vmcb, VMCB_NPT);
3576
3577 /* Also sync guest cr3 here in case we live migrate */
3578 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3579 mark_dirty(svm->vmcb, VMCB_CR);
3580
3581 force_new_asid(vcpu);
3582 }
3583
3584 static int is_disabled(void)
3585 {
3586 u64 vm_cr;
3587
3588 rdmsrl(MSR_VM_CR, vm_cr);
3589 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3590 return 1;
3591
3592 return 0;
3593 }
3594
3595 static void
3596 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3597 {
3598 /*
3599 * Patch in the VMMCALL instruction:
3600 */
3601 hypercall[0] = 0x0f;
3602 hypercall[1] = 0x01;
3603 hypercall[2] = 0xd9;
3604 }
3605
3606 static void svm_check_processor_compat(void *rtn)
3607 {
3608 *(int *)rtn = 0;
3609 }
3610
3611 static bool svm_cpu_has_accelerated_tpr(void)
3612 {
3613 return false;
3614 }
3615
3616 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3617 {
3618 return 0;
3619 }
3620
3621 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3622 {
3623 }
3624
3625 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3626 {
3627 switch (func) {
3628 case 0x00000001:
3629 /* Mask out xsave bit as long as it is not supported by SVM */
3630 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3631 break;
3632 case 0x80000001:
3633 if (nested)
3634 entry->ecx |= (1 << 2); /* Set SVM bit */
3635 break;
3636 case 0x8000000A:
3637 entry->eax = 1; /* SVM revision 1 */
3638 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3639 ASID emulation to nested SVM */
3640 entry->ecx = 0; /* Reserved */
3641 entry->edx = 0; /* Per default do not support any
3642 additional features */
3643
3644 /* Support next_rip if host supports it */
3645 if (boot_cpu_has(X86_FEATURE_NRIPS))
3646 entry->edx |= SVM_FEATURE_NRIP;
3647
3648 /* Support NPT for the guest if enabled */
3649 if (npt_enabled)
3650 entry->edx |= SVM_FEATURE_NPT;
3651
3652 break;
3653 }
3654 }
3655
3656 static const struct trace_print_flags svm_exit_reasons_str[] = {
3657 { SVM_EXIT_READ_CR0, "read_cr0" },
3658 { SVM_EXIT_READ_CR3, "read_cr3" },
3659 { SVM_EXIT_READ_CR4, "read_cr4" },
3660 { SVM_EXIT_READ_CR8, "read_cr8" },
3661 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3662 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3663 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3664 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3665 { SVM_EXIT_READ_DR0, "read_dr0" },
3666 { SVM_EXIT_READ_DR1, "read_dr1" },
3667 { SVM_EXIT_READ_DR2, "read_dr2" },
3668 { SVM_EXIT_READ_DR3, "read_dr3" },
3669 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3670 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3671 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3672 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3673 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3674 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3675 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3676 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3677 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3678 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3679 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3680 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3681 { SVM_EXIT_INTR, "interrupt" },
3682 { SVM_EXIT_NMI, "nmi" },
3683 { SVM_EXIT_SMI, "smi" },
3684 { SVM_EXIT_INIT, "init" },
3685 { SVM_EXIT_VINTR, "vintr" },
3686 { SVM_EXIT_CPUID, "cpuid" },
3687 { SVM_EXIT_INVD, "invd" },
3688 { SVM_EXIT_HLT, "hlt" },
3689 { SVM_EXIT_INVLPG, "invlpg" },
3690 { SVM_EXIT_INVLPGA, "invlpga" },
3691 { SVM_EXIT_IOIO, "io" },
3692 { SVM_EXIT_MSR, "msr" },
3693 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3694 { SVM_EXIT_SHUTDOWN, "shutdown" },
3695 { SVM_EXIT_VMRUN, "vmrun" },
3696 { SVM_EXIT_VMMCALL, "hypercall" },
3697 { SVM_EXIT_VMLOAD, "vmload" },
3698 { SVM_EXIT_VMSAVE, "vmsave" },
3699 { SVM_EXIT_STGI, "stgi" },
3700 { SVM_EXIT_CLGI, "clgi" },
3701 { SVM_EXIT_SKINIT, "skinit" },
3702 { SVM_EXIT_WBINVD, "wbinvd" },
3703 { SVM_EXIT_MONITOR, "monitor" },
3704 { SVM_EXIT_MWAIT, "mwait" },
3705 { SVM_EXIT_NPF, "npf" },
3706 { -1, NULL }
3707 };
3708
3709 static int svm_get_lpage_level(void)
3710 {
3711 return PT_PDPE_LEVEL;
3712 }
3713
3714 static bool svm_rdtscp_supported(void)
3715 {
3716 return false;
3717 }
3718
3719 static bool svm_has_wbinvd_exit(void)
3720 {
3721 return true;
3722 }
3723
3724 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3725 {
3726 struct vcpu_svm *svm = to_svm(vcpu);
3727
3728 set_exception_intercept(svm, NM_VECTOR);
3729 update_cr0_intercept(svm);
3730 }
3731
3732 static struct kvm_x86_ops svm_x86_ops = {
3733 .cpu_has_kvm_support = has_svm,
3734 .disabled_by_bios = is_disabled,
3735 .hardware_setup = svm_hardware_setup,
3736 .hardware_unsetup = svm_hardware_unsetup,
3737 .check_processor_compatibility = svm_check_processor_compat,
3738 .hardware_enable = svm_hardware_enable,
3739 .hardware_disable = svm_hardware_disable,
3740 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3741
3742 .vcpu_create = svm_create_vcpu,
3743 .vcpu_free = svm_free_vcpu,
3744 .vcpu_reset = svm_vcpu_reset,
3745
3746 .prepare_guest_switch = svm_prepare_guest_switch,
3747 .vcpu_load = svm_vcpu_load,
3748 .vcpu_put = svm_vcpu_put,
3749
3750 .set_guest_debug = svm_guest_debug,
3751 .get_msr = svm_get_msr,
3752 .set_msr = svm_set_msr,
3753 .get_segment_base = svm_get_segment_base,
3754 .get_segment = svm_get_segment,
3755 .set_segment = svm_set_segment,
3756 .get_cpl = svm_get_cpl,
3757 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3758 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3759 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3760 .set_cr0 = svm_set_cr0,
3761 .set_cr3 = svm_set_cr3,
3762 .set_cr4 = svm_set_cr4,
3763 .set_efer = svm_set_efer,
3764 .get_idt = svm_get_idt,
3765 .set_idt = svm_set_idt,
3766 .get_gdt = svm_get_gdt,
3767 .set_gdt = svm_set_gdt,
3768 .set_dr7 = svm_set_dr7,
3769 .cache_reg = svm_cache_reg,
3770 .get_rflags = svm_get_rflags,
3771 .set_rflags = svm_set_rflags,
3772 .fpu_activate = svm_fpu_activate,
3773 .fpu_deactivate = svm_fpu_deactivate,
3774
3775 .tlb_flush = svm_flush_tlb,
3776
3777 .run = svm_vcpu_run,
3778 .handle_exit = handle_exit,
3779 .skip_emulated_instruction = skip_emulated_instruction,
3780 .set_interrupt_shadow = svm_set_interrupt_shadow,
3781 .get_interrupt_shadow = svm_get_interrupt_shadow,
3782 .patch_hypercall = svm_patch_hypercall,
3783 .set_irq = svm_set_irq,
3784 .set_nmi = svm_inject_nmi,
3785 .queue_exception = svm_queue_exception,
3786 .cancel_injection = svm_cancel_injection,
3787 .interrupt_allowed = svm_interrupt_allowed,
3788 .nmi_allowed = svm_nmi_allowed,
3789 .get_nmi_mask = svm_get_nmi_mask,
3790 .set_nmi_mask = svm_set_nmi_mask,
3791 .enable_nmi_window = enable_nmi_window,
3792 .enable_irq_window = enable_irq_window,
3793 .update_cr8_intercept = update_cr8_intercept,
3794
3795 .set_tss_addr = svm_set_tss_addr,
3796 .get_tdp_level = get_npt_level,
3797 .get_mt_mask = svm_get_mt_mask,
3798
3799 .get_exit_info = svm_get_exit_info,
3800 .exit_reasons_str = svm_exit_reasons_str,
3801
3802 .get_lpage_level = svm_get_lpage_level,
3803
3804 .cpuid_update = svm_cpuid_update,
3805
3806 .rdtscp_supported = svm_rdtscp_supported,
3807
3808 .set_supported_cpuid = svm_set_supported_cpuid,
3809
3810 .has_wbinvd_exit = svm_has_wbinvd_exit,
3811
3812 .write_tsc_offset = svm_write_tsc_offset,
3813 .adjust_tsc_offset = svm_adjust_tsc_offset,
3814
3815 .set_tdp_cr3 = set_tdp_cr3,
3816 };
3817
3818 static int __init svm_init(void)
3819 {
3820 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3821 __alignof__(struct vcpu_svm), THIS_MODULE);
3822 }
3823
3824 static void __exit svm_exit(void)
3825 {
3826 kvm_exit();
3827 }
3828
3829 module_init(svm_init)
3830 module_exit(svm_exit)
Linux kernel - Deliverables
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