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KVM: SVM: Add clean-bit for intercetps, tsc-offset and pause filter count
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_DIRTY_MAX,
192 };
193
194 #define VMCB_ALWAYS_DIRTY_MASK 0U
195
196 static inline void mark_all_dirty(struct vmcb *vmcb)
197 {
198 vmcb->control.clean = 0;
199 }
200
201 static inline void mark_all_clean(struct vmcb *vmcb)
202 {
203 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
204 & ~VMCB_ALWAYS_DIRTY_MASK;
205 }
206
207 static inline void mark_dirty(struct vmcb *vmcb, int bit)
208 {
209 vmcb->control.clean &= ~(1 << bit);
210 }
211
212 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
213 {
214 return container_of(vcpu, struct vcpu_svm, vcpu);
215 }
216
217 static void recalc_intercepts(struct vcpu_svm *svm)
218 {
219 struct vmcb_control_area *c, *h;
220 struct nested_state *g;
221
222 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
223
224 if (!is_guest_mode(&svm->vcpu))
225 return;
226
227 c = &svm->vmcb->control;
228 h = &svm->nested.hsave->control;
229 g = &svm->nested;
230
231 c->intercept_cr = h->intercept_cr | g->intercept_cr;
232 c->intercept_dr = h->intercept_dr | g->intercept_dr;
233 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
234 c->intercept = h->intercept | g->intercept;
235 }
236
237 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
238 {
239 if (is_guest_mode(&svm->vcpu))
240 return svm->nested.hsave;
241 else
242 return svm->vmcb;
243 }
244
245 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
246 {
247 struct vmcb *vmcb = get_host_vmcb(svm);
248
249 vmcb->control.intercept_cr |= (1U << bit);
250
251 recalc_intercepts(svm);
252 }
253
254 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
255 {
256 struct vmcb *vmcb = get_host_vmcb(svm);
257
258 vmcb->control.intercept_cr &= ~(1U << bit);
259
260 recalc_intercepts(svm);
261 }
262
263 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
264 {
265 struct vmcb *vmcb = get_host_vmcb(svm);
266
267 return vmcb->control.intercept_cr & (1U << bit);
268 }
269
270 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
271 {
272 struct vmcb *vmcb = get_host_vmcb(svm);
273
274 vmcb->control.intercept_dr |= (1U << bit);
275
276 recalc_intercepts(svm);
277 }
278
279 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
280 {
281 struct vmcb *vmcb = get_host_vmcb(svm);
282
283 vmcb->control.intercept_dr &= ~(1U << bit);
284
285 recalc_intercepts(svm);
286 }
287
288 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
289 {
290 struct vmcb *vmcb = get_host_vmcb(svm);
291
292 vmcb->control.intercept_exceptions |= (1U << bit);
293
294 recalc_intercepts(svm);
295 }
296
297 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
298 {
299 struct vmcb *vmcb = get_host_vmcb(svm);
300
301 vmcb->control.intercept_exceptions &= ~(1U << bit);
302
303 recalc_intercepts(svm);
304 }
305
306 static inline void set_intercept(struct vcpu_svm *svm, int bit)
307 {
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept |= (1ULL << bit);
311
312 recalc_intercepts(svm);
313 }
314
315 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
316 {
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept &= ~(1ULL << bit);
320
321 recalc_intercepts(svm);
322 }
323
324 static inline void enable_gif(struct vcpu_svm *svm)
325 {
326 svm->vcpu.arch.hflags |= HF_GIF_MASK;
327 }
328
329 static inline void disable_gif(struct vcpu_svm *svm)
330 {
331 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
332 }
333
334 static inline bool gif_set(struct vcpu_svm *svm)
335 {
336 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
337 }
338
339 static unsigned long iopm_base;
340
341 struct kvm_ldttss_desc {
342 u16 limit0;
343 u16 base0;
344 unsigned base1:8, type:5, dpl:2, p:1;
345 unsigned limit1:4, zero0:3, g:1, base2:8;
346 u32 base3;
347 u32 zero1;
348 } __attribute__((packed));
349
350 struct svm_cpu_data {
351 int cpu;
352
353 u64 asid_generation;
354 u32 max_asid;
355 u32 next_asid;
356 struct kvm_ldttss_desc *tss_desc;
357
358 struct page *save_area;
359 };
360
361 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
362 static uint32_t svm_features;
363
364 struct svm_init_data {
365 int cpu;
366 int r;
367 };
368
369 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
370
371 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
372 #define MSRS_RANGE_SIZE 2048
373 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
374
375 static u32 svm_msrpm_offset(u32 msr)
376 {
377 u32 offset;
378 int i;
379
380 for (i = 0; i < NUM_MSR_MAPS; i++) {
381 if (msr < msrpm_ranges[i] ||
382 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
383 continue;
384
385 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
386 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
387
388 /* Now we have the u8 offset - but need the u32 offset */
389 return offset / 4;
390 }
391
392 /* MSR not in any range */
393 return MSR_INVALID;
394 }
395
396 #define MAX_INST_SIZE 15
397
398 static inline void clgi(void)
399 {
400 asm volatile (__ex(SVM_CLGI));
401 }
402
403 static inline void stgi(void)
404 {
405 asm volatile (__ex(SVM_STGI));
406 }
407
408 static inline void invlpga(unsigned long addr, u32 asid)
409 {
410 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
411 }
412
413 static inline void force_new_asid(struct kvm_vcpu *vcpu)
414 {
415 to_svm(vcpu)->asid_generation--;
416 }
417
418 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
419 {
420 force_new_asid(vcpu);
421 }
422
423 static int get_npt_level(void)
424 {
425 #ifdef CONFIG_X86_64
426 return PT64_ROOT_LEVEL;
427 #else
428 return PT32E_ROOT_LEVEL;
429 #endif
430 }
431
432 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
433 {
434 vcpu->arch.efer = efer;
435 if (!npt_enabled && !(efer & EFER_LMA))
436 efer &= ~EFER_LME;
437
438 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
439 }
440
441 static int is_external_interrupt(u32 info)
442 {
443 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
444 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
445 }
446
447 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
448 {
449 struct vcpu_svm *svm = to_svm(vcpu);
450 u32 ret = 0;
451
452 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
453 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
454 return ret & mask;
455 }
456
457 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
458 {
459 struct vcpu_svm *svm = to_svm(vcpu);
460
461 if (mask == 0)
462 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
463 else
464 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
465
466 }
467
468 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
469 {
470 struct vcpu_svm *svm = to_svm(vcpu);
471
472 if (svm->vmcb->control.next_rip != 0)
473 svm->next_rip = svm->vmcb->control.next_rip;
474
475 if (!svm->next_rip) {
476 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
477 EMULATE_DONE)
478 printk(KERN_DEBUG "%s: NOP\n", __func__);
479 return;
480 }
481 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
482 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
483 __func__, kvm_rip_read(vcpu), svm->next_rip);
484
485 kvm_rip_write(vcpu, svm->next_rip);
486 svm_set_interrupt_shadow(vcpu, 0);
487 }
488
489 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
490 bool has_error_code, u32 error_code,
491 bool reinject)
492 {
493 struct vcpu_svm *svm = to_svm(vcpu);
494
495 /*
496 * If we are within a nested VM we'd better #VMEXIT and let the guest
497 * handle the exception
498 */
499 if (!reinject &&
500 nested_svm_check_exception(svm, nr, has_error_code, error_code))
501 return;
502
503 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
504 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
505
506 /*
507 * For guest debugging where we have to reinject #BP if some
508 * INT3 is guest-owned:
509 * Emulate nRIP by moving RIP forward. Will fail if injection
510 * raises a fault that is not intercepted. Still better than
511 * failing in all cases.
512 */
513 skip_emulated_instruction(&svm->vcpu);
514 rip = kvm_rip_read(&svm->vcpu);
515 svm->int3_rip = rip + svm->vmcb->save.cs.base;
516 svm->int3_injected = rip - old_rip;
517 }
518
519 svm->vmcb->control.event_inj = nr
520 | SVM_EVTINJ_VALID
521 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
522 | SVM_EVTINJ_TYPE_EXEPT;
523 svm->vmcb->control.event_inj_err = error_code;
524 }
525
526 static void svm_init_erratum_383(void)
527 {
528 u32 low, high;
529 int err;
530 u64 val;
531
532 if (!cpu_has_amd_erratum(amd_erratum_383))
533 return;
534
535 /* Use _safe variants to not break nested virtualization */
536 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
537 if (err)
538 return;
539
540 val |= (1ULL << 47);
541
542 low = lower_32_bits(val);
543 high = upper_32_bits(val);
544
545 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
546
547 erratum_383_found = true;
548 }
549
550 static int has_svm(void)
551 {
552 const char *msg;
553
554 if (!cpu_has_svm(&msg)) {
555 printk(KERN_INFO "has_svm: %s\n", msg);
556 return 0;
557 }
558
559 return 1;
560 }
561
562 static void svm_hardware_disable(void *garbage)
563 {
564 cpu_svm_disable();
565 }
566
567 static int svm_hardware_enable(void *garbage)
568 {
569
570 struct svm_cpu_data *sd;
571 uint64_t efer;
572 struct desc_ptr gdt_descr;
573 struct desc_struct *gdt;
574 int me = raw_smp_processor_id();
575
576 rdmsrl(MSR_EFER, efer);
577 if (efer & EFER_SVME)
578 return -EBUSY;
579
580 if (!has_svm()) {
581 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
582 me);
583 return -EINVAL;
584 }
585 sd = per_cpu(svm_data, me);
586
587 if (!sd) {
588 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
589 me);
590 return -EINVAL;
591 }
592
593 sd->asid_generation = 1;
594 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
595 sd->next_asid = sd->max_asid + 1;
596
597 native_store_gdt(&gdt_descr);
598 gdt = (struct desc_struct *)gdt_descr.address;
599 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
600
601 wrmsrl(MSR_EFER, efer | EFER_SVME);
602
603 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
604
605 svm_init_erratum_383();
606
607 return 0;
608 }
609
610 static void svm_cpu_uninit(int cpu)
611 {
612 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
613
614 if (!sd)
615 return;
616
617 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
618 __free_page(sd->save_area);
619 kfree(sd);
620 }
621
622 static int svm_cpu_init(int cpu)
623 {
624 struct svm_cpu_data *sd;
625 int r;
626
627 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
628 if (!sd)
629 return -ENOMEM;
630 sd->cpu = cpu;
631 sd->save_area = alloc_page(GFP_KERNEL);
632 r = -ENOMEM;
633 if (!sd->save_area)
634 goto err_1;
635
636 per_cpu(svm_data, cpu) = sd;
637
638 return 0;
639
640 err_1:
641 kfree(sd);
642 return r;
643
644 }
645
646 static bool valid_msr_intercept(u32 index)
647 {
648 int i;
649
650 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
651 if (direct_access_msrs[i].index == index)
652 return true;
653
654 return false;
655 }
656
657 static void set_msr_interception(u32 *msrpm, unsigned msr,
658 int read, int write)
659 {
660 u8 bit_read, bit_write;
661 unsigned long tmp;
662 u32 offset;
663
664 /*
665 * If this warning triggers extend the direct_access_msrs list at the
666 * beginning of the file
667 */
668 WARN_ON(!valid_msr_intercept(msr));
669
670 offset = svm_msrpm_offset(msr);
671 bit_read = 2 * (msr & 0x0f);
672 bit_write = 2 * (msr & 0x0f) + 1;
673 tmp = msrpm[offset];
674
675 BUG_ON(offset == MSR_INVALID);
676
677 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
678 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
679
680 msrpm[offset] = tmp;
681 }
682
683 static void svm_vcpu_init_msrpm(u32 *msrpm)
684 {
685 int i;
686
687 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
688
689 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
690 if (!direct_access_msrs[i].always)
691 continue;
692
693 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
694 }
695 }
696
697 static void add_msr_offset(u32 offset)
698 {
699 int i;
700
701 for (i = 0; i < MSRPM_OFFSETS; ++i) {
702
703 /* Offset already in list? */
704 if (msrpm_offsets[i] == offset)
705 return;
706
707 /* Slot used by another offset? */
708 if (msrpm_offsets[i] != MSR_INVALID)
709 continue;
710
711 /* Add offset to list */
712 msrpm_offsets[i] = offset;
713
714 return;
715 }
716
717 /*
718 * If this BUG triggers the msrpm_offsets table has an overflow. Just
719 * increase MSRPM_OFFSETS in this case.
720 */
721 BUG();
722 }
723
724 static void init_msrpm_offsets(void)
725 {
726 int i;
727
728 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
729
730 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
731 u32 offset;
732
733 offset = svm_msrpm_offset(direct_access_msrs[i].index);
734 BUG_ON(offset == MSR_INVALID);
735
736 add_msr_offset(offset);
737 }
738 }
739
740 static void svm_enable_lbrv(struct vcpu_svm *svm)
741 {
742 u32 *msrpm = svm->msrpm;
743
744 svm->vmcb->control.lbr_ctl = 1;
745 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
746 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
747 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
748 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
749 }
750
751 static void svm_disable_lbrv(struct vcpu_svm *svm)
752 {
753 u32 *msrpm = svm->msrpm;
754
755 svm->vmcb->control.lbr_ctl = 0;
756 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
757 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
758 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
759 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
760 }
761
762 static __init int svm_hardware_setup(void)
763 {
764 int cpu;
765 struct page *iopm_pages;
766 void *iopm_va;
767 int r;
768
769 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
770
771 if (!iopm_pages)
772 return -ENOMEM;
773
774 iopm_va = page_address(iopm_pages);
775 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
776 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
777
778 init_msrpm_offsets();
779
780 if (boot_cpu_has(X86_FEATURE_NX))
781 kvm_enable_efer_bits(EFER_NX);
782
783 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
784 kvm_enable_efer_bits(EFER_FFXSR);
785
786 if (nested) {
787 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
788 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
789 }
790
791 for_each_possible_cpu(cpu) {
792 r = svm_cpu_init(cpu);
793 if (r)
794 goto err;
795 }
796
797 svm_features = cpuid_edx(SVM_CPUID_FUNC);
798
799 if (!boot_cpu_has(X86_FEATURE_NPT))
800 npt_enabled = false;
801
802 if (npt_enabled && !npt) {
803 printk(KERN_INFO "kvm: Nested Paging disabled\n");
804 npt_enabled = false;
805 }
806
807 if (npt_enabled) {
808 printk(KERN_INFO "kvm: Nested Paging enabled\n");
809 kvm_enable_tdp();
810 } else
811 kvm_disable_tdp();
812
813 return 0;
814
815 err:
816 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
817 iopm_base = 0;
818 return r;
819 }
820
821 static __exit void svm_hardware_unsetup(void)
822 {
823 int cpu;
824
825 for_each_possible_cpu(cpu)
826 svm_cpu_uninit(cpu);
827
828 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
829 iopm_base = 0;
830 }
831
832 static void init_seg(struct vmcb_seg *seg)
833 {
834 seg->selector = 0;
835 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
836 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
837 seg->limit = 0xffff;
838 seg->base = 0;
839 }
840
841 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
842 {
843 seg->selector = 0;
844 seg->attrib = SVM_SELECTOR_P_MASK | type;
845 seg->limit = 0xffff;
846 seg->base = 0;
847 }
848
849 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
850 {
851 struct vcpu_svm *svm = to_svm(vcpu);
852 u64 g_tsc_offset = 0;
853
854 if (is_guest_mode(vcpu)) {
855 g_tsc_offset = svm->vmcb->control.tsc_offset -
856 svm->nested.hsave->control.tsc_offset;
857 svm->nested.hsave->control.tsc_offset = offset;
858 }
859
860 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
861
862 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
863 }
864
865 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
866 {
867 struct vcpu_svm *svm = to_svm(vcpu);
868
869 svm->vmcb->control.tsc_offset += adjustment;
870 if (is_guest_mode(vcpu))
871 svm->nested.hsave->control.tsc_offset += adjustment;
872 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
873 }
874
875 static void init_vmcb(struct vcpu_svm *svm)
876 {
877 struct vmcb_control_area *control = &svm->vmcb->control;
878 struct vmcb_save_area *save = &svm->vmcb->save;
879
880 svm->vcpu.fpu_active = 1;
881 svm->vcpu.arch.hflags = 0;
882
883 set_cr_intercept(svm, INTERCEPT_CR0_READ);
884 set_cr_intercept(svm, INTERCEPT_CR3_READ);
885 set_cr_intercept(svm, INTERCEPT_CR4_READ);
886 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
887 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
888 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
889 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
890
891 set_dr_intercept(svm, INTERCEPT_DR0_READ);
892 set_dr_intercept(svm, INTERCEPT_DR1_READ);
893 set_dr_intercept(svm, INTERCEPT_DR2_READ);
894 set_dr_intercept(svm, INTERCEPT_DR3_READ);
895 set_dr_intercept(svm, INTERCEPT_DR4_READ);
896 set_dr_intercept(svm, INTERCEPT_DR5_READ);
897 set_dr_intercept(svm, INTERCEPT_DR6_READ);
898 set_dr_intercept(svm, INTERCEPT_DR7_READ);
899
900 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
901 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
902 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
903 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
904 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
908
909 set_exception_intercept(svm, PF_VECTOR);
910 set_exception_intercept(svm, UD_VECTOR);
911 set_exception_intercept(svm, MC_VECTOR);
912
913 set_intercept(svm, INTERCEPT_INTR);
914 set_intercept(svm, INTERCEPT_NMI);
915 set_intercept(svm, INTERCEPT_SMI);
916 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
917 set_intercept(svm, INTERCEPT_CPUID);
918 set_intercept(svm, INTERCEPT_INVD);
919 set_intercept(svm, INTERCEPT_HLT);
920 set_intercept(svm, INTERCEPT_INVLPG);
921 set_intercept(svm, INTERCEPT_INVLPGA);
922 set_intercept(svm, INTERCEPT_IOIO_PROT);
923 set_intercept(svm, INTERCEPT_MSR_PROT);
924 set_intercept(svm, INTERCEPT_TASK_SWITCH);
925 set_intercept(svm, INTERCEPT_SHUTDOWN);
926 set_intercept(svm, INTERCEPT_VMRUN);
927 set_intercept(svm, INTERCEPT_VMMCALL);
928 set_intercept(svm, INTERCEPT_VMLOAD);
929 set_intercept(svm, INTERCEPT_VMSAVE);
930 set_intercept(svm, INTERCEPT_STGI);
931 set_intercept(svm, INTERCEPT_CLGI);
932 set_intercept(svm, INTERCEPT_SKINIT);
933 set_intercept(svm, INTERCEPT_WBINVD);
934 set_intercept(svm, INTERCEPT_MONITOR);
935 set_intercept(svm, INTERCEPT_MWAIT);
936
937 control->iopm_base_pa = iopm_base;
938 control->msrpm_base_pa = __pa(svm->msrpm);
939 control->int_ctl = V_INTR_MASKING_MASK;
940
941 init_seg(&save->es);
942 init_seg(&save->ss);
943 init_seg(&save->ds);
944 init_seg(&save->fs);
945 init_seg(&save->gs);
946
947 save->cs.selector = 0xf000;
948 /* Executable/Readable Code Segment */
949 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
950 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
951 save->cs.limit = 0xffff;
952 /*
953 * cs.base should really be 0xffff0000, but vmx can't handle that, so
954 * be consistent with it.
955 *
956 * Replace when we have real mode working for vmx.
957 */
958 save->cs.base = 0xf0000;
959
960 save->gdtr.limit = 0xffff;
961 save->idtr.limit = 0xffff;
962
963 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
964 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
965
966 svm_set_efer(&svm->vcpu, 0);
967 save->dr6 = 0xffff0ff0;
968 save->dr7 = 0x400;
969 save->rflags = 2;
970 save->rip = 0x0000fff0;
971 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
972
973 /*
974 * This is the guest-visible cr0 value.
975 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
976 */
977 svm->vcpu.arch.cr0 = 0;
978 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
979
980 save->cr4 = X86_CR4_PAE;
981 /* rdx = ?? */
982
983 if (npt_enabled) {
984 /* Setup VMCB for Nested Paging */
985 control->nested_ctl = 1;
986 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
987 clr_intercept(svm, INTERCEPT_INVLPG);
988 clr_exception_intercept(svm, PF_VECTOR);
989 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
990 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
991 save->g_pat = 0x0007040600070406ULL;
992 save->cr3 = 0;
993 save->cr4 = 0;
994 }
995 force_new_asid(&svm->vcpu);
996
997 svm->nested.vmcb = 0;
998 svm->vcpu.arch.hflags = 0;
999
1000 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1001 control->pause_filter_count = 3000;
1002 set_intercept(svm, INTERCEPT_PAUSE);
1003 }
1004
1005 mark_all_dirty(svm->vmcb);
1006
1007 enable_gif(svm);
1008 }
1009
1010 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1011 {
1012 struct vcpu_svm *svm = to_svm(vcpu);
1013
1014 init_vmcb(svm);
1015
1016 if (!kvm_vcpu_is_bsp(vcpu)) {
1017 kvm_rip_write(vcpu, 0);
1018 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1019 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1020 }
1021 vcpu->arch.regs_avail = ~0;
1022 vcpu->arch.regs_dirty = ~0;
1023
1024 return 0;
1025 }
1026
1027 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1028 {
1029 struct vcpu_svm *svm;
1030 struct page *page;
1031 struct page *msrpm_pages;
1032 struct page *hsave_page;
1033 struct page *nested_msrpm_pages;
1034 int err;
1035
1036 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1037 if (!svm) {
1038 err = -ENOMEM;
1039 goto out;
1040 }
1041
1042 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1043 if (err)
1044 goto free_svm;
1045
1046 err = -ENOMEM;
1047 page = alloc_page(GFP_KERNEL);
1048 if (!page)
1049 goto uninit;
1050
1051 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1052 if (!msrpm_pages)
1053 goto free_page1;
1054
1055 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1056 if (!nested_msrpm_pages)
1057 goto free_page2;
1058
1059 hsave_page = alloc_page(GFP_KERNEL);
1060 if (!hsave_page)
1061 goto free_page3;
1062
1063 svm->nested.hsave = page_address(hsave_page);
1064
1065 svm->msrpm = page_address(msrpm_pages);
1066 svm_vcpu_init_msrpm(svm->msrpm);
1067
1068 svm->nested.msrpm = page_address(nested_msrpm_pages);
1069 svm_vcpu_init_msrpm(svm->nested.msrpm);
1070
1071 svm->vmcb = page_address(page);
1072 clear_page(svm->vmcb);
1073 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1074 svm->asid_generation = 0;
1075 init_vmcb(svm);
1076 kvm_write_tsc(&svm->vcpu, 0);
1077
1078 err = fx_init(&svm->vcpu);
1079 if (err)
1080 goto free_page4;
1081
1082 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1083 if (kvm_vcpu_is_bsp(&svm->vcpu))
1084 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1085
1086 return &svm->vcpu;
1087
1088 free_page4:
1089 __free_page(hsave_page);
1090 free_page3:
1091 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1092 free_page2:
1093 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1094 free_page1:
1095 __free_page(page);
1096 uninit:
1097 kvm_vcpu_uninit(&svm->vcpu);
1098 free_svm:
1099 kmem_cache_free(kvm_vcpu_cache, svm);
1100 out:
1101 return ERR_PTR(err);
1102 }
1103
1104 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1105 {
1106 struct vcpu_svm *svm = to_svm(vcpu);
1107
1108 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1109 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1110 __free_page(virt_to_page(svm->nested.hsave));
1111 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1112 kvm_vcpu_uninit(vcpu);
1113 kmem_cache_free(kvm_vcpu_cache, svm);
1114 }
1115
1116 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1117 {
1118 struct vcpu_svm *svm = to_svm(vcpu);
1119 int i;
1120
1121 if (unlikely(cpu != vcpu->cpu)) {
1122 svm->asid_generation = 0;
1123 mark_all_dirty(svm->vmcb);
1124 }
1125
1126 #ifdef CONFIG_X86_64
1127 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1128 #endif
1129 savesegment(fs, svm->host.fs);
1130 savesegment(gs, svm->host.gs);
1131 svm->host.ldt = kvm_read_ldt();
1132
1133 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1134 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1135 }
1136
1137 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1138 {
1139 struct vcpu_svm *svm = to_svm(vcpu);
1140 int i;
1141
1142 ++vcpu->stat.host_state_reload;
1143 kvm_load_ldt(svm->host.ldt);
1144 #ifdef CONFIG_X86_64
1145 loadsegment(fs, svm->host.fs);
1146 load_gs_index(svm->host.gs);
1147 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1148 #else
1149 loadsegment(gs, svm->host.gs);
1150 #endif
1151 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1152 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1153 }
1154
1155 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1156 {
1157 return to_svm(vcpu)->vmcb->save.rflags;
1158 }
1159
1160 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1161 {
1162 to_svm(vcpu)->vmcb->save.rflags = rflags;
1163 }
1164
1165 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1166 {
1167 switch (reg) {
1168 case VCPU_EXREG_PDPTR:
1169 BUG_ON(!npt_enabled);
1170 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1171 break;
1172 default:
1173 BUG();
1174 }
1175 }
1176
1177 static void svm_set_vintr(struct vcpu_svm *svm)
1178 {
1179 set_intercept(svm, INTERCEPT_VINTR);
1180 }
1181
1182 static void svm_clear_vintr(struct vcpu_svm *svm)
1183 {
1184 clr_intercept(svm, INTERCEPT_VINTR);
1185 }
1186
1187 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1188 {
1189 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1190
1191 switch (seg) {
1192 case VCPU_SREG_CS: return &save->cs;
1193 case VCPU_SREG_DS: return &save->ds;
1194 case VCPU_SREG_ES: return &save->es;
1195 case VCPU_SREG_FS: return &save->fs;
1196 case VCPU_SREG_GS: return &save->gs;
1197 case VCPU_SREG_SS: return &save->ss;
1198 case VCPU_SREG_TR: return &save->tr;
1199 case VCPU_SREG_LDTR: return &save->ldtr;
1200 }
1201 BUG();
1202 return NULL;
1203 }
1204
1205 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1206 {
1207 struct vmcb_seg *s = svm_seg(vcpu, seg);
1208
1209 return s->base;
1210 }
1211
1212 static void svm_get_segment(struct kvm_vcpu *vcpu,
1213 struct kvm_segment *var, int seg)
1214 {
1215 struct vmcb_seg *s = svm_seg(vcpu, seg);
1216
1217 var->base = s->base;
1218 var->limit = s->limit;
1219 var->selector = s->selector;
1220 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1221 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1222 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1223 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1224 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1225 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1226 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1227 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1228
1229 /*
1230 * AMD's VMCB does not have an explicit unusable field, so emulate it
1231 * for cross vendor migration purposes by "not present"
1232 */
1233 var->unusable = !var->present || (var->type == 0);
1234
1235 switch (seg) {
1236 case VCPU_SREG_CS:
1237 /*
1238 * SVM always stores 0 for the 'G' bit in the CS selector in
1239 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1240 * Intel's VMENTRY has a check on the 'G' bit.
1241 */
1242 var->g = s->limit > 0xfffff;
1243 break;
1244 case VCPU_SREG_TR:
1245 /*
1246 * Work around a bug where the busy flag in the tr selector
1247 * isn't exposed
1248 */
1249 var->type |= 0x2;
1250 break;
1251 case VCPU_SREG_DS:
1252 case VCPU_SREG_ES:
1253 case VCPU_SREG_FS:
1254 case VCPU_SREG_GS:
1255 /*
1256 * The accessed bit must always be set in the segment
1257 * descriptor cache, although it can be cleared in the
1258 * descriptor, the cached bit always remains at 1. Since
1259 * Intel has a check on this, set it here to support
1260 * cross-vendor migration.
1261 */
1262 if (!var->unusable)
1263 var->type |= 0x1;
1264 break;
1265 case VCPU_SREG_SS:
1266 /*
1267 * On AMD CPUs sometimes the DB bit in the segment
1268 * descriptor is left as 1, although the whole segment has
1269 * been made unusable. Clear it here to pass an Intel VMX
1270 * entry check when cross vendor migrating.
1271 */
1272 if (var->unusable)
1273 var->db = 0;
1274 break;
1275 }
1276 }
1277
1278 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1279 {
1280 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1281
1282 return save->cpl;
1283 }
1284
1285 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1286 {
1287 struct vcpu_svm *svm = to_svm(vcpu);
1288
1289 dt->size = svm->vmcb->save.idtr.limit;
1290 dt->address = svm->vmcb->save.idtr.base;
1291 }
1292
1293 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1294 {
1295 struct vcpu_svm *svm = to_svm(vcpu);
1296
1297 svm->vmcb->save.idtr.limit = dt->size;
1298 svm->vmcb->save.idtr.base = dt->address ;
1299 }
1300
1301 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1302 {
1303 struct vcpu_svm *svm = to_svm(vcpu);
1304
1305 dt->size = svm->vmcb->save.gdtr.limit;
1306 dt->address = svm->vmcb->save.gdtr.base;
1307 }
1308
1309 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1310 {
1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
1313 svm->vmcb->save.gdtr.limit = dt->size;
1314 svm->vmcb->save.gdtr.base = dt->address ;
1315 }
1316
1317 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1318 {
1319 }
1320
1321 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1322 {
1323 }
1324
1325 static void update_cr0_intercept(struct vcpu_svm *svm)
1326 {
1327 ulong gcr0 = svm->vcpu.arch.cr0;
1328 u64 *hcr0 = &svm->vmcb->save.cr0;
1329
1330 if (!svm->vcpu.fpu_active)
1331 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1332 else
1333 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1334 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1335
1336
1337 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1338 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1339 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1340 } else {
1341 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1342 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1343 }
1344 }
1345
1346 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1347 {
1348 struct vcpu_svm *svm = to_svm(vcpu);
1349
1350 if (is_guest_mode(vcpu)) {
1351 /*
1352 * We are here because we run in nested mode, the host kvm
1353 * intercepts cr0 writes but the l1 hypervisor does not.
1354 * But the L1 hypervisor may intercept selective cr0 writes.
1355 * This needs to be checked here.
1356 */
1357 unsigned long old, new;
1358
1359 /* Remove bits that would trigger a real cr0 write intercept */
1360 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1361 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1362
1363 if (old == new) {
1364 /* cr0 write with ts and mp unchanged */
1365 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1366 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1367 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1368 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1369 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1370 return;
1371 }
1372 }
1373 }
1374
1375 #ifdef CONFIG_X86_64
1376 if (vcpu->arch.efer & EFER_LME) {
1377 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1378 vcpu->arch.efer |= EFER_LMA;
1379 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1380 }
1381
1382 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1383 vcpu->arch.efer &= ~EFER_LMA;
1384 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1385 }
1386 }
1387 #endif
1388 vcpu->arch.cr0 = cr0;
1389
1390 if (!npt_enabled)
1391 cr0 |= X86_CR0_PG | X86_CR0_WP;
1392
1393 if (!vcpu->fpu_active)
1394 cr0 |= X86_CR0_TS;
1395 /*
1396 * re-enable caching here because the QEMU bios
1397 * does not do it - this results in some delay at
1398 * reboot
1399 */
1400 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1401 svm->vmcb->save.cr0 = cr0;
1402 update_cr0_intercept(svm);
1403 }
1404
1405 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1406 {
1407 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1408 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1409
1410 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1411 force_new_asid(vcpu);
1412
1413 vcpu->arch.cr4 = cr4;
1414 if (!npt_enabled)
1415 cr4 |= X86_CR4_PAE;
1416 cr4 |= host_cr4_mce;
1417 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1418 }
1419
1420 static void svm_set_segment(struct kvm_vcpu *vcpu,
1421 struct kvm_segment *var, int seg)
1422 {
1423 struct vcpu_svm *svm = to_svm(vcpu);
1424 struct vmcb_seg *s = svm_seg(vcpu, seg);
1425
1426 s->base = var->base;
1427 s->limit = var->limit;
1428 s->selector = var->selector;
1429 if (var->unusable)
1430 s->attrib = 0;
1431 else {
1432 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1433 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1434 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1435 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1436 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1437 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1438 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1439 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1440 }
1441 if (seg == VCPU_SREG_CS)
1442 svm->vmcb->save.cpl
1443 = (svm->vmcb->save.cs.attrib
1444 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1445
1446 }
1447
1448 static void update_db_intercept(struct kvm_vcpu *vcpu)
1449 {
1450 struct vcpu_svm *svm = to_svm(vcpu);
1451
1452 clr_exception_intercept(svm, DB_VECTOR);
1453 clr_exception_intercept(svm, BP_VECTOR);
1454
1455 if (svm->nmi_singlestep)
1456 set_exception_intercept(svm, DB_VECTOR);
1457
1458 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1459 if (vcpu->guest_debug &
1460 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1461 set_exception_intercept(svm, DB_VECTOR);
1462 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1463 set_exception_intercept(svm, BP_VECTOR);
1464 } else
1465 vcpu->guest_debug = 0;
1466 }
1467
1468 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1469 {
1470 struct vcpu_svm *svm = to_svm(vcpu);
1471
1472 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1473 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1474 else
1475 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1476
1477 update_db_intercept(vcpu);
1478 }
1479
1480 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1481 {
1482 if (sd->next_asid > sd->max_asid) {
1483 ++sd->asid_generation;
1484 sd->next_asid = 1;
1485 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1486 }
1487
1488 svm->asid_generation = sd->asid_generation;
1489 svm->vmcb->control.asid = sd->next_asid++;
1490 }
1491
1492 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1493 {
1494 struct vcpu_svm *svm = to_svm(vcpu);
1495
1496 svm->vmcb->save.dr7 = value;
1497 }
1498
1499 static int pf_interception(struct vcpu_svm *svm)
1500 {
1501 u64 fault_address = svm->vmcb->control.exit_info_2;
1502 u32 error_code;
1503 int r = 1;
1504
1505 switch (svm->apf_reason) {
1506 default:
1507 error_code = svm->vmcb->control.exit_info_1;
1508
1509 trace_kvm_page_fault(fault_address, error_code);
1510 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1511 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1512 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1513 break;
1514 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1515 svm->apf_reason = 0;
1516 local_irq_disable();
1517 kvm_async_pf_task_wait(fault_address);
1518 local_irq_enable();
1519 break;
1520 case KVM_PV_REASON_PAGE_READY:
1521 svm->apf_reason = 0;
1522 local_irq_disable();
1523 kvm_async_pf_task_wake(fault_address);
1524 local_irq_enable();
1525 break;
1526 }
1527 return r;
1528 }
1529
1530 static int db_interception(struct vcpu_svm *svm)
1531 {
1532 struct kvm_run *kvm_run = svm->vcpu.run;
1533
1534 if (!(svm->vcpu.guest_debug &
1535 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1536 !svm->nmi_singlestep) {
1537 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1538 return 1;
1539 }
1540
1541 if (svm->nmi_singlestep) {
1542 svm->nmi_singlestep = false;
1543 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1544 svm->vmcb->save.rflags &=
1545 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1546 update_db_intercept(&svm->vcpu);
1547 }
1548
1549 if (svm->vcpu.guest_debug &
1550 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1551 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1552 kvm_run->debug.arch.pc =
1553 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1554 kvm_run->debug.arch.exception = DB_VECTOR;
1555 return 0;
1556 }
1557
1558 return 1;
1559 }
1560
1561 static int bp_interception(struct vcpu_svm *svm)
1562 {
1563 struct kvm_run *kvm_run = svm->vcpu.run;
1564
1565 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1566 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1567 kvm_run->debug.arch.exception = BP_VECTOR;
1568 return 0;
1569 }
1570
1571 static int ud_interception(struct vcpu_svm *svm)
1572 {
1573 int er;
1574
1575 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1576 if (er != EMULATE_DONE)
1577 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1578 return 1;
1579 }
1580
1581 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1582 {
1583 struct vcpu_svm *svm = to_svm(vcpu);
1584
1585 clr_exception_intercept(svm, NM_VECTOR);
1586
1587 svm->vcpu.fpu_active = 1;
1588 update_cr0_intercept(svm);
1589 }
1590
1591 static int nm_interception(struct vcpu_svm *svm)
1592 {
1593 svm_fpu_activate(&svm->vcpu);
1594 return 1;
1595 }
1596
1597 static bool is_erratum_383(void)
1598 {
1599 int err, i;
1600 u64 value;
1601
1602 if (!erratum_383_found)
1603 return false;
1604
1605 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1606 if (err)
1607 return false;
1608
1609 /* Bit 62 may or may not be set for this mce */
1610 value &= ~(1ULL << 62);
1611
1612 if (value != 0xb600000000010015ULL)
1613 return false;
1614
1615 /* Clear MCi_STATUS registers */
1616 for (i = 0; i < 6; ++i)
1617 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1618
1619 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1620 if (!err) {
1621 u32 low, high;
1622
1623 value &= ~(1ULL << 2);
1624 low = lower_32_bits(value);
1625 high = upper_32_bits(value);
1626
1627 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1628 }
1629
1630 /* Flush tlb to evict multi-match entries */
1631 __flush_tlb_all();
1632
1633 return true;
1634 }
1635
1636 static void svm_handle_mce(struct vcpu_svm *svm)
1637 {
1638 if (is_erratum_383()) {
1639 /*
1640 * Erratum 383 triggered. Guest state is corrupt so kill the
1641 * guest.
1642 */
1643 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1644
1645 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1646
1647 return;
1648 }
1649
1650 /*
1651 * On an #MC intercept the MCE handler is not called automatically in
1652 * the host. So do it by hand here.
1653 */
1654 asm volatile (
1655 "int $0x12\n");
1656 /* not sure if we ever come back to this point */
1657
1658 return;
1659 }
1660
1661 static int mc_interception(struct vcpu_svm *svm)
1662 {
1663 return 1;
1664 }
1665
1666 static int shutdown_interception(struct vcpu_svm *svm)
1667 {
1668 struct kvm_run *kvm_run = svm->vcpu.run;
1669
1670 /*
1671 * VMCB is undefined after a SHUTDOWN intercept
1672 * so reinitialize it.
1673 */
1674 clear_page(svm->vmcb);
1675 init_vmcb(svm);
1676
1677 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1678 return 0;
1679 }
1680
1681 static int io_interception(struct vcpu_svm *svm)
1682 {
1683 struct kvm_vcpu *vcpu = &svm->vcpu;
1684 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1685 int size, in, string;
1686 unsigned port;
1687
1688 ++svm->vcpu.stat.io_exits;
1689 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1690 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1691 if (string || in)
1692 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1693
1694 port = io_info >> 16;
1695 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1696 svm->next_rip = svm->vmcb->control.exit_info_2;
1697 skip_emulated_instruction(&svm->vcpu);
1698
1699 return kvm_fast_pio_out(vcpu, size, port);
1700 }
1701
1702 static int nmi_interception(struct vcpu_svm *svm)
1703 {
1704 return 1;
1705 }
1706
1707 static int intr_interception(struct vcpu_svm *svm)
1708 {
1709 ++svm->vcpu.stat.irq_exits;
1710 return 1;
1711 }
1712
1713 static int nop_on_interception(struct vcpu_svm *svm)
1714 {
1715 return 1;
1716 }
1717
1718 static int halt_interception(struct vcpu_svm *svm)
1719 {
1720 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1721 skip_emulated_instruction(&svm->vcpu);
1722 return kvm_emulate_halt(&svm->vcpu);
1723 }
1724
1725 static int vmmcall_interception(struct vcpu_svm *svm)
1726 {
1727 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1728 skip_emulated_instruction(&svm->vcpu);
1729 kvm_emulate_hypercall(&svm->vcpu);
1730 return 1;
1731 }
1732
1733 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1734 {
1735 struct vcpu_svm *svm = to_svm(vcpu);
1736
1737 return svm->nested.nested_cr3;
1738 }
1739
1740 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1741 unsigned long root)
1742 {
1743 struct vcpu_svm *svm = to_svm(vcpu);
1744
1745 svm->vmcb->control.nested_cr3 = root;
1746 force_new_asid(vcpu);
1747 }
1748
1749 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1750 struct x86_exception *fault)
1751 {
1752 struct vcpu_svm *svm = to_svm(vcpu);
1753
1754 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1755 svm->vmcb->control.exit_code_hi = 0;
1756 svm->vmcb->control.exit_info_1 = fault->error_code;
1757 svm->vmcb->control.exit_info_2 = fault->address;
1758
1759 nested_svm_vmexit(svm);
1760 }
1761
1762 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1763 {
1764 int r;
1765
1766 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1767
1768 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1769 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1770 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1771 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1772 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1773
1774 return r;
1775 }
1776
1777 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1778 {
1779 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1780 }
1781
1782 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1783 {
1784 if (!(svm->vcpu.arch.efer & EFER_SVME)
1785 || !is_paging(&svm->vcpu)) {
1786 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1787 return 1;
1788 }
1789
1790 if (svm->vmcb->save.cpl) {
1791 kvm_inject_gp(&svm->vcpu, 0);
1792 return 1;
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1799 bool has_error_code, u32 error_code)
1800 {
1801 int vmexit;
1802
1803 if (!is_guest_mode(&svm->vcpu))
1804 return 0;
1805
1806 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1807 svm->vmcb->control.exit_code_hi = 0;
1808 svm->vmcb->control.exit_info_1 = error_code;
1809 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1810
1811 vmexit = nested_svm_intercept(svm);
1812 if (vmexit == NESTED_EXIT_DONE)
1813 svm->nested.exit_required = true;
1814
1815 return vmexit;
1816 }
1817
1818 /* This function returns true if it is save to enable the irq window */
1819 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1820 {
1821 if (!is_guest_mode(&svm->vcpu))
1822 return true;
1823
1824 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1825 return true;
1826
1827 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1828 return false;
1829
1830 /*
1831 * if vmexit was already requested (by intercepted exception
1832 * for instance) do not overwrite it with "external interrupt"
1833 * vmexit.
1834 */
1835 if (svm->nested.exit_required)
1836 return false;
1837
1838 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1839 svm->vmcb->control.exit_info_1 = 0;
1840 svm->vmcb->control.exit_info_2 = 0;
1841
1842 if (svm->nested.intercept & 1ULL) {
1843 /*
1844 * The #vmexit can't be emulated here directly because this
1845 * code path runs with irqs and preemtion disabled. A
1846 * #vmexit emulation might sleep. Only signal request for
1847 * the #vmexit here.
1848 */
1849 svm->nested.exit_required = true;
1850 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1851 return false;
1852 }
1853
1854 return true;
1855 }
1856
1857 /* This function returns true if it is save to enable the nmi window */
1858 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1859 {
1860 if (!is_guest_mode(&svm->vcpu))
1861 return true;
1862
1863 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1864 return true;
1865
1866 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1867 svm->nested.exit_required = true;
1868
1869 return false;
1870 }
1871
1872 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1873 {
1874 struct page *page;
1875
1876 might_sleep();
1877
1878 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1879 if (is_error_page(page))
1880 goto error;
1881
1882 *_page = page;
1883
1884 return kmap(page);
1885
1886 error:
1887 kvm_release_page_clean(page);
1888 kvm_inject_gp(&svm->vcpu, 0);
1889
1890 return NULL;
1891 }
1892
1893 static void nested_svm_unmap(struct page *page)
1894 {
1895 kunmap(page);
1896 kvm_release_page_dirty(page);
1897 }
1898
1899 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1900 {
1901 unsigned port;
1902 u8 val, bit;
1903 u64 gpa;
1904
1905 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1906 return NESTED_EXIT_HOST;
1907
1908 port = svm->vmcb->control.exit_info_1 >> 16;
1909 gpa = svm->nested.vmcb_iopm + (port / 8);
1910 bit = port % 8;
1911 val = 0;
1912
1913 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1914 val &= (1 << bit);
1915
1916 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1917 }
1918
1919 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1920 {
1921 u32 offset, msr, value;
1922 int write, mask;
1923
1924 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1925 return NESTED_EXIT_HOST;
1926
1927 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1928 offset = svm_msrpm_offset(msr);
1929 write = svm->vmcb->control.exit_info_1 & 1;
1930 mask = 1 << ((2 * (msr & 0xf)) + write);
1931
1932 if (offset == MSR_INVALID)
1933 return NESTED_EXIT_DONE;
1934
1935 /* Offset is in 32 bit units but need in 8 bit units */
1936 offset *= 4;
1937
1938 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1939 return NESTED_EXIT_DONE;
1940
1941 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1942 }
1943
1944 static int nested_svm_exit_special(struct vcpu_svm *svm)
1945 {
1946 u32 exit_code = svm->vmcb->control.exit_code;
1947
1948 switch (exit_code) {
1949 case SVM_EXIT_INTR:
1950 case SVM_EXIT_NMI:
1951 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1952 return NESTED_EXIT_HOST;
1953 case SVM_EXIT_NPF:
1954 /* For now we are always handling NPFs when using them */
1955 if (npt_enabled)
1956 return NESTED_EXIT_HOST;
1957 break;
1958 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1959 /* When we're shadowing, trap PFs, but not async PF */
1960 if (!npt_enabled && svm->apf_reason == 0)
1961 return NESTED_EXIT_HOST;
1962 break;
1963 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1964 nm_interception(svm);
1965 break;
1966 default:
1967 break;
1968 }
1969
1970 return NESTED_EXIT_CONTINUE;
1971 }
1972
1973 /*
1974 * If this function returns true, this #vmexit was already handled
1975 */
1976 static int nested_svm_intercept(struct vcpu_svm *svm)
1977 {
1978 u32 exit_code = svm->vmcb->control.exit_code;
1979 int vmexit = NESTED_EXIT_HOST;
1980
1981 switch (exit_code) {
1982 case SVM_EXIT_MSR:
1983 vmexit = nested_svm_exit_handled_msr(svm);
1984 break;
1985 case SVM_EXIT_IOIO:
1986 vmexit = nested_svm_intercept_ioio(svm);
1987 break;
1988 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1989 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1990 if (svm->nested.intercept_cr & bit)
1991 vmexit = NESTED_EXIT_DONE;
1992 break;
1993 }
1994 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
1995 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
1996 if (svm->nested.intercept_dr & bit)
1997 vmexit = NESTED_EXIT_DONE;
1998 break;
1999 }
2000 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2001 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2002 if (svm->nested.intercept_exceptions & excp_bits)
2003 vmexit = NESTED_EXIT_DONE;
2004 /* async page fault always cause vmexit */
2005 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2006 svm->apf_reason != 0)
2007 vmexit = NESTED_EXIT_DONE;
2008 break;
2009 }
2010 case SVM_EXIT_ERR: {
2011 vmexit = NESTED_EXIT_DONE;
2012 break;
2013 }
2014 default: {
2015 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2016 if (svm->nested.intercept & exit_bits)
2017 vmexit = NESTED_EXIT_DONE;
2018 }
2019 }
2020
2021 return vmexit;
2022 }
2023
2024 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2025 {
2026 int vmexit;
2027
2028 vmexit = nested_svm_intercept(svm);
2029
2030 if (vmexit == NESTED_EXIT_DONE)
2031 nested_svm_vmexit(svm);
2032
2033 return vmexit;
2034 }
2035
2036 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2037 {
2038 struct vmcb_control_area *dst = &dst_vmcb->control;
2039 struct vmcb_control_area *from = &from_vmcb->control;
2040
2041 dst->intercept_cr = from->intercept_cr;
2042 dst->intercept_dr = from->intercept_dr;
2043 dst->intercept_exceptions = from->intercept_exceptions;
2044 dst->intercept = from->intercept;
2045 dst->iopm_base_pa = from->iopm_base_pa;
2046 dst->msrpm_base_pa = from->msrpm_base_pa;
2047 dst->tsc_offset = from->tsc_offset;
2048 dst->asid = from->asid;
2049 dst->tlb_ctl = from->tlb_ctl;
2050 dst->int_ctl = from->int_ctl;
2051 dst->int_vector = from->int_vector;
2052 dst->int_state = from->int_state;
2053 dst->exit_code = from->exit_code;
2054 dst->exit_code_hi = from->exit_code_hi;
2055 dst->exit_info_1 = from->exit_info_1;
2056 dst->exit_info_2 = from->exit_info_2;
2057 dst->exit_int_info = from->exit_int_info;
2058 dst->exit_int_info_err = from->exit_int_info_err;
2059 dst->nested_ctl = from->nested_ctl;
2060 dst->event_inj = from->event_inj;
2061 dst->event_inj_err = from->event_inj_err;
2062 dst->nested_cr3 = from->nested_cr3;
2063 dst->lbr_ctl = from->lbr_ctl;
2064 }
2065
2066 static int nested_svm_vmexit(struct vcpu_svm *svm)
2067 {
2068 struct vmcb *nested_vmcb;
2069 struct vmcb *hsave = svm->nested.hsave;
2070 struct vmcb *vmcb = svm->vmcb;
2071 struct page *page;
2072
2073 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2074 vmcb->control.exit_info_1,
2075 vmcb->control.exit_info_2,
2076 vmcb->control.exit_int_info,
2077 vmcb->control.exit_int_info_err);
2078
2079 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2080 if (!nested_vmcb)
2081 return 1;
2082
2083 /* Exit Guest-Mode */
2084 leave_guest_mode(&svm->vcpu);
2085 svm->nested.vmcb = 0;
2086
2087 /* Give the current vmcb to the guest */
2088 disable_gif(svm);
2089
2090 nested_vmcb->save.es = vmcb->save.es;
2091 nested_vmcb->save.cs = vmcb->save.cs;
2092 nested_vmcb->save.ss = vmcb->save.ss;
2093 nested_vmcb->save.ds = vmcb->save.ds;
2094 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2095 nested_vmcb->save.idtr = vmcb->save.idtr;
2096 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2097 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2098 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2099 nested_vmcb->save.cr2 = vmcb->save.cr2;
2100 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2101 nested_vmcb->save.rflags = vmcb->save.rflags;
2102 nested_vmcb->save.rip = vmcb->save.rip;
2103 nested_vmcb->save.rsp = vmcb->save.rsp;
2104 nested_vmcb->save.rax = vmcb->save.rax;
2105 nested_vmcb->save.dr7 = vmcb->save.dr7;
2106 nested_vmcb->save.dr6 = vmcb->save.dr6;
2107 nested_vmcb->save.cpl = vmcb->save.cpl;
2108
2109 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2110 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2111 nested_vmcb->control.int_state = vmcb->control.int_state;
2112 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2113 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2114 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2115 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2116 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2117 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2118 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2119
2120 /*
2121 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2122 * to make sure that we do not lose injected events. So check event_inj
2123 * here and copy it to exit_int_info if it is valid.
2124 * Exit_int_info and event_inj can't be both valid because the case
2125 * below only happens on a VMRUN instruction intercept which has
2126 * no valid exit_int_info set.
2127 */
2128 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2129 struct vmcb_control_area *nc = &nested_vmcb->control;
2130
2131 nc->exit_int_info = vmcb->control.event_inj;
2132 nc->exit_int_info_err = vmcb->control.event_inj_err;
2133 }
2134
2135 nested_vmcb->control.tlb_ctl = 0;
2136 nested_vmcb->control.event_inj = 0;
2137 nested_vmcb->control.event_inj_err = 0;
2138
2139 /* We always set V_INTR_MASKING and remember the old value in hflags */
2140 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2141 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2142
2143 /* Restore the original control entries */
2144 copy_vmcb_control_area(vmcb, hsave);
2145
2146 kvm_clear_exception_queue(&svm->vcpu);
2147 kvm_clear_interrupt_queue(&svm->vcpu);
2148
2149 svm->nested.nested_cr3 = 0;
2150
2151 /* Restore selected save entries */
2152 svm->vmcb->save.es = hsave->save.es;
2153 svm->vmcb->save.cs = hsave->save.cs;
2154 svm->vmcb->save.ss = hsave->save.ss;
2155 svm->vmcb->save.ds = hsave->save.ds;
2156 svm->vmcb->save.gdtr = hsave->save.gdtr;
2157 svm->vmcb->save.idtr = hsave->save.idtr;
2158 svm->vmcb->save.rflags = hsave->save.rflags;
2159 svm_set_efer(&svm->vcpu, hsave->save.efer);
2160 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2161 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2162 if (npt_enabled) {
2163 svm->vmcb->save.cr3 = hsave->save.cr3;
2164 svm->vcpu.arch.cr3 = hsave->save.cr3;
2165 } else {
2166 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2167 }
2168 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2169 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2170 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2171 svm->vmcb->save.dr7 = 0;
2172 svm->vmcb->save.cpl = 0;
2173 svm->vmcb->control.exit_int_info = 0;
2174
2175 mark_all_dirty(svm->vmcb);
2176
2177 nested_svm_unmap(page);
2178
2179 nested_svm_uninit_mmu_context(&svm->vcpu);
2180 kvm_mmu_reset_context(&svm->vcpu);
2181 kvm_mmu_load(&svm->vcpu);
2182
2183 return 0;
2184 }
2185
2186 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2187 {
2188 /*
2189 * This function merges the msr permission bitmaps of kvm and the
2190 * nested vmcb. It is omptimized in that it only merges the parts where
2191 * the kvm msr permission bitmap may contain zero bits
2192 */
2193 int i;
2194
2195 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2196 return true;
2197
2198 for (i = 0; i < MSRPM_OFFSETS; i++) {
2199 u32 value, p;
2200 u64 offset;
2201
2202 if (msrpm_offsets[i] == 0xffffffff)
2203 break;
2204
2205 p = msrpm_offsets[i];
2206 offset = svm->nested.vmcb_msrpm + (p * 4);
2207
2208 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2209 return false;
2210
2211 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2212 }
2213
2214 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2215
2216 return true;
2217 }
2218
2219 static bool nested_vmcb_checks(struct vmcb *vmcb)
2220 {
2221 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2222 return false;
2223
2224 if (vmcb->control.asid == 0)
2225 return false;
2226
2227 if (vmcb->control.nested_ctl && !npt_enabled)
2228 return false;
2229
2230 return true;
2231 }
2232
2233 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2234 {
2235 struct vmcb *nested_vmcb;
2236 struct vmcb *hsave = svm->nested.hsave;
2237 struct vmcb *vmcb = svm->vmcb;
2238 struct page *page;
2239 u64 vmcb_gpa;
2240
2241 vmcb_gpa = svm->vmcb->save.rax;
2242
2243 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2244 if (!nested_vmcb)
2245 return false;
2246
2247 if (!nested_vmcb_checks(nested_vmcb)) {
2248 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2249 nested_vmcb->control.exit_code_hi = 0;
2250 nested_vmcb->control.exit_info_1 = 0;
2251 nested_vmcb->control.exit_info_2 = 0;
2252
2253 nested_svm_unmap(page);
2254
2255 return false;
2256 }
2257
2258 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2259 nested_vmcb->save.rip,
2260 nested_vmcb->control.int_ctl,
2261 nested_vmcb->control.event_inj,
2262 nested_vmcb->control.nested_ctl);
2263
2264 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2265 nested_vmcb->control.intercept_cr >> 16,
2266 nested_vmcb->control.intercept_exceptions,
2267 nested_vmcb->control.intercept);
2268
2269 /* Clear internal status */
2270 kvm_clear_exception_queue(&svm->vcpu);
2271 kvm_clear_interrupt_queue(&svm->vcpu);
2272
2273 /*
2274 * Save the old vmcb, so we don't need to pick what we save, but can
2275 * restore everything when a VMEXIT occurs
2276 */
2277 hsave->save.es = vmcb->save.es;
2278 hsave->save.cs = vmcb->save.cs;
2279 hsave->save.ss = vmcb->save.ss;
2280 hsave->save.ds = vmcb->save.ds;
2281 hsave->save.gdtr = vmcb->save.gdtr;
2282 hsave->save.idtr = vmcb->save.idtr;
2283 hsave->save.efer = svm->vcpu.arch.efer;
2284 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2285 hsave->save.cr4 = svm->vcpu.arch.cr4;
2286 hsave->save.rflags = vmcb->save.rflags;
2287 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2288 hsave->save.rsp = vmcb->save.rsp;
2289 hsave->save.rax = vmcb->save.rax;
2290 if (npt_enabled)
2291 hsave->save.cr3 = vmcb->save.cr3;
2292 else
2293 hsave->save.cr3 = svm->vcpu.arch.cr3;
2294
2295 copy_vmcb_control_area(hsave, vmcb);
2296
2297 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2298 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2299 else
2300 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2301
2302 if (nested_vmcb->control.nested_ctl) {
2303 kvm_mmu_unload(&svm->vcpu);
2304 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2305 nested_svm_init_mmu_context(&svm->vcpu);
2306 }
2307
2308 /* Load the nested guest state */
2309 svm->vmcb->save.es = nested_vmcb->save.es;
2310 svm->vmcb->save.cs = nested_vmcb->save.cs;
2311 svm->vmcb->save.ss = nested_vmcb->save.ss;
2312 svm->vmcb->save.ds = nested_vmcb->save.ds;
2313 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2314 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2315 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2316 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2317 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2318 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2319 if (npt_enabled) {
2320 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2321 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2322 } else
2323 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2324
2325 /* Guest paging mode is active - reset mmu */
2326 kvm_mmu_reset_context(&svm->vcpu);
2327
2328 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2329 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2330 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2331 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2332
2333 /* In case we don't even reach vcpu_run, the fields are not updated */
2334 svm->vmcb->save.rax = nested_vmcb->save.rax;
2335 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2336 svm->vmcb->save.rip = nested_vmcb->save.rip;
2337 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2338 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2339 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2340
2341 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2342 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2343
2344 /* cache intercepts */
2345 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2346 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2347 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2348 svm->nested.intercept = nested_vmcb->control.intercept;
2349
2350 force_new_asid(&svm->vcpu);
2351 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2352 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2353 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2354 else
2355 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2356
2357 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2358 /* We only want the cr8 intercept bits of the guest */
2359 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2360 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2361 }
2362
2363 /* We don't want to see VMMCALLs from a nested guest */
2364 clr_intercept(svm, INTERCEPT_VMMCALL);
2365
2366 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2367 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2368 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2369 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2370 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2371 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2372
2373 nested_svm_unmap(page);
2374
2375 /* Enter Guest-Mode */
2376 enter_guest_mode(&svm->vcpu);
2377
2378 /*
2379 * Merge guest and host intercepts - must be called with vcpu in
2380 * guest-mode to take affect here
2381 */
2382 recalc_intercepts(svm);
2383
2384 svm->nested.vmcb = vmcb_gpa;
2385
2386 enable_gif(svm);
2387
2388 mark_all_dirty(svm->vmcb);
2389
2390 return true;
2391 }
2392
2393 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2394 {
2395 to_vmcb->save.fs = from_vmcb->save.fs;
2396 to_vmcb->save.gs = from_vmcb->save.gs;
2397 to_vmcb->save.tr = from_vmcb->save.tr;
2398 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2399 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2400 to_vmcb->save.star = from_vmcb->save.star;
2401 to_vmcb->save.lstar = from_vmcb->save.lstar;
2402 to_vmcb->save.cstar = from_vmcb->save.cstar;
2403 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2404 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2405 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2406 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2407 }
2408
2409 static int vmload_interception(struct vcpu_svm *svm)
2410 {
2411 struct vmcb *nested_vmcb;
2412 struct page *page;
2413
2414 if (nested_svm_check_permissions(svm))
2415 return 1;
2416
2417 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2418 skip_emulated_instruction(&svm->vcpu);
2419
2420 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2421 if (!nested_vmcb)
2422 return 1;
2423
2424 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2425 nested_svm_unmap(page);
2426
2427 return 1;
2428 }
2429
2430 static int vmsave_interception(struct vcpu_svm *svm)
2431 {
2432 struct vmcb *nested_vmcb;
2433 struct page *page;
2434
2435 if (nested_svm_check_permissions(svm))
2436 return 1;
2437
2438 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2439 skip_emulated_instruction(&svm->vcpu);
2440
2441 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2442 if (!nested_vmcb)
2443 return 1;
2444
2445 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2446 nested_svm_unmap(page);
2447
2448 return 1;
2449 }
2450
2451 static int vmrun_interception(struct vcpu_svm *svm)
2452 {
2453 if (nested_svm_check_permissions(svm))
2454 return 1;
2455
2456 /* Save rip after vmrun instruction */
2457 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2458
2459 if (!nested_svm_vmrun(svm))
2460 return 1;
2461
2462 if (!nested_svm_vmrun_msrpm(svm))
2463 goto failed;
2464
2465 return 1;
2466
2467 failed:
2468
2469 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2470 svm->vmcb->control.exit_code_hi = 0;
2471 svm->vmcb->control.exit_info_1 = 0;
2472 svm->vmcb->control.exit_info_2 = 0;
2473
2474 nested_svm_vmexit(svm);
2475
2476 return 1;
2477 }
2478
2479 static int stgi_interception(struct vcpu_svm *svm)
2480 {
2481 if (nested_svm_check_permissions(svm))
2482 return 1;
2483
2484 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2485 skip_emulated_instruction(&svm->vcpu);
2486 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2487
2488 enable_gif(svm);
2489
2490 return 1;
2491 }
2492
2493 static int clgi_interception(struct vcpu_svm *svm)
2494 {
2495 if (nested_svm_check_permissions(svm))
2496 return 1;
2497
2498 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2499 skip_emulated_instruction(&svm->vcpu);
2500
2501 disable_gif(svm);
2502
2503 /* After a CLGI no interrupts should come */
2504 svm_clear_vintr(svm);
2505 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2506
2507 return 1;
2508 }
2509
2510 static int invlpga_interception(struct vcpu_svm *svm)
2511 {
2512 struct kvm_vcpu *vcpu = &svm->vcpu;
2513
2514 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2515 vcpu->arch.regs[VCPU_REGS_RAX]);
2516
2517 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2518 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2519
2520 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2521 skip_emulated_instruction(&svm->vcpu);
2522 return 1;
2523 }
2524
2525 static int skinit_interception(struct vcpu_svm *svm)
2526 {
2527 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2528
2529 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2530 return 1;
2531 }
2532
2533 static int invalid_op_interception(struct vcpu_svm *svm)
2534 {
2535 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2536 return 1;
2537 }
2538
2539 static int task_switch_interception(struct vcpu_svm *svm)
2540 {
2541 u16 tss_selector;
2542 int reason;
2543 int int_type = svm->vmcb->control.exit_int_info &
2544 SVM_EXITINTINFO_TYPE_MASK;
2545 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2546 uint32_t type =
2547 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2548 uint32_t idt_v =
2549 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2550 bool has_error_code = false;
2551 u32 error_code = 0;
2552
2553 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2554
2555 if (svm->vmcb->control.exit_info_2 &
2556 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2557 reason = TASK_SWITCH_IRET;
2558 else if (svm->vmcb->control.exit_info_2 &
2559 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2560 reason = TASK_SWITCH_JMP;
2561 else if (idt_v)
2562 reason = TASK_SWITCH_GATE;
2563 else
2564 reason = TASK_SWITCH_CALL;
2565
2566 if (reason == TASK_SWITCH_GATE) {
2567 switch (type) {
2568 case SVM_EXITINTINFO_TYPE_NMI:
2569 svm->vcpu.arch.nmi_injected = false;
2570 break;
2571 case SVM_EXITINTINFO_TYPE_EXEPT:
2572 if (svm->vmcb->control.exit_info_2 &
2573 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2574 has_error_code = true;
2575 error_code =
2576 (u32)svm->vmcb->control.exit_info_2;
2577 }
2578 kvm_clear_exception_queue(&svm->vcpu);
2579 break;
2580 case SVM_EXITINTINFO_TYPE_INTR:
2581 kvm_clear_interrupt_queue(&svm->vcpu);
2582 break;
2583 default:
2584 break;
2585 }
2586 }
2587
2588 if (reason != TASK_SWITCH_GATE ||
2589 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2590 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2591 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2592 skip_emulated_instruction(&svm->vcpu);
2593
2594 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2595 has_error_code, error_code) == EMULATE_FAIL) {
2596 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2597 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2598 svm->vcpu.run->internal.ndata = 0;
2599 return 0;
2600 }
2601 return 1;
2602 }
2603
2604 static int cpuid_interception(struct vcpu_svm *svm)
2605 {
2606 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2607 kvm_emulate_cpuid(&svm->vcpu);
2608 return 1;
2609 }
2610
2611 static int iret_interception(struct vcpu_svm *svm)
2612 {
2613 ++svm->vcpu.stat.nmi_window_exits;
2614 clr_intercept(svm, INTERCEPT_IRET);
2615 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2616 return 1;
2617 }
2618
2619 static int invlpg_interception(struct vcpu_svm *svm)
2620 {
2621 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2622 }
2623
2624 static int emulate_on_interception(struct vcpu_svm *svm)
2625 {
2626 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2627 }
2628
2629 static int cr0_write_interception(struct vcpu_svm *svm)
2630 {
2631 struct kvm_vcpu *vcpu = &svm->vcpu;
2632 int r;
2633
2634 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2635
2636 if (svm->nested.vmexit_rip) {
2637 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2638 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2639 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2640 svm->nested.vmexit_rip = 0;
2641 }
2642
2643 return r == EMULATE_DONE;
2644 }
2645
2646 static int cr8_write_interception(struct vcpu_svm *svm)
2647 {
2648 struct kvm_run *kvm_run = svm->vcpu.run;
2649
2650 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2651 /* instruction emulation calls kvm_set_cr8() */
2652 emulate_instruction(&svm->vcpu, 0, 0, 0);
2653 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2654 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2655 return 1;
2656 }
2657 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2658 return 1;
2659 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2660 return 0;
2661 }
2662
2663 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2664 {
2665 struct vcpu_svm *svm = to_svm(vcpu);
2666
2667 switch (ecx) {
2668 case MSR_IA32_TSC: {
2669 struct vmcb *vmcb = get_host_vmcb(svm);
2670
2671 *data = vmcb->control.tsc_offset + native_read_tsc();
2672 break;
2673 }
2674 case MSR_STAR:
2675 *data = svm->vmcb->save.star;
2676 break;
2677 #ifdef CONFIG_X86_64
2678 case MSR_LSTAR:
2679 *data = svm->vmcb->save.lstar;
2680 break;
2681 case MSR_CSTAR:
2682 *data = svm->vmcb->save.cstar;
2683 break;
2684 case MSR_KERNEL_GS_BASE:
2685 *data = svm->vmcb->save.kernel_gs_base;
2686 break;
2687 case MSR_SYSCALL_MASK:
2688 *data = svm->vmcb->save.sfmask;
2689 break;
2690 #endif
2691 case MSR_IA32_SYSENTER_CS:
2692 *data = svm->vmcb->save.sysenter_cs;
2693 break;
2694 case MSR_IA32_SYSENTER_EIP:
2695 *data = svm->sysenter_eip;
2696 break;
2697 case MSR_IA32_SYSENTER_ESP:
2698 *data = svm->sysenter_esp;
2699 break;
2700 /*
2701 * Nobody will change the following 5 values in the VMCB so we can
2702 * safely return them on rdmsr. They will always be 0 until LBRV is
2703 * implemented.
2704 */
2705 case MSR_IA32_DEBUGCTLMSR:
2706 *data = svm->vmcb->save.dbgctl;
2707 break;
2708 case MSR_IA32_LASTBRANCHFROMIP:
2709 *data = svm->vmcb->save.br_from;
2710 break;
2711 case MSR_IA32_LASTBRANCHTOIP:
2712 *data = svm->vmcb->save.br_to;
2713 break;
2714 case MSR_IA32_LASTINTFROMIP:
2715 *data = svm->vmcb->save.last_excp_from;
2716 break;
2717 case MSR_IA32_LASTINTTOIP:
2718 *data = svm->vmcb->save.last_excp_to;
2719 break;
2720 case MSR_VM_HSAVE_PA:
2721 *data = svm->nested.hsave_msr;
2722 break;
2723 case MSR_VM_CR:
2724 *data = svm->nested.vm_cr_msr;
2725 break;
2726 case MSR_IA32_UCODE_REV:
2727 *data = 0x01000065;
2728 break;
2729 default:
2730 return kvm_get_msr_common(vcpu, ecx, data);
2731 }
2732 return 0;
2733 }
2734
2735 static int rdmsr_interception(struct vcpu_svm *svm)
2736 {
2737 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2738 u64 data;
2739
2740 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2741 trace_kvm_msr_read_ex(ecx);
2742 kvm_inject_gp(&svm->vcpu, 0);
2743 } else {
2744 trace_kvm_msr_read(ecx, data);
2745
2746 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2747 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2748 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2749 skip_emulated_instruction(&svm->vcpu);
2750 }
2751 return 1;
2752 }
2753
2754 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2755 {
2756 struct vcpu_svm *svm = to_svm(vcpu);
2757 int svm_dis, chg_mask;
2758
2759 if (data & ~SVM_VM_CR_VALID_MASK)
2760 return 1;
2761
2762 chg_mask = SVM_VM_CR_VALID_MASK;
2763
2764 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2765 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2766
2767 svm->nested.vm_cr_msr &= ~chg_mask;
2768 svm->nested.vm_cr_msr |= (data & chg_mask);
2769
2770 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2771
2772 /* check for svm_disable while efer.svme is set */
2773 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2774 return 1;
2775
2776 return 0;
2777 }
2778
2779 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2780 {
2781 struct vcpu_svm *svm = to_svm(vcpu);
2782
2783 switch (ecx) {
2784 case MSR_IA32_TSC:
2785 kvm_write_tsc(vcpu, data);
2786 break;
2787 case MSR_STAR:
2788 svm->vmcb->save.star = data;
2789 break;
2790 #ifdef CONFIG_X86_64
2791 case MSR_LSTAR:
2792 svm->vmcb->save.lstar = data;
2793 break;
2794 case MSR_CSTAR:
2795 svm->vmcb->save.cstar = data;
2796 break;
2797 case MSR_KERNEL_GS_BASE:
2798 svm->vmcb->save.kernel_gs_base = data;
2799 break;
2800 case MSR_SYSCALL_MASK:
2801 svm->vmcb->save.sfmask = data;
2802 break;
2803 #endif
2804 case MSR_IA32_SYSENTER_CS:
2805 svm->vmcb->save.sysenter_cs = data;
2806 break;
2807 case MSR_IA32_SYSENTER_EIP:
2808 svm->sysenter_eip = data;
2809 svm->vmcb->save.sysenter_eip = data;
2810 break;
2811 case MSR_IA32_SYSENTER_ESP:
2812 svm->sysenter_esp = data;
2813 svm->vmcb->save.sysenter_esp = data;
2814 break;
2815 case MSR_IA32_DEBUGCTLMSR:
2816 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2817 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2818 __func__, data);
2819 break;
2820 }
2821 if (data & DEBUGCTL_RESERVED_BITS)
2822 return 1;
2823
2824 svm->vmcb->save.dbgctl = data;
2825 if (data & (1ULL<<0))
2826 svm_enable_lbrv(svm);
2827 else
2828 svm_disable_lbrv(svm);
2829 break;
2830 case MSR_VM_HSAVE_PA:
2831 svm->nested.hsave_msr = data;
2832 break;
2833 case MSR_VM_CR:
2834 return svm_set_vm_cr(vcpu, data);
2835 case MSR_VM_IGNNE:
2836 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2837 break;
2838 default:
2839 return kvm_set_msr_common(vcpu, ecx, data);
2840 }
2841 return 0;
2842 }
2843
2844 static int wrmsr_interception(struct vcpu_svm *svm)
2845 {
2846 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2847 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2848 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2849
2850
2851 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2852 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2853 trace_kvm_msr_write_ex(ecx, data);
2854 kvm_inject_gp(&svm->vcpu, 0);
2855 } else {
2856 trace_kvm_msr_write(ecx, data);
2857 skip_emulated_instruction(&svm->vcpu);
2858 }
2859 return 1;
2860 }
2861
2862 static int msr_interception(struct vcpu_svm *svm)
2863 {
2864 if (svm->vmcb->control.exit_info_1)
2865 return wrmsr_interception(svm);
2866 else
2867 return rdmsr_interception(svm);
2868 }
2869
2870 static int interrupt_window_interception(struct vcpu_svm *svm)
2871 {
2872 struct kvm_run *kvm_run = svm->vcpu.run;
2873
2874 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2875 svm_clear_vintr(svm);
2876 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2877 /*
2878 * If the user space waits to inject interrupts, exit as soon as
2879 * possible
2880 */
2881 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2882 kvm_run->request_interrupt_window &&
2883 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2884 ++svm->vcpu.stat.irq_window_exits;
2885 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2886 return 0;
2887 }
2888
2889 return 1;
2890 }
2891
2892 static int pause_interception(struct vcpu_svm *svm)
2893 {
2894 kvm_vcpu_on_spin(&(svm->vcpu));
2895 return 1;
2896 }
2897
2898 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2899 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2900 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2901 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2902 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2903 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2904 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2905 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2906 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2907 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2908 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2909 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2910 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2911 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2912 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2913 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2914 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2915 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2916 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2917 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2918 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2919 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2920 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2921 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2922 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2923 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2924 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2925 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2926 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2927 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2928 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2929 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2930 [SVM_EXIT_INTR] = intr_interception,
2931 [SVM_EXIT_NMI] = nmi_interception,
2932 [SVM_EXIT_SMI] = nop_on_interception,
2933 [SVM_EXIT_INIT] = nop_on_interception,
2934 [SVM_EXIT_VINTR] = interrupt_window_interception,
2935 [SVM_EXIT_CPUID] = cpuid_interception,
2936 [SVM_EXIT_IRET] = iret_interception,
2937 [SVM_EXIT_INVD] = emulate_on_interception,
2938 [SVM_EXIT_PAUSE] = pause_interception,
2939 [SVM_EXIT_HLT] = halt_interception,
2940 [SVM_EXIT_INVLPG] = invlpg_interception,
2941 [SVM_EXIT_INVLPGA] = invlpga_interception,
2942 [SVM_EXIT_IOIO] = io_interception,
2943 [SVM_EXIT_MSR] = msr_interception,
2944 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2945 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2946 [SVM_EXIT_VMRUN] = vmrun_interception,
2947 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2948 [SVM_EXIT_VMLOAD] = vmload_interception,
2949 [SVM_EXIT_VMSAVE] = vmsave_interception,
2950 [SVM_EXIT_STGI] = stgi_interception,
2951 [SVM_EXIT_CLGI] = clgi_interception,
2952 [SVM_EXIT_SKINIT] = skinit_interception,
2953 [SVM_EXIT_WBINVD] = emulate_on_interception,
2954 [SVM_EXIT_MONITOR] = invalid_op_interception,
2955 [SVM_EXIT_MWAIT] = invalid_op_interception,
2956 [SVM_EXIT_NPF] = pf_interception,
2957 };
2958
2959 void dump_vmcb(struct kvm_vcpu *vcpu)
2960 {
2961 struct vcpu_svm *svm = to_svm(vcpu);
2962 struct vmcb_control_area *control = &svm->vmcb->control;
2963 struct vmcb_save_area *save = &svm->vmcb->save;
2964
2965 pr_err("VMCB Control Area:\n");
2966 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2967 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2968 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2969 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2970 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2971 pr_err("intercepts: %016llx\n", control->intercept);
2972 pr_err("pause filter count: %d\n", control->pause_filter_count);
2973 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2974 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2975 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2976 pr_err("asid: %d\n", control->asid);
2977 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2978 pr_err("int_ctl: %08x\n", control->int_ctl);
2979 pr_err("int_vector: %08x\n", control->int_vector);
2980 pr_err("int_state: %08x\n", control->int_state);
2981 pr_err("exit_code: %08x\n", control->exit_code);
2982 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2983 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2984 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2985 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2986 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2987 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2988 pr_err("event_inj: %08x\n", control->event_inj);
2989 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2990 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2991 pr_err("next_rip: %016llx\n", control->next_rip);
2992 pr_err("VMCB State Save Area:\n");
2993 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2994 save->es.selector, save->es.attrib,
2995 save->es.limit, save->es.base);
2996 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2997 save->cs.selector, save->cs.attrib,
2998 save->cs.limit, save->cs.base);
2999 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3000 save->ss.selector, save->ss.attrib,
3001 save->ss.limit, save->ss.base);
3002 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3003 save->ds.selector, save->ds.attrib,
3004 save->ds.limit, save->ds.base);
3005 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3006 save->fs.selector, save->fs.attrib,
3007 save->fs.limit, save->fs.base);
3008 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3009 save->gs.selector, save->gs.attrib,
3010 save->gs.limit, save->gs.base);
3011 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3012 save->gdtr.selector, save->gdtr.attrib,
3013 save->gdtr.limit, save->gdtr.base);
3014 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3015 save->ldtr.selector, save->ldtr.attrib,
3016 save->ldtr.limit, save->ldtr.base);
3017 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3018 save->idtr.selector, save->idtr.attrib,
3019 save->idtr.limit, save->idtr.base);
3020 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3021 save->tr.selector, save->tr.attrib,
3022 save->tr.limit, save->tr.base);
3023 pr_err("cpl: %d efer: %016llx\n",
3024 save->cpl, save->efer);
3025 pr_err("cr0: %016llx cr2: %016llx\n",
3026 save->cr0, save->cr2);
3027 pr_err("cr3: %016llx cr4: %016llx\n",
3028 save->cr3, save->cr4);
3029 pr_err("dr6: %016llx dr7: %016llx\n",
3030 save->dr6, save->dr7);
3031 pr_err("rip: %016llx rflags: %016llx\n",
3032 save->rip, save->rflags);
3033 pr_err("rsp: %016llx rax: %016llx\n",
3034 save->rsp, save->rax);
3035 pr_err("star: %016llx lstar: %016llx\n",
3036 save->star, save->lstar);
3037 pr_err("cstar: %016llx sfmask: %016llx\n",
3038 save->cstar, save->sfmask);
3039 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3040 save->kernel_gs_base, save->sysenter_cs);
3041 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3042 save->sysenter_esp, save->sysenter_eip);
3043 pr_err("gpat: %016llx dbgctl: %016llx\n",
3044 save->g_pat, save->dbgctl);
3045 pr_err("br_from: %016llx br_to: %016llx\n",
3046 save->br_from, save->br_to);
3047 pr_err("excp_from: %016llx excp_to: %016llx\n",
3048 save->last_excp_from, save->last_excp_to);
3049
3050 }
3051
3052 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3053 {
3054 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3055
3056 *info1 = control->exit_info_1;
3057 *info2 = control->exit_info_2;
3058 }
3059
3060 static int handle_exit(struct kvm_vcpu *vcpu)
3061 {
3062 struct vcpu_svm *svm = to_svm(vcpu);
3063 struct kvm_run *kvm_run = vcpu->run;
3064 u32 exit_code = svm->vmcb->control.exit_code;
3065
3066 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3067
3068 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3069 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3070 if (npt_enabled)
3071 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3072
3073 if (unlikely(svm->nested.exit_required)) {
3074 nested_svm_vmexit(svm);
3075 svm->nested.exit_required = false;
3076
3077 return 1;
3078 }
3079
3080 if (is_guest_mode(vcpu)) {
3081 int vmexit;
3082
3083 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3084 svm->vmcb->control.exit_info_1,
3085 svm->vmcb->control.exit_info_2,
3086 svm->vmcb->control.exit_int_info,
3087 svm->vmcb->control.exit_int_info_err);
3088
3089 vmexit = nested_svm_exit_special(svm);
3090
3091 if (vmexit == NESTED_EXIT_CONTINUE)
3092 vmexit = nested_svm_exit_handled(svm);
3093
3094 if (vmexit == NESTED_EXIT_DONE)
3095 return 1;
3096 }
3097
3098 svm_complete_interrupts(svm);
3099
3100 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3101 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3102 kvm_run->fail_entry.hardware_entry_failure_reason
3103 = svm->vmcb->control.exit_code;
3104 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3105 dump_vmcb(vcpu);
3106 return 0;
3107 }
3108
3109 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3110 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3111 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3112 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3113 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3114 "exit_code 0x%x\n",
3115 __func__, svm->vmcb->control.exit_int_info,
3116 exit_code);
3117
3118 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3119 || !svm_exit_handlers[exit_code]) {
3120 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3121 kvm_run->hw.hardware_exit_reason = exit_code;
3122 return 0;
3123 }
3124
3125 return svm_exit_handlers[exit_code](svm);
3126 }
3127
3128 static void reload_tss(struct kvm_vcpu *vcpu)
3129 {
3130 int cpu = raw_smp_processor_id();
3131
3132 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3133 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3134 load_TR_desc();
3135 }
3136
3137 static void pre_svm_run(struct vcpu_svm *svm)
3138 {
3139 int cpu = raw_smp_processor_id();
3140
3141 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3142
3143 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3144 /* FIXME: handle wraparound of asid_generation */
3145 if (svm->asid_generation != sd->asid_generation)
3146 new_asid(svm, sd);
3147 }
3148
3149 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3150 {
3151 struct vcpu_svm *svm = to_svm(vcpu);
3152
3153 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3154 vcpu->arch.hflags |= HF_NMI_MASK;
3155 set_intercept(svm, INTERCEPT_IRET);
3156 ++vcpu->stat.nmi_injections;
3157 }
3158
3159 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3160 {
3161 struct vmcb_control_area *control;
3162
3163 control = &svm->vmcb->control;
3164 control->int_vector = irq;
3165 control->int_ctl &= ~V_INTR_PRIO_MASK;
3166 control->int_ctl |= V_IRQ_MASK |
3167 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3168 }
3169
3170 static void svm_set_irq(struct kvm_vcpu *vcpu)
3171 {
3172 struct vcpu_svm *svm = to_svm(vcpu);
3173
3174 BUG_ON(!(gif_set(svm)));
3175
3176 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3177 ++vcpu->stat.irq_injections;
3178
3179 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3180 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3181 }
3182
3183 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3184 {
3185 struct vcpu_svm *svm = to_svm(vcpu);
3186
3187 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3188 return;
3189
3190 if (irr == -1)
3191 return;
3192
3193 if (tpr >= irr)
3194 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3195 }
3196
3197 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3198 {
3199 struct vcpu_svm *svm = to_svm(vcpu);
3200 struct vmcb *vmcb = svm->vmcb;
3201 int ret;
3202 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3203 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3204 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3205
3206 return ret;
3207 }
3208
3209 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3210 {
3211 struct vcpu_svm *svm = to_svm(vcpu);
3212
3213 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3214 }
3215
3216 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3217 {
3218 struct vcpu_svm *svm = to_svm(vcpu);
3219
3220 if (masked) {
3221 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3222 set_intercept(svm, INTERCEPT_IRET);
3223 } else {
3224 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3225 clr_intercept(svm, INTERCEPT_IRET);
3226 }
3227 }
3228
3229 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3230 {
3231 struct vcpu_svm *svm = to_svm(vcpu);
3232 struct vmcb *vmcb = svm->vmcb;
3233 int ret;
3234
3235 if (!gif_set(svm) ||
3236 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3237 return 0;
3238
3239 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3240
3241 if (is_guest_mode(vcpu))
3242 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3243
3244 return ret;
3245 }
3246
3247 static void enable_irq_window(struct kvm_vcpu *vcpu)
3248 {
3249 struct vcpu_svm *svm = to_svm(vcpu);
3250
3251 /*
3252 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3253 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3254 * get that intercept, this function will be called again though and
3255 * we'll get the vintr intercept.
3256 */
3257 if (gif_set(svm) && nested_svm_intr(svm)) {
3258 svm_set_vintr(svm);
3259 svm_inject_irq(svm, 0x0);
3260 }
3261 }
3262
3263 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3264 {
3265 struct vcpu_svm *svm = to_svm(vcpu);
3266
3267 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3268 == HF_NMI_MASK)
3269 return; /* IRET will cause a vm exit */
3270
3271 /*
3272 * Something prevents NMI from been injected. Single step over possible
3273 * problem (IRET or exception injection or interrupt shadow)
3274 */
3275 svm->nmi_singlestep = true;
3276 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3277 update_db_intercept(vcpu);
3278 }
3279
3280 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3281 {
3282 return 0;
3283 }
3284
3285 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3286 {
3287 force_new_asid(vcpu);
3288 }
3289
3290 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3291 {
3292 }
3293
3294 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3295 {
3296 struct vcpu_svm *svm = to_svm(vcpu);
3297
3298 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3299 return;
3300
3301 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3302 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3303 kvm_set_cr8(vcpu, cr8);
3304 }
3305 }
3306
3307 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3308 {
3309 struct vcpu_svm *svm = to_svm(vcpu);
3310 u64 cr8;
3311
3312 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3313 return;
3314
3315 cr8 = kvm_get_cr8(vcpu);
3316 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3317 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3318 }
3319
3320 static void svm_complete_interrupts(struct vcpu_svm *svm)
3321 {
3322 u8 vector;
3323 int type;
3324 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3325 unsigned int3_injected = svm->int3_injected;
3326
3327 svm->int3_injected = 0;
3328
3329 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3330 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3331 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3332 }
3333
3334 svm->vcpu.arch.nmi_injected = false;
3335 kvm_clear_exception_queue(&svm->vcpu);
3336 kvm_clear_interrupt_queue(&svm->vcpu);
3337
3338 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3339 return;
3340
3341 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3342
3343 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3344 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3345
3346 switch (type) {
3347 case SVM_EXITINTINFO_TYPE_NMI:
3348 svm->vcpu.arch.nmi_injected = true;
3349 break;
3350 case SVM_EXITINTINFO_TYPE_EXEPT:
3351 /*
3352 * In case of software exceptions, do not reinject the vector,
3353 * but re-execute the instruction instead. Rewind RIP first
3354 * if we emulated INT3 before.
3355 */
3356 if (kvm_exception_is_soft(vector)) {
3357 if (vector == BP_VECTOR && int3_injected &&
3358 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3359 kvm_rip_write(&svm->vcpu,
3360 kvm_rip_read(&svm->vcpu) -
3361 int3_injected);
3362 break;
3363 }
3364 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3365 u32 err = svm->vmcb->control.exit_int_info_err;
3366 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3367
3368 } else
3369 kvm_requeue_exception(&svm->vcpu, vector);
3370 break;
3371 case SVM_EXITINTINFO_TYPE_INTR:
3372 kvm_queue_interrupt(&svm->vcpu, vector, false);
3373 break;
3374 default:
3375 break;
3376 }
3377 }
3378
3379 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3380 {
3381 struct vcpu_svm *svm = to_svm(vcpu);
3382 struct vmcb_control_area *control = &svm->vmcb->control;
3383
3384 control->exit_int_info = control->event_inj;
3385 control->exit_int_info_err = control->event_inj_err;
3386 control->event_inj = 0;
3387 svm_complete_interrupts(svm);
3388 }
3389
3390 #ifdef CONFIG_X86_64
3391 #define R "r"
3392 #else
3393 #define R "e"
3394 #endif
3395
3396 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3397 {
3398 struct vcpu_svm *svm = to_svm(vcpu);
3399
3400 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3401 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3402 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3403
3404 /*
3405 * A vmexit emulation is required before the vcpu can be executed
3406 * again.
3407 */
3408 if (unlikely(svm->nested.exit_required))
3409 return;
3410
3411 pre_svm_run(svm);
3412
3413 sync_lapic_to_cr8(vcpu);
3414
3415 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3416
3417 clgi();
3418
3419 local_irq_enable();
3420
3421 asm volatile (
3422 "push %%"R"bp; \n\t"
3423 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3424 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3425 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3426 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3427 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3428 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3429 #ifdef CONFIG_X86_64
3430 "mov %c[r8](%[svm]), %%r8 \n\t"
3431 "mov %c[r9](%[svm]), %%r9 \n\t"
3432 "mov %c[r10](%[svm]), %%r10 \n\t"
3433 "mov %c[r11](%[svm]), %%r11 \n\t"
3434 "mov %c[r12](%[svm]), %%r12 \n\t"
3435 "mov %c[r13](%[svm]), %%r13 \n\t"
3436 "mov %c[r14](%[svm]), %%r14 \n\t"
3437 "mov %c[r15](%[svm]), %%r15 \n\t"
3438 #endif
3439
3440 /* Enter guest mode */
3441 "push %%"R"ax \n\t"
3442 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3443 __ex(SVM_VMLOAD) "\n\t"
3444 __ex(SVM_VMRUN) "\n\t"
3445 __ex(SVM_VMSAVE) "\n\t"
3446 "pop %%"R"ax \n\t"
3447
3448 /* Save guest registers, load host registers */
3449 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3450 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3451 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3452 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3453 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3454 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3455 #ifdef CONFIG_X86_64
3456 "mov %%r8, %c[r8](%[svm]) \n\t"
3457 "mov %%r9, %c[r9](%[svm]) \n\t"
3458 "mov %%r10, %c[r10](%[svm]) \n\t"
3459 "mov %%r11, %c[r11](%[svm]) \n\t"
3460 "mov %%r12, %c[r12](%[svm]) \n\t"
3461 "mov %%r13, %c[r13](%[svm]) \n\t"
3462 "mov %%r14, %c[r14](%[svm]) \n\t"
3463 "mov %%r15, %c[r15](%[svm]) \n\t"
3464 #endif
3465 "pop %%"R"bp"
3466 :
3467 : [svm]"a"(svm),
3468 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3469 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3470 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3471 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3472 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3473 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3474 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3475 #ifdef CONFIG_X86_64
3476 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3477 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3478 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3479 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3480 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3481 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3482 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3483 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3484 #endif
3485 : "cc", "memory"
3486 , R"bx", R"cx", R"dx", R"si", R"di"
3487 #ifdef CONFIG_X86_64
3488 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3489 #endif
3490 );
3491
3492 #ifdef CONFIG_X86_64
3493 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3494 #else
3495 loadsegment(fs, svm->host.fs);
3496 #endif
3497
3498 reload_tss(vcpu);
3499
3500 local_irq_disable();
3501
3502 stgi();
3503
3504 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3505 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3506 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3507 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3508
3509 sync_cr8_to_lapic(vcpu);
3510
3511 svm->next_rip = 0;
3512
3513 /* if exit due to PF check for async PF */
3514 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3515 svm->apf_reason = kvm_read_and_reset_pf_reason();
3516
3517 if (npt_enabled) {
3518 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3519 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3520 }
3521
3522 /*
3523 * We need to handle MC intercepts here before the vcpu has a chance to
3524 * change the physical cpu
3525 */
3526 if (unlikely(svm->vmcb->control.exit_code ==
3527 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3528 svm_handle_mce(svm);
3529
3530 mark_all_clean(svm->vmcb);
3531 }
3532
3533 #undef R
3534
3535 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3536 {
3537 struct vcpu_svm *svm = to_svm(vcpu);
3538
3539 svm->vmcb->save.cr3 = root;
3540 force_new_asid(vcpu);
3541 }
3542
3543 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3544 {
3545 struct vcpu_svm *svm = to_svm(vcpu);
3546
3547 svm->vmcb->control.nested_cr3 = root;
3548
3549 /* Also sync guest cr3 here in case we live migrate */
3550 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3551
3552 force_new_asid(vcpu);
3553 }
3554
3555 static int is_disabled(void)
3556 {
3557 u64 vm_cr;
3558
3559 rdmsrl(MSR_VM_CR, vm_cr);
3560 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3561 return 1;
3562
3563 return 0;
3564 }
3565
3566 static void
3567 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3568 {
3569 /*
3570 * Patch in the VMMCALL instruction:
3571 */
3572 hypercall[0] = 0x0f;
3573 hypercall[1] = 0x01;
3574 hypercall[2] = 0xd9;
3575 }
3576
3577 static void svm_check_processor_compat(void *rtn)
3578 {
3579 *(int *)rtn = 0;
3580 }
3581
3582 static bool svm_cpu_has_accelerated_tpr(void)
3583 {
3584 return false;
3585 }
3586
3587 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3588 {
3589 return 0;
3590 }
3591
3592 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3593 {
3594 }
3595
3596 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3597 {
3598 switch (func) {
3599 case 0x00000001:
3600 /* Mask out xsave bit as long as it is not supported by SVM */
3601 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3602 break;
3603 case 0x80000001:
3604 if (nested)
3605 entry->ecx |= (1 << 2); /* Set SVM bit */
3606 break;
3607 case 0x8000000A:
3608 entry->eax = 1; /* SVM revision 1 */
3609 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3610 ASID emulation to nested SVM */
3611 entry->ecx = 0; /* Reserved */
3612 entry->edx = 0; /* Per default do not support any
3613 additional features */
3614
3615 /* Support next_rip if host supports it */
3616 if (boot_cpu_has(X86_FEATURE_NRIPS))
3617 entry->edx |= SVM_FEATURE_NRIP;
3618
3619 /* Support NPT for the guest if enabled */
3620 if (npt_enabled)
3621 entry->edx |= SVM_FEATURE_NPT;
3622
3623 break;
3624 }
3625 }
3626
3627 static const struct trace_print_flags svm_exit_reasons_str[] = {
3628 { SVM_EXIT_READ_CR0, "read_cr0" },
3629 { SVM_EXIT_READ_CR3, "read_cr3" },
3630 { SVM_EXIT_READ_CR4, "read_cr4" },
3631 { SVM_EXIT_READ_CR8, "read_cr8" },
3632 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3633 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3634 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3635 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3636 { SVM_EXIT_READ_DR0, "read_dr0" },
3637 { SVM_EXIT_READ_DR1, "read_dr1" },
3638 { SVM_EXIT_READ_DR2, "read_dr2" },
3639 { SVM_EXIT_READ_DR3, "read_dr3" },
3640 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3641 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3642 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3643 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3644 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3645 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3646 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3647 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3648 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3649 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3650 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3651 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3652 { SVM_EXIT_INTR, "interrupt" },
3653 { SVM_EXIT_NMI, "nmi" },
3654 { SVM_EXIT_SMI, "smi" },
3655 { SVM_EXIT_INIT, "init" },
3656 { SVM_EXIT_VINTR, "vintr" },
3657 { SVM_EXIT_CPUID, "cpuid" },
3658 { SVM_EXIT_INVD, "invd" },
3659 { SVM_EXIT_HLT, "hlt" },
3660 { SVM_EXIT_INVLPG, "invlpg" },
3661 { SVM_EXIT_INVLPGA, "invlpga" },
3662 { SVM_EXIT_IOIO, "io" },
3663 { SVM_EXIT_MSR, "msr" },
3664 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3665 { SVM_EXIT_SHUTDOWN, "shutdown" },
3666 { SVM_EXIT_VMRUN, "vmrun" },
3667 { SVM_EXIT_VMMCALL, "hypercall" },
3668 { SVM_EXIT_VMLOAD, "vmload" },
3669 { SVM_EXIT_VMSAVE, "vmsave" },
3670 { SVM_EXIT_STGI, "stgi" },
3671 { SVM_EXIT_CLGI, "clgi" },
3672 { SVM_EXIT_SKINIT, "skinit" },
3673 { SVM_EXIT_WBINVD, "wbinvd" },
3674 { SVM_EXIT_MONITOR, "monitor" },
3675 { SVM_EXIT_MWAIT, "mwait" },
3676 { SVM_EXIT_NPF, "npf" },
3677 { -1, NULL }
3678 };
3679
3680 static int svm_get_lpage_level(void)
3681 {
3682 return PT_PDPE_LEVEL;
3683 }
3684
3685 static bool svm_rdtscp_supported(void)
3686 {
3687 return false;
3688 }
3689
3690 static bool svm_has_wbinvd_exit(void)
3691 {
3692 return true;
3693 }
3694
3695 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3696 {
3697 struct vcpu_svm *svm = to_svm(vcpu);
3698
3699 set_exception_intercept(svm, NM_VECTOR);
3700 update_cr0_intercept(svm);
3701 }
3702
3703 static struct kvm_x86_ops svm_x86_ops = {
3704 .cpu_has_kvm_support = has_svm,
3705 .disabled_by_bios = is_disabled,
3706 .hardware_setup = svm_hardware_setup,
3707 .hardware_unsetup = svm_hardware_unsetup,
3708 .check_processor_compatibility = svm_check_processor_compat,
3709 .hardware_enable = svm_hardware_enable,
3710 .hardware_disable = svm_hardware_disable,
3711 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3712
3713 .vcpu_create = svm_create_vcpu,
3714 .vcpu_free = svm_free_vcpu,
3715 .vcpu_reset = svm_vcpu_reset,
3716
3717 .prepare_guest_switch = svm_prepare_guest_switch,
3718 .vcpu_load = svm_vcpu_load,
3719 .vcpu_put = svm_vcpu_put,
3720
3721 .set_guest_debug = svm_guest_debug,
3722 .get_msr = svm_get_msr,
3723 .set_msr = svm_set_msr,
3724 .get_segment_base = svm_get_segment_base,
3725 .get_segment = svm_get_segment,
3726 .set_segment = svm_set_segment,
3727 .get_cpl = svm_get_cpl,
3728 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3729 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3730 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3731 .set_cr0 = svm_set_cr0,
3732 .set_cr3 = svm_set_cr3,
3733 .set_cr4 = svm_set_cr4,
3734 .set_efer = svm_set_efer,
3735 .get_idt = svm_get_idt,
3736 .set_idt = svm_set_idt,
3737 .get_gdt = svm_get_gdt,
3738 .set_gdt = svm_set_gdt,
3739 .set_dr7 = svm_set_dr7,
3740 .cache_reg = svm_cache_reg,
3741 .get_rflags = svm_get_rflags,
3742 .set_rflags = svm_set_rflags,
3743 .fpu_activate = svm_fpu_activate,
3744 .fpu_deactivate = svm_fpu_deactivate,
3745
3746 .tlb_flush = svm_flush_tlb,
3747
3748 .run = svm_vcpu_run,
3749 .handle_exit = handle_exit,
3750 .skip_emulated_instruction = skip_emulated_instruction,
3751 .set_interrupt_shadow = svm_set_interrupt_shadow,
3752 .get_interrupt_shadow = svm_get_interrupt_shadow,
3753 .patch_hypercall = svm_patch_hypercall,
3754 .set_irq = svm_set_irq,
3755 .set_nmi = svm_inject_nmi,
3756 .queue_exception = svm_queue_exception,
3757 .cancel_injection = svm_cancel_injection,
3758 .interrupt_allowed = svm_interrupt_allowed,
3759 .nmi_allowed = svm_nmi_allowed,
3760 .get_nmi_mask = svm_get_nmi_mask,
3761 .set_nmi_mask = svm_set_nmi_mask,
3762 .enable_nmi_window = enable_nmi_window,
3763 .enable_irq_window = enable_irq_window,
3764 .update_cr8_intercept = update_cr8_intercept,
3765
3766 .set_tss_addr = svm_set_tss_addr,
3767 .get_tdp_level = get_npt_level,
3768 .get_mt_mask = svm_get_mt_mask,
3769
3770 .get_exit_info = svm_get_exit_info,
3771 .exit_reasons_str = svm_exit_reasons_str,
3772
3773 .get_lpage_level = svm_get_lpage_level,
3774
3775 .cpuid_update = svm_cpuid_update,
3776
3777 .rdtscp_supported = svm_rdtscp_supported,
3778
3779 .set_supported_cpuid = svm_set_supported_cpuid,
3780
3781 .has_wbinvd_exit = svm_has_wbinvd_exit,
3782
3783 .write_tsc_offset = svm_write_tsc_offset,
3784 .adjust_tsc_offset = svm_adjust_tsc_offset,
3785
3786 .set_tdp_cr3 = set_tdp_cr3,
3787 };
3788
3789 static int __init svm_init(void)
3790 {
3791 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3792 __alignof__(struct vcpu_svm), THIS_MODULE);
3793 }
3794
3795 static void __exit svm_exit(void)
3796 {
3797 kvm_exit();
3798 }
3799
3800 module_init(svm_init)
3801 module_exit(svm_exit)
Linux kernel - Deliverables
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