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KVM: SVM: Add manipulation functions for exception intercepts
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
189 {
190 return container_of(vcpu, struct vcpu_svm, vcpu);
191 }
192
193 static void recalc_intercepts(struct vcpu_svm *svm)
194 {
195 struct vmcb_control_area *c, *h;
196 struct nested_state *g;
197
198 if (!is_guest_mode(&svm->vcpu))
199 return;
200
201 c = &svm->vmcb->control;
202 h = &svm->nested.hsave->control;
203 g = &svm->nested;
204
205 c->intercept_cr = h->intercept_cr | g->intercept_cr;
206 c->intercept_dr = h->intercept_dr | g->intercept_dr;
207 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
208 c->intercept = h->intercept | g->intercept;
209 }
210
211 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
212 {
213 if (is_guest_mode(&svm->vcpu))
214 return svm->nested.hsave;
215 else
216 return svm->vmcb;
217 }
218
219 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
220 {
221 struct vmcb *vmcb = get_host_vmcb(svm);
222
223 vmcb->control.intercept_cr |= (1U << bit);
224
225 recalc_intercepts(svm);
226 }
227
228 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
229 {
230 struct vmcb *vmcb = get_host_vmcb(svm);
231
232 vmcb->control.intercept_cr &= ~(1U << bit);
233
234 recalc_intercepts(svm);
235 }
236
237 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
238 {
239 struct vmcb *vmcb = get_host_vmcb(svm);
240
241 return vmcb->control.intercept_cr & (1U << bit);
242 }
243
244 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
245 {
246 struct vmcb *vmcb = get_host_vmcb(svm);
247
248 vmcb->control.intercept_dr |= (1U << bit);
249
250 recalc_intercepts(svm);
251 }
252
253 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
254 {
255 struct vmcb *vmcb = get_host_vmcb(svm);
256
257 vmcb->control.intercept_dr &= ~(1U << bit);
258
259 recalc_intercepts(svm);
260 }
261
262 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
263 {
264 struct vmcb *vmcb = get_host_vmcb(svm);
265
266 vmcb->control.intercept_exceptions |= (1U << bit);
267
268 recalc_intercepts(svm);
269 }
270
271 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
272 {
273 struct vmcb *vmcb = get_host_vmcb(svm);
274
275 vmcb->control.intercept_exceptions &= ~(1U << bit);
276
277 recalc_intercepts(svm);
278 }
279
280 static inline void enable_gif(struct vcpu_svm *svm)
281 {
282 svm->vcpu.arch.hflags |= HF_GIF_MASK;
283 }
284
285 static inline void disable_gif(struct vcpu_svm *svm)
286 {
287 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
288 }
289
290 static inline bool gif_set(struct vcpu_svm *svm)
291 {
292 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
293 }
294
295 static unsigned long iopm_base;
296
297 struct kvm_ldttss_desc {
298 u16 limit0;
299 u16 base0;
300 unsigned base1:8, type:5, dpl:2, p:1;
301 unsigned limit1:4, zero0:3, g:1, base2:8;
302 u32 base3;
303 u32 zero1;
304 } __attribute__((packed));
305
306 struct svm_cpu_data {
307 int cpu;
308
309 u64 asid_generation;
310 u32 max_asid;
311 u32 next_asid;
312 struct kvm_ldttss_desc *tss_desc;
313
314 struct page *save_area;
315 };
316
317 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
318 static uint32_t svm_features;
319
320 struct svm_init_data {
321 int cpu;
322 int r;
323 };
324
325 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
326
327 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
328 #define MSRS_RANGE_SIZE 2048
329 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
330
331 static u32 svm_msrpm_offset(u32 msr)
332 {
333 u32 offset;
334 int i;
335
336 for (i = 0; i < NUM_MSR_MAPS; i++) {
337 if (msr < msrpm_ranges[i] ||
338 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
339 continue;
340
341 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
342 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
343
344 /* Now we have the u8 offset - but need the u32 offset */
345 return offset / 4;
346 }
347
348 /* MSR not in any range */
349 return MSR_INVALID;
350 }
351
352 #define MAX_INST_SIZE 15
353
354 static inline void clgi(void)
355 {
356 asm volatile (__ex(SVM_CLGI));
357 }
358
359 static inline void stgi(void)
360 {
361 asm volatile (__ex(SVM_STGI));
362 }
363
364 static inline void invlpga(unsigned long addr, u32 asid)
365 {
366 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
367 }
368
369 static inline void force_new_asid(struct kvm_vcpu *vcpu)
370 {
371 to_svm(vcpu)->asid_generation--;
372 }
373
374 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
375 {
376 force_new_asid(vcpu);
377 }
378
379 static int get_npt_level(void)
380 {
381 #ifdef CONFIG_X86_64
382 return PT64_ROOT_LEVEL;
383 #else
384 return PT32E_ROOT_LEVEL;
385 #endif
386 }
387
388 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
389 {
390 vcpu->arch.efer = efer;
391 if (!npt_enabled && !(efer & EFER_LMA))
392 efer &= ~EFER_LME;
393
394 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
395 }
396
397 static int is_external_interrupt(u32 info)
398 {
399 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
400 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
401 }
402
403 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
404 {
405 struct vcpu_svm *svm = to_svm(vcpu);
406 u32 ret = 0;
407
408 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
409 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
410 return ret & mask;
411 }
412
413 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
414 {
415 struct vcpu_svm *svm = to_svm(vcpu);
416
417 if (mask == 0)
418 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
419 else
420 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
421
422 }
423
424 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
425 {
426 struct vcpu_svm *svm = to_svm(vcpu);
427
428 if (svm->vmcb->control.next_rip != 0)
429 svm->next_rip = svm->vmcb->control.next_rip;
430
431 if (!svm->next_rip) {
432 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
433 EMULATE_DONE)
434 printk(KERN_DEBUG "%s: NOP\n", __func__);
435 return;
436 }
437 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
438 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
439 __func__, kvm_rip_read(vcpu), svm->next_rip);
440
441 kvm_rip_write(vcpu, svm->next_rip);
442 svm_set_interrupt_shadow(vcpu, 0);
443 }
444
445 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
446 bool has_error_code, u32 error_code,
447 bool reinject)
448 {
449 struct vcpu_svm *svm = to_svm(vcpu);
450
451 /*
452 * If we are within a nested VM we'd better #VMEXIT and let the guest
453 * handle the exception
454 */
455 if (!reinject &&
456 nested_svm_check_exception(svm, nr, has_error_code, error_code))
457 return;
458
459 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
460 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
461
462 /*
463 * For guest debugging where we have to reinject #BP if some
464 * INT3 is guest-owned:
465 * Emulate nRIP by moving RIP forward. Will fail if injection
466 * raises a fault that is not intercepted. Still better than
467 * failing in all cases.
468 */
469 skip_emulated_instruction(&svm->vcpu);
470 rip = kvm_rip_read(&svm->vcpu);
471 svm->int3_rip = rip + svm->vmcb->save.cs.base;
472 svm->int3_injected = rip - old_rip;
473 }
474
475 svm->vmcb->control.event_inj = nr
476 | SVM_EVTINJ_VALID
477 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
478 | SVM_EVTINJ_TYPE_EXEPT;
479 svm->vmcb->control.event_inj_err = error_code;
480 }
481
482 static void svm_init_erratum_383(void)
483 {
484 u32 low, high;
485 int err;
486 u64 val;
487
488 if (!cpu_has_amd_erratum(amd_erratum_383))
489 return;
490
491 /* Use _safe variants to not break nested virtualization */
492 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
493 if (err)
494 return;
495
496 val |= (1ULL << 47);
497
498 low = lower_32_bits(val);
499 high = upper_32_bits(val);
500
501 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
502
503 erratum_383_found = true;
504 }
505
506 static int has_svm(void)
507 {
508 const char *msg;
509
510 if (!cpu_has_svm(&msg)) {
511 printk(KERN_INFO "has_svm: %s\n", msg);
512 return 0;
513 }
514
515 return 1;
516 }
517
518 static void svm_hardware_disable(void *garbage)
519 {
520 cpu_svm_disable();
521 }
522
523 static int svm_hardware_enable(void *garbage)
524 {
525
526 struct svm_cpu_data *sd;
527 uint64_t efer;
528 struct desc_ptr gdt_descr;
529 struct desc_struct *gdt;
530 int me = raw_smp_processor_id();
531
532 rdmsrl(MSR_EFER, efer);
533 if (efer & EFER_SVME)
534 return -EBUSY;
535
536 if (!has_svm()) {
537 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
538 me);
539 return -EINVAL;
540 }
541 sd = per_cpu(svm_data, me);
542
543 if (!sd) {
544 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
545 me);
546 return -EINVAL;
547 }
548
549 sd->asid_generation = 1;
550 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
551 sd->next_asid = sd->max_asid + 1;
552
553 native_store_gdt(&gdt_descr);
554 gdt = (struct desc_struct *)gdt_descr.address;
555 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
556
557 wrmsrl(MSR_EFER, efer | EFER_SVME);
558
559 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
560
561 svm_init_erratum_383();
562
563 return 0;
564 }
565
566 static void svm_cpu_uninit(int cpu)
567 {
568 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
569
570 if (!sd)
571 return;
572
573 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
574 __free_page(sd->save_area);
575 kfree(sd);
576 }
577
578 static int svm_cpu_init(int cpu)
579 {
580 struct svm_cpu_data *sd;
581 int r;
582
583 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
584 if (!sd)
585 return -ENOMEM;
586 sd->cpu = cpu;
587 sd->save_area = alloc_page(GFP_KERNEL);
588 r = -ENOMEM;
589 if (!sd->save_area)
590 goto err_1;
591
592 per_cpu(svm_data, cpu) = sd;
593
594 return 0;
595
596 err_1:
597 kfree(sd);
598 return r;
599
600 }
601
602 static bool valid_msr_intercept(u32 index)
603 {
604 int i;
605
606 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
607 if (direct_access_msrs[i].index == index)
608 return true;
609
610 return false;
611 }
612
613 static void set_msr_interception(u32 *msrpm, unsigned msr,
614 int read, int write)
615 {
616 u8 bit_read, bit_write;
617 unsigned long tmp;
618 u32 offset;
619
620 /*
621 * If this warning triggers extend the direct_access_msrs list at the
622 * beginning of the file
623 */
624 WARN_ON(!valid_msr_intercept(msr));
625
626 offset = svm_msrpm_offset(msr);
627 bit_read = 2 * (msr & 0x0f);
628 bit_write = 2 * (msr & 0x0f) + 1;
629 tmp = msrpm[offset];
630
631 BUG_ON(offset == MSR_INVALID);
632
633 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
634 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
635
636 msrpm[offset] = tmp;
637 }
638
639 static void svm_vcpu_init_msrpm(u32 *msrpm)
640 {
641 int i;
642
643 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
644
645 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
646 if (!direct_access_msrs[i].always)
647 continue;
648
649 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
650 }
651 }
652
653 static void add_msr_offset(u32 offset)
654 {
655 int i;
656
657 for (i = 0; i < MSRPM_OFFSETS; ++i) {
658
659 /* Offset already in list? */
660 if (msrpm_offsets[i] == offset)
661 return;
662
663 /* Slot used by another offset? */
664 if (msrpm_offsets[i] != MSR_INVALID)
665 continue;
666
667 /* Add offset to list */
668 msrpm_offsets[i] = offset;
669
670 return;
671 }
672
673 /*
674 * If this BUG triggers the msrpm_offsets table has an overflow. Just
675 * increase MSRPM_OFFSETS in this case.
676 */
677 BUG();
678 }
679
680 static void init_msrpm_offsets(void)
681 {
682 int i;
683
684 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
685
686 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
687 u32 offset;
688
689 offset = svm_msrpm_offset(direct_access_msrs[i].index);
690 BUG_ON(offset == MSR_INVALID);
691
692 add_msr_offset(offset);
693 }
694 }
695
696 static void svm_enable_lbrv(struct vcpu_svm *svm)
697 {
698 u32 *msrpm = svm->msrpm;
699
700 svm->vmcb->control.lbr_ctl = 1;
701 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
702 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
703 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
704 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
705 }
706
707 static void svm_disable_lbrv(struct vcpu_svm *svm)
708 {
709 u32 *msrpm = svm->msrpm;
710
711 svm->vmcb->control.lbr_ctl = 0;
712 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
713 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
714 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
715 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
716 }
717
718 static __init int svm_hardware_setup(void)
719 {
720 int cpu;
721 struct page *iopm_pages;
722 void *iopm_va;
723 int r;
724
725 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
726
727 if (!iopm_pages)
728 return -ENOMEM;
729
730 iopm_va = page_address(iopm_pages);
731 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
732 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
733
734 init_msrpm_offsets();
735
736 if (boot_cpu_has(X86_FEATURE_NX))
737 kvm_enable_efer_bits(EFER_NX);
738
739 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
740 kvm_enable_efer_bits(EFER_FFXSR);
741
742 if (nested) {
743 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
744 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
745 }
746
747 for_each_possible_cpu(cpu) {
748 r = svm_cpu_init(cpu);
749 if (r)
750 goto err;
751 }
752
753 svm_features = cpuid_edx(SVM_CPUID_FUNC);
754
755 if (!boot_cpu_has(X86_FEATURE_NPT))
756 npt_enabled = false;
757
758 if (npt_enabled && !npt) {
759 printk(KERN_INFO "kvm: Nested Paging disabled\n");
760 npt_enabled = false;
761 }
762
763 if (npt_enabled) {
764 printk(KERN_INFO "kvm: Nested Paging enabled\n");
765 kvm_enable_tdp();
766 } else
767 kvm_disable_tdp();
768
769 return 0;
770
771 err:
772 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
773 iopm_base = 0;
774 return r;
775 }
776
777 static __exit void svm_hardware_unsetup(void)
778 {
779 int cpu;
780
781 for_each_possible_cpu(cpu)
782 svm_cpu_uninit(cpu);
783
784 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
785 iopm_base = 0;
786 }
787
788 static void init_seg(struct vmcb_seg *seg)
789 {
790 seg->selector = 0;
791 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
792 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
793 seg->limit = 0xffff;
794 seg->base = 0;
795 }
796
797 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
798 {
799 seg->selector = 0;
800 seg->attrib = SVM_SELECTOR_P_MASK | type;
801 seg->limit = 0xffff;
802 seg->base = 0;
803 }
804
805 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
806 {
807 struct vcpu_svm *svm = to_svm(vcpu);
808 u64 g_tsc_offset = 0;
809
810 if (is_guest_mode(vcpu)) {
811 g_tsc_offset = svm->vmcb->control.tsc_offset -
812 svm->nested.hsave->control.tsc_offset;
813 svm->nested.hsave->control.tsc_offset = offset;
814 }
815
816 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
817 }
818
819 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
820 {
821 struct vcpu_svm *svm = to_svm(vcpu);
822
823 svm->vmcb->control.tsc_offset += adjustment;
824 if (is_guest_mode(vcpu))
825 svm->nested.hsave->control.tsc_offset += adjustment;
826 }
827
828 static void init_vmcb(struct vcpu_svm *svm)
829 {
830 struct vmcb_control_area *control = &svm->vmcb->control;
831 struct vmcb_save_area *save = &svm->vmcb->save;
832
833 svm->vcpu.fpu_active = 1;
834 svm->vcpu.arch.hflags = 0;
835
836 set_cr_intercept(svm, INTERCEPT_CR0_READ);
837 set_cr_intercept(svm, INTERCEPT_CR3_READ);
838 set_cr_intercept(svm, INTERCEPT_CR4_READ);
839 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
840 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
841 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
842 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
843
844 set_dr_intercept(svm, INTERCEPT_DR0_READ);
845 set_dr_intercept(svm, INTERCEPT_DR1_READ);
846 set_dr_intercept(svm, INTERCEPT_DR2_READ);
847 set_dr_intercept(svm, INTERCEPT_DR3_READ);
848 set_dr_intercept(svm, INTERCEPT_DR4_READ);
849 set_dr_intercept(svm, INTERCEPT_DR5_READ);
850 set_dr_intercept(svm, INTERCEPT_DR6_READ);
851 set_dr_intercept(svm, INTERCEPT_DR7_READ);
852
853 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
854 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
855 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
856 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
857 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
858 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
859 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
860 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
861
862 set_exception_intercept(svm, PF_VECTOR);
863 set_exception_intercept(svm, UD_VECTOR);
864 set_exception_intercept(svm, MC_VECTOR);
865
866 control->intercept = (1ULL << INTERCEPT_INTR) |
867 (1ULL << INTERCEPT_NMI) |
868 (1ULL << INTERCEPT_SMI) |
869 (1ULL << INTERCEPT_SELECTIVE_CR0) |
870 (1ULL << INTERCEPT_CPUID) |
871 (1ULL << INTERCEPT_INVD) |
872 (1ULL << INTERCEPT_HLT) |
873 (1ULL << INTERCEPT_INVLPG) |
874 (1ULL << INTERCEPT_INVLPGA) |
875 (1ULL << INTERCEPT_IOIO_PROT) |
876 (1ULL << INTERCEPT_MSR_PROT) |
877 (1ULL << INTERCEPT_TASK_SWITCH) |
878 (1ULL << INTERCEPT_SHUTDOWN) |
879 (1ULL << INTERCEPT_VMRUN) |
880 (1ULL << INTERCEPT_VMMCALL) |
881 (1ULL << INTERCEPT_VMLOAD) |
882 (1ULL << INTERCEPT_VMSAVE) |
883 (1ULL << INTERCEPT_STGI) |
884 (1ULL << INTERCEPT_CLGI) |
885 (1ULL << INTERCEPT_SKINIT) |
886 (1ULL << INTERCEPT_WBINVD) |
887 (1ULL << INTERCEPT_MONITOR) |
888 (1ULL << INTERCEPT_MWAIT);
889
890 control->iopm_base_pa = iopm_base;
891 control->msrpm_base_pa = __pa(svm->msrpm);
892 control->int_ctl = V_INTR_MASKING_MASK;
893
894 init_seg(&save->es);
895 init_seg(&save->ss);
896 init_seg(&save->ds);
897 init_seg(&save->fs);
898 init_seg(&save->gs);
899
900 save->cs.selector = 0xf000;
901 /* Executable/Readable Code Segment */
902 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
903 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
904 save->cs.limit = 0xffff;
905 /*
906 * cs.base should really be 0xffff0000, but vmx can't handle that, so
907 * be consistent with it.
908 *
909 * Replace when we have real mode working for vmx.
910 */
911 save->cs.base = 0xf0000;
912
913 save->gdtr.limit = 0xffff;
914 save->idtr.limit = 0xffff;
915
916 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
917 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
918
919 svm_set_efer(&svm->vcpu, 0);
920 save->dr6 = 0xffff0ff0;
921 save->dr7 = 0x400;
922 save->rflags = 2;
923 save->rip = 0x0000fff0;
924 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
925
926 /*
927 * This is the guest-visible cr0 value.
928 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
929 */
930 svm->vcpu.arch.cr0 = 0;
931 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
932
933 save->cr4 = X86_CR4_PAE;
934 /* rdx = ?? */
935
936 if (npt_enabled) {
937 /* Setup VMCB for Nested Paging */
938 control->nested_ctl = 1;
939 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
940 (1ULL << INTERCEPT_INVLPG));
941 clr_exception_intercept(svm, PF_VECTOR);
942 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
943 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
944 save->g_pat = 0x0007040600070406ULL;
945 save->cr3 = 0;
946 save->cr4 = 0;
947 }
948 force_new_asid(&svm->vcpu);
949
950 svm->nested.vmcb = 0;
951 svm->vcpu.arch.hflags = 0;
952
953 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
954 control->pause_filter_count = 3000;
955 control->intercept |= (1ULL << INTERCEPT_PAUSE);
956 }
957
958 enable_gif(svm);
959 }
960
961 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
962 {
963 struct vcpu_svm *svm = to_svm(vcpu);
964
965 init_vmcb(svm);
966
967 if (!kvm_vcpu_is_bsp(vcpu)) {
968 kvm_rip_write(vcpu, 0);
969 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
970 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
971 }
972 vcpu->arch.regs_avail = ~0;
973 vcpu->arch.regs_dirty = ~0;
974
975 return 0;
976 }
977
978 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
979 {
980 struct vcpu_svm *svm;
981 struct page *page;
982 struct page *msrpm_pages;
983 struct page *hsave_page;
984 struct page *nested_msrpm_pages;
985 int err;
986
987 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
988 if (!svm) {
989 err = -ENOMEM;
990 goto out;
991 }
992
993 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
994 if (err)
995 goto free_svm;
996
997 err = -ENOMEM;
998 page = alloc_page(GFP_KERNEL);
999 if (!page)
1000 goto uninit;
1001
1002 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1003 if (!msrpm_pages)
1004 goto free_page1;
1005
1006 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1007 if (!nested_msrpm_pages)
1008 goto free_page2;
1009
1010 hsave_page = alloc_page(GFP_KERNEL);
1011 if (!hsave_page)
1012 goto free_page3;
1013
1014 svm->nested.hsave = page_address(hsave_page);
1015
1016 svm->msrpm = page_address(msrpm_pages);
1017 svm_vcpu_init_msrpm(svm->msrpm);
1018
1019 svm->nested.msrpm = page_address(nested_msrpm_pages);
1020 svm_vcpu_init_msrpm(svm->nested.msrpm);
1021
1022 svm->vmcb = page_address(page);
1023 clear_page(svm->vmcb);
1024 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1025 svm->asid_generation = 0;
1026 init_vmcb(svm);
1027 kvm_write_tsc(&svm->vcpu, 0);
1028
1029 err = fx_init(&svm->vcpu);
1030 if (err)
1031 goto free_page4;
1032
1033 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1034 if (kvm_vcpu_is_bsp(&svm->vcpu))
1035 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1036
1037 return &svm->vcpu;
1038
1039 free_page4:
1040 __free_page(hsave_page);
1041 free_page3:
1042 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1043 free_page2:
1044 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1045 free_page1:
1046 __free_page(page);
1047 uninit:
1048 kvm_vcpu_uninit(&svm->vcpu);
1049 free_svm:
1050 kmem_cache_free(kvm_vcpu_cache, svm);
1051 out:
1052 return ERR_PTR(err);
1053 }
1054
1055 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1056 {
1057 struct vcpu_svm *svm = to_svm(vcpu);
1058
1059 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1060 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1061 __free_page(virt_to_page(svm->nested.hsave));
1062 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1063 kvm_vcpu_uninit(vcpu);
1064 kmem_cache_free(kvm_vcpu_cache, svm);
1065 }
1066
1067 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1068 {
1069 struct vcpu_svm *svm = to_svm(vcpu);
1070 int i;
1071
1072 if (unlikely(cpu != vcpu->cpu)) {
1073 svm->asid_generation = 0;
1074 }
1075
1076 #ifdef CONFIG_X86_64
1077 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1078 #endif
1079 savesegment(fs, svm->host.fs);
1080 savesegment(gs, svm->host.gs);
1081 svm->host.ldt = kvm_read_ldt();
1082
1083 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1084 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1085 }
1086
1087 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1088 {
1089 struct vcpu_svm *svm = to_svm(vcpu);
1090 int i;
1091
1092 ++vcpu->stat.host_state_reload;
1093 kvm_load_ldt(svm->host.ldt);
1094 #ifdef CONFIG_X86_64
1095 loadsegment(fs, svm->host.fs);
1096 load_gs_index(svm->host.gs);
1097 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1098 #else
1099 loadsegment(gs, svm->host.gs);
1100 #endif
1101 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1102 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1103 }
1104
1105 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1106 {
1107 return to_svm(vcpu)->vmcb->save.rflags;
1108 }
1109
1110 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1111 {
1112 to_svm(vcpu)->vmcb->save.rflags = rflags;
1113 }
1114
1115 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1116 {
1117 switch (reg) {
1118 case VCPU_EXREG_PDPTR:
1119 BUG_ON(!npt_enabled);
1120 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1121 break;
1122 default:
1123 BUG();
1124 }
1125 }
1126
1127 static void svm_set_vintr(struct vcpu_svm *svm)
1128 {
1129 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1130 }
1131
1132 static void svm_clear_vintr(struct vcpu_svm *svm)
1133 {
1134 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1135 }
1136
1137 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1138 {
1139 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1140
1141 switch (seg) {
1142 case VCPU_SREG_CS: return &save->cs;
1143 case VCPU_SREG_DS: return &save->ds;
1144 case VCPU_SREG_ES: return &save->es;
1145 case VCPU_SREG_FS: return &save->fs;
1146 case VCPU_SREG_GS: return &save->gs;
1147 case VCPU_SREG_SS: return &save->ss;
1148 case VCPU_SREG_TR: return &save->tr;
1149 case VCPU_SREG_LDTR: return &save->ldtr;
1150 }
1151 BUG();
1152 return NULL;
1153 }
1154
1155 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1156 {
1157 struct vmcb_seg *s = svm_seg(vcpu, seg);
1158
1159 return s->base;
1160 }
1161
1162 static void svm_get_segment(struct kvm_vcpu *vcpu,
1163 struct kvm_segment *var, int seg)
1164 {
1165 struct vmcb_seg *s = svm_seg(vcpu, seg);
1166
1167 var->base = s->base;
1168 var->limit = s->limit;
1169 var->selector = s->selector;
1170 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1171 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1172 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1173 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1174 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1175 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1176 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1177 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1178
1179 /*
1180 * AMD's VMCB does not have an explicit unusable field, so emulate it
1181 * for cross vendor migration purposes by "not present"
1182 */
1183 var->unusable = !var->present || (var->type == 0);
1184
1185 switch (seg) {
1186 case VCPU_SREG_CS:
1187 /*
1188 * SVM always stores 0 for the 'G' bit in the CS selector in
1189 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1190 * Intel's VMENTRY has a check on the 'G' bit.
1191 */
1192 var->g = s->limit > 0xfffff;
1193 break;
1194 case VCPU_SREG_TR:
1195 /*
1196 * Work around a bug where the busy flag in the tr selector
1197 * isn't exposed
1198 */
1199 var->type |= 0x2;
1200 break;
1201 case VCPU_SREG_DS:
1202 case VCPU_SREG_ES:
1203 case VCPU_SREG_FS:
1204 case VCPU_SREG_GS:
1205 /*
1206 * The accessed bit must always be set in the segment
1207 * descriptor cache, although it can be cleared in the
1208 * descriptor, the cached bit always remains at 1. Since
1209 * Intel has a check on this, set it here to support
1210 * cross-vendor migration.
1211 */
1212 if (!var->unusable)
1213 var->type |= 0x1;
1214 break;
1215 case VCPU_SREG_SS:
1216 /*
1217 * On AMD CPUs sometimes the DB bit in the segment
1218 * descriptor is left as 1, although the whole segment has
1219 * been made unusable. Clear it here to pass an Intel VMX
1220 * entry check when cross vendor migrating.
1221 */
1222 if (var->unusable)
1223 var->db = 0;
1224 break;
1225 }
1226 }
1227
1228 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1229 {
1230 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1231
1232 return save->cpl;
1233 }
1234
1235 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1236 {
1237 struct vcpu_svm *svm = to_svm(vcpu);
1238
1239 dt->size = svm->vmcb->save.idtr.limit;
1240 dt->address = svm->vmcb->save.idtr.base;
1241 }
1242
1243 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1244 {
1245 struct vcpu_svm *svm = to_svm(vcpu);
1246
1247 svm->vmcb->save.idtr.limit = dt->size;
1248 svm->vmcb->save.idtr.base = dt->address ;
1249 }
1250
1251 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1252 {
1253 struct vcpu_svm *svm = to_svm(vcpu);
1254
1255 dt->size = svm->vmcb->save.gdtr.limit;
1256 dt->address = svm->vmcb->save.gdtr.base;
1257 }
1258
1259 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1260 {
1261 struct vcpu_svm *svm = to_svm(vcpu);
1262
1263 svm->vmcb->save.gdtr.limit = dt->size;
1264 svm->vmcb->save.gdtr.base = dt->address ;
1265 }
1266
1267 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1268 {
1269 }
1270
1271 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1272 {
1273 }
1274
1275 static void update_cr0_intercept(struct vcpu_svm *svm)
1276 {
1277 ulong gcr0 = svm->vcpu.arch.cr0;
1278 u64 *hcr0 = &svm->vmcb->save.cr0;
1279
1280 if (!svm->vcpu.fpu_active)
1281 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1282 else
1283 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1284 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1285
1286
1287 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1288 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1289 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1290 } else {
1291 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1292 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1293 }
1294 }
1295
1296 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1297 {
1298 struct vcpu_svm *svm = to_svm(vcpu);
1299
1300 if (is_guest_mode(vcpu)) {
1301 /*
1302 * We are here because we run in nested mode, the host kvm
1303 * intercepts cr0 writes but the l1 hypervisor does not.
1304 * But the L1 hypervisor may intercept selective cr0 writes.
1305 * This needs to be checked here.
1306 */
1307 unsigned long old, new;
1308
1309 /* Remove bits that would trigger a real cr0 write intercept */
1310 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1311 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1312
1313 if (old == new) {
1314 /* cr0 write with ts and mp unchanged */
1315 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1316 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1317 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1318 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1319 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1320 return;
1321 }
1322 }
1323 }
1324
1325 #ifdef CONFIG_X86_64
1326 if (vcpu->arch.efer & EFER_LME) {
1327 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1328 vcpu->arch.efer |= EFER_LMA;
1329 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1330 }
1331
1332 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1333 vcpu->arch.efer &= ~EFER_LMA;
1334 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1335 }
1336 }
1337 #endif
1338 vcpu->arch.cr0 = cr0;
1339
1340 if (!npt_enabled)
1341 cr0 |= X86_CR0_PG | X86_CR0_WP;
1342
1343 if (!vcpu->fpu_active)
1344 cr0 |= X86_CR0_TS;
1345 /*
1346 * re-enable caching here because the QEMU bios
1347 * does not do it - this results in some delay at
1348 * reboot
1349 */
1350 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1351 svm->vmcb->save.cr0 = cr0;
1352 update_cr0_intercept(svm);
1353 }
1354
1355 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1356 {
1357 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1358 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1359
1360 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1361 force_new_asid(vcpu);
1362
1363 vcpu->arch.cr4 = cr4;
1364 if (!npt_enabled)
1365 cr4 |= X86_CR4_PAE;
1366 cr4 |= host_cr4_mce;
1367 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1368 }
1369
1370 static void svm_set_segment(struct kvm_vcpu *vcpu,
1371 struct kvm_segment *var, int seg)
1372 {
1373 struct vcpu_svm *svm = to_svm(vcpu);
1374 struct vmcb_seg *s = svm_seg(vcpu, seg);
1375
1376 s->base = var->base;
1377 s->limit = var->limit;
1378 s->selector = var->selector;
1379 if (var->unusable)
1380 s->attrib = 0;
1381 else {
1382 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1383 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1384 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1385 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1386 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1387 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1388 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1389 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1390 }
1391 if (seg == VCPU_SREG_CS)
1392 svm->vmcb->save.cpl
1393 = (svm->vmcb->save.cs.attrib
1394 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1395
1396 }
1397
1398 static void update_db_intercept(struct kvm_vcpu *vcpu)
1399 {
1400 struct vcpu_svm *svm = to_svm(vcpu);
1401
1402 clr_exception_intercept(svm, DB_VECTOR);
1403 clr_exception_intercept(svm, BP_VECTOR);
1404
1405 if (svm->nmi_singlestep)
1406 set_exception_intercept(svm, DB_VECTOR);
1407
1408 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1409 if (vcpu->guest_debug &
1410 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1411 set_exception_intercept(svm, DB_VECTOR);
1412 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1413 set_exception_intercept(svm, BP_VECTOR);
1414 } else
1415 vcpu->guest_debug = 0;
1416 }
1417
1418 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1419 {
1420 struct vcpu_svm *svm = to_svm(vcpu);
1421
1422 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1423 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1424 else
1425 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1426
1427 update_db_intercept(vcpu);
1428 }
1429
1430 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1431 {
1432 if (sd->next_asid > sd->max_asid) {
1433 ++sd->asid_generation;
1434 sd->next_asid = 1;
1435 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1436 }
1437
1438 svm->asid_generation = sd->asid_generation;
1439 svm->vmcb->control.asid = sd->next_asid++;
1440 }
1441
1442 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1443 {
1444 struct vcpu_svm *svm = to_svm(vcpu);
1445
1446 svm->vmcb->save.dr7 = value;
1447 }
1448
1449 static int pf_interception(struct vcpu_svm *svm)
1450 {
1451 u64 fault_address = svm->vmcb->control.exit_info_2;
1452 u32 error_code;
1453 int r = 1;
1454
1455 switch (svm->apf_reason) {
1456 default:
1457 error_code = svm->vmcb->control.exit_info_1;
1458
1459 trace_kvm_page_fault(fault_address, error_code);
1460 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1461 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1462 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1463 break;
1464 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1465 svm->apf_reason = 0;
1466 local_irq_disable();
1467 kvm_async_pf_task_wait(fault_address);
1468 local_irq_enable();
1469 break;
1470 case KVM_PV_REASON_PAGE_READY:
1471 svm->apf_reason = 0;
1472 local_irq_disable();
1473 kvm_async_pf_task_wake(fault_address);
1474 local_irq_enable();
1475 break;
1476 }
1477 return r;
1478 }
1479
1480 static int db_interception(struct vcpu_svm *svm)
1481 {
1482 struct kvm_run *kvm_run = svm->vcpu.run;
1483
1484 if (!(svm->vcpu.guest_debug &
1485 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1486 !svm->nmi_singlestep) {
1487 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1488 return 1;
1489 }
1490
1491 if (svm->nmi_singlestep) {
1492 svm->nmi_singlestep = false;
1493 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1494 svm->vmcb->save.rflags &=
1495 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1496 update_db_intercept(&svm->vcpu);
1497 }
1498
1499 if (svm->vcpu.guest_debug &
1500 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1501 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1502 kvm_run->debug.arch.pc =
1503 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1504 kvm_run->debug.arch.exception = DB_VECTOR;
1505 return 0;
1506 }
1507
1508 return 1;
1509 }
1510
1511 static int bp_interception(struct vcpu_svm *svm)
1512 {
1513 struct kvm_run *kvm_run = svm->vcpu.run;
1514
1515 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1516 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1517 kvm_run->debug.arch.exception = BP_VECTOR;
1518 return 0;
1519 }
1520
1521 static int ud_interception(struct vcpu_svm *svm)
1522 {
1523 int er;
1524
1525 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1526 if (er != EMULATE_DONE)
1527 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1528 return 1;
1529 }
1530
1531 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1532 {
1533 struct vcpu_svm *svm = to_svm(vcpu);
1534
1535 clr_exception_intercept(svm, NM_VECTOR);
1536
1537 svm->vcpu.fpu_active = 1;
1538 update_cr0_intercept(svm);
1539 }
1540
1541 static int nm_interception(struct vcpu_svm *svm)
1542 {
1543 svm_fpu_activate(&svm->vcpu);
1544 return 1;
1545 }
1546
1547 static bool is_erratum_383(void)
1548 {
1549 int err, i;
1550 u64 value;
1551
1552 if (!erratum_383_found)
1553 return false;
1554
1555 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1556 if (err)
1557 return false;
1558
1559 /* Bit 62 may or may not be set for this mce */
1560 value &= ~(1ULL << 62);
1561
1562 if (value != 0xb600000000010015ULL)
1563 return false;
1564
1565 /* Clear MCi_STATUS registers */
1566 for (i = 0; i < 6; ++i)
1567 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1568
1569 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1570 if (!err) {
1571 u32 low, high;
1572
1573 value &= ~(1ULL << 2);
1574 low = lower_32_bits(value);
1575 high = upper_32_bits(value);
1576
1577 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1578 }
1579
1580 /* Flush tlb to evict multi-match entries */
1581 __flush_tlb_all();
1582
1583 return true;
1584 }
1585
1586 static void svm_handle_mce(struct vcpu_svm *svm)
1587 {
1588 if (is_erratum_383()) {
1589 /*
1590 * Erratum 383 triggered. Guest state is corrupt so kill the
1591 * guest.
1592 */
1593 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1594
1595 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1596
1597 return;
1598 }
1599
1600 /*
1601 * On an #MC intercept the MCE handler is not called automatically in
1602 * the host. So do it by hand here.
1603 */
1604 asm volatile (
1605 "int $0x12\n");
1606 /* not sure if we ever come back to this point */
1607
1608 return;
1609 }
1610
1611 static int mc_interception(struct vcpu_svm *svm)
1612 {
1613 return 1;
1614 }
1615
1616 static int shutdown_interception(struct vcpu_svm *svm)
1617 {
1618 struct kvm_run *kvm_run = svm->vcpu.run;
1619
1620 /*
1621 * VMCB is undefined after a SHUTDOWN intercept
1622 * so reinitialize it.
1623 */
1624 clear_page(svm->vmcb);
1625 init_vmcb(svm);
1626
1627 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1628 return 0;
1629 }
1630
1631 static int io_interception(struct vcpu_svm *svm)
1632 {
1633 struct kvm_vcpu *vcpu = &svm->vcpu;
1634 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1635 int size, in, string;
1636 unsigned port;
1637
1638 ++svm->vcpu.stat.io_exits;
1639 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1640 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1641 if (string || in)
1642 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1643
1644 port = io_info >> 16;
1645 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1646 svm->next_rip = svm->vmcb->control.exit_info_2;
1647 skip_emulated_instruction(&svm->vcpu);
1648
1649 return kvm_fast_pio_out(vcpu, size, port);
1650 }
1651
1652 static int nmi_interception(struct vcpu_svm *svm)
1653 {
1654 return 1;
1655 }
1656
1657 static int intr_interception(struct vcpu_svm *svm)
1658 {
1659 ++svm->vcpu.stat.irq_exits;
1660 return 1;
1661 }
1662
1663 static int nop_on_interception(struct vcpu_svm *svm)
1664 {
1665 return 1;
1666 }
1667
1668 static int halt_interception(struct vcpu_svm *svm)
1669 {
1670 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1671 skip_emulated_instruction(&svm->vcpu);
1672 return kvm_emulate_halt(&svm->vcpu);
1673 }
1674
1675 static int vmmcall_interception(struct vcpu_svm *svm)
1676 {
1677 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1678 skip_emulated_instruction(&svm->vcpu);
1679 kvm_emulate_hypercall(&svm->vcpu);
1680 return 1;
1681 }
1682
1683 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1684 {
1685 struct vcpu_svm *svm = to_svm(vcpu);
1686
1687 return svm->nested.nested_cr3;
1688 }
1689
1690 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1691 unsigned long root)
1692 {
1693 struct vcpu_svm *svm = to_svm(vcpu);
1694
1695 svm->vmcb->control.nested_cr3 = root;
1696 force_new_asid(vcpu);
1697 }
1698
1699 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1700 struct x86_exception *fault)
1701 {
1702 struct vcpu_svm *svm = to_svm(vcpu);
1703
1704 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1705 svm->vmcb->control.exit_code_hi = 0;
1706 svm->vmcb->control.exit_info_1 = fault->error_code;
1707 svm->vmcb->control.exit_info_2 = fault->address;
1708
1709 nested_svm_vmexit(svm);
1710 }
1711
1712 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1713 {
1714 int r;
1715
1716 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1717
1718 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1719 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1720 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1721 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1722 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1723
1724 return r;
1725 }
1726
1727 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1728 {
1729 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1730 }
1731
1732 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1733 {
1734 if (!(svm->vcpu.arch.efer & EFER_SVME)
1735 || !is_paging(&svm->vcpu)) {
1736 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1737 return 1;
1738 }
1739
1740 if (svm->vmcb->save.cpl) {
1741 kvm_inject_gp(&svm->vcpu, 0);
1742 return 1;
1743 }
1744
1745 return 0;
1746 }
1747
1748 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1749 bool has_error_code, u32 error_code)
1750 {
1751 int vmexit;
1752
1753 if (!is_guest_mode(&svm->vcpu))
1754 return 0;
1755
1756 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1757 svm->vmcb->control.exit_code_hi = 0;
1758 svm->vmcb->control.exit_info_1 = error_code;
1759 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1760
1761 vmexit = nested_svm_intercept(svm);
1762 if (vmexit == NESTED_EXIT_DONE)
1763 svm->nested.exit_required = true;
1764
1765 return vmexit;
1766 }
1767
1768 /* This function returns true if it is save to enable the irq window */
1769 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1770 {
1771 if (!is_guest_mode(&svm->vcpu))
1772 return true;
1773
1774 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1775 return true;
1776
1777 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1778 return false;
1779
1780 /*
1781 * if vmexit was already requested (by intercepted exception
1782 * for instance) do not overwrite it with "external interrupt"
1783 * vmexit.
1784 */
1785 if (svm->nested.exit_required)
1786 return false;
1787
1788 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1789 svm->vmcb->control.exit_info_1 = 0;
1790 svm->vmcb->control.exit_info_2 = 0;
1791
1792 if (svm->nested.intercept & 1ULL) {
1793 /*
1794 * The #vmexit can't be emulated here directly because this
1795 * code path runs with irqs and preemtion disabled. A
1796 * #vmexit emulation might sleep. Only signal request for
1797 * the #vmexit here.
1798 */
1799 svm->nested.exit_required = true;
1800 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1801 return false;
1802 }
1803
1804 return true;
1805 }
1806
1807 /* This function returns true if it is save to enable the nmi window */
1808 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1809 {
1810 if (!is_guest_mode(&svm->vcpu))
1811 return true;
1812
1813 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1814 return true;
1815
1816 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1817 svm->nested.exit_required = true;
1818
1819 return false;
1820 }
1821
1822 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1823 {
1824 struct page *page;
1825
1826 might_sleep();
1827
1828 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1829 if (is_error_page(page))
1830 goto error;
1831
1832 *_page = page;
1833
1834 return kmap(page);
1835
1836 error:
1837 kvm_release_page_clean(page);
1838 kvm_inject_gp(&svm->vcpu, 0);
1839
1840 return NULL;
1841 }
1842
1843 static void nested_svm_unmap(struct page *page)
1844 {
1845 kunmap(page);
1846 kvm_release_page_dirty(page);
1847 }
1848
1849 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1850 {
1851 unsigned port;
1852 u8 val, bit;
1853 u64 gpa;
1854
1855 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1856 return NESTED_EXIT_HOST;
1857
1858 port = svm->vmcb->control.exit_info_1 >> 16;
1859 gpa = svm->nested.vmcb_iopm + (port / 8);
1860 bit = port % 8;
1861 val = 0;
1862
1863 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1864 val &= (1 << bit);
1865
1866 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1867 }
1868
1869 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1870 {
1871 u32 offset, msr, value;
1872 int write, mask;
1873
1874 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1875 return NESTED_EXIT_HOST;
1876
1877 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1878 offset = svm_msrpm_offset(msr);
1879 write = svm->vmcb->control.exit_info_1 & 1;
1880 mask = 1 << ((2 * (msr & 0xf)) + write);
1881
1882 if (offset == MSR_INVALID)
1883 return NESTED_EXIT_DONE;
1884
1885 /* Offset is in 32 bit units but need in 8 bit units */
1886 offset *= 4;
1887
1888 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1889 return NESTED_EXIT_DONE;
1890
1891 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1892 }
1893
1894 static int nested_svm_exit_special(struct vcpu_svm *svm)
1895 {
1896 u32 exit_code = svm->vmcb->control.exit_code;
1897
1898 switch (exit_code) {
1899 case SVM_EXIT_INTR:
1900 case SVM_EXIT_NMI:
1901 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1902 return NESTED_EXIT_HOST;
1903 case SVM_EXIT_NPF:
1904 /* For now we are always handling NPFs when using them */
1905 if (npt_enabled)
1906 return NESTED_EXIT_HOST;
1907 break;
1908 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1909 /* When we're shadowing, trap PFs, but not async PF */
1910 if (!npt_enabled && svm->apf_reason == 0)
1911 return NESTED_EXIT_HOST;
1912 break;
1913 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1914 nm_interception(svm);
1915 break;
1916 default:
1917 break;
1918 }
1919
1920 return NESTED_EXIT_CONTINUE;
1921 }
1922
1923 /*
1924 * If this function returns true, this #vmexit was already handled
1925 */
1926 static int nested_svm_intercept(struct vcpu_svm *svm)
1927 {
1928 u32 exit_code = svm->vmcb->control.exit_code;
1929 int vmexit = NESTED_EXIT_HOST;
1930
1931 switch (exit_code) {
1932 case SVM_EXIT_MSR:
1933 vmexit = nested_svm_exit_handled_msr(svm);
1934 break;
1935 case SVM_EXIT_IOIO:
1936 vmexit = nested_svm_intercept_ioio(svm);
1937 break;
1938 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1939 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1940 if (svm->nested.intercept_cr & bit)
1941 vmexit = NESTED_EXIT_DONE;
1942 break;
1943 }
1944 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
1945 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
1946 if (svm->nested.intercept_dr & bit)
1947 vmexit = NESTED_EXIT_DONE;
1948 break;
1949 }
1950 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1951 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1952 if (svm->nested.intercept_exceptions & excp_bits)
1953 vmexit = NESTED_EXIT_DONE;
1954 /* async page fault always cause vmexit */
1955 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1956 svm->apf_reason != 0)
1957 vmexit = NESTED_EXIT_DONE;
1958 break;
1959 }
1960 case SVM_EXIT_ERR: {
1961 vmexit = NESTED_EXIT_DONE;
1962 break;
1963 }
1964 default: {
1965 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1966 if (svm->nested.intercept & exit_bits)
1967 vmexit = NESTED_EXIT_DONE;
1968 }
1969 }
1970
1971 return vmexit;
1972 }
1973
1974 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1975 {
1976 int vmexit;
1977
1978 vmexit = nested_svm_intercept(svm);
1979
1980 if (vmexit == NESTED_EXIT_DONE)
1981 nested_svm_vmexit(svm);
1982
1983 return vmexit;
1984 }
1985
1986 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1987 {
1988 struct vmcb_control_area *dst = &dst_vmcb->control;
1989 struct vmcb_control_area *from = &from_vmcb->control;
1990
1991 dst->intercept_cr = from->intercept_cr;
1992 dst->intercept_dr = from->intercept_dr;
1993 dst->intercept_exceptions = from->intercept_exceptions;
1994 dst->intercept = from->intercept;
1995 dst->iopm_base_pa = from->iopm_base_pa;
1996 dst->msrpm_base_pa = from->msrpm_base_pa;
1997 dst->tsc_offset = from->tsc_offset;
1998 dst->asid = from->asid;
1999 dst->tlb_ctl = from->tlb_ctl;
2000 dst->int_ctl = from->int_ctl;
2001 dst->int_vector = from->int_vector;
2002 dst->int_state = from->int_state;
2003 dst->exit_code = from->exit_code;
2004 dst->exit_code_hi = from->exit_code_hi;
2005 dst->exit_info_1 = from->exit_info_1;
2006 dst->exit_info_2 = from->exit_info_2;
2007 dst->exit_int_info = from->exit_int_info;
2008 dst->exit_int_info_err = from->exit_int_info_err;
2009 dst->nested_ctl = from->nested_ctl;
2010 dst->event_inj = from->event_inj;
2011 dst->event_inj_err = from->event_inj_err;
2012 dst->nested_cr3 = from->nested_cr3;
2013 dst->lbr_ctl = from->lbr_ctl;
2014 }
2015
2016 static int nested_svm_vmexit(struct vcpu_svm *svm)
2017 {
2018 struct vmcb *nested_vmcb;
2019 struct vmcb *hsave = svm->nested.hsave;
2020 struct vmcb *vmcb = svm->vmcb;
2021 struct page *page;
2022
2023 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2024 vmcb->control.exit_info_1,
2025 vmcb->control.exit_info_2,
2026 vmcb->control.exit_int_info,
2027 vmcb->control.exit_int_info_err);
2028
2029 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2030 if (!nested_vmcb)
2031 return 1;
2032
2033 /* Exit Guest-Mode */
2034 leave_guest_mode(&svm->vcpu);
2035 svm->nested.vmcb = 0;
2036
2037 /* Give the current vmcb to the guest */
2038 disable_gif(svm);
2039
2040 nested_vmcb->save.es = vmcb->save.es;
2041 nested_vmcb->save.cs = vmcb->save.cs;
2042 nested_vmcb->save.ss = vmcb->save.ss;
2043 nested_vmcb->save.ds = vmcb->save.ds;
2044 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2045 nested_vmcb->save.idtr = vmcb->save.idtr;
2046 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2047 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2048 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2049 nested_vmcb->save.cr2 = vmcb->save.cr2;
2050 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2051 nested_vmcb->save.rflags = vmcb->save.rflags;
2052 nested_vmcb->save.rip = vmcb->save.rip;
2053 nested_vmcb->save.rsp = vmcb->save.rsp;
2054 nested_vmcb->save.rax = vmcb->save.rax;
2055 nested_vmcb->save.dr7 = vmcb->save.dr7;
2056 nested_vmcb->save.dr6 = vmcb->save.dr6;
2057 nested_vmcb->save.cpl = vmcb->save.cpl;
2058
2059 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2060 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2061 nested_vmcb->control.int_state = vmcb->control.int_state;
2062 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2063 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2064 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2065 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2066 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2067 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2068 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2069
2070 /*
2071 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2072 * to make sure that we do not lose injected events. So check event_inj
2073 * here and copy it to exit_int_info if it is valid.
2074 * Exit_int_info and event_inj can't be both valid because the case
2075 * below only happens on a VMRUN instruction intercept which has
2076 * no valid exit_int_info set.
2077 */
2078 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2079 struct vmcb_control_area *nc = &nested_vmcb->control;
2080
2081 nc->exit_int_info = vmcb->control.event_inj;
2082 nc->exit_int_info_err = vmcb->control.event_inj_err;
2083 }
2084
2085 nested_vmcb->control.tlb_ctl = 0;
2086 nested_vmcb->control.event_inj = 0;
2087 nested_vmcb->control.event_inj_err = 0;
2088
2089 /* We always set V_INTR_MASKING and remember the old value in hflags */
2090 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2091 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2092
2093 /* Restore the original control entries */
2094 copy_vmcb_control_area(vmcb, hsave);
2095
2096 kvm_clear_exception_queue(&svm->vcpu);
2097 kvm_clear_interrupt_queue(&svm->vcpu);
2098
2099 svm->nested.nested_cr3 = 0;
2100
2101 /* Restore selected save entries */
2102 svm->vmcb->save.es = hsave->save.es;
2103 svm->vmcb->save.cs = hsave->save.cs;
2104 svm->vmcb->save.ss = hsave->save.ss;
2105 svm->vmcb->save.ds = hsave->save.ds;
2106 svm->vmcb->save.gdtr = hsave->save.gdtr;
2107 svm->vmcb->save.idtr = hsave->save.idtr;
2108 svm->vmcb->save.rflags = hsave->save.rflags;
2109 svm_set_efer(&svm->vcpu, hsave->save.efer);
2110 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2111 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2112 if (npt_enabled) {
2113 svm->vmcb->save.cr3 = hsave->save.cr3;
2114 svm->vcpu.arch.cr3 = hsave->save.cr3;
2115 } else {
2116 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2117 }
2118 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2119 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2120 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2121 svm->vmcb->save.dr7 = 0;
2122 svm->vmcb->save.cpl = 0;
2123 svm->vmcb->control.exit_int_info = 0;
2124
2125 nested_svm_unmap(page);
2126
2127 nested_svm_uninit_mmu_context(&svm->vcpu);
2128 kvm_mmu_reset_context(&svm->vcpu);
2129 kvm_mmu_load(&svm->vcpu);
2130
2131 return 0;
2132 }
2133
2134 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2135 {
2136 /*
2137 * This function merges the msr permission bitmaps of kvm and the
2138 * nested vmcb. It is omptimized in that it only merges the parts where
2139 * the kvm msr permission bitmap may contain zero bits
2140 */
2141 int i;
2142
2143 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2144 return true;
2145
2146 for (i = 0; i < MSRPM_OFFSETS; i++) {
2147 u32 value, p;
2148 u64 offset;
2149
2150 if (msrpm_offsets[i] == 0xffffffff)
2151 break;
2152
2153 p = msrpm_offsets[i];
2154 offset = svm->nested.vmcb_msrpm + (p * 4);
2155
2156 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2157 return false;
2158
2159 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2160 }
2161
2162 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2163
2164 return true;
2165 }
2166
2167 static bool nested_vmcb_checks(struct vmcb *vmcb)
2168 {
2169 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2170 return false;
2171
2172 if (vmcb->control.asid == 0)
2173 return false;
2174
2175 if (vmcb->control.nested_ctl && !npt_enabled)
2176 return false;
2177
2178 return true;
2179 }
2180
2181 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2182 {
2183 struct vmcb *nested_vmcb;
2184 struct vmcb *hsave = svm->nested.hsave;
2185 struct vmcb *vmcb = svm->vmcb;
2186 struct page *page;
2187 u64 vmcb_gpa;
2188
2189 vmcb_gpa = svm->vmcb->save.rax;
2190
2191 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2192 if (!nested_vmcb)
2193 return false;
2194
2195 if (!nested_vmcb_checks(nested_vmcb)) {
2196 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2197 nested_vmcb->control.exit_code_hi = 0;
2198 nested_vmcb->control.exit_info_1 = 0;
2199 nested_vmcb->control.exit_info_2 = 0;
2200
2201 nested_svm_unmap(page);
2202
2203 return false;
2204 }
2205
2206 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2207 nested_vmcb->save.rip,
2208 nested_vmcb->control.int_ctl,
2209 nested_vmcb->control.event_inj,
2210 nested_vmcb->control.nested_ctl);
2211
2212 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2213 nested_vmcb->control.intercept_cr >> 16,
2214 nested_vmcb->control.intercept_exceptions,
2215 nested_vmcb->control.intercept);
2216
2217 /* Clear internal status */
2218 kvm_clear_exception_queue(&svm->vcpu);
2219 kvm_clear_interrupt_queue(&svm->vcpu);
2220
2221 /*
2222 * Save the old vmcb, so we don't need to pick what we save, but can
2223 * restore everything when a VMEXIT occurs
2224 */
2225 hsave->save.es = vmcb->save.es;
2226 hsave->save.cs = vmcb->save.cs;
2227 hsave->save.ss = vmcb->save.ss;
2228 hsave->save.ds = vmcb->save.ds;
2229 hsave->save.gdtr = vmcb->save.gdtr;
2230 hsave->save.idtr = vmcb->save.idtr;
2231 hsave->save.efer = svm->vcpu.arch.efer;
2232 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2233 hsave->save.cr4 = svm->vcpu.arch.cr4;
2234 hsave->save.rflags = vmcb->save.rflags;
2235 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2236 hsave->save.rsp = vmcb->save.rsp;
2237 hsave->save.rax = vmcb->save.rax;
2238 if (npt_enabled)
2239 hsave->save.cr3 = vmcb->save.cr3;
2240 else
2241 hsave->save.cr3 = svm->vcpu.arch.cr3;
2242
2243 copy_vmcb_control_area(hsave, vmcb);
2244
2245 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2246 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2247 else
2248 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2249
2250 if (nested_vmcb->control.nested_ctl) {
2251 kvm_mmu_unload(&svm->vcpu);
2252 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2253 nested_svm_init_mmu_context(&svm->vcpu);
2254 }
2255
2256 /* Load the nested guest state */
2257 svm->vmcb->save.es = nested_vmcb->save.es;
2258 svm->vmcb->save.cs = nested_vmcb->save.cs;
2259 svm->vmcb->save.ss = nested_vmcb->save.ss;
2260 svm->vmcb->save.ds = nested_vmcb->save.ds;
2261 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2262 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2263 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2264 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2265 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2266 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2267 if (npt_enabled) {
2268 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2269 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2270 } else
2271 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2272
2273 /* Guest paging mode is active - reset mmu */
2274 kvm_mmu_reset_context(&svm->vcpu);
2275
2276 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2277 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2278 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2279 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2280
2281 /* In case we don't even reach vcpu_run, the fields are not updated */
2282 svm->vmcb->save.rax = nested_vmcb->save.rax;
2283 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2284 svm->vmcb->save.rip = nested_vmcb->save.rip;
2285 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2286 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2287 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2288
2289 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2290 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2291
2292 /* cache intercepts */
2293 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2294 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2295 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2296 svm->nested.intercept = nested_vmcb->control.intercept;
2297
2298 force_new_asid(&svm->vcpu);
2299 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2300 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2301 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2302 else
2303 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2304
2305 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2306 /* We only want the cr8 intercept bits of the guest */
2307 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2308 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2309 }
2310
2311 /* We don't want to see VMMCALLs from a nested guest */
2312 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2313
2314 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2315 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2316 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2317 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2318 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2319 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2320
2321 nested_svm_unmap(page);
2322
2323 /* Enter Guest-Mode */
2324 enter_guest_mode(&svm->vcpu);
2325
2326 /*
2327 * Merge guest and host intercepts - must be called with vcpu in
2328 * guest-mode to take affect here
2329 */
2330 recalc_intercepts(svm);
2331
2332 svm->nested.vmcb = vmcb_gpa;
2333
2334 enable_gif(svm);
2335
2336 return true;
2337 }
2338
2339 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2340 {
2341 to_vmcb->save.fs = from_vmcb->save.fs;
2342 to_vmcb->save.gs = from_vmcb->save.gs;
2343 to_vmcb->save.tr = from_vmcb->save.tr;
2344 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2345 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2346 to_vmcb->save.star = from_vmcb->save.star;
2347 to_vmcb->save.lstar = from_vmcb->save.lstar;
2348 to_vmcb->save.cstar = from_vmcb->save.cstar;
2349 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2350 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2351 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2352 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2353 }
2354
2355 static int vmload_interception(struct vcpu_svm *svm)
2356 {
2357 struct vmcb *nested_vmcb;
2358 struct page *page;
2359
2360 if (nested_svm_check_permissions(svm))
2361 return 1;
2362
2363 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2364 skip_emulated_instruction(&svm->vcpu);
2365
2366 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2367 if (!nested_vmcb)
2368 return 1;
2369
2370 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2371 nested_svm_unmap(page);
2372
2373 return 1;
2374 }
2375
2376 static int vmsave_interception(struct vcpu_svm *svm)
2377 {
2378 struct vmcb *nested_vmcb;
2379 struct page *page;
2380
2381 if (nested_svm_check_permissions(svm))
2382 return 1;
2383
2384 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2385 skip_emulated_instruction(&svm->vcpu);
2386
2387 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2388 if (!nested_vmcb)
2389 return 1;
2390
2391 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2392 nested_svm_unmap(page);
2393
2394 return 1;
2395 }
2396
2397 static int vmrun_interception(struct vcpu_svm *svm)
2398 {
2399 if (nested_svm_check_permissions(svm))
2400 return 1;
2401
2402 /* Save rip after vmrun instruction */
2403 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2404
2405 if (!nested_svm_vmrun(svm))
2406 return 1;
2407
2408 if (!nested_svm_vmrun_msrpm(svm))
2409 goto failed;
2410
2411 return 1;
2412
2413 failed:
2414
2415 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2416 svm->vmcb->control.exit_code_hi = 0;
2417 svm->vmcb->control.exit_info_1 = 0;
2418 svm->vmcb->control.exit_info_2 = 0;
2419
2420 nested_svm_vmexit(svm);
2421
2422 return 1;
2423 }
2424
2425 static int stgi_interception(struct vcpu_svm *svm)
2426 {
2427 if (nested_svm_check_permissions(svm))
2428 return 1;
2429
2430 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2431 skip_emulated_instruction(&svm->vcpu);
2432 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2433
2434 enable_gif(svm);
2435
2436 return 1;
2437 }
2438
2439 static int clgi_interception(struct vcpu_svm *svm)
2440 {
2441 if (nested_svm_check_permissions(svm))
2442 return 1;
2443
2444 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2445 skip_emulated_instruction(&svm->vcpu);
2446
2447 disable_gif(svm);
2448
2449 /* After a CLGI no interrupts should come */
2450 svm_clear_vintr(svm);
2451 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2452
2453 return 1;
2454 }
2455
2456 static int invlpga_interception(struct vcpu_svm *svm)
2457 {
2458 struct kvm_vcpu *vcpu = &svm->vcpu;
2459
2460 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2461 vcpu->arch.regs[VCPU_REGS_RAX]);
2462
2463 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2464 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2465
2466 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2467 skip_emulated_instruction(&svm->vcpu);
2468 return 1;
2469 }
2470
2471 static int skinit_interception(struct vcpu_svm *svm)
2472 {
2473 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2474
2475 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2476 return 1;
2477 }
2478
2479 static int invalid_op_interception(struct vcpu_svm *svm)
2480 {
2481 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2482 return 1;
2483 }
2484
2485 static int task_switch_interception(struct vcpu_svm *svm)
2486 {
2487 u16 tss_selector;
2488 int reason;
2489 int int_type = svm->vmcb->control.exit_int_info &
2490 SVM_EXITINTINFO_TYPE_MASK;
2491 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2492 uint32_t type =
2493 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2494 uint32_t idt_v =
2495 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2496 bool has_error_code = false;
2497 u32 error_code = 0;
2498
2499 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2500
2501 if (svm->vmcb->control.exit_info_2 &
2502 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2503 reason = TASK_SWITCH_IRET;
2504 else if (svm->vmcb->control.exit_info_2 &
2505 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2506 reason = TASK_SWITCH_JMP;
2507 else if (idt_v)
2508 reason = TASK_SWITCH_GATE;
2509 else
2510 reason = TASK_SWITCH_CALL;
2511
2512 if (reason == TASK_SWITCH_GATE) {
2513 switch (type) {
2514 case SVM_EXITINTINFO_TYPE_NMI:
2515 svm->vcpu.arch.nmi_injected = false;
2516 break;
2517 case SVM_EXITINTINFO_TYPE_EXEPT:
2518 if (svm->vmcb->control.exit_info_2 &
2519 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2520 has_error_code = true;
2521 error_code =
2522 (u32)svm->vmcb->control.exit_info_2;
2523 }
2524 kvm_clear_exception_queue(&svm->vcpu);
2525 break;
2526 case SVM_EXITINTINFO_TYPE_INTR:
2527 kvm_clear_interrupt_queue(&svm->vcpu);
2528 break;
2529 default:
2530 break;
2531 }
2532 }
2533
2534 if (reason != TASK_SWITCH_GATE ||
2535 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2536 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2537 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2538 skip_emulated_instruction(&svm->vcpu);
2539
2540 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2541 has_error_code, error_code) == EMULATE_FAIL) {
2542 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2543 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2544 svm->vcpu.run->internal.ndata = 0;
2545 return 0;
2546 }
2547 return 1;
2548 }
2549
2550 static int cpuid_interception(struct vcpu_svm *svm)
2551 {
2552 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2553 kvm_emulate_cpuid(&svm->vcpu);
2554 return 1;
2555 }
2556
2557 static int iret_interception(struct vcpu_svm *svm)
2558 {
2559 ++svm->vcpu.stat.nmi_window_exits;
2560 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2561 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2562 return 1;
2563 }
2564
2565 static int invlpg_interception(struct vcpu_svm *svm)
2566 {
2567 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2568 }
2569
2570 static int emulate_on_interception(struct vcpu_svm *svm)
2571 {
2572 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2573 }
2574
2575 static int cr0_write_interception(struct vcpu_svm *svm)
2576 {
2577 struct kvm_vcpu *vcpu = &svm->vcpu;
2578 int r;
2579
2580 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2581
2582 if (svm->nested.vmexit_rip) {
2583 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2584 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2585 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2586 svm->nested.vmexit_rip = 0;
2587 }
2588
2589 return r == EMULATE_DONE;
2590 }
2591
2592 static int cr8_write_interception(struct vcpu_svm *svm)
2593 {
2594 struct kvm_run *kvm_run = svm->vcpu.run;
2595
2596 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2597 /* instruction emulation calls kvm_set_cr8() */
2598 emulate_instruction(&svm->vcpu, 0, 0, 0);
2599 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2600 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2601 return 1;
2602 }
2603 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2604 return 1;
2605 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2606 return 0;
2607 }
2608
2609 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2610 {
2611 struct vcpu_svm *svm = to_svm(vcpu);
2612
2613 switch (ecx) {
2614 case MSR_IA32_TSC: {
2615 u64 tsc_offset;
2616
2617 if (is_guest_mode(vcpu))
2618 tsc_offset = svm->nested.hsave->control.tsc_offset;
2619 else
2620 tsc_offset = svm->vmcb->control.tsc_offset;
2621
2622 *data = tsc_offset + native_read_tsc();
2623 break;
2624 }
2625 case MSR_STAR:
2626 *data = svm->vmcb->save.star;
2627 break;
2628 #ifdef CONFIG_X86_64
2629 case MSR_LSTAR:
2630 *data = svm->vmcb->save.lstar;
2631 break;
2632 case MSR_CSTAR:
2633 *data = svm->vmcb->save.cstar;
2634 break;
2635 case MSR_KERNEL_GS_BASE:
2636 *data = svm->vmcb->save.kernel_gs_base;
2637 break;
2638 case MSR_SYSCALL_MASK:
2639 *data = svm->vmcb->save.sfmask;
2640 break;
2641 #endif
2642 case MSR_IA32_SYSENTER_CS:
2643 *data = svm->vmcb->save.sysenter_cs;
2644 break;
2645 case MSR_IA32_SYSENTER_EIP:
2646 *data = svm->sysenter_eip;
2647 break;
2648 case MSR_IA32_SYSENTER_ESP:
2649 *data = svm->sysenter_esp;
2650 break;
2651 /*
2652 * Nobody will change the following 5 values in the VMCB so we can
2653 * safely return them on rdmsr. They will always be 0 until LBRV is
2654 * implemented.
2655 */
2656 case MSR_IA32_DEBUGCTLMSR:
2657 *data = svm->vmcb->save.dbgctl;
2658 break;
2659 case MSR_IA32_LASTBRANCHFROMIP:
2660 *data = svm->vmcb->save.br_from;
2661 break;
2662 case MSR_IA32_LASTBRANCHTOIP:
2663 *data = svm->vmcb->save.br_to;
2664 break;
2665 case MSR_IA32_LASTINTFROMIP:
2666 *data = svm->vmcb->save.last_excp_from;
2667 break;
2668 case MSR_IA32_LASTINTTOIP:
2669 *data = svm->vmcb->save.last_excp_to;
2670 break;
2671 case MSR_VM_HSAVE_PA:
2672 *data = svm->nested.hsave_msr;
2673 break;
2674 case MSR_VM_CR:
2675 *data = svm->nested.vm_cr_msr;
2676 break;
2677 case MSR_IA32_UCODE_REV:
2678 *data = 0x01000065;
2679 break;
2680 default:
2681 return kvm_get_msr_common(vcpu, ecx, data);
2682 }
2683 return 0;
2684 }
2685
2686 static int rdmsr_interception(struct vcpu_svm *svm)
2687 {
2688 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2689 u64 data;
2690
2691 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2692 trace_kvm_msr_read_ex(ecx);
2693 kvm_inject_gp(&svm->vcpu, 0);
2694 } else {
2695 trace_kvm_msr_read(ecx, data);
2696
2697 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2698 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2699 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2700 skip_emulated_instruction(&svm->vcpu);
2701 }
2702 return 1;
2703 }
2704
2705 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2706 {
2707 struct vcpu_svm *svm = to_svm(vcpu);
2708 int svm_dis, chg_mask;
2709
2710 if (data & ~SVM_VM_CR_VALID_MASK)
2711 return 1;
2712
2713 chg_mask = SVM_VM_CR_VALID_MASK;
2714
2715 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2716 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2717
2718 svm->nested.vm_cr_msr &= ~chg_mask;
2719 svm->nested.vm_cr_msr |= (data & chg_mask);
2720
2721 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2722
2723 /* check for svm_disable while efer.svme is set */
2724 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2725 return 1;
2726
2727 return 0;
2728 }
2729
2730 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2731 {
2732 struct vcpu_svm *svm = to_svm(vcpu);
2733
2734 switch (ecx) {
2735 case MSR_IA32_TSC:
2736 kvm_write_tsc(vcpu, data);
2737 break;
2738 case MSR_STAR:
2739 svm->vmcb->save.star = data;
2740 break;
2741 #ifdef CONFIG_X86_64
2742 case MSR_LSTAR:
2743 svm->vmcb->save.lstar = data;
2744 break;
2745 case MSR_CSTAR:
2746 svm->vmcb->save.cstar = data;
2747 break;
2748 case MSR_KERNEL_GS_BASE:
2749 svm->vmcb->save.kernel_gs_base = data;
2750 break;
2751 case MSR_SYSCALL_MASK:
2752 svm->vmcb->save.sfmask = data;
2753 break;
2754 #endif
2755 case MSR_IA32_SYSENTER_CS:
2756 svm->vmcb->save.sysenter_cs = data;
2757 break;
2758 case MSR_IA32_SYSENTER_EIP:
2759 svm->sysenter_eip = data;
2760 svm->vmcb->save.sysenter_eip = data;
2761 break;
2762 case MSR_IA32_SYSENTER_ESP:
2763 svm->sysenter_esp = data;
2764 svm->vmcb->save.sysenter_esp = data;
2765 break;
2766 case MSR_IA32_DEBUGCTLMSR:
2767 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2768 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2769 __func__, data);
2770 break;
2771 }
2772 if (data & DEBUGCTL_RESERVED_BITS)
2773 return 1;
2774
2775 svm->vmcb->save.dbgctl = data;
2776 if (data & (1ULL<<0))
2777 svm_enable_lbrv(svm);
2778 else
2779 svm_disable_lbrv(svm);
2780 break;
2781 case MSR_VM_HSAVE_PA:
2782 svm->nested.hsave_msr = data;
2783 break;
2784 case MSR_VM_CR:
2785 return svm_set_vm_cr(vcpu, data);
2786 case MSR_VM_IGNNE:
2787 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2788 break;
2789 default:
2790 return kvm_set_msr_common(vcpu, ecx, data);
2791 }
2792 return 0;
2793 }
2794
2795 static int wrmsr_interception(struct vcpu_svm *svm)
2796 {
2797 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2798 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2799 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2800
2801
2802 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2803 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2804 trace_kvm_msr_write_ex(ecx, data);
2805 kvm_inject_gp(&svm->vcpu, 0);
2806 } else {
2807 trace_kvm_msr_write(ecx, data);
2808 skip_emulated_instruction(&svm->vcpu);
2809 }
2810 return 1;
2811 }
2812
2813 static int msr_interception(struct vcpu_svm *svm)
2814 {
2815 if (svm->vmcb->control.exit_info_1)
2816 return wrmsr_interception(svm);
2817 else
2818 return rdmsr_interception(svm);
2819 }
2820
2821 static int interrupt_window_interception(struct vcpu_svm *svm)
2822 {
2823 struct kvm_run *kvm_run = svm->vcpu.run;
2824
2825 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2826 svm_clear_vintr(svm);
2827 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2828 /*
2829 * If the user space waits to inject interrupts, exit as soon as
2830 * possible
2831 */
2832 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2833 kvm_run->request_interrupt_window &&
2834 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2835 ++svm->vcpu.stat.irq_window_exits;
2836 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2837 return 0;
2838 }
2839
2840 return 1;
2841 }
2842
2843 static int pause_interception(struct vcpu_svm *svm)
2844 {
2845 kvm_vcpu_on_spin(&(svm->vcpu));
2846 return 1;
2847 }
2848
2849 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2850 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2851 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2852 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2853 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2854 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2855 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2856 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2857 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2858 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2859 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2860 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2861 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2862 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2863 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2864 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2865 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2866 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2867 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2868 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2869 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2870 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2871 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2872 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2873 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2874 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2875 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2876 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2877 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2878 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2879 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2880 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2881 [SVM_EXIT_INTR] = intr_interception,
2882 [SVM_EXIT_NMI] = nmi_interception,
2883 [SVM_EXIT_SMI] = nop_on_interception,
2884 [SVM_EXIT_INIT] = nop_on_interception,
2885 [SVM_EXIT_VINTR] = interrupt_window_interception,
2886 [SVM_EXIT_CPUID] = cpuid_interception,
2887 [SVM_EXIT_IRET] = iret_interception,
2888 [SVM_EXIT_INVD] = emulate_on_interception,
2889 [SVM_EXIT_PAUSE] = pause_interception,
2890 [SVM_EXIT_HLT] = halt_interception,
2891 [SVM_EXIT_INVLPG] = invlpg_interception,
2892 [SVM_EXIT_INVLPGA] = invlpga_interception,
2893 [SVM_EXIT_IOIO] = io_interception,
2894 [SVM_EXIT_MSR] = msr_interception,
2895 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2896 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2897 [SVM_EXIT_VMRUN] = vmrun_interception,
2898 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2899 [SVM_EXIT_VMLOAD] = vmload_interception,
2900 [SVM_EXIT_VMSAVE] = vmsave_interception,
2901 [SVM_EXIT_STGI] = stgi_interception,
2902 [SVM_EXIT_CLGI] = clgi_interception,
2903 [SVM_EXIT_SKINIT] = skinit_interception,
2904 [SVM_EXIT_WBINVD] = emulate_on_interception,
2905 [SVM_EXIT_MONITOR] = invalid_op_interception,
2906 [SVM_EXIT_MWAIT] = invalid_op_interception,
2907 [SVM_EXIT_NPF] = pf_interception,
2908 };
2909
2910 void dump_vmcb(struct kvm_vcpu *vcpu)
2911 {
2912 struct vcpu_svm *svm = to_svm(vcpu);
2913 struct vmcb_control_area *control = &svm->vmcb->control;
2914 struct vmcb_save_area *save = &svm->vmcb->save;
2915
2916 pr_err("VMCB Control Area:\n");
2917 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2918 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2919 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2920 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2921 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2922 pr_err("intercepts: %016llx\n", control->intercept);
2923 pr_err("pause filter count: %d\n", control->pause_filter_count);
2924 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2925 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2926 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2927 pr_err("asid: %d\n", control->asid);
2928 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2929 pr_err("int_ctl: %08x\n", control->int_ctl);
2930 pr_err("int_vector: %08x\n", control->int_vector);
2931 pr_err("int_state: %08x\n", control->int_state);
2932 pr_err("exit_code: %08x\n", control->exit_code);
2933 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2934 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2935 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2936 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2937 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2938 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2939 pr_err("event_inj: %08x\n", control->event_inj);
2940 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2941 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2942 pr_err("next_rip: %016llx\n", control->next_rip);
2943 pr_err("VMCB State Save Area:\n");
2944 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->es.selector, save->es.attrib,
2946 save->es.limit, save->es.base);
2947 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2948 save->cs.selector, save->cs.attrib,
2949 save->cs.limit, save->cs.base);
2950 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2951 save->ss.selector, save->ss.attrib,
2952 save->ss.limit, save->ss.base);
2953 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2954 save->ds.selector, save->ds.attrib,
2955 save->ds.limit, save->ds.base);
2956 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2957 save->fs.selector, save->fs.attrib,
2958 save->fs.limit, save->fs.base);
2959 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2960 save->gs.selector, save->gs.attrib,
2961 save->gs.limit, save->gs.base);
2962 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2963 save->gdtr.selector, save->gdtr.attrib,
2964 save->gdtr.limit, save->gdtr.base);
2965 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2966 save->ldtr.selector, save->ldtr.attrib,
2967 save->ldtr.limit, save->ldtr.base);
2968 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2969 save->idtr.selector, save->idtr.attrib,
2970 save->idtr.limit, save->idtr.base);
2971 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2972 save->tr.selector, save->tr.attrib,
2973 save->tr.limit, save->tr.base);
2974 pr_err("cpl: %d efer: %016llx\n",
2975 save->cpl, save->efer);
2976 pr_err("cr0: %016llx cr2: %016llx\n",
2977 save->cr0, save->cr2);
2978 pr_err("cr3: %016llx cr4: %016llx\n",
2979 save->cr3, save->cr4);
2980 pr_err("dr6: %016llx dr7: %016llx\n",
2981 save->dr6, save->dr7);
2982 pr_err("rip: %016llx rflags: %016llx\n",
2983 save->rip, save->rflags);
2984 pr_err("rsp: %016llx rax: %016llx\n",
2985 save->rsp, save->rax);
2986 pr_err("star: %016llx lstar: %016llx\n",
2987 save->star, save->lstar);
2988 pr_err("cstar: %016llx sfmask: %016llx\n",
2989 save->cstar, save->sfmask);
2990 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2991 save->kernel_gs_base, save->sysenter_cs);
2992 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2993 save->sysenter_esp, save->sysenter_eip);
2994 pr_err("gpat: %016llx dbgctl: %016llx\n",
2995 save->g_pat, save->dbgctl);
2996 pr_err("br_from: %016llx br_to: %016llx\n",
2997 save->br_from, save->br_to);
2998 pr_err("excp_from: %016llx excp_to: %016llx\n",
2999 save->last_excp_from, save->last_excp_to);
3000
3001 }
3002
3003 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3004 {
3005 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3006
3007 *info1 = control->exit_info_1;
3008 *info2 = control->exit_info_2;
3009 }
3010
3011 static int handle_exit(struct kvm_vcpu *vcpu)
3012 {
3013 struct vcpu_svm *svm = to_svm(vcpu);
3014 struct kvm_run *kvm_run = vcpu->run;
3015 u32 exit_code = svm->vmcb->control.exit_code;
3016
3017 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3018
3019 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3020 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3021 if (npt_enabled)
3022 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3023
3024 if (unlikely(svm->nested.exit_required)) {
3025 nested_svm_vmexit(svm);
3026 svm->nested.exit_required = false;
3027
3028 return 1;
3029 }
3030
3031 if (is_guest_mode(vcpu)) {
3032 int vmexit;
3033
3034 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3035 svm->vmcb->control.exit_info_1,
3036 svm->vmcb->control.exit_info_2,
3037 svm->vmcb->control.exit_int_info,
3038 svm->vmcb->control.exit_int_info_err);
3039
3040 vmexit = nested_svm_exit_special(svm);
3041
3042 if (vmexit == NESTED_EXIT_CONTINUE)
3043 vmexit = nested_svm_exit_handled(svm);
3044
3045 if (vmexit == NESTED_EXIT_DONE)
3046 return 1;
3047 }
3048
3049 svm_complete_interrupts(svm);
3050
3051 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3052 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3053 kvm_run->fail_entry.hardware_entry_failure_reason
3054 = svm->vmcb->control.exit_code;
3055 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3056 dump_vmcb(vcpu);
3057 return 0;
3058 }
3059
3060 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3061 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3062 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3063 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3064 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3065 "exit_code 0x%x\n",
3066 __func__, svm->vmcb->control.exit_int_info,
3067 exit_code);
3068
3069 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3070 || !svm_exit_handlers[exit_code]) {
3071 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3072 kvm_run->hw.hardware_exit_reason = exit_code;
3073 return 0;
3074 }
3075
3076 return svm_exit_handlers[exit_code](svm);
3077 }
3078
3079 static void reload_tss(struct kvm_vcpu *vcpu)
3080 {
3081 int cpu = raw_smp_processor_id();
3082
3083 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3084 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3085 load_TR_desc();
3086 }
3087
3088 static void pre_svm_run(struct vcpu_svm *svm)
3089 {
3090 int cpu = raw_smp_processor_id();
3091
3092 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3093
3094 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3095 /* FIXME: handle wraparound of asid_generation */
3096 if (svm->asid_generation != sd->asid_generation)
3097 new_asid(svm, sd);
3098 }
3099
3100 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3101 {
3102 struct vcpu_svm *svm = to_svm(vcpu);
3103
3104 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3105 vcpu->arch.hflags |= HF_NMI_MASK;
3106 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3107 ++vcpu->stat.nmi_injections;
3108 }
3109
3110 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3111 {
3112 struct vmcb_control_area *control;
3113
3114 control = &svm->vmcb->control;
3115 control->int_vector = irq;
3116 control->int_ctl &= ~V_INTR_PRIO_MASK;
3117 control->int_ctl |= V_IRQ_MASK |
3118 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3119 }
3120
3121 static void svm_set_irq(struct kvm_vcpu *vcpu)
3122 {
3123 struct vcpu_svm *svm = to_svm(vcpu);
3124
3125 BUG_ON(!(gif_set(svm)));
3126
3127 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3128 ++vcpu->stat.irq_injections;
3129
3130 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3131 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3132 }
3133
3134 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3135 {
3136 struct vcpu_svm *svm = to_svm(vcpu);
3137
3138 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3139 return;
3140
3141 if (irr == -1)
3142 return;
3143
3144 if (tpr >= irr)
3145 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3146 }
3147
3148 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3149 {
3150 struct vcpu_svm *svm = to_svm(vcpu);
3151 struct vmcb *vmcb = svm->vmcb;
3152 int ret;
3153 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3154 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3155 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3156
3157 return ret;
3158 }
3159
3160 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3161 {
3162 struct vcpu_svm *svm = to_svm(vcpu);
3163
3164 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3165 }
3166
3167 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3168 {
3169 struct vcpu_svm *svm = to_svm(vcpu);
3170
3171 if (masked) {
3172 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3173 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3174 } else {
3175 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3176 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3177 }
3178 }
3179
3180 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3181 {
3182 struct vcpu_svm *svm = to_svm(vcpu);
3183 struct vmcb *vmcb = svm->vmcb;
3184 int ret;
3185
3186 if (!gif_set(svm) ||
3187 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3188 return 0;
3189
3190 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3191
3192 if (is_guest_mode(vcpu))
3193 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3194
3195 return ret;
3196 }
3197
3198 static void enable_irq_window(struct kvm_vcpu *vcpu)
3199 {
3200 struct vcpu_svm *svm = to_svm(vcpu);
3201
3202 /*
3203 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3204 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3205 * get that intercept, this function will be called again though and
3206 * we'll get the vintr intercept.
3207 */
3208 if (gif_set(svm) && nested_svm_intr(svm)) {
3209 svm_set_vintr(svm);
3210 svm_inject_irq(svm, 0x0);
3211 }
3212 }
3213
3214 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3215 {
3216 struct vcpu_svm *svm = to_svm(vcpu);
3217
3218 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3219 == HF_NMI_MASK)
3220 return; /* IRET will cause a vm exit */
3221
3222 /*
3223 * Something prevents NMI from been injected. Single step over possible
3224 * problem (IRET or exception injection or interrupt shadow)
3225 */
3226 svm->nmi_singlestep = true;
3227 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3228 update_db_intercept(vcpu);
3229 }
3230
3231 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3232 {
3233 return 0;
3234 }
3235
3236 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3237 {
3238 force_new_asid(vcpu);
3239 }
3240
3241 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3242 {
3243 }
3244
3245 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3246 {
3247 struct vcpu_svm *svm = to_svm(vcpu);
3248
3249 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3250 return;
3251
3252 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3253 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3254 kvm_set_cr8(vcpu, cr8);
3255 }
3256 }
3257
3258 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3259 {
3260 struct vcpu_svm *svm = to_svm(vcpu);
3261 u64 cr8;
3262
3263 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3264 return;
3265
3266 cr8 = kvm_get_cr8(vcpu);
3267 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3268 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3269 }
3270
3271 static void svm_complete_interrupts(struct vcpu_svm *svm)
3272 {
3273 u8 vector;
3274 int type;
3275 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3276 unsigned int3_injected = svm->int3_injected;
3277
3278 svm->int3_injected = 0;
3279
3280 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3281 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3282 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3283 }
3284
3285 svm->vcpu.arch.nmi_injected = false;
3286 kvm_clear_exception_queue(&svm->vcpu);
3287 kvm_clear_interrupt_queue(&svm->vcpu);
3288
3289 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3290 return;
3291
3292 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3293
3294 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3295 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3296
3297 switch (type) {
3298 case SVM_EXITINTINFO_TYPE_NMI:
3299 svm->vcpu.arch.nmi_injected = true;
3300 break;
3301 case SVM_EXITINTINFO_TYPE_EXEPT:
3302 /*
3303 * In case of software exceptions, do not reinject the vector,
3304 * but re-execute the instruction instead. Rewind RIP first
3305 * if we emulated INT3 before.
3306 */
3307 if (kvm_exception_is_soft(vector)) {
3308 if (vector == BP_VECTOR && int3_injected &&
3309 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3310 kvm_rip_write(&svm->vcpu,
3311 kvm_rip_read(&svm->vcpu) -
3312 int3_injected);
3313 break;
3314 }
3315 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3316 u32 err = svm->vmcb->control.exit_int_info_err;
3317 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3318
3319 } else
3320 kvm_requeue_exception(&svm->vcpu, vector);
3321 break;
3322 case SVM_EXITINTINFO_TYPE_INTR:
3323 kvm_queue_interrupt(&svm->vcpu, vector, false);
3324 break;
3325 default:
3326 break;
3327 }
3328 }
3329
3330 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3331 {
3332 struct vcpu_svm *svm = to_svm(vcpu);
3333 struct vmcb_control_area *control = &svm->vmcb->control;
3334
3335 control->exit_int_info = control->event_inj;
3336 control->exit_int_info_err = control->event_inj_err;
3337 control->event_inj = 0;
3338 svm_complete_interrupts(svm);
3339 }
3340
3341 #ifdef CONFIG_X86_64
3342 #define R "r"
3343 #else
3344 #define R "e"
3345 #endif
3346
3347 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3348 {
3349 struct vcpu_svm *svm = to_svm(vcpu);
3350
3351 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3352 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3353 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3354
3355 /*
3356 * A vmexit emulation is required before the vcpu can be executed
3357 * again.
3358 */
3359 if (unlikely(svm->nested.exit_required))
3360 return;
3361
3362 pre_svm_run(svm);
3363
3364 sync_lapic_to_cr8(vcpu);
3365
3366 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3367
3368 clgi();
3369
3370 local_irq_enable();
3371
3372 asm volatile (
3373 "push %%"R"bp; \n\t"
3374 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3375 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3376 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3377 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3378 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3379 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3380 #ifdef CONFIG_X86_64
3381 "mov %c[r8](%[svm]), %%r8 \n\t"
3382 "mov %c[r9](%[svm]), %%r9 \n\t"
3383 "mov %c[r10](%[svm]), %%r10 \n\t"
3384 "mov %c[r11](%[svm]), %%r11 \n\t"
3385 "mov %c[r12](%[svm]), %%r12 \n\t"
3386 "mov %c[r13](%[svm]), %%r13 \n\t"
3387 "mov %c[r14](%[svm]), %%r14 \n\t"
3388 "mov %c[r15](%[svm]), %%r15 \n\t"
3389 #endif
3390
3391 /* Enter guest mode */
3392 "push %%"R"ax \n\t"
3393 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3394 __ex(SVM_VMLOAD) "\n\t"
3395 __ex(SVM_VMRUN) "\n\t"
3396 __ex(SVM_VMSAVE) "\n\t"
3397 "pop %%"R"ax \n\t"
3398
3399 /* Save guest registers, load host registers */
3400 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3401 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3402 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3403 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3404 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3405 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3406 #ifdef CONFIG_X86_64
3407 "mov %%r8, %c[r8](%[svm]) \n\t"
3408 "mov %%r9, %c[r9](%[svm]) \n\t"
3409 "mov %%r10, %c[r10](%[svm]) \n\t"
3410 "mov %%r11, %c[r11](%[svm]) \n\t"
3411 "mov %%r12, %c[r12](%[svm]) \n\t"
3412 "mov %%r13, %c[r13](%[svm]) \n\t"
3413 "mov %%r14, %c[r14](%[svm]) \n\t"
3414 "mov %%r15, %c[r15](%[svm]) \n\t"
3415 #endif
3416 "pop %%"R"bp"
3417 :
3418 : [svm]"a"(svm),
3419 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3420 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3421 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3422 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3423 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3424 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3425 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3426 #ifdef CONFIG_X86_64
3427 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3428 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3429 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3430 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3431 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3432 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3433 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3434 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3435 #endif
3436 : "cc", "memory"
3437 , R"bx", R"cx", R"dx", R"si", R"di"
3438 #ifdef CONFIG_X86_64
3439 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3440 #endif
3441 );
3442
3443 #ifdef CONFIG_X86_64
3444 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3445 #else
3446 loadsegment(fs, svm->host.fs);
3447 #endif
3448
3449 reload_tss(vcpu);
3450
3451 local_irq_disable();
3452
3453 stgi();
3454
3455 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3456 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3457 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3458 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3459
3460 sync_cr8_to_lapic(vcpu);
3461
3462 svm->next_rip = 0;
3463
3464 /* if exit due to PF check for async PF */
3465 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3466 svm->apf_reason = kvm_read_and_reset_pf_reason();
3467
3468 if (npt_enabled) {
3469 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3470 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3471 }
3472
3473 /*
3474 * We need to handle MC intercepts here before the vcpu has a chance to
3475 * change the physical cpu
3476 */
3477 if (unlikely(svm->vmcb->control.exit_code ==
3478 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3479 svm_handle_mce(svm);
3480 }
3481
3482 #undef R
3483
3484 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3485 {
3486 struct vcpu_svm *svm = to_svm(vcpu);
3487
3488 svm->vmcb->save.cr3 = root;
3489 force_new_asid(vcpu);
3490 }
3491
3492 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3493 {
3494 struct vcpu_svm *svm = to_svm(vcpu);
3495
3496 svm->vmcb->control.nested_cr3 = root;
3497
3498 /* Also sync guest cr3 here in case we live migrate */
3499 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3500
3501 force_new_asid(vcpu);
3502 }
3503
3504 static int is_disabled(void)
3505 {
3506 u64 vm_cr;
3507
3508 rdmsrl(MSR_VM_CR, vm_cr);
3509 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3510 return 1;
3511
3512 return 0;
3513 }
3514
3515 static void
3516 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3517 {
3518 /*
3519 * Patch in the VMMCALL instruction:
3520 */
3521 hypercall[0] = 0x0f;
3522 hypercall[1] = 0x01;
3523 hypercall[2] = 0xd9;
3524 }
3525
3526 static void svm_check_processor_compat(void *rtn)
3527 {
3528 *(int *)rtn = 0;
3529 }
3530
3531 static bool svm_cpu_has_accelerated_tpr(void)
3532 {
3533 return false;
3534 }
3535
3536 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3537 {
3538 return 0;
3539 }
3540
3541 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3542 {
3543 }
3544
3545 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3546 {
3547 switch (func) {
3548 case 0x00000001:
3549 /* Mask out xsave bit as long as it is not supported by SVM */
3550 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3551 break;
3552 case 0x80000001:
3553 if (nested)
3554 entry->ecx |= (1 << 2); /* Set SVM bit */
3555 break;
3556 case 0x8000000A:
3557 entry->eax = 1; /* SVM revision 1 */
3558 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3559 ASID emulation to nested SVM */
3560 entry->ecx = 0; /* Reserved */
3561 entry->edx = 0; /* Per default do not support any
3562 additional features */
3563
3564 /* Support next_rip if host supports it */
3565 if (boot_cpu_has(X86_FEATURE_NRIPS))
3566 entry->edx |= SVM_FEATURE_NRIP;
3567
3568 /* Support NPT for the guest if enabled */
3569 if (npt_enabled)
3570 entry->edx |= SVM_FEATURE_NPT;
3571
3572 break;
3573 }
3574 }
3575
3576 static const struct trace_print_flags svm_exit_reasons_str[] = {
3577 { SVM_EXIT_READ_CR0, "read_cr0" },
3578 { SVM_EXIT_READ_CR3, "read_cr3" },
3579 { SVM_EXIT_READ_CR4, "read_cr4" },
3580 { SVM_EXIT_READ_CR8, "read_cr8" },
3581 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3582 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3583 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3584 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3585 { SVM_EXIT_READ_DR0, "read_dr0" },
3586 { SVM_EXIT_READ_DR1, "read_dr1" },
3587 { SVM_EXIT_READ_DR2, "read_dr2" },
3588 { SVM_EXIT_READ_DR3, "read_dr3" },
3589 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3590 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3591 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3592 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3593 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3594 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3595 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3596 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3597 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3598 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3599 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3600 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3601 { SVM_EXIT_INTR, "interrupt" },
3602 { SVM_EXIT_NMI, "nmi" },
3603 { SVM_EXIT_SMI, "smi" },
3604 { SVM_EXIT_INIT, "init" },
3605 { SVM_EXIT_VINTR, "vintr" },
3606 { SVM_EXIT_CPUID, "cpuid" },
3607 { SVM_EXIT_INVD, "invd" },
3608 { SVM_EXIT_HLT, "hlt" },
3609 { SVM_EXIT_INVLPG, "invlpg" },
3610 { SVM_EXIT_INVLPGA, "invlpga" },
3611 { SVM_EXIT_IOIO, "io" },
3612 { SVM_EXIT_MSR, "msr" },
3613 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3614 { SVM_EXIT_SHUTDOWN, "shutdown" },
3615 { SVM_EXIT_VMRUN, "vmrun" },
3616 { SVM_EXIT_VMMCALL, "hypercall" },
3617 { SVM_EXIT_VMLOAD, "vmload" },
3618 { SVM_EXIT_VMSAVE, "vmsave" },
3619 { SVM_EXIT_STGI, "stgi" },
3620 { SVM_EXIT_CLGI, "clgi" },
3621 { SVM_EXIT_SKINIT, "skinit" },
3622 { SVM_EXIT_WBINVD, "wbinvd" },
3623 { SVM_EXIT_MONITOR, "monitor" },
3624 { SVM_EXIT_MWAIT, "mwait" },
3625 { SVM_EXIT_NPF, "npf" },
3626 { -1, NULL }
3627 };
3628
3629 static int svm_get_lpage_level(void)
3630 {
3631 return PT_PDPE_LEVEL;
3632 }
3633
3634 static bool svm_rdtscp_supported(void)
3635 {
3636 return false;
3637 }
3638
3639 static bool svm_has_wbinvd_exit(void)
3640 {
3641 return true;
3642 }
3643
3644 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3645 {
3646 struct vcpu_svm *svm = to_svm(vcpu);
3647
3648 set_exception_intercept(svm, NM_VECTOR);
3649 update_cr0_intercept(svm);
3650 }
3651
3652 static struct kvm_x86_ops svm_x86_ops = {
3653 .cpu_has_kvm_support = has_svm,
3654 .disabled_by_bios = is_disabled,
3655 .hardware_setup = svm_hardware_setup,
3656 .hardware_unsetup = svm_hardware_unsetup,
3657 .check_processor_compatibility = svm_check_processor_compat,
3658 .hardware_enable = svm_hardware_enable,
3659 .hardware_disable = svm_hardware_disable,
3660 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3661
3662 .vcpu_create = svm_create_vcpu,
3663 .vcpu_free = svm_free_vcpu,
3664 .vcpu_reset = svm_vcpu_reset,
3665
3666 .prepare_guest_switch = svm_prepare_guest_switch,
3667 .vcpu_load = svm_vcpu_load,
3668 .vcpu_put = svm_vcpu_put,
3669
3670 .set_guest_debug = svm_guest_debug,
3671 .get_msr = svm_get_msr,
3672 .set_msr = svm_set_msr,
3673 .get_segment_base = svm_get_segment_base,
3674 .get_segment = svm_get_segment,
3675 .set_segment = svm_set_segment,
3676 .get_cpl = svm_get_cpl,
3677 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3678 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3679 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3680 .set_cr0 = svm_set_cr0,
3681 .set_cr3 = svm_set_cr3,
3682 .set_cr4 = svm_set_cr4,
3683 .set_efer = svm_set_efer,
3684 .get_idt = svm_get_idt,
3685 .set_idt = svm_set_idt,
3686 .get_gdt = svm_get_gdt,
3687 .set_gdt = svm_set_gdt,
3688 .set_dr7 = svm_set_dr7,
3689 .cache_reg = svm_cache_reg,
3690 .get_rflags = svm_get_rflags,
3691 .set_rflags = svm_set_rflags,
3692 .fpu_activate = svm_fpu_activate,
3693 .fpu_deactivate = svm_fpu_deactivate,
3694
3695 .tlb_flush = svm_flush_tlb,
3696
3697 .run = svm_vcpu_run,
3698 .handle_exit = handle_exit,
3699 .skip_emulated_instruction = skip_emulated_instruction,
3700 .set_interrupt_shadow = svm_set_interrupt_shadow,
3701 .get_interrupt_shadow = svm_get_interrupt_shadow,
3702 .patch_hypercall = svm_patch_hypercall,
3703 .set_irq = svm_set_irq,
3704 .set_nmi = svm_inject_nmi,
3705 .queue_exception = svm_queue_exception,
3706 .cancel_injection = svm_cancel_injection,
3707 .interrupt_allowed = svm_interrupt_allowed,
3708 .nmi_allowed = svm_nmi_allowed,
3709 .get_nmi_mask = svm_get_nmi_mask,
3710 .set_nmi_mask = svm_set_nmi_mask,
3711 .enable_nmi_window = enable_nmi_window,
3712 .enable_irq_window = enable_irq_window,
3713 .update_cr8_intercept = update_cr8_intercept,
3714
3715 .set_tss_addr = svm_set_tss_addr,
3716 .get_tdp_level = get_npt_level,
3717 .get_mt_mask = svm_get_mt_mask,
3718
3719 .get_exit_info = svm_get_exit_info,
3720 .exit_reasons_str = svm_exit_reasons_str,
3721
3722 .get_lpage_level = svm_get_lpage_level,
3723
3724 .cpuid_update = svm_cpuid_update,
3725
3726 .rdtscp_supported = svm_rdtscp_supported,
3727
3728 .set_supported_cpuid = svm_set_supported_cpuid,
3729
3730 .has_wbinvd_exit = svm_has_wbinvd_exit,
3731
3732 .write_tsc_offset = svm_write_tsc_offset,
3733 .adjust_tsc_offset = svm_adjust_tsc_offset,
3734
3735 .set_tdp_cr3 = set_tdp_cr3,
3736 };
3737
3738 static int __init svm_init(void)
3739 {
3740 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3741 __alignof__(struct vcpu_svm), THIS_MODULE);
3742 }
3743
3744 static void __exit svm_exit(void)
3745 {
3746 kvm_exit();
3747 }
3748
3749 module_init(svm_init)
3750 module_exit(svm_exit)
Linux kernel - Deliverables
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