2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
41 #include <asm/virtext.h>
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
49 static const struct x86_cpu_id svm_cpu_id
[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
53 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
81 static bool erratum_383_found __read_mostly
;
83 static const u32 host_save_user_msrs
[] = {
85 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
88 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
101 /* These are the merged vectors */
104 /* gpa pointers to the real vectors */
108 /* A VMEXIT is required but not yet emulated */
111 /* cache for intercepts of the guest */
114 u32 intercept_exceptions
;
117 /* Nested Paging related state */
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
128 static uint64_t osvw_len
= 4, osvw_status
;
131 struct kvm_vcpu vcpu
;
133 unsigned long vmcb_pa
;
134 struct svm_cpu_data
*svm_data
;
135 uint64_t asid_generation
;
136 uint64_t sysenter_esp
;
137 uint64_t sysenter_eip
;
141 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
153 struct nested_state nested
;
157 unsigned int3_injected
;
158 unsigned long int3_rip
;
164 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
165 #define TSC_RATIO_DEFAULT 0x0100000000ULL
167 #define MSR_INVALID 0xffffffffU
169 static const struct svm_direct_access_msrs
{
170 u32 index
; /* Index of the MSR */
171 bool always
; /* True if intercept is always on */
172 } direct_access_msrs
[] = {
173 { .index
= MSR_STAR
, .always
= true },
174 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
176 { .index
= MSR_GS_BASE
, .always
= true },
177 { .index
= MSR_FS_BASE
, .always
= true },
178 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
179 { .index
= MSR_LSTAR
, .always
= true },
180 { .index
= MSR_CSTAR
, .always
= true },
181 { .index
= MSR_SYSCALL_MASK
, .always
= true },
183 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
184 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
185 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
186 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
187 { .index
= MSR_INVALID
, .always
= false },
190 /* enable NPT for AMD64 and X86 with PAE */
191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192 static bool npt_enabled
= true;
194 static bool npt_enabled
;
197 /* allow nested paging (virtualized MMU) for all guests */
198 static int npt
= true;
199 module_param(npt
, int, S_IRUGO
);
201 /* allow nested virtualization in KVM/SVM */
202 static int nested
= true;
203 module_param(nested
, int, S_IRUGO
);
205 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
206 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
208 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
209 static int nested_svm_intercept(struct vcpu_svm
*svm
);
210 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
211 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
212 bool has_error_code
, u32 error_code
);
213 static u64
__scale_tsc(u64 ratio
, u64 tsc
);
216 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
217 pause filter count */
218 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
219 VMCB_ASID
, /* ASID */
220 VMCB_INTR
, /* int_ctl, int_vector */
221 VMCB_NPT
, /* npt_en, nCR3, gPAT */
222 VMCB_CR
, /* CR0, CR3, CR4, EFER */
223 VMCB_DR
, /* DR6, DR7 */
224 VMCB_DT
, /* GDT, IDT */
225 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
226 VMCB_CR2
, /* CR2 only */
227 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
231 /* TPR and CR2 are always written before VMRUN */
232 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
234 static inline void mark_all_dirty(struct vmcb
*vmcb
)
236 vmcb
->control
.clean
= 0;
239 static inline void mark_all_clean(struct vmcb
*vmcb
)
241 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
242 & ~VMCB_ALWAYS_DIRTY_MASK
;
245 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
247 vmcb
->control
.clean
&= ~(1 << bit
);
250 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
252 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
255 static void recalc_intercepts(struct vcpu_svm
*svm
)
257 struct vmcb_control_area
*c
, *h
;
258 struct nested_state
*g
;
260 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
262 if (!is_guest_mode(&svm
->vcpu
))
265 c
= &svm
->vmcb
->control
;
266 h
= &svm
->nested
.hsave
->control
;
269 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
270 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
271 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
272 c
->intercept
= h
->intercept
| g
->intercept
;
275 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
277 if (is_guest_mode(&svm
->vcpu
))
278 return svm
->nested
.hsave
;
283 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
285 struct vmcb
*vmcb
= get_host_vmcb(svm
);
287 vmcb
->control
.intercept_cr
|= (1U << bit
);
289 recalc_intercepts(svm
);
292 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
294 struct vmcb
*vmcb
= get_host_vmcb(svm
);
296 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
298 recalc_intercepts(svm
);
301 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
303 struct vmcb
*vmcb
= get_host_vmcb(svm
);
305 return vmcb
->control
.intercept_cr
& (1U << bit
);
308 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
310 struct vmcb
*vmcb
= get_host_vmcb(svm
);
312 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
313 | (1 << INTERCEPT_DR1_READ
)
314 | (1 << INTERCEPT_DR2_READ
)
315 | (1 << INTERCEPT_DR3_READ
)
316 | (1 << INTERCEPT_DR4_READ
)
317 | (1 << INTERCEPT_DR5_READ
)
318 | (1 << INTERCEPT_DR6_READ
)
319 | (1 << INTERCEPT_DR7_READ
)
320 | (1 << INTERCEPT_DR0_WRITE
)
321 | (1 << INTERCEPT_DR1_WRITE
)
322 | (1 << INTERCEPT_DR2_WRITE
)
323 | (1 << INTERCEPT_DR3_WRITE
)
324 | (1 << INTERCEPT_DR4_WRITE
)
325 | (1 << INTERCEPT_DR5_WRITE
)
326 | (1 << INTERCEPT_DR6_WRITE
)
327 | (1 << INTERCEPT_DR7_WRITE
);
329 recalc_intercepts(svm
);
332 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
334 struct vmcb
*vmcb
= get_host_vmcb(svm
);
336 vmcb
->control
.intercept_dr
= 0;
338 recalc_intercepts(svm
);
341 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
343 struct vmcb
*vmcb
= get_host_vmcb(svm
);
345 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
347 recalc_intercepts(svm
);
350 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
352 struct vmcb
*vmcb
= get_host_vmcb(svm
);
354 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
356 recalc_intercepts(svm
);
359 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
361 struct vmcb
*vmcb
= get_host_vmcb(svm
);
363 vmcb
->control
.intercept
|= (1ULL << bit
);
365 recalc_intercepts(svm
);
368 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
370 struct vmcb
*vmcb
= get_host_vmcb(svm
);
372 vmcb
->control
.intercept
&= ~(1ULL << bit
);
374 recalc_intercepts(svm
);
377 static inline void enable_gif(struct vcpu_svm
*svm
)
379 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
382 static inline void disable_gif(struct vcpu_svm
*svm
)
384 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
387 static inline bool gif_set(struct vcpu_svm
*svm
)
389 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
392 static unsigned long iopm_base
;
394 struct kvm_ldttss_desc
{
397 unsigned base1
:8, type
:5, dpl
:2, p
:1;
398 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
401 } __attribute__((packed
));
403 struct svm_cpu_data
{
409 struct kvm_ldttss_desc
*tss_desc
;
411 struct page
*save_area
;
414 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
416 struct svm_init_data
{
421 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
423 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
424 #define MSRS_RANGE_SIZE 2048
425 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
427 static u32
svm_msrpm_offset(u32 msr
)
432 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
433 if (msr
< msrpm_ranges
[i
] ||
434 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
437 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
438 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
440 /* Now we have the u8 offset - but need the u32 offset */
444 /* MSR not in any range */
448 #define MAX_INST_SIZE 15
450 static inline void clgi(void)
452 asm volatile (__ex(SVM_CLGI
));
455 static inline void stgi(void)
457 asm volatile (__ex(SVM_STGI
));
460 static inline void invlpga(unsigned long addr
, u32 asid
)
462 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
465 static int get_npt_level(void)
468 return PT64_ROOT_LEVEL
;
470 return PT32E_ROOT_LEVEL
;
474 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
476 vcpu
->arch
.efer
= efer
;
477 if (!npt_enabled
&& !(efer
& EFER_LMA
))
480 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
481 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
484 static int is_external_interrupt(u32 info
)
486 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
487 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
490 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
492 struct vcpu_svm
*svm
= to_svm(vcpu
);
495 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
496 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
500 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
502 struct vcpu_svm
*svm
= to_svm(vcpu
);
505 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
507 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
511 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
513 struct vcpu_svm
*svm
= to_svm(vcpu
);
515 if (svm
->vmcb
->control
.next_rip
!= 0) {
516 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS
));
517 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
520 if (!svm
->next_rip
) {
521 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
523 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
526 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
527 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
528 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
530 kvm_rip_write(vcpu
, svm
->next_rip
);
531 svm_set_interrupt_shadow(vcpu
, 0);
534 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
535 bool has_error_code
, u32 error_code
,
538 struct vcpu_svm
*svm
= to_svm(vcpu
);
541 * If we are within a nested VM we'd better #VMEXIT and let the guest
542 * handle the exception
545 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
548 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
549 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
552 * For guest debugging where we have to reinject #BP if some
553 * INT3 is guest-owned:
554 * Emulate nRIP by moving RIP forward. Will fail if injection
555 * raises a fault that is not intercepted. Still better than
556 * failing in all cases.
558 skip_emulated_instruction(&svm
->vcpu
);
559 rip
= kvm_rip_read(&svm
->vcpu
);
560 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
561 svm
->int3_injected
= rip
- old_rip
;
564 svm
->vmcb
->control
.event_inj
= nr
566 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
567 | SVM_EVTINJ_TYPE_EXEPT
;
568 svm
->vmcb
->control
.event_inj_err
= error_code
;
571 static void svm_init_erratum_383(void)
577 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
580 /* Use _safe variants to not break nested virtualization */
581 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
587 low
= lower_32_bits(val
);
588 high
= upper_32_bits(val
);
590 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
592 erratum_383_found
= true;
595 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
598 * Guests should see errata 400 and 415 as fixed (assuming that
599 * HLT and IO instructions are intercepted).
601 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
602 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
605 * By increasing VCPU's osvw.length to 3 we are telling the guest that
606 * all osvw.status bits inside that length, including bit 0 (which is
607 * reserved for erratum 298), are valid. However, if host processor's
608 * osvw_len is 0 then osvw_status[0] carries no information. We need to
609 * be conservative here and therefore we tell the guest that erratum 298
610 * is present (because we really don't know).
612 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
613 vcpu
->arch
.osvw
.status
|= 1;
616 static int has_svm(void)
620 if (!cpu_has_svm(&msg
)) {
621 printk(KERN_INFO
"has_svm: %s\n", msg
);
628 static void svm_hardware_disable(void)
630 /* Make sure we clean up behind us */
631 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
632 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
636 amd_pmu_disable_virt();
639 static int svm_hardware_enable(void)
642 struct svm_cpu_data
*sd
;
644 struct desc_ptr gdt_descr
;
645 struct desc_struct
*gdt
;
646 int me
= raw_smp_processor_id();
648 rdmsrl(MSR_EFER
, efer
);
649 if (efer
& EFER_SVME
)
653 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
656 sd
= per_cpu(svm_data
, me
);
658 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
662 sd
->asid_generation
= 1;
663 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
664 sd
->next_asid
= sd
->max_asid
+ 1;
666 native_store_gdt(&gdt_descr
);
667 gdt
= (struct desc_struct
*)gdt_descr
.address
;
668 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
670 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
672 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
674 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
675 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
676 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
683 * Note that it is possible to have a system with mixed processor
684 * revisions and therefore different OSVW bits. If bits are not the same
685 * on different processors then choose the worst case (i.e. if erratum
686 * is present on one processor and not on another then assume that the
687 * erratum is present everywhere).
689 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
690 uint64_t len
, status
= 0;
693 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
695 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
699 osvw_status
= osvw_len
= 0;
703 osvw_status
|= status
;
704 osvw_status
&= (1ULL << osvw_len
) - 1;
707 osvw_status
= osvw_len
= 0;
709 svm_init_erratum_383();
711 amd_pmu_enable_virt();
716 static void svm_cpu_uninit(int cpu
)
718 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
723 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
724 __free_page(sd
->save_area
);
728 static int svm_cpu_init(int cpu
)
730 struct svm_cpu_data
*sd
;
733 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
737 sd
->save_area
= alloc_page(GFP_KERNEL
);
742 per_cpu(svm_data
, cpu
) = sd
;
752 static bool valid_msr_intercept(u32 index
)
756 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
757 if (direct_access_msrs
[i
].index
== index
)
763 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
766 u8 bit_read
, bit_write
;
771 * If this warning triggers extend the direct_access_msrs list at the
772 * beginning of the file
774 WARN_ON(!valid_msr_intercept(msr
));
776 offset
= svm_msrpm_offset(msr
);
777 bit_read
= 2 * (msr
& 0x0f);
778 bit_write
= 2 * (msr
& 0x0f) + 1;
781 BUG_ON(offset
== MSR_INVALID
);
783 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
784 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
789 static void svm_vcpu_init_msrpm(u32
*msrpm
)
793 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
795 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
796 if (!direct_access_msrs
[i
].always
)
799 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
803 static void add_msr_offset(u32 offset
)
807 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
809 /* Offset already in list? */
810 if (msrpm_offsets
[i
] == offset
)
813 /* Slot used by another offset? */
814 if (msrpm_offsets
[i
] != MSR_INVALID
)
817 /* Add offset to list */
818 msrpm_offsets
[i
] = offset
;
824 * If this BUG triggers the msrpm_offsets table has an overflow. Just
825 * increase MSRPM_OFFSETS in this case.
830 static void init_msrpm_offsets(void)
834 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
836 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
839 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
840 BUG_ON(offset
== MSR_INVALID
);
842 add_msr_offset(offset
);
846 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
848 u32
*msrpm
= svm
->msrpm
;
850 svm
->vmcb
->control
.lbr_ctl
= 1;
851 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
852 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
853 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
854 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
857 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
859 u32
*msrpm
= svm
->msrpm
;
861 svm
->vmcb
->control
.lbr_ctl
= 0;
862 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
863 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
864 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
865 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
868 #define MTRR_TYPE_UC_MINUS 7
869 #define MTRR2PROTVAL_INVALID 0xff
871 static u8 mtrr2protval
[8];
873 static u8
fallback_mtrr_type(int mtrr
)
876 * WT and WP aren't always available in the host PAT. Treat
877 * them as UC and UC- respectively. Everything else should be
882 case MTRR_TYPE_WRTHROUGH
:
883 return MTRR_TYPE_UNCACHABLE
;
884 case MTRR_TYPE_WRPROT
:
885 return MTRR_TYPE_UC_MINUS
;
891 static void build_mtrr2protval(void)
896 for (i
= 0; i
< 8; i
++)
897 mtrr2protval
[i
] = MTRR2PROTVAL_INVALID
;
899 /* Ignore the invalid MTRR types. */
904 * Use host PAT value to figure out the mapping from guest MTRR
905 * values to nested page table PAT/PCD/PWT values. We do not
906 * want to change the host PAT value every time we enter the
909 rdmsrl(MSR_IA32_CR_PAT
, pat
);
910 for (i
= 0; i
< 8; i
++) {
911 u8 mtrr
= pat
>> (8 * i
);
913 if (mtrr2protval
[mtrr
] == MTRR2PROTVAL_INVALID
)
914 mtrr2protval
[mtrr
] = __cm_idx2pte(i
);
917 for (i
= 0; i
< 8; i
++) {
918 if (mtrr2protval
[i
] == MTRR2PROTVAL_INVALID
) {
919 u8 fallback
= fallback_mtrr_type(i
);
920 mtrr2protval
[i
] = mtrr2protval
[fallback
];
921 BUG_ON(mtrr2protval
[i
] == MTRR2PROTVAL_INVALID
);
926 static __init
int svm_hardware_setup(void)
929 struct page
*iopm_pages
;
933 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
938 iopm_va
= page_address(iopm_pages
);
939 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
940 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
942 init_msrpm_offsets();
944 if (boot_cpu_has(X86_FEATURE_NX
))
945 kvm_enable_efer_bits(EFER_NX
);
947 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
948 kvm_enable_efer_bits(EFER_FFXSR
);
950 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
953 kvm_has_tsc_control
= true;
956 * Make sure the user can only configure tsc_khz values that
957 * fit into a signed integer.
958 * A min value is not calculated needed because it will always
959 * be 1 on all machines and a value of 0 is used to disable
960 * tsc-scaling for the vcpu.
962 max
= min(0x7fffffffULL
, __scale_tsc(tsc_khz
, TSC_RATIO_MAX
));
964 kvm_max_guest_tsc_khz
= max
;
968 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
969 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
972 for_each_possible_cpu(cpu
) {
973 r
= svm_cpu_init(cpu
);
978 if (!boot_cpu_has(X86_FEATURE_NPT
))
981 if (npt_enabled
&& !npt
) {
982 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
987 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
992 build_mtrr2protval();
996 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1001 static __exit
void svm_hardware_unsetup(void)
1005 for_each_possible_cpu(cpu
)
1006 svm_cpu_uninit(cpu
);
1008 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1012 static void init_seg(struct vmcb_seg
*seg
)
1015 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1016 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1017 seg
->limit
= 0xffff;
1021 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1024 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1025 seg
->limit
= 0xffff;
1029 static u64
__scale_tsc(u64 ratio
, u64 tsc
)
1031 u64 mult
, frac
, _tsc
;
1034 frac
= ratio
& ((1ULL << 32) - 1);
1038 _tsc
+= (tsc
>> 32) * frac
;
1039 _tsc
+= ((tsc
& ((1ULL << 32) - 1)) * frac
) >> 32;
1044 static u64
svm_scale_tsc(struct kvm_vcpu
*vcpu
, u64 tsc
)
1046 struct vcpu_svm
*svm
= to_svm(vcpu
);
1049 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
1050 _tsc
= __scale_tsc(svm
->tsc_ratio
, tsc
);
1055 static void svm_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1057 struct vcpu_svm
*svm
= to_svm(vcpu
);
1061 /* Guest TSC same frequency as host TSC? */
1063 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1067 /* TSC scaling supported? */
1068 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1069 if (user_tsc_khz
> tsc_khz
) {
1070 vcpu
->arch
.tsc_catchup
= 1;
1071 vcpu
->arch
.tsc_always_catchup
= 1;
1073 WARN(1, "user requested TSC rate below hardware speed\n");
1079 /* TSC scaling required - calculate ratio */
1081 do_div(ratio
, tsc_khz
);
1083 if (ratio
== 0 || ratio
& TSC_RATIO_RSVD
) {
1084 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1088 svm
->tsc_ratio
= ratio
;
1091 static u64
svm_read_tsc_offset(struct kvm_vcpu
*vcpu
)
1093 struct vcpu_svm
*svm
= to_svm(vcpu
);
1095 return svm
->vmcb
->control
.tsc_offset
;
1098 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1100 struct vcpu_svm
*svm
= to_svm(vcpu
);
1101 u64 g_tsc_offset
= 0;
1103 if (is_guest_mode(vcpu
)) {
1104 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1105 svm
->nested
.hsave
->control
.tsc_offset
;
1106 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1108 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1109 svm
->vmcb
->control
.tsc_offset
,
1112 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1114 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1117 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1119 struct vcpu_svm
*svm
= to_svm(vcpu
);
1122 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
1123 WARN_ON(adjustment
< 0);
1124 adjustment
= svm_scale_tsc(vcpu
, (u64
)adjustment
);
1127 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
1128 if (is_guest_mode(vcpu
))
1129 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
1131 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1132 svm
->vmcb
->control
.tsc_offset
- adjustment
,
1133 svm
->vmcb
->control
.tsc_offset
);
1135 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1138 static u64
svm_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1142 tsc
= svm_scale_tsc(vcpu
, rdtsc());
1144 return target_tsc
- tsc
;
1147 static void svm_set_guest_pat(struct vcpu_svm
*svm
, u64
*g_pat
)
1149 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1151 /* Unlike Intel, AMD takes the guest's CR0.CD into account.
1153 * AMD does not have IPAT. To emulate it for the case of guests
1154 * with no assigned devices, just set everything to WB. If guests
1155 * have assigned devices, however, we cannot force WB for RAM
1156 * pages only, so use the guest PAT directly.
1158 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1159 *g_pat
= 0x0606060606060606;
1161 *g_pat
= vcpu
->arch
.pat
;
1164 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
1169 * 1. MMIO: trust guest MTRR, so same as item 3.
1170 * 2. No passthrough: always map as WB, and force guest PAT to WB as well
1171 * 3. Passthrough: can't guarantee the result, try to trust guest.
1173 if (!is_mmio
&& !kvm_arch_has_assigned_device(vcpu
->kvm
))
1176 if (!kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
) &&
1177 kvm_read_cr0(vcpu
) & X86_CR0_CD
)
1178 return _PAGE_NOCACHE
;
1180 mtrr
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
1181 return mtrr2protval
[mtrr
];
1184 static void init_vmcb(struct vcpu_svm
*svm
, bool init_event
)
1186 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1187 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1189 svm
->vcpu
.fpu_active
= 1;
1190 svm
->vcpu
.arch
.hflags
= 0;
1192 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1193 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1194 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1195 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1196 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1197 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1198 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1200 set_dr_intercepts(svm
);
1202 set_exception_intercept(svm
, PF_VECTOR
);
1203 set_exception_intercept(svm
, UD_VECTOR
);
1204 set_exception_intercept(svm
, MC_VECTOR
);
1206 set_intercept(svm
, INTERCEPT_INTR
);
1207 set_intercept(svm
, INTERCEPT_NMI
);
1208 set_intercept(svm
, INTERCEPT_SMI
);
1209 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1210 set_intercept(svm
, INTERCEPT_RDPMC
);
1211 set_intercept(svm
, INTERCEPT_CPUID
);
1212 set_intercept(svm
, INTERCEPT_INVD
);
1213 set_intercept(svm
, INTERCEPT_HLT
);
1214 set_intercept(svm
, INTERCEPT_INVLPG
);
1215 set_intercept(svm
, INTERCEPT_INVLPGA
);
1216 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1217 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1218 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1219 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1220 set_intercept(svm
, INTERCEPT_VMRUN
);
1221 set_intercept(svm
, INTERCEPT_VMMCALL
);
1222 set_intercept(svm
, INTERCEPT_VMLOAD
);
1223 set_intercept(svm
, INTERCEPT_VMSAVE
);
1224 set_intercept(svm
, INTERCEPT_STGI
);
1225 set_intercept(svm
, INTERCEPT_CLGI
);
1226 set_intercept(svm
, INTERCEPT_SKINIT
);
1227 set_intercept(svm
, INTERCEPT_WBINVD
);
1228 set_intercept(svm
, INTERCEPT_MONITOR
);
1229 set_intercept(svm
, INTERCEPT_MWAIT
);
1230 set_intercept(svm
, INTERCEPT_XSETBV
);
1232 control
->iopm_base_pa
= iopm_base
;
1233 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1234 control
->int_ctl
= V_INTR_MASKING_MASK
;
1236 init_seg(&save
->es
);
1237 init_seg(&save
->ss
);
1238 init_seg(&save
->ds
);
1239 init_seg(&save
->fs
);
1240 init_seg(&save
->gs
);
1242 save
->cs
.selector
= 0xf000;
1243 save
->cs
.base
= 0xffff0000;
1244 /* Executable/Readable Code Segment */
1245 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1246 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1247 save
->cs
.limit
= 0xffff;
1249 save
->gdtr
.limit
= 0xffff;
1250 save
->idtr
.limit
= 0xffff;
1252 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1253 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1256 svm_set_efer(&svm
->vcpu
, 0);
1257 save
->dr6
= 0xffff0ff0;
1258 kvm_set_rflags(&svm
->vcpu
, 2);
1259 save
->rip
= 0x0000fff0;
1260 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1263 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1264 * It also updates the guest-visible cr0 value.
1266 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1268 save
->cr4
= X86_CR4_PAE
;
1272 /* Setup VMCB for Nested Paging */
1273 control
->nested_ctl
= 1;
1274 clr_intercept(svm
, INTERCEPT_INVLPG
);
1275 clr_exception_intercept(svm
, PF_VECTOR
);
1276 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1277 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1278 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1279 svm_set_guest_pat(svm
, &save
->g_pat
);
1283 svm
->asid_generation
= 0;
1285 svm
->nested
.vmcb
= 0;
1286 svm
->vcpu
.arch
.hflags
= 0;
1288 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1289 control
->pause_filter_count
= 3000;
1290 set_intercept(svm
, INTERCEPT_PAUSE
);
1293 mark_all_dirty(svm
->vmcb
);
1298 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1300 struct vcpu_svm
*svm
= to_svm(vcpu
);
1305 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1306 MSR_IA32_APICBASE_ENABLE
;
1307 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1308 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1310 init_vmcb(svm
, init_event
);
1312 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
);
1313 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1316 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1318 struct vcpu_svm
*svm
;
1320 struct page
*msrpm_pages
;
1321 struct page
*hsave_page
;
1322 struct page
*nested_msrpm_pages
;
1325 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1331 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1333 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1338 page
= alloc_page(GFP_KERNEL
);
1342 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1346 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1347 if (!nested_msrpm_pages
)
1350 hsave_page
= alloc_page(GFP_KERNEL
);
1354 svm
->nested
.hsave
= page_address(hsave_page
);
1356 svm
->msrpm
= page_address(msrpm_pages
);
1357 svm_vcpu_init_msrpm(svm
->msrpm
);
1359 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1360 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1362 svm
->vmcb
= page_address(page
);
1363 clear_page(svm
->vmcb
);
1364 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1365 svm
->asid_generation
= 0;
1366 init_vmcb(svm
, false);
1368 svm_init_osvw(&svm
->vcpu
);
1373 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1375 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1379 kvm_vcpu_uninit(&svm
->vcpu
);
1381 kmem_cache_free(kvm_vcpu_cache
, svm
);
1383 return ERR_PTR(err
);
1386 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1388 struct vcpu_svm
*svm
= to_svm(vcpu
);
1390 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1391 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1392 __free_page(virt_to_page(svm
->nested
.hsave
));
1393 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1394 kvm_vcpu_uninit(vcpu
);
1395 kmem_cache_free(kvm_vcpu_cache
, svm
);
1398 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1400 struct vcpu_svm
*svm
= to_svm(vcpu
);
1403 if (unlikely(cpu
!= vcpu
->cpu
)) {
1404 svm
->asid_generation
= 0;
1405 mark_all_dirty(svm
->vmcb
);
1408 #ifdef CONFIG_X86_64
1409 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1411 savesegment(fs
, svm
->host
.fs
);
1412 savesegment(gs
, svm
->host
.gs
);
1413 svm
->host
.ldt
= kvm_read_ldt();
1415 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1416 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1418 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
) &&
1419 svm
->tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1420 __this_cpu_write(current_tsc_ratio
, svm
->tsc_ratio
);
1421 wrmsrl(MSR_AMD64_TSC_RATIO
, svm
->tsc_ratio
);
1425 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1427 struct vcpu_svm
*svm
= to_svm(vcpu
);
1430 ++vcpu
->stat
.host_state_reload
;
1431 kvm_load_ldt(svm
->host
.ldt
);
1432 #ifdef CONFIG_X86_64
1433 loadsegment(fs
, svm
->host
.fs
);
1434 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1435 load_gs_index(svm
->host
.gs
);
1437 #ifdef CONFIG_X86_32_LAZY_GS
1438 loadsegment(gs
, svm
->host
.gs
);
1441 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1442 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1445 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1447 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1450 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1453 * Any change of EFLAGS.VM is accompained by a reload of SS
1454 * (caused by either a task switch or an inter-privilege IRET),
1455 * so we do not need to update the CPL here.
1457 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1460 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1463 case VCPU_EXREG_PDPTR
:
1464 BUG_ON(!npt_enabled
);
1465 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1472 static void svm_set_vintr(struct vcpu_svm
*svm
)
1474 set_intercept(svm
, INTERCEPT_VINTR
);
1477 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1479 clr_intercept(svm
, INTERCEPT_VINTR
);
1482 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1484 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1487 case VCPU_SREG_CS
: return &save
->cs
;
1488 case VCPU_SREG_DS
: return &save
->ds
;
1489 case VCPU_SREG_ES
: return &save
->es
;
1490 case VCPU_SREG_FS
: return &save
->fs
;
1491 case VCPU_SREG_GS
: return &save
->gs
;
1492 case VCPU_SREG_SS
: return &save
->ss
;
1493 case VCPU_SREG_TR
: return &save
->tr
;
1494 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1500 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1502 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1507 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1508 struct kvm_segment
*var
, int seg
)
1510 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1512 var
->base
= s
->base
;
1513 var
->limit
= s
->limit
;
1514 var
->selector
= s
->selector
;
1515 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1516 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1517 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1518 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1519 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1520 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1521 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1524 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1525 * However, the SVM spec states that the G bit is not observed by the
1526 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1527 * So let's synthesize a legal G bit for all segments, this helps
1528 * running KVM nested. It also helps cross-vendor migration, because
1529 * Intel's vmentry has a check on the 'G' bit.
1531 var
->g
= s
->limit
> 0xfffff;
1534 * AMD's VMCB does not have an explicit unusable field, so emulate it
1535 * for cross vendor migration purposes by "not present"
1537 var
->unusable
= !var
->present
|| (var
->type
== 0);
1542 * Work around a bug where the busy flag in the tr selector
1552 * The accessed bit must always be set in the segment
1553 * descriptor cache, although it can be cleared in the
1554 * descriptor, the cached bit always remains at 1. Since
1555 * Intel has a check on this, set it here to support
1556 * cross-vendor migration.
1563 * On AMD CPUs sometimes the DB bit in the segment
1564 * descriptor is left as 1, although the whole segment has
1565 * been made unusable. Clear it here to pass an Intel VMX
1566 * entry check when cross vendor migrating.
1570 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1575 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1577 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1582 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1584 struct vcpu_svm
*svm
= to_svm(vcpu
);
1586 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1587 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1590 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1592 struct vcpu_svm
*svm
= to_svm(vcpu
);
1594 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1595 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1596 mark_dirty(svm
->vmcb
, VMCB_DT
);
1599 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1601 struct vcpu_svm
*svm
= to_svm(vcpu
);
1603 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1604 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1607 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1609 struct vcpu_svm
*svm
= to_svm(vcpu
);
1611 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1612 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1613 mark_dirty(svm
->vmcb
, VMCB_DT
);
1616 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1620 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1624 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1628 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1630 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1631 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1633 if (!svm
->vcpu
.fpu_active
)
1634 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1636 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1637 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1639 mark_dirty(svm
->vmcb
, VMCB_CR
);
1641 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1642 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1643 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1645 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1646 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1650 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1652 struct vcpu_svm
*svm
= to_svm(vcpu
);
1654 #ifdef CONFIG_X86_64
1655 if (vcpu
->arch
.efer
& EFER_LME
) {
1656 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1657 vcpu
->arch
.efer
|= EFER_LMA
;
1658 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1661 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1662 vcpu
->arch
.efer
&= ~EFER_LMA
;
1663 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1667 vcpu
->arch
.cr0
= cr0
;
1670 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1672 if (!vcpu
->fpu_active
)
1675 /* These are emulated via page tables. */
1676 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1678 svm
->vmcb
->save
.cr0
= cr0
;
1679 mark_dirty(svm
->vmcb
, VMCB_CR
);
1680 update_cr0_intercept(svm
);
1683 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1685 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
1686 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1688 if (cr4
& X86_CR4_VMXE
)
1691 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1692 svm_flush_tlb(vcpu
);
1694 vcpu
->arch
.cr4
= cr4
;
1697 cr4
|= host_cr4_mce
;
1698 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1699 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1703 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1704 struct kvm_segment
*var
, int seg
)
1706 struct vcpu_svm
*svm
= to_svm(vcpu
);
1707 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1709 s
->base
= var
->base
;
1710 s
->limit
= var
->limit
;
1711 s
->selector
= var
->selector
;
1715 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1716 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1717 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1718 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1719 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1720 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1721 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1722 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1726 * This is always accurate, except if SYSRET returned to a segment
1727 * with SS.DPL != 3. Intel does not have this quirk, and always
1728 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1729 * would entail passing the CPL to userspace and back.
1731 if (seg
== VCPU_SREG_SS
)
1732 svm
->vmcb
->save
.cpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1734 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1737 static void update_db_bp_intercept(struct kvm_vcpu
*vcpu
)
1739 struct vcpu_svm
*svm
= to_svm(vcpu
);
1741 clr_exception_intercept(svm
, DB_VECTOR
);
1742 clr_exception_intercept(svm
, BP_VECTOR
);
1744 if (svm
->nmi_singlestep
)
1745 set_exception_intercept(svm
, DB_VECTOR
);
1747 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1748 if (vcpu
->guest_debug
&
1749 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1750 set_exception_intercept(svm
, DB_VECTOR
);
1751 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1752 set_exception_intercept(svm
, BP_VECTOR
);
1754 vcpu
->guest_debug
= 0;
1757 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1759 if (sd
->next_asid
> sd
->max_asid
) {
1760 ++sd
->asid_generation
;
1762 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1765 svm
->asid_generation
= sd
->asid_generation
;
1766 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1768 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1771 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
1773 return to_svm(vcpu
)->vmcb
->save
.dr6
;
1776 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
1778 struct vcpu_svm
*svm
= to_svm(vcpu
);
1780 svm
->vmcb
->save
.dr6
= value
;
1781 mark_dirty(svm
->vmcb
, VMCB_DR
);
1784 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
1786 struct vcpu_svm
*svm
= to_svm(vcpu
);
1788 get_debugreg(vcpu
->arch
.db
[0], 0);
1789 get_debugreg(vcpu
->arch
.db
[1], 1);
1790 get_debugreg(vcpu
->arch
.db
[2], 2);
1791 get_debugreg(vcpu
->arch
.db
[3], 3);
1792 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
1793 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
1795 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
1796 set_dr_intercepts(svm
);
1799 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1801 struct vcpu_svm
*svm
= to_svm(vcpu
);
1803 svm
->vmcb
->save
.dr7
= value
;
1804 mark_dirty(svm
->vmcb
, VMCB_DR
);
1807 static int pf_interception(struct vcpu_svm
*svm
)
1809 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1813 switch (svm
->apf_reason
) {
1815 error_code
= svm
->vmcb
->control
.exit_info_1
;
1817 trace_kvm_page_fault(fault_address
, error_code
);
1818 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1819 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1820 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1821 svm
->vmcb
->control
.insn_bytes
,
1822 svm
->vmcb
->control
.insn_len
);
1824 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1825 svm
->apf_reason
= 0;
1826 local_irq_disable();
1827 kvm_async_pf_task_wait(fault_address
);
1830 case KVM_PV_REASON_PAGE_READY
:
1831 svm
->apf_reason
= 0;
1832 local_irq_disable();
1833 kvm_async_pf_task_wake(fault_address
);
1840 static int db_interception(struct vcpu_svm
*svm
)
1842 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1844 if (!(svm
->vcpu
.guest_debug
&
1845 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1846 !svm
->nmi_singlestep
) {
1847 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1851 if (svm
->nmi_singlestep
) {
1852 svm
->nmi_singlestep
= false;
1853 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1854 svm
->vmcb
->save
.rflags
&=
1855 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1856 update_db_bp_intercept(&svm
->vcpu
);
1859 if (svm
->vcpu
.guest_debug
&
1860 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1861 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1862 kvm_run
->debug
.arch
.pc
=
1863 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1864 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1871 static int bp_interception(struct vcpu_svm
*svm
)
1873 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1875 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1876 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1877 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1881 static int ud_interception(struct vcpu_svm
*svm
)
1885 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1886 if (er
!= EMULATE_DONE
)
1887 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1891 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1893 struct vcpu_svm
*svm
= to_svm(vcpu
);
1895 clr_exception_intercept(svm
, NM_VECTOR
);
1897 svm
->vcpu
.fpu_active
= 1;
1898 update_cr0_intercept(svm
);
1901 static int nm_interception(struct vcpu_svm
*svm
)
1903 svm_fpu_activate(&svm
->vcpu
);
1907 static bool is_erratum_383(void)
1912 if (!erratum_383_found
)
1915 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1919 /* Bit 62 may or may not be set for this mce */
1920 value
&= ~(1ULL << 62);
1922 if (value
!= 0xb600000000010015ULL
)
1925 /* Clear MCi_STATUS registers */
1926 for (i
= 0; i
< 6; ++i
)
1927 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1929 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1933 value
&= ~(1ULL << 2);
1934 low
= lower_32_bits(value
);
1935 high
= upper_32_bits(value
);
1937 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1940 /* Flush tlb to evict multi-match entries */
1946 static void svm_handle_mce(struct vcpu_svm
*svm
)
1948 if (is_erratum_383()) {
1950 * Erratum 383 triggered. Guest state is corrupt so kill the
1953 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1955 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1961 * On an #MC intercept the MCE handler is not called automatically in
1962 * the host. So do it by hand here.
1966 /* not sure if we ever come back to this point */
1971 static int mc_interception(struct vcpu_svm
*svm
)
1976 static int shutdown_interception(struct vcpu_svm
*svm
)
1978 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1981 * VMCB is undefined after a SHUTDOWN intercept
1982 * so reinitialize it.
1984 clear_page(svm
->vmcb
);
1985 init_vmcb(svm
, false);
1987 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1991 static int io_interception(struct vcpu_svm
*svm
)
1993 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1994 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1995 int size
, in
, string
;
1998 ++svm
->vcpu
.stat
.io_exits
;
1999 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2000 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2002 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2004 port
= io_info
>> 16;
2005 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2006 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2007 skip_emulated_instruction(&svm
->vcpu
);
2009 return kvm_fast_pio_out(vcpu
, size
, port
);
2012 static int nmi_interception(struct vcpu_svm
*svm
)
2017 static int intr_interception(struct vcpu_svm
*svm
)
2019 ++svm
->vcpu
.stat
.irq_exits
;
2023 static int nop_on_interception(struct vcpu_svm
*svm
)
2028 static int halt_interception(struct vcpu_svm
*svm
)
2030 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2031 return kvm_emulate_halt(&svm
->vcpu
);
2034 static int vmmcall_interception(struct vcpu_svm
*svm
)
2036 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2037 kvm_emulate_hypercall(&svm
->vcpu
);
2041 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2043 struct vcpu_svm
*svm
= to_svm(vcpu
);
2045 return svm
->nested
.nested_cr3
;
2048 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2050 struct vcpu_svm
*svm
= to_svm(vcpu
);
2051 u64 cr3
= svm
->nested
.nested_cr3
;
2055 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(cr3
), &pdpte
,
2056 offset_in_page(cr3
) + index
* 8, 8);
2062 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2065 struct vcpu_svm
*svm
= to_svm(vcpu
);
2067 svm
->vmcb
->control
.nested_cr3
= root
;
2068 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2069 svm_flush_tlb(vcpu
);
2072 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2073 struct x86_exception
*fault
)
2075 struct vcpu_svm
*svm
= to_svm(vcpu
);
2077 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2079 * TODO: track the cause of the nested page fault, and
2080 * correctly fill in the high bits of exit_info_1.
2082 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2083 svm
->vmcb
->control
.exit_code_hi
= 0;
2084 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2085 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2088 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2089 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2092 * The present bit is always zero for page structure faults on real
2095 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2096 svm
->vmcb
->control
.exit_info_1
&= ~1;
2098 nested_svm_vmexit(svm
);
2101 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2103 WARN_ON(mmu_is_nested(vcpu
));
2104 kvm_init_shadow_mmu(vcpu
);
2105 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2106 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2107 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2108 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2109 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
2110 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2111 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2114 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2116 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2119 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2121 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
2122 || !is_paging(&svm
->vcpu
)) {
2123 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2127 if (svm
->vmcb
->save
.cpl
) {
2128 kvm_inject_gp(&svm
->vcpu
, 0);
2135 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2136 bool has_error_code
, u32 error_code
)
2140 if (!is_guest_mode(&svm
->vcpu
))
2143 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2144 svm
->vmcb
->control
.exit_code_hi
= 0;
2145 svm
->vmcb
->control
.exit_info_1
= error_code
;
2146 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2148 vmexit
= nested_svm_intercept(svm
);
2149 if (vmexit
== NESTED_EXIT_DONE
)
2150 svm
->nested
.exit_required
= true;
2155 /* This function returns true if it is save to enable the irq window */
2156 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2158 if (!is_guest_mode(&svm
->vcpu
))
2161 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2164 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2168 * if vmexit was already requested (by intercepted exception
2169 * for instance) do not overwrite it with "external interrupt"
2172 if (svm
->nested
.exit_required
)
2175 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2176 svm
->vmcb
->control
.exit_info_1
= 0;
2177 svm
->vmcb
->control
.exit_info_2
= 0;
2179 if (svm
->nested
.intercept
& 1ULL) {
2181 * The #vmexit can't be emulated here directly because this
2182 * code path runs with irqs and preemption disabled. A
2183 * #vmexit emulation might sleep. Only signal request for
2186 svm
->nested
.exit_required
= true;
2187 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2194 /* This function returns true if it is save to enable the nmi window */
2195 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2197 if (!is_guest_mode(&svm
->vcpu
))
2200 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2203 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2204 svm
->nested
.exit_required
= true;
2209 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2215 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2216 if (is_error_page(page
))
2224 kvm_inject_gp(&svm
->vcpu
, 0);
2229 static void nested_svm_unmap(struct page
*page
)
2232 kvm_release_page_dirty(page
);
2235 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2237 unsigned port
, size
, iopm_len
;
2242 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2243 return NESTED_EXIT_HOST
;
2245 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2246 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2247 SVM_IOIO_SIZE_SHIFT
;
2248 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2249 start_bit
= port
% 8;
2250 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2251 mask
= (0xf >> (4 - size
)) << start_bit
;
2254 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2255 return NESTED_EXIT_DONE
;
2257 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2260 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2262 u32 offset
, msr
, value
;
2265 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2266 return NESTED_EXIT_HOST
;
2268 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2269 offset
= svm_msrpm_offset(msr
);
2270 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2271 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2273 if (offset
== MSR_INVALID
)
2274 return NESTED_EXIT_DONE
;
2276 /* Offset is in 32 bit units but need in 8 bit units */
2279 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2280 return NESTED_EXIT_DONE
;
2282 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2285 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2287 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2289 switch (exit_code
) {
2292 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2293 return NESTED_EXIT_HOST
;
2295 /* For now we are always handling NPFs when using them */
2297 return NESTED_EXIT_HOST
;
2299 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2300 /* When we're shadowing, trap PFs, but not async PF */
2301 if (!npt_enabled
&& svm
->apf_reason
== 0)
2302 return NESTED_EXIT_HOST
;
2304 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2305 nm_interception(svm
);
2311 return NESTED_EXIT_CONTINUE
;
2315 * If this function returns true, this #vmexit was already handled
2317 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2319 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2320 int vmexit
= NESTED_EXIT_HOST
;
2322 switch (exit_code
) {
2324 vmexit
= nested_svm_exit_handled_msr(svm
);
2327 vmexit
= nested_svm_intercept_ioio(svm
);
2329 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2330 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2331 if (svm
->nested
.intercept_cr
& bit
)
2332 vmexit
= NESTED_EXIT_DONE
;
2335 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2336 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2337 if (svm
->nested
.intercept_dr
& bit
)
2338 vmexit
= NESTED_EXIT_DONE
;
2341 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2342 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2343 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2344 vmexit
= NESTED_EXIT_DONE
;
2345 /* async page fault always cause vmexit */
2346 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2347 svm
->apf_reason
!= 0)
2348 vmexit
= NESTED_EXIT_DONE
;
2351 case SVM_EXIT_ERR
: {
2352 vmexit
= NESTED_EXIT_DONE
;
2356 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2357 if (svm
->nested
.intercept
& exit_bits
)
2358 vmexit
= NESTED_EXIT_DONE
;
2365 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2369 vmexit
= nested_svm_intercept(svm
);
2371 if (vmexit
== NESTED_EXIT_DONE
)
2372 nested_svm_vmexit(svm
);
2377 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2379 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2380 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2382 dst
->intercept_cr
= from
->intercept_cr
;
2383 dst
->intercept_dr
= from
->intercept_dr
;
2384 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2385 dst
->intercept
= from
->intercept
;
2386 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2387 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2388 dst
->tsc_offset
= from
->tsc_offset
;
2389 dst
->asid
= from
->asid
;
2390 dst
->tlb_ctl
= from
->tlb_ctl
;
2391 dst
->int_ctl
= from
->int_ctl
;
2392 dst
->int_vector
= from
->int_vector
;
2393 dst
->int_state
= from
->int_state
;
2394 dst
->exit_code
= from
->exit_code
;
2395 dst
->exit_code_hi
= from
->exit_code_hi
;
2396 dst
->exit_info_1
= from
->exit_info_1
;
2397 dst
->exit_info_2
= from
->exit_info_2
;
2398 dst
->exit_int_info
= from
->exit_int_info
;
2399 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2400 dst
->nested_ctl
= from
->nested_ctl
;
2401 dst
->event_inj
= from
->event_inj
;
2402 dst
->event_inj_err
= from
->event_inj_err
;
2403 dst
->nested_cr3
= from
->nested_cr3
;
2404 dst
->lbr_ctl
= from
->lbr_ctl
;
2407 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2409 struct vmcb
*nested_vmcb
;
2410 struct vmcb
*hsave
= svm
->nested
.hsave
;
2411 struct vmcb
*vmcb
= svm
->vmcb
;
2414 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2415 vmcb
->control
.exit_info_1
,
2416 vmcb
->control
.exit_info_2
,
2417 vmcb
->control
.exit_int_info
,
2418 vmcb
->control
.exit_int_info_err
,
2421 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2425 /* Exit Guest-Mode */
2426 leave_guest_mode(&svm
->vcpu
);
2427 svm
->nested
.vmcb
= 0;
2429 /* Give the current vmcb to the guest */
2432 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2433 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2434 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2435 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2436 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2437 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2438 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2439 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2440 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2441 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2442 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2443 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2444 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2445 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2446 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2447 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2448 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2449 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2451 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2452 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2453 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2454 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2455 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2456 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2457 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2458 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2459 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2460 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2463 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2464 * to make sure that we do not lose injected events. So check event_inj
2465 * here and copy it to exit_int_info if it is valid.
2466 * Exit_int_info and event_inj can't be both valid because the case
2467 * below only happens on a VMRUN instruction intercept which has
2468 * no valid exit_int_info set.
2470 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2471 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2473 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2474 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2477 nested_vmcb
->control
.tlb_ctl
= 0;
2478 nested_vmcb
->control
.event_inj
= 0;
2479 nested_vmcb
->control
.event_inj_err
= 0;
2481 /* We always set V_INTR_MASKING and remember the old value in hflags */
2482 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2483 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2485 /* Restore the original control entries */
2486 copy_vmcb_control_area(vmcb
, hsave
);
2488 kvm_clear_exception_queue(&svm
->vcpu
);
2489 kvm_clear_interrupt_queue(&svm
->vcpu
);
2491 svm
->nested
.nested_cr3
= 0;
2493 /* Restore selected save entries */
2494 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2495 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2496 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2497 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2498 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2499 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2500 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2501 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2502 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2503 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2505 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2506 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2508 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2510 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2511 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2512 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2513 svm
->vmcb
->save
.dr7
= 0;
2514 svm
->vmcb
->save
.cpl
= 0;
2515 svm
->vmcb
->control
.exit_int_info
= 0;
2517 mark_all_dirty(svm
->vmcb
);
2519 nested_svm_unmap(page
);
2521 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2522 kvm_mmu_reset_context(&svm
->vcpu
);
2523 kvm_mmu_load(&svm
->vcpu
);
2528 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2531 * This function merges the msr permission bitmaps of kvm and the
2532 * nested vmcb. It is optimized in that it only merges the parts where
2533 * the kvm msr permission bitmap may contain zero bits
2537 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2540 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2544 if (msrpm_offsets
[i
] == 0xffffffff)
2547 p
= msrpm_offsets
[i
];
2548 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2550 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2553 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2556 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2561 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2563 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2566 if (vmcb
->control
.asid
== 0)
2569 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2575 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2577 struct vmcb
*nested_vmcb
;
2578 struct vmcb
*hsave
= svm
->nested
.hsave
;
2579 struct vmcb
*vmcb
= svm
->vmcb
;
2583 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2585 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2589 if (!nested_vmcb_checks(nested_vmcb
)) {
2590 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2591 nested_vmcb
->control
.exit_code_hi
= 0;
2592 nested_vmcb
->control
.exit_info_1
= 0;
2593 nested_vmcb
->control
.exit_info_2
= 0;
2595 nested_svm_unmap(page
);
2600 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2601 nested_vmcb
->save
.rip
,
2602 nested_vmcb
->control
.int_ctl
,
2603 nested_vmcb
->control
.event_inj
,
2604 nested_vmcb
->control
.nested_ctl
);
2606 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2607 nested_vmcb
->control
.intercept_cr
>> 16,
2608 nested_vmcb
->control
.intercept_exceptions
,
2609 nested_vmcb
->control
.intercept
);
2611 /* Clear internal status */
2612 kvm_clear_exception_queue(&svm
->vcpu
);
2613 kvm_clear_interrupt_queue(&svm
->vcpu
);
2616 * Save the old vmcb, so we don't need to pick what we save, but can
2617 * restore everything when a VMEXIT occurs
2619 hsave
->save
.es
= vmcb
->save
.es
;
2620 hsave
->save
.cs
= vmcb
->save
.cs
;
2621 hsave
->save
.ss
= vmcb
->save
.ss
;
2622 hsave
->save
.ds
= vmcb
->save
.ds
;
2623 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2624 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2625 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2626 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2627 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2628 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2629 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2630 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2631 hsave
->save
.rax
= vmcb
->save
.rax
;
2633 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2635 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2637 copy_vmcb_control_area(hsave
, vmcb
);
2639 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2640 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2642 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2644 if (nested_vmcb
->control
.nested_ctl
) {
2645 kvm_mmu_unload(&svm
->vcpu
);
2646 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2647 nested_svm_init_mmu_context(&svm
->vcpu
);
2650 /* Load the nested guest state */
2651 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2652 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2653 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2654 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2655 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2656 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2657 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2658 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2659 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2660 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2662 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2663 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2665 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2667 /* Guest paging mode is active - reset mmu */
2668 kvm_mmu_reset_context(&svm
->vcpu
);
2670 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2671 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2672 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2673 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2675 /* In case we don't even reach vcpu_run, the fields are not updated */
2676 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2677 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2678 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2679 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2680 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2681 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2683 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2684 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2686 /* cache intercepts */
2687 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2688 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2689 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2690 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2692 svm_flush_tlb(&svm
->vcpu
);
2693 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2694 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2695 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2697 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2699 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2700 /* We only want the cr8 intercept bits of the guest */
2701 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2702 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2705 /* We don't want to see VMMCALLs from a nested guest */
2706 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2708 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2709 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2710 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2711 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2712 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2713 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2715 nested_svm_unmap(page
);
2717 /* Enter Guest-Mode */
2718 enter_guest_mode(&svm
->vcpu
);
2721 * Merge guest and host intercepts - must be called with vcpu in
2722 * guest-mode to take affect here
2724 recalc_intercepts(svm
);
2726 svm
->nested
.vmcb
= vmcb_gpa
;
2730 mark_all_dirty(svm
->vmcb
);
2735 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2737 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2738 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2739 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2740 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2741 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2742 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2743 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2744 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2745 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2746 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2747 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2748 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2751 static int vmload_interception(struct vcpu_svm
*svm
)
2753 struct vmcb
*nested_vmcb
;
2756 if (nested_svm_check_permissions(svm
))
2759 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2763 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2764 skip_emulated_instruction(&svm
->vcpu
);
2766 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2767 nested_svm_unmap(page
);
2772 static int vmsave_interception(struct vcpu_svm
*svm
)
2774 struct vmcb
*nested_vmcb
;
2777 if (nested_svm_check_permissions(svm
))
2780 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2784 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2785 skip_emulated_instruction(&svm
->vcpu
);
2787 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2788 nested_svm_unmap(page
);
2793 static int vmrun_interception(struct vcpu_svm
*svm
)
2795 if (nested_svm_check_permissions(svm
))
2798 /* Save rip after vmrun instruction */
2799 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2801 if (!nested_svm_vmrun(svm
))
2804 if (!nested_svm_vmrun_msrpm(svm
))
2811 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2812 svm
->vmcb
->control
.exit_code_hi
= 0;
2813 svm
->vmcb
->control
.exit_info_1
= 0;
2814 svm
->vmcb
->control
.exit_info_2
= 0;
2816 nested_svm_vmexit(svm
);
2821 static int stgi_interception(struct vcpu_svm
*svm
)
2823 if (nested_svm_check_permissions(svm
))
2826 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2827 skip_emulated_instruction(&svm
->vcpu
);
2828 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2835 static int clgi_interception(struct vcpu_svm
*svm
)
2837 if (nested_svm_check_permissions(svm
))
2840 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2841 skip_emulated_instruction(&svm
->vcpu
);
2845 /* After a CLGI no interrupts should come */
2846 svm_clear_vintr(svm
);
2847 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2849 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2854 static int invlpga_interception(struct vcpu_svm
*svm
)
2856 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2858 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
2859 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2861 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2862 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2864 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2865 skip_emulated_instruction(&svm
->vcpu
);
2869 static int skinit_interception(struct vcpu_svm
*svm
)
2871 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2873 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2877 static int wbinvd_interception(struct vcpu_svm
*svm
)
2879 kvm_emulate_wbinvd(&svm
->vcpu
);
2883 static int xsetbv_interception(struct vcpu_svm
*svm
)
2885 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2886 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2888 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2889 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2890 skip_emulated_instruction(&svm
->vcpu
);
2896 static int task_switch_interception(struct vcpu_svm
*svm
)
2900 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2901 SVM_EXITINTINFO_TYPE_MASK
;
2902 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2904 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2906 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2907 bool has_error_code
= false;
2910 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2912 if (svm
->vmcb
->control
.exit_info_2
&
2913 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2914 reason
= TASK_SWITCH_IRET
;
2915 else if (svm
->vmcb
->control
.exit_info_2
&
2916 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2917 reason
= TASK_SWITCH_JMP
;
2919 reason
= TASK_SWITCH_GATE
;
2921 reason
= TASK_SWITCH_CALL
;
2923 if (reason
== TASK_SWITCH_GATE
) {
2925 case SVM_EXITINTINFO_TYPE_NMI
:
2926 svm
->vcpu
.arch
.nmi_injected
= false;
2928 case SVM_EXITINTINFO_TYPE_EXEPT
:
2929 if (svm
->vmcb
->control
.exit_info_2
&
2930 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2931 has_error_code
= true;
2933 (u32
)svm
->vmcb
->control
.exit_info_2
;
2935 kvm_clear_exception_queue(&svm
->vcpu
);
2937 case SVM_EXITINTINFO_TYPE_INTR
:
2938 kvm_clear_interrupt_queue(&svm
->vcpu
);
2945 if (reason
!= TASK_SWITCH_GATE
||
2946 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2947 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2948 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2949 skip_emulated_instruction(&svm
->vcpu
);
2951 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2954 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
2955 has_error_code
, error_code
) == EMULATE_FAIL
) {
2956 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2957 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2958 svm
->vcpu
.run
->internal
.ndata
= 0;
2964 static int cpuid_interception(struct vcpu_svm
*svm
)
2966 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2967 kvm_emulate_cpuid(&svm
->vcpu
);
2971 static int iret_interception(struct vcpu_svm
*svm
)
2973 ++svm
->vcpu
.stat
.nmi_window_exits
;
2974 clr_intercept(svm
, INTERCEPT_IRET
);
2975 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2976 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2977 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2981 static int invlpg_interception(struct vcpu_svm
*svm
)
2983 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2984 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2986 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2987 skip_emulated_instruction(&svm
->vcpu
);
2991 static int emulate_on_interception(struct vcpu_svm
*svm
)
2993 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2996 static int rdpmc_interception(struct vcpu_svm
*svm
)
3000 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3001 return emulate_on_interception(svm
);
3003 err
= kvm_rdpmc(&svm
->vcpu
);
3004 kvm_complete_insn_gp(&svm
->vcpu
, err
);
3009 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3012 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3016 intercept
= svm
->nested
.intercept
;
3018 if (!is_guest_mode(&svm
->vcpu
) ||
3019 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3022 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3023 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3026 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3027 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3033 #define CR_VALID (1ULL << 63)
3035 static int cr_interception(struct vcpu_svm
*svm
)
3041 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3042 return emulate_on_interception(svm
);
3044 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3045 return emulate_on_interception(svm
);
3047 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3048 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3049 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3051 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3054 if (cr
>= 16) { /* mov to cr */
3056 val
= kvm_register_read(&svm
->vcpu
, reg
);
3059 if (!check_selective_cr0_intercepted(svm
, val
))
3060 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3066 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3069 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3072 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3075 WARN(1, "unhandled write to CR%d", cr
);
3076 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3079 } else { /* mov from cr */
3082 val
= kvm_read_cr0(&svm
->vcpu
);
3085 val
= svm
->vcpu
.arch
.cr2
;
3088 val
= kvm_read_cr3(&svm
->vcpu
);
3091 val
= kvm_read_cr4(&svm
->vcpu
);
3094 val
= kvm_get_cr8(&svm
->vcpu
);
3097 WARN(1, "unhandled read from CR%d", cr
);
3098 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3101 kvm_register_write(&svm
->vcpu
, reg
, val
);
3103 kvm_complete_insn_gp(&svm
->vcpu
, err
);
3108 static int dr_interception(struct vcpu_svm
*svm
)
3113 if (svm
->vcpu
.guest_debug
== 0) {
3115 * No more DR vmexits; force a reload of the debug registers
3116 * and reenter on this instruction. The next vmexit will
3117 * retrieve the full state of the debug registers.
3119 clr_dr_intercepts(svm
);
3120 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3124 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3125 return emulate_on_interception(svm
);
3127 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3128 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3130 if (dr
>= 16) { /* mov to DRn */
3131 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3133 val
= kvm_register_read(&svm
->vcpu
, reg
);
3134 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3136 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3138 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3139 kvm_register_write(&svm
->vcpu
, reg
, val
);
3142 skip_emulated_instruction(&svm
->vcpu
);
3147 static int cr8_write_interception(struct vcpu_svm
*svm
)
3149 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3152 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3153 /* instruction emulation calls kvm_set_cr8() */
3154 r
= cr_interception(svm
);
3155 if (irqchip_in_kernel(svm
->vcpu
.kvm
))
3157 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3159 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3163 static u64
svm_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
3165 struct vmcb
*vmcb
= get_host_vmcb(to_svm(vcpu
));
3166 return vmcb
->control
.tsc_offset
+
3167 svm_scale_tsc(vcpu
, host_tsc
);
3170 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3172 struct vcpu_svm
*svm
= to_svm(vcpu
);
3174 switch (msr_info
->index
) {
3175 case MSR_IA32_TSC
: {
3176 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
3177 svm_scale_tsc(vcpu
, rdtsc());
3182 msr_info
->data
= svm
->vmcb
->save
.star
;
3184 #ifdef CONFIG_X86_64
3186 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3189 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3191 case MSR_KERNEL_GS_BASE
:
3192 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3194 case MSR_SYSCALL_MASK
:
3195 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3198 case MSR_IA32_SYSENTER_CS
:
3199 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3201 case MSR_IA32_SYSENTER_EIP
:
3202 msr_info
->data
= svm
->sysenter_eip
;
3204 case MSR_IA32_SYSENTER_ESP
:
3205 msr_info
->data
= svm
->sysenter_esp
;
3208 * Nobody will change the following 5 values in the VMCB so we can
3209 * safely return them on rdmsr. They will always be 0 until LBRV is
3212 case MSR_IA32_DEBUGCTLMSR
:
3213 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3215 case MSR_IA32_LASTBRANCHFROMIP
:
3216 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3218 case MSR_IA32_LASTBRANCHTOIP
:
3219 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3221 case MSR_IA32_LASTINTFROMIP
:
3222 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3224 case MSR_IA32_LASTINTTOIP
:
3225 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3227 case MSR_VM_HSAVE_PA
:
3228 msr_info
->data
= svm
->nested
.hsave_msr
;
3231 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3233 case MSR_IA32_UCODE_REV
:
3234 msr_info
->data
= 0x01000065;
3237 return kvm_get_msr_common(vcpu
, msr_info
);
3242 static int rdmsr_interception(struct vcpu_svm
*svm
)
3244 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3245 struct msr_data msr_info
;
3247 msr_info
.index
= ecx
;
3248 msr_info
.host_initiated
= false;
3249 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3250 trace_kvm_msr_read_ex(ecx
);
3251 kvm_inject_gp(&svm
->vcpu
, 0);
3253 trace_kvm_msr_read(ecx
, msr_info
.data
);
3255 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3256 msr_info
.data
& 0xffffffff);
3257 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3258 msr_info
.data
>> 32);
3259 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3260 skip_emulated_instruction(&svm
->vcpu
);
3265 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3267 struct vcpu_svm
*svm
= to_svm(vcpu
);
3268 int svm_dis
, chg_mask
;
3270 if (data
& ~SVM_VM_CR_VALID_MASK
)
3273 chg_mask
= SVM_VM_CR_VALID_MASK
;
3275 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3276 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3278 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3279 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3281 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3283 /* check for svm_disable while efer.svme is set */
3284 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3290 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3292 struct vcpu_svm
*svm
= to_svm(vcpu
);
3294 u32 ecx
= msr
->index
;
3295 u64 data
= msr
->data
;
3298 kvm_write_tsc(vcpu
, msr
);
3301 svm
->vmcb
->save
.star
= data
;
3303 #ifdef CONFIG_X86_64
3305 svm
->vmcb
->save
.lstar
= data
;
3308 svm
->vmcb
->save
.cstar
= data
;
3310 case MSR_KERNEL_GS_BASE
:
3311 svm
->vmcb
->save
.kernel_gs_base
= data
;
3313 case MSR_SYSCALL_MASK
:
3314 svm
->vmcb
->save
.sfmask
= data
;
3317 case MSR_IA32_SYSENTER_CS
:
3318 svm
->vmcb
->save
.sysenter_cs
= data
;
3320 case MSR_IA32_SYSENTER_EIP
:
3321 svm
->sysenter_eip
= data
;
3322 svm
->vmcb
->save
.sysenter_eip
= data
;
3324 case MSR_IA32_SYSENTER_ESP
:
3325 svm
->sysenter_esp
= data
;
3326 svm
->vmcb
->save
.sysenter_esp
= data
;
3328 case MSR_IA32_DEBUGCTLMSR
:
3329 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3330 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3334 if (data
& DEBUGCTL_RESERVED_BITS
)
3337 svm
->vmcb
->save
.dbgctl
= data
;
3338 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3339 if (data
& (1ULL<<0))
3340 svm_enable_lbrv(svm
);
3342 svm_disable_lbrv(svm
);
3344 case MSR_VM_HSAVE_PA
:
3345 svm
->nested
.hsave_msr
= data
;
3348 return svm_set_vm_cr(vcpu
, data
);
3350 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3352 case MSR_IA32_CR_PAT
:
3354 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3356 vcpu
->arch
.pat
= data
;
3357 svm_set_guest_pat(svm
, &svm
->vmcb
->save
.g_pat
);
3358 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3363 return kvm_set_msr_common(vcpu
, msr
);
3368 static int wrmsr_interception(struct vcpu_svm
*svm
)
3370 struct msr_data msr
;
3371 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3372 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3376 msr
.host_initiated
= false;
3378 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3379 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3380 trace_kvm_msr_write_ex(ecx
, data
);
3381 kvm_inject_gp(&svm
->vcpu
, 0);
3383 trace_kvm_msr_write(ecx
, data
);
3384 skip_emulated_instruction(&svm
->vcpu
);
3389 static int msr_interception(struct vcpu_svm
*svm
)
3391 if (svm
->vmcb
->control
.exit_info_1
)
3392 return wrmsr_interception(svm
);
3394 return rdmsr_interception(svm
);
3397 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3399 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3401 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3402 svm_clear_vintr(svm
);
3403 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3404 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3405 ++svm
->vcpu
.stat
.irq_window_exits
;
3407 * If the user space waits to inject interrupts, exit as soon as
3410 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
3411 kvm_run
->request_interrupt_window
&&
3412 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
3413 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3420 static int pause_interception(struct vcpu_svm
*svm
)
3422 kvm_vcpu_on_spin(&(svm
->vcpu
));
3426 static int nop_interception(struct vcpu_svm
*svm
)
3428 skip_emulated_instruction(&(svm
->vcpu
));
3432 static int monitor_interception(struct vcpu_svm
*svm
)
3434 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3435 return nop_interception(svm
);
3438 static int mwait_interception(struct vcpu_svm
*svm
)
3440 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3441 return nop_interception(svm
);
3444 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3445 [SVM_EXIT_READ_CR0
] = cr_interception
,
3446 [SVM_EXIT_READ_CR3
] = cr_interception
,
3447 [SVM_EXIT_READ_CR4
] = cr_interception
,
3448 [SVM_EXIT_READ_CR8
] = cr_interception
,
3449 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
3450 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3451 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3452 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3453 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3454 [SVM_EXIT_READ_DR0
] = dr_interception
,
3455 [SVM_EXIT_READ_DR1
] = dr_interception
,
3456 [SVM_EXIT_READ_DR2
] = dr_interception
,
3457 [SVM_EXIT_READ_DR3
] = dr_interception
,
3458 [SVM_EXIT_READ_DR4
] = dr_interception
,
3459 [SVM_EXIT_READ_DR5
] = dr_interception
,
3460 [SVM_EXIT_READ_DR6
] = dr_interception
,
3461 [SVM_EXIT_READ_DR7
] = dr_interception
,
3462 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3463 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3464 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3465 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3466 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3467 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3468 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3469 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3470 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3471 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3472 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3473 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3474 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3475 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3476 [SVM_EXIT_INTR
] = intr_interception
,
3477 [SVM_EXIT_NMI
] = nmi_interception
,
3478 [SVM_EXIT_SMI
] = nop_on_interception
,
3479 [SVM_EXIT_INIT
] = nop_on_interception
,
3480 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3481 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3482 [SVM_EXIT_CPUID
] = cpuid_interception
,
3483 [SVM_EXIT_IRET
] = iret_interception
,
3484 [SVM_EXIT_INVD
] = emulate_on_interception
,
3485 [SVM_EXIT_PAUSE
] = pause_interception
,
3486 [SVM_EXIT_HLT
] = halt_interception
,
3487 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3488 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3489 [SVM_EXIT_IOIO
] = io_interception
,
3490 [SVM_EXIT_MSR
] = msr_interception
,
3491 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3492 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3493 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3494 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3495 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3496 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3497 [SVM_EXIT_STGI
] = stgi_interception
,
3498 [SVM_EXIT_CLGI
] = clgi_interception
,
3499 [SVM_EXIT_SKINIT
] = skinit_interception
,
3500 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
3501 [SVM_EXIT_MONITOR
] = monitor_interception
,
3502 [SVM_EXIT_MWAIT
] = mwait_interception
,
3503 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3504 [SVM_EXIT_NPF
] = pf_interception
,
3505 [SVM_EXIT_RSM
] = emulate_on_interception
,
3508 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3510 struct vcpu_svm
*svm
= to_svm(vcpu
);
3511 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3512 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3514 pr_err("VMCB Control Area:\n");
3515 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
3516 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
3517 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
3518 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
3519 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
3520 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
3521 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3522 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3523 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3524 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3525 pr_err("%-20s%d\n", "asid:", control
->asid
);
3526 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3527 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3528 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3529 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3530 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3531 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3532 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3533 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3534 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3535 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3536 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3537 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3538 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3539 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
3540 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3541 pr_err("VMCB State Save Area:\n");
3542 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3544 save
->es
.selector
, save
->es
.attrib
,
3545 save
->es
.limit
, save
->es
.base
);
3546 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3548 save
->cs
.selector
, save
->cs
.attrib
,
3549 save
->cs
.limit
, save
->cs
.base
);
3550 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3552 save
->ss
.selector
, save
->ss
.attrib
,
3553 save
->ss
.limit
, save
->ss
.base
);
3554 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3556 save
->ds
.selector
, save
->ds
.attrib
,
3557 save
->ds
.limit
, save
->ds
.base
);
3558 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3560 save
->fs
.selector
, save
->fs
.attrib
,
3561 save
->fs
.limit
, save
->fs
.base
);
3562 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3564 save
->gs
.selector
, save
->gs
.attrib
,
3565 save
->gs
.limit
, save
->gs
.base
);
3566 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3568 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3569 save
->gdtr
.limit
, save
->gdtr
.base
);
3570 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3572 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3573 save
->ldtr
.limit
, save
->ldtr
.base
);
3574 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3576 save
->idtr
.selector
, save
->idtr
.attrib
,
3577 save
->idtr
.limit
, save
->idtr
.base
);
3578 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3580 save
->tr
.selector
, save
->tr
.attrib
,
3581 save
->tr
.limit
, save
->tr
.base
);
3582 pr_err("cpl: %d efer: %016llx\n",
3583 save
->cpl
, save
->efer
);
3584 pr_err("%-15s %016llx %-13s %016llx\n",
3585 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3586 pr_err("%-15s %016llx %-13s %016llx\n",
3587 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3588 pr_err("%-15s %016llx %-13s %016llx\n",
3589 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3590 pr_err("%-15s %016llx %-13s %016llx\n",
3591 "rip:", save
->rip
, "rflags:", save
->rflags
);
3592 pr_err("%-15s %016llx %-13s %016llx\n",
3593 "rsp:", save
->rsp
, "rax:", save
->rax
);
3594 pr_err("%-15s %016llx %-13s %016llx\n",
3595 "star:", save
->star
, "lstar:", save
->lstar
);
3596 pr_err("%-15s %016llx %-13s %016llx\n",
3597 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3598 pr_err("%-15s %016llx %-13s %016llx\n",
3599 "kernel_gs_base:", save
->kernel_gs_base
,
3600 "sysenter_cs:", save
->sysenter_cs
);
3601 pr_err("%-15s %016llx %-13s %016llx\n",
3602 "sysenter_esp:", save
->sysenter_esp
,
3603 "sysenter_eip:", save
->sysenter_eip
);
3604 pr_err("%-15s %016llx %-13s %016llx\n",
3605 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3606 pr_err("%-15s %016llx %-13s %016llx\n",
3607 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3608 pr_err("%-15s %016llx %-13s %016llx\n",
3609 "excp_from:", save
->last_excp_from
,
3610 "excp_to:", save
->last_excp_to
);
3613 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3615 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3617 *info1
= control
->exit_info_1
;
3618 *info2
= control
->exit_info_2
;
3621 static int handle_exit(struct kvm_vcpu
*vcpu
)
3623 struct vcpu_svm
*svm
= to_svm(vcpu
);
3624 struct kvm_run
*kvm_run
= vcpu
->run
;
3625 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3627 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3628 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3630 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3632 if (unlikely(svm
->nested
.exit_required
)) {
3633 nested_svm_vmexit(svm
);
3634 svm
->nested
.exit_required
= false;
3639 if (is_guest_mode(vcpu
)) {
3642 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3643 svm
->vmcb
->control
.exit_info_1
,
3644 svm
->vmcb
->control
.exit_info_2
,
3645 svm
->vmcb
->control
.exit_int_info
,
3646 svm
->vmcb
->control
.exit_int_info_err
,
3649 vmexit
= nested_svm_exit_special(svm
);
3651 if (vmexit
== NESTED_EXIT_CONTINUE
)
3652 vmexit
= nested_svm_exit_handled(svm
);
3654 if (vmexit
== NESTED_EXIT_DONE
)
3658 svm_complete_interrupts(svm
);
3660 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3661 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3662 kvm_run
->fail_entry
.hardware_entry_failure_reason
3663 = svm
->vmcb
->control
.exit_code
;
3664 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3669 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3670 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3671 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3672 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3673 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
3675 __func__
, svm
->vmcb
->control
.exit_int_info
,
3678 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3679 || !svm_exit_handlers
[exit_code
]) {
3680 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
3681 kvm_queue_exception(vcpu
, UD_VECTOR
);
3685 return svm_exit_handlers
[exit_code
](svm
);
3688 static void reload_tss(struct kvm_vcpu
*vcpu
)
3690 int cpu
= raw_smp_processor_id();
3692 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3693 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3697 static void pre_svm_run(struct vcpu_svm
*svm
)
3699 int cpu
= raw_smp_processor_id();
3701 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3703 /* FIXME: handle wraparound of asid_generation */
3704 if (svm
->asid_generation
!= sd
->asid_generation
)
3708 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3710 struct vcpu_svm
*svm
= to_svm(vcpu
);
3712 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3713 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3714 set_intercept(svm
, INTERCEPT_IRET
);
3715 ++vcpu
->stat
.nmi_injections
;
3718 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3720 struct vmcb_control_area
*control
;
3722 control
= &svm
->vmcb
->control
;
3723 control
->int_vector
= irq
;
3724 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3725 control
->int_ctl
|= V_IRQ_MASK
|
3726 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3727 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3730 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3732 struct vcpu_svm
*svm
= to_svm(vcpu
);
3734 BUG_ON(!(gif_set(svm
)));
3736 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3737 ++vcpu
->stat
.irq_injections
;
3739 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3740 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3743 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3745 struct vcpu_svm
*svm
= to_svm(vcpu
);
3747 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3750 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3756 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3759 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
3764 static int svm_vm_has_apicv(struct kvm
*kvm
)
3769 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
3774 static void svm_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
3779 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3781 struct vcpu_svm
*svm
= to_svm(vcpu
);
3782 struct vmcb
*vmcb
= svm
->vmcb
;
3784 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3785 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3786 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3791 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3793 struct vcpu_svm
*svm
= to_svm(vcpu
);
3795 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3798 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3800 struct vcpu_svm
*svm
= to_svm(vcpu
);
3803 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3804 set_intercept(svm
, INTERCEPT_IRET
);
3806 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3807 clr_intercept(svm
, INTERCEPT_IRET
);
3811 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3813 struct vcpu_svm
*svm
= to_svm(vcpu
);
3814 struct vmcb
*vmcb
= svm
->vmcb
;
3817 if (!gif_set(svm
) ||
3818 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3821 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
3823 if (is_guest_mode(vcpu
))
3824 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3829 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3831 struct vcpu_svm
*svm
= to_svm(vcpu
);
3834 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3835 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3836 * get that intercept, this function will be called again though and
3837 * we'll get the vintr intercept.
3839 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3841 svm_inject_irq(svm
, 0x0);
3845 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3847 struct vcpu_svm
*svm
= to_svm(vcpu
);
3849 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3851 return; /* IRET will cause a vm exit */
3854 * Something prevents NMI from been injected. Single step over possible
3855 * problem (IRET or exception injection or interrupt shadow)
3857 svm
->nmi_singlestep
= true;
3858 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3859 update_db_bp_intercept(vcpu
);
3862 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3867 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3869 struct vcpu_svm
*svm
= to_svm(vcpu
);
3871 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3872 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3874 svm
->asid_generation
--;
3877 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3881 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3883 struct vcpu_svm
*svm
= to_svm(vcpu
);
3885 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3888 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3889 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3890 kvm_set_cr8(vcpu
, cr8
);
3894 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3896 struct vcpu_svm
*svm
= to_svm(vcpu
);
3899 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3902 cr8
= kvm_get_cr8(vcpu
);
3903 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3904 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3907 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3911 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3912 unsigned int3_injected
= svm
->int3_injected
;
3914 svm
->int3_injected
= 0;
3917 * If we've made progress since setting HF_IRET_MASK, we've
3918 * executed an IRET and can allow NMI injection.
3920 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3921 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
3922 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3923 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3926 svm
->vcpu
.arch
.nmi_injected
= false;
3927 kvm_clear_exception_queue(&svm
->vcpu
);
3928 kvm_clear_interrupt_queue(&svm
->vcpu
);
3930 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3933 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3935 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3936 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3939 case SVM_EXITINTINFO_TYPE_NMI
:
3940 svm
->vcpu
.arch
.nmi_injected
= true;
3942 case SVM_EXITINTINFO_TYPE_EXEPT
:
3944 * In case of software exceptions, do not reinject the vector,
3945 * but re-execute the instruction instead. Rewind RIP first
3946 * if we emulated INT3 before.
3948 if (kvm_exception_is_soft(vector
)) {
3949 if (vector
== BP_VECTOR
&& int3_injected
&&
3950 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3951 kvm_rip_write(&svm
->vcpu
,
3952 kvm_rip_read(&svm
->vcpu
) -
3956 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3957 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3958 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3961 kvm_requeue_exception(&svm
->vcpu
, vector
);
3963 case SVM_EXITINTINFO_TYPE_INTR
:
3964 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3971 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3973 struct vcpu_svm
*svm
= to_svm(vcpu
);
3974 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3976 control
->exit_int_info
= control
->event_inj
;
3977 control
->exit_int_info_err
= control
->event_inj_err
;
3978 control
->event_inj
= 0;
3979 svm_complete_interrupts(svm
);
3982 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3984 struct vcpu_svm
*svm
= to_svm(vcpu
);
3986 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3987 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3988 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3991 * A vmexit emulation is required before the vcpu can be executed
3994 if (unlikely(svm
->nested
.exit_required
))
3999 sync_lapic_to_cr8(vcpu
);
4001 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
4008 "push %%" _ASM_BP
"; \n\t"
4009 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
4010 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
4011 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
4012 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
4013 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
4014 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
4015 #ifdef CONFIG_X86_64
4016 "mov %c[r8](%[svm]), %%r8 \n\t"
4017 "mov %c[r9](%[svm]), %%r9 \n\t"
4018 "mov %c[r10](%[svm]), %%r10 \n\t"
4019 "mov %c[r11](%[svm]), %%r11 \n\t"
4020 "mov %c[r12](%[svm]), %%r12 \n\t"
4021 "mov %c[r13](%[svm]), %%r13 \n\t"
4022 "mov %c[r14](%[svm]), %%r14 \n\t"
4023 "mov %c[r15](%[svm]), %%r15 \n\t"
4026 /* Enter guest mode */
4027 "push %%" _ASM_AX
" \n\t"
4028 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
4029 __ex(SVM_VMLOAD
) "\n\t"
4030 __ex(SVM_VMRUN
) "\n\t"
4031 __ex(SVM_VMSAVE
) "\n\t"
4032 "pop %%" _ASM_AX
" \n\t"
4034 /* Save guest registers, load host registers */
4035 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
4036 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
4037 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
4038 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
4039 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
4040 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
4041 #ifdef CONFIG_X86_64
4042 "mov %%r8, %c[r8](%[svm]) \n\t"
4043 "mov %%r9, %c[r9](%[svm]) \n\t"
4044 "mov %%r10, %c[r10](%[svm]) \n\t"
4045 "mov %%r11, %c[r11](%[svm]) \n\t"
4046 "mov %%r12, %c[r12](%[svm]) \n\t"
4047 "mov %%r13, %c[r13](%[svm]) \n\t"
4048 "mov %%r14, %c[r14](%[svm]) \n\t"
4049 "mov %%r15, %c[r15](%[svm]) \n\t"
4054 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
4055 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4056 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4057 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4058 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4059 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4060 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
4061 #ifdef CONFIG_X86_64
4062 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4063 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4064 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4065 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4066 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4067 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4068 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4069 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
4072 #ifdef CONFIG_X86_64
4073 , "rbx", "rcx", "rdx", "rsi", "rdi"
4074 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4076 , "ebx", "ecx", "edx", "esi", "edi"
4080 #ifdef CONFIG_X86_64
4081 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
4083 loadsegment(fs
, svm
->host
.fs
);
4084 #ifndef CONFIG_X86_32_LAZY_GS
4085 loadsegment(gs
, svm
->host
.gs
);
4091 local_irq_disable();
4093 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
4094 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
4095 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
4096 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
4098 trace_kvm_exit(svm
->vmcb
->control
.exit_code
, vcpu
, KVM_ISA_SVM
);
4100 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
4101 kvm_before_handle_nmi(&svm
->vcpu
);
4105 /* Any pending NMI will happen here */
4107 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
4108 kvm_after_handle_nmi(&svm
->vcpu
);
4110 sync_cr8_to_lapic(vcpu
);
4114 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
4116 /* if exit due to PF check for async PF */
4117 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
4118 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
4121 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
4122 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
4126 * We need to handle MC intercepts here before the vcpu has a chance to
4127 * change the physical cpu
4129 if (unlikely(svm
->vmcb
->control
.exit_code
==
4130 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
4131 svm_handle_mce(svm
);
4133 mark_all_clean(svm
->vmcb
);
4136 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4138 struct vcpu_svm
*svm
= to_svm(vcpu
);
4140 svm
->vmcb
->save
.cr3
= root
;
4141 mark_dirty(svm
->vmcb
, VMCB_CR
);
4142 svm_flush_tlb(vcpu
);
4145 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4147 struct vcpu_svm
*svm
= to_svm(vcpu
);
4149 svm
->vmcb
->control
.nested_cr3
= root
;
4150 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4152 /* Also sync guest cr3 here in case we live migrate */
4153 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
4154 mark_dirty(svm
->vmcb
, VMCB_CR
);
4156 svm_flush_tlb(vcpu
);
4159 static int is_disabled(void)
4163 rdmsrl(MSR_VM_CR
, vm_cr
);
4164 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
4171 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4174 * Patch in the VMMCALL instruction:
4176 hypercall
[0] = 0x0f;
4177 hypercall
[1] = 0x01;
4178 hypercall
[2] = 0xd9;
4181 static void svm_check_processor_compat(void *rtn
)
4186 static bool svm_cpu_has_accelerated_tpr(void)
4191 static bool svm_has_high_real_mode_segbase(void)
4196 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
4200 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4205 entry
->ecx
|= (1 << 2); /* Set SVM bit */
4208 entry
->eax
= 1; /* SVM revision 1 */
4209 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
4210 ASID emulation to nested SVM */
4211 entry
->ecx
= 0; /* Reserved */
4212 entry
->edx
= 0; /* Per default do not support any
4213 additional features */
4215 /* Support next_rip if host supports it */
4216 if (boot_cpu_has(X86_FEATURE_NRIPS
))
4217 entry
->edx
|= SVM_FEATURE_NRIP
;
4219 /* Support NPT for the guest if enabled */
4221 entry
->edx
|= SVM_FEATURE_NPT
;
4227 static int svm_get_lpage_level(void)
4229 return PT_PDPE_LEVEL
;
4232 static bool svm_rdtscp_supported(void)
4237 static bool svm_invpcid_supported(void)
4242 static bool svm_mpx_supported(void)
4247 static bool svm_xsaves_supported(void)
4252 static bool svm_has_wbinvd_exit(void)
4257 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
4259 struct vcpu_svm
*svm
= to_svm(vcpu
);
4261 set_exception_intercept(svm
, NM_VECTOR
);
4262 update_cr0_intercept(svm
);
4265 #define PRE_EX(exit) { .exit_code = (exit), \
4266 .stage = X86_ICPT_PRE_EXCEPT, }
4267 #define POST_EX(exit) { .exit_code = (exit), \
4268 .stage = X86_ICPT_POST_EXCEPT, }
4269 #define POST_MEM(exit) { .exit_code = (exit), \
4270 .stage = X86_ICPT_POST_MEMACCESS, }
4272 static const struct __x86_intercept
{
4274 enum x86_intercept_stage stage
;
4275 } x86_intercept_map
[] = {
4276 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4277 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4278 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4279 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4280 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4281 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4282 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4283 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4284 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4285 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4286 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4287 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4288 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4289 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4290 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4291 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4292 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4293 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4294 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4295 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4296 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4297 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4298 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4299 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4300 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4301 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4302 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4303 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4304 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4305 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4306 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4307 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4308 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4309 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4310 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4311 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4312 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4313 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4314 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4315 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4316 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4317 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4318 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4319 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4320 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4321 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4328 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4329 struct x86_instruction_info
*info
,
4330 enum x86_intercept_stage stage
)
4332 struct vcpu_svm
*svm
= to_svm(vcpu
);
4333 int vmexit
, ret
= X86EMUL_CONTINUE
;
4334 struct __x86_intercept icpt_info
;
4335 struct vmcb
*vmcb
= svm
->vmcb
;
4337 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4340 icpt_info
= x86_intercept_map
[info
->intercept
];
4342 if (stage
!= icpt_info
.stage
)
4345 switch (icpt_info
.exit_code
) {
4346 case SVM_EXIT_READ_CR0
:
4347 if (info
->intercept
== x86_intercept_cr_read
)
4348 icpt_info
.exit_code
+= info
->modrm_reg
;
4350 case SVM_EXIT_WRITE_CR0
: {
4351 unsigned long cr0
, val
;
4354 if (info
->intercept
== x86_intercept_cr_write
)
4355 icpt_info
.exit_code
+= info
->modrm_reg
;
4357 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
4358 info
->intercept
== x86_intercept_clts
)
4361 intercept
= svm
->nested
.intercept
;
4363 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
4366 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4367 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4369 if (info
->intercept
== x86_intercept_lmsw
) {
4372 /* lmsw can't clear PE - catch this here */
4373 if (cr0
& X86_CR0_PE
)
4378 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4382 case SVM_EXIT_READ_DR0
:
4383 case SVM_EXIT_WRITE_DR0
:
4384 icpt_info
.exit_code
+= info
->modrm_reg
;
4387 if (info
->intercept
== x86_intercept_wrmsr
)
4388 vmcb
->control
.exit_info_1
= 1;
4390 vmcb
->control
.exit_info_1
= 0;
4392 case SVM_EXIT_PAUSE
:
4394 * We get this for NOP only, but pause
4395 * is rep not, check this here
4397 if (info
->rep_prefix
!= REPE_PREFIX
)
4399 case SVM_EXIT_IOIO
: {
4403 if (info
->intercept
== x86_intercept_in
||
4404 info
->intercept
== x86_intercept_ins
) {
4405 exit_info
= ((info
->src_val
& 0xffff) << 16) |
4407 bytes
= info
->dst_bytes
;
4409 exit_info
= (info
->dst_val
& 0xffff) << 16;
4410 bytes
= info
->src_bytes
;
4413 if (info
->intercept
== x86_intercept_outs
||
4414 info
->intercept
== x86_intercept_ins
)
4415 exit_info
|= SVM_IOIO_STR_MASK
;
4417 if (info
->rep_prefix
)
4418 exit_info
|= SVM_IOIO_REP_MASK
;
4420 bytes
= min(bytes
, 4u);
4422 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4424 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4426 vmcb
->control
.exit_info_1
= exit_info
;
4427 vmcb
->control
.exit_info_2
= info
->next_rip
;
4435 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4436 if (static_cpu_has(X86_FEATURE_NRIPS
))
4437 vmcb
->control
.next_rip
= info
->next_rip
;
4438 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4439 vmexit
= nested_svm_exit_handled(svm
);
4441 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4448 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
4453 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
4457 static struct kvm_x86_ops svm_x86_ops
= {
4458 .cpu_has_kvm_support
= has_svm
,
4459 .disabled_by_bios
= is_disabled
,
4460 .hardware_setup
= svm_hardware_setup
,
4461 .hardware_unsetup
= svm_hardware_unsetup
,
4462 .check_processor_compatibility
= svm_check_processor_compat
,
4463 .hardware_enable
= svm_hardware_enable
,
4464 .hardware_disable
= svm_hardware_disable
,
4465 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4466 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
4468 .vcpu_create
= svm_create_vcpu
,
4469 .vcpu_free
= svm_free_vcpu
,
4470 .vcpu_reset
= svm_vcpu_reset
,
4472 .prepare_guest_switch
= svm_prepare_guest_switch
,
4473 .vcpu_load
= svm_vcpu_load
,
4474 .vcpu_put
= svm_vcpu_put
,
4476 .update_db_bp_intercept
= update_db_bp_intercept
,
4477 .get_msr
= svm_get_msr
,
4478 .set_msr
= svm_set_msr
,
4479 .get_segment_base
= svm_get_segment_base
,
4480 .get_segment
= svm_get_segment
,
4481 .set_segment
= svm_set_segment
,
4482 .get_cpl
= svm_get_cpl
,
4483 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4484 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
4485 .decache_cr3
= svm_decache_cr3
,
4486 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
4487 .set_cr0
= svm_set_cr0
,
4488 .set_cr3
= svm_set_cr3
,
4489 .set_cr4
= svm_set_cr4
,
4490 .set_efer
= svm_set_efer
,
4491 .get_idt
= svm_get_idt
,
4492 .set_idt
= svm_set_idt
,
4493 .get_gdt
= svm_get_gdt
,
4494 .set_gdt
= svm_set_gdt
,
4495 .get_dr6
= svm_get_dr6
,
4496 .set_dr6
= svm_set_dr6
,
4497 .set_dr7
= svm_set_dr7
,
4498 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
4499 .cache_reg
= svm_cache_reg
,
4500 .get_rflags
= svm_get_rflags
,
4501 .set_rflags
= svm_set_rflags
,
4502 .fpu_activate
= svm_fpu_activate
,
4503 .fpu_deactivate
= svm_fpu_deactivate
,
4505 .tlb_flush
= svm_flush_tlb
,
4507 .run
= svm_vcpu_run
,
4508 .handle_exit
= handle_exit
,
4509 .skip_emulated_instruction
= skip_emulated_instruction
,
4510 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4511 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4512 .patch_hypercall
= svm_patch_hypercall
,
4513 .set_irq
= svm_set_irq
,
4514 .set_nmi
= svm_inject_nmi
,
4515 .queue_exception
= svm_queue_exception
,
4516 .cancel_injection
= svm_cancel_injection
,
4517 .interrupt_allowed
= svm_interrupt_allowed
,
4518 .nmi_allowed
= svm_nmi_allowed
,
4519 .get_nmi_mask
= svm_get_nmi_mask
,
4520 .set_nmi_mask
= svm_set_nmi_mask
,
4521 .enable_nmi_window
= enable_nmi_window
,
4522 .enable_irq_window
= enable_irq_window
,
4523 .update_cr8_intercept
= update_cr8_intercept
,
4524 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
4525 .vm_has_apicv
= svm_vm_has_apicv
,
4526 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
4527 .sync_pir_to_irr
= svm_sync_pir_to_irr
,
4529 .set_tss_addr
= svm_set_tss_addr
,
4530 .get_tdp_level
= get_npt_level
,
4531 .get_mt_mask
= svm_get_mt_mask
,
4533 .get_exit_info
= svm_get_exit_info
,
4535 .get_lpage_level
= svm_get_lpage_level
,
4537 .cpuid_update
= svm_cpuid_update
,
4539 .rdtscp_supported
= svm_rdtscp_supported
,
4540 .invpcid_supported
= svm_invpcid_supported
,
4541 .mpx_supported
= svm_mpx_supported
,
4542 .xsaves_supported
= svm_xsaves_supported
,
4544 .set_supported_cpuid
= svm_set_supported_cpuid
,
4546 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4548 .set_tsc_khz
= svm_set_tsc_khz
,
4549 .read_tsc_offset
= svm_read_tsc_offset
,
4550 .write_tsc_offset
= svm_write_tsc_offset
,
4551 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
4552 .compute_tsc_offset
= svm_compute_tsc_offset
,
4553 .read_l1_tsc
= svm_read_l1_tsc
,
4555 .set_tdp_cr3
= set_tdp_cr3
,
4557 .check_intercept
= svm_check_intercept
,
4558 .handle_external_intr
= svm_handle_external_intr
,
4560 .sched_in
= svm_sched_in
,
4562 .pmu_ops
= &amd_pmu_ops
,
4565 static int __init
svm_init(void)
4567 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
4568 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4571 static void __exit
svm_exit(void)
4576 module_init(svm_init
)
4577 module_exit(svm_exit
)