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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24 #include "pmu.h"
25
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
37 #include <asm/desc.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
40
41 #include <asm/virtext.h>
42 #include "trace.h"
43
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
48
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
51 {}
52 };
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
57
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
60
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
80
81 static bool erratum_383_found __read_mostly;
82
83 static const u32 host_save_user_msrs[] = {
84 #ifdef CONFIG_X86_64
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
86 MSR_FS_BASE,
87 #endif
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
89 };
90
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
92
93 struct kvm_vcpu;
94
95 struct nested_state {
96 struct vmcb *hsave;
97 u64 hsave_msr;
98 u64 vm_cr_msr;
99 u64 vmcb;
100
101 /* These are the merged vectors */
102 u32 *msrpm;
103
104 /* gpa pointers to the real vectors */
105 u64 vmcb_msrpm;
106 u64 vmcb_iopm;
107
108 /* A VMEXIT is required but not yet emulated */
109 bool exit_required;
110
111 /* cache for intercepts of the guest */
112 u32 intercept_cr;
113 u32 intercept_dr;
114 u32 intercept_exceptions;
115 u64 intercept;
116
117 /* Nested Paging related state */
118 u64 nested_cr3;
119 };
120
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
123
124 /*
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
127 */
128 static uint64_t osvw_len = 4, osvw_status;
129
130 struct vcpu_svm {
131 struct kvm_vcpu vcpu;
132 struct vmcb *vmcb;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
138
139 u64 next_rip;
140
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
142 struct {
143 u16 fs;
144 u16 gs;
145 u16 ldt;
146 u64 gs_base;
147 } host;
148
149 u32 *msrpm;
150
151 ulong nmi_iret_rip;
152
153 struct nested_state nested;
154
155 bool nmi_singlestep;
156
157 unsigned int3_injected;
158 unsigned long int3_rip;
159 u32 apf_reason;
160
161 u64 tsc_ratio;
162 };
163
164 static DEFINE_PER_CPU(u64, current_tsc_ratio);
165 #define TSC_RATIO_DEFAULT 0x0100000000ULL
166
167 #define MSR_INVALID 0xffffffffU
168
169 static const struct svm_direct_access_msrs {
170 u32 index; /* Index of the MSR */
171 bool always; /* True if intercept is always on */
172 } direct_access_msrs[] = {
173 { .index = MSR_STAR, .always = true },
174 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175 #ifdef CONFIG_X86_64
176 { .index = MSR_GS_BASE, .always = true },
177 { .index = MSR_FS_BASE, .always = true },
178 { .index = MSR_KERNEL_GS_BASE, .always = true },
179 { .index = MSR_LSTAR, .always = true },
180 { .index = MSR_CSTAR, .always = true },
181 { .index = MSR_SYSCALL_MASK, .always = true },
182 #endif
183 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
184 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
185 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
186 { .index = MSR_IA32_LASTINTTOIP, .always = false },
187 { .index = MSR_INVALID, .always = false },
188 };
189
190 /* enable NPT for AMD64 and X86 with PAE */
191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192 static bool npt_enabled = true;
193 #else
194 static bool npt_enabled;
195 #endif
196
197 /* allow nested paging (virtualized MMU) for all guests */
198 static int npt = true;
199 module_param(npt, int, S_IRUGO);
200
201 /* allow nested virtualization in KVM/SVM */
202 static int nested = true;
203 module_param(nested, int, S_IRUGO);
204
205 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
206 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
207 static void svm_complete_interrupts(struct vcpu_svm *svm);
208
209 static int nested_svm_exit_handled(struct vcpu_svm *svm);
210 static int nested_svm_intercept(struct vcpu_svm *svm);
211 static int nested_svm_vmexit(struct vcpu_svm *svm);
212 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
213 bool has_error_code, u32 error_code);
214 static u64 __scale_tsc(u64 ratio, u64 tsc);
215
216 enum {
217 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
218 pause filter count */
219 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
220 VMCB_ASID, /* ASID */
221 VMCB_INTR, /* int_ctl, int_vector */
222 VMCB_NPT, /* npt_en, nCR3, gPAT */
223 VMCB_CR, /* CR0, CR3, CR4, EFER */
224 VMCB_DR, /* DR6, DR7 */
225 VMCB_DT, /* GDT, IDT */
226 VMCB_SEG, /* CS, DS, SS, ES, CPL */
227 VMCB_CR2, /* CR2 only */
228 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
229 VMCB_DIRTY_MAX,
230 };
231
232 /* TPR and CR2 are always written before VMRUN */
233 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
234
235 static inline void mark_all_dirty(struct vmcb *vmcb)
236 {
237 vmcb->control.clean = 0;
238 }
239
240 static inline void mark_all_clean(struct vmcb *vmcb)
241 {
242 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
243 & ~VMCB_ALWAYS_DIRTY_MASK;
244 }
245
246 static inline void mark_dirty(struct vmcb *vmcb, int bit)
247 {
248 vmcb->control.clean &= ~(1 << bit);
249 }
250
251 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
252 {
253 return container_of(vcpu, struct vcpu_svm, vcpu);
254 }
255
256 static void recalc_intercepts(struct vcpu_svm *svm)
257 {
258 struct vmcb_control_area *c, *h;
259 struct nested_state *g;
260
261 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
262
263 if (!is_guest_mode(&svm->vcpu))
264 return;
265
266 c = &svm->vmcb->control;
267 h = &svm->nested.hsave->control;
268 g = &svm->nested;
269
270 c->intercept_cr = h->intercept_cr | g->intercept_cr;
271 c->intercept_dr = h->intercept_dr | g->intercept_dr;
272 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
273 c->intercept = h->intercept | g->intercept;
274 }
275
276 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
277 {
278 if (is_guest_mode(&svm->vcpu))
279 return svm->nested.hsave;
280 else
281 return svm->vmcb;
282 }
283
284 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
285 {
286 struct vmcb *vmcb = get_host_vmcb(svm);
287
288 vmcb->control.intercept_cr |= (1U << bit);
289
290 recalc_intercepts(svm);
291 }
292
293 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
294 {
295 struct vmcb *vmcb = get_host_vmcb(svm);
296
297 vmcb->control.intercept_cr &= ~(1U << bit);
298
299 recalc_intercepts(svm);
300 }
301
302 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
303 {
304 struct vmcb *vmcb = get_host_vmcb(svm);
305
306 return vmcb->control.intercept_cr & (1U << bit);
307 }
308
309 static inline void set_dr_intercepts(struct vcpu_svm *svm)
310 {
311 struct vmcb *vmcb = get_host_vmcb(svm);
312
313 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
314 | (1 << INTERCEPT_DR1_READ)
315 | (1 << INTERCEPT_DR2_READ)
316 | (1 << INTERCEPT_DR3_READ)
317 | (1 << INTERCEPT_DR4_READ)
318 | (1 << INTERCEPT_DR5_READ)
319 | (1 << INTERCEPT_DR6_READ)
320 | (1 << INTERCEPT_DR7_READ)
321 | (1 << INTERCEPT_DR0_WRITE)
322 | (1 << INTERCEPT_DR1_WRITE)
323 | (1 << INTERCEPT_DR2_WRITE)
324 | (1 << INTERCEPT_DR3_WRITE)
325 | (1 << INTERCEPT_DR4_WRITE)
326 | (1 << INTERCEPT_DR5_WRITE)
327 | (1 << INTERCEPT_DR6_WRITE)
328 | (1 << INTERCEPT_DR7_WRITE);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
334 {
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_dr = 0;
338
339 recalc_intercepts(svm);
340 }
341
342 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
343 {
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept_exceptions |= (1U << bit);
347
348 recalc_intercepts(svm);
349 }
350
351 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
352 {
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept_exceptions &= ~(1U << bit);
356
357 recalc_intercepts(svm);
358 }
359
360 static inline void set_intercept(struct vcpu_svm *svm, int bit)
361 {
362 struct vmcb *vmcb = get_host_vmcb(svm);
363
364 vmcb->control.intercept |= (1ULL << bit);
365
366 recalc_intercepts(svm);
367 }
368
369 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
370 {
371 struct vmcb *vmcb = get_host_vmcb(svm);
372
373 vmcb->control.intercept &= ~(1ULL << bit);
374
375 recalc_intercepts(svm);
376 }
377
378 static inline void enable_gif(struct vcpu_svm *svm)
379 {
380 svm->vcpu.arch.hflags |= HF_GIF_MASK;
381 }
382
383 static inline void disable_gif(struct vcpu_svm *svm)
384 {
385 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
386 }
387
388 static inline bool gif_set(struct vcpu_svm *svm)
389 {
390 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
391 }
392
393 static unsigned long iopm_base;
394
395 struct kvm_ldttss_desc {
396 u16 limit0;
397 u16 base0;
398 unsigned base1:8, type:5, dpl:2, p:1;
399 unsigned limit1:4, zero0:3, g:1, base2:8;
400 u32 base3;
401 u32 zero1;
402 } __attribute__((packed));
403
404 struct svm_cpu_data {
405 int cpu;
406
407 u64 asid_generation;
408 u32 max_asid;
409 u32 next_asid;
410 struct kvm_ldttss_desc *tss_desc;
411
412 struct page *save_area;
413 };
414
415 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
416
417 struct svm_init_data {
418 int cpu;
419 int r;
420 };
421
422 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
423
424 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
425 #define MSRS_RANGE_SIZE 2048
426 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
427
428 static u32 svm_msrpm_offset(u32 msr)
429 {
430 u32 offset;
431 int i;
432
433 for (i = 0; i < NUM_MSR_MAPS; i++) {
434 if (msr < msrpm_ranges[i] ||
435 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
436 continue;
437
438 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
439 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
440
441 /* Now we have the u8 offset - but need the u32 offset */
442 return offset / 4;
443 }
444
445 /* MSR not in any range */
446 return MSR_INVALID;
447 }
448
449 #define MAX_INST_SIZE 15
450
451 static inline void clgi(void)
452 {
453 asm volatile (__ex(SVM_CLGI));
454 }
455
456 static inline void stgi(void)
457 {
458 asm volatile (__ex(SVM_STGI));
459 }
460
461 static inline void invlpga(unsigned long addr, u32 asid)
462 {
463 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
464 }
465
466 static int get_npt_level(void)
467 {
468 #ifdef CONFIG_X86_64
469 return PT64_ROOT_LEVEL;
470 #else
471 return PT32E_ROOT_LEVEL;
472 #endif
473 }
474
475 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
476 {
477 vcpu->arch.efer = efer;
478 if (!npt_enabled && !(efer & EFER_LMA))
479 efer &= ~EFER_LME;
480
481 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
482 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
483 }
484
485 static int is_external_interrupt(u32 info)
486 {
487 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
488 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
489 }
490
491 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
492 {
493 struct vcpu_svm *svm = to_svm(vcpu);
494 u32 ret = 0;
495
496 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
497 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
498 return ret;
499 }
500
501 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
502 {
503 struct vcpu_svm *svm = to_svm(vcpu);
504
505 if (mask == 0)
506 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
507 else
508 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
509
510 }
511
512 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
513 {
514 struct vcpu_svm *svm = to_svm(vcpu);
515
516 if (svm->vmcb->control.next_rip != 0) {
517 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS));
518 svm->next_rip = svm->vmcb->control.next_rip;
519 }
520
521 if (!svm->next_rip) {
522 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
523 EMULATE_DONE)
524 printk(KERN_DEBUG "%s: NOP\n", __func__);
525 return;
526 }
527 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
528 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
529 __func__, kvm_rip_read(vcpu), svm->next_rip);
530
531 kvm_rip_write(vcpu, svm->next_rip);
532 svm_set_interrupt_shadow(vcpu, 0);
533 }
534
535 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
536 bool has_error_code, u32 error_code,
537 bool reinject)
538 {
539 struct vcpu_svm *svm = to_svm(vcpu);
540
541 /*
542 * If we are within a nested VM we'd better #VMEXIT and let the guest
543 * handle the exception
544 */
545 if (!reinject &&
546 nested_svm_check_exception(svm, nr, has_error_code, error_code))
547 return;
548
549 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
550 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
551
552 /*
553 * For guest debugging where we have to reinject #BP if some
554 * INT3 is guest-owned:
555 * Emulate nRIP by moving RIP forward. Will fail if injection
556 * raises a fault that is not intercepted. Still better than
557 * failing in all cases.
558 */
559 skip_emulated_instruction(&svm->vcpu);
560 rip = kvm_rip_read(&svm->vcpu);
561 svm->int3_rip = rip + svm->vmcb->save.cs.base;
562 svm->int3_injected = rip - old_rip;
563 }
564
565 svm->vmcb->control.event_inj = nr
566 | SVM_EVTINJ_VALID
567 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
568 | SVM_EVTINJ_TYPE_EXEPT;
569 svm->vmcb->control.event_inj_err = error_code;
570 }
571
572 static void svm_init_erratum_383(void)
573 {
574 u32 low, high;
575 int err;
576 u64 val;
577
578 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
579 return;
580
581 /* Use _safe variants to not break nested virtualization */
582 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
583 if (err)
584 return;
585
586 val |= (1ULL << 47);
587
588 low = lower_32_bits(val);
589 high = upper_32_bits(val);
590
591 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
592
593 erratum_383_found = true;
594 }
595
596 static void svm_init_osvw(struct kvm_vcpu *vcpu)
597 {
598 /*
599 * Guests should see errata 400 and 415 as fixed (assuming that
600 * HLT and IO instructions are intercepted).
601 */
602 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
603 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
604
605 /*
606 * By increasing VCPU's osvw.length to 3 we are telling the guest that
607 * all osvw.status bits inside that length, including bit 0 (which is
608 * reserved for erratum 298), are valid. However, if host processor's
609 * osvw_len is 0 then osvw_status[0] carries no information. We need to
610 * be conservative here and therefore we tell the guest that erratum 298
611 * is present (because we really don't know).
612 */
613 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
614 vcpu->arch.osvw.status |= 1;
615 }
616
617 static int has_svm(void)
618 {
619 const char *msg;
620
621 if (!cpu_has_svm(&msg)) {
622 printk(KERN_INFO "has_svm: %s\n", msg);
623 return 0;
624 }
625
626 return 1;
627 }
628
629 static void svm_hardware_disable(void)
630 {
631 /* Make sure we clean up behind us */
632 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
633 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
634
635 cpu_svm_disable();
636
637 amd_pmu_disable_virt();
638 }
639
640 static int svm_hardware_enable(void)
641 {
642
643 struct svm_cpu_data *sd;
644 uint64_t efer;
645 struct desc_ptr gdt_descr;
646 struct desc_struct *gdt;
647 int me = raw_smp_processor_id();
648
649 rdmsrl(MSR_EFER, efer);
650 if (efer & EFER_SVME)
651 return -EBUSY;
652
653 if (!has_svm()) {
654 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
655 return -EINVAL;
656 }
657 sd = per_cpu(svm_data, me);
658 if (!sd) {
659 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
660 return -EINVAL;
661 }
662
663 sd->asid_generation = 1;
664 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
665 sd->next_asid = sd->max_asid + 1;
666
667 native_store_gdt(&gdt_descr);
668 gdt = (struct desc_struct *)gdt_descr.address;
669 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
670
671 wrmsrl(MSR_EFER, efer | EFER_SVME);
672
673 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
674
675 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
676 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
677 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
678 }
679
680
681 /*
682 * Get OSVW bits.
683 *
684 * Note that it is possible to have a system with mixed processor
685 * revisions and therefore different OSVW bits. If bits are not the same
686 * on different processors then choose the worst case (i.e. if erratum
687 * is present on one processor and not on another then assume that the
688 * erratum is present everywhere).
689 */
690 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
691 uint64_t len, status = 0;
692 int err;
693
694 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
695 if (!err)
696 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
697 &err);
698
699 if (err)
700 osvw_status = osvw_len = 0;
701 else {
702 if (len < osvw_len)
703 osvw_len = len;
704 osvw_status |= status;
705 osvw_status &= (1ULL << osvw_len) - 1;
706 }
707 } else
708 osvw_status = osvw_len = 0;
709
710 svm_init_erratum_383();
711
712 amd_pmu_enable_virt();
713
714 return 0;
715 }
716
717 static void svm_cpu_uninit(int cpu)
718 {
719 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
720
721 if (!sd)
722 return;
723
724 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
725 __free_page(sd->save_area);
726 kfree(sd);
727 }
728
729 static int svm_cpu_init(int cpu)
730 {
731 struct svm_cpu_data *sd;
732 int r;
733
734 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
735 if (!sd)
736 return -ENOMEM;
737 sd->cpu = cpu;
738 sd->save_area = alloc_page(GFP_KERNEL);
739 r = -ENOMEM;
740 if (!sd->save_area)
741 goto err_1;
742
743 per_cpu(svm_data, cpu) = sd;
744
745 return 0;
746
747 err_1:
748 kfree(sd);
749 return r;
750
751 }
752
753 static bool valid_msr_intercept(u32 index)
754 {
755 int i;
756
757 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
758 if (direct_access_msrs[i].index == index)
759 return true;
760
761 return false;
762 }
763
764 static void set_msr_interception(u32 *msrpm, unsigned msr,
765 int read, int write)
766 {
767 u8 bit_read, bit_write;
768 unsigned long tmp;
769 u32 offset;
770
771 /*
772 * If this warning triggers extend the direct_access_msrs list at the
773 * beginning of the file
774 */
775 WARN_ON(!valid_msr_intercept(msr));
776
777 offset = svm_msrpm_offset(msr);
778 bit_read = 2 * (msr & 0x0f);
779 bit_write = 2 * (msr & 0x0f) + 1;
780 tmp = msrpm[offset];
781
782 BUG_ON(offset == MSR_INVALID);
783
784 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
785 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
786
787 msrpm[offset] = tmp;
788 }
789
790 static void svm_vcpu_init_msrpm(u32 *msrpm)
791 {
792 int i;
793
794 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
795
796 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
797 if (!direct_access_msrs[i].always)
798 continue;
799
800 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
801 }
802 }
803
804 static void add_msr_offset(u32 offset)
805 {
806 int i;
807
808 for (i = 0; i < MSRPM_OFFSETS; ++i) {
809
810 /* Offset already in list? */
811 if (msrpm_offsets[i] == offset)
812 return;
813
814 /* Slot used by another offset? */
815 if (msrpm_offsets[i] != MSR_INVALID)
816 continue;
817
818 /* Add offset to list */
819 msrpm_offsets[i] = offset;
820
821 return;
822 }
823
824 /*
825 * If this BUG triggers the msrpm_offsets table has an overflow. Just
826 * increase MSRPM_OFFSETS in this case.
827 */
828 BUG();
829 }
830
831 static void init_msrpm_offsets(void)
832 {
833 int i;
834
835 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
836
837 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
838 u32 offset;
839
840 offset = svm_msrpm_offset(direct_access_msrs[i].index);
841 BUG_ON(offset == MSR_INVALID);
842
843 add_msr_offset(offset);
844 }
845 }
846
847 static void svm_enable_lbrv(struct vcpu_svm *svm)
848 {
849 u32 *msrpm = svm->msrpm;
850
851 svm->vmcb->control.lbr_ctl = 1;
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
855 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
856 }
857
858 static void svm_disable_lbrv(struct vcpu_svm *svm)
859 {
860 u32 *msrpm = svm->msrpm;
861
862 svm->vmcb->control.lbr_ctl = 0;
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
866 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
867 }
868
869 #define MTRR_TYPE_UC_MINUS 7
870 #define MTRR2PROTVAL_INVALID 0xff
871
872 static u8 mtrr2protval[8];
873
874 static u8 fallback_mtrr_type(int mtrr)
875 {
876 /*
877 * WT and WP aren't always available in the host PAT. Treat
878 * them as UC and UC- respectively. Everything else should be
879 * there.
880 */
881 switch (mtrr)
882 {
883 case MTRR_TYPE_WRTHROUGH:
884 return MTRR_TYPE_UNCACHABLE;
885 case MTRR_TYPE_WRPROT:
886 return MTRR_TYPE_UC_MINUS;
887 default:
888 BUG();
889 }
890 }
891
892 static void build_mtrr2protval(void)
893 {
894 int i;
895 u64 pat;
896
897 for (i = 0; i < 8; i++)
898 mtrr2protval[i] = MTRR2PROTVAL_INVALID;
899
900 /* Ignore the invalid MTRR types. */
901 mtrr2protval[2] = 0;
902 mtrr2protval[3] = 0;
903
904 /*
905 * Use host PAT value to figure out the mapping from guest MTRR
906 * values to nested page table PAT/PCD/PWT values. We do not
907 * want to change the host PAT value every time we enter the
908 * guest.
909 */
910 rdmsrl(MSR_IA32_CR_PAT, pat);
911 for (i = 0; i < 8; i++) {
912 u8 mtrr = pat >> (8 * i);
913
914 if (mtrr2protval[mtrr] == MTRR2PROTVAL_INVALID)
915 mtrr2protval[mtrr] = __cm_idx2pte(i);
916 }
917
918 for (i = 0; i < 8; i++) {
919 if (mtrr2protval[i] == MTRR2PROTVAL_INVALID) {
920 u8 fallback = fallback_mtrr_type(i);
921 mtrr2protval[i] = mtrr2protval[fallback];
922 BUG_ON(mtrr2protval[i] == MTRR2PROTVAL_INVALID);
923 }
924 }
925 }
926
927 static __init int svm_hardware_setup(void)
928 {
929 int cpu;
930 struct page *iopm_pages;
931 void *iopm_va;
932 int r;
933
934 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
935
936 if (!iopm_pages)
937 return -ENOMEM;
938
939 iopm_va = page_address(iopm_pages);
940 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
941 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
942
943 init_msrpm_offsets();
944
945 if (boot_cpu_has(X86_FEATURE_NX))
946 kvm_enable_efer_bits(EFER_NX);
947
948 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
949 kvm_enable_efer_bits(EFER_FFXSR);
950
951 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
952 u64 max;
953
954 kvm_has_tsc_control = true;
955
956 /*
957 * Make sure the user can only configure tsc_khz values that
958 * fit into a signed integer.
959 * A min value is not calculated needed because it will always
960 * be 1 on all machines and a value of 0 is used to disable
961 * tsc-scaling for the vcpu.
962 */
963 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
964
965 kvm_max_guest_tsc_khz = max;
966 }
967
968 if (nested) {
969 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
970 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
971 }
972
973 for_each_possible_cpu(cpu) {
974 r = svm_cpu_init(cpu);
975 if (r)
976 goto err;
977 }
978
979 if (!boot_cpu_has(X86_FEATURE_NPT))
980 npt_enabled = false;
981
982 if (npt_enabled && !npt) {
983 printk(KERN_INFO "kvm: Nested Paging disabled\n");
984 npt_enabled = false;
985 }
986
987 if (npt_enabled) {
988 printk(KERN_INFO "kvm: Nested Paging enabled\n");
989 kvm_enable_tdp();
990 } else
991 kvm_disable_tdp();
992
993 build_mtrr2protval();
994 return 0;
995
996 err:
997 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
998 iopm_base = 0;
999 return r;
1000 }
1001
1002 static __exit void svm_hardware_unsetup(void)
1003 {
1004 int cpu;
1005
1006 for_each_possible_cpu(cpu)
1007 svm_cpu_uninit(cpu);
1008
1009 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1010 iopm_base = 0;
1011 }
1012
1013 static void init_seg(struct vmcb_seg *seg)
1014 {
1015 seg->selector = 0;
1016 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1017 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1018 seg->limit = 0xffff;
1019 seg->base = 0;
1020 }
1021
1022 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1023 {
1024 seg->selector = 0;
1025 seg->attrib = SVM_SELECTOR_P_MASK | type;
1026 seg->limit = 0xffff;
1027 seg->base = 0;
1028 }
1029
1030 static u64 __scale_tsc(u64 ratio, u64 tsc)
1031 {
1032 u64 mult, frac, _tsc;
1033
1034 mult = ratio >> 32;
1035 frac = ratio & ((1ULL << 32) - 1);
1036
1037 _tsc = tsc;
1038 _tsc *= mult;
1039 _tsc += (tsc >> 32) * frac;
1040 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
1041
1042 return _tsc;
1043 }
1044
1045 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1046 {
1047 struct vcpu_svm *svm = to_svm(vcpu);
1048 u64 _tsc = tsc;
1049
1050 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1051 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
1052
1053 return _tsc;
1054 }
1055
1056 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1057 {
1058 struct vcpu_svm *svm = to_svm(vcpu);
1059 u64 ratio;
1060 u64 khz;
1061
1062 /* Guest TSC same frequency as host TSC? */
1063 if (!scale) {
1064 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1065 return;
1066 }
1067
1068 /* TSC scaling supported? */
1069 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1070 if (user_tsc_khz > tsc_khz) {
1071 vcpu->arch.tsc_catchup = 1;
1072 vcpu->arch.tsc_always_catchup = 1;
1073 } else
1074 WARN(1, "user requested TSC rate below hardware speed\n");
1075 return;
1076 }
1077
1078 khz = user_tsc_khz;
1079
1080 /* TSC scaling required - calculate ratio */
1081 ratio = khz << 32;
1082 do_div(ratio, tsc_khz);
1083
1084 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1085 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1086 user_tsc_khz);
1087 return;
1088 }
1089 svm->tsc_ratio = ratio;
1090 }
1091
1092 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1093 {
1094 struct vcpu_svm *svm = to_svm(vcpu);
1095
1096 return svm->vmcb->control.tsc_offset;
1097 }
1098
1099 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1100 {
1101 struct vcpu_svm *svm = to_svm(vcpu);
1102 u64 g_tsc_offset = 0;
1103
1104 if (is_guest_mode(vcpu)) {
1105 g_tsc_offset = svm->vmcb->control.tsc_offset -
1106 svm->nested.hsave->control.tsc_offset;
1107 svm->nested.hsave->control.tsc_offset = offset;
1108 } else
1109 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1110 svm->vmcb->control.tsc_offset,
1111 offset);
1112
1113 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1114
1115 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1116 }
1117
1118 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1119 {
1120 struct vcpu_svm *svm = to_svm(vcpu);
1121
1122 if (host) {
1123 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1124 WARN_ON(adjustment < 0);
1125 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1126 }
1127
1128 svm->vmcb->control.tsc_offset += adjustment;
1129 if (is_guest_mode(vcpu))
1130 svm->nested.hsave->control.tsc_offset += adjustment;
1131 else
1132 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1133 svm->vmcb->control.tsc_offset - adjustment,
1134 svm->vmcb->control.tsc_offset);
1135
1136 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1137 }
1138
1139 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1140 {
1141 u64 tsc;
1142
1143 tsc = svm_scale_tsc(vcpu, rdtsc());
1144
1145 return target_tsc - tsc;
1146 }
1147
1148 static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
1149 {
1150 struct kvm_vcpu *vcpu = &svm->vcpu;
1151
1152 /* Unlike Intel, AMD takes the guest's CR0.CD into account.
1153 *
1154 * AMD does not have IPAT. To emulate it for the case of guests
1155 * with no assigned devices, just set everything to WB. If guests
1156 * have assigned devices, however, we cannot force WB for RAM
1157 * pages only, so use the guest PAT directly.
1158 */
1159 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1160 *g_pat = 0x0606060606060606;
1161 else
1162 *g_pat = vcpu->arch.pat;
1163 }
1164
1165 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
1166 {
1167 u8 mtrr;
1168
1169 /*
1170 * 1. MMIO: trust guest MTRR, so same as item 3.
1171 * 2. No passthrough: always map as WB, and force guest PAT to WB as well
1172 * 3. Passthrough: can't guarantee the result, try to trust guest.
1173 */
1174 if (!is_mmio && !kvm_arch_has_assigned_device(vcpu->kvm))
1175 return 0;
1176
1177 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED) &&
1178 kvm_read_cr0(vcpu) & X86_CR0_CD)
1179 return _PAGE_NOCACHE;
1180
1181 mtrr = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
1182 return mtrr2protval[mtrr];
1183 }
1184
1185 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1186 {
1187 struct vmcb_control_area *control = &svm->vmcb->control;
1188 struct vmcb_save_area *save = &svm->vmcb->save;
1189
1190 svm->vcpu.fpu_active = 1;
1191 svm->vcpu.arch.hflags = 0;
1192
1193 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1194 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1195 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1196 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1197 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1198 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1199 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1200
1201 set_dr_intercepts(svm);
1202
1203 set_exception_intercept(svm, PF_VECTOR);
1204 set_exception_intercept(svm, UD_VECTOR);
1205 set_exception_intercept(svm, MC_VECTOR);
1206
1207 set_intercept(svm, INTERCEPT_INTR);
1208 set_intercept(svm, INTERCEPT_NMI);
1209 set_intercept(svm, INTERCEPT_SMI);
1210 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1211 set_intercept(svm, INTERCEPT_RDPMC);
1212 set_intercept(svm, INTERCEPT_CPUID);
1213 set_intercept(svm, INTERCEPT_INVD);
1214 set_intercept(svm, INTERCEPT_HLT);
1215 set_intercept(svm, INTERCEPT_INVLPG);
1216 set_intercept(svm, INTERCEPT_INVLPGA);
1217 set_intercept(svm, INTERCEPT_IOIO_PROT);
1218 set_intercept(svm, INTERCEPT_MSR_PROT);
1219 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1220 set_intercept(svm, INTERCEPT_SHUTDOWN);
1221 set_intercept(svm, INTERCEPT_VMRUN);
1222 set_intercept(svm, INTERCEPT_VMMCALL);
1223 set_intercept(svm, INTERCEPT_VMLOAD);
1224 set_intercept(svm, INTERCEPT_VMSAVE);
1225 set_intercept(svm, INTERCEPT_STGI);
1226 set_intercept(svm, INTERCEPT_CLGI);
1227 set_intercept(svm, INTERCEPT_SKINIT);
1228 set_intercept(svm, INTERCEPT_WBINVD);
1229 set_intercept(svm, INTERCEPT_MONITOR);
1230 set_intercept(svm, INTERCEPT_MWAIT);
1231 set_intercept(svm, INTERCEPT_XSETBV);
1232
1233 control->iopm_base_pa = iopm_base;
1234 control->msrpm_base_pa = __pa(svm->msrpm);
1235 control->int_ctl = V_INTR_MASKING_MASK;
1236
1237 init_seg(&save->es);
1238 init_seg(&save->ss);
1239 init_seg(&save->ds);
1240 init_seg(&save->fs);
1241 init_seg(&save->gs);
1242
1243 save->cs.selector = 0xf000;
1244 save->cs.base = 0xffff0000;
1245 /* Executable/Readable Code Segment */
1246 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1247 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1248 save->cs.limit = 0xffff;
1249
1250 save->gdtr.limit = 0xffff;
1251 save->idtr.limit = 0xffff;
1252
1253 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1254 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1255
1256 if (!init_event)
1257 svm_set_efer(&svm->vcpu, 0);
1258 save->dr6 = 0xffff0ff0;
1259 kvm_set_rflags(&svm->vcpu, 2);
1260 save->rip = 0x0000fff0;
1261 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1262
1263 /*
1264 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1265 * It also updates the guest-visible cr0 value.
1266 */
1267 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1268 kvm_mmu_reset_context(&svm->vcpu);
1269
1270 save->cr4 = X86_CR4_PAE;
1271 /* rdx = ?? */
1272
1273 if (npt_enabled) {
1274 /* Setup VMCB for Nested Paging */
1275 control->nested_ctl = 1;
1276 clr_intercept(svm, INTERCEPT_INVLPG);
1277 clr_exception_intercept(svm, PF_VECTOR);
1278 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1279 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1280 save->g_pat = svm->vcpu.arch.pat;
1281 svm_set_guest_pat(svm, &save->g_pat);
1282 save->cr3 = 0;
1283 save->cr4 = 0;
1284 }
1285 svm->asid_generation = 0;
1286
1287 svm->nested.vmcb = 0;
1288 svm->vcpu.arch.hflags = 0;
1289
1290 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1291 control->pause_filter_count = 3000;
1292 set_intercept(svm, INTERCEPT_PAUSE);
1293 }
1294
1295 mark_all_dirty(svm->vmcb);
1296
1297 enable_gif(svm);
1298 }
1299
1300 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1301 {
1302 struct vcpu_svm *svm = to_svm(vcpu);
1303 u32 dummy;
1304 u32 eax = 1;
1305
1306 if (!init_event) {
1307 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1308 MSR_IA32_APICBASE_ENABLE;
1309 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1310 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1311 }
1312 init_vmcb(svm, init_event);
1313
1314 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1315 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1316 }
1317
1318 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1319 {
1320 struct vcpu_svm *svm;
1321 struct page *page;
1322 struct page *msrpm_pages;
1323 struct page *hsave_page;
1324 struct page *nested_msrpm_pages;
1325 int err;
1326
1327 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1328 if (!svm) {
1329 err = -ENOMEM;
1330 goto out;
1331 }
1332
1333 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1334
1335 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1336 if (err)
1337 goto free_svm;
1338
1339 err = -ENOMEM;
1340 page = alloc_page(GFP_KERNEL);
1341 if (!page)
1342 goto uninit;
1343
1344 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1345 if (!msrpm_pages)
1346 goto free_page1;
1347
1348 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1349 if (!nested_msrpm_pages)
1350 goto free_page2;
1351
1352 hsave_page = alloc_page(GFP_KERNEL);
1353 if (!hsave_page)
1354 goto free_page3;
1355
1356 svm->nested.hsave = page_address(hsave_page);
1357
1358 svm->msrpm = page_address(msrpm_pages);
1359 svm_vcpu_init_msrpm(svm->msrpm);
1360
1361 svm->nested.msrpm = page_address(nested_msrpm_pages);
1362 svm_vcpu_init_msrpm(svm->nested.msrpm);
1363
1364 svm->vmcb = page_address(page);
1365 clear_page(svm->vmcb);
1366 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1367 svm->asid_generation = 0;
1368 init_vmcb(svm, false);
1369
1370 svm_init_osvw(&svm->vcpu);
1371
1372 return &svm->vcpu;
1373
1374 free_page3:
1375 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1376 free_page2:
1377 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1378 free_page1:
1379 __free_page(page);
1380 uninit:
1381 kvm_vcpu_uninit(&svm->vcpu);
1382 free_svm:
1383 kmem_cache_free(kvm_vcpu_cache, svm);
1384 out:
1385 return ERR_PTR(err);
1386 }
1387
1388 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1389 {
1390 struct vcpu_svm *svm = to_svm(vcpu);
1391
1392 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1393 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1394 __free_page(virt_to_page(svm->nested.hsave));
1395 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1396 kvm_vcpu_uninit(vcpu);
1397 kmem_cache_free(kvm_vcpu_cache, svm);
1398 }
1399
1400 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1401 {
1402 struct vcpu_svm *svm = to_svm(vcpu);
1403 int i;
1404
1405 if (unlikely(cpu != vcpu->cpu)) {
1406 svm->asid_generation = 0;
1407 mark_all_dirty(svm->vmcb);
1408 }
1409
1410 #ifdef CONFIG_X86_64
1411 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1412 #endif
1413 savesegment(fs, svm->host.fs);
1414 savesegment(gs, svm->host.gs);
1415 svm->host.ldt = kvm_read_ldt();
1416
1417 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1418 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1419
1420 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1421 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1422 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1423 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1424 }
1425 }
1426
1427 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1428 {
1429 struct vcpu_svm *svm = to_svm(vcpu);
1430 int i;
1431
1432 ++vcpu->stat.host_state_reload;
1433 kvm_load_ldt(svm->host.ldt);
1434 #ifdef CONFIG_X86_64
1435 loadsegment(fs, svm->host.fs);
1436 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1437 load_gs_index(svm->host.gs);
1438 #else
1439 #ifdef CONFIG_X86_32_LAZY_GS
1440 loadsegment(gs, svm->host.gs);
1441 #endif
1442 #endif
1443 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1444 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1445 }
1446
1447 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1448 {
1449 return to_svm(vcpu)->vmcb->save.rflags;
1450 }
1451
1452 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1453 {
1454 /*
1455 * Any change of EFLAGS.VM is accompained by a reload of SS
1456 * (caused by either a task switch or an inter-privilege IRET),
1457 * so we do not need to update the CPL here.
1458 */
1459 to_svm(vcpu)->vmcb->save.rflags = rflags;
1460 }
1461
1462 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1463 {
1464 switch (reg) {
1465 case VCPU_EXREG_PDPTR:
1466 BUG_ON(!npt_enabled);
1467 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1468 break;
1469 default:
1470 BUG();
1471 }
1472 }
1473
1474 static void svm_set_vintr(struct vcpu_svm *svm)
1475 {
1476 set_intercept(svm, INTERCEPT_VINTR);
1477 }
1478
1479 static void svm_clear_vintr(struct vcpu_svm *svm)
1480 {
1481 clr_intercept(svm, INTERCEPT_VINTR);
1482 }
1483
1484 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1485 {
1486 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1487
1488 switch (seg) {
1489 case VCPU_SREG_CS: return &save->cs;
1490 case VCPU_SREG_DS: return &save->ds;
1491 case VCPU_SREG_ES: return &save->es;
1492 case VCPU_SREG_FS: return &save->fs;
1493 case VCPU_SREG_GS: return &save->gs;
1494 case VCPU_SREG_SS: return &save->ss;
1495 case VCPU_SREG_TR: return &save->tr;
1496 case VCPU_SREG_LDTR: return &save->ldtr;
1497 }
1498 BUG();
1499 return NULL;
1500 }
1501
1502 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1503 {
1504 struct vmcb_seg *s = svm_seg(vcpu, seg);
1505
1506 return s->base;
1507 }
1508
1509 static void svm_get_segment(struct kvm_vcpu *vcpu,
1510 struct kvm_segment *var, int seg)
1511 {
1512 struct vmcb_seg *s = svm_seg(vcpu, seg);
1513
1514 var->base = s->base;
1515 var->limit = s->limit;
1516 var->selector = s->selector;
1517 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1518 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1519 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1520 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1521 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1522 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1523 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1524
1525 /*
1526 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1527 * However, the SVM spec states that the G bit is not observed by the
1528 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1529 * So let's synthesize a legal G bit for all segments, this helps
1530 * running KVM nested. It also helps cross-vendor migration, because
1531 * Intel's vmentry has a check on the 'G' bit.
1532 */
1533 var->g = s->limit > 0xfffff;
1534
1535 /*
1536 * AMD's VMCB does not have an explicit unusable field, so emulate it
1537 * for cross vendor migration purposes by "not present"
1538 */
1539 var->unusable = !var->present || (var->type == 0);
1540
1541 switch (seg) {
1542 case VCPU_SREG_TR:
1543 /*
1544 * Work around a bug where the busy flag in the tr selector
1545 * isn't exposed
1546 */
1547 var->type |= 0x2;
1548 break;
1549 case VCPU_SREG_DS:
1550 case VCPU_SREG_ES:
1551 case VCPU_SREG_FS:
1552 case VCPU_SREG_GS:
1553 /*
1554 * The accessed bit must always be set in the segment
1555 * descriptor cache, although it can be cleared in the
1556 * descriptor, the cached bit always remains at 1. Since
1557 * Intel has a check on this, set it here to support
1558 * cross-vendor migration.
1559 */
1560 if (!var->unusable)
1561 var->type |= 0x1;
1562 break;
1563 case VCPU_SREG_SS:
1564 /*
1565 * On AMD CPUs sometimes the DB bit in the segment
1566 * descriptor is left as 1, although the whole segment has
1567 * been made unusable. Clear it here to pass an Intel VMX
1568 * entry check when cross vendor migrating.
1569 */
1570 if (var->unusable)
1571 var->db = 0;
1572 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1573 break;
1574 }
1575 }
1576
1577 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1578 {
1579 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1580
1581 return save->cpl;
1582 }
1583
1584 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1585 {
1586 struct vcpu_svm *svm = to_svm(vcpu);
1587
1588 dt->size = svm->vmcb->save.idtr.limit;
1589 dt->address = svm->vmcb->save.idtr.base;
1590 }
1591
1592 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1593 {
1594 struct vcpu_svm *svm = to_svm(vcpu);
1595
1596 svm->vmcb->save.idtr.limit = dt->size;
1597 svm->vmcb->save.idtr.base = dt->address ;
1598 mark_dirty(svm->vmcb, VMCB_DT);
1599 }
1600
1601 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1602 {
1603 struct vcpu_svm *svm = to_svm(vcpu);
1604
1605 dt->size = svm->vmcb->save.gdtr.limit;
1606 dt->address = svm->vmcb->save.gdtr.base;
1607 }
1608
1609 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1610 {
1611 struct vcpu_svm *svm = to_svm(vcpu);
1612
1613 svm->vmcb->save.gdtr.limit = dt->size;
1614 svm->vmcb->save.gdtr.base = dt->address ;
1615 mark_dirty(svm->vmcb, VMCB_DT);
1616 }
1617
1618 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1619 {
1620 }
1621
1622 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1623 {
1624 }
1625
1626 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1627 {
1628 }
1629
1630 static void update_cr0_intercept(struct vcpu_svm *svm)
1631 {
1632 ulong gcr0 = svm->vcpu.arch.cr0;
1633 u64 *hcr0 = &svm->vmcb->save.cr0;
1634
1635 if (!svm->vcpu.fpu_active)
1636 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1637 else
1638 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1639 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1640
1641 mark_dirty(svm->vmcb, VMCB_CR);
1642
1643 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1644 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1645 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1646 } else {
1647 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1648 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1649 }
1650 }
1651
1652 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1653 {
1654 struct vcpu_svm *svm = to_svm(vcpu);
1655
1656 #ifdef CONFIG_X86_64
1657 if (vcpu->arch.efer & EFER_LME) {
1658 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1659 vcpu->arch.efer |= EFER_LMA;
1660 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1661 }
1662
1663 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1664 vcpu->arch.efer &= ~EFER_LMA;
1665 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1666 }
1667 }
1668 #endif
1669 vcpu->arch.cr0 = cr0;
1670
1671 if (!npt_enabled)
1672 cr0 |= X86_CR0_PG | X86_CR0_WP;
1673
1674 if (!vcpu->fpu_active)
1675 cr0 |= X86_CR0_TS;
1676
1677 /* These are emulated via page tables. */
1678 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1679
1680 svm->vmcb->save.cr0 = cr0;
1681 mark_dirty(svm->vmcb, VMCB_CR);
1682 update_cr0_intercept(svm);
1683 }
1684
1685 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1686 {
1687 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1688 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1689
1690 if (cr4 & X86_CR4_VMXE)
1691 return 1;
1692
1693 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1694 svm_flush_tlb(vcpu);
1695
1696 vcpu->arch.cr4 = cr4;
1697 if (!npt_enabled)
1698 cr4 |= X86_CR4_PAE;
1699 cr4 |= host_cr4_mce;
1700 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1701 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1702 return 0;
1703 }
1704
1705 static void svm_set_segment(struct kvm_vcpu *vcpu,
1706 struct kvm_segment *var, int seg)
1707 {
1708 struct vcpu_svm *svm = to_svm(vcpu);
1709 struct vmcb_seg *s = svm_seg(vcpu, seg);
1710
1711 s->base = var->base;
1712 s->limit = var->limit;
1713 s->selector = var->selector;
1714 if (var->unusable)
1715 s->attrib = 0;
1716 else {
1717 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1718 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1719 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1720 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1721 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1722 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1723 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1724 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1725 }
1726
1727 /*
1728 * This is always accurate, except if SYSRET returned to a segment
1729 * with SS.DPL != 3. Intel does not have this quirk, and always
1730 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1731 * would entail passing the CPL to userspace and back.
1732 */
1733 if (seg == VCPU_SREG_SS)
1734 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1735
1736 mark_dirty(svm->vmcb, VMCB_SEG);
1737 }
1738
1739 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1740 {
1741 struct vcpu_svm *svm = to_svm(vcpu);
1742
1743 clr_exception_intercept(svm, DB_VECTOR);
1744 clr_exception_intercept(svm, BP_VECTOR);
1745
1746 if (svm->nmi_singlestep)
1747 set_exception_intercept(svm, DB_VECTOR);
1748
1749 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1750 if (vcpu->guest_debug &
1751 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1752 set_exception_intercept(svm, DB_VECTOR);
1753 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1754 set_exception_intercept(svm, BP_VECTOR);
1755 } else
1756 vcpu->guest_debug = 0;
1757 }
1758
1759 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1760 {
1761 if (sd->next_asid > sd->max_asid) {
1762 ++sd->asid_generation;
1763 sd->next_asid = 1;
1764 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1765 }
1766
1767 svm->asid_generation = sd->asid_generation;
1768 svm->vmcb->control.asid = sd->next_asid++;
1769
1770 mark_dirty(svm->vmcb, VMCB_ASID);
1771 }
1772
1773 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1774 {
1775 return to_svm(vcpu)->vmcb->save.dr6;
1776 }
1777
1778 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1779 {
1780 struct vcpu_svm *svm = to_svm(vcpu);
1781
1782 svm->vmcb->save.dr6 = value;
1783 mark_dirty(svm->vmcb, VMCB_DR);
1784 }
1785
1786 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1787 {
1788 struct vcpu_svm *svm = to_svm(vcpu);
1789
1790 get_debugreg(vcpu->arch.db[0], 0);
1791 get_debugreg(vcpu->arch.db[1], 1);
1792 get_debugreg(vcpu->arch.db[2], 2);
1793 get_debugreg(vcpu->arch.db[3], 3);
1794 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1795 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1796
1797 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1798 set_dr_intercepts(svm);
1799 }
1800
1801 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1802 {
1803 struct vcpu_svm *svm = to_svm(vcpu);
1804
1805 svm->vmcb->save.dr7 = value;
1806 mark_dirty(svm->vmcb, VMCB_DR);
1807 }
1808
1809 static int pf_interception(struct vcpu_svm *svm)
1810 {
1811 u64 fault_address = svm->vmcb->control.exit_info_2;
1812 u32 error_code;
1813 int r = 1;
1814
1815 switch (svm->apf_reason) {
1816 default:
1817 error_code = svm->vmcb->control.exit_info_1;
1818
1819 trace_kvm_page_fault(fault_address, error_code);
1820 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1821 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1822 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1823 svm->vmcb->control.insn_bytes,
1824 svm->vmcb->control.insn_len);
1825 break;
1826 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1827 svm->apf_reason = 0;
1828 local_irq_disable();
1829 kvm_async_pf_task_wait(fault_address);
1830 local_irq_enable();
1831 break;
1832 case KVM_PV_REASON_PAGE_READY:
1833 svm->apf_reason = 0;
1834 local_irq_disable();
1835 kvm_async_pf_task_wake(fault_address);
1836 local_irq_enable();
1837 break;
1838 }
1839 return r;
1840 }
1841
1842 static int db_interception(struct vcpu_svm *svm)
1843 {
1844 struct kvm_run *kvm_run = svm->vcpu.run;
1845
1846 if (!(svm->vcpu.guest_debug &
1847 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1848 !svm->nmi_singlestep) {
1849 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1850 return 1;
1851 }
1852
1853 if (svm->nmi_singlestep) {
1854 svm->nmi_singlestep = false;
1855 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1856 svm->vmcb->save.rflags &=
1857 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1858 update_db_bp_intercept(&svm->vcpu);
1859 }
1860
1861 if (svm->vcpu.guest_debug &
1862 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1863 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1864 kvm_run->debug.arch.pc =
1865 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1866 kvm_run->debug.arch.exception = DB_VECTOR;
1867 return 0;
1868 }
1869
1870 return 1;
1871 }
1872
1873 static int bp_interception(struct vcpu_svm *svm)
1874 {
1875 struct kvm_run *kvm_run = svm->vcpu.run;
1876
1877 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1878 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1879 kvm_run->debug.arch.exception = BP_VECTOR;
1880 return 0;
1881 }
1882
1883 static int ud_interception(struct vcpu_svm *svm)
1884 {
1885 int er;
1886
1887 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1888 if (er != EMULATE_DONE)
1889 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1890 return 1;
1891 }
1892
1893 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1894 {
1895 struct vcpu_svm *svm = to_svm(vcpu);
1896
1897 clr_exception_intercept(svm, NM_VECTOR);
1898
1899 svm->vcpu.fpu_active = 1;
1900 update_cr0_intercept(svm);
1901 }
1902
1903 static int nm_interception(struct vcpu_svm *svm)
1904 {
1905 svm_fpu_activate(&svm->vcpu);
1906 return 1;
1907 }
1908
1909 static bool is_erratum_383(void)
1910 {
1911 int err, i;
1912 u64 value;
1913
1914 if (!erratum_383_found)
1915 return false;
1916
1917 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1918 if (err)
1919 return false;
1920
1921 /* Bit 62 may or may not be set for this mce */
1922 value &= ~(1ULL << 62);
1923
1924 if (value != 0xb600000000010015ULL)
1925 return false;
1926
1927 /* Clear MCi_STATUS registers */
1928 for (i = 0; i < 6; ++i)
1929 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1930
1931 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1932 if (!err) {
1933 u32 low, high;
1934
1935 value &= ~(1ULL << 2);
1936 low = lower_32_bits(value);
1937 high = upper_32_bits(value);
1938
1939 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1940 }
1941
1942 /* Flush tlb to evict multi-match entries */
1943 __flush_tlb_all();
1944
1945 return true;
1946 }
1947
1948 static void svm_handle_mce(struct vcpu_svm *svm)
1949 {
1950 if (is_erratum_383()) {
1951 /*
1952 * Erratum 383 triggered. Guest state is corrupt so kill the
1953 * guest.
1954 */
1955 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1956
1957 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1958
1959 return;
1960 }
1961
1962 /*
1963 * On an #MC intercept the MCE handler is not called automatically in
1964 * the host. So do it by hand here.
1965 */
1966 asm volatile (
1967 "int $0x12\n");
1968 /* not sure if we ever come back to this point */
1969
1970 return;
1971 }
1972
1973 static int mc_interception(struct vcpu_svm *svm)
1974 {
1975 return 1;
1976 }
1977
1978 static int shutdown_interception(struct vcpu_svm *svm)
1979 {
1980 struct kvm_run *kvm_run = svm->vcpu.run;
1981
1982 /*
1983 * VMCB is undefined after a SHUTDOWN intercept
1984 * so reinitialize it.
1985 */
1986 clear_page(svm->vmcb);
1987 init_vmcb(svm, false);
1988
1989 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1990 return 0;
1991 }
1992
1993 static int io_interception(struct vcpu_svm *svm)
1994 {
1995 struct kvm_vcpu *vcpu = &svm->vcpu;
1996 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1997 int size, in, string;
1998 unsigned port;
1999
2000 ++svm->vcpu.stat.io_exits;
2001 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2002 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2003 if (string || in)
2004 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2005
2006 port = io_info >> 16;
2007 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2008 svm->next_rip = svm->vmcb->control.exit_info_2;
2009 skip_emulated_instruction(&svm->vcpu);
2010
2011 return kvm_fast_pio_out(vcpu, size, port);
2012 }
2013
2014 static int nmi_interception(struct vcpu_svm *svm)
2015 {
2016 return 1;
2017 }
2018
2019 static int intr_interception(struct vcpu_svm *svm)
2020 {
2021 ++svm->vcpu.stat.irq_exits;
2022 return 1;
2023 }
2024
2025 static int nop_on_interception(struct vcpu_svm *svm)
2026 {
2027 return 1;
2028 }
2029
2030 static int halt_interception(struct vcpu_svm *svm)
2031 {
2032 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2033 return kvm_emulate_halt(&svm->vcpu);
2034 }
2035
2036 static int vmmcall_interception(struct vcpu_svm *svm)
2037 {
2038 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2039 kvm_emulate_hypercall(&svm->vcpu);
2040 return 1;
2041 }
2042
2043 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2044 {
2045 struct vcpu_svm *svm = to_svm(vcpu);
2046
2047 return svm->nested.nested_cr3;
2048 }
2049
2050 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2051 {
2052 struct vcpu_svm *svm = to_svm(vcpu);
2053 u64 cr3 = svm->nested.nested_cr3;
2054 u64 pdpte;
2055 int ret;
2056
2057 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2058 offset_in_page(cr3) + index * 8, 8);
2059 if (ret)
2060 return 0;
2061 return pdpte;
2062 }
2063
2064 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2065 unsigned long root)
2066 {
2067 struct vcpu_svm *svm = to_svm(vcpu);
2068
2069 svm->vmcb->control.nested_cr3 = root;
2070 mark_dirty(svm->vmcb, VMCB_NPT);
2071 svm_flush_tlb(vcpu);
2072 }
2073
2074 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2075 struct x86_exception *fault)
2076 {
2077 struct vcpu_svm *svm = to_svm(vcpu);
2078
2079 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2080 /*
2081 * TODO: track the cause of the nested page fault, and
2082 * correctly fill in the high bits of exit_info_1.
2083 */
2084 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2085 svm->vmcb->control.exit_code_hi = 0;
2086 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2087 svm->vmcb->control.exit_info_2 = fault->address;
2088 }
2089
2090 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2091 svm->vmcb->control.exit_info_1 |= fault->error_code;
2092
2093 /*
2094 * The present bit is always zero for page structure faults on real
2095 * hardware.
2096 */
2097 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2098 svm->vmcb->control.exit_info_1 &= ~1;
2099
2100 nested_svm_vmexit(svm);
2101 }
2102
2103 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2104 {
2105 WARN_ON(mmu_is_nested(vcpu));
2106 kvm_init_shadow_mmu(vcpu);
2107 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2108 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2109 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2110 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2111 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2112 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2113 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2114 }
2115
2116 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2117 {
2118 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2119 }
2120
2121 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2122 {
2123 if (!(svm->vcpu.arch.efer & EFER_SVME)
2124 || !is_paging(&svm->vcpu)) {
2125 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2126 return 1;
2127 }
2128
2129 if (svm->vmcb->save.cpl) {
2130 kvm_inject_gp(&svm->vcpu, 0);
2131 return 1;
2132 }
2133
2134 return 0;
2135 }
2136
2137 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2138 bool has_error_code, u32 error_code)
2139 {
2140 int vmexit;
2141
2142 if (!is_guest_mode(&svm->vcpu))
2143 return 0;
2144
2145 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2146 svm->vmcb->control.exit_code_hi = 0;
2147 svm->vmcb->control.exit_info_1 = error_code;
2148 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2149
2150 vmexit = nested_svm_intercept(svm);
2151 if (vmexit == NESTED_EXIT_DONE)
2152 svm->nested.exit_required = true;
2153
2154 return vmexit;
2155 }
2156
2157 /* This function returns true if it is save to enable the irq window */
2158 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2159 {
2160 if (!is_guest_mode(&svm->vcpu))
2161 return true;
2162
2163 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2164 return true;
2165
2166 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2167 return false;
2168
2169 /*
2170 * if vmexit was already requested (by intercepted exception
2171 * for instance) do not overwrite it with "external interrupt"
2172 * vmexit.
2173 */
2174 if (svm->nested.exit_required)
2175 return false;
2176
2177 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2178 svm->vmcb->control.exit_info_1 = 0;
2179 svm->vmcb->control.exit_info_2 = 0;
2180
2181 if (svm->nested.intercept & 1ULL) {
2182 /*
2183 * The #vmexit can't be emulated here directly because this
2184 * code path runs with irqs and preemption disabled. A
2185 * #vmexit emulation might sleep. Only signal request for
2186 * the #vmexit here.
2187 */
2188 svm->nested.exit_required = true;
2189 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2190 return false;
2191 }
2192
2193 return true;
2194 }
2195
2196 /* This function returns true if it is save to enable the nmi window */
2197 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2198 {
2199 if (!is_guest_mode(&svm->vcpu))
2200 return true;
2201
2202 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2203 return true;
2204
2205 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2206 svm->nested.exit_required = true;
2207
2208 return false;
2209 }
2210
2211 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2212 {
2213 struct page *page;
2214
2215 might_sleep();
2216
2217 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2218 if (is_error_page(page))
2219 goto error;
2220
2221 *_page = page;
2222
2223 return kmap(page);
2224
2225 error:
2226 kvm_inject_gp(&svm->vcpu, 0);
2227
2228 return NULL;
2229 }
2230
2231 static void nested_svm_unmap(struct page *page)
2232 {
2233 kunmap(page);
2234 kvm_release_page_dirty(page);
2235 }
2236
2237 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2238 {
2239 unsigned port, size, iopm_len;
2240 u16 val, mask;
2241 u8 start_bit;
2242 u64 gpa;
2243
2244 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2245 return NESTED_EXIT_HOST;
2246
2247 port = svm->vmcb->control.exit_info_1 >> 16;
2248 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2249 SVM_IOIO_SIZE_SHIFT;
2250 gpa = svm->nested.vmcb_iopm + (port / 8);
2251 start_bit = port % 8;
2252 iopm_len = (start_bit + size > 8) ? 2 : 1;
2253 mask = (0xf >> (4 - size)) << start_bit;
2254 val = 0;
2255
2256 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2257 return NESTED_EXIT_DONE;
2258
2259 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2260 }
2261
2262 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2263 {
2264 u32 offset, msr, value;
2265 int write, mask;
2266
2267 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2268 return NESTED_EXIT_HOST;
2269
2270 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2271 offset = svm_msrpm_offset(msr);
2272 write = svm->vmcb->control.exit_info_1 & 1;
2273 mask = 1 << ((2 * (msr & 0xf)) + write);
2274
2275 if (offset == MSR_INVALID)
2276 return NESTED_EXIT_DONE;
2277
2278 /* Offset is in 32 bit units but need in 8 bit units */
2279 offset *= 4;
2280
2281 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2282 return NESTED_EXIT_DONE;
2283
2284 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2285 }
2286
2287 static int nested_svm_exit_special(struct vcpu_svm *svm)
2288 {
2289 u32 exit_code = svm->vmcb->control.exit_code;
2290
2291 switch (exit_code) {
2292 case SVM_EXIT_INTR:
2293 case SVM_EXIT_NMI:
2294 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2295 return NESTED_EXIT_HOST;
2296 case SVM_EXIT_NPF:
2297 /* For now we are always handling NPFs when using them */
2298 if (npt_enabled)
2299 return NESTED_EXIT_HOST;
2300 break;
2301 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2302 /* When we're shadowing, trap PFs, but not async PF */
2303 if (!npt_enabled && svm->apf_reason == 0)
2304 return NESTED_EXIT_HOST;
2305 break;
2306 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2307 nm_interception(svm);
2308 break;
2309 default:
2310 break;
2311 }
2312
2313 return NESTED_EXIT_CONTINUE;
2314 }
2315
2316 /*
2317 * If this function returns true, this #vmexit was already handled
2318 */
2319 static int nested_svm_intercept(struct vcpu_svm *svm)
2320 {
2321 u32 exit_code = svm->vmcb->control.exit_code;
2322 int vmexit = NESTED_EXIT_HOST;
2323
2324 switch (exit_code) {
2325 case SVM_EXIT_MSR:
2326 vmexit = nested_svm_exit_handled_msr(svm);
2327 break;
2328 case SVM_EXIT_IOIO:
2329 vmexit = nested_svm_intercept_ioio(svm);
2330 break;
2331 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2332 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2333 if (svm->nested.intercept_cr & bit)
2334 vmexit = NESTED_EXIT_DONE;
2335 break;
2336 }
2337 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2338 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2339 if (svm->nested.intercept_dr & bit)
2340 vmexit = NESTED_EXIT_DONE;
2341 break;
2342 }
2343 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2344 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2345 if (svm->nested.intercept_exceptions & excp_bits)
2346 vmexit = NESTED_EXIT_DONE;
2347 /* async page fault always cause vmexit */
2348 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2349 svm->apf_reason != 0)
2350 vmexit = NESTED_EXIT_DONE;
2351 break;
2352 }
2353 case SVM_EXIT_ERR: {
2354 vmexit = NESTED_EXIT_DONE;
2355 break;
2356 }
2357 default: {
2358 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2359 if (svm->nested.intercept & exit_bits)
2360 vmexit = NESTED_EXIT_DONE;
2361 }
2362 }
2363
2364 return vmexit;
2365 }
2366
2367 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2368 {
2369 int vmexit;
2370
2371 vmexit = nested_svm_intercept(svm);
2372
2373 if (vmexit == NESTED_EXIT_DONE)
2374 nested_svm_vmexit(svm);
2375
2376 return vmexit;
2377 }
2378
2379 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2380 {
2381 struct vmcb_control_area *dst = &dst_vmcb->control;
2382 struct vmcb_control_area *from = &from_vmcb->control;
2383
2384 dst->intercept_cr = from->intercept_cr;
2385 dst->intercept_dr = from->intercept_dr;
2386 dst->intercept_exceptions = from->intercept_exceptions;
2387 dst->intercept = from->intercept;
2388 dst->iopm_base_pa = from->iopm_base_pa;
2389 dst->msrpm_base_pa = from->msrpm_base_pa;
2390 dst->tsc_offset = from->tsc_offset;
2391 dst->asid = from->asid;
2392 dst->tlb_ctl = from->tlb_ctl;
2393 dst->int_ctl = from->int_ctl;
2394 dst->int_vector = from->int_vector;
2395 dst->int_state = from->int_state;
2396 dst->exit_code = from->exit_code;
2397 dst->exit_code_hi = from->exit_code_hi;
2398 dst->exit_info_1 = from->exit_info_1;
2399 dst->exit_info_2 = from->exit_info_2;
2400 dst->exit_int_info = from->exit_int_info;
2401 dst->exit_int_info_err = from->exit_int_info_err;
2402 dst->nested_ctl = from->nested_ctl;
2403 dst->event_inj = from->event_inj;
2404 dst->event_inj_err = from->event_inj_err;
2405 dst->nested_cr3 = from->nested_cr3;
2406 dst->lbr_ctl = from->lbr_ctl;
2407 }
2408
2409 static int nested_svm_vmexit(struct vcpu_svm *svm)
2410 {
2411 struct vmcb *nested_vmcb;
2412 struct vmcb *hsave = svm->nested.hsave;
2413 struct vmcb *vmcb = svm->vmcb;
2414 struct page *page;
2415
2416 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2417 vmcb->control.exit_info_1,
2418 vmcb->control.exit_info_2,
2419 vmcb->control.exit_int_info,
2420 vmcb->control.exit_int_info_err,
2421 KVM_ISA_SVM);
2422
2423 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2424 if (!nested_vmcb)
2425 return 1;
2426
2427 /* Exit Guest-Mode */
2428 leave_guest_mode(&svm->vcpu);
2429 svm->nested.vmcb = 0;
2430
2431 /* Give the current vmcb to the guest */
2432 disable_gif(svm);
2433
2434 nested_vmcb->save.es = vmcb->save.es;
2435 nested_vmcb->save.cs = vmcb->save.cs;
2436 nested_vmcb->save.ss = vmcb->save.ss;
2437 nested_vmcb->save.ds = vmcb->save.ds;
2438 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2439 nested_vmcb->save.idtr = vmcb->save.idtr;
2440 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2441 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2442 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2443 nested_vmcb->save.cr2 = vmcb->save.cr2;
2444 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2445 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2446 nested_vmcb->save.rip = vmcb->save.rip;
2447 nested_vmcb->save.rsp = vmcb->save.rsp;
2448 nested_vmcb->save.rax = vmcb->save.rax;
2449 nested_vmcb->save.dr7 = vmcb->save.dr7;
2450 nested_vmcb->save.dr6 = vmcb->save.dr6;
2451 nested_vmcb->save.cpl = vmcb->save.cpl;
2452
2453 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2454 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2455 nested_vmcb->control.int_state = vmcb->control.int_state;
2456 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2457 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2458 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2459 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2460 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2461 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2462 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2463
2464 /*
2465 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2466 * to make sure that we do not lose injected events. So check event_inj
2467 * here and copy it to exit_int_info if it is valid.
2468 * Exit_int_info and event_inj can't be both valid because the case
2469 * below only happens on a VMRUN instruction intercept which has
2470 * no valid exit_int_info set.
2471 */
2472 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2473 struct vmcb_control_area *nc = &nested_vmcb->control;
2474
2475 nc->exit_int_info = vmcb->control.event_inj;
2476 nc->exit_int_info_err = vmcb->control.event_inj_err;
2477 }
2478
2479 nested_vmcb->control.tlb_ctl = 0;
2480 nested_vmcb->control.event_inj = 0;
2481 nested_vmcb->control.event_inj_err = 0;
2482
2483 /* We always set V_INTR_MASKING and remember the old value in hflags */
2484 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2485 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2486
2487 /* Restore the original control entries */
2488 copy_vmcb_control_area(vmcb, hsave);
2489
2490 kvm_clear_exception_queue(&svm->vcpu);
2491 kvm_clear_interrupt_queue(&svm->vcpu);
2492
2493 svm->nested.nested_cr3 = 0;
2494
2495 /* Restore selected save entries */
2496 svm->vmcb->save.es = hsave->save.es;
2497 svm->vmcb->save.cs = hsave->save.cs;
2498 svm->vmcb->save.ss = hsave->save.ss;
2499 svm->vmcb->save.ds = hsave->save.ds;
2500 svm->vmcb->save.gdtr = hsave->save.gdtr;
2501 svm->vmcb->save.idtr = hsave->save.idtr;
2502 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2503 svm_set_efer(&svm->vcpu, hsave->save.efer);
2504 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2505 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2506 if (npt_enabled) {
2507 svm->vmcb->save.cr3 = hsave->save.cr3;
2508 svm->vcpu.arch.cr3 = hsave->save.cr3;
2509 } else {
2510 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2511 }
2512 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2513 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2514 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2515 svm->vmcb->save.dr7 = 0;
2516 svm->vmcb->save.cpl = 0;
2517 svm->vmcb->control.exit_int_info = 0;
2518
2519 mark_all_dirty(svm->vmcb);
2520
2521 nested_svm_unmap(page);
2522
2523 nested_svm_uninit_mmu_context(&svm->vcpu);
2524 kvm_mmu_reset_context(&svm->vcpu);
2525 kvm_mmu_load(&svm->vcpu);
2526
2527 return 0;
2528 }
2529
2530 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2531 {
2532 /*
2533 * This function merges the msr permission bitmaps of kvm and the
2534 * nested vmcb. It is optimized in that it only merges the parts where
2535 * the kvm msr permission bitmap may contain zero bits
2536 */
2537 int i;
2538
2539 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2540 return true;
2541
2542 for (i = 0; i < MSRPM_OFFSETS; i++) {
2543 u32 value, p;
2544 u64 offset;
2545
2546 if (msrpm_offsets[i] == 0xffffffff)
2547 break;
2548
2549 p = msrpm_offsets[i];
2550 offset = svm->nested.vmcb_msrpm + (p * 4);
2551
2552 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2553 return false;
2554
2555 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2556 }
2557
2558 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2559
2560 return true;
2561 }
2562
2563 static bool nested_vmcb_checks(struct vmcb *vmcb)
2564 {
2565 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2566 return false;
2567
2568 if (vmcb->control.asid == 0)
2569 return false;
2570
2571 if (vmcb->control.nested_ctl && !npt_enabled)
2572 return false;
2573
2574 return true;
2575 }
2576
2577 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2578 {
2579 struct vmcb *nested_vmcb;
2580 struct vmcb *hsave = svm->nested.hsave;
2581 struct vmcb *vmcb = svm->vmcb;
2582 struct page *page;
2583 u64 vmcb_gpa;
2584
2585 vmcb_gpa = svm->vmcb->save.rax;
2586
2587 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2588 if (!nested_vmcb)
2589 return false;
2590
2591 if (!nested_vmcb_checks(nested_vmcb)) {
2592 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2593 nested_vmcb->control.exit_code_hi = 0;
2594 nested_vmcb->control.exit_info_1 = 0;
2595 nested_vmcb->control.exit_info_2 = 0;
2596
2597 nested_svm_unmap(page);
2598
2599 return false;
2600 }
2601
2602 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2603 nested_vmcb->save.rip,
2604 nested_vmcb->control.int_ctl,
2605 nested_vmcb->control.event_inj,
2606 nested_vmcb->control.nested_ctl);
2607
2608 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2609 nested_vmcb->control.intercept_cr >> 16,
2610 nested_vmcb->control.intercept_exceptions,
2611 nested_vmcb->control.intercept);
2612
2613 /* Clear internal status */
2614 kvm_clear_exception_queue(&svm->vcpu);
2615 kvm_clear_interrupt_queue(&svm->vcpu);
2616
2617 /*
2618 * Save the old vmcb, so we don't need to pick what we save, but can
2619 * restore everything when a VMEXIT occurs
2620 */
2621 hsave->save.es = vmcb->save.es;
2622 hsave->save.cs = vmcb->save.cs;
2623 hsave->save.ss = vmcb->save.ss;
2624 hsave->save.ds = vmcb->save.ds;
2625 hsave->save.gdtr = vmcb->save.gdtr;
2626 hsave->save.idtr = vmcb->save.idtr;
2627 hsave->save.efer = svm->vcpu.arch.efer;
2628 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2629 hsave->save.cr4 = svm->vcpu.arch.cr4;
2630 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2631 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2632 hsave->save.rsp = vmcb->save.rsp;
2633 hsave->save.rax = vmcb->save.rax;
2634 if (npt_enabled)
2635 hsave->save.cr3 = vmcb->save.cr3;
2636 else
2637 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2638
2639 copy_vmcb_control_area(hsave, vmcb);
2640
2641 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2642 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2643 else
2644 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2645
2646 if (nested_vmcb->control.nested_ctl) {
2647 kvm_mmu_unload(&svm->vcpu);
2648 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2649 nested_svm_init_mmu_context(&svm->vcpu);
2650 }
2651
2652 /* Load the nested guest state */
2653 svm->vmcb->save.es = nested_vmcb->save.es;
2654 svm->vmcb->save.cs = nested_vmcb->save.cs;
2655 svm->vmcb->save.ss = nested_vmcb->save.ss;
2656 svm->vmcb->save.ds = nested_vmcb->save.ds;
2657 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2658 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2659 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2660 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2661 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2662 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2663 if (npt_enabled) {
2664 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2665 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2666 } else
2667 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2668
2669 /* Guest paging mode is active - reset mmu */
2670 kvm_mmu_reset_context(&svm->vcpu);
2671
2672 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2673 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2674 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2675 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2676
2677 /* In case we don't even reach vcpu_run, the fields are not updated */
2678 svm->vmcb->save.rax = nested_vmcb->save.rax;
2679 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2680 svm->vmcb->save.rip = nested_vmcb->save.rip;
2681 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2682 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2683 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2684
2685 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2686 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2687
2688 /* cache intercepts */
2689 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2690 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2691 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2692 svm->nested.intercept = nested_vmcb->control.intercept;
2693
2694 svm_flush_tlb(&svm->vcpu);
2695 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2696 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2697 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2698 else
2699 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2700
2701 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2702 /* We only want the cr8 intercept bits of the guest */
2703 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2704 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2705 }
2706
2707 /* We don't want to see VMMCALLs from a nested guest */
2708 clr_intercept(svm, INTERCEPT_VMMCALL);
2709
2710 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2711 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2712 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2713 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2714 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2715 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2716
2717 nested_svm_unmap(page);
2718
2719 /* Enter Guest-Mode */
2720 enter_guest_mode(&svm->vcpu);
2721
2722 /*
2723 * Merge guest and host intercepts - must be called with vcpu in
2724 * guest-mode to take affect here
2725 */
2726 recalc_intercepts(svm);
2727
2728 svm->nested.vmcb = vmcb_gpa;
2729
2730 enable_gif(svm);
2731
2732 mark_all_dirty(svm->vmcb);
2733
2734 return true;
2735 }
2736
2737 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2738 {
2739 to_vmcb->save.fs = from_vmcb->save.fs;
2740 to_vmcb->save.gs = from_vmcb->save.gs;
2741 to_vmcb->save.tr = from_vmcb->save.tr;
2742 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2743 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2744 to_vmcb->save.star = from_vmcb->save.star;
2745 to_vmcb->save.lstar = from_vmcb->save.lstar;
2746 to_vmcb->save.cstar = from_vmcb->save.cstar;
2747 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2748 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2749 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2750 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2751 }
2752
2753 static int vmload_interception(struct vcpu_svm *svm)
2754 {
2755 struct vmcb *nested_vmcb;
2756 struct page *page;
2757
2758 if (nested_svm_check_permissions(svm))
2759 return 1;
2760
2761 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2762 if (!nested_vmcb)
2763 return 1;
2764
2765 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2766 skip_emulated_instruction(&svm->vcpu);
2767
2768 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2769 nested_svm_unmap(page);
2770
2771 return 1;
2772 }
2773
2774 static int vmsave_interception(struct vcpu_svm *svm)
2775 {
2776 struct vmcb *nested_vmcb;
2777 struct page *page;
2778
2779 if (nested_svm_check_permissions(svm))
2780 return 1;
2781
2782 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2783 if (!nested_vmcb)
2784 return 1;
2785
2786 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2787 skip_emulated_instruction(&svm->vcpu);
2788
2789 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2790 nested_svm_unmap(page);
2791
2792 return 1;
2793 }
2794
2795 static int vmrun_interception(struct vcpu_svm *svm)
2796 {
2797 if (nested_svm_check_permissions(svm))
2798 return 1;
2799
2800 /* Save rip after vmrun instruction */
2801 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2802
2803 if (!nested_svm_vmrun(svm))
2804 return 1;
2805
2806 if (!nested_svm_vmrun_msrpm(svm))
2807 goto failed;
2808
2809 return 1;
2810
2811 failed:
2812
2813 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2814 svm->vmcb->control.exit_code_hi = 0;
2815 svm->vmcb->control.exit_info_1 = 0;
2816 svm->vmcb->control.exit_info_2 = 0;
2817
2818 nested_svm_vmexit(svm);
2819
2820 return 1;
2821 }
2822
2823 static int stgi_interception(struct vcpu_svm *svm)
2824 {
2825 if (nested_svm_check_permissions(svm))
2826 return 1;
2827
2828 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2829 skip_emulated_instruction(&svm->vcpu);
2830 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2831
2832 enable_gif(svm);
2833
2834 return 1;
2835 }
2836
2837 static int clgi_interception(struct vcpu_svm *svm)
2838 {
2839 if (nested_svm_check_permissions(svm))
2840 return 1;
2841
2842 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2843 skip_emulated_instruction(&svm->vcpu);
2844
2845 disable_gif(svm);
2846
2847 /* After a CLGI no interrupts should come */
2848 svm_clear_vintr(svm);
2849 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2850
2851 mark_dirty(svm->vmcb, VMCB_INTR);
2852
2853 return 1;
2854 }
2855
2856 static int invlpga_interception(struct vcpu_svm *svm)
2857 {
2858 struct kvm_vcpu *vcpu = &svm->vcpu;
2859
2860 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2861 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2862
2863 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2864 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2865
2866 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2867 skip_emulated_instruction(&svm->vcpu);
2868 return 1;
2869 }
2870
2871 static int skinit_interception(struct vcpu_svm *svm)
2872 {
2873 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2874
2875 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2876 return 1;
2877 }
2878
2879 static int wbinvd_interception(struct vcpu_svm *svm)
2880 {
2881 kvm_emulate_wbinvd(&svm->vcpu);
2882 return 1;
2883 }
2884
2885 static int xsetbv_interception(struct vcpu_svm *svm)
2886 {
2887 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2888 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2889
2890 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2891 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2892 skip_emulated_instruction(&svm->vcpu);
2893 }
2894
2895 return 1;
2896 }
2897
2898 static int task_switch_interception(struct vcpu_svm *svm)
2899 {
2900 u16 tss_selector;
2901 int reason;
2902 int int_type = svm->vmcb->control.exit_int_info &
2903 SVM_EXITINTINFO_TYPE_MASK;
2904 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2905 uint32_t type =
2906 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2907 uint32_t idt_v =
2908 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2909 bool has_error_code = false;
2910 u32 error_code = 0;
2911
2912 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2913
2914 if (svm->vmcb->control.exit_info_2 &
2915 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2916 reason = TASK_SWITCH_IRET;
2917 else if (svm->vmcb->control.exit_info_2 &
2918 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2919 reason = TASK_SWITCH_JMP;
2920 else if (idt_v)
2921 reason = TASK_SWITCH_GATE;
2922 else
2923 reason = TASK_SWITCH_CALL;
2924
2925 if (reason == TASK_SWITCH_GATE) {
2926 switch (type) {
2927 case SVM_EXITINTINFO_TYPE_NMI:
2928 svm->vcpu.arch.nmi_injected = false;
2929 break;
2930 case SVM_EXITINTINFO_TYPE_EXEPT:
2931 if (svm->vmcb->control.exit_info_2 &
2932 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2933 has_error_code = true;
2934 error_code =
2935 (u32)svm->vmcb->control.exit_info_2;
2936 }
2937 kvm_clear_exception_queue(&svm->vcpu);
2938 break;
2939 case SVM_EXITINTINFO_TYPE_INTR:
2940 kvm_clear_interrupt_queue(&svm->vcpu);
2941 break;
2942 default:
2943 break;
2944 }
2945 }
2946
2947 if (reason != TASK_SWITCH_GATE ||
2948 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2949 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2950 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2951 skip_emulated_instruction(&svm->vcpu);
2952
2953 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2954 int_vec = -1;
2955
2956 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2957 has_error_code, error_code) == EMULATE_FAIL) {
2958 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2959 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2960 svm->vcpu.run->internal.ndata = 0;
2961 return 0;
2962 }
2963 return 1;
2964 }
2965
2966 static int cpuid_interception(struct vcpu_svm *svm)
2967 {
2968 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2969 kvm_emulate_cpuid(&svm->vcpu);
2970 return 1;
2971 }
2972
2973 static int iret_interception(struct vcpu_svm *svm)
2974 {
2975 ++svm->vcpu.stat.nmi_window_exits;
2976 clr_intercept(svm, INTERCEPT_IRET);
2977 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2978 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2979 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2980 return 1;
2981 }
2982
2983 static int invlpg_interception(struct vcpu_svm *svm)
2984 {
2985 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2986 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2987
2988 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2989 skip_emulated_instruction(&svm->vcpu);
2990 return 1;
2991 }
2992
2993 static int emulate_on_interception(struct vcpu_svm *svm)
2994 {
2995 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2996 }
2997
2998 static int rdpmc_interception(struct vcpu_svm *svm)
2999 {
3000 int err;
3001
3002 if (!static_cpu_has(X86_FEATURE_NRIPS))
3003 return emulate_on_interception(svm);
3004
3005 err = kvm_rdpmc(&svm->vcpu);
3006 kvm_complete_insn_gp(&svm->vcpu, err);
3007
3008 return 1;
3009 }
3010
3011 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3012 unsigned long val)
3013 {
3014 unsigned long cr0 = svm->vcpu.arch.cr0;
3015 bool ret = false;
3016 u64 intercept;
3017
3018 intercept = svm->nested.intercept;
3019
3020 if (!is_guest_mode(&svm->vcpu) ||
3021 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3022 return false;
3023
3024 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3025 val &= ~SVM_CR0_SELECTIVE_MASK;
3026
3027 if (cr0 ^ val) {
3028 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3029 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3030 }
3031
3032 return ret;
3033 }
3034
3035 #define CR_VALID (1ULL << 63)
3036
3037 static int cr_interception(struct vcpu_svm *svm)
3038 {
3039 int reg, cr;
3040 unsigned long val;
3041 int err;
3042
3043 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3044 return emulate_on_interception(svm);
3045
3046 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3047 return emulate_on_interception(svm);
3048
3049 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3050 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3051 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3052 else
3053 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3054
3055 err = 0;
3056 if (cr >= 16) { /* mov to cr */
3057 cr -= 16;
3058 val = kvm_register_read(&svm->vcpu, reg);
3059 switch (cr) {
3060 case 0:
3061 if (!check_selective_cr0_intercepted(svm, val))
3062 err = kvm_set_cr0(&svm->vcpu, val);
3063 else
3064 return 1;
3065
3066 break;
3067 case 3:
3068 err = kvm_set_cr3(&svm->vcpu, val);
3069 break;
3070 case 4:
3071 err = kvm_set_cr4(&svm->vcpu, val);
3072 break;
3073 case 8:
3074 err = kvm_set_cr8(&svm->vcpu, val);
3075 break;
3076 default:
3077 WARN(1, "unhandled write to CR%d", cr);
3078 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3079 return 1;
3080 }
3081 } else { /* mov from cr */
3082 switch (cr) {
3083 case 0:
3084 val = kvm_read_cr0(&svm->vcpu);
3085 break;
3086 case 2:
3087 val = svm->vcpu.arch.cr2;
3088 break;
3089 case 3:
3090 val = kvm_read_cr3(&svm->vcpu);
3091 break;
3092 case 4:
3093 val = kvm_read_cr4(&svm->vcpu);
3094 break;
3095 case 8:
3096 val = kvm_get_cr8(&svm->vcpu);
3097 break;
3098 default:
3099 WARN(1, "unhandled read from CR%d", cr);
3100 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3101 return 1;
3102 }
3103 kvm_register_write(&svm->vcpu, reg, val);
3104 }
3105 kvm_complete_insn_gp(&svm->vcpu, err);
3106
3107 return 1;
3108 }
3109
3110 static int dr_interception(struct vcpu_svm *svm)
3111 {
3112 int reg, dr;
3113 unsigned long val;
3114
3115 if (svm->vcpu.guest_debug == 0) {
3116 /*
3117 * No more DR vmexits; force a reload of the debug registers
3118 * and reenter on this instruction. The next vmexit will
3119 * retrieve the full state of the debug registers.
3120 */
3121 clr_dr_intercepts(svm);
3122 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3123 return 1;
3124 }
3125
3126 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3127 return emulate_on_interception(svm);
3128
3129 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3130 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3131
3132 if (dr >= 16) { /* mov to DRn */
3133 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3134 return 1;
3135 val = kvm_register_read(&svm->vcpu, reg);
3136 kvm_set_dr(&svm->vcpu, dr - 16, val);
3137 } else {
3138 if (!kvm_require_dr(&svm->vcpu, dr))
3139 return 1;
3140 kvm_get_dr(&svm->vcpu, dr, &val);
3141 kvm_register_write(&svm->vcpu, reg, val);
3142 }
3143
3144 skip_emulated_instruction(&svm->vcpu);
3145
3146 return 1;
3147 }
3148
3149 static int cr8_write_interception(struct vcpu_svm *svm)
3150 {
3151 struct kvm_run *kvm_run = svm->vcpu.run;
3152 int r;
3153
3154 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3155 /* instruction emulation calls kvm_set_cr8() */
3156 r = cr_interception(svm);
3157 if (irqchip_in_kernel(svm->vcpu.kvm))
3158 return r;
3159 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3160 return r;
3161 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3162 return 0;
3163 }
3164
3165 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3166 {
3167 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3168 return vmcb->control.tsc_offset +
3169 svm_scale_tsc(vcpu, host_tsc);
3170 }
3171
3172 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3173 {
3174 struct vcpu_svm *svm = to_svm(vcpu);
3175
3176 switch (msr_info->index) {
3177 case MSR_IA32_TSC: {
3178 msr_info->data = svm->vmcb->control.tsc_offset +
3179 svm_scale_tsc(vcpu, rdtsc());
3180
3181 break;
3182 }
3183 case MSR_STAR:
3184 msr_info->data = svm->vmcb->save.star;
3185 break;
3186 #ifdef CONFIG_X86_64
3187 case MSR_LSTAR:
3188 msr_info->data = svm->vmcb->save.lstar;
3189 break;
3190 case MSR_CSTAR:
3191 msr_info->data = svm->vmcb->save.cstar;
3192 break;
3193 case MSR_KERNEL_GS_BASE:
3194 msr_info->data = svm->vmcb->save.kernel_gs_base;
3195 break;
3196 case MSR_SYSCALL_MASK:
3197 msr_info->data = svm->vmcb->save.sfmask;
3198 break;
3199 #endif
3200 case MSR_IA32_SYSENTER_CS:
3201 msr_info->data = svm->vmcb->save.sysenter_cs;
3202 break;
3203 case MSR_IA32_SYSENTER_EIP:
3204 msr_info->data = svm->sysenter_eip;
3205 break;
3206 case MSR_IA32_SYSENTER_ESP:
3207 msr_info->data = svm->sysenter_esp;
3208 break;
3209 /*
3210 * Nobody will change the following 5 values in the VMCB so we can
3211 * safely return them on rdmsr. They will always be 0 until LBRV is
3212 * implemented.
3213 */
3214 case MSR_IA32_DEBUGCTLMSR:
3215 msr_info->data = svm->vmcb->save.dbgctl;
3216 break;
3217 case MSR_IA32_LASTBRANCHFROMIP:
3218 msr_info->data = svm->vmcb->save.br_from;
3219 break;
3220 case MSR_IA32_LASTBRANCHTOIP:
3221 msr_info->data = svm->vmcb->save.br_to;
3222 break;
3223 case MSR_IA32_LASTINTFROMIP:
3224 msr_info->data = svm->vmcb->save.last_excp_from;
3225 break;
3226 case MSR_IA32_LASTINTTOIP:
3227 msr_info->data = svm->vmcb->save.last_excp_to;
3228 break;
3229 case MSR_VM_HSAVE_PA:
3230 msr_info->data = svm->nested.hsave_msr;
3231 break;
3232 case MSR_VM_CR:
3233 msr_info->data = svm->nested.vm_cr_msr;
3234 break;
3235 case MSR_IA32_UCODE_REV:
3236 msr_info->data = 0x01000065;
3237 break;
3238 default:
3239 return kvm_get_msr_common(vcpu, msr_info);
3240 }
3241 return 0;
3242 }
3243
3244 static int rdmsr_interception(struct vcpu_svm *svm)
3245 {
3246 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3247 struct msr_data msr_info;
3248
3249 msr_info.index = ecx;
3250 msr_info.host_initiated = false;
3251 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3252 trace_kvm_msr_read_ex(ecx);
3253 kvm_inject_gp(&svm->vcpu, 0);
3254 } else {
3255 trace_kvm_msr_read(ecx, msr_info.data);
3256
3257 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3258 msr_info.data & 0xffffffff);
3259 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3260 msr_info.data >> 32);
3261 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3262 skip_emulated_instruction(&svm->vcpu);
3263 }
3264 return 1;
3265 }
3266
3267 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3268 {
3269 struct vcpu_svm *svm = to_svm(vcpu);
3270 int svm_dis, chg_mask;
3271
3272 if (data & ~SVM_VM_CR_VALID_MASK)
3273 return 1;
3274
3275 chg_mask = SVM_VM_CR_VALID_MASK;
3276
3277 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3278 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3279
3280 svm->nested.vm_cr_msr &= ~chg_mask;
3281 svm->nested.vm_cr_msr |= (data & chg_mask);
3282
3283 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3284
3285 /* check for svm_disable while efer.svme is set */
3286 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3287 return 1;
3288
3289 return 0;
3290 }
3291
3292 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3293 {
3294 struct vcpu_svm *svm = to_svm(vcpu);
3295
3296 u32 ecx = msr->index;
3297 u64 data = msr->data;
3298 switch (ecx) {
3299 case MSR_IA32_TSC:
3300 kvm_write_tsc(vcpu, msr);
3301 break;
3302 case MSR_STAR:
3303 svm->vmcb->save.star = data;
3304 break;
3305 #ifdef CONFIG_X86_64
3306 case MSR_LSTAR:
3307 svm->vmcb->save.lstar = data;
3308 break;
3309 case MSR_CSTAR:
3310 svm->vmcb->save.cstar = data;
3311 break;
3312 case MSR_KERNEL_GS_BASE:
3313 svm->vmcb->save.kernel_gs_base = data;
3314 break;
3315 case MSR_SYSCALL_MASK:
3316 svm->vmcb->save.sfmask = data;
3317 break;
3318 #endif
3319 case MSR_IA32_SYSENTER_CS:
3320 svm->vmcb->save.sysenter_cs = data;
3321 break;
3322 case MSR_IA32_SYSENTER_EIP:
3323 svm->sysenter_eip = data;
3324 svm->vmcb->save.sysenter_eip = data;
3325 break;
3326 case MSR_IA32_SYSENTER_ESP:
3327 svm->sysenter_esp = data;
3328 svm->vmcb->save.sysenter_esp = data;
3329 break;
3330 case MSR_IA32_DEBUGCTLMSR:
3331 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3332 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3333 __func__, data);
3334 break;
3335 }
3336 if (data & DEBUGCTL_RESERVED_BITS)
3337 return 1;
3338
3339 svm->vmcb->save.dbgctl = data;
3340 mark_dirty(svm->vmcb, VMCB_LBR);
3341 if (data & (1ULL<<0))
3342 svm_enable_lbrv(svm);
3343 else
3344 svm_disable_lbrv(svm);
3345 break;
3346 case MSR_VM_HSAVE_PA:
3347 svm->nested.hsave_msr = data;
3348 break;
3349 case MSR_VM_CR:
3350 return svm_set_vm_cr(vcpu, data);
3351 case MSR_VM_IGNNE:
3352 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3353 break;
3354 case MSR_IA32_CR_PAT:
3355 if (npt_enabled) {
3356 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3357 return 1;
3358 vcpu->arch.pat = data;
3359 svm_set_guest_pat(svm, &svm->vmcb->save.g_pat);
3360 mark_dirty(svm->vmcb, VMCB_NPT);
3361 break;
3362 }
3363 /* fall through */
3364 default:
3365 return kvm_set_msr_common(vcpu, msr);
3366 }
3367 return 0;
3368 }
3369
3370 static int wrmsr_interception(struct vcpu_svm *svm)
3371 {
3372 struct msr_data msr;
3373 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3374 u64 data = kvm_read_edx_eax(&svm->vcpu);
3375
3376 msr.data = data;
3377 msr.index = ecx;
3378 msr.host_initiated = false;
3379
3380 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3381 if (kvm_set_msr(&svm->vcpu, &msr)) {
3382 trace_kvm_msr_write_ex(ecx, data);
3383 kvm_inject_gp(&svm->vcpu, 0);
3384 } else {
3385 trace_kvm_msr_write(ecx, data);
3386 skip_emulated_instruction(&svm->vcpu);
3387 }
3388 return 1;
3389 }
3390
3391 static int msr_interception(struct vcpu_svm *svm)
3392 {
3393 if (svm->vmcb->control.exit_info_1)
3394 return wrmsr_interception(svm);
3395 else
3396 return rdmsr_interception(svm);
3397 }
3398
3399 static int interrupt_window_interception(struct vcpu_svm *svm)
3400 {
3401 struct kvm_run *kvm_run = svm->vcpu.run;
3402
3403 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3404 svm_clear_vintr(svm);
3405 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3406 mark_dirty(svm->vmcb, VMCB_INTR);
3407 ++svm->vcpu.stat.irq_window_exits;
3408 /*
3409 * If the user space waits to inject interrupts, exit as soon as
3410 * possible
3411 */
3412 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3413 kvm_run->request_interrupt_window &&
3414 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3415 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3416 return 0;
3417 }
3418
3419 return 1;
3420 }
3421
3422 static int pause_interception(struct vcpu_svm *svm)
3423 {
3424 kvm_vcpu_on_spin(&(svm->vcpu));
3425 return 1;
3426 }
3427
3428 static int nop_interception(struct vcpu_svm *svm)
3429 {
3430 skip_emulated_instruction(&(svm->vcpu));
3431 return 1;
3432 }
3433
3434 static int monitor_interception(struct vcpu_svm *svm)
3435 {
3436 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3437 return nop_interception(svm);
3438 }
3439
3440 static int mwait_interception(struct vcpu_svm *svm)
3441 {
3442 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3443 return nop_interception(svm);
3444 }
3445
3446 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3447 [SVM_EXIT_READ_CR0] = cr_interception,
3448 [SVM_EXIT_READ_CR3] = cr_interception,
3449 [SVM_EXIT_READ_CR4] = cr_interception,
3450 [SVM_EXIT_READ_CR8] = cr_interception,
3451 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3452 [SVM_EXIT_WRITE_CR0] = cr_interception,
3453 [SVM_EXIT_WRITE_CR3] = cr_interception,
3454 [SVM_EXIT_WRITE_CR4] = cr_interception,
3455 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3456 [SVM_EXIT_READ_DR0] = dr_interception,
3457 [SVM_EXIT_READ_DR1] = dr_interception,
3458 [SVM_EXIT_READ_DR2] = dr_interception,
3459 [SVM_EXIT_READ_DR3] = dr_interception,
3460 [SVM_EXIT_READ_DR4] = dr_interception,
3461 [SVM_EXIT_READ_DR5] = dr_interception,
3462 [SVM_EXIT_READ_DR6] = dr_interception,
3463 [SVM_EXIT_READ_DR7] = dr_interception,
3464 [SVM_EXIT_WRITE_DR0] = dr_interception,
3465 [SVM_EXIT_WRITE_DR1] = dr_interception,
3466 [SVM_EXIT_WRITE_DR2] = dr_interception,
3467 [SVM_EXIT_WRITE_DR3] = dr_interception,
3468 [SVM_EXIT_WRITE_DR4] = dr_interception,
3469 [SVM_EXIT_WRITE_DR5] = dr_interception,
3470 [SVM_EXIT_WRITE_DR6] = dr_interception,
3471 [SVM_EXIT_WRITE_DR7] = dr_interception,
3472 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3473 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3474 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3475 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3476 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3477 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3478 [SVM_EXIT_INTR] = intr_interception,
3479 [SVM_EXIT_NMI] = nmi_interception,
3480 [SVM_EXIT_SMI] = nop_on_interception,
3481 [SVM_EXIT_INIT] = nop_on_interception,
3482 [SVM_EXIT_VINTR] = interrupt_window_interception,
3483 [SVM_EXIT_RDPMC] = rdpmc_interception,
3484 [SVM_EXIT_CPUID] = cpuid_interception,
3485 [SVM_EXIT_IRET] = iret_interception,
3486 [SVM_EXIT_INVD] = emulate_on_interception,
3487 [SVM_EXIT_PAUSE] = pause_interception,
3488 [SVM_EXIT_HLT] = halt_interception,
3489 [SVM_EXIT_INVLPG] = invlpg_interception,
3490 [SVM_EXIT_INVLPGA] = invlpga_interception,
3491 [SVM_EXIT_IOIO] = io_interception,
3492 [SVM_EXIT_MSR] = msr_interception,
3493 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3494 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3495 [SVM_EXIT_VMRUN] = vmrun_interception,
3496 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3497 [SVM_EXIT_VMLOAD] = vmload_interception,
3498 [SVM_EXIT_VMSAVE] = vmsave_interception,
3499 [SVM_EXIT_STGI] = stgi_interception,
3500 [SVM_EXIT_CLGI] = clgi_interception,
3501 [SVM_EXIT_SKINIT] = skinit_interception,
3502 [SVM_EXIT_WBINVD] = wbinvd_interception,
3503 [SVM_EXIT_MONITOR] = monitor_interception,
3504 [SVM_EXIT_MWAIT] = mwait_interception,
3505 [SVM_EXIT_XSETBV] = xsetbv_interception,
3506 [SVM_EXIT_NPF] = pf_interception,
3507 [SVM_EXIT_RSM] = emulate_on_interception,
3508 };
3509
3510 static void dump_vmcb(struct kvm_vcpu *vcpu)
3511 {
3512 struct vcpu_svm *svm = to_svm(vcpu);
3513 struct vmcb_control_area *control = &svm->vmcb->control;
3514 struct vmcb_save_area *save = &svm->vmcb->save;
3515
3516 pr_err("VMCB Control Area:\n");
3517 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3518 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3519 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3520 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3521 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3522 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3523 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3524 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3525 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3526 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3527 pr_err("%-20s%d\n", "asid:", control->asid);
3528 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3529 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3530 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3531 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3532 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3533 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3534 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3535 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3536 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3537 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3538 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3539 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3540 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3541 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3542 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3543 pr_err("VMCB State Save Area:\n");
3544 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3545 "es:",
3546 save->es.selector, save->es.attrib,
3547 save->es.limit, save->es.base);
3548 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3549 "cs:",
3550 save->cs.selector, save->cs.attrib,
3551 save->cs.limit, save->cs.base);
3552 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3553 "ss:",
3554 save->ss.selector, save->ss.attrib,
3555 save->ss.limit, save->ss.base);
3556 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3557 "ds:",
3558 save->ds.selector, save->ds.attrib,
3559 save->ds.limit, save->ds.base);
3560 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3561 "fs:",
3562 save->fs.selector, save->fs.attrib,
3563 save->fs.limit, save->fs.base);
3564 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3565 "gs:",
3566 save->gs.selector, save->gs.attrib,
3567 save->gs.limit, save->gs.base);
3568 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3569 "gdtr:",
3570 save->gdtr.selector, save->gdtr.attrib,
3571 save->gdtr.limit, save->gdtr.base);
3572 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3573 "ldtr:",
3574 save->ldtr.selector, save->ldtr.attrib,
3575 save->ldtr.limit, save->ldtr.base);
3576 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3577 "idtr:",
3578 save->idtr.selector, save->idtr.attrib,
3579 save->idtr.limit, save->idtr.base);
3580 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3581 "tr:",
3582 save->tr.selector, save->tr.attrib,
3583 save->tr.limit, save->tr.base);
3584 pr_err("cpl: %d efer: %016llx\n",
3585 save->cpl, save->efer);
3586 pr_err("%-15s %016llx %-13s %016llx\n",
3587 "cr0:", save->cr0, "cr2:", save->cr2);
3588 pr_err("%-15s %016llx %-13s %016llx\n",
3589 "cr3:", save->cr3, "cr4:", save->cr4);
3590 pr_err("%-15s %016llx %-13s %016llx\n",
3591 "dr6:", save->dr6, "dr7:", save->dr7);
3592 pr_err("%-15s %016llx %-13s %016llx\n",
3593 "rip:", save->rip, "rflags:", save->rflags);
3594 pr_err("%-15s %016llx %-13s %016llx\n",
3595 "rsp:", save->rsp, "rax:", save->rax);
3596 pr_err("%-15s %016llx %-13s %016llx\n",
3597 "star:", save->star, "lstar:", save->lstar);
3598 pr_err("%-15s %016llx %-13s %016llx\n",
3599 "cstar:", save->cstar, "sfmask:", save->sfmask);
3600 pr_err("%-15s %016llx %-13s %016llx\n",
3601 "kernel_gs_base:", save->kernel_gs_base,
3602 "sysenter_cs:", save->sysenter_cs);
3603 pr_err("%-15s %016llx %-13s %016llx\n",
3604 "sysenter_esp:", save->sysenter_esp,
3605 "sysenter_eip:", save->sysenter_eip);
3606 pr_err("%-15s %016llx %-13s %016llx\n",
3607 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3608 pr_err("%-15s %016llx %-13s %016llx\n",
3609 "br_from:", save->br_from, "br_to:", save->br_to);
3610 pr_err("%-15s %016llx %-13s %016llx\n",
3611 "excp_from:", save->last_excp_from,
3612 "excp_to:", save->last_excp_to);
3613 }
3614
3615 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3616 {
3617 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3618
3619 *info1 = control->exit_info_1;
3620 *info2 = control->exit_info_2;
3621 }
3622
3623 static int handle_exit(struct kvm_vcpu *vcpu)
3624 {
3625 struct vcpu_svm *svm = to_svm(vcpu);
3626 struct kvm_run *kvm_run = vcpu->run;
3627 u32 exit_code = svm->vmcb->control.exit_code;
3628
3629 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3630 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3631 if (npt_enabled)
3632 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3633
3634 if (unlikely(svm->nested.exit_required)) {
3635 nested_svm_vmexit(svm);
3636 svm->nested.exit_required = false;
3637
3638 return 1;
3639 }
3640
3641 if (is_guest_mode(vcpu)) {
3642 int vmexit;
3643
3644 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3645 svm->vmcb->control.exit_info_1,
3646 svm->vmcb->control.exit_info_2,
3647 svm->vmcb->control.exit_int_info,
3648 svm->vmcb->control.exit_int_info_err,
3649 KVM_ISA_SVM);
3650
3651 vmexit = nested_svm_exit_special(svm);
3652
3653 if (vmexit == NESTED_EXIT_CONTINUE)
3654 vmexit = nested_svm_exit_handled(svm);
3655
3656 if (vmexit == NESTED_EXIT_DONE)
3657 return 1;
3658 }
3659
3660 svm_complete_interrupts(svm);
3661
3662 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3663 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3664 kvm_run->fail_entry.hardware_entry_failure_reason
3665 = svm->vmcb->control.exit_code;
3666 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3667 dump_vmcb(vcpu);
3668 return 0;
3669 }
3670
3671 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3672 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3673 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3674 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3675 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3676 "exit_code 0x%x\n",
3677 __func__, svm->vmcb->control.exit_int_info,
3678 exit_code);
3679
3680 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3681 || !svm_exit_handlers[exit_code]) {
3682 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3683 kvm_queue_exception(vcpu, UD_VECTOR);
3684 return 1;
3685 }
3686
3687 return svm_exit_handlers[exit_code](svm);
3688 }
3689
3690 static void reload_tss(struct kvm_vcpu *vcpu)
3691 {
3692 int cpu = raw_smp_processor_id();
3693
3694 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3695 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3696 load_TR_desc();
3697 }
3698
3699 static void pre_svm_run(struct vcpu_svm *svm)
3700 {
3701 int cpu = raw_smp_processor_id();
3702
3703 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3704
3705 /* FIXME: handle wraparound of asid_generation */
3706 if (svm->asid_generation != sd->asid_generation)
3707 new_asid(svm, sd);
3708 }
3709
3710 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3711 {
3712 struct vcpu_svm *svm = to_svm(vcpu);
3713
3714 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3715 vcpu->arch.hflags |= HF_NMI_MASK;
3716 set_intercept(svm, INTERCEPT_IRET);
3717 ++vcpu->stat.nmi_injections;
3718 }
3719
3720 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3721 {
3722 struct vmcb_control_area *control;
3723
3724 control = &svm->vmcb->control;
3725 control->int_vector = irq;
3726 control->int_ctl &= ~V_INTR_PRIO_MASK;
3727 control->int_ctl |= V_IRQ_MASK |
3728 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3729 mark_dirty(svm->vmcb, VMCB_INTR);
3730 }
3731
3732 static void svm_set_irq(struct kvm_vcpu *vcpu)
3733 {
3734 struct vcpu_svm *svm = to_svm(vcpu);
3735
3736 BUG_ON(!(gif_set(svm)));
3737
3738 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3739 ++vcpu->stat.irq_injections;
3740
3741 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3742 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3743 }
3744
3745 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3746 {
3747 struct vcpu_svm *svm = to_svm(vcpu);
3748
3749 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3750 return;
3751
3752 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3753
3754 if (irr == -1)
3755 return;
3756
3757 if (tpr >= irr)
3758 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3759 }
3760
3761 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3762 {
3763 return;
3764 }
3765
3766 static int svm_vm_has_apicv(struct kvm *kvm)
3767 {
3768 return 0;
3769 }
3770
3771 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3772 {
3773 return;
3774 }
3775
3776 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3777 {
3778 return;
3779 }
3780
3781 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3782 {
3783 struct vcpu_svm *svm = to_svm(vcpu);
3784 struct vmcb *vmcb = svm->vmcb;
3785 int ret;
3786 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3787 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3788 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3789
3790 return ret;
3791 }
3792
3793 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3794 {
3795 struct vcpu_svm *svm = to_svm(vcpu);
3796
3797 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3798 }
3799
3800 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3801 {
3802 struct vcpu_svm *svm = to_svm(vcpu);
3803
3804 if (masked) {
3805 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3806 set_intercept(svm, INTERCEPT_IRET);
3807 } else {
3808 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3809 clr_intercept(svm, INTERCEPT_IRET);
3810 }
3811 }
3812
3813 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3814 {
3815 struct vcpu_svm *svm = to_svm(vcpu);
3816 struct vmcb *vmcb = svm->vmcb;
3817 int ret;
3818
3819 if (!gif_set(svm) ||
3820 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3821 return 0;
3822
3823 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3824
3825 if (is_guest_mode(vcpu))
3826 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3827
3828 return ret;
3829 }
3830
3831 static void enable_irq_window(struct kvm_vcpu *vcpu)
3832 {
3833 struct vcpu_svm *svm = to_svm(vcpu);
3834
3835 /*
3836 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3837 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3838 * get that intercept, this function will be called again though and
3839 * we'll get the vintr intercept.
3840 */
3841 if (gif_set(svm) && nested_svm_intr(svm)) {
3842 svm_set_vintr(svm);
3843 svm_inject_irq(svm, 0x0);
3844 }
3845 }
3846
3847 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3848 {
3849 struct vcpu_svm *svm = to_svm(vcpu);
3850
3851 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3852 == HF_NMI_MASK)
3853 return; /* IRET will cause a vm exit */
3854
3855 /*
3856 * Something prevents NMI from been injected. Single step over possible
3857 * problem (IRET or exception injection or interrupt shadow)
3858 */
3859 svm->nmi_singlestep = true;
3860 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3861 update_db_bp_intercept(vcpu);
3862 }
3863
3864 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3865 {
3866 return 0;
3867 }
3868
3869 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3870 {
3871 struct vcpu_svm *svm = to_svm(vcpu);
3872
3873 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3874 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3875 else
3876 svm->asid_generation--;
3877 }
3878
3879 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3880 {
3881 }
3882
3883 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3884 {
3885 struct vcpu_svm *svm = to_svm(vcpu);
3886
3887 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3888 return;
3889
3890 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3891 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3892 kvm_set_cr8(vcpu, cr8);
3893 }
3894 }
3895
3896 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3897 {
3898 struct vcpu_svm *svm = to_svm(vcpu);
3899 u64 cr8;
3900
3901 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3902 return;
3903
3904 cr8 = kvm_get_cr8(vcpu);
3905 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3906 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3907 }
3908
3909 static void svm_complete_interrupts(struct vcpu_svm *svm)
3910 {
3911 u8 vector;
3912 int type;
3913 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3914 unsigned int3_injected = svm->int3_injected;
3915
3916 svm->int3_injected = 0;
3917
3918 /*
3919 * If we've made progress since setting HF_IRET_MASK, we've
3920 * executed an IRET and can allow NMI injection.
3921 */
3922 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3923 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3924 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3925 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3926 }
3927
3928 svm->vcpu.arch.nmi_injected = false;
3929 kvm_clear_exception_queue(&svm->vcpu);
3930 kvm_clear_interrupt_queue(&svm->vcpu);
3931
3932 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3933 return;
3934
3935 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3936
3937 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3938 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3939
3940 switch (type) {
3941 case SVM_EXITINTINFO_TYPE_NMI:
3942 svm->vcpu.arch.nmi_injected = true;
3943 break;
3944 case SVM_EXITINTINFO_TYPE_EXEPT:
3945 /*
3946 * In case of software exceptions, do not reinject the vector,
3947 * but re-execute the instruction instead. Rewind RIP first
3948 * if we emulated INT3 before.
3949 */
3950 if (kvm_exception_is_soft(vector)) {
3951 if (vector == BP_VECTOR && int3_injected &&
3952 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3953 kvm_rip_write(&svm->vcpu,
3954 kvm_rip_read(&svm->vcpu) -
3955 int3_injected);
3956 break;
3957 }
3958 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3959 u32 err = svm->vmcb->control.exit_int_info_err;
3960 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3961
3962 } else
3963 kvm_requeue_exception(&svm->vcpu, vector);
3964 break;
3965 case SVM_EXITINTINFO_TYPE_INTR:
3966 kvm_queue_interrupt(&svm->vcpu, vector, false);
3967 break;
3968 default:
3969 break;
3970 }
3971 }
3972
3973 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3974 {
3975 struct vcpu_svm *svm = to_svm(vcpu);
3976 struct vmcb_control_area *control = &svm->vmcb->control;
3977
3978 control->exit_int_info = control->event_inj;
3979 control->exit_int_info_err = control->event_inj_err;
3980 control->event_inj = 0;
3981 svm_complete_interrupts(svm);
3982 }
3983
3984 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3985 {
3986 struct vcpu_svm *svm = to_svm(vcpu);
3987
3988 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3989 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3990 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3991
3992 /*
3993 * A vmexit emulation is required before the vcpu can be executed
3994 * again.
3995 */
3996 if (unlikely(svm->nested.exit_required))
3997 return;
3998
3999 pre_svm_run(svm);
4000
4001 sync_lapic_to_cr8(vcpu);
4002
4003 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4004
4005 clgi();
4006
4007 local_irq_enable();
4008
4009 asm volatile (
4010 "push %%" _ASM_BP "; \n\t"
4011 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4012 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4013 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4014 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4015 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4016 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4017 #ifdef CONFIG_X86_64
4018 "mov %c[r8](%[svm]), %%r8 \n\t"
4019 "mov %c[r9](%[svm]), %%r9 \n\t"
4020 "mov %c[r10](%[svm]), %%r10 \n\t"
4021 "mov %c[r11](%[svm]), %%r11 \n\t"
4022 "mov %c[r12](%[svm]), %%r12 \n\t"
4023 "mov %c[r13](%[svm]), %%r13 \n\t"
4024 "mov %c[r14](%[svm]), %%r14 \n\t"
4025 "mov %c[r15](%[svm]), %%r15 \n\t"
4026 #endif
4027
4028 /* Enter guest mode */
4029 "push %%" _ASM_AX " \n\t"
4030 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4031 __ex(SVM_VMLOAD) "\n\t"
4032 __ex(SVM_VMRUN) "\n\t"
4033 __ex(SVM_VMSAVE) "\n\t"
4034 "pop %%" _ASM_AX " \n\t"
4035
4036 /* Save guest registers, load host registers */
4037 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4038 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4039 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4040 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4041 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4042 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4043 #ifdef CONFIG_X86_64
4044 "mov %%r8, %c[r8](%[svm]) \n\t"
4045 "mov %%r9, %c[r9](%[svm]) \n\t"
4046 "mov %%r10, %c[r10](%[svm]) \n\t"
4047 "mov %%r11, %c[r11](%[svm]) \n\t"
4048 "mov %%r12, %c[r12](%[svm]) \n\t"
4049 "mov %%r13, %c[r13](%[svm]) \n\t"
4050 "mov %%r14, %c[r14](%[svm]) \n\t"
4051 "mov %%r15, %c[r15](%[svm]) \n\t"
4052 #endif
4053 "pop %%" _ASM_BP
4054 :
4055 : [svm]"a"(svm),
4056 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4057 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4058 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4059 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4060 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4061 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4062 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4063 #ifdef CONFIG_X86_64
4064 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4065 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4066 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4067 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4068 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4069 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4070 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4071 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4072 #endif
4073 : "cc", "memory"
4074 #ifdef CONFIG_X86_64
4075 , "rbx", "rcx", "rdx", "rsi", "rdi"
4076 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4077 #else
4078 , "ebx", "ecx", "edx", "esi", "edi"
4079 #endif
4080 );
4081
4082 #ifdef CONFIG_X86_64
4083 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4084 #else
4085 loadsegment(fs, svm->host.fs);
4086 #ifndef CONFIG_X86_32_LAZY_GS
4087 loadsegment(gs, svm->host.gs);
4088 #endif
4089 #endif
4090
4091 reload_tss(vcpu);
4092
4093 local_irq_disable();
4094
4095 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4096 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4097 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4098 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4099
4100 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
4101
4102 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4103 kvm_before_handle_nmi(&svm->vcpu);
4104
4105 stgi();
4106
4107 /* Any pending NMI will happen here */
4108
4109 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4110 kvm_after_handle_nmi(&svm->vcpu);
4111
4112 sync_cr8_to_lapic(vcpu);
4113
4114 svm->next_rip = 0;
4115
4116 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4117
4118 /* if exit due to PF check for async PF */
4119 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4120 svm->apf_reason = kvm_read_and_reset_pf_reason();
4121
4122 if (npt_enabled) {
4123 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4124 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4125 }
4126
4127 /*
4128 * We need to handle MC intercepts here before the vcpu has a chance to
4129 * change the physical cpu
4130 */
4131 if (unlikely(svm->vmcb->control.exit_code ==
4132 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4133 svm_handle_mce(svm);
4134
4135 mark_all_clean(svm->vmcb);
4136 }
4137
4138 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4139 {
4140 struct vcpu_svm *svm = to_svm(vcpu);
4141
4142 svm->vmcb->save.cr3 = root;
4143 mark_dirty(svm->vmcb, VMCB_CR);
4144 svm_flush_tlb(vcpu);
4145 }
4146
4147 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4148 {
4149 struct vcpu_svm *svm = to_svm(vcpu);
4150
4151 svm->vmcb->control.nested_cr3 = root;
4152 mark_dirty(svm->vmcb, VMCB_NPT);
4153
4154 /* Also sync guest cr3 here in case we live migrate */
4155 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4156 mark_dirty(svm->vmcb, VMCB_CR);
4157
4158 svm_flush_tlb(vcpu);
4159 }
4160
4161 static int is_disabled(void)
4162 {
4163 u64 vm_cr;
4164
4165 rdmsrl(MSR_VM_CR, vm_cr);
4166 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4167 return 1;
4168
4169 return 0;
4170 }
4171
4172 static void
4173 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4174 {
4175 /*
4176 * Patch in the VMMCALL instruction:
4177 */
4178 hypercall[0] = 0x0f;
4179 hypercall[1] = 0x01;
4180 hypercall[2] = 0xd9;
4181 }
4182
4183 static void svm_check_processor_compat(void *rtn)
4184 {
4185 *(int *)rtn = 0;
4186 }
4187
4188 static bool svm_cpu_has_accelerated_tpr(void)
4189 {
4190 return false;
4191 }
4192
4193 static bool svm_has_high_real_mode_segbase(void)
4194 {
4195 return true;
4196 }
4197
4198 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4199 {
4200 }
4201
4202 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4203 {
4204 switch (func) {
4205 case 0x80000001:
4206 if (nested)
4207 entry->ecx |= (1 << 2); /* Set SVM bit */
4208 break;
4209 case 0x8000000A:
4210 entry->eax = 1; /* SVM revision 1 */
4211 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4212 ASID emulation to nested SVM */
4213 entry->ecx = 0; /* Reserved */
4214 entry->edx = 0; /* Per default do not support any
4215 additional features */
4216
4217 /* Support next_rip if host supports it */
4218 if (boot_cpu_has(X86_FEATURE_NRIPS))
4219 entry->edx |= SVM_FEATURE_NRIP;
4220
4221 /* Support NPT for the guest if enabled */
4222 if (npt_enabled)
4223 entry->edx |= SVM_FEATURE_NPT;
4224
4225 break;
4226 }
4227 }
4228
4229 static int svm_get_lpage_level(void)
4230 {
4231 return PT_PDPE_LEVEL;
4232 }
4233
4234 static bool svm_rdtscp_supported(void)
4235 {
4236 return false;
4237 }
4238
4239 static bool svm_invpcid_supported(void)
4240 {
4241 return false;
4242 }
4243
4244 static bool svm_mpx_supported(void)
4245 {
4246 return false;
4247 }
4248
4249 static bool svm_xsaves_supported(void)
4250 {
4251 return false;
4252 }
4253
4254 static bool svm_has_wbinvd_exit(void)
4255 {
4256 return true;
4257 }
4258
4259 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4260 {
4261 struct vcpu_svm *svm = to_svm(vcpu);
4262
4263 set_exception_intercept(svm, NM_VECTOR);
4264 update_cr0_intercept(svm);
4265 }
4266
4267 #define PRE_EX(exit) { .exit_code = (exit), \
4268 .stage = X86_ICPT_PRE_EXCEPT, }
4269 #define POST_EX(exit) { .exit_code = (exit), \
4270 .stage = X86_ICPT_POST_EXCEPT, }
4271 #define POST_MEM(exit) { .exit_code = (exit), \
4272 .stage = X86_ICPT_POST_MEMACCESS, }
4273
4274 static const struct __x86_intercept {
4275 u32 exit_code;
4276 enum x86_intercept_stage stage;
4277 } x86_intercept_map[] = {
4278 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4279 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4280 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4281 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4282 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4283 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4284 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4285 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4286 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4287 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4288 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4289 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4290 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4291 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4292 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4293 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4294 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4295 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4296 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4297 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4298 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4299 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4300 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4301 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4302 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4303 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4304 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4305 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4306 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4307 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4308 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4309 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4310 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4311 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4312 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4313 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4314 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4315 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4316 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4317 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4318 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4319 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4320 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4321 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4322 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4323 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4324 };
4325
4326 #undef PRE_EX
4327 #undef POST_EX
4328 #undef POST_MEM
4329
4330 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4331 struct x86_instruction_info *info,
4332 enum x86_intercept_stage stage)
4333 {
4334 struct vcpu_svm *svm = to_svm(vcpu);
4335 int vmexit, ret = X86EMUL_CONTINUE;
4336 struct __x86_intercept icpt_info;
4337 struct vmcb *vmcb = svm->vmcb;
4338
4339 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4340 goto out;
4341
4342 icpt_info = x86_intercept_map[info->intercept];
4343
4344 if (stage != icpt_info.stage)
4345 goto out;
4346
4347 switch (icpt_info.exit_code) {
4348 case SVM_EXIT_READ_CR0:
4349 if (info->intercept == x86_intercept_cr_read)
4350 icpt_info.exit_code += info->modrm_reg;
4351 break;
4352 case SVM_EXIT_WRITE_CR0: {
4353 unsigned long cr0, val;
4354 u64 intercept;
4355
4356 if (info->intercept == x86_intercept_cr_write)
4357 icpt_info.exit_code += info->modrm_reg;
4358
4359 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4360 info->intercept == x86_intercept_clts)
4361 break;
4362
4363 intercept = svm->nested.intercept;
4364
4365 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4366 break;
4367
4368 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4369 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4370
4371 if (info->intercept == x86_intercept_lmsw) {
4372 cr0 &= 0xfUL;
4373 val &= 0xfUL;
4374 /* lmsw can't clear PE - catch this here */
4375 if (cr0 & X86_CR0_PE)
4376 val |= X86_CR0_PE;
4377 }
4378
4379 if (cr0 ^ val)
4380 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4381
4382 break;
4383 }
4384 case SVM_EXIT_READ_DR0:
4385 case SVM_EXIT_WRITE_DR0:
4386 icpt_info.exit_code += info->modrm_reg;
4387 break;
4388 case SVM_EXIT_MSR:
4389 if (info->intercept == x86_intercept_wrmsr)
4390 vmcb->control.exit_info_1 = 1;
4391 else
4392 vmcb->control.exit_info_1 = 0;
4393 break;
4394 case SVM_EXIT_PAUSE:
4395 /*
4396 * We get this for NOP only, but pause
4397 * is rep not, check this here
4398 */
4399 if (info->rep_prefix != REPE_PREFIX)
4400 goto out;
4401 case SVM_EXIT_IOIO: {
4402 u64 exit_info;
4403 u32 bytes;
4404
4405 if (info->intercept == x86_intercept_in ||
4406 info->intercept == x86_intercept_ins) {
4407 exit_info = ((info->src_val & 0xffff) << 16) |
4408 SVM_IOIO_TYPE_MASK;
4409 bytes = info->dst_bytes;
4410 } else {
4411 exit_info = (info->dst_val & 0xffff) << 16;
4412 bytes = info->src_bytes;
4413 }
4414
4415 if (info->intercept == x86_intercept_outs ||
4416 info->intercept == x86_intercept_ins)
4417 exit_info |= SVM_IOIO_STR_MASK;
4418
4419 if (info->rep_prefix)
4420 exit_info |= SVM_IOIO_REP_MASK;
4421
4422 bytes = min(bytes, 4u);
4423
4424 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4425
4426 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4427
4428 vmcb->control.exit_info_1 = exit_info;
4429 vmcb->control.exit_info_2 = info->next_rip;
4430
4431 break;
4432 }
4433 default:
4434 break;
4435 }
4436
4437 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4438 if (static_cpu_has(X86_FEATURE_NRIPS))
4439 vmcb->control.next_rip = info->next_rip;
4440 vmcb->control.exit_code = icpt_info.exit_code;
4441 vmexit = nested_svm_exit_handled(svm);
4442
4443 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4444 : X86EMUL_CONTINUE;
4445
4446 out:
4447 return ret;
4448 }
4449
4450 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4451 {
4452 local_irq_enable();
4453 }
4454
4455 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4456 {
4457 }
4458
4459 static struct kvm_x86_ops svm_x86_ops = {
4460 .cpu_has_kvm_support = has_svm,
4461 .disabled_by_bios = is_disabled,
4462 .hardware_setup = svm_hardware_setup,
4463 .hardware_unsetup = svm_hardware_unsetup,
4464 .check_processor_compatibility = svm_check_processor_compat,
4465 .hardware_enable = svm_hardware_enable,
4466 .hardware_disable = svm_hardware_disable,
4467 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4468 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4469
4470 .vcpu_create = svm_create_vcpu,
4471 .vcpu_free = svm_free_vcpu,
4472 .vcpu_reset = svm_vcpu_reset,
4473
4474 .prepare_guest_switch = svm_prepare_guest_switch,
4475 .vcpu_load = svm_vcpu_load,
4476 .vcpu_put = svm_vcpu_put,
4477
4478 .update_db_bp_intercept = update_db_bp_intercept,
4479 .get_msr = svm_get_msr,
4480 .set_msr = svm_set_msr,
4481 .get_segment_base = svm_get_segment_base,
4482 .get_segment = svm_get_segment,
4483 .set_segment = svm_set_segment,
4484 .get_cpl = svm_get_cpl,
4485 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4486 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4487 .decache_cr3 = svm_decache_cr3,
4488 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4489 .set_cr0 = svm_set_cr0,
4490 .set_cr3 = svm_set_cr3,
4491 .set_cr4 = svm_set_cr4,
4492 .set_efer = svm_set_efer,
4493 .get_idt = svm_get_idt,
4494 .set_idt = svm_set_idt,
4495 .get_gdt = svm_get_gdt,
4496 .set_gdt = svm_set_gdt,
4497 .get_dr6 = svm_get_dr6,
4498 .set_dr6 = svm_set_dr6,
4499 .set_dr7 = svm_set_dr7,
4500 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4501 .cache_reg = svm_cache_reg,
4502 .get_rflags = svm_get_rflags,
4503 .set_rflags = svm_set_rflags,
4504 .fpu_activate = svm_fpu_activate,
4505 .fpu_deactivate = svm_fpu_deactivate,
4506
4507 .tlb_flush = svm_flush_tlb,
4508
4509 .run = svm_vcpu_run,
4510 .handle_exit = handle_exit,
4511 .skip_emulated_instruction = skip_emulated_instruction,
4512 .set_interrupt_shadow = svm_set_interrupt_shadow,
4513 .get_interrupt_shadow = svm_get_interrupt_shadow,
4514 .patch_hypercall = svm_patch_hypercall,
4515 .set_irq = svm_set_irq,
4516 .set_nmi = svm_inject_nmi,
4517 .queue_exception = svm_queue_exception,
4518 .cancel_injection = svm_cancel_injection,
4519 .interrupt_allowed = svm_interrupt_allowed,
4520 .nmi_allowed = svm_nmi_allowed,
4521 .get_nmi_mask = svm_get_nmi_mask,
4522 .set_nmi_mask = svm_set_nmi_mask,
4523 .enable_nmi_window = enable_nmi_window,
4524 .enable_irq_window = enable_irq_window,
4525 .update_cr8_intercept = update_cr8_intercept,
4526 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4527 .vm_has_apicv = svm_vm_has_apicv,
4528 .load_eoi_exitmap = svm_load_eoi_exitmap,
4529 .sync_pir_to_irr = svm_sync_pir_to_irr,
4530
4531 .set_tss_addr = svm_set_tss_addr,
4532 .get_tdp_level = get_npt_level,
4533 .get_mt_mask = svm_get_mt_mask,
4534
4535 .get_exit_info = svm_get_exit_info,
4536
4537 .get_lpage_level = svm_get_lpage_level,
4538
4539 .cpuid_update = svm_cpuid_update,
4540
4541 .rdtscp_supported = svm_rdtscp_supported,
4542 .invpcid_supported = svm_invpcid_supported,
4543 .mpx_supported = svm_mpx_supported,
4544 .xsaves_supported = svm_xsaves_supported,
4545
4546 .set_supported_cpuid = svm_set_supported_cpuid,
4547
4548 .has_wbinvd_exit = svm_has_wbinvd_exit,
4549
4550 .set_tsc_khz = svm_set_tsc_khz,
4551 .read_tsc_offset = svm_read_tsc_offset,
4552 .write_tsc_offset = svm_write_tsc_offset,
4553 .adjust_tsc_offset = svm_adjust_tsc_offset,
4554 .compute_tsc_offset = svm_compute_tsc_offset,
4555 .read_l1_tsc = svm_read_l1_tsc,
4556
4557 .set_tdp_cr3 = set_tdp_cr3,
4558
4559 .check_intercept = svm_check_intercept,
4560 .handle_external_intr = svm_handle_external_intr,
4561
4562 .sched_in = svm_sched_in,
4563
4564 .pmu_ops = &amd_pmu_ops,
4565 };
4566
4567 static int __init svm_init(void)
4568 {
4569 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4570 __alignof__(struct vcpu_svm), THIS_MODULE);
4571 }
4572
4573 static void __exit svm_exit(void)
4574 {
4575 kvm_exit();
4576 }
4577
4578 module_init(svm_init)
4579 module_exit(svm_exit)
Linux kernel - Deliverables
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