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KVM: SVM: Add clean-bit for DR6 and DR7
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_CR, /* CR0, CR3, CR4, EFER */
196 VMCB_DR, /* DR6, DR7 */
197 VMCB_DIRTY_MAX,
198 };
199
200 /* TPR is always written before VMRUN */
201 #define VMCB_ALWAYS_DIRTY_MASK (1U << VMCB_INTR)
202
203 static inline void mark_all_dirty(struct vmcb *vmcb)
204 {
205 vmcb->control.clean = 0;
206 }
207
208 static inline void mark_all_clean(struct vmcb *vmcb)
209 {
210 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
211 & ~VMCB_ALWAYS_DIRTY_MASK;
212 }
213
214 static inline void mark_dirty(struct vmcb *vmcb, int bit)
215 {
216 vmcb->control.clean &= ~(1 << bit);
217 }
218
219 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
220 {
221 return container_of(vcpu, struct vcpu_svm, vcpu);
222 }
223
224 static void recalc_intercepts(struct vcpu_svm *svm)
225 {
226 struct vmcb_control_area *c, *h;
227 struct nested_state *g;
228
229 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
230
231 if (!is_guest_mode(&svm->vcpu))
232 return;
233
234 c = &svm->vmcb->control;
235 h = &svm->nested.hsave->control;
236 g = &svm->nested;
237
238 c->intercept_cr = h->intercept_cr | g->intercept_cr;
239 c->intercept_dr = h->intercept_dr | g->intercept_dr;
240 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
241 c->intercept = h->intercept | g->intercept;
242 }
243
244 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
245 {
246 if (is_guest_mode(&svm->vcpu))
247 return svm->nested.hsave;
248 else
249 return svm->vmcb;
250 }
251
252 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
253 {
254 struct vmcb *vmcb = get_host_vmcb(svm);
255
256 vmcb->control.intercept_cr |= (1U << bit);
257
258 recalc_intercepts(svm);
259 }
260
261 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
262 {
263 struct vmcb *vmcb = get_host_vmcb(svm);
264
265 vmcb->control.intercept_cr &= ~(1U << bit);
266
267 recalc_intercepts(svm);
268 }
269
270 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
271 {
272 struct vmcb *vmcb = get_host_vmcb(svm);
273
274 return vmcb->control.intercept_cr & (1U << bit);
275 }
276
277 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
278 {
279 struct vmcb *vmcb = get_host_vmcb(svm);
280
281 vmcb->control.intercept_dr |= (1U << bit);
282
283 recalc_intercepts(svm);
284 }
285
286 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
287 {
288 struct vmcb *vmcb = get_host_vmcb(svm);
289
290 vmcb->control.intercept_dr &= ~(1U << bit);
291
292 recalc_intercepts(svm);
293 }
294
295 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
296 {
297 struct vmcb *vmcb = get_host_vmcb(svm);
298
299 vmcb->control.intercept_exceptions |= (1U << bit);
300
301 recalc_intercepts(svm);
302 }
303
304 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
305 {
306 struct vmcb *vmcb = get_host_vmcb(svm);
307
308 vmcb->control.intercept_exceptions &= ~(1U << bit);
309
310 recalc_intercepts(svm);
311 }
312
313 static inline void set_intercept(struct vcpu_svm *svm, int bit)
314 {
315 struct vmcb *vmcb = get_host_vmcb(svm);
316
317 vmcb->control.intercept |= (1ULL << bit);
318
319 recalc_intercepts(svm);
320 }
321
322 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
323 {
324 struct vmcb *vmcb = get_host_vmcb(svm);
325
326 vmcb->control.intercept &= ~(1ULL << bit);
327
328 recalc_intercepts(svm);
329 }
330
331 static inline void enable_gif(struct vcpu_svm *svm)
332 {
333 svm->vcpu.arch.hflags |= HF_GIF_MASK;
334 }
335
336 static inline void disable_gif(struct vcpu_svm *svm)
337 {
338 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
339 }
340
341 static inline bool gif_set(struct vcpu_svm *svm)
342 {
343 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
344 }
345
346 static unsigned long iopm_base;
347
348 struct kvm_ldttss_desc {
349 u16 limit0;
350 u16 base0;
351 unsigned base1:8, type:5, dpl:2, p:1;
352 unsigned limit1:4, zero0:3, g:1, base2:8;
353 u32 base3;
354 u32 zero1;
355 } __attribute__((packed));
356
357 struct svm_cpu_data {
358 int cpu;
359
360 u64 asid_generation;
361 u32 max_asid;
362 u32 next_asid;
363 struct kvm_ldttss_desc *tss_desc;
364
365 struct page *save_area;
366 };
367
368 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
369 static uint32_t svm_features;
370
371 struct svm_init_data {
372 int cpu;
373 int r;
374 };
375
376 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
377
378 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
379 #define MSRS_RANGE_SIZE 2048
380 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
381
382 static u32 svm_msrpm_offset(u32 msr)
383 {
384 u32 offset;
385 int i;
386
387 for (i = 0; i < NUM_MSR_MAPS; i++) {
388 if (msr < msrpm_ranges[i] ||
389 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
390 continue;
391
392 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
393 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
394
395 /* Now we have the u8 offset - but need the u32 offset */
396 return offset / 4;
397 }
398
399 /* MSR not in any range */
400 return MSR_INVALID;
401 }
402
403 #define MAX_INST_SIZE 15
404
405 static inline void clgi(void)
406 {
407 asm volatile (__ex(SVM_CLGI));
408 }
409
410 static inline void stgi(void)
411 {
412 asm volatile (__ex(SVM_STGI));
413 }
414
415 static inline void invlpga(unsigned long addr, u32 asid)
416 {
417 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
418 }
419
420 static inline void force_new_asid(struct kvm_vcpu *vcpu)
421 {
422 to_svm(vcpu)->asid_generation--;
423 }
424
425 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
426 {
427 force_new_asid(vcpu);
428 }
429
430 static int get_npt_level(void)
431 {
432 #ifdef CONFIG_X86_64
433 return PT64_ROOT_LEVEL;
434 #else
435 return PT32E_ROOT_LEVEL;
436 #endif
437 }
438
439 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
440 {
441 vcpu->arch.efer = efer;
442 if (!npt_enabled && !(efer & EFER_LMA))
443 efer &= ~EFER_LME;
444
445 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
446 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
447 }
448
449 static int is_external_interrupt(u32 info)
450 {
451 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
452 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
453 }
454
455 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
456 {
457 struct vcpu_svm *svm = to_svm(vcpu);
458 u32 ret = 0;
459
460 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
461 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
462 return ret & mask;
463 }
464
465 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
466 {
467 struct vcpu_svm *svm = to_svm(vcpu);
468
469 if (mask == 0)
470 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
471 else
472 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
473
474 }
475
476 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
477 {
478 struct vcpu_svm *svm = to_svm(vcpu);
479
480 if (svm->vmcb->control.next_rip != 0)
481 svm->next_rip = svm->vmcb->control.next_rip;
482
483 if (!svm->next_rip) {
484 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
485 EMULATE_DONE)
486 printk(KERN_DEBUG "%s: NOP\n", __func__);
487 return;
488 }
489 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
490 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
491 __func__, kvm_rip_read(vcpu), svm->next_rip);
492
493 kvm_rip_write(vcpu, svm->next_rip);
494 svm_set_interrupt_shadow(vcpu, 0);
495 }
496
497 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
498 bool has_error_code, u32 error_code,
499 bool reinject)
500 {
501 struct vcpu_svm *svm = to_svm(vcpu);
502
503 /*
504 * If we are within a nested VM we'd better #VMEXIT and let the guest
505 * handle the exception
506 */
507 if (!reinject &&
508 nested_svm_check_exception(svm, nr, has_error_code, error_code))
509 return;
510
511 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
512 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
513
514 /*
515 * For guest debugging where we have to reinject #BP if some
516 * INT3 is guest-owned:
517 * Emulate nRIP by moving RIP forward. Will fail if injection
518 * raises a fault that is not intercepted. Still better than
519 * failing in all cases.
520 */
521 skip_emulated_instruction(&svm->vcpu);
522 rip = kvm_rip_read(&svm->vcpu);
523 svm->int3_rip = rip + svm->vmcb->save.cs.base;
524 svm->int3_injected = rip - old_rip;
525 }
526
527 svm->vmcb->control.event_inj = nr
528 | SVM_EVTINJ_VALID
529 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
530 | SVM_EVTINJ_TYPE_EXEPT;
531 svm->vmcb->control.event_inj_err = error_code;
532 }
533
534 static void svm_init_erratum_383(void)
535 {
536 u32 low, high;
537 int err;
538 u64 val;
539
540 if (!cpu_has_amd_erratum(amd_erratum_383))
541 return;
542
543 /* Use _safe variants to not break nested virtualization */
544 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
545 if (err)
546 return;
547
548 val |= (1ULL << 47);
549
550 low = lower_32_bits(val);
551 high = upper_32_bits(val);
552
553 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
554
555 erratum_383_found = true;
556 }
557
558 static int has_svm(void)
559 {
560 const char *msg;
561
562 if (!cpu_has_svm(&msg)) {
563 printk(KERN_INFO "has_svm: %s\n", msg);
564 return 0;
565 }
566
567 return 1;
568 }
569
570 static void svm_hardware_disable(void *garbage)
571 {
572 cpu_svm_disable();
573 }
574
575 static int svm_hardware_enable(void *garbage)
576 {
577
578 struct svm_cpu_data *sd;
579 uint64_t efer;
580 struct desc_ptr gdt_descr;
581 struct desc_struct *gdt;
582 int me = raw_smp_processor_id();
583
584 rdmsrl(MSR_EFER, efer);
585 if (efer & EFER_SVME)
586 return -EBUSY;
587
588 if (!has_svm()) {
589 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
590 me);
591 return -EINVAL;
592 }
593 sd = per_cpu(svm_data, me);
594
595 if (!sd) {
596 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
597 me);
598 return -EINVAL;
599 }
600
601 sd->asid_generation = 1;
602 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
603 sd->next_asid = sd->max_asid + 1;
604
605 native_store_gdt(&gdt_descr);
606 gdt = (struct desc_struct *)gdt_descr.address;
607 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
608
609 wrmsrl(MSR_EFER, efer | EFER_SVME);
610
611 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
612
613 svm_init_erratum_383();
614
615 return 0;
616 }
617
618 static void svm_cpu_uninit(int cpu)
619 {
620 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
621
622 if (!sd)
623 return;
624
625 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
626 __free_page(sd->save_area);
627 kfree(sd);
628 }
629
630 static int svm_cpu_init(int cpu)
631 {
632 struct svm_cpu_data *sd;
633 int r;
634
635 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
636 if (!sd)
637 return -ENOMEM;
638 sd->cpu = cpu;
639 sd->save_area = alloc_page(GFP_KERNEL);
640 r = -ENOMEM;
641 if (!sd->save_area)
642 goto err_1;
643
644 per_cpu(svm_data, cpu) = sd;
645
646 return 0;
647
648 err_1:
649 kfree(sd);
650 return r;
651
652 }
653
654 static bool valid_msr_intercept(u32 index)
655 {
656 int i;
657
658 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
659 if (direct_access_msrs[i].index == index)
660 return true;
661
662 return false;
663 }
664
665 static void set_msr_interception(u32 *msrpm, unsigned msr,
666 int read, int write)
667 {
668 u8 bit_read, bit_write;
669 unsigned long tmp;
670 u32 offset;
671
672 /*
673 * If this warning triggers extend the direct_access_msrs list at the
674 * beginning of the file
675 */
676 WARN_ON(!valid_msr_intercept(msr));
677
678 offset = svm_msrpm_offset(msr);
679 bit_read = 2 * (msr & 0x0f);
680 bit_write = 2 * (msr & 0x0f) + 1;
681 tmp = msrpm[offset];
682
683 BUG_ON(offset == MSR_INVALID);
684
685 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
686 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
687
688 msrpm[offset] = tmp;
689 }
690
691 static void svm_vcpu_init_msrpm(u32 *msrpm)
692 {
693 int i;
694
695 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
696
697 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
698 if (!direct_access_msrs[i].always)
699 continue;
700
701 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
702 }
703 }
704
705 static void add_msr_offset(u32 offset)
706 {
707 int i;
708
709 for (i = 0; i < MSRPM_OFFSETS; ++i) {
710
711 /* Offset already in list? */
712 if (msrpm_offsets[i] == offset)
713 return;
714
715 /* Slot used by another offset? */
716 if (msrpm_offsets[i] != MSR_INVALID)
717 continue;
718
719 /* Add offset to list */
720 msrpm_offsets[i] = offset;
721
722 return;
723 }
724
725 /*
726 * If this BUG triggers the msrpm_offsets table has an overflow. Just
727 * increase MSRPM_OFFSETS in this case.
728 */
729 BUG();
730 }
731
732 static void init_msrpm_offsets(void)
733 {
734 int i;
735
736 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
737
738 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
739 u32 offset;
740
741 offset = svm_msrpm_offset(direct_access_msrs[i].index);
742 BUG_ON(offset == MSR_INVALID);
743
744 add_msr_offset(offset);
745 }
746 }
747
748 static void svm_enable_lbrv(struct vcpu_svm *svm)
749 {
750 u32 *msrpm = svm->msrpm;
751
752 svm->vmcb->control.lbr_ctl = 1;
753 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
754 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
755 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
756 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
757 }
758
759 static void svm_disable_lbrv(struct vcpu_svm *svm)
760 {
761 u32 *msrpm = svm->msrpm;
762
763 svm->vmcb->control.lbr_ctl = 0;
764 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
765 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
766 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
767 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
768 }
769
770 static __init int svm_hardware_setup(void)
771 {
772 int cpu;
773 struct page *iopm_pages;
774 void *iopm_va;
775 int r;
776
777 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
778
779 if (!iopm_pages)
780 return -ENOMEM;
781
782 iopm_va = page_address(iopm_pages);
783 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
784 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
785
786 init_msrpm_offsets();
787
788 if (boot_cpu_has(X86_FEATURE_NX))
789 kvm_enable_efer_bits(EFER_NX);
790
791 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
792 kvm_enable_efer_bits(EFER_FFXSR);
793
794 if (nested) {
795 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
796 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
797 }
798
799 for_each_possible_cpu(cpu) {
800 r = svm_cpu_init(cpu);
801 if (r)
802 goto err;
803 }
804
805 svm_features = cpuid_edx(SVM_CPUID_FUNC);
806
807 if (!boot_cpu_has(X86_FEATURE_NPT))
808 npt_enabled = false;
809
810 if (npt_enabled && !npt) {
811 printk(KERN_INFO "kvm: Nested Paging disabled\n");
812 npt_enabled = false;
813 }
814
815 if (npt_enabled) {
816 printk(KERN_INFO "kvm: Nested Paging enabled\n");
817 kvm_enable_tdp();
818 } else
819 kvm_disable_tdp();
820
821 return 0;
822
823 err:
824 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
825 iopm_base = 0;
826 return r;
827 }
828
829 static __exit void svm_hardware_unsetup(void)
830 {
831 int cpu;
832
833 for_each_possible_cpu(cpu)
834 svm_cpu_uninit(cpu);
835
836 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
837 iopm_base = 0;
838 }
839
840 static void init_seg(struct vmcb_seg *seg)
841 {
842 seg->selector = 0;
843 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
844 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
845 seg->limit = 0xffff;
846 seg->base = 0;
847 }
848
849 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
850 {
851 seg->selector = 0;
852 seg->attrib = SVM_SELECTOR_P_MASK | type;
853 seg->limit = 0xffff;
854 seg->base = 0;
855 }
856
857 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
858 {
859 struct vcpu_svm *svm = to_svm(vcpu);
860 u64 g_tsc_offset = 0;
861
862 if (is_guest_mode(vcpu)) {
863 g_tsc_offset = svm->vmcb->control.tsc_offset -
864 svm->nested.hsave->control.tsc_offset;
865 svm->nested.hsave->control.tsc_offset = offset;
866 }
867
868 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
869
870 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
871 }
872
873 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
874 {
875 struct vcpu_svm *svm = to_svm(vcpu);
876
877 svm->vmcb->control.tsc_offset += adjustment;
878 if (is_guest_mode(vcpu))
879 svm->nested.hsave->control.tsc_offset += adjustment;
880 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
881 }
882
883 static void init_vmcb(struct vcpu_svm *svm)
884 {
885 struct vmcb_control_area *control = &svm->vmcb->control;
886 struct vmcb_save_area *save = &svm->vmcb->save;
887
888 svm->vcpu.fpu_active = 1;
889 svm->vcpu.arch.hflags = 0;
890
891 set_cr_intercept(svm, INTERCEPT_CR0_READ);
892 set_cr_intercept(svm, INTERCEPT_CR3_READ);
893 set_cr_intercept(svm, INTERCEPT_CR4_READ);
894 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
895 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
896 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
897 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
898
899 set_dr_intercept(svm, INTERCEPT_DR0_READ);
900 set_dr_intercept(svm, INTERCEPT_DR1_READ);
901 set_dr_intercept(svm, INTERCEPT_DR2_READ);
902 set_dr_intercept(svm, INTERCEPT_DR3_READ);
903 set_dr_intercept(svm, INTERCEPT_DR4_READ);
904 set_dr_intercept(svm, INTERCEPT_DR5_READ);
905 set_dr_intercept(svm, INTERCEPT_DR6_READ);
906 set_dr_intercept(svm, INTERCEPT_DR7_READ);
907
908 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
914 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
915 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
916
917 set_exception_intercept(svm, PF_VECTOR);
918 set_exception_intercept(svm, UD_VECTOR);
919 set_exception_intercept(svm, MC_VECTOR);
920
921 set_intercept(svm, INTERCEPT_INTR);
922 set_intercept(svm, INTERCEPT_NMI);
923 set_intercept(svm, INTERCEPT_SMI);
924 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
925 set_intercept(svm, INTERCEPT_CPUID);
926 set_intercept(svm, INTERCEPT_INVD);
927 set_intercept(svm, INTERCEPT_HLT);
928 set_intercept(svm, INTERCEPT_INVLPG);
929 set_intercept(svm, INTERCEPT_INVLPGA);
930 set_intercept(svm, INTERCEPT_IOIO_PROT);
931 set_intercept(svm, INTERCEPT_MSR_PROT);
932 set_intercept(svm, INTERCEPT_TASK_SWITCH);
933 set_intercept(svm, INTERCEPT_SHUTDOWN);
934 set_intercept(svm, INTERCEPT_VMRUN);
935 set_intercept(svm, INTERCEPT_VMMCALL);
936 set_intercept(svm, INTERCEPT_VMLOAD);
937 set_intercept(svm, INTERCEPT_VMSAVE);
938 set_intercept(svm, INTERCEPT_STGI);
939 set_intercept(svm, INTERCEPT_CLGI);
940 set_intercept(svm, INTERCEPT_SKINIT);
941 set_intercept(svm, INTERCEPT_WBINVD);
942 set_intercept(svm, INTERCEPT_MONITOR);
943 set_intercept(svm, INTERCEPT_MWAIT);
944
945 control->iopm_base_pa = iopm_base;
946 control->msrpm_base_pa = __pa(svm->msrpm);
947 control->int_ctl = V_INTR_MASKING_MASK;
948
949 init_seg(&save->es);
950 init_seg(&save->ss);
951 init_seg(&save->ds);
952 init_seg(&save->fs);
953 init_seg(&save->gs);
954
955 save->cs.selector = 0xf000;
956 /* Executable/Readable Code Segment */
957 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
958 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
959 save->cs.limit = 0xffff;
960 /*
961 * cs.base should really be 0xffff0000, but vmx can't handle that, so
962 * be consistent with it.
963 *
964 * Replace when we have real mode working for vmx.
965 */
966 save->cs.base = 0xf0000;
967
968 save->gdtr.limit = 0xffff;
969 save->idtr.limit = 0xffff;
970
971 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
972 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
973
974 svm_set_efer(&svm->vcpu, 0);
975 save->dr6 = 0xffff0ff0;
976 save->dr7 = 0x400;
977 save->rflags = 2;
978 save->rip = 0x0000fff0;
979 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
980
981 /*
982 * This is the guest-visible cr0 value.
983 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
984 */
985 svm->vcpu.arch.cr0 = 0;
986 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
987
988 save->cr4 = X86_CR4_PAE;
989 /* rdx = ?? */
990
991 if (npt_enabled) {
992 /* Setup VMCB for Nested Paging */
993 control->nested_ctl = 1;
994 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
995 clr_intercept(svm, INTERCEPT_INVLPG);
996 clr_exception_intercept(svm, PF_VECTOR);
997 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
998 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
999 save->g_pat = 0x0007040600070406ULL;
1000 save->cr3 = 0;
1001 save->cr4 = 0;
1002 }
1003 force_new_asid(&svm->vcpu);
1004
1005 svm->nested.vmcb = 0;
1006 svm->vcpu.arch.hflags = 0;
1007
1008 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1009 control->pause_filter_count = 3000;
1010 set_intercept(svm, INTERCEPT_PAUSE);
1011 }
1012
1013 mark_all_dirty(svm->vmcb);
1014
1015 enable_gif(svm);
1016 }
1017
1018 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1019 {
1020 struct vcpu_svm *svm = to_svm(vcpu);
1021
1022 init_vmcb(svm);
1023
1024 if (!kvm_vcpu_is_bsp(vcpu)) {
1025 kvm_rip_write(vcpu, 0);
1026 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1027 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1028 }
1029 vcpu->arch.regs_avail = ~0;
1030 vcpu->arch.regs_dirty = ~0;
1031
1032 return 0;
1033 }
1034
1035 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1036 {
1037 struct vcpu_svm *svm;
1038 struct page *page;
1039 struct page *msrpm_pages;
1040 struct page *hsave_page;
1041 struct page *nested_msrpm_pages;
1042 int err;
1043
1044 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1045 if (!svm) {
1046 err = -ENOMEM;
1047 goto out;
1048 }
1049
1050 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1051 if (err)
1052 goto free_svm;
1053
1054 err = -ENOMEM;
1055 page = alloc_page(GFP_KERNEL);
1056 if (!page)
1057 goto uninit;
1058
1059 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1060 if (!msrpm_pages)
1061 goto free_page1;
1062
1063 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1064 if (!nested_msrpm_pages)
1065 goto free_page2;
1066
1067 hsave_page = alloc_page(GFP_KERNEL);
1068 if (!hsave_page)
1069 goto free_page3;
1070
1071 svm->nested.hsave = page_address(hsave_page);
1072
1073 svm->msrpm = page_address(msrpm_pages);
1074 svm_vcpu_init_msrpm(svm->msrpm);
1075
1076 svm->nested.msrpm = page_address(nested_msrpm_pages);
1077 svm_vcpu_init_msrpm(svm->nested.msrpm);
1078
1079 svm->vmcb = page_address(page);
1080 clear_page(svm->vmcb);
1081 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1082 svm->asid_generation = 0;
1083 init_vmcb(svm);
1084 kvm_write_tsc(&svm->vcpu, 0);
1085
1086 err = fx_init(&svm->vcpu);
1087 if (err)
1088 goto free_page4;
1089
1090 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1091 if (kvm_vcpu_is_bsp(&svm->vcpu))
1092 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1093
1094 return &svm->vcpu;
1095
1096 free_page4:
1097 __free_page(hsave_page);
1098 free_page3:
1099 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1100 free_page2:
1101 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1102 free_page1:
1103 __free_page(page);
1104 uninit:
1105 kvm_vcpu_uninit(&svm->vcpu);
1106 free_svm:
1107 kmem_cache_free(kvm_vcpu_cache, svm);
1108 out:
1109 return ERR_PTR(err);
1110 }
1111
1112 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1113 {
1114 struct vcpu_svm *svm = to_svm(vcpu);
1115
1116 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1117 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1118 __free_page(virt_to_page(svm->nested.hsave));
1119 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1120 kvm_vcpu_uninit(vcpu);
1121 kmem_cache_free(kvm_vcpu_cache, svm);
1122 }
1123
1124 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1125 {
1126 struct vcpu_svm *svm = to_svm(vcpu);
1127 int i;
1128
1129 if (unlikely(cpu != vcpu->cpu)) {
1130 svm->asid_generation = 0;
1131 mark_all_dirty(svm->vmcb);
1132 }
1133
1134 #ifdef CONFIG_X86_64
1135 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1136 #endif
1137 savesegment(fs, svm->host.fs);
1138 savesegment(gs, svm->host.gs);
1139 svm->host.ldt = kvm_read_ldt();
1140
1141 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1142 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1143 }
1144
1145 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1146 {
1147 struct vcpu_svm *svm = to_svm(vcpu);
1148 int i;
1149
1150 ++vcpu->stat.host_state_reload;
1151 kvm_load_ldt(svm->host.ldt);
1152 #ifdef CONFIG_X86_64
1153 loadsegment(fs, svm->host.fs);
1154 load_gs_index(svm->host.gs);
1155 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1156 #else
1157 loadsegment(gs, svm->host.gs);
1158 #endif
1159 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1160 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1161 }
1162
1163 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1164 {
1165 return to_svm(vcpu)->vmcb->save.rflags;
1166 }
1167
1168 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1169 {
1170 to_svm(vcpu)->vmcb->save.rflags = rflags;
1171 }
1172
1173 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1174 {
1175 switch (reg) {
1176 case VCPU_EXREG_PDPTR:
1177 BUG_ON(!npt_enabled);
1178 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1179 break;
1180 default:
1181 BUG();
1182 }
1183 }
1184
1185 static void svm_set_vintr(struct vcpu_svm *svm)
1186 {
1187 set_intercept(svm, INTERCEPT_VINTR);
1188 }
1189
1190 static void svm_clear_vintr(struct vcpu_svm *svm)
1191 {
1192 clr_intercept(svm, INTERCEPT_VINTR);
1193 }
1194
1195 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1196 {
1197 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1198
1199 switch (seg) {
1200 case VCPU_SREG_CS: return &save->cs;
1201 case VCPU_SREG_DS: return &save->ds;
1202 case VCPU_SREG_ES: return &save->es;
1203 case VCPU_SREG_FS: return &save->fs;
1204 case VCPU_SREG_GS: return &save->gs;
1205 case VCPU_SREG_SS: return &save->ss;
1206 case VCPU_SREG_TR: return &save->tr;
1207 case VCPU_SREG_LDTR: return &save->ldtr;
1208 }
1209 BUG();
1210 return NULL;
1211 }
1212
1213 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1214 {
1215 struct vmcb_seg *s = svm_seg(vcpu, seg);
1216
1217 return s->base;
1218 }
1219
1220 static void svm_get_segment(struct kvm_vcpu *vcpu,
1221 struct kvm_segment *var, int seg)
1222 {
1223 struct vmcb_seg *s = svm_seg(vcpu, seg);
1224
1225 var->base = s->base;
1226 var->limit = s->limit;
1227 var->selector = s->selector;
1228 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1229 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1230 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1231 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1232 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1233 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1234 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1235 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1236
1237 /*
1238 * AMD's VMCB does not have an explicit unusable field, so emulate it
1239 * for cross vendor migration purposes by "not present"
1240 */
1241 var->unusable = !var->present || (var->type == 0);
1242
1243 switch (seg) {
1244 case VCPU_SREG_CS:
1245 /*
1246 * SVM always stores 0 for the 'G' bit in the CS selector in
1247 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1248 * Intel's VMENTRY has a check on the 'G' bit.
1249 */
1250 var->g = s->limit > 0xfffff;
1251 break;
1252 case VCPU_SREG_TR:
1253 /*
1254 * Work around a bug where the busy flag in the tr selector
1255 * isn't exposed
1256 */
1257 var->type |= 0x2;
1258 break;
1259 case VCPU_SREG_DS:
1260 case VCPU_SREG_ES:
1261 case VCPU_SREG_FS:
1262 case VCPU_SREG_GS:
1263 /*
1264 * The accessed bit must always be set in the segment
1265 * descriptor cache, although it can be cleared in the
1266 * descriptor, the cached bit always remains at 1. Since
1267 * Intel has a check on this, set it here to support
1268 * cross-vendor migration.
1269 */
1270 if (!var->unusable)
1271 var->type |= 0x1;
1272 break;
1273 case VCPU_SREG_SS:
1274 /*
1275 * On AMD CPUs sometimes the DB bit in the segment
1276 * descriptor is left as 1, although the whole segment has
1277 * been made unusable. Clear it here to pass an Intel VMX
1278 * entry check when cross vendor migrating.
1279 */
1280 if (var->unusable)
1281 var->db = 0;
1282 break;
1283 }
1284 }
1285
1286 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1287 {
1288 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1289
1290 return save->cpl;
1291 }
1292
1293 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1294 {
1295 struct vcpu_svm *svm = to_svm(vcpu);
1296
1297 dt->size = svm->vmcb->save.idtr.limit;
1298 dt->address = svm->vmcb->save.idtr.base;
1299 }
1300
1301 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1302 {
1303 struct vcpu_svm *svm = to_svm(vcpu);
1304
1305 svm->vmcb->save.idtr.limit = dt->size;
1306 svm->vmcb->save.idtr.base = dt->address ;
1307 }
1308
1309 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1310 {
1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
1313 dt->size = svm->vmcb->save.gdtr.limit;
1314 dt->address = svm->vmcb->save.gdtr.base;
1315 }
1316
1317 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1318 {
1319 struct vcpu_svm *svm = to_svm(vcpu);
1320
1321 svm->vmcb->save.gdtr.limit = dt->size;
1322 svm->vmcb->save.gdtr.base = dt->address ;
1323 }
1324
1325 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1326 {
1327 }
1328
1329 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1330 {
1331 }
1332
1333 static void update_cr0_intercept(struct vcpu_svm *svm)
1334 {
1335 ulong gcr0 = svm->vcpu.arch.cr0;
1336 u64 *hcr0 = &svm->vmcb->save.cr0;
1337
1338 if (!svm->vcpu.fpu_active)
1339 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1340 else
1341 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1342 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1343
1344 mark_dirty(svm->vmcb, VMCB_CR);
1345
1346 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1347 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1348 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1349 } else {
1350 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1351 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1352 }
1353 }
1354
1355 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1356 {
1357 struct vcpu_svm *svm = to_svm(vcpu);
1358
1359 if (is_guest_mode(vcpu)) {
1360 /*
1361 * We are here because we run in nested mode, the host kvm
1362 * intercepts cr0 writes but the l1 hypervisor does not.
1363 * But the L1 hypervisor may intercept selective cr0 writes.
1364 * This needs to be checked here.
1365 */
1366 unsigned long old, new;
1367
1368 /* Remove bits that would trigger a real cr0 write intercept */
1369 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1370 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1371
1372 if (old == new) {
1373 /* cr0 write with ts and mp unchanged */
1374 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1375 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1376 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1377 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1378 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1379 return;
1380 }
1381 }
1382 }
1383
1384 #ifdef CONFIG_X86_64
1385 if (vcpu->arch.efer & EFER_LME) {
1386 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1387 vcpu->arch.efer |= EFER_LMA;
1388 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1389 }
1390
1391 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1392 vcpu->arch.efer &= ~EFER_LMA;
1393 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1394 }
1395 }
1396 #endif
1397 vcpu->arch.cr0 = cr0;
1398
1399 if (!npt_enabled)
1400 cr0 |= X86_CR0_PG | X86_CR0_WP;
1401
1402 if (!vcpu->fpu_active)
1403 cr0 |= X86_CR0_TS;
1404 /*
1405 * re-enable caching here because the QEMU bios
1406 * does not do it - this results in some delay at
1407 * reboot
1408 */
1409 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1410 svm->vmcb->save.cr0 = cr0;
1411 mark_dirty(svm->vmcb, VMCB_CR);
1412 update_cr0_intercept(svm);
1413 }
1414
1415 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1416 {
1417 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1418 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1419
1420 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1421 force_new_asid(vcpu);
1422
1423 vcpu->arch.cr4 = cr4;
1424 if (!npt_enabled)
1425 cr4 |= X86_CR4_PAE;
1426 cr4 |= host_cr4_mce;
1427 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1428 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1429 }
1430
1431 static void svm_set_segment(struct kvm_vcpu *vcpu,
1432 struct kvm_segment *var, int seg)
1433 {
1434 struct vcpu_svm *svm = to_svm(vcpu);
1435 struct vmcb_seg *s = svm_seg(vcpu, seg);
1436
1437 s->base = var->base;
1438 s->limit = var->limit;
1439 s->selector = var->selector;
1440 if (var->unusable)
1441 s->attrib = 0;
1442 else {
1443 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1444 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1445 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1446 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1447 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1448 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1449 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1450 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1451 }
1452 if (seg == VCPU_SREG_CS)
1453 svm->vmcb->save.cpl
1454 = (svm->vmcb->save.cs.attrib
1455 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1456
1457 }
1458
1459 static void update_db_intercept(struct kvm_vcpu *vcpu)
1460 {
1461 struct vcpu_svm *svm = to_svm(vcpu);
1462
1463 clr_exception_intercept(svm, DB_VECTOR);
1464 clr_exception_intercept(svm, BP_VECTOR);
1465
1466 if (svm->nmi_singlestep)
1467 set_exception_intercept(svm, DB_VECTOR);
1468
1469 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1470 if (vcpu->guest_debug &
1471 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1472 set_exception_intercept(svm, DB_VECTOR);
1473 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1474 set_exception_intercept(svm, BP_VECTOR);
1475 } else
1476 vcpu->guest_debug = 0;
1477 }
1478
1479 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1480 {
1481 struct vcpu_svm *svm = to_svm(vcpu);
1482
1483 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1484 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1485 else
1486 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1487
1488 mark_dirty(svm->vmcb, VMCB_DR);
1489
1490 update_db_intercept(vcpu);
1491 }
1492
1493 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1494 {
1495 if (sd->next_asid > sd->max_asid) {
1496 ++sd->asid_generation;
1497 sd->next_asid = 1;
1498 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1499 }
1500
1501 svm->asid_generation = sd->asid_generation;
1502 svm->vmcb->control.asid = sd->next_asid++;
1503
1504 mark_dirty(svm->vmcb, VMCB_ASID);
1505 }
1506
1507 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1508 {
1509 struct vcpu_svm *svm = to_svm(vcpu);
1510
1511 svm->vmcb->save.dr7 = value;
1512 mark_dirty(svm->vmcb, VMCB_DR);
1513 }
1514
1515 static int pf_interception(struct vcpu_svm *svm)
1516 {
1517 u64 fault_address = svm->vmcb->control.exit_info_2;
1518 u32 error_code;
1519 int r = 1;
1520
1521 switch (svm->apf_reason) {
1522 default:
1523 error_code = svm->vmcb->control.exit_info_1;
1524
1525 trace_kvm_page_fault(fault_address, error_code);
1526 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1527 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1528 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1529 break;
1530 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1531 svm->apf_reason = 0;
1532 local_irq_disable();
1533 kvm_async_pf_task_wait(fault_address);
1534 local_irq_enable();
1535 break;
1536 case KVM_PV_REASON_PAGE_READY:
1537 svm->apf_reason = 0;
1538 local_irq_disable();
1539 kvm_async_pf_task_wake(fault_address);
1540 local_irq_enable();
1541 break;
1542 }
1543 return r;
1544 }
1545
1546 static int db_interception(struct vcpu_svm *svm)
1547 {
1548 struct kvm_run *kvm_run = svm->vcpu.run;
1549
1550 if (!(svm->vcpu.guest_debug &
1551 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1552 !svm->nmi_singlestep) {
1553 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1554 return 1;
1555 }
1556
1557 if (svm->nmi_singlestep) {
1558 svm->nmi_singlestep = false;
1559 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1560 svm->vmcb->save.rflags &=
1561 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1562 update_db_intercept(&svm->vcpu);
1563 }
1564
1565 if (svm->vcpu.guest_debug &
1566 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1567 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1568 kvm_run->debug.arch.pc =
1569 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1570 kvm_run->debug.arch.exception = DB_VECTOR;
1571 return 0;
1572 }
1573
1574 return 1;
1575 }
1576
1577 static int bp_interception(struct vcpu_svm *svm)
1578 {
1579 struct kvm_run *kvm_run = svm->vcpu.run;
1580
1581 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1582 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1583 kvm_run->debug.arch.exception = BP_VECTOR;
1584 return 0;
1585 }
1586
1587 static int ud_interception(struct vcpu_svm *svm)
1588 {
1589 int er;
1590
1591 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1592 if (er != EMULATE_DONE)
1593 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1594 return 1;
1595 }
1596
1597 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1598 {
1599 struct vcpu_svm *svm = to_svm(vcpu);
1600
1601 clr_exception_intercept(svm, NM_VECTOR);
1602
1603 svm->vcpu.fpu_active = 1;
1604 update_cr0_intercept(svm);
1605 }
1606
1607 static int nm_interception(struct vcpu_svm *svm)
1608 {
1609 svm_fpu_activate(&svm->vcpu);
1610 return 1;
1611 }
1612
1613 static bool is_erratum_383(void)
1614 {
1615 int err, i;
1616 u64 value;
1617
1618 if (!erratum_383_found)
1619 return false;
1620
1621 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1622 if (err)
1623 return false;
1624
1625 /* Bit 62 may or may not be set for this mce */
1626 value &= ~(1ULL << 62);
1627
1628 if (value != 0xb600000000010015ULL)
1629 return false;
1630
1631 /* Clear MCi_STATUS registers */
1632 for (i = 0; i < 6; ++i)
1633 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1634
1635 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1636 if (!err) {
1637 u32 low, high;
1638
1639 value &= ~(1ULL << 2);
1640 low = lower_32_bits(value);
1641 high = upper_32_bits(value);
1642
1643 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1644 }
1645
1646 /* Flush tlb to evict multi-match entries */
1647 __flush_tlb_all();
1648
1649 return true;
1650 }
1651
1652 static void svm_handle_mce(struct vcpu_svm *svm)
1653 {
1654 if (is_erratum_383()) {
1655 /*
1656 * Erratum 383 triggered. Guest state is corrupt so kill the
1657 * guest.
1658 */
1659 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1660
1661 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1662
1663 return;
1664 }
1665
1666 /*
1667 * On an #MC intercept the MCE handler is not called automatically in
1668 * the host. So do it by hand here.
1669 */
1670 asm volatile (
1671 "int $0x12\n");
1672 /* not sure if we ever come back to this point */
1673
1674 return;
1675 }
1676
1677 static int mc_interception(struct vcpu_svm *svm)
1678 {
1679 return 1;
1680 }
1681
1682 static int shutdown_interception(struct vcpu_svm *svm)
1683 {
1684 struct kvm_run *kvm_run = svm->vcpu.run;
1685
1686 /*
1687 * VMCB is undefined after a SHUTDOWN intercept
1688 * so reinitialize it.
1689 */
1690 clear_page(svm->vmcb);
1691 init_vmcb(svm);
1692
1693 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1694 return 0;
1695 }
1696
1697 static int io_interception(struct vcpu_svm *svm)
1698 {
1699 struct kvm_vcpu *vcpu = &svm->vcpu;
1700 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1701 int size, in, string;
1702 unsigned port;
1703
1704 ++svm->vcpu.stat.io_exits;
1705 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1706 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1707 if (string || in)
1708 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1709
1710 port = io_info >> 16;
1711 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1712 svm->next_rip = svm->vmcb->control.exit_info_2;
1713 skip_emulated_instruction(&svm->vcpu);
1714
1715 return kvm_fast_pio_out(vcpu, size, port);
1716 }
1717
1718 static int nmi_interception(struct vcpu_svm *svm)
1719 {
1720 return 1;
1721 }
1722
1723 static int intr_interception(struct vcpu_svm *svm)
1724 {
1725 ++svm->vcpu.stat.irq_exits;
1726 return 1;
1727 }
1728
1729 static int nop_on_interception(struct vcpu_svm *svm)
1730 {
1731 return 1;
1732 }
1733
1734 static int halt_interception(struct vcpu_svm *svm)
1735 {
1736 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1737 skip_emulated_instruction(&svm->vcpu);
1738 return kvm_emulate_halt(&svm->vcpu);
1739 }
1740
1741 static int vmmcall_interception(struct vcpu_svm *svm)
1742 {
1743 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1744 skip_emulated_instruction(&svm->vcpu);
1745 kvm_emulate_hypercall(&svm->vcpu);
1746 return 1;
1747 }
1748
1749 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1750 {
1751 struct vcpu_svm *svm = to_svm(vcpu);
1752
1753 return svm->nested.nested_cr3;
1754 }
1755
1756 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1757 unsigned long root)
1758 {
1759 struct vcpu_svm *svm = to_svm(vcpu);
1760
1761 svm->vmcb->control.nested_cr3 = root;
1762 mark_dirty(svm->vmcb, VMCB_NPT);
1763 force_new_asid(vcpu);
1764 }
1765
1766 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1767 struct x86_exception *fault)
1768 {
1769 struct vcpu_svm *svm = to_svm(vcpu);
1770
1771 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1772 svm->vmcb->control.exit_code_hi = 0;
1773 svm->vmcb->control.exit_info_1 = fault->error_code;
1774 svm->vmcb->control.exit_info_2 = fault->address;
1775
1776 nested_svm_vmexit(svm);
1777 }
1778
1779 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1780 {
1781 int r;
1782
1783 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1784
1785 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1786 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1787 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1788 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1789 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1790
1791 return r;
1792 }
1793
1794 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1795 {
1796 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1797 }
1798
1799 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1800 {
1801 if (!(svm->vcpu.arch.efer & EFER_SVME)
1802 || !is_paging(&svm->vcpu)) {
1803 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1804 return 1;
1805 }
1806
1807 if (svm->vmcb->save.cpl) {
1808 kvm_inject_gp(&svm->vcpu, 0);
1809 return 1;
1810 }
1811
1812 return 0;
1813 }
1814
1815 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1816 bool has_error_code, u32 error_code)
1817 {
1818 int vmexit;
1819
1820 if (!is_guest_mode(&svm->vcpu))
1821 return 0;
1822
1823 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1824 svm->vmcb->control.exit_code_hi = 0;
1825 svm->vmcb->control.exit_info_1 = error_code;
1826 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1827
1828 vmexit = nested_svm_intercept(svm);
1829 if (vmexit == NESTED_EXIT_DONE)
1830 svm->nested.exit_required = true;
1831
1832 return vmexit;
1833 }
1834
1835 /* This function returns true if it is save to enable the irq window */
1836 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1837 {
1838 if (!is_guest_mode(&svm->vcpu))
1839 return true;
1840
1841 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1842 return true;
1843
1844 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1845 return false;
1846
1847 /*
1848 * if vmexit was already requested (by intercepted exception
1849 * for instance) do not overwrite it with "external interrupt"
1850 * vmexit.
1851 */
1852 if (svm->nested.exit_required)
1853 return false;
1854
1855 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1856 svm->vmcb->control.exit_info_1 = 0;
1857 svm->vmcb->control.exit_info_2 = 0;
1858
1859 if (svm->nested.intercept & 1ULL) {
1860 /*
1861 * The #vmexit can't be emulated here directly because this
1862 * code path runs with irqs and preemtion disabled. A
1863 * #vmexit emulation might sleep. Only signal request for
1864 * the #vmexit here.
1865 */
1866 svm->nested.exit_required = true;
1867 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1868 return false;
1869 }
1870
1871 return true;
1872 }
1873
1874 /* This function returns true if it is save to enable the nmi window */
1875 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1876 {
1877 if (!is_guest_mode(&svm->vcpu))
1878 return true;
1879
1880 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1881 return true;
1882
1883 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1884 svm->nested.exit_required = true;
1885
1886 return false;
1887 }
1888
1889 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1890 {
1891 struct page *page;
1892
1893 might_sleep();
1894
1895 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1896 if (is_error_page(page))
1897 goto error;
1898
1899 *_page = page;
1900
1901 return kmap(page);
1902
1903 error:
1904 kvm_release_page_clean(page);
1905 kvm_inject_gp(&svm->vcpu, 0);
1906
1907 return NULL;
1908 }
1909
1910 static void nested_svm_unmap(struct page *page)
1911 {
1912 kunmap(page);
1913 kvm_release_page_dirty(page);
1914 }
1915
1916 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1917 {
1918 unsigned port;
1919 u8 val, bit;
1920 u64 gpa;
1921
1922 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1923 return NESTED_EXIT_HOST;
1924
1925 port = svm->vmcb->control.exit_info_1 >> 16;
1926 gpa = svm->nested.vmcb_iopm + (port / 8);
1927 bit = port % 8;
1928 val = 0;
1929
1930 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1931 val &= (1 << bit);
1932
1933 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1934 }
1935
1936 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1937 {
1938 u32 offset, msr, value;
1939 int write, mask;
1940
1941 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1942 return NESTED_EXIT_HOST;
1943
1944 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1945 offset = svm_msrpm_offset(msr);
1946 write = svm->vmcb->control.exit_info_1 & 1;
1947 mask = 1 << ((2 * (msr & 0xf)) + write);
1948
1949 if (offset == MSR_INVALID)
1950 return NESTED_EXIT_DONE;
1951
1952 /* Offset is in 32 bit units but need in 8 bit units */
1953 offset *= 4;
1954
1955 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1956 return NESTED_EXIT_DONE;
1957
1958 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1959 }
1960
1961 static int nested_svm_exit_special(struct vcpu_svm *svm)
1962 {
1963 u32 exit_code = svm->vmcb->control.exit_code;
1964
1965 switch (exit_code) {
1966 case SVM_EXIT_INTR:
1967 case SVM_EXIT_NMI:
1968 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1969 return NESTED_EXIT_HOST;
1970 case SVM_EXIT_NPF:
1971 /* For now we are always handling NPFs when using them */
1972 if (npt_enabled)
1973 return NESTED_EXIT_HOST;
1974 break;
1975 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1976 /* When we're shadowing, trap PFs, but not async PF */
1977 if (!npt_enabled && svm->apf_reason == 0)
1978 return NESTED_EXIT_HOST;
1979 break;
1980 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1981 nm_interception(svm);
1982 break;
1983 default:
1984 break;
1985 }
1986
1987 return NESTED_EXIT_CONTINUE;
1988 }
1989
1990 /*
1991 * If this function returns true, this #vmexit was already handled
1992 */
1993 static int nested_svm_intercept(struct vcpu_svm *svm)
1994 {
1995 u32 exit_code = svm->vmcb->control.exit_code;
1996 int vmexit = NESTED_EXIT_HOST;
1997
1998 switch (exit_code) {
1999 case SVM_EXIT_MSR:
2000 vmexit = nested_svm_exit_handled_msr(svm);
2001 break;
2002 case SVM_EXIT_IOIO:
2003 vmexit = nested_svm_intercept_ioio(svm);
2004 break;
2005 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2006 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2007 if (svm->nested.intercept_cr & bit)
2008 vmexit = NESTED_EXIT_DONE;
2009 break;
2010 }
2011 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2012 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2013 if (svm->nested.intercept_dr & bit)
2014 vmexit = NESTED_EXIT_DONE;
2015 break;
2016 }
2017 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2018 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2019 if (svm->nested.intercept_exceptions & excp_bits)
2020 vmexit = NESTED_EXIT_DONE;
2021 /* async page fault always cause vmexit */
2022 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2023 svm->apf_reason != 0)
2024 vmexit = NESTED_EXIT_DONE;
2025 break;
2026 }
2027 case SVM_EXIT_ERR: {
2028 vmexit = NESTED_EXIT_DONE;
2029 break;
2030 }
2031 default: {
2032 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2033 if (svm->nested.intercept & exit_bits)
2034 vmexit = NESTED_EXIT_DONE;
2035 }
2036 }
2037
2038 return vmexit;
2039 }
2040
2041 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2042 {
2043 int vmexit;
2044
2045 vmexit = nested_svm_intercept(svm);
2046
2047 if (vmexit == NESTED_EXIT_DONE)
2048 nested_svm_vmexit(svm);
2049
2050 return vmexit;
2051 }
2052
2053 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2054 {
2055 struct vmcb_control_area *dst = &dst_vmcb->control;
2056 struct vmcb_control_area *from = &from_vmcb->control;
2057
2058 dst->intercept_cr = from->intercept_cr;
2059 dst->intercept_dr = from->intercept_dr;
2060 dst->intercept_exceptions = from->intercept_exceptions;
2061 dst->intercept = from->intercept;
2062 dst->iopm_base_pa = from->iopm_base_pa;
2063 dst->msrpm_base_pa = from->msrpm_base_pa;
2064 dst->tsc_offset = from->tsc_offset;
2065 dst->asid = from->asid;
2066 dst->tlb_ctl = from->tlb_ctl;
2067 dst->int_ctl = from->int_ctl;
2068 dst->int_vector = from->int_vector;
2069 dst->int_state = from->int_state;
2070 dst->exit_code = from->exit_code;
2071 dst->exit_code_hi = from->exit_code_hi;
2072 dst->exit_info_1 = from->exit_info_1;
2073 dst->exit_info_2 = from->exit_info_2;
2074 dst->exit_int_info = from->exit_int_info;
2075 dst->exit_int_info_err = from->exit_int_info_err;
2076 dst->nested_ctl = from->nested_ctl;
2077 dst->event_inj = from->event_inj;
2078 dst->event_inj_err = from->event_inj_err;
2079 dst->nested_cr3 = from->nested_cr3;
2080 dst->lbr_ctl = from->lbr_ctl;
2081 }
2082
2083 static int nested_svm_vmexit(struct vcpu_svm *svm)
2084 {
2085 struct vmcb *nested_vmcb;
2086 struct vmcb *hsave = svm->nested.hsave;
2087 struct vmcb *vmcb = svm->vmcb;
2088 struct page *page;
2089
2090 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2091 vmcb->control.exit_info_1,
2092 vmcb->control.exit_info_2,
2093 vmcb->control.exit_int_info,
2094 vmcb->control.exit_int_info_err);
2095
2096 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2097 if (!nested_vmcb)
2098 return 1;
2099
2100 /* Exit Guest-Mode */
2101 leave_guest_mode(&svm->vcpu);
2102 svm->nested.vmcb = 0;
2103
2104 /* Give the current vmcb to the guest */
2105 disable_gif(svm);
2106
2107 nested_vmcb->save.es = vmcb->save.es;
2108 nested_vmcb->save.cs = vmcb->save.cs;
2109 nested_vmcb->save.ss = vmcb->save.ss;
2110 nested_vmcb->save.ds = vmcb->save.ds;
2111 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2112 nested_vmcb->save.idtr = vmcb->save.idtr;
2113 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2114 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2115 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2116 nested_vmcb->save.cr2 = vmcb->save.cr2;
2117 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2118 nested_vmcb->save.rflags = vmcb->save.rflags;
2119 nested_vmcb->save.rip = vmcb->save.rip;
2120 nested_vmcb->save.rsp = vmcb->save.rsp;
2121 nested_vmcb->save.rax = vmcb->save.rax;
2122 nested_vmcb->save.dr7 = vmcb->save.dr7;
2123 nested_vmcb->save.dr6 = vmcb->save.dr6;
2124 nested_vmcb->save.cpl = vmcb->save.cpl;
2125
2126 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2127 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2128 nested_vmcb->control.int_state = vmcb->control.int_state;
2129 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2130 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2131 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2132 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2133 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2134 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2135 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2136
2137 /*
2138 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2139 * to make sure that we do not lose injected events. So check event_inj
2140 * here and copy it to exit_int_info if it is valid.
2141 * Exit_int_info and event_inj can't be both valid because the case
2142 * below only happens on a VMRUN instruction intercept which has
2143 * no valid exit_int_info set.
2144 */
2145 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2146 struct vmcb_control_area *nc = &nested_vmcb->control;
2147
2148 nc->exit_int_info = vmcb->control.event_inj;
2149 nc->exit_int_info_err = vmcb->control.event_inj_err;
2150 }
2151
2152 nested_vmcb->control.tlb_ctl = 0;
2153 nested_vmcb->control.event_inj = 0;
2154 nested_vmcb->control.event_inj_err = 0;
2155
2156 /* We always set V_INTR_MASKING and remember the old value in hflags */
2157 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2158 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2159
2160 /* Restore the original control entries */
2161 copy_vmcb_control_area(vmcb, hsave);
2162
2163 kvm_clear_exception_queue(&svm->vcpu);
2164 kvm_clear_interrupt_queue(&svm->vcpu);
2165
2166 svm->nested.nested_cr3 = 0;
2167
2168 /* Restore selected save entries */
2169 svm->vmcb->save.es = hsave->save.es;
2170 svm->vmcb->save.cs = hsave->save.cs;
2171 svm->vmcb->save.ss = hsave->save.ss;
2172 svm->vmcb->save.ds = hsave->save.ds;
2173 svm->vmcb->save.gdtr = hsave->save.gdtr;
2174 svm->vmcb->save.idtr = hsave->save.idtr;
2175 svm->vmcb->save.rflags = hsave->save.rflags;
2176 svm_set_efer(&svm->vcpu, hsave->save.efer);
2177 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2178 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2179 if (npt_enabled) {
2180 svm->vmcb->save.cr3 = hsave->save.cr3;
2181 svm->vcpu.arch.cr3 = hsave->save.cr3;
2182 } else {
2183 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2184 }
2185 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2186 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2187 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2188 svm->vmcb->save.dr7 = 0;
2189 svm->vmcb->save.cpl = 0;
2190 svm->vmcb->control.exit_int_info = 0;
2191
2192 mark_all_dirty(svm->vmcb);
2193
2194 nested_svm_unmap(page);
2195
2196 nested_svm_uninit_mmu_context(&svm->vcpu);
2197 kvm_mmu_reset_context(&svm->vcpu);
2198 kvm_mmu_load(&svm->vcpu);
2199
2200 return 0;
2201 }
2202
2203 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2204 {
2205 /*
2206 * This function merges the msr permission bitmaps of kvm and the
2207 * nested vmcb. It is omptimized in that it only merges the parts where
2208 * the kvm msr permission bitmap may contain zero bits
2209 */
2210 int i;
2211
2212 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2213 return true;
2214
2215 for (i = 0; i < MSRPM_OFFSETS; i++) {
2216 u32 value, p;
2217 u64 offset;
2218
2219 if (msrpm_offsets[i] == 0xffffffff)
2220 break;
2221
2222 p = msrpm_offsets[i];
2223 offset = svm->nested.vmcb_msrpm + (p * 4);
2224
2225 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2226 return false;
2227
2228 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2229 }
2230
2231 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2232
2233 return true;
2234 }
2235
2236 static bool nested_vmcb_checks(struct vmcb *vmcb)
2237 {
2238 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2239 return false;
2240
2241 if (vmcb->control.asid == 0)
2242 return false;
2243
2244 if (vmcb->control.nested_ctl && !npt_enabled)
2245 return false;
2246
2247 return true;
2248 }
2249
2250 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2251 {
2252 struct vmcb *nested_vmcb;
2253 struct vmcb *hsave = svm->nested.hsave;
2254 struct vmcb *vmcb = svm->vmcb;
2255 struct page *page;
2256 u64 vmcb_gpa;
2257
2258 vmcb_gpa = svm->vmcb->save.rax;
2259
2260 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2261 if (!nested_vmcb)
2262 return false;
2263
2264 if (!nested_vmcb_checks(nested_vmcb)) {
2265 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2266 nested_vmcb->control.exit_code_hi = 0;
2267 nested_vmcb->control.exit_info_1 = 0;
2268 nested_vmcb->control.exit_info_2 = 0;
2269
2270 nested_svm_unmap(page);
2271
2272 return false;
2273 }
2274
2275 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2276 nested_vmcb->save.rip,
2277 nested_vmcb->control.int_ctl,
2278 nested_vmcb->control.event_inj,
2279 nested_vmcb->control.nested_ctl);
2280
2281 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2282 nested_vmcb->control.intercept_cr >> 16,
2283 nested_vmcb->control.intercept_exceptions,
2284 nested_vmcb->control.intercept);
2285
2286 /* Clear internal status */
2287 kvm_clear_exception_queue(&svm->vcpu);
2288 kvm_clear_interrupt_queue(&svm->vcpu);
2289
2290 /*
2291 * Save the old vmcb, so we don't need to pick what we save, but can
2292 * restore everything when a VMEXIT occurs
2293 */
2294 hsave->save.es = vmcb->save.es;
2295 hsave->save.cs = vmcb->save.cs;
2296 hsave->save.ss = vmcb->save.ss;
2297 hsave->save.ds = vmcb->save.ds;
2298 hsave->save.gdtr = vmcb->save.gdtr;
2299 hsave->save.idtr = vmcb->save.idtr;
2300 hsave->save.efer = svm->vcpu.arch.efer;
2301 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2302 hsave->save.cr4 = svm->vcpu.arch.cr4;
2303 hsave->save.rflags = vmcb->save.rflags;
2304 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2305 hsave->save.rsp = vmcb->save.rsp;
2306 hsave->save.rax = vmcb->save.rax;
2307 if (npt_enabled)
2308 hsave->save.cr3 = vmcb->save.cr3;
2309 else
2310 hsave->save.cr3 = svm->vcpu.arch.cr3;
2311
2312 copy_vmcb_control_area(hsave, vmcb);
2313
2314 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2315 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2316 else
2317 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2318
2319 if (nested_vmcb->control.nested_ctl) {
2320 kvm_mmu_unload(&svm->vcpu);
2321 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2322 nested_svm_init_mmu_context(&svm->vcpu);
2323 }
2324
2325 /* Load the nested guest state */
2326 svm->vmcb->save.es = nested_vmcb->save.es;
2327 svm->vmcb->save.cs = nested_vmcb->save.cs;
2328 svm->vmcb->save.ss = nested_vmcb->save.ss;
2329 svm->vmcb->save.ds = nested_vmcb->save.ds;
2330 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2331 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2332 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2333 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2334 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2335 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2336 if (npt_enabled) {
2337 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2338 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2339 } else
2340 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2341
2342 /* Guest paging mode is active - reset mmu */
2343 kvm_mmu_reset_context(&svm->vcpu);
2344
2345 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2346 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2347 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2348 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2349
2350 /* In case we don't even reach vcpu_run, the fields are not updated */
2351 svm->vmcb->save.rax = nested_vmcb->save.rax;
2352 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2353 svm->vmcb->save.rip = nested_vmcb->save.rip;
2354 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2355 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2356 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2357
2358 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2359 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2360
2361 /* cache intercepts */
2362 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2363 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2364 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2365 svm->nested.intercept = nested_vmcb->control.intercept;
2366
2367 force_new_asid(&svm->vcpu);
2368 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2369 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2370 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2371 else
2372 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2373
2374 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2375 /* We only want the cr8 intercept bits of the guest */
2376 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2377 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2378 }
2379
2380 /* We don't want to see VMMCALLs from a nested guest */
2381 clr_intercept(svm, INTERCEPT_VMMCALL);
2382
2383 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2384 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2385 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2386 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2387 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2388 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2389
2390 nested_svm_unmap(page);
2391
2392 /* Enter Guest-Mode */
2393 enter_guest_mode(&svm->vcpu);
2394
2395 /*
2396 * Merge guest and host intercepts - must be called with vcpu in
2397 * guest-mode to take affect here
2398 */
2399 recalc_intercepts(svm);
2400
2401 svm->nested.vmcb = vmcb_gpa;
2402
2403 enable_gif(svm);
2404
2405 mark_all_dirty(svm->vmcb);
2406
2407 return true;
2408 }
2409
2410 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2411 {
2412 to_vmcb->save.fs = from_vmcb->save.fs;
2413 to_vmcb->save.gs = from_vmcb->save.gs;
2414 to_vmcb->save.tr = from_vmcb->save.tr;
2415 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2416 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2417 to_vmcb->save.star = from_vmcb->save.star;
2418 to_vmcb->save.lstar = from_vmcb->save.lstar;
2419 to_vmcb->save.cstar = from_vmcb->save.cstar;
2420 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2421 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2422 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2423 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2424 }
2425
2426 static int vmload_interception(struct vcpu_svm *svm)
2427 {
2428 struct vmcb *nested_vmcb;
2429 struct page *page;
2430
2431 if (nested_svm_check_permissions(svm))
2432 return 1;
2433
2434 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2435 skip_emulated_instruction(&svm->vcpu);
2436
2437 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2438 if (!nested_vmcb)
2439 return 1;
2440
2441 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2442 nested_svm_unmap(page);
2443
2444 return 1;
2445 }
2446
2447 static int vmsave_interception(struct vcpu_svm *svm)
2448 {
2449 struct vmcb *nested_vmcb;
2450 struct page *page;
2451
2452 if (nested_svm_check_permissions(svm))
2453 return 1;
2454
2455 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2456 skip_emulated_instruction(&svm->vcpu);
2457
2458 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2459 if (!nested_vmcb)
2460 return 1;
2461
2462 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2463 nested_svm_unmap(page);
2464
2465 return 1;
2466 }
2467
2468 static int vmrun_interception(struct vcpu_svm *svm)
2469 {
2470 if (nested_svm_check_permissions(svm))
2471 return 1;
2472
2473 /* Save rip after vmrun instruction */
2474 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2475
2476 if (!nested_svm_vmrun(svm))
2477 return 1;
2478
2479 if (!nested_svm_vmrun_msrpm(svm))
2480 goto failed;
2481
2482 return 1;
2483
2484 failed:
2485
2486 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2487 svm->vmcb->control.exit_code_hi = 0;
2488 svm->vmcb->control.exit_info_1 = 0;
2489 svm->vmcb->control.exit_info_2 = 0;
2490
2491 nested_svm_vmexit(svm);
2492
2493 return 1;
2494 }
2495
2496 static int stgi_interception(struct vcpu_svm *svm)
2497 {
2498 if (nested_svm_check_permissions(svm))
2499 return 1;
2500
2501 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2502 skip_emulated_instruction(&svm->vcpu);
2503 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2504
2505 enable_gif(svm);
2506
2507 return 1;
2508 }
2509
2510 static int clgi_interception(struct vcpu_svm *svm)
2511 {
2512 if (nested_svm_check_permissions(svm))
2513 return 1;
2514
2515 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2516 skip_emulated_instruction(&svm->vcpu);
2517
2518 disable_gif(svm);
2519
2520 /* After a CLGI no interrupts should come */
2521 svm_clear_vintr(svm);
2522 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2523
2524 mark_dirty(svm->vmcb, VMCB_INTR);
2525
2526 return 1;
2527 }
2528
2529 static int invlpga_interception(struct vcpu_svm *svm)
2530 {
2531 struct kvm_vcpu *vcpu = &svm->vcpu;
2532
2533 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2534 vcpu->arch.regs[VCPU_REGS_RAX]);
2535
2536 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2537 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2538
2539 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2540 skip_emulated_instruction(&svm->vcpu);
2541 return 1;
2542 }
2543
2544 static int skinit_interception(struct vcpu_svm *svm)
2545 {
2546 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2547
2548 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2549 return 1;
2550 }
2551
2552 static int invalid_op_interception(struct vcpu_svm *svm)
2553 {
2554 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2555 return 1;
2556 }
2557
2558 static int task_switch_interception(struct vcpu_svm *svm)
2559 {
2560 u16 tss_selector;
2561 int reason;
2562 int int_type = svm->vmcb->control.exit_int_info &
2563 SVM_EXITINTINFO_TYPE_MASK;
2564 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2565 uint32_t type =
2566 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2567 uint32_t idt_v =
2568 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2569 bool has_error_code = false;
2570 u32 error_code = 0;
2571
2572 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2573
2574 if (svm->vmcb->control.exit_info_2 &
2575 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2576 reason = TASK_SWITCH_IRET;
2577 else if (svm->vmcb->control.exit_info_2 &
2578 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2579 reason = TASK_SWITCH_JMP;
2580 else if (idt_v)
2581 reason = TASK_SWITCH_GATE;
2582 else
2583 reason = TASK_SWITCH_CALL;
2584
2585 if (reason == TASK_SWITCH_GATE) {
2586 switch (type) {
2587 case SVM_EXITINTINFO_TYPE_NMI:
2588 svm->vcpu.arch.nmi_injected = false;
2589 break;
2590 case SVM_EXITINTINFO_TYPE_EXEPT:
2591 if (svm->vmcb->control.exit_info_2 &
2592 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2593 has_error_code = true;
2594 error_code =
2595 (u32)svm->vmcb->control.exit_info_2;
2596 }
2597 kvm_clear_exception_queue(&svm->vcpu);
2598 break;
2599 case SVM_EXITINTINFO_TYPE_INTR:
2600 kvm_clear_interrupt_queue(&svm->vcpu);
2601 break;
2602 default:
2603 break;
2604 }
2605 }
2606
2607 if (reason != TASK_SWITCH_GATE ||
2608 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2609 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2610 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2611 skip_emulated_instruction(&svm->vcpu);
2612
2613 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2614 has_error_code, error_code) == EMULATE_FAIL) {
2615 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2616 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2617 svm->vcpu.run->internal.ndata = 0;
2618 return 0;
2619 }
2620 return 1;
2621 }
2622
2623 static int cpuid_interception(struct vcpu_svm *svm)
2624 {
2625 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2626 kvm_emulate_cpuid(&svm->vcpu);
2627 return 1;
2628 }
2629
2630 static int iret_interception(struct vcpu_svm *svm)
2631 {
2632 ++svm->vcpu.stat.nmi_window_exits;
2633 clr_intercept(svm, INTERCEPT_IRET);
2634 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2635 return 1;
2636 }
2637
2638 static int invlpg_interception(struct vcpu_svm *svm)
2639 {
2640 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2641 }
2642
2643 static int emulate_on_interception(struct vcpu_svm *svm)
2644 {
2645 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2646 }
2647
2648 static int cr0_write_interception(struct vcpu_svm *svm)
2649 {
2650 struct kvm_vcpu *vcpu = &svm->vcpu;
2651 int r;
2652
2653 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2654
2655 if (svm->nested.vmexit_rip) {
2656 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2657 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2658 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2659 svm->nested.vmexit_rip = 0;
2660 }
2661
2662 return r == EMULATE_DONE;
2663 }
2664
2665 static int cr8_write_interception(struct vcpu_svm *svm)
2666 {
2667 struct kvm_run *kvm_run = svm->vcpu.run;
2668
2669 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2670 /* instruction emulation calls kvm_set_cr8() */
2671 emulate_instruction(&svm->vcpu, 0, 0, 0);
2672 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2673 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2674 return 1;
2675 }
2676 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2677 return 1;
2678 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2679 return 0;
2680 }
2681
2682 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2683 {
2684 struct vcpu_svm *svm = to_svm(vcpu);
2685
2686 switch (ecx) {
2687 case MSR_IA32_TSC: {
2688 struct vmcb *vmcb = get_host_vmcb(svm);
2689
2690 *data = vmcb->control.tsc_offset + native_read_tsc();
2691 break;
2692 }
2693 case MSR_STAR:
2694 *data = svm->vmcb->save.star;
2695 break;
2696 #ifdef CONFIG_X86_64
2697 case MSR_LSTAR:
2698 *data = svm->vmcb->save.lstar;
2699 break;
2700 case MSR_CSTAR:
2701 *data = svm->vmcb->save.cstar;
2702 break;
2703 case MSR_KERNEL_GS_BASE:
2704 *data = svm->vmcb->save.kernel_gs_base;
2705 break;
2706 case MSR_SYSCALL_MASK:
2707 *data = svm->vmcb->save.sfmask;
2708 break;
2709 #endif
2710 case MSR_IA32_SYSENTER_CS:
2711 *data = svm->vmcb->save.sysenter_cs;
2712 break;
2713 case MSR_IA32_SYSENTER_EIP:
2714 *data = svm->sysenter_eip;
2715 break;
2716 case MSR_IA32_SYSENTER_ESP:
2717 *data = svm->sysenter_esp;
2718 break;
2719 /*
2720 * Nobody will change the following 5 values in the VMCB so we can
2721 * safely return them on rdmsr. They will always be 0 until LBRV is
2722 * implemented.
2723 */
2724 case MSR_IA32_DEBUGCTLMSR:
2725 *data = svm->vmcb->save.dbgctl;
2726 break;
2727 case MSR_IA32_LASTBRANCHFROMIP:
2728 *data = svm->vmcb->save.br_from;
2729 break;
2730 case MSR_IA32_LASTBRANCHTOIP:
2731 *data = svm->vmcb->save.br_to;
2732 break;
2733 case MSR_IA32_LASTINTFROMIP:
2734 *data = svm->vmcb->save.last_excp_from;
2735 break;
2736 case MSR_IA32_LASTINTTOIP:
2737 *data = svm->vmcb->save.last_excp_to;
2738 break;
2739 case MSR_VM_HSAVE_PA:
2740 *data = svm->nested.hsave_msr;
2741 break;
2742 case MSR_VM_CR:
2743 *data = svm->nested.vm_cr_msr;
2744 break;
2745 case MSR_IA32_UCODE_REV:
2746 *data = 0x01000065;
2747 break;
2748 default:
2749 return kvm_get_msr_common(vcpu, ecx, data);
2750 }
2751 return 0;
2752 }
2753
2754 static int rdmsr_interception(struct vcpu_svm *svm)
2755 {
2756 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2757 u64 data;
2758
2759 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2760 trace_kvm_msr_read_ex(ecx);
2761 kvm_inject_gp(&svm->vcpu, 0);
2762 } else {
2763 trace_kvm_msr_read(ecx, data);
2764
2765 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2766 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2767 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2768 skip_emulated_instruction(&svm->vcpu);
2769 }
2770 return 1;
2771 }
2772
2773 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2774 {
2775 struct vcpu_svm *svm = to_svm(vcpu);
2776 int svm_dis, chg_mask;
2777
2778 if (data & ~SVM_VM_CR_VALID_MASK)
2779 return 1;
2780
2781 chg_mask = SVM_VM_CR_VALID_MASK;
2782
2783 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2784 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2785
2786 svm->nested.vm_cr_msr &= ~chg_mask;
2787 svm->nested.vm_cr_msr |= (data & chg_mask);
2788
2789 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2790
2791 /* check for svm_disable while efer.svme is set */
2792 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2793 return 1;
2794
2795 return 0;
2796 }
2797
2798 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2799 {
2800 struct vcpu_svm *svm = to_svm(vcpu);
2801
2802 switch (ecx) {
2803 case MSR_IA32_TSC:
2804 kvm_write_tsc(vcpu, data);
2805 break;
2806 case MSR_STAR:
2807 svm->vmcb->save.star = data;
2808 break;
2809 #ifdef CONFIG_X86_64
2810 case MSR_LSTAR:
2811 svm->vmcb->save.lstar = data;
2812 break;
2813 case MSR_CSTAR:
2814 svm->vmcb->save.cstar = data;
2815 break;
2816 case MSR_KERNEL_GS_BASE:
2817 svm->vmcb->save.kernel_gs_base = data;
2818 break;
2819 case MSR_SYSCALL_MASK:
2820 svm->vmcb->save.sfmask = data;
2821 break;
2822 #endif
2823 case MSR_IA32_SYSENTER_CS:
2824 svm->vmcb->save.sysenter_cs = data;
2825 break;
2826 case MSR_IA32_SYSENTER_EIP:
2827 svm->sysenter_eip = data;
2828 svm->vmcb->save.sysenter_eip = data;
2829 break;
2830 case MSR_IA32_SYSENTER_ESP:
2831 svm->sysenter_esp = data;
2832 svm->vmcb->save.sysenter_esp = data;
2833 break;
2834 case MSR_IA32_DEBUGCTLMSR:
2835 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2836 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2837 __func__, data);
2838 break;
2839 }
2840 if (data & DEBUGCTL_RESERVED_BITS)
2841 return 1;
2842
2843 svm->vmcb->save.dbgctl = data;
2844 if (data & (1ULL<<0))
2845 svm_enable_lbrv(svm);
2846 else
2847 svm_disable_lbrv(svm);
2848 break;
2849 case MSR_VM_HSAVE_PA:
2850 svm->nested.hsave_msr = data;
2851 break;
2852 case MSR_VM_CR:
2853 return svm_set_vm_cr(vcpu, data);
2854 case MSR_VM_IGNNE:
2855 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2856 break;
2857 default:
2858 return kvm_set_msr_common(vcpu, ecx, data);
2859 }
2860 return 0;
2861 }
2862
2863 static int wrmsr_interception(struct vcpu_svm *svm)
2864 {
2865 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2866 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2867 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2868
2869
2870 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2871 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2872 trace_kvm_msr_write_ex(ecx, data);
2873 kvm_inject_gp(&svm->vcpu, 0);
2874 } else {
2875 trace_kvm_msr_write(ecx, data);
2876 skip_emulated_instruction(&svm->vcpu);
2877 }
2878 return 1;
2879 }
2880
2881 static int msr_interception(struct vcpu_svm *svm)
2882 {
2883 if (svm->vmcb->control.exit_info_1)
2884 return wrmsr_interception(svm);
2885 else
2886 return rdmsr_interception(svm);
2887 }
2888
2889 static int interrupt_window_interception(struct vcpu_svm *svm)
2890 {
2891 struct kvm_run *kvm_run = svm->vcpu.run;
2892
2893 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2894 svm_clear_vintr(svm);
2895 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2896 mark_dirty(svm->vmcb, VMCB_INTR);
2897 /*
2898 * If the user space waits to inject interrupts, exit as soon as
2899 * possible
2900 */
2901 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2902 kvm_run->request_interrupt_window &&
2903 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2904 ++svm->vcpu.stat.irq_window_exits;
2905 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2906 return 0;
2907 }
2908
2909 return 1;
2910 }
2911
2912 static int pause_interception(struct vcpu_svm *svm)
2913 {
2914 kvm_vcpu_on_spin(&(svm->vcpu));
2915 return 1;
2916 }
2917
2918 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2919 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2920 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2921 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2922 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2923 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2924 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2925 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2926 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2927 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2928 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2929 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2930 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2931 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2932 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2933 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2934 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2935 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2936 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2937 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2938 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2939 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2940 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2941 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2942 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2943 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2944 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2945 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2946 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2947 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2948 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2949 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2950 [SVM_EXIT_INTR] = intr_interception,
2951 [SVM_EXIT_NMI] = nmi_interception,
2952 [SVM_EXIT_SMI] = nop_on_interception,
2953 [SVM_EXIT_INIT] = nop_on_interception,
2954 [SVM_EXIT_VINTR] = interrupt_window_interception,
2955 [SVM_EXIT_CPUID] = cpuid_interception,
2956 [SVM_EXIT_IRET] = iret_interception,
2957 [SVM_EXIT_INVD] = emulate_on_interception,
2958 [SVM_EXIT_PAUSE] = pause_interception,
2959 [SVM_EXIT_HLT] = halt_interception,
2960 [SVM_EXIT_INVLPG] = invlpg_interception,
2961 [SVM_EXIT_INVLPGA] = invlpga_interception,
2962 [SVM_EXIT_IOIO] = io_interception,
2963 [SVM_EXIT_MSR] = msr_interception,
2964 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2965 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2966 [SVM_EXIT_VMRUN] = vmrun_interception,
2967 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2968 [SVM_EXIT_VMLOAD] = vmload_interception,
2969 [SVM_EXIT_VMSAVE] = vmsave_interception,
2970 [SVM_EXIT_STGI] = stgi_interception,
2971 [SVM_EXIT_CLGI] = clgi_interception,
2972 [SVM_EXIT_SKINIT] = skinit_interception,
2973 [SVM_EXIT_WBINVD] = emulate_on_interception,
2974 [SVM_EXIT_MONITOR] = invalid_op_interception,
2975 [SVM_EXIT_MWAIT] = invalid_op_interception,
2976 [SVM_EXIT_NPF] = pf_interception,
2977 };
2978
2979 void dump_vmcb(struct kvm_vcpu *vcpu)
2980 {
2981 struct vcpu_svm *svm = to_svm(vcpu);
2982 struct vmcb_control_area *control = &svm->vmcb->control;
2983 struct vmcb_save_area *save = &svm->vmcb->save;
2984
2985 pr_err("VMCB Control Area:\n");
2986 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2987 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2988 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2989 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2990 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2991 pr_err("intercepts: %016llx\n", control->intercept);
2992 pr_err("pause filter count: %d\n", control->pause_filter_count);
2993 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2994 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2995 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2996 pr_err("asid: %d\n", control->asid);
2997 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2998 pr_err("int_ctl: %08x\n", control->int_ctl);
2999 pr_err("int_vector: %08x\n", control->int_vector);
3000 pr_err("int_state: %08x\n", control->int_state);
3001 pr_err("exit_code: %08x\n", control->exit_code);
3002 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3003 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3004 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3005 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3006 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3007 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3008 pr_err("event_inj: %08x\n", control->event_inj);
3009 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3010 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3011 pr_err("next_rip: %016llx\n", control->next_rip);
3012 pr_err("VMCB State Save Area:\n");
3013 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3014 save->es.selector, save->es.attrib,
3015 save->es.limit, save->es.base);
3016 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3017 save->cs.selector, save->cs.attrib,
3018 save->cs.limit, save->cs.base);
3019 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3020 save->ss.selector, save->ss.attrib,
3021 save->ss.limit, save->ss.base);
3022 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3023 save->ds.selector, save->ds.attrib,
3024 save->ds.limit, save->ds.base);
3025 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3026 save->fs.selector, save->fs.attrib,
3027 save->fs.limit, save->fs.base);
3028 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3029 save->gs.selector, save->gs.attrib,
3030 save->gs.limit, save->gs.base);
3031 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3032 save->gdtr.selector, save->gdtr.attrib,
3033 save->gdtr.limit, save->gdtr.base);
3034 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3035 save->ldtr.selector, save->ldtr.attrib,
3036 save->ldtr.limit, save->ldtr.base);
3037 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3038 save->idtr.selector, save->idtr.attrib,
3039 save->idtr.limit, save->idtr.base);
3040 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3041 save->tr.selector, save->tr.attrib,
3042 save->tr.limit, save->tr.base);
3043 pr_err("cpl: %d efer: %016llx\n",
3044 save->cpl, save->efer);
3045 pr_err("cr0: %016llx cr2: %016llx\n",
3046 save->cr0, save->cr2);
3047 pr_err("cr3: %016llx cr4: %016llx\n",
3048 save->cr3, save->cr4);
3049 pr_err("dr6: %016llx dr7: %016llx\n",
3050 save->dr6, save->dr7);
3051 pr_err("rip: %016llx rflags: %016llx\n",
3052 save->rip, save->rflags);
3053 pr_err("rsp: %016llx rax: %016llx\n",
3054 save->rsp, save->rax);
3055 pr_err("star: %016llx lstar: %016llx\n",
3056 save->star, save->lstar);
3057 pr_err("cstar: %016llx sfmask: %016llx\n",
3058 save->cstar, save->sfmask);
3059 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3060 save->kernel_gs_base, save->sysenter_cs);
3061 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3062 save->sysenter_esp, save->sysenter_eip);
3063 pr_err("gpat: %016llx dbgctl: %016llx\n",
3064 save->g_pat, save->dbgctl);
3065 pr_err("br_from: %016llx br_to: %016llx\n",
3066 save->br_from, save->br_to);
3067 pr_err("excp_from: %016llx excp_to: %016llx\n",
3068 save->last_excp_from, save->last_excp_to);
3069
3070 }
3071
3072 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3073 {
3074 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3075
3076 *info1 = control->exit_info_1;
3077 *info2 = control->exit_info_2;
3078 }
3079
3080 static int handle_exit(struct kvm_vcpu *vcpu)
3081 {
3082 struct vcpu_svm *svm = to_svm(vcpu);
3083 struct kvm_run *kvm_run = vcpu->run;
3084 u32 exit_code = svm->vmcb->control.exit_code;
3085
3086 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3087
3088 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3089 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3090 if (npt_enabled)
3091 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3092
3093 if (unlikely(svm->nested.exit_required)) {
3094 nested_svm_vmexit(svm);
3095 svm->nested.exit_required = false;
3096
3097 return 1;
3098 }
3099
3100 if (is_guest_mode(vcpu)) {
3101 int vmexit;
3102
3103 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3104 svm->vmcb->control.exit_info_1,
3105 svm->vmcb->control.exit_info_2,
3106 svm->vmcb->control.exit_int_info,
3107 svm->vmcb->control.exit_int_info_err);
3108
3109 vmexit = nested_svm_exit_special(svm);
3110
3111 if (vmexit == NESTED_EXIT_CONTINUE)
3112 vmexit = nested_svm_exit_handled(svm);
3113
3114 if (vmexit == NESTED_EXIT_DONE)
3115 return 1;
3116 }
3117
3118 svm_complete_interrupts(svm);
3119
3120 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3121 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3122 kvm_run->fail_entry.hardware_entry_failure_reason
3123 = svm->vmcb->control.exit_code;
3124 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3125 dump_vmcb(vcpu);
3126 return 0;
3127 }
3128
3129 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3130 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3131 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3132 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3133 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3134 "exit_code 0x%x\n",
3135 __func__, svm->vmcb->control.exit_int_info,
3136 exit_code);
3137
3138 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3139 || !svm_exit_handlers[exit_code]) {
3140 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3141 kvm_run->hw.hardware_exit_reason = exit_code;
3142 return 0;
3143 }
3144
3145 return svm_exit_handlers[exit_code](svm);
3146 }
3147
3148 static void reload_tss(struct kvm_vcpu *vcpu)
3149 {
3150 int cpu = raw_smp_processor_id();
3151
3152 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3153 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3154 load_TR_desc();
3155 }
3156
3157 static void pre_svm_run(struct vcpu_svm *svm)
3158 {
3159 int cpu = raw_smp_processor_id();
3160
3161 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3162
3163 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3164 /* FIXME: handle wraparound of asid_generation */
3165 if (svm->asid_generation != sd->asid_generation)
3166 new_asid(svm, sd);
3167 }
3168
3169 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3170 {
3171 struct vcpu_svm *svm = to_svm(vcpu);
3172
3173 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3174 vcpu->arch.hflags |= HF_NMI_MASK;
3175 set_intercept(svm, INTERCEPT_IRET);
3176 ++vcpu->stat.nmi_injections;
3177 }
3178
3179 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3180 {
3181 struct vmcb_control_area *control;
3182
3183 control = &svm->vmcb->control;
3184 control->int_vector = irq;
3185 control->int_ctl &= ~V_INTR_PRIO_MASK;
3186 control->int_ctl |= V_IRQ_MASK |
3187 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3188 mark_dirty(svm->vmcb, VMCB_INTR);
3189 }
3190
3191 static void svm_set_irq(struct kvm_vcpu *vcpu)
3192 {
3193 struct vcpu_svm *svm = to_svm(vcpu);
3194
3195 BUG_ON(!(gif_set(svm)));
3196
3197 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3198 ++vcpu->stat.irq_injections;
3199
3200 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3201 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3202 }
3203
3204 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3205 {
3206 struct vcpu_svm *svm = to_svm(vcpu);
3207
3208 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3209 return;
3210
3211 if (irr == -1)
3212 return;
3213
3214 if (tpr >= irr)
3215 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3216 }
3217
3218 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3219 {
3220 struct vcpu_svm *svm = to_svm(vcpu);
3221 struct vmcb *vmcb = svm->vmcb;
3222 int ret;
3223 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3224 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3225 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3226
3227 return ret;
3228 }
3229
3230 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3231 {
3232 struct vcpu_svm *svm = to_svm(vcpu);
3233
3234 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3235 }
3236
3237 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3238 {
3239 struct vcpu_svm *svm = to_svm(vcpu);
3240
3241 if (masked) {
3242 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3243 set_intercept(svm, INTERCEPT_IRET);
3244 } else {
3245 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3246 clr_intercept(svm, INTERCEPT_IRET);
3247 }
3248 }
3249
3250 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3251 {
3252 struct vcpu_svm *svm = to_svm(vcpu);
3253 struct vmcb *vmcb = svm->vmcb;
3254 int ret;
3255
3256 if (!gif_set(svm) ||
3257 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3258 return 0;
3259
3260 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3261
3262 if (is_guest_mode(vcpu))
3263 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3264
3265 return ret;
3266 }
3267
3268 static void enable_irq_window(struct kvm_vcpu *vcpu)
3269 {
3270 struct vcpu_svm *svm = to_svm(vcpu);
3271
3272 /*
3273 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3274 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3275 * get that intercept, this function will be called again though and
3276 * we'll get the vintr intercept.
3277 */
3278 if (gif_set(svm) && nested_svm_intr(svm)) {
3279 svm_set_vintr(svm);
3280 svm_inject_irq(svm, 0x0);
3281 }
3282 }
3283
3284 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3285 {
3286 struct vcpu_svm *svm = to_svm(vcpu);
3287
3288 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3289 == HF_NMI_MASK)
3290 return; /* IRET will cause a vm exit */
3291
3292 /*
3293 * Something prevents NMI from been injected. Single step over possible
3294 * problem (IRET or exception injection or interrupt shadow)
3295 */
3296 svm->nmi_singlestep = true;
3297 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3298 update_db_intercept(vcpu);
3299 }
3300
3301 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3302 {
3303 return 0;
3304 }
3305
3306 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3307 {
3308 force_new_asid(vcpu);
3309 }
3310
3311 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3312 {
3313 }
3314
3315 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3316 {
3317 struct vcpu_svm *svm = to_svm(vcpu);
3318
3319 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3320 return;
3321
3322 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3323 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3324 kvm_set_cr8(vcpu, cr8);
3325 }
3326 }
3327
3328 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3329 {
3330 struct vcpu_svm *svm = to_svm(vcpu);
3331 u64 cr8;
3332
3333 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3334 return;
3335
3336 cr8 = kvm_get_cr8(vcpu);
3337 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3338 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3339 }
3340
3341 static void svm_complete_interrupts(struct vcpu_svm *svm)
3342 {
3343 u8 vector;
3344 int type;
3345 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3346 unsigned int3_injected = svm->int3_injected;
3347
3348 svm->int3_injected = 0;
3349
3350 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3351 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3352 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3353 }
3354
3355 svm->vcpu.arch.nmi_injected = false;
3356 kvm_clear_exception_queue(&svm->vcpu);
3357 kvm_clear_interrupt_queue(&svm->vcpu);
3358
3359 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3360 return;
3361
3362 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3363
3364 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3365 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3366
3367 switch (type) {
3368 case SVM_EXITINTINFO_TYPE_NMI:
3369 svm->vcpu.arch.nmi_injected = true;
3370 break;
3371 case SVM_EXITINTINFO_TYPE_EXEPT:
3372 /*
3373 * In case of software exceptions, do not reinject the vector,
3374 * but re-execute the instruction instead. Rewind RIP first
3375 * if we emulated INT3 before.
3376 */
3377 if (kvm_exception_is_soft(vector)) {
3378 if (vector == BP_VECTOR && int3_injected &&
3379 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3380 kvm_rip_write(&svm->vcpu,
3381 kvm_rip_read(&svm->vcpu) -
3382 int3_injected);
3383 break;
3384 }
3385 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3386 u32 err = svm->vmcb->control.exit_int_info_err;
3387 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3388
3389 } else
3390 kvm_requeue_exception(&svm->vcpu, vector);
3391 break;
3392 case SVM_EXITINTINFO_TYPE_INTR:
3393 kvm_queue_interrupt(&svm->vcpu, vector, false);
3394 break;
3395 default:
3396 break;
3397 }
3398 }
3399
3400 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3401 {
3402 struct vcpu_svm *svm = to_svm(vcpu);
3403 struct vmcb_control_area *control = &svm->vmcb->control;
3404
3405 control->exit_int_info = control->event_inj;
3406 control->exit_int_info_err = control->event_inj_err;
3407 control->event_inj = 0;
3408 svm_complete_interrupts(svm);
3409 }
3410
3411 #ifdef CONFIG_X86_64
3412 #define R "r"
3413 #else
3414 #define R "e"
3415 #endif
3416
3417 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3418 {
3419 struct vcpu_svm *svm = to_svm(vcpu);
3420
3421 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3422 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3423 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3424
3425 /*
3426 * A vmexit emulation is required before the vcpu can be executed
3427 * again.
3428 */
3429 if (unlikely(svm->nested.exit_required))
3430 return;
3431
3432 pre_svm_run(svm);
3433
3434 sync_lapic_to_cr8(vcpu);
3435
3436 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3437
3438 clgi();
3439
3440 local_irq_enable();
3441
3442 asm volatile (
3443 "push %%"R"bp; \n\t"
3444 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3445 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3446 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3447 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3448 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3449 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3450 #ifdef CONFIG_X86_64
3451 "mov %c[r8](%[svm]), %%r8 \n\t"
3452 "mov %c[r9](%[svm]), %%r9 \n\t"
3453 "mov %c[r10](%[svm]), %%r10 \n\t"
3454 "mov %c[r11](%[svm]), %%r11 \n\t"
3455 "mov %c[r12](%[svm]), %%r12 \n\t"
3456 "mov %c[r13](%[svm]), %%r13 \n\t"
3457 "mov %c[r14](%[svm]), %%r14 \n\t"
3458 "mov %c[r15](%[svm]), %%r15 \n\t"
3459 #endif
3460
3461 /* Enter guest mode */
3462 "push %%"R"ax \n\t"
3463 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3464 __ex(SVM_VMLOAD) "\n\t"
3465 __ex(SVM_VMRUN) "\n\t"
3466 __ex(SVM_VMSAVE) "\n\t"
3467 "pop %%"R"ax \n\t"
3468
3469 /* Save guest registers, load host registers */
3470 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3471 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3472 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3473 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3474 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3475 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3476 #ifdef CONFIG_X86_64
3477 "mov %%r8, %c[r8](%[svm]) \n\t"
3478 "mov %%r9, %c[r9](%[svm]) \n\t"
3479 "mov %%r10, %c[r10](%[svm]) \n\t"
3480 "mov %%r11, %c[r11](%[svm]) \n\t"
3481 "mov %%r12, %c[r12](%[svm]) \n\t"
3482 "mov %%r13, %c[r13](%[svm]) \n\t"
3483 "mov %%r14, %c[r14](%[svm]) \n\t"
3484 "mov %%r15, %c[r15](%[svm]) \n\t"
3485 #endif
3486 "pop %%"R"bp"
3487 :
3488 : [svm]"a"(svm),
3489 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3490 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3491 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3492 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3493 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3494 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3495 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3496 #ifdef CONFIG_X86_64
3497 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3498 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3499 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3500 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3501 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3502 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3503 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3504 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3505 #endif
3506 : "cc", "memory"
3507 , R"bx", R"cx", R"dx", R"si", R"di"
3508 #ifdef CONFIG_X86_64
3509 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3510 #endif
3511 );
3512
3513 #ifdef CONFIG_X86_64
3514 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3515 #else
3516 loadsegment(fs, svm->host.fs);
3517 #endif
3518
3519 reload_tss(vcpu);
3520
3521 local_irq_disable();
3522
3523 stgi();
3524
3525 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3526 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3527 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3528 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3529
3530 sync_cr8_to_lapic(vcpu);
3531
3532 svm->next_rip = 0;
3533
3534 /* if exit due to PF check for async PF */
3535 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3536 svm->apf_reason = kvm_read_and_reset_pf_reason();
3537
3538 if (npt_enabled) {
3539 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3540 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3541 }
3542
3543 /*
3544 * We need to handle MC intercepts here before the vcpu has a chance to
3545 * change the physical cpu
3546 */
3547 if (unlikely(svm->vmcb->control.exit_code ==
3548 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3549 svm_handle_mce(svm);
3550
3551 mark_all_clean(svm->vmcb);
3552 }
3553
3554 #undef R
3555
3556 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3557 {
3558 struct vcpu_svm *svm = to_svm(vcpu);
3559
3560 svm->vmcb->save.cr3 = root;
3561 mark_dirty(svm->vmcb, VMCB_CR);
3562 force_new_asid(vcpu);
3563 }
3564
3565 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3566 {
3567 struct vcpu_svm *svm = to_svm(vcpu);
3568
3569 svm->vmcb->control.nested_cr3 = root;
3570 mark_dirty(svm->vmcb, VMCB_NPT);
3571
3572 /* Also sync guest cr3 here in case we live migrate */
3573 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3574 mark_dirty(svm->vmcb, VMCB_CR);
3575
3576 force_new_asid(vcpu);
3577 }
3578
3579 static int is_disabled(void)
3580 {
3581 u64 vm_cr;
3582
3583 rdmsrl(MSR_VM_CR, vm_cr);
3584 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3585 return 1;
3586
3587 return 0;
3588 }
3589
3590 static void
3591 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3592 {
3593 /*
3594 * Patch in the VMMCALL instruction:
3595 */
3596 hypercall[0] = 0x0f;
3597 hypercall[1] = 0x01;
3598 hypercall[2] = 0xd9;
3599 }
3600
3601 static void svm_check_processor_compat(void *rtn)
3602 {
3603 *(int *)rtn = 0;
3604 }
3605
3606 static bool svm_cpu_has_accelerated_tpr(void)
3607 {
3608 return false;
3609 }
3610
3611 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3612 {
3613 return 0;
3614 }
3615
3616 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3617 {
3618 }
3619
3620 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3621 {
3622 switch (func) {
3623 case 0x00000001:
3624 /* Mask out xsave bit as long as it is not supported by SVM */
3625 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3626 break;
3627 case 0x80000001:
3628 if (nested)
3629 entry->ecx |= (1 << 2); /* Set SVM bit */
3630 break;
3631 case 0x8000000A:
3632 entry->eax = 1; /* SVM revision 1 */
3633 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3634 ASID emulation to nested SVM */
3635 entry->ecx = 0; /* Reserved */
3636 entry->edx = 0; /* Per default do not support any
3637 additional features */
3638
3639 /* Support next_rip if host supports it */
3640 if (boot_cpu_has(X86_FEATURE_NRIPS))
3641 entry->edx |= SVM_FEATURE_NRIP;
3642
3643 /* Support NPT for the guest if enabled */
3644 if (npt_enabled)
3645 entry->edx |= SVM_FEATURE_NPT;
3646
3647 break;
3648 }
3649 }
3650
3651 static const struct trace_print_flags svm_exit_reasons_str[] = {
3652 { SVM_EXIT_READ_CR0, "read_cr0" },
3653 { SVM_EXIT_READ_CR3, "read_cr3" },
3654 { SVM_EXIT_READ_CR4, "read_cr4" },
3655 { SVM_EXIT_READ_CR8, "read_cr8" },
3656 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3657 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3658 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3659 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3660 { SVM_EXIT_READ_DR0, "read_dr0" },
3661 { SVM_EXIT_READ_DR1, "read_dr1" },
3662 { SVM_EXIT_READ_DR2, "read_dr2" },
3663 { SVM_EXIT_READ_DR3, "read_dr3" },
3664 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3665 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3666 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3667 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3668 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3669 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3670 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3671 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3672 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3673 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3674 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3675 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3676 { SVM_EXIT_INTR, "interrupt" },
3677 { SVM_EXIT_NMI, "nmi" },
3678 { SVM_EXIT_SMI, "smi" },
3679 { SVM_EXIT_INIT, "init" },
3680 { SVM_EXIT_VINTR, "vintr" },
3681 { SVM_EXIT_CPUID, "cpuid" },
3682 { SVM_EXIT_INVD, "invd" },
3683 { SVM_EXIT_HLT, "hlt" },
3684 { SVM_EXIT_INVLPG, "invlpg" },
3685 { SVM_EXIT_INVLPGA, "invlpga" },
3686 { SVM_EXIT_IOIO, "io" },
3687 { SVM_EXIT_MSR, "msr" },
3688 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3689 { SVM_EXIT_SHUTDOWN, "shutdown" },
3690 { SVM_EXIT_VMRUN, "vmrun" },
3691 { SVM_EXIT_VMMCALL, "hypercall" },
3692 { SVM_EXIT_VMLOAD, "vmload" },
3693 { SVM_EXIT_VMSAVE, "vmsave" },
3694 { SVM_EXIT_STGI, "stgi" },
3695 { SVM_EXIT_CLGI, "clgi" },
3696 { SVM_EXIT_SKINIT, "skinit" },
3697 { SVM_EXIT_WBINVD, "wbinvd" },
3698 { SVM_EXIT_MONITOR, "monitor" },
3699 { SVM_EXIT_MWAIT, "mwait" },
3700 { SVM_EXIT_NPF, "npf" },
3701 { -1, NULL }
3702 };
3703
3704 static int svm_get_lpage_level(void)
3705 {
3706 return PT_PDPE_LEVEL;
3707 }
3708
3709 static bool svm_rdtscp_supported(void)
3710 {
3711 return false;
3712 }
3713
3714 static bool svm_has_wbinvd_exit(void)
3715 {
3716 return true;
3717 }
3718
3719 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3720 {
3721 struct vcpu_svm *svm = to_svm(vcpu);
3722
3723 set_exception_intercept(svm, NM_VECTOR);
3724 update_cr0_intercept(svm);
3725 }
3726
3727 static struct kvm_x86_ops svm_x86_ops = {
3728 .cpu_has_kvm_support = has_svm,
3729 .disabled_by_bios = is_disabled,
3730 .hardware_setup = svm_hardware_setup,
3731 .hardware_unsetup = svm_hardware_unsetup,
3732 .check_processor_compatibility = svm_check_processor_compat,
3733 .hardware_enable = svm_hardware_enable,
3734 .hardware_disable = svm_hardware_disable,
3735 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3736
3737 .vcpu_create = svm_create_vcpu,
3738 .vcpu_free = svm_free_vcpu,
3739 .vcpu_reset = svm_vcpu_reset,
3740
3741 .prepare_guest_switch = svm_prepare_guest_switch,
3742 .vcpu_load = svm_vcpu_load,
3743 .vcpu_put = svm_vcpu_put,
3744
3745 .set_guest_debug = svm_guest_debug,
3746 .get_msr = svm_get_msr,
3747 .set_msr = svm_set_msr,
3748 .get_segment_base = svm_get_segment_base,
3749 .get_segment = svm_get_segment,
3750 .set_segment = svm_set_segment,
3751 .get_cpl = svm_get_cpl,
3752 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3753 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3754 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3755 .set_cr0 = svm_set_cr0,
3756 .set_cr3 = svm_set_cr3,
3757 .set_cr4 = svm_set_cr4,
3758 .set_efer = svm_set_efer,
3759 .get_idt = svm_get_idt,
3760 .set_idt = svm_set_idt,
3761 .get_gdt = svm_get_gdt,
3762 .set_gdt = svm_set_gdt,
3763 .set_dr7 = svm_set_dr7,
3764 .cache_reg = svm_cache_reg,
3765 .get_rflags = svm_get_rflags,
3766 .set_rflags = svm_set_rflags,
3767 .fpu_activate = svm_fpu_activate,
3768 .fpu_deactivate = svm_fpu_deactivate,
3769
3770 .tlb_flush = svm_flush_tlb,
3771
3772 .run = svm_vcpu_run,
3773 .handle_exit = handle_exit,
3774 .skip_emulated_instruction = skip_emulated_instruction,
3775 .set_interrupt_shadow = svm_set_interrupt_shadow,
3776 .get_interrupt_shadow = svm_get_interrupt_shadow,
3777 .patch_hypercall = svm_patch_hypercall,
3778 .set_irq = svm_set_irq,
3779 .set_nmi = svm_inject_nmi,
3780 .queue_exception = svm_queue_exception,
3781 .cancel_injection = svm_cancel_injection,
3782 .interrupt_allowed = svm_interrupt_allowed,
3783 .nmi_allowed = svm_nmi_allowed,
3784 .get_nmi_mask = svm_get_nmi_mask,
3785 .set_nmi_mask = svm_set_nmi_mask,
3786 .enable_nmi_window = enable_nmi_window,
3787 .enable_irq_window = enable_irq_window,
3788 .update_cr8_intercept = update_cr8_intercept,
3789
3790 .set_tss_addr = svm_set_tss_addr,
3791 .get_tdp_level = get_npt_level,
3792 .get_mt_mask = svm_get_mt_mask,
3793
3794 .get_exit_info = svm_get_exit_info,
3795 .exit_reasons_str = svm_exit_reasons_str,
3796
3797 .get_lpage_level = svm_get_lpage_level,
3798
3799 .cpuid_update = svm_cpuid_update,
3800
3801 .rdtscp_supported = svm_rdtscp_supported,
3802
3803 .set_supported_cpuid = svm_set_supported_cpuid,
3804
3805 .has_wbinvd_exit = svm_has_wbinvd_exit,
3806
3807 .write_tsc_offset = svm_write_tsc_offset,
3808 .adjust_tsc_offset = svm_adjust_tsc_offset,
3809
3810 .set_tdp_cr3 = set_tdp_cr3,
3811 };
3812
3813 static int __init svm_init(void)
3814 {
3815 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3816 __alignof__(struct vcpu_svm), THIS_MODULE);
3817 }
3818
3819 static void __exit svm_exit(void)
3820 {
3821 kvm_exit();
3822 }
3823
3824 module_init(svm_init)
3825 module_exit(svm_exit)
Linux kernel - Deliverables
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