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KVM: SVM: Fold save_host_msrs() and load_host_msrs() into their callers
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
108 /* Nested Paging related state */
109 u64 nested_cr3;
110 };
111
112 #define MSRPM_OFFSETS 16
113 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
115 struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
127 struct {
128 u16 fs;
129 u16 gs;
130 u16 ldt;
131 u64 gs_base;
132 } host;
133
134 u32 *msrpm;
135
136 struct nested_state nested;
137
138 bool nmi_singlestep;
139
140 unsigned int3_injected;
141 unsigned long int3_rip;
142 u32 apf_reason;
143 };
144
145 #define MSR_INVALID 0xffffffffU
146
147 static struct svm_direct_access_msrs {
148 u32 index; /* Index of the MSR */
149 bool always; /* True if intercept is always on */
150 } direct_access_msrs[] = {
151 { .index = MSR_STAR, .always = true },
152 { .index = MSR_IA32_SYSENTER_CS, .always = true },
153 #ifdef CONFIG_X86_64
154 { .index = MSR_GS_BASE, .always = true },
155 { .index = MSR_FS_BASE, .always = true },
156 { .index = MSR_KERNEL_GS_BASE, .always = true },
157 { .index = MSR_LSTAR, .always = true },
158 { .index = MSR_CSTAR, .always = true },
159 { .index = MSR_SYSCALL_MASK, .always = true },
160 #endif
161 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
162 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
163 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
164 { .index = MSR_IA32_LASTINTTOIP, .always = false },
165 { .index = MSR_INVALID, .always = false },
166 };
167
168 /* enable NPT for AMD64 and X86 with PAE */
169 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
170 static bool npt_enabled = true;
171 #else
172 static bool npt_enabled;
173 #endif
174 static int npt = 1;
175
176 module_param(npt, int, S_IRUGO);
177
178 static int nested = 1;
179 module_param(nested, int, S_IRUGO);
180
181 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
182 static void svm_complete_interrupts(struct vcpu_svm *svm);
183
184 static int nested_svm_exit_handled(struct vcpu_svm *svm);
185 static int nested_svm_intercept(struct vcpu_svm *svm);
186 static int nested_svm_vmexit(struct vcpu_svm *svm);
187 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
188 bool has_error_code, u32 error_code);
189
190 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
191 {
192 return container_of(vcpu, struct vcpu_svm, vcpu);
193 }
194
195 static inline bool is_nested(struct vcpu_svm *svm)
196 {
197 return svm->nested.vmcb;
198 }
199
200 static inline void enable_gif(struct vcpu_svm *svm)
201 {
202 svm->vcpu.arch.hflags |= HF_GIF_MASK;
203 }
204
205 static inline void disable_gif(struct vcpu_svm *svm)
206 {
207 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
208 }
209
210 static inline bool gif_set(struct vcpu_svm *svm)
211 {
212 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
213 }
214
215 static unsigned long iopm_base;
216
217 struct kvm_ldttss_desc {
218 u16 limit0;
219 u16 base0;
220 unsigned base1:8, type:5, dpl:2, p:1;
221 unsigned limit1:4, zero0:3, g:1, base2:8;
222 u32 base3;
223 u32 zero1;
224 } __attribute__((packed));
225
226 struct svm_cpu_data {
227 int cpu;
228
229 u64 asid_generation;
230 u32 max_asid;
231 u32 next_asid;
232 struct kvm_ldttss_desc *tss_desc;
233
234 struct page *save_area;
235 };
236
237 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
238 static uint32_t svm_features;
239
240 struct svm_init_data {
241 int cpu;
242 int r;
243 };
244
245 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
246
247 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
248 #define MSRS_RANGE_SIZE 2048
249 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
250
251 static u32 svm_msrpm_offset(u32 msr)
252 {
253 u32 offset;
254 int i;
255
256 for (i = 0; i < NUM_MSR_MAPS; i++) {
257 if (msr < msrpm_ranges[i] ||
258 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
259 continue;
260
261 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
262 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
263
264 /* Now we have the u8 offset - but need the u32 offset */
265 return offset / 4;
266 }
267
268 /* MSR not in any range */
269 return MSR_INVALID;
270 }
271
272 #define MAX_INST_SIZE 15
273
274 static inline u32 svm_has(u32 feat)
275 {
276 return svm_features & feat;
277 }
278
279 static inline void clgi(void)
280 {
281 asm volatile (__ex(SVM_CLGI));
282 }
283
284 static inline void stgi(void)
285 {
286 asm volatile (__ex(SVM_STGI));
287 }
288
289 static inline void invlpga(unsigned long addr, u32 asid)
290 {
291 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
292 }
293
294 static inline void force_new_asid(struct kvm_vcpu *vcpu)
295 {
296 to_svm(vcpu)->asid_generation--;
297 }
298
299 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
300 {
301 force_new_asid(vcpu);
302 }
303
304 static int get_npt_level(void)
305 {
306 #ifdef CONFIG_X86_64
307 return PT64_ROOT_LEVEL;
308 #else
309 return PT32E_ROOT_LEVEL;
310 #endif
311 }
312
313 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
314 {
315 vcpu->arch.efer = efer;
316 if (!npt_enabled && !(efer & EFER_LMA))
317 efer &= ~EFER_LME;
318
319 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
320 }
321
322 static int is_external_interrupt(u32 info)
323 {
324 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
325 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
326 }
327
328 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
329 {
330 struct vcpu_svm *svm = to_svm(vcpu);
331 u32 ret = 0;
332
333 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
334 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
335 return ret & mask;
336 }
337
338 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
339 {
340 struct vcpu_svm *svm = to_svm(vcpu);
341
342 if (mask == 0)
343 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
344 else
345 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
346
347 }
348
349 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
350 {
351 struct vcpu_svm *svm = to_svm(vcpu);
352
353 if (svm->vmcb->control.next_rip != 0)
354 svm->next_rip = svm->vmcb->control.next_rip;
355
356 if (!svm->next_rip) {
357 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
358 EMULATE_DONE)
359 printk(KERN_DEBUG "%s: NOP\n", __func__);
360 return;
361 }
362 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
363 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
364 __func__, kvm_rip_read(vcpu), svm->next_rip);
365
366 kvm_rip_write(vcpu, svm->next_rip);
367 svm_set_interrupt_shadow(vcpu, 0);
368 }
369
370 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
371 bool has_error_code, u32 error_code,
372 bool reinject)
373 {
374 struct vcpu_svm *svm = to_svm(vcpu);
375
376 /*
377 * If we are within a nested VM we'd better #VMEXIT and let the guest
378 * handle the exception
379 */
380 if (!reinject &&
381 nested_svm_check_exception(svm, nr, has_error_code, error_code))
382 return;
383
384 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
385 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
386
387 /*
388 * For guest debugging where we have to reinject #BP if some
389 * INT3 is guest-owned:
390 * Emulate nRIP by moving RIP forward. Will fail if injection
391 * raises a fault that is not intercepted. Still better than
392 * failing in all cases.
393 */
394 skip_emulated_instruction(&svm->vcpu);
395 rip = kvm_rip_read(&svm->vcpu);
396 svm->int3_rip = rip + svm->vmcb->save.cs.base;
397 svm->int3_injected = rip - old_rip;
398 }
399
400 svm->vmcb->control.event_inj = nr
401 | SVM_EVTINJ_VALID
402 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
403 | SVM_EVTINJ_TYPE_EXEPT;
404 svm->vmcb->control.event_inj_err = error_code;
405 }
406
407 static void svm_init_erratum_383(void)
408 {
409 u32 low, high;
410 int err;
411 u64 val;
412
413 if (!cpu_has_amd_erratum(amd_erratum_383))
414 return;
415
416 /* Use _safe variants to not break nested virtualization */
417 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
418 if (err)
419 return;
420
421 val |= (1ULL << 47);
422
423 low = lower_32_bits(val);
424 high = upper_32_bits(val);
425
426 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
427
428 erratum_383_found = true;
429 }
430
431 static int has_svm(void)
432 {
433 const char *msg;
434
435 if (!cpu_has_svm(&msg)) {
436 printk(KERN_INFO "has_svm: %s\n", msg);
437 return 0;
438 }
439
440 return 1;
441 }
442
443 static void svm_hardware_disable(void *garbage)
444 {
445 cpu_svm_disable();
446 }
447
448 static int svm_hardware_enable(void *garbage)
449 {
450
451 struct svm_cpu_data *sd;
452 uint64_t efer;
453 struct desc_ptr gdt_descr;
454 struct desc_struct *gdt;
455 int me = raw_smp_processor_id();
456
457 rdmsrl(MSR_EFER, efer);
458 if (efer & EFER_SVME)
459 return -EBUSY;
460
461 if (!has_svm()) {
462 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
463 me);
464 return -EINVAL;
465 }
466 sd = per_cpu(svm_data, me);
467
468 if (!sd) {
469 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
470 me);
471 return -EINVAL;
472 }
473
474 sd->asid_generation = 1;
475 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
476 sd->next_asid = sd->max_asid + 1;
477
478 native_store_gdt(&gdt_descr);
479 gdt = (struct desc_struct *)gdt_descr.address;
480 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
481
482 wrmsrl(MSR_EFER, efer | EFER_SVME);
483
484 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
485
486 svm_init_erratum_383();
487
488 return 0;
489 }
490
491 static void svm_cpu_uninit(int cpu)
492 {
493 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
494
495 if (!sd)
496 return;
497
498 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
499 __free_page(sd->save_area);
500 kfree(sd);
501 }
502
503 static int svm_cpu_init(int cpu)
504 {
505 struct svm_cpu_data *sd;
506 int r;
507
508 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
509 if (!sd)
510 return -ENOMEM;
511 sd->cpu = cpu;
512 sd->save_area = alloc_page(GFP_KERNEL);
513 r = -ENOMEM;
514 if (!sd->save_area)
515 goto err_1;
516
517 per_cpu(svm_data, cpu) = sd;
518
519 return 0;
520
521 err_1:
522 kfree(sd);
523 return r;
524
525 }
526
527 static bool valid_msr_intercept(u32 index)
528 {
529 int i;
530
531 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
532 if (direct_access_msrs[i].index == index)
533 return true;
534
535 return false;
536 }
537
538 static void set_msr_interception(u32 *msrpm, unsigned msr,
539 int read, int write)
540 {
541 u8 bit_read, bit_write;
542 unsigned long tmp;
543 u32 offset;
544
545 /*
546 * If this warning triggers extend the direct_access_msrs list at the
547 * beginning of the file
548 */
549 WARN_ON(!valid_msr_intercept(msr));
550
551 offset = svm_msrpm_offset(msr);
552 bit_read = 2 * (msr & 0x0f);
553 bit_write = 2 * (msr & 0x0f) + 1;
554 tmp = msrpm[offset];
555
556 BUG_ON(offset == MSR_INVALID);
557
558 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
559 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
560
561 msrpm[offset] = tmp;
562 }
563
564 static void svm_vcpu_init_msrpm(u32 *msrpm)
565 {
566 int i;
567
568 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
569
570 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
571 if (!direct_access_msrs[i].always)
572 continue;
573
574 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
575 }
576 }
577
578 static void add_msr_offset(u32 offset)
579 {
580 int i;
581
582 for (i = 0; i < MSRPM_OFFSETS; ++i) {
583
584 /* Offset already in list? */
585 if (msrpm_offsets[i] == offset)
586 return;
587
588 /* Slot used by another offset? */
589 if (msrpm_offsets[i] != MSR_INVALID)
590 continue;
591
592 /* Add offset to list */
593 msrpm_offsets[i] = offset;
594
595 return;
596 }
597
598 /*
599 * If this BUG triggers the msrpm_offsets table has an overflow. Just
600 * increase MSRPM_OFFSETS in this case.
601 */
602 BUG();
603 }
604
605 static void init_msrpm_offsets(void)
606 {
607 int i;
608
609 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
610
611 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
612 u32 offset;
613
614 offset = svm_msrpm_offset(direct_access_msrs[i].index);
615 BUG_ON(offset == MSR_INVALID);
616
617 add_msr_offset(offset);
618 }
619 }
620
621 static void svm_enable_lbrv(struct vcpu_svm *svm)
622 {
623 u32 *msrpm = svm->msrpm;
624
625 svm->vmcb->control.lbr_ctl = 1;
626 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
627 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
628 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
629 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
630 }
631
632 static void svm_disable_lbrv(struct vcpu_svm *svm)
633 {
634 u32 *msrpm = svm->msrpm;
635
636 svm->vmcb->control.lbr_ctl = 0;
637 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
638 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
639 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
640 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
641 }
642
643 static __init int svm_hardware_setup(void)
644 {
645 int cpu;
646 struct page *iopm_pages;
647 void *iopm_va;
648 int r;
649
650 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
651
652 if (!iopm_pages)
653 return -ENOMEM;
654
655 iopm_va = page_address(iopm_pages);
656 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
657 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
658
659 init_msrpm_offsets();
660
661 if (boot_cpu_has(X86_FEATURE_NX))
662 kvm_enable_efer_bits(EFER_NX);
663
664 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
665 kvm_enable_efer_bits(EFER_FFXSR);
666
667 if (nested) {
668 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
669 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
670 }
671
672 for_each_possible_cpu(cpu) {
673 r = svm_cpu_init(cpu);
674 if (r)
675 goto err;
676 }
677
678 svm_features = cpuid_edx(SVM_CPUID_FUNC);
679
680 if (!svm_has(SVM_FEATURE_NPT))
681 npt_enabled = false;
682
683 if (npt_enabled && !npt) {
684 printk(KERN_INFO "kvm: Nested Paging disabled\n");
685 npt_enabled = false;
686 }
687
688 if (npt_enabled) {
689 printk(KERN_INFO "kvm: Nested Paging enabled\n");
690 kvm_enable_tdp();
691 } else
692 kvm_disable_tdp();
693
694 return 0;
695
696 err:
697 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
698 iopm_base = 0;
699 return r;
700 }
701
702 static __exit void svm_hardware_unsetup(void)
703 {
704 int cpu;
705
706 for_each_possible_cpu(cpu)
707 svm_cpu_uninit(cpu);
708
709 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
710 iopm_base = 0;
711 }
712
713 static void init_seg(struct vmcb_seg *seg)
714 {
715 seg->selector = 0;
716 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
717 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
718 seg->limit = 0xffff;
719 seg->base = 0;
720 }
721
722 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
723 {
724 seg->selector = 0;
725 seg->attrib = SVM_SELECTOR_P_MASK | type;
726 seg->limit = 0xffff;
727 seg->base = 0;
728 }
729
730 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
731 {
732 struct vcpu_svm *svm = to_svm(vcpu);
733 u64 g_tsc_offset = 0;
734
735 if (is_nested(svm)) {
736 g_tsc_offset = svm->vmcb->control.tsc_offset -
737 svm->nested.hsave->control.tsc_offset;
738 svm->nested.hsave->control.tsc_offset = offset;
739 }
740
741 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
742 }
743
744 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
745 {
746 struct vcpu_svm *svm = to_svm(vcpu);
747
748 svm->vmcb->control.tsc_offset += adjustment;
749 if (is_nested(svm))
750 svm->nested.hsave->control.tsc_offset += adjustment;
751 }
752
753 static void init_vmcb(struct vcpu_svm *svm)
754 {
755 struct vmcb_control_area *control = &svm->vmcb->control;
756 struct vmcb_save_area *save = &svm->vmcb->save;
757
758 svm->vcpu.fpu_active = 1;
759
760 control->intercept_cr_read = INTERCEPT_CR0_MASK |
761 INTERCEPT_CR3_MASK |
762 INTERCEPT_CR4_MASK;
763
764 control->intercept_cr_write = INTERCEPT_CR0_MASK |
765 INTERCEPT_CR3_MASK |
766 INTERCEPT_CR4_MASK |
767 INTERCEPT_CR8_MASK;
768
769 control->intercept_dr_read = INTERCEPT_DR0_MASK |
770 INTERCEPT_DR1_MASK |
771 INTERCEPT_DR2_MASK |
772 INTERCEPT_DR3_MASK |
773 INTERCEPT_DR4_MASK |
774 INTERCEPT_DR5_MASK |
775 INTERCEPT_DR6_MASK |
776 INTERCEPT_DR7_MASK;
777
778 control->intercept_dr_write = INTERCEPT_DR0_MASK |
779 INTERCEPT_DR1_MASK |
780 INTERCEPT_DR2_MASK |
781 INTERCEPT_DR3_MASK |
782 INTERCEPT_DR4_MASK |
783 INTERCEPT_DR5_MASK |
784 INTERCEPT_DR6_MASK |
785 INTERCEPT_DR7_MASK;
786
787 control->intercept_exceptions = (1 << PF_VECTOR) |
788 (1 << UD_VECTOR) |
789 (1 << MC_VECTOR);
790
791
792 control->intercept = (1ULL << INTERCEPT_INTR) |
793 (1ULL << INTERCEPT_NMI) |
794 (1ULL << INTERCEPT_SMI) |
795 (1ULL << INTERCEPT_SELECTIVE_CR0) |
796 (1ULL << INTERCEPT_CPUID) |
797 (1ULL << INTERCEPT_INVD) |
798 (1ULL << INTERCEPT_HLT) |
799 (1ULL << INTERCEPT_INVLPG) |
800 (1ULL << INTERCEPT_INVLPGA) |
801 (1ULL << INTERCEPT_IOIO_PROT) |
802 (1ULL << INTERCEPT_MSR_PROT) |
803 (1ULL << INTERCEPT_TASK_SWITCH) |
804 (1ULL << INTERCEPT_SHUTDOWN) |
805 (1ULL << INTERCEPT_VMRUN) |
806 (1ULL << INTERCEPT_VMMCALL) |
807 (1ULL << INTERCEPT_VMLOAD) |
808 (1ULL << INTERCEPT_VMSAVE) |
809 (1ULL << INTERCEPT_STGI) |
810 (1ULL << INTERCEPT_CLGI) |
811 (1ULL << INTERCEPT_SKINIT) |
812 (1ULL << INTERCEPT_WBINVD) |
813 (1ULL << INTERCEPT_MONITOR) |
814 (1ULL << INTERCEPT_MWAIT);
815
816 control->iopm_base_pa = iopm_base;
817 control->msrpm_base_pa = __pa(svm->msrpm);
818 control->int_ctl = V_INTR_MASKING_MASK;
819
820 init_seg(&save->es);
821 init_seg(&save->ss);
822 init_seg(&save->ds);
823 init_seg(&save->fs);
824 init_seg(&save->gs);
825
826 save->cs.selector = 0xf000;
827 /* Executable/Readable Code Segment */
828 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
829 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
830 save->cs.limit = 0xffff;
831 /*
832 * cs.base should really be 0xffff0000, but vmx can't handle that, so
833 * be consistent with it.
834 *
835 * Replace when we have real mode working for vmx.
836 */
837 save->cs.base = 0xf0000;
838
839 save->gdtr.limit = 0xffff;
840 save->idtr.limit = 0xffff;
841
842 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
843 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
844
845 svm_set_efer(&svm->vcpu, 0);
846 save->dr6 = 0xffff0ff0;
847 save->dr7 = 0x400;
848 save->rflags = 2;
849 save->rip = 0x0000fff0;
850 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
851
852 /*
853 * This is the guest-visible cr0 value.
854 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
855 */
856 svm->vcpu.arch.cr0 = 0;
857 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
858
859 save->cr4 = X86_CR4_PAE;
860 /* rdx = ?? */
861
862 if (npt_enabled) {
863 /* Setup VMCB for Nested Paging */
864 control->nested_ctl = 1;
865 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
866 (1ULL << INTERCEPT_INVLPG));
867 control->intercept_exceptions &= ~(1 << PF_VECTOR);
868 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
869 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
870 save->g_pat = 0x0007040600070406ULL;
871 save->cr3 = 0;
872 save->cr4 = 0;
873 }
874 force_new_asid(&svm->vcpu);
875
876 svm->nested.vmcb = 0;
877 svm->vcpu.arch.hflags = 0;
878
879 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
880 control->pause_filter_count = 3000;
881 control->intercept |= (1ULL << INTERCEPT_PAUSE);
882 }
883
884 enable_gif(svm);
885 }
886
887 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
888 {
889 struct vcpu_svm *svm = to_svm(vcpu);
890
891 init_vmcb(svm);
892
893 if (!kvm_vcpu_is_bsp(vcpu)) {
894 kvm_rip_write(vcpu, 0);
895 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
896 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
897 }
898 vcpu->arch.regs_avail = ~0;
899 vcpu->arch.regs_dirty = ~0;
900
901 return 0;
902 }
903
904 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
905 {
906 struct vcpu_svm *svm;
907 struct page *page;
908 struct page *msrpm_pages;
909 struct page *hsave_page;
910 struct page *nested_msrpm_pages;
911 int err;
912
913 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
914 if (!svm) {
915 err = -ENOMEM;
916 goto out;
917 }
918
919 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
920 if (err)
921 goto free_svm;
922
923 err = -ENOMEM;
924 page = alloc_page(GFP_KERNEL);
925 if (!page)
926 goto uninit;
927
928 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
929 if (!msrpm_pages)
930 goto free_page1;
931
932 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
933 if (!nested_msrpm_pages)
934 goto free_page2;
935
936 hsave_page = alloc_page(GFP_KERNEL);
937 if (!hsave_page)
938 goto free_page3;
939
940 svm->nested.hsave = page_address(hsave_page);
941
942 svm->msrpm = page_address(msrpm_pages);
943 svm_vcpu_init_msrpm(svm->msrpm);
944
945 svm->nested.msrpm = page_address(nested_msrpm_pages);
946 svm_vcpu_init_msrpm(svm->nested.msrpm);
947
948 svm->vmcb = page_address(page);
949 clear_page(svm->vmcb);
950 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
951 svm->asid_generation = 0;
952 init_vmcb(svm);
953 kvm_write_tsc(&svm->vcpu, 0);
954
955 err = fx_init(&svm->vcpu);
956 if (err)
957 goto free_page4;
958
959 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
960 if (kvm_vcpu_is_bsp(&svm->vcpu))
961 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
962
963 return &svm->vcpu;
964
965 free_page4:
966 __free_page(hsave_page);
967 free_page3:
968 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
969 free_page2:
970 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
971 free_page1:
972 __free_page(page);
973 uninit:
974 kvm_vcpu_uninit(&svm->vcpu);
975 free_svm:
976 kmem_cache_free(kvm_vcpu_cache, svm);
977 out:
978 return ERR_PTR(err);
979 }
980
981 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
982 {
983 struct vcpu_svm *svm = to_svm(vcpu);
984
985 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
986 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
987 __free_page(virt_to_page(svm->nested.hsave));
988 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
989 kvm_vcpu_uninit(vcpu);
990 kmem_cache_free(kvm_vcpu_cache, svm);
991 }
992
993 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
994 {
995 struct vcpu_svm *svm = to_svm(vcpu);
996 int i;
997
998 if (unlikely(cpu != vcpu->cpu)) {
999 svm->asid_generation = 0;
1000 }
1001
1002 #ifdef CONFIG_X86_64
1003 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1004 #endif
1005 savesegment(fs, svm->host.fs);
1006 savesegment(gs, svm->host.gs);
1007 svm->host.ldt = kvm_read_ldt();
1008
1009 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1010 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1011 }
1012
1013 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1014 {
1015 struct vcpu_svm *svm = to_svm(vcpu);
1016 int i;
1017
1018 ++vcpu->stat.host_state_reload;
1019 kvm_load_ldt(svm->host.ldt);
1020 #ifdef CONFIG_X86_64
1021 loadsegment(fs, svm->host.fs);
1022 load_gs_index(svm->host.gs);
1023 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1024 #else
1025 loadsegment(gs, svm->host.gs);
1026 #endif
1027 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1028 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1029 }
1030
1031 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1032 {
1033 return to_svm(vcpu)->vmcb->save.rflags;
1034 }
1035
1036 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1037 {
1038 to_svm(vcpu)->vmcb->save.rflags = rflags;
1039 }
1040
1041 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1042 {
1043 switch (reg) {
1044 case VCPU_EXREG_PDPTR:
1045 BUG_ON(!npt_enabled);
1046 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1047 break;
1048 default:
1049 BUG();
1050 }
1051 }
1052
1053 static void svm_set_vintr(struct vcpu_svm *svm)
1054 {
1055 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1056 }
1057
1058 static void svm_clear_vintr(struct vcpu_svm *svm)
1059 {
1060 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1061 }
1062
1063 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1064 {
1065 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1066
1067 switch (seg) {
1068 case VCPU_SREG_CS: return &save->cs;
1069 case VCPU_SREG_DS: return &save->ds;
1070 case VCPU_SREG_ES: return &save->es;
1071 case VCPU_SREG_FS: return &save->fs;
1072 case VCPU_SREG_GS: return &save->gs;
1073 case VCPU_SREG_SS: return &save->ss;
1074 case VCPU_SREG_TR: return &save->tr;
1075 case VCPU_SREG_LDTR: return &save->ldtr;
1076 }
1077 BUG();
1078 return NULL;
1079 }
1080
1081 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1082 {
1083 struct vmcb_seg *s = svm_seg(vcpu, seg);
1084
1085 return s->base;
1086 }
1087
1088 static void svm_get_segment(struct kvm_vcpu *vcpu,
1089 struct kvm_segment *var, int seg)
1090 {
1091 struct vmcb_seg *s = svm_seg(vcpu, seg);
1092
1093 var->base = s->base;
1094 var->limit = s->limit;
1095 var->selector = s->selector;
1096 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1097 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1098 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1099 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1100 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1101 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1102 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1103 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1104
1105 /*
1106 * AMD's VMCB does not have an explicit unusable field, so emulate it
1107 * for cross vendor migration purposes by "not present"
1108 */
1109 var->unusable = !var->present || (var->type == 0);
1110
1111 switch (seg) {
1112 case VCPU_SREG_CS:
1113 /*
1114 * SVM always stores 0 for the 'G' bit in the CS selector in
1115 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1116 * Intel's VMENTRY has a check on the 'G' bit.
1117 */
1118 var->g = s->limit > 0xfffff;
1119 break;
1120 case VCPU_SREG_TR:
1121 /*
1122 * Work around a bug where the busy flag in the tr selector
1123 * isn't exposed
1124 */
1125 var->type |= 0x2;
1126 break;
1127 case VCPU_SREG_DS:
1128 case VCPU_SREG_ES:
1129 case VCPU_SREG_FS:
1130 case VCPU_SREG_GS:
1131 /*
1132 * The accessed bit must always be set in the segment
1133 * descriptor cache, although it can be cleared in the
1134 * descriptor, the cached bit always remains at 1. Since
1135 * Intel has a check on this, set it here to support
1136 * cross-vendor migration.
1137 */
1138 if (!var->unusable)
1139 var->type |= 0x1;
1140 break;
1141 case VCPU_SREG_SS:
1142 /*
1143 * On AMD CPUs sometimes the DB bit in the segment
1144 * descriptor is left as 1, although the whole segment has
1145 * been made unusable. Clear it here to pass an Intel VMX
1146 * entry check when cross vendor migrating.
1147 */
1148 if (var->unusable)
1149 var->db = 0;
1150 break;
1151 }
1152 }
1153
1154 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1155 {
1156 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1157
1158 return save->cpl;
1159 }
1160
1161 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1162 {
1163 struct vcpu_svm *svm = to_svm(vcpu);
1164
1165 dt->size = svm->vmcb->save.idtr.limit;
1166 dt->address = svm->vmcb->save.idtr.base;
1167 }
1168
1169 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1170 {
1171 struct vcpu_svm *svm = to_svm(vcpu);
1172
1173 svm->vmcb->save.idtr.limit = dt->size;
1174 svm->vmcb->save.idtr.base = dt->address ;
1175 }
1176
1177 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1178 {
1179 struct vcpu_svm *svm = to_svm(vcpu);
1180
1181 dt->size = svm->vmcb->save.gdtr.limit;
1182 dt->address = svm->vmcb->save.gdtr.base;
1183 }
1184
1185 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1186 {
1187 struct vcpu_svm *svm = to_svm(vcpu);
1188
1189 svm->vmcb->save.gdtr.limit = dt->size;
1190 svm->vmcb->save.gdtr.base = dt->address ;
1191 }
1192
1193 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1194 {
1195 }
1196
1197 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1198 {
1199 }
1200
1201 static void update_cr0_intercept(struct vcpu_svm *svm)
1202 {
1203 struct vmcb *vmcb = svm->vmcb;
1204 ulong gcr0 = svm->vcpu.arch.cr0;
1205 u64 *hcr0 = &svm->vmcb->save.cr0;
1206
1207 if (!svm->vcpu.fpu_active)
1208 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1209 else
1210 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1211 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1212
1213
1214 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1215 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1216 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1217 if (is_nested(svm)) {
1218 struct vmcb *hsave = svm->nested.hsave;
1219
1220 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1221 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1222 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1223 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1224 }
1225 } else {
1226 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1227 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1228 if (is_nested(svm)) {
1229 struct vmcb *hsave = svm->nested.hsave;
1230
1231 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1232 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1233 }
1234 }
1235 }
1236
1237 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1238 {
1239 struct vcpu_svm *svm = to_svm(vcpu);
1240
1241 if (is_nested(svm)) {
1242 /*
1243 * We are here because we run in nested mode, the host kvm
1244 * intercepts cr0 writes but the l1 hypervisor does not.
1245 * But the L1 hypervisor may intercept selective cr0 writes.
1246 * This needs to be checked here.
1247 */
1248 unsigned long old, new;
1249
1250 /* Remove bits that would trigger a real cr0 write intercept */
1251 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1252 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1253
1254 if (old == new) {
1255 /* cr0 write with ts and mp unchanged */
1256 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1257 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1258 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1259 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1260 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1261 return;
1262 }
1263 }
1264 }
1265
1266 #ifdef CONFIG_X86_64
1267 if (vcpu->arch.efer & EFER_LME) {
1268 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1269 vcpu->arch.efer |= EFER_LMA;
1270 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1271 }
1272
1273 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1274 vcpu->arch.efer &= ~EFER_LMA;
1275 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1276 }
1277 }
1278 #endif
1279 vcpu->arch.cr0 = cr0;
1280
1281 if (!npt_enabled)
1282 cr0 |= X86_CR0_PG | X86_CR0_WP;
1283
1284 if (!vcpu->fpu_active)
1285 cr0 |= X86_CR0_TS;
1286 /*
1287 * re-enable caching here because the QEMU bios
1288 * does not do it - this results in some delay at
1289 * reboot
1290 */
1291 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1292 svm->vmcb->save.cr0 = cr0;
1293 update_cr0_intercept(svm);
1294 }
1295
1296 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1297 {
1298 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1299 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1300
1301 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1302 force_new_asid(vcpu);
1303
1304 vcpu->arch.cr4 = cr4;
1305 if (!npt_enabled)
1306 cr4 |= X86_CR4_PAE;
1307 cr4 |= host_cr4_mce;
1308 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1309 }
1310
1311 static void svm_set_segment(struct kvm_vcpu *vcpu,
1312 struct kvm_segment *var, int seg)
1313 {
1314 struct vcpu_svm *svm = to_svm(vcpu);
1315 struct vmcb_seg *s = svm_seg(vcpu, seg);
1316
1317 s->base = var->base;
1318 s->limit = var->limit;
1319 s->selector = var->selector;
1320 if (var->unusable)
1321 s->attrib = 0;
1322 else {
1323 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1324 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1325 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1326 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1327 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1328 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1329 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1330 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1331 }
1332 if (seg == VCPU_SREG_CS)
1333 svm->vmcb->save.cpl
1334 = (svm->vmcb->save.cs.attrib
1335 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1336
1337 }
1338
1339 static void update_db_intercept(struct kvm_vcpu *vcpu)
1340 {
1341 struct vcpu_svm *svm = to_svm(vcpu);
1342
1343 svm->vmcb->control.intercept_exceptions &=
1344 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1345
1346 if (svm->nmi_singlestep)
1347 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1348
1349 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1350 if (vcpu->guest_debug &
1351 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1352 svm->vmcb->control.intercept_exceptions |=
1353 1 << DB_VECTOR;
1354 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1355 svm->vmcb->control.intercept_exceptions |=
1356 1 << BP_VECTOR;
1357 } else
1358 vcpu->guest_debug = 0;
1359 }
1360
1361 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1362 {
1363 struct vcpu_svm *svm = to_svm(vcpu);
1364
1365 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1366 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1367 else
1368 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1369
1370 update_db_intercept(vcpu);
1371 }
1372
1373 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1374 {
1375 if (sd->next_asid > sd->max_asid) {
1376 ++sd->asid_generation;
1377 sd->next_asid = 1;
1378 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1379 }
1380
1381 svm->asid_generation = sd->asid_generation;
1382 svm->vmcb->control.asid = sd->next_asid++;
1383 }
1384
1385 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1386 {
1387 struct vcpu_svm *svm = to_svm(vcpu);
1388
1389 svm->vmcb->save.dr7 = value;
1390 }
1391
1392 static int pf_interception(struct vcpu_svm *svm)
1393 {
1394 u64 fault_address = svm->vmcb->control.exit_info_2;
1395 u32 error_code;
1396 int r = 1;
1397
1398 switch (svm->apf_reason) {
1399 default:
1400 error_code = svm->vmcb->control.exit_info_1;
1401
1402 trace_kvm_page_fault(fault_address, error_code);
1403 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1404 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1405 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1406 break;
1407 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1408 svm->apf_reason = 0;
1409 local_irq_disable();
1410 kvm_async_pf_task_wait(fault_address);
1411 local_irq_enable();
1412 break;
1413 case KVM_PV_REASON_PAGE_READY:
1414 svm->apf_reason = 0;
1415 local_irq_disable();
1416 kvm_async_pf_task_wake(fault_address);
1417 local_irq_enable();
1418 break;
1419 }
1420 return r;
1421 }
1422
1423 static int db_interception(struct vcpu_svm *svm)
1424 {
1425 struct kvm_run *kvm_run = svm->vcpu.run;
1426
1427 if (!(svm->vcpu.guest_debug &
1428 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1429 !svm->nmi_singlestep) {
1430 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1431 return 1;
1432 }
1433
1434 if (svm->nmi_singlestep) {
1435 svm->nmi_singlestep = false;
1436 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1437 svm->vmcb->save.rflags &=
1438 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1439 update_db_intercept(&svm->vcpu);
1440 }
1441
1442 if (svm->vcpu.guest_debug &
1443 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1444 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1445 kvm_run->debug.arch.pc =
1446 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1447 kvm_run->debug.arch.exception = DB_VECTOR;
1448 return 0;
1449 }
1450
1451 return 1;
1452 }
1453
1454 static int bp_interception(struct vcpu_svm *svm)
1455 {
1456 struct kvm_run *kvm_run = svm->vcpu.run;
1457
1458 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1459 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1460 kvm_run->debug.arch.exception = BP_VECTOR;
1461 return 0;
1462 }
1463
1464 static int ud_interception(struct vcpu_svm *svm)
1465 {
1466 int er;
1467
1468 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1469 if (er != EMULATE_DONE)
1470 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1471 return 1;
1472 }
1473
1474 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1475 {
1476 struct vcpu_svm *svm = to_svm(vcpu);
1477 u32 excp;
1478
1479 if (is_nested(svm)) {
1480 u32 h_excp, n_excp;
1481
1482 h_excp = svm->nested.hsave->control.intercept_exceptions;
1483 n_excp = svm->nested.intercept_exceptions;
1484 h_excp &= ~(1 << NM_VECTOR);
1485 excp = h_excp | n_excp;
1486 } else {
1487 excp = svm->vmcb->control.intercept_exceptions;
1488 excp &= ~(1 << NM_VECTOR);
1489 }
1490
1491 svm->vmcb->control.intercept_exceptions = excp;
1492
1493 svm->vcpu.fpu_active = 1;
1494 update_cr0_intercept(svm);
1495 }
1496
1497 static int nm_interception(struct vcpu_svm *svm)
1498 {
1499 svm_fpu_activate(&svm->vcpu);
1500 return 1;
1501 }
1502
1503 static bool is_erratum_383(void)
1504 {
1505 int err, i;
1506 u64 value;
1507
1508 if (!erratum_383_found)
1509 return false;
1510
1511 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1512 if (err)
1513 return false;
1514
1515 /* Bit 62 may or may not be set for this mce */
1516 value &= ~(1ULL << 62);
1517
1518 if (value != 0xb600000000010015ULL)
1519 return false;
1520
1521 /* Clear MCi_STATUS registers */
1522 for (i = 0; i < 6; ++i)
1523 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1524
1525 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1526 if (!err) {
1527 u32 low, high;
1528
1529 value &= ~(1ULL << 2);
1530 low = lower_32_bits(value);
1531 high = upper_32_bits(value);
1532
1533 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1534 }
1535
1536 /* Flush tlb to evict multi-match entries */
1537 __flush_tlb_all();
1538
1539 return true;
1540 }
1541
1542 static void svm_handle_mce(struct vcpu_svm *svm)
1543 {
1544 if (is_erratum_383()) {
1545 /*
1546 * Erratum 383 triggered. Guest state is corrupt so kill the
1547 * guest.
1548 */
1549 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1550
1551 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1552
1553 return;
1554 }
1555
1556 /*
1557 * On an #MC intercept the MCE handler is not called automatically in
1558 * the host. So do it by hand here.
1559 */
1560 asm volatile (
1561 "int $0x12\n");
1562 /* not sure if we ever come back to this point */
1563
1564 return;
1565 }
1566
1567 static int mc_interception(struct vcpu_svm *svm)
1568 {
1569 return 1;
1570 }
1571
1572 static int shutdown_interception(struct vcpu_svm *svm)
1573 {
1574 struct kvm_run *kvm_run = svm->vcpu.run;
1575
1576 /*
1577 * VMCB is undefined after a SHUTDOWN intercept
1578 * so reinitialize it.
1579 */
1580 clear_page(svm->vmcb);
1581 init_vmcb(svm);
1582
1583 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1584 return 0;
1585 }
1586
1587 static int io_interception(struct vcpu_svm *svm)
1588 {
1589 struct kvm_vcpu *vcpu = &svm->vcpu;
1590 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1591 int size, in, string;
1592 unsigned port;
1593
1594 ++svm->vcpu.stat.io_exits;
1595 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1596 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1597 if (string || in)
1598 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1599
1600 port = io_info >> 16;
1601 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1602 svm->next_rip = svm->vmcb->control.exit_info_2;
1603 skip_emulated_instruction(&svm->vcpu);
1604
1605 return kvm_fast_pio_out(vcpu, size, port);
1606 }
1607
1608 static int nmi_interception(struct vcpu_svm *svm)
1609 {
1610 return 1;
1611 }
1612
1613 static int intr_interception(struct vcpu_svm *svm)
1614 {
1615 ++svm->vcpu.stat.irq_exits;
1616 return 1;
1617 }
1618
1619 static int nop_on_interception(struct vcpu_svm *svm)
1620 {
1621 return 1;
1622 }
1623
1624 static int halt_interception(struct vcpu_svm *svm)
1625 {
1626 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1627 skip_emulated_instruction(&svm->vcpu);
1628 return kvm_emulate_halt(&svm->vcpu);
1629 }
1630
1631 static int vmmcall_interception(struct vcpu_svm *svm)
1632 {
1633 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1634 skip_emulated_instruction(&svm->vcpu);
1635 kvm_emulate_hypercall(&svm->vcpu);
1636 return 1;
1637 }
1638
1639 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1640 {
1641 struct vcpu_svm *svm = to_svm(vcpu);
1642
1643 return svm->nested.nested_cr3;
1644 }
1645
1646 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1647 unsigned long root)
1648 {
1649 struct vcpu_svm *svm = to_svm(vcpu);
1650
1651 svm->vmcb->control.nested_cr3 = root;
1652 force_new_asid(vcpu);
1653 }
1654
1655 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1656 {
1657 struct vcpu_svm *svm = to_svm(vcpu);
1658
1659 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1660 svm->vmcb->control.exit_code_hi = 0;
1661 svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1662 svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1663
1664 nested_svm_vmexit(svm);
1665 }
1666
1667 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1668 {
1669 int r;
1670
1671 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1672
1673 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1674 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1675 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1676 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1677 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1678
1679 return r;
1680 }
1681
1682 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1683 {
1684 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1685 }
1686
1687 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1688 {
1689 if (!(svm->vcpu.arch.efer & EFER_SVME)
1690 || !is_paging(&svm->vcpu)) {
1691 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1692 return 1;
1693 }
1694
1695 if (svm->vmcb->save.cpl) {
1696 kvm_inject_gp(&svm->vcpu, 0);
1697 return 1;
1698 }
1699
1700 return 0;
1701 }
1702
1703 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1704 bool has_error_code, u32 error_code)
1705 {
1706 int vmexit;
1707
1708 if (!is_nested(svm))
1709 return 0;
1710
1711 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1712 svm->vmcb->control.exit_code_hi = 0;
1713 svm->vmcb->control.exit_info_1 = error_code;
1714 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1715
1716 vmexit = nested_svm_intercept(svm);
1717 if (vmexit == NESTED_EXIT_DONE)
1718 svm->nested.exit_required = true;
1719
1720 return vmexit;
1721 }
1722
1723 /* This function returns true if it is save to enable the irq window */
1724 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1725 {
1726 if (!is_nested(svm))
1727 return true;
1728
1729 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1730 return true;
1731
1732 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1733 return false;
1734
1735 /*
1736 * if vmexit was already requested (by intercepted exception
1737 * for instance) do not overwrite it with "external interrupt"
1738 * vmexit.
1739 */
1740 if (svm->nested.exit_required)
1741 return false;
1742
1743 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1744 svm->vmcb->control.exit_info_1 = 0;
1745 svm->vmcb->control.exit_info_2 = 0;
1746
1747 if (svm->nested.intercept & 1ULL) {
1748 /*
1749 * The #vmexit can't be emulated here directly because this
1750 * code path runs with irqs and preemtion disabled. A
1751 * #vmexit emulation might sleep. Only signal request for
1752 * the #vmexit here.
1753 */
1754 svm->nested.exit_required = true;
1755 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1756 return false;
1757 }
1758
1759 return true;
1760 }
1761
1762 /* This function returns true if it is save to enable the nmi window */
1763 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1764 {
1765 if (!is_nested(svm))
1766 return true;
1767
1768 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1769 return true;
1770
1771 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1772 svm->nested.exit_required = true;
1773
1774 return false;
1775 }
1776
1777 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1778 {
1779 struct page *page;
1780
1781 might_sleep();
1782
1783 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1784 if (is_error_page(page))
1785 goto error;
1786
1787 *_page = page;
1788
1789 return kmap(page);
1790
1791 error:
1792 kvm_release_page_clean(page);
1793 kvm_inject_gp(&svm->vcpu, 0);
1794
1795 return NULL;
1796 }
1797
1798 static void nested_svm_unmap(struct page *page)
1799 {
1800 kunmap(page);
1801 kvm_release_page_dirty(page);
1802 }
1803
1804 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1805 {
1806 unsigned port;
1807 u8 val, bit;
1808 u64 gpa;
1809
1810 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1811 return NESTED_EXIT_HOST;
1812
1813 port = svm->vmcb->control.exit_info_1 >> 16;
1814 gpa = svm->nested.vmcb_iopm + (port / 8);
1815 bit = port % 8;
1816 val = 0;
1817
1818 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1819 val &= (1 << bit);
1820
1821 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1822 }
1823
1824 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1825 {
1826 u32 offset, msr, value;
1827 int write, mask;
1828
1829 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1830 return NESTED_EXIT_HOST;
1831
1832 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1833 offset = svm_msrpm_offset(msr);
1834 write = svm->vmcb->control.exit_info_1 & 1;
1835 mask = 1 << ((2 * (msr & 0xf)) + write);
1836
1837 if (offset == MSR_INVALID)
1838 return NESTED_EXIT_DONE;
1839
1840 /* Offset is in 32 bit units but need in 8 bit units */
1841 offset *= 4;
1842
1843 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1844 return NESTED_EXIT_DONE;
1845
1846 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1847 }
1848
1849 static int nested_svm_exit_special(struct vcpu_svm *svm)
1850 {
1851 u32 exit_code = svm->vmcb->control.exit_code;
1852
1853 switch (exit_code) {
1854 case SVM_EXIT_INTR:
1855 case SVM_EXIT_NMI:
1856 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1857 return NESTED_EXIT_HOST;
1858 case SVM_EXIT_NPF:
1859 /* For now we are always handling NPFs when using them */
1860 if (npt_enabled)
1861 return NESTED_EXIT_HOST;
1862 break;
1863 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1864 /* When we're shadowing, trap PFs, but not async PF */
1865 if (!npt_enabled && svm->apf_reason == 0)
1866 return NESTED_EXIT_HOST;
1867 break;
1868 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1869 nm_interception(svm);
1870 break;
1871 default:
1872 break;
1873 }
1874
1875 return NESTED_EXIT_CONTINUE;
1876 }
1877
1878 /*
1879 * If this function returns true, this #vmexit was already handled
1880 */
1881 static int nested_svm_intercept(struct vcpu_svm *svm)
1882 {
1883 u32 exit_code = svm->vmcb->control.exit_code;
1884 int vmexit = NESTED_EXIT_HOST;
1885
1886 switch (exit_code) {
1887 case SVM_EXIT_MSR:
1888 vmexit = nested_svm_exit_handled_msr(svm);
1889 break;
1890 case SVM_EXIT_IOIO:
1891 vmexit = nested_svm_intercept_ioio(svm);
1892 break;
1893 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1894 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1895 if (svm->nested.intercept_cr_read & cr_bits)
1896 vmexit = NESTED_EXIT_DONE;
1897 break;
1898 }
1899 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1900 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1901 if (svm->nested.intercept_cr_write & cr_bits)
1902 vmexit = NESTED_EXIT_DONE;
1903 break;
1904 }
1905 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1906 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1907 if (svm->nested.intercept_dr_read & dr_bits)
1908 vmexit = NESTED_EXIT_DONE;
1909 break;
1910 }
1911 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1912 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1913 if (svm->nested.intercept_dr_write & dr_bits)
1914 vmexit = NESTED_EXIT_DONE;
1915 break;
1916 }
1917 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1918 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1919 if (svm->nested.intercept_exceptions & excp_bits)
1920 vmexit = NESTED_EXIT_DONE;
1921 /* async page fault always cause vmexit */
1922 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1923 svm->apf_reason != 0)
1924 vmexit = NESTED_EXIT_DONE;
1925 break;
1926 }
1927 case SVM_EXIT_ERR: {
1928 vmexit = NESTED_EXIT_DONE;
1929 break;
1930 }
1931 default: {
1932 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1933 if (svm->nested.intercept & exit_bits)
1934 vmexit = NESTED_EXIT_DONE;
1935 }
1936 }
1937
1938 return vmexit;
1939 }
1940
1941 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1942 {
1943 int vmexit;
1944
1945 vmexit = nested_svm_intercept(svm);
1946
1947 if (vmexit == NESTED_EXIT_DONE)
1948 nested_svm_vmexit(svm);
1949
1950 return vmexit;
1951 }
1952
1953 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1954 {
1955 struct vmcb_control_area *dst = &dst_vmcb->control;
1956 struct vmcb_control_area *from = &from_vmcb->control;
1957
1958 dst->intercept_cr_read = from->intercept_cr_read;
1959 dst->intercept_cr_write = from->intercept_cr_write;
1960 dst->intercept_dr_read = from->intercept_dr_read;
1961 dst->intercept_dr_write = from->intercept_dr_write;
1962 dst->intercept_exceptions = from->intercept_exceptions;
1963 dst->intercept = from->intercept;
1964 dst->iopm_base_pa = from->iopm_base_pa;
1965 dst->msrpm_base_pa = from->msrpm_base_pa;
1966 dst->tsc_offset = from->tsc_offset;
1967 dst->asid = from->asid;
1968 dst->tlb_ctl = from->tlb_ctl;
1969 dst->int_ctl = from->int_ctl;
1970 dst->int_vector = from->int_vector;
1971 dst->int_state = from->int_state;
1972 dst->exit_code = from->exit_code;
1973 dst->exit_code_hi = from->exit_code_hi;
1974 dst->exit_info_1 = from->exit_info_1;
1975 dst->exit_info_2 = from->exit_info_2;
1976 dst->exit_int_info = from->exit_int_info;
1977 dst->exit_int_info_err = from->exit_int_info_err;
1978 dst->nested_ctl = from->nested_ctl;
1979 dst->event_inj = from->event_inj;
1980 dst->event_inj_err = from->event_inj_err;
1981 dst->nested_cr3 = from->nested_cr3;
1982 dst->lbr_ctl = from->lbr_ctl;
1983 }
1984
1985 static int nested_svm_vmexit(struct vcpu_svm *svm)
1986 {
1987 struct vmcb *nested_vmcb;
1988 struct vmcb *hsave = svm->nested.hsave;
1989 struct vmcb *vmcb = svm->vmcb;
1990 struct page *page;
1991
1992 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1993 vmcb->control.exit_info_1,
1994 vmcb->control.exit_info_2,
1995 vmcb->control.exit_int_info,
1996 vmcb->control.exit_int_info_err);
1997
1998 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1999 if (!nested_vmcb)
2000 return 1;
2001
2002 /* Exit nested SVM mode */
2003 svm->nested.vmcb = 0;
2004
2005 /* Give the current vmcb to the guest */
2006 disable_gif(svm);
2007
2008 nested_vmcb->save.es = vmcb->save.es;
2009 nested_vmcb->save.cs = vmcb->save.cs;
2010 nested_vmcb->save.ss = vmcb->save.ss;
2011 nested_vmcb->save.ds = vmcb->save.ds;
2012 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2013 nested_vmcb->save.idtr = vmcb->save.idtr;
2014 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2015 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2016 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2017 nested_vmcb->save.cr2 = vmcb->save.cr2;
2018 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2019 nested_vmcb->save.rflags = vmcb->save.rflags;
2020 nested_vmcb->save.rip = vmcb->save.rip;
2021 nested_vmcb->save.rsp = vmcb->save.rsp;
2022 nested_vmcb->save.rax = vmcb->save.rax;
2023 nested_vmcb->save.dr7 = vmcb->save.dr7;
2024 nested_vmcb->save.dr6 = vmcb->save.dr6;
2025 nested_vmcb->save.cpl = vmcb->save.cpl;
2026
2027 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2028 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2029 nested_vmcb->control.int_state = vmcb->control.int_state;
2030 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2031 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2032 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2033 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2034 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2035 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2036 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2037
2038 /*
2039 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2040 * to make sure that we do not lose injected events. So check event_inj
2041 * here and copy it to exit_int_info if it is valid.
2042 * Exit_int_info and event_inj can't be both valid because the case
2043 * below only happens on a VMRUN instruction intercept which has
2044 * no valid exit_int_info set.
2045 */
2046 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2047 struct vmcb_control_area *nc = &nested_vmcb->control;
2048
2049 nc->exit_int_info = vmcb->control.event_inj;
2050 nc->exit_int_info_err = vmcb->control.event_inj_err;
2051 }
2052
2053 nested_vmcb->control.tlb_ctl = 0;
2054 nested_vmcb->control.event_inj = 0;
2055 nested_vmcb->control.event_inj_err = 0;
2056
2057 /* We always set V_INTR_MASKING and remember the old value in hflags */
2058 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2059 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2060
2061 /* Restore the original control entries */
2062 copy_vmcb_control_area(vmcb, hsave);
2063
2064 kvm_clear_exception_queue(&svm->vcpu);
2065 kvm_clear_interrupt_queue(&svm->vcpu);
2066
2067 svm->nested.nested_cr3 = 0;
2068
2069 /* Restore selected save entries */
2070 svm->vmcb->save.es = hsave->save.es;
2071 svm->vmcb->save.cs = hsave->save.cs;
2072 svm->vmcb->save.ss = hsave->save.ss;
2073 svm->vmcb->save.ds = hsave->save.ds;
2074 svm->vmcb->save.gdtr = hsave->save.gdtr;
2075 svm->vmcb->save.idtr = hsave->save.idtr;
2076 svm->vmcb->save.rflags = hsave->save.rflags;
2077 svm_set_efer(&svm->vcpu, hsave->save.efer);
2078 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2079 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2080 if (npt_enabled) {
2081 svm->vmcb->save.cr3 = hsave->save.cr3;
2082 svm->vcpu.arch.cr3 = hsave->save.cr3;
2083 } else {
2084 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2085 }
2086 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2087 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2088 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2089 svm->vmcb->save.dr7 = 0;
2090 svm->vmcb->save.cpl = 0;
2091 svm->vmcb->control.exit_int_info = 0;
2092
2093 nested_svm_unmap(page);
2094
2095 nested_svm_uninit_mmu_context(&svm->vcpu);
2096 kvm_mmu_reset_context(&svm->vcpu);
2097 kvm_mmu_load(&svm->vcpu);
2098
2099 return 0;
2100 }
2101
2102 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2103 {
2104 /*
2105 * This function merges the msr permission bitmaps of kvm and the
2106 * nested vmcb. It is omptimized in that it only merges the parts where
2107 * the kvm msr permission bitmap may contain zero bits
2108 */
2109 int i;
2110
2111 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2112 return true;
2113
2114 for (i = 0; i < MSRPM_OFFSETS; i++) {
2115 u32 value, p;
2116 u64 offset;
2117
2118 if (msrpm_offsets[i] == 0xffffffff)
2119 break;
2120
2121 p = msrpm_offsets[i];
2122 offset = svm->nested.vmcb_msrpm + (p * 4);
2123
2124 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2125 return false;
2126
2127 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2128 }
2129
2130 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2131
2132 return true;
2133 }
2134
2135 static bool nested_vmcb_checks(struct vmcb *vmcb)
2136 {
2137 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2138 return false;
2139
2140 if (vmcb->control.asid == 0)
2141 return false;
2142
2143 if (vmcb->control.nested_ctl && !npt_enabled)
2144 return false;
2145
2146 return true;
2147 }
2148
2149 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2150 {
2151 struct vmcb *nested_vmcb;
2152 struct vmcb *hsave = svm->nested.hsave;
2153 struct vmcb *vmcb = svm->vmcb;
2154 struct page *page;
2155 u64 vmcb_gpa;
2156
2157 vmcb_gpa = svm->vmcb->save.rax;
2158
2159 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2160 if (!nested_vmcb)
2161 return false;
2162
2163 if (!nested_vmcb_checks(nested_vmcb)) {
2164 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2165 nested_vmcb->control.exit_code_hi = 0;
2166 nested_vmcb->control.exit_info_1 = 0;
2167 nested_vmcb->control.exit_info_2 = 0;
2168
2169 nested_svm_unmap(page);
2170
2171 return false;
2172 }
2173
2174 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2175 nested_vmcb->save.rip,
2176 nested_vmcb->control.int_ctl,
2177 nested_vmcb->control.event_inj,
2178 nested_vmcb->control.nested_ctl);
2179
2180 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2181 nested_vmcb->control.intercept_cr_write,
2182 nested_vmcb->control.intercept_exceptions,
2183 nested_vmcb->control.intercept);
2184
2185 /* Clear internal status */
2186 kvm_clear_exception_queue(&svm->vcpu);
2187 kvm_clear_interrupt_queue(&svm->vcpu);
2188
2189 /*
2190 * Save the old vmcb, so we don't need to pick what we save, but can
2191 * restore everything when a VMEXIT occurs
2192 */
2193 hsave->save.es = vmcb->save.es;
2194 hsave->save.cs = vmcb->save.cs;
2195 hsave->save.ss = vmcb->save.ss;
2196 hsave->save.ds = vmcb->save.ds;
2197 hsave->save.gdtr = vmcb->save.gdtr;
2198 hsave->save.idtr = vmcb->save.idtr;
2199 hsave->save.efer = svm->vcpu.arch.efer;
2200 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2201 hsave->save.cr4 = svm->vcpu.arch.cr4;
2202 hsave->save.rflags = vmcb->save.rflags;
2203 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2204 hsave->save.rsp = vmcb->save.rsp;
2205 hsave->save.rax = vmcb->save.rax;
2206 if (npt_enabled)
2207 hsave->save.cr3 = vmcb->save.cr3;
2208 else
2209 hsave->save.cr3 = svm->vcpu.arch.cr3;
2210
2211 copy_vmcb_control_area(hsave, vmcb);
2212
2213 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2214 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2215 else
2216 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2217
2218 if (nested_vmcb->control.nested_ctl) {
2219 kvm_mmu_unload(&svm->vcpu);
2220 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2221 nested_svm_init_mmu_context(&svm->vcpu);
2222 }
2223
2224 /* Load the nested guest state */
2225 svm->vmcb->save.es = nested_vmcb->save.es;
2226 svm->vmcb->save.cs = nested_vmcb->save.cs;
2227 svm->vmcb->save.ss = nested_vmcb->save.ss;
2228 svm->vmcb->save.ds = nested_vmcb->save.ds;
2229 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2230 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2231 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2232 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2233 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2234 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2235 if (npt_enabled) {
2236 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2237 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2238 } else
2239 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2240
2241 /* Guest paging mode is active - reset mmu */
2242 kvm_mmu_reset_context(&svm->vcpu);
2243
2244 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2245 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2246 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2247 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2248
2249 /* In case we don't even reach vcpu_run, the fields are not updated */
2250 svm->vmcb->save.rax = nested_vmcb->save.rax;
2251 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2252 svm->vmcb->save.rip = nested_vmcb->save.rip;
2253 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2254 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2255 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2256
2257 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2258 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2259
2260 /* cache intercepts */
2261 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2262 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2263 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2264 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2265 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2266 svm->nested.intercept = nested_vmcb->control.intercept;
2267
2268 force_new_asid(&svm->vcpu);
2269 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2270 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2271 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2272 else
2273 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2274
2275 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2276 /* We only want the cr8 intercept bits of the guest */
2277 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2278 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2279 }
2280
2281 /* We don't want to see VMMCALLs from a nested guest */
2282 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2283
2284 /*
2285 * We don't want a nested guest to be more powerful than the guest, so
2286 * all intercepts are ORed
2287 */
2288 svm->vmcb->control.intercept_cr_read |=
2289 nested_vmcb->control.intercept_cr_read;
2290 svm->vmcb->control.intercept_cr_write |=
2291 nested_vmcb->control.intercept_cr_write;
2292 svm->vmcb->control.intercept_dr_read |=
2293 nested_vmcb->control.intercept_dr_read;
2294 svm->vmcb->control.intercept_dr_write |=
2295 nested_vmcb->control.intercept_dr_write;
2296 svm->vmcb->control.intercept_exceptions |=
2297 nested_vmcb->control.intercept_exceptions;
2298
2299 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2300
2301 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2302 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2303 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2304 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2305 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2306 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2307
2308 nested_svm_unmap(page);
2309
2310 /* nested_vmcb is our indicator if nested SVM is activated */
2311 svm->nested.vmcb = vmcb_gpa;
2312
2313 enable_gif(svm);
2314
2315 return true;
2316 }
2317
2318 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2319 {
2320 to_vmcb->save.fs = from_vmcb->save.fs;
2321 to_vmcb->save.gs = from_vmcb->save.gs;
2322 to_vmcb->save.tr = from_vmcb->save.tr;
2323 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2324 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2325 to_vmcb->save.star = from_vmcb->save.star;
2326 to_vmcb->save.lstar = from_vmcb->save.lstar;
2327 to_vmcb->save.cstar = from_vmcb->save.cstar;
2328 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2329 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2330 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2331 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2332 }
2333
2334 static int vmload_interception(struct vcpu_svm *svm)
2335 {
2336 struct vmcb *nested_vmcb;
2337 struct page *page;
2338
2339 if (nested_svm_check_permissions(svm))
2340 return 1;
2341
2342 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2343 skip_emulated_instruction(&svm->vcpu);
2344
2345 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2346 if (!nested_vmcb)
2347 return 1;
2348
2349 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2350 nested_svm_unmap(page);
2351
2352 return 1;
2353 }
2354
2355 static int vmsave_interception(struct vcpu_svm *svm)
2356 {
2357 struct vmcb *nested_vmcb;
2358 struct page *page;
2359
2360 if (nested_svm_check_permissions(svm))
2361 return 1;
2362
2363 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2364 skip_emulated_instruction(&svm->vcpu);
2365
2366 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2367 if (!nested_vmcb)
2368 return 1;
2369
2370 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2371 nested_svm_unmap(page);
2372
2373 return 1;
2374 }
2375
2376 static int vmrun_interception(struct vcpu_svm *svm)
2377 {
2378 if (nested_svm_check_permissions(svm))
2379 return 1;
2380
2381 /* Save rip after vmrun instruction */
2382 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2383
2384 if (!nested_svm_vmrun(svm))
2385 return 1;
2386
2387 if (!nested_svm_vmrun_msrpm(svm))
2388 goto failed;
2389
2390 return 1;
2391
2392 failed:
2393
2394 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2395 svm->vmcb->control.exit_code_hi = 0;
2396 svm->vmcb->control.exit_info_1 = 0;
2397 svm->vmcb->control.exit_info_2 = 0;
2398
2399 nested_svm_vmexit(svm);
2400
2401 return 1;
2402 }
2403
2404 static int stgi_interception(struct vcpu_svm *svm)
2405 {
2406 if (nested_svm_check_permissions(svm))
2407 return 1;
2408
2409 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2410 skip_emulated_instruction(&svm->vcpu);
2411 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2412
2413 enable_gif(svm);
2414
2415 return 1;
2416 }
2417
2418 static int clgi_interception(struct vcpu_svm *svm)
2419 {
2420 if (nested_svm_check_permissions(svm))
2421 return 1;
2422
2423 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2424 skip_emulated_instruction(&svm->vcpu);
2425
2426 disable_gif(svm);
2427
2428 /* After a CLGI no interrupts should come */
2429 svm_clear_vintr(svm);
2430 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2431
2432 return 1;
2433 }
2434
2435 static int invlpga_interception(struct vcpu_svm *svm)
2436 {
2437 struct kvm_vcpu *vcpu = &svm->vcpu;
2438
2439 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2440 vcpu->arch.regs[VCPU_REGS_RAX]);
2441
2442 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2443 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2444
2445 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2446 skip_emulated_instruction(&svm->vcpu);
2447 return 1;
2448 }
2449
2450 static int skinit_interception(struct vcpu_svm *svm)
2451 {
2452 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2453
2454 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2455 return 1;
2456 }
2457
2458 static int invalid_op_interception(struct vcpu_svm *svm)
2459 {
2460 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2461 return 1;
2462 }
2463
2464 static int task_switch_interception(struct vcpu_svm *svm)
2465 {
2466 u16 tss_selector;
2467 int reason;
2468 int int_type = svm->vmcb->control.exit_int_info &
2469 SVM_EXITINTINFO_TYPE_MASK;
2470 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2471 uint32_t type =
2472 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2473 uint32_t idt_v =
2474 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2475 bool has_error_code = false;
2476 u32 error_code = 0;
2477
2478 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2479
2480 if (svm->vmcb->control.exit_info_2 &
2481 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2482 reason = TASK_SWITCH_IRET;
2483 else if (svm->vmcb->control.exit_info_2 &
2484 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2485 reason = TASK_SWITCH_JMP;
2486 else if (idt_v)
2487 reason = TASK_SWITCH_GATE;
2488 else
2489 reason = TASK_SWITCH_CALL;
2490
2491 if (reason == TASK_SWITCH_GATE) {
2492 switch (type) {
2493 case SVM_EXITINTINFO_TYPE_NMI:
2494 svm->vcpu.arch.nmi_injected = false;
2495 break;
2496 case SVM_EXITINTINFO_TYPE_EXEPT:
2497 if (svm->vmcb->control.exit_info_2 &
2498 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2499 has_error_code = true;
2500 error_code =
2501 (u32)svm->vmcb->control.exit_info_2;
2502 }
2503 kvm_clear_exception_queue(&svm->vcpu);
2504 break;
2505 case SVM_EXITINTINFO_TYPE_INTR:
2506 kvm_clear_interrupt_queue(&svm->vcpu);
2507 break;
2508 default:
2509 break;
2510 }
2511 }
2512
2513 if (reason != TASK_SWITCH_GATE ||
2514 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2515 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2516 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2517 skip_emulated_instruction(&svm->vcpu);
2518
2519 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2520 has_error_code, error_code) == EMULATE_FAIL) {
2521 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2522 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2523 svm->vcpu.run->internal.ndata = 0;
2524 return 0;
2525 }
2526 return 1;
2527 }
2528
2529 static int cpuid_interception(struct vcpu_svm *svm)
2530 {
2531 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2532 kvm_emulate_cpuid(&svm->vcpu);
2533 return 1;
2534 }
2535
2536 static int iret_interception(struct vcpu_svm *svm)
2537 {
2538 ++svm->vcpu.stat.nmi_window_exits;
2539 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2540 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2541 return 1;
2542 }
2543
2544 static int invlpg_interception(struct vcpu_svm *svm)
2545 {
2546 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2547 }
2548
2549 static int emulate_on_interception(struct vcpu_svm *svm)
2550 {
2551 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2552 }
2553
2554 static int cr0_write_interception(struct vcpu_svm *svm)
2555 {
2556 struct kvm_vcpu *vcpu = &svm->vcpu;
2557 int r;
2558
2559 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2560
2561 if (svm->nested.vmexit_rip) {
2562 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2563 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2564 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2565 svm->nested.vmexit_rip = 0;
2566 }
2567
2568 return r == EMULATE_DONE;
2569 }
2570
2571 static int cr8_write_interception(struct vcpu_svm *svm)
2572 {
2573 struct kvm_run *kvm_run = svm->vcpu.run;
2574
2575 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2576 /* instruction emulation calls kvm_set_cr8() */
2577 emulate_instruction(&svm->vcpu, 0, 0, 0);
2578 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2579 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2580 return 1;
2581 }
2582 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2583 return 1;
2584 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2585 return 0;
2586 }
2587
2588 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2589 {
2590 struct vcpu_svm *svm = to_svm(vcpu);
2591
2592 switch (ecx) {
2593 case MSR_IA32_TSC: {
2594 u64 tsc_offset;
2595
2596 if (is_nested(svm))
2597 tsc_offset = svm->nested.hsave->control.tsc_offset;
2598 else
2599 tsc_offset = svm->vmcb->control.tsc_offset;
2600
2601 *data = tsc_offset + native_read_tsc();
2602 break;
2603 }
2604 case MSR_STAR:
2605 *data = svm->vmcb->save.star;
2606 break;
2607 #ifdef CONFIG_X86_64
2608 case MSR_LSTAR:
2609 *data = svm->vmcb->save.lstar;
2610 break;
2611 case MSR_CSTAR:
2612 *data = svm->vmcb->save.cstar;
2613 break;
2614 case MSR_KERNEL_GS_BASE:
2615 *data = svm->vmcb->save.kernel_gs_base;
2616 break;
2617 case MSR_SYSCALL_MASK:
2618 *data = svm->vmcb->save.sfmask;
2619 break;
2620 #endif
2621 case MSR_IA32_SYSENTER_CS:
2622 *data = svm->vmcb->save.sysenter_cs;
2623 break;
2624 case MSR_IA32_SYSENTER_EIP:
2625 *data = svm->sysenter_eip;
2626 break;
2627 case MSR_IA32_SYSENTER_ESP:
2628 *data = svm->sysenter_esp;
2629 break;
2630 /*
2631 * Nobody will change the following 5 values in the VMCB so we can
2632 * safely return them on rdmsr. They will always be 0 until LBRV is
2633 * implemented.
2634 */
2635 case MSR_IA32_DEBUGCTLMSR:
2636 *data = svm->vmcb->save.dbgctl;
2637 break;
2638 case MSR_IA32_LASTBRANCHFROMIP:
2639 *data = svm->vmcb->save.br_from;
2640 break;
2641 case MSR_IA32_LASTBRANCHTOIP:
2642 *data = svm->vmcb->save.br_to;
2643 break;
2644 case MSR_IA32_LASTINTFROMIP:
2645 *data = svm->vmcb->save.last_excp_from;
2646 break;
2647 case MSR_IA32_LASTINTTOIP:
2648 *data = svm->vmcb->save.last_excp_to;
2649 break;
2650 case MSR_VM_HSAVE_PA:
2651 *data = svm->nested.hsave_msr;
2652 break;
2653 case MSR_VM_CR:
2654 *data = svm->nested.vm_cr_msr;
2655 break;
2656 case MSR_IA32_UCODE_REV:
2657 *data = 0x01000065;
2658 break;
2659 default:
2660 return kvm_get_msr_common(vcpu, ecx, data);
2661 }
2662 return 0;
2663 }
2664
2665 static int rdmsr_interception(struct vcpu_svm *svm)
2666 {
2667 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2668 u64 data;
2669
2670 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2671 trace_kvm_msr_read_ex(ecx);
2672 kvm_inject_gp(&svm->vcpu, 0);
2673 } else {
2674 trace_kvm_msr_read(ecx, data);
2675
2676 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2677 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2678 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2679 skip_emulated_instruction(&svm->vcpu);
2680 }
2681 return 1;
2682 }
2683
2684 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2685 {
2686 struct vcpu_svm *svm = to_svm(vcpu);
2687 int svm_dis, chg_mask;
2688
2689 if (data & ~SVM_VM_CR_VALID_MASK)
2690 return 1;
2691
2692 chg_mask = SVM_VM_CR_VALID_MASK;
2693
2694 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2695 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2696
2697 svm->nested.vm_cr_msr &= ~chg_mask;
2698 svm->nested.vm_cr_msr |= (data & chg_mask);
2699
2700 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2701
2702 /* check for svm_disable while efer.svme is set */
2703 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2704 return 1;
2705
2706 return 0;
2707 }
2708
2709 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2710 {
2711 struct vcpu_svm *svm = to_svm(vcpu);
2712
2713 switch (ecx) {
2714 case MSR_IA32_TSC:
2715 kvm_write_tsc(vcpu, data);
2716 break;
2717 case MSR_STAR:
2718 svm->vmcb->save.star = data;
2719 break;
2720 #ifdef CONFIG_X86_64
2721 case MSR_LSTAR:
2722 svm->vmcb->save.lstar = data;
2723 break;
2724 case MSR_CSTAR:
2725 svm->vmcb->save.cstar = data;
2726 break;
2727 case MSR_KERNEL_GS_BASE:
2728 svm->vmcb->save.kernel_gs_base = data;
2729 break;
2730 case MSR_SYSCALL_MASK:
2731 svm->vmcb->save.sfmask = data;
2732 break;
2733 #endif
2734 case MSR_IA32_SYSENTER_CS:
2735 svm->vmcb->save.sysenter_cs = data;
2736 break;
2737 case MSR_IA32_SYSENTER_EIP:
2738 svm->sysenter_eip = data;
2739 svm->vmcb->save.sysenter_eip = data;
2740 break;
2741 case MSR_IA32_SYSENTER_ESP:
2742 svm->sysenter_esp = data;
2743 svm->vmcb->save.sysenter_esp = data;
2744 break;
2745 case MSR_IA32_DEBUGCTLMSR:
2746 if (!svm_has(SVM_FEATURE_LBRV)) {
2747 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2748 __func__, data);
2749 break;
2750 }
2751 if (data & DEBUGCTL_RESERVED_BITS)
2752 return 1;
2753
2754 svm->vmcb->save.dbgctl = data;
2755 if (data & (1ULL<<0))
2756 svm_enable_lbrv(svm);
2757 else
2758 svm_disable_lbrv(svm);
2759 break;
2760 case MSR_VM_HSAVE_PA:
2761 svm->nested.hsave_msr = data;
2762 break;
2763 case MSR_VM_CR:
2764 return svm_set_vm_cr(vcpu, data);
2765 case MSR_VM_IGNNE:
2766 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2767 break;
2768 default:
2769 return kvm_set_msr_common(vcpu, ecx, data);
2770 }
2771 return 0;
2772 }
2773
2774 static int wrmsr_interception(struct vcpu_svm *svm)
2775 {
2776 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2777 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2778 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2779
2780
2781 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2782 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2783 trace_kvm_msr_write_ex(ecx, data);
2784 kvm_inject_gp(&svm->vcpu, 0);
2785 } else {
2786 trace_kvm_msr_write(ecx, data);
2787 skip_emulated_instruction(&svm->vcpu);
2788 }
2789 return 1;
2790 }
2791
2792 static int msr_interception(struct vcpu_svm *svm)
2793 {
2794 if (svm->vmcb->control.exit_info_1)
2795 return wrmsr_interception(svm);
2796 else
2797 return rdmsr_interception(svm);
2798 }
2799
2800 static int interrupt_window_interception(struct vcpu_svm *svm)
2801 {
2802 struct kvm_run *kvm_run = svm->vcpu.run;
2803
2804 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2805 svm_clear_vintr(svm);
2806 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2807 /*
2808 * If the user space waits to inject interrupts, exit as soon as
2809 * possible
2810 */
2811 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2812 kvm_run->request_interrupt_window &&
2813 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2814 ++svm->vcpu.stat.irq_window_exits;
2815 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2816 return 0;
2817 }
2818
2819 return 1;
2820 }
2821
2822 static int pause_interception(struct vcpu_svm *svm)
2823 {
2824 kvm_vcpu_on_spin(&(svm->vcpu));
2825 return 1;
2826 }
2827
2828 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2829 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2830 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2831 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2832 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2833 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2834 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2835 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2836 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2837 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2838 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2839 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2840 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2841 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2842 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2843 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2844 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2845 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2846 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2847 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2848 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2849 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2850 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2851 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2852 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2853 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2854 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2855 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2856 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2857 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2858 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2859 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2860 [SVM_EXIT_INTR] = intr_interception,
2861 [SVM_EXIT_NMI] = nmi_interception,
2862 [SVM_EXIT_SMI] = nop_on_interception,
2863 [SVM_EXIT_INIT] = nop_on_interception,
2864 [SVM_EXIT_VINTR] = interrupt_window_interception,
2865 [SVM_EXIT_CPUID] = cpuid_interception,
2866 [SVM_EXIT_IRET] = iret_interception,
2867 [SVM_EXIT_INVD] = emulate_on_interception,
2868 [SVM_EXIT_PAUSE] = pause_interception,
2869 [SVM_EXIT_HLT] = halt_interception,
2870 [SVM_EXIT_INVLPG] = invlpg_interception,
2871 [SVM_EXIT_INVLPGA] = invlpga_interception,
2872 [SVM_EXIT_IOIO] = io_interception,
2873 [SVM_EXIT_MSR] = msr_interception,
2874 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2875 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2876 [SVM_EXIT_VMRUN] = vmrun_interception,
2877 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2878 [SVM_EXIT_VMLOAD] = vmload_interception,
2879 [SVM_EXIT_VMSAVE] = vmsave_interception,
2880 [SVM_EXIT_STGI] = stgi_interception,
2881 [SVM_EXIT_CLGI] = clgi_interception,
2882 [SVM_EXIT_SKINIT] = skinit_interception,
2883 [SVM_EXIT_WBINVD] = emulate_on_interception,
2884 [SVM_EXIT_MONITOR] = invalid_op_interception,
2885 [SVM_EXIT_MWAIT] = invalid_op_interception,
2886 [SVM_EXIT_NPF] = pf_interception,
2887 };
2888
2889 void dump_vmcb(struct kvm_vcpu *vcpu)
2890 {
2891 struct vcpu_svm *svm = to_svm(vcpu);
2892 struct vmcb_control_area *control = &svm->vmcb->control;
2893 struct vmcb_save_area *save = &svm->vmcb->save;
2894
2895 pr_err("VMCB Control Area:\n");
2896 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2897 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2898 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2899 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2900 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2901 pr_err("intercepts: %016llx\n", control->intercept);
2902 pr_err("pause filter count: %d\n", control->pause_filter_count);
2903 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2904 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2905 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2906 pr_err("asid: %d\n", control->asid);
2907 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2908 pr_err("int_ctl: %08x\n", control->int_ctl);
2909 pr_err("int_vector: %08x\n", control->int_vector);
2910 pr_err("int_state: %08x\n", control->int_state);
2911 pr_err("exit_code: %08x\n", control->exit_code);
2912 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2913 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2914 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2915 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2916 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2917 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2918 pr_err("event_inj: %08x\n", control->event_inj);
2919 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2920 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2921 pr_err("next_rip: %016llx\n", control->next_rip);
2922 pr_err("VMCB State Save Area:\n");
2923 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2924 save->es.selector, save->es.attrib,
2925 save->es.limit, save->es.base);
2926 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2927 save->cs.selector, save->cs.attrib,
2928 save->cs.limit, save->cs.base);
2929 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2930 save->ss.selector, save->ss.attrib,
2931 save->ss.limit, save->ss.base);
2932 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2933 save->ds.selector, save->ds.attrib,
2934 save->ds.limit, save->ds.base);
2935 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2936 save->fs.selector, save->fs.attrib,
2937 save->fs.limit, save->fs.base);
2938 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2939 save->gs.selector, save->gs.attrib,
2940 save->gs.limit, save->gs.base);
2941 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2942 save->gdtr.selector, save->gdtr.attrib,
2943 save->gdtr.limit, save->gdtr.base);
2944 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->ldtr.selector, save->ldtr.attrib,
2946 save->ldtr.limit, save->ldtr.base);
2947 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2948 save->idtr.selector, save->idtr.attrib,
2949 save->idtr.limit, save->idtr.base);
2950 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2951 save->tr.selector, save->tr.attrib,
2952 save->tr.limit, save->tr.base);
2953 pr_err("cpl: %d efer: %016llx\n",
2954 save->cpl, save->efer);
2955 pr_err("cr0: %016llx cr2: %016llx\n",
2956 save->cr0, save->cr2);
2957 pr_err("cr3: %016llx cr4: %016llx\n",
2958 save->cr3, save->cr4);
2959 pr_err("dr6: %016llx dr7: %016llx\n",
2960 save->dr6, save->dr7);
2961 pr_err("rip: %016llx rflags: %016llx\n",
2962 save->rip, save->rflags);
2963 pr_err("rsp: %016llx rax: %016llx\n",
2964 save->rsp, save->rax);
2965 pr_err("star: %016llx lstar: %016llx\n",
2966 save->star, save->lstar);
2967 pr_err("cstar: %016llx sfmask: %016llx\n",
2968 save->cstar, save->sfmask);
2969 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2970 save->kernel_gs_base, save->sysenter_cs);
2971 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2972 save->sysenter_esp, save->sysenter_eip);
2973 pr_err("gpat: %016llx dbgctl: %016llx\n",
2974 save->g_pat, save->dbgctl);
2975 pr_err("br_from: %016llx br_to: %016llx\n",
2976 save->br_from, save->br_to);
2977 pr_err("excp_from: %016llx excp_to: %016llx\n",
2978 save->last_excp_from, save->last_excp_to);
2979
2980 }
2981
2982 static int handle_exit(struct kvm_vcpu *vcpu)
2983 {
2984 struct vcpu_svm *svm = to_svm(vcpu);
2985 struct kvm_run *kvm_run = vcpu->run;
2986 u32 exit_code = svm->vmcb->control.exit_code;
2987
2988 trace_kvm_exit(exit_code, vcpu);
2989
2990 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2991 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2992 if (npt_enabled)
2993 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2994
2995 if (unlikely(svm->nested.exit_required)) {
2996 nested_svm_vmexit(svm);
2997 svm->nested.exit_required = false;
2998
2999 return 1;
3000 }
3001
3002 if (is_nested(svm)) {
3003 int vmexit;
3004
3005 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3006 svm->vmcb->control.exit_info_1,
3007 svm->vmcb->control.exit_info_2,
3008 svm->vmcb->control.exit_int_info,
3009 svm->vmcb->control.exit_int_info_err);
3010
3011 vmexit = nested_svm_exit_special(svm);
3012
3013 if (vmexit == NESTED_EXIT_CONTINUE)
3014 vmexit = nested_svm_exit_handled(svm);
3015
3016 if (vmexit == NESTED_EXIT_DONE)
3017 return 1;
3018 }
3019
3020 svm_complete_interrupts(svm);
3021
3022 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3023 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3024 kvm_run->fail_entry.hardware_entry_failure_reason
3025 = svm->vmcb->control.exit_code;
3026 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3027 dump_vmcb(vcpu);
3028 return 0;
3029 }
3030
3031 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3032 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3033 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3034 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3035 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3036 "exit_code 0x%x\n",
3037 __func__, svm->vmcb->control.exit_int_info,
3038 exit_code);
3039
3040 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3041 || !svm_exit_handlers[exit_code]) {
3042 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3043 kvm_run->hw.hardware_exit_reason = exit_code;
3044 return 0;
3045 }
3046
3047 return svm_exit_handlers[exit_code](svm);
3048 }
3049
3050 static void reload_tss(struct kvm_vcpu *vcpu)
3051 {
3052 int cpu = raw_smp_processor_id();
3053
3054 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3055 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3056 load_TR_desc();
3057 }
3058
3059 static void pre_svm_run(struct vcpu_svm *svm)
3060 {
3061 int cpu = raw_smp_processor_id();
3062
3063 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3064
3065 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3066 /* FIXME: handle wraparound of asid_generation */
3067 if (svm->asid_generation != sd->asid_generation)
3068 new_asid(svm, sd);
3069 }
3070
3071 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3072 {
3073 struct vcpu_svm *svm = to_svm(vcpu);
3074
3075 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3076 vcpu->arch.hflags |= HF_NMI_MASK;
3077 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3078 ++vcpu->stat.nmi_injections;
3079 }
3080
3081 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3082 {
3083 struct vmcb_control_area *control;
3084
3085 control = &svm->vmcb->control;
3086 control->int_vector = irq;
3087 control->int_ctl &= ~V_INTR_PRIO_MASK;
3088 control->int_ctl |= V_IRQ_MASK |
3089 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3090 }
3091
3092 static void svm_set_irq(struct kvm_vcpu *vcpu)
3093 {
3094 struct vcpu_svm *svm = to_svm(vcpu);
3095
3096 BUG_ON(!(gif_set(svm)));
3097
3098 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3099 ++vcpu->stat.irq_injections;
3100
3101 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3102 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3103 }
3104
3105 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3106 {
3107 struct vcpu_svm *svm = to_svm(vcpu);
3108
3109 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3110 return;
3111
3112 if (irr == -1)
3113 return;
3114
3115 if (tpr >= irr)
3116 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3117 }
3118
3119 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3120 {
3121 struct vcpu_svm *svm = to_svm(vcpu);
3122 struct vmcb *vmcb = svm->vmcb;
3123 int ret;
3124 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3125 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3126 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3127
3128 return ret;
3129 }
3130
3131 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3132 {
3133 struct vcpu_svm *svm = to_svm(vcpu);
3134
3135 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3136 }
3137
3138 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3139 {
3140 struct vcpu_svm *svm = to_svm(vcpu);
3141
3142 if (masked) {
3143 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3144 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3145 } else {
3146 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3147 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3148 }
3149 }
3150
3151 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3152 {
3153 struct vcpu_svm *svm = to_svm(vcpu);
3154 struct vmcb *vmcb = svm->vmcb;
3155 int ret;
3156
3157 if (!gif_set(svm) ||
3158 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3159 return 0;
3160
3161 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3162
3163 if (is_nested(svm))
3164 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3165
3166 return ret;
3167 }
3168
3169 static void enable_irq_window(struct kvm_vcpu *vcpu)
3170 {
3171 struct vcpu_svm *svm = to_svm(vcpu);
3172
3173 /*
3174 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3175 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3176 * get that intercept, this function will be called again though and
3177 * we'll get the vintr intercept.
3178 */
3179 if (gif_set(svm) && nested_svm_intr(svm)) {
3180 svm_set_vintr(svm);
3181 svm_inject_irq(svm, 0x0);
3182 }
3183 }
3184
3185 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3186 {
3187 struct vcpu_svm *svm = to_svm(vcpu);
3188
3189 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3190 == HF_NMI_MASK)
3191 return; /* IRET will cause a vm exit */
3192
3193 /*
3194 * Something prevents NMI from been injected. Single step over possible
3195 * problem (IRET or exception injection or interrupt shadow)
3196 */
3197 svm->nmi_singlestep = true;
3198 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3199 update_db_intercept(vcpu);
3200 }
3201
3202 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3203 {
3204 return 0;
3205 }
3206
3207 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3208 {
3209 force_new_asid(vcpu);
3210 }
3211
3212 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3213 {
3214 }
3215
3216 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3217 {
3218 struct vcpu_svm *svm = to_svm(vcpu);
3219
3220 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3221 return;
3222
3223 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3224 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3225 kvm_set_cr8(vcpu, cr8);
3226 }
3227 }
3228
3229 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3230 {
3231 struct vcpu_svm *svm = to_svm(vcpu);
3232 u64 cr8;
3233
3234 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3235 return;
3236
3237 cr8 = kvm_get_cr8(vcpu);
3238 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3239 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3240 }
3241
3242 static void svm_complete_interrupts(struct vcpu_svm *svm)
3243 {
3244 u8 vector;
3245 int type;
3246 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3247 unsigned int3_injected = svm->int3_injected;
3248
3249 svm->int3_injected = 0;
3250
3251 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3252 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3253 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3254 }
3255
3256 svm->vcpu.arch.nmi_injected = false;
3257 kvm_clear_exception_queue(&svm->vcpu);
3258 kvm_clear_interrupt_queue(&svm->vcpu);
3259
3260 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3261 return;
3262
3263 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3264
3265 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3266 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3267
3268 switch (type) {
3269 case SVM_EXITINTINFO_TYPE_NMI:
3270 svm->vcpu.arch.nmi_injected = true;
3271 break;
3272 case SVM_EXITINTINFO_TYPE_EXEPT:
3273 /*
3274 * In case of software exceptions, do not reinject the vector,
3275 * but re-execute the instruction instead. Rewind RIP first
3276 * if we emulated INT3 before.
3277 */
3278 if (kvm_exception_is_soft(vector)) {
3279 if (vector == BP_VECTOR && int3_injected &&
3280 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3281 kvm_rip_write(&svm->vcpu,
3282 kvm_rip_read(&svm->vcpu) -
3283 int3_injected);
3284 break;
3285 }
3286 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3287 u32 err = svm->vmcb->control.exit_int_info_err;
3288 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3289
3290 } else
3291 kvm_requeue_exception(&svm->vcpu, vector);
3292 break;
3293 case SVM_EXITINTINFO_TYPE_INTR:
3294 kvm_queue_interrupt(&svm->vcpu, vector, false);
3295 break;
3296 default:
3297 break;
3298 }
3299 }
3300
3301 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3302 {
3303 struct vcpu_svm *svm = to_svm(vcpu);
3304 struct vmcb_control_area *control = &svm->vmcb->control;
3305
3306 control->exit_int_info = control->event_inj;
3307 control->exit_int_info_err = control->event_inj_err;
3308 control->event_inj = 0;
3309 svm_complete_interrupts(svm);
3310 }
3311
3312 #ifdef CONFIG_X86_64
3313 #define R "r"
3314 #else
3315 #define R "e"
3316 #endif
3317
3318 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3319 {
3320 struct vcpu_svm *svm = to_svm(vcpu);
3321
3322 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3323 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3324 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3325
3326 /*
3327 * A vmexit emulation is required before the vcpu can be executed
3328 * again.
3329 */
3330 if (unlikely(svm->nested.exit_required))
3331 return;
3332
3333 pre_svm_run(svm);
3334
3335 sync_lapic_to_cr8(vcpu);
3336
3337 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3338
3339 clgi();
3340
3341 local_irq_enable();
3342
3343 asm volatile (
3344 "push %%"R"bp; \n\t"
3345 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3346 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3347 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3348 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3349 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3350 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3351 #ifdef CONFIG_X86_64
3352 "mov %c[r8](%[svm]), %%r8 \n\t"
3353 "mov %c[r9](%[svm]), %%r9 \n\t"
3354 "mov %c[r10](%[svm]), %%r10 \n\t"
3355 "mov %c[r11](%[svm]), %%r11 \n\t"
3356 "mov %c[r12](%[svm]), %%r12 \n\t"
3357 "mov %c[r13](%[svm]), %%r13 \n\t"
3358 "mov %c[r14](%[svm]), %%r14 \n\t"
3359 "mov %c[r15](%[svm]), %%r15 \n\t"
3360 #endif
3361
3362 /* Enter guest mode */
3363 "push %%"R"ax \n\t"
3364 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3365 __ex(SVM_VMLOAD) "\n\t"
3366 __ex(SVM_VMRUN) "\n\t"
3367 __ex(SVM_VMSAVE) "\n\t"
3368 "pop %%"R"ax \n\t"
3369
3370 /* Save guest registers, load host registers */
3371 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3372 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3373 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3374 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3375 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3376 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3377 #ifdef CONFIG_X86_64
3378 "mov %%r8, %c[r8](%[svm]) \n\t"
3379 "mov %%r9, %c[r9](%[svm]) \n\t"
3380 "mov %%r10, %c[r10](%[svm]) \n\t"
3381 "mov %%r11, %c[r11](%[svm]) \n\t"
3382 "mov %%r12, %c[r12](%[svm]) \n\t"
3383 "mov %%r13, %c[r13](%[svm]) \n\t"
3384 "mov %%r14, %c[r14](%[svm]) \n\t"
3385 "mov %%r15, %c[r15](%[svm]) \n\t"
3386 #endif
3387 "pop %%"R"bp"
3388 :
3389 : [svm]"a"(svm),
3390 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3391 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3392 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3393 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3394 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3395 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3396 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3397 #ifdef CONFIG_X86_64
3398 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3399 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3400 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3401 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3402 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3403 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3404 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3405 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3406 #endif
3407 : "cc", "memory"
3408 , R"bx", R"cx", R"dx", R"si", R"di"
3409 #ifdef CONFIG_X86_64
3410 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3411 #endif
3412 );
3413
3414 #ifdef CONFIG_X86_64
3415 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3416 #else
3417 loadsegment(fs, svm->host.fs);
3418 #endif
3419
3420 reload_tss(vcpu);
3421
3422 local_irq_disable();
3423
3424 stgi();
3425
3426 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3427 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3428 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3429 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3430
3431 sync_cr8_to_lapic(vcpu);
3432
3433 svm->next_rip = 0;
3434
3435 /* if exit due to PF check for async PF */
3436 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3437 svm->apf_reason = kvm_read_and_reset_pf_reason();
3438
3439 if (npt_enabled) {
3440 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3441 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3442 }
3443
3444 /*
3445 * We need to handle MC intercepts here before the vcpu has a chance to
3446 * change the physical cpu
3447 */
3448 if (unlikely(svm->vmcb->control.exit_code ==
3449 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3450 svm_handle_mce(svm);
3451 }
3452
3453 #undef R
3454
3455 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3456 {
3457 struct vcpu_svm *svm = to_svm(vcpu);
3458
3459 svm->vmcb->save.cr3 = root;
3460 force_new_asid(vcpu);
3461 }
3462
3463 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3464 {
3465 struct vcpu_svm *svm = to_svm(vcpu);
3466
3467 svm->vmcb->control.nested_cr3 = root;
3468
3469 /* Also sync guest cr3 here in case we live migrate */
3470 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3471
3472 force_new_asid(vcpu);
3473 }
3474
3475 static int is_disabled(void)
3476 {
3477 u64 vm_cr;
3478
3479 rdmsrl(MSR_VM_CR, vm_cr);
3480 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3481 return 1;
3482
3483 return 0;
3484 }
3485
3486 static void
3487 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3488 {
3489 /*
3490 * Patch in the VMMCALL instruction:
3491 */
3492 hypercall[0] = 0x0f;
3493 hypercall[1] = 0x01;
3494 hypercall[2] = 0xd9;
3495 }
3496
3497 static void svm_check_processor_compat(void *rtn)
3498 {
3499 *(int *)rtn = 0;
3500 }
3501
3502 static bool svm_cpu_has_accelerated_tpr(void)
3503 {
3504 return false;
3505 }
3506
3507 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3508 {
3509 return 0;
3510 }
3511
3512 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3513 {
3514 }
3515
3516 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3517 {
3518 switch (func) {
3519 case 0x00000001:
3520 /* Mask out xsave bit as long as it is not supported by SVM */
3521 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3522 break;
3523 case 0x80000001:
3524 if (nested)
3525 entry->ecx |= (1 << 2); /* Set SVM bit */
3526 break;
3527 case 0x8000000A:
3528 entry->eax = 1; /* SVM revision 1 */
3529 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3530 ASID emulation to nested SVM */
3531 entry->ecx = 0; /* Reserved */
3532 entry->edx = 0; /* Per default do not support any
3533 additional features */
3534
3535 /* Support next_rip if host supports it */
3536 if (svm_has(SVM_FEATURE_NRIP))
3537 entry->edx |= SVM_FEATURE_NRIP;
3538
3539 /* Support NPT for the guest if enabled */
3540 if (npt_enabled)
3541 entry->edx |= SVM_FEATURE_NPT;
3542
3543 break;
3544 }
3545 }
3546
3547 static const struct trace_print_flags svm_exit_reasons_str[] = {
3548 { SVM_EXIT_READ_CR0, "read_cr0" },
3549 { SVM_EXIT_READ_CR3, "read_cr3" },
3550 { SVM_EXIT_READ_CR4, "read_cr4" },
3551 { SVM_EXIT_READ_CR8, "read_cr8" },
3552 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3553 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3554 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3555 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3556 { SVM_EXIT_READ_DR0, "read_dr0" },
3557 { SVM_EXIT_READ_DR1, "read_dr1" },
3558 { SVM_EXIT_READ_DR2, "read_dr2" },
3559 { SVM_EXIT_READ_DR3, "read_dr3" },
3560 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3561 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3562 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3563 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3564 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3565 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3566 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3567 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3568 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3569 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3570 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3571 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3572 { SVM_EXIT_INTR, "interrupt" },
3573 { SVM_EXIT_NMI, "nmi" },
3574 { SVM_EXIT_SMI, "smi" },
3575 { SVM_EXIT_INIT, "init" },
3576 { SVM_EXIT_VINTR, "vintr" },
3577 { SVM_EXIT_CPUID, "cpuid" },
3578 { SVM_EXIT_INVD, "invd" },
3579 { SVM_EXIT_HLT, "hlt" },
3580 { SVM_EXIT_INVLPG, "invlpg" },
3581 { SVM_EXIT_INVLPGA, "invlpga" },
3582 { SVM_EXIT_IOIO, "io" },
3583 { SVM_EXIT_MSR, "msr" },
3584 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3585 { SVM_EXIT_SHUTDOWN, "shutdown" },
3586 { SVM_EXIT_VMRUN, "vmrun" },
3587 { SVM_EXIT_VMMCALL, "hypercall" },
3588 { SVM_EXIT_VMLOAD, "vmload" },
3589 { SVM_EXIT_VMSAVE, "vmsave" },
3590 { SVM_EXIT_STGI, "stgi" },
3591 { SVM_EXIT_CLGI, "clgi" },
3592 { SVM_EXIT_SKINIT, "skinit" },
3593 { SVM_EXIT_WBINVD, "wbinvd" },
3594 { SVM_EXIT_MONITOR, "monitor" },
3595 { SVM_EXIT_MWAIT, "mwait" },
3596 { SVM_EXIT_NPF, "npf" },
3597 { -1, NULL }
3598 };
3599
3600 static int svm_get_lpage_level(void)
3601 {
3602 return PT_PDPE_LEVEL;
3603 }
3604
3605 static bool svm_rdtscp_supported(void)
3606 {
3607 return false;
3608 }
3609
3610 static bool svm_has_wbinvd_exit(void)
3611 {
3612 return true;
3613 }
3614
3615 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3616 {
3617 struct vcpu_svm *svm = to_svm(vcpu);
3618
3619 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3620 if (is_nested(svm))
3621 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3622 update_cr0_intercept(svm);
3623 }
3624
3625 static struct kvm_x86_ops svm_x86_ops = {
3626 .cpu_has_kvm_support = has_svm,
3627 .disabled_by_bios = is_disabled,
3628 .hardware_setup = svm_hardware_setup,
3629 .hardware_unsetup = svm_hardware_unsetup,
3630 .check_processor_compatibility = svm_check_processor_compat,
3631 .hardware_enable = svm_hardware_enable,
3632 .hardware_disable = svm_hardware_disable,
3633 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3634
3635 .vcpu_create = svm_create_vcpu,
3636 .vcpu_free = svm_free_vcpu,
3637 .vcpu_reset = svm_vcpu_reset,
3638
3639 .prepare_guest_switch = svm_prepare_guest_switch,
3640 .vcpu_load = svm_vcpu_load,
3641 .vcpu_put = svm_vcpu_put,
3642
3643 .set_guest_debug = svm_guest_debug,
3644 .get_msr = svm_get_msr,
3645 .set_msr = svm_set_msr,
3646 .get_segment_base = svm_get_segment_base,
3647 .get_segment = svm_get_segment,
3648 .set_segment = svm_set_segment,
3649 .get_cpl = svm_get_cpl,
3650 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3651 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3652 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3653 .set_cr0 = svm_set_cr0,
3654 .set_cr3 = svm_set_cr3,
3655 .set_cr4 = svm_set_cr4,
3656 .set_efer = svm_set_efer,
3657 .get_idt = svm_get_idt,
3658 .set_idt = svm_set_idt,
3659 .get_gdt = svm_get_gdt,
3660 .set_gdt = svm_set_gdt,
3661 .set_dr7 = svm_set_dr7,
3662 .cache_reg = svm_cache_reg,
3663 .get_rflags = svm_get_rflags,
3664 .set_rflags = svm_set_rflags,
3665 .fpu_activate = svm_fpu_activate,
3666 .fpu_deactivate = svm_fpu_deactivate,
3667
3668 .tlb_flush = svm_flush_tlb,
3669
3670 .run = svm_vcpu_run,
3671 .handle_exit = handle_exit,
3672 .skip_emulated_instruction = skip_emulated_instruction,
3673 .set_interrupt_shadow = svm_set_interrupt_shadow,
3674 .get_interrupt_shadow = svm_get_interrupt_shadow,
3675 .patch_hypercall = svm_patch_hypercall,
3676 .set_irq = svm_set_irq,
3677 .set_nmi = svm_inject_nmi,
3678 .queue_exception = svm_queue_exception,
3679 .cancel_injection = svm_cancel_injection,
3680 .interrupt_allowed = svm_interrupt_allowed,
3681 .nmi_allowed = svm_nmi_allowed,
3682 .get_nmi_mask = svm_get_nmi_mask,
3683 .set_nmi_mask = svm_set_nmi_mask,
3684 .enable_nmi_window = enable_nmi_window,
3685 .enable_irq_window = enable_irq_window,
3686 .update_cr8_intercept = update_cr8_intercept,
3687
3688 .set_tss_addr = svm_set_tss_addr,
3689 .get_tdp_level = get_npt_level,
3690 .get_mt_mask = svm_get_mt_mask,
3691
3692 .exit_reasons_str = svm_exit_reasons_str,
3693 .get_lpage_level = svm_get_lpage_level,
3694
3695 .cpuid_update = svm_cpuid_update,
3696
3697 .rdtscp_supported = svm_rdtscp_supported,
3698
3699 .set_supported_cpuid = svm_set_supported_cpuid,
3700
3701 .has_wbinvd_exit = svm_has_wbinvd_exit,
3702
3703 .write_tsc_offset = svm_write_tsc_offset,
3704 .adjust_tsc_offset = svm_adjust_tsc_offset,
3705
3706 .set_tdp_cr3 = set_tdp_cr3,
3707 };
3708
3709 static int __init svm_init(void)
3710 {
3711 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3712 __alignof__(struct vcpu_svm), THIS_MODULE);
3713 }
3714
3715 static void __exit svm_exit(void)
3716 {
3717 kvm_exit();
3718 }
3719
3720 module_init(svm_init)
3721 module_exit(svm_exit)
Linux kernel - Deliverables
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