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KVM: SVM: Add clean-bit for NPT state
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_DIRTY_MAX,
196 };
197
198 /* TPR is always written before VMRUN */
199 #define VMCB_ALWAYS_DIRTY_MASK (1U << VMCB_INTR)
200
201 static inline void mark_all_dirty(struct vmcb *vmcb)
202 {
203 vmcb->control.clean = 0;
204 }
205
206 static inline void mark_all_clean(struct vmcb *vmcb)
207 {
208 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
209 & ~VMCB_ALWAYS_DIRTY_MASK;
210 }
211
212 static inline void mark_dirty(struct vmcb *vmcb, int bit)
213 {
214 vmcb->control.clean &= ~(1 << bit);
215 }
216
217 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
218 {
219 return container_of(vcpu, struct vcpu_svm, vcpu);
220 }
221
222 static void recalc_intercepts(struct vcpu_svm *svm)
223 {
224 struct vmcb_control_area *c, *h;
225 struct nested_state *g;
226
227 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
228
229 if (!is_guest_mode(&svm->vcpu))
230 return;
231
232 c = &svm->vmcb->control;
233 h = &svm->nested.hsave->control;
234 g = &svm->nested;
235
236 c->intercept_cr = h->intercept_cr | g->intercept_cr;
237 c->intercept_dr = h->intercept_dr | g->intercept_dr;
238 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
239 c->intercept = h->intercept | g->intercept;
240 }
241
242 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
243 {
244 if (is_guest_mode(&svm->vcpu))
245 return svm->nested.hsave;
246 else
247 return svm->vmcb;
248 }
249
250 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
251 {
252 struct vmcb *vmcb = get_host_vmcb(svm);
253
254 vmcb->control.intercept_cr |= (1U << bit);
255
256 recalc_intercepts(svm);
257 }
258
259 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
260 {
261 struct vmcb *vmcb = get_host_vmcb(svm);
262
263 vmcb->control.intercept_cr &= ~(1U << bit);
264
265 recalc_intercepts(svm);
266 }
267
268 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
269 {
270 struct vmcb *vmcb = get_host_vmcb(svm);
271
272 return vmcb->control.intercept_cr & (1U << bit);
273 }
274
275 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
276 {
277 struct vmcb *vmcb = get_host_vmcb(svm);
278
279 vmcb->control.intercept_dr |= (1U << bit);
280
281 recalc_intercepts(svm);
282 }
283
284 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
285 {
286 struct vmcb *vmcb = get_host_vmcb(svm);
287
288 vmcb->control.intercept_dr &= ~(1U << bit);
289
290 recalc_intercepts(svm);
291 }
292
293 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
294 {
295 struct vmcb *vmcb = get_host_vmcb(svm);
296
297 vmcb->control.intercept_exceptions |= (1U << bit);
298
299 recalc_intercepts(svm);
300 }
301
302 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
303 {
304 struct vmcb *vmcb = get_host_vmcb(svm);
305
306 vmcb->control.intercept_exceptions &= ~(1U << bit);
307
308 recalc_intercepts(svm);
309 }
310
311 static inline void set_intercept(struct vcpu_svm *svm, int bit)
312 {
313 struct vmcb *vmcb = get_host_vmcb(svm);
314
315 vmcb->control.intercept |= (1ULL << bit);
316
317 recalc_intercepts(svm);
318 }
319
320 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
321 {
322 struct vmcb *vmcb = get_host_vmcb(svm);
323
324 vmcb->control.intercept &= ~(1ULL << bit);
325
326 recalc_intercepts(svm);
327 }
328
329 static inline void enable_gif(struct vcpu_svm *svm)
330 {
331 svm->vcpu.arch.hflags |= HF_GIF_MASK;
332 }
333
334 static inline void disable_gif(struct vcpu_svm *svm)
335 {
336 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
337 }
338
339 static inline bool gif_set(struct vcpu_svm *svm)
340 {
341 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
342 }
343
344 static unsigned long iopm_base;
345
346 struct kvm_ldttss_desc {
347 u16 limit0;
348 u16 base0;
349 unsigned base1:8, type:5, dpl:2, p:1;
350 unsigned limit1:4, zero0:3, g:1, base2:8;
351 u32 base3;
352 u32 zero1;
353 } __attribute__((packed));
354
355 struct svm_cpu_data {
356 int cpu;
357
358 u64 asid_generation;
359 u32 max_asid;
360 u32 next_asid;
361 struct kvm_ldttss_desc *tss_desc;
362
363 struct page *save_area;
364 };
365
366 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
367 static uint32_t svm_features;
368
369 struct svm_init_data {
370 int cpu;
371 int r;
372 };
373
374 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
375
376 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
377 #define MSRS_RANGE_SIZE 2048
378 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
379
380 static u32 svm_msrpm_offset(u32 msr)
381 {
382 u32 offset;
383 int i;
384
385 for (i = 0; i < NUM_MSR_MAPS; i++) {
386 if (msr < msrpm_ranges[i] ||
387 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
388 continue;
389
390 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
391 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
392
393 /* Now we have the u8 offset - but need the u32 offset */
394 return offset / 4;
395 }
396
397 /* MSR not in any range */
398 return MSR_INVALID;
399 }
400
401 #define MAX_INST_SIZE 15
402
403 static inline void clgi(void)
404 {
405 asm volatile (__ex(SVM_CLGI));
406 }
407
408 static inline void stgi(void)
409 {
410 asm volatile (__ex(SVM_STGI));
411 }
412
413 static inline void invlpga(unsigned long addr, u32 asid)
414 {
415 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
416 }
417
418 static inline void force_new_asid(struct kvm_vcpu *vcpu)
419 {
420 to_svm(vcpu)->asid_generation--;
421 }
422
423 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
424 {
425 force_new_asid(vcpu);
426 }
427
428 static int get_npt_level(void)
429 {
430 #ifdef CONFIG_X86_64
431 return PT64_ROOT_LEVEL;
432 #else
433 return PT32E_ROOT_LEVEL;
434 #endif
435 }
436
437 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
438 {
439 vcpu->arch.efer = efer;
440 if (!npt_enabled && !(efer & EFER_LMA))
441 efer &= ~EFER_LME;
442
443 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
444 }
445
446 static int is_external_interrupt(u32 info)
447 {
448 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
449 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
450 }
451
452 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
453 {
454 struct vcpu_svm *svm = to_svm(vcpu);
455 u32 ret = 0;
456
457 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
458 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
459 return ret & mask;
460 }
461
462 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
463 {
464 struct vcpu_svm *svm = to_svm(vcpu);
465
466 if (mask == 0)
467 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
468 else
469 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
470
471 }
472
473 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
474 {
475 struct vcpu_svm *svm = to_svm(vcpu);
476
477 if (svm->vmcb->control.next_rip != 0)
478 svm->next_rip = svm->vmcb->control.next_rip;
479
480 if (!svm->next_rip) {
481 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
482 EMULATE_DONE)
483 printk(KERN_DEBUG "%s: NOP\n", __func__);
484 return;
485 }
486 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
487 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
488 __func__, kvm_rip_read(vcpu), svm->next_rip);
489
490 kvm_rip_write(vcpu, svm->next_rip);
491 svm_set_interrupt_shadow(vcpu, 0);
492 }
493
494 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
495 bool has_error_code, u32 error_code,
496 bool reinject)
497 {
498 struct vcpu_svm *svm = to_svm(vcpu);
499
500 /*
501 * If we are within a nested VM we'd better #VMEXIT and let the guest
502 * handle the exception
503 */
504 if (!reinject &&
505 nested_svm_check_exception(svm, nr, has_error_code, error_code))
506 return;
507
508 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
509 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
510
511 /*
512 * For guest debugging where we have to reinject #BP if some
513 * INT3 is guest-owned:
514 * Emulate nRIP by moving RIP forward. Will fail if injection
515 * raises a fault that is not intercepted. Still better than
516 * failing in all cases.
517 */
518 skip_emulated_instruction(&svm->vcpu);
519 rip = kvm_rip_read(&svm->vcpu);
520 svm->int3_rip = rip + svm->vmcb->save.cs.base;
521 svm->int3_injected = rip - old_rip;
522 }
523
524 svm->vmcb->control.event_inj = nr
525 | SVM_EVTINJ_VALID
526 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
527 | SVM_EVTINJ_TYPE_EXEPT;
528 svm->vmcb->control.event_inj_err = error_code;
529 }
530
531 static void svm_init_erratum_383(void)
532 {
533 u32 low, high;
534 int err;
535 u64 val;
536
537 if (!cpu_has_amd_erratum(amd_erratum_383))
538 return;
539
540 /* Use _safe variants to not break nested virtualization */
541 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
542 if (err)
543 return;
544
545 val |= (1ULL << 47);
546
547 low = lower_32_bits(val);
548 high = upper_32_bits(val);
549
550 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
551
552 erratum_383_found = true;
553 }
554
555 static int has_svm(void)
556 {
557 const char *msg;
558
559 if (!cpu_has_svm(&msg)) {
560 printk(KERN_INFO "has_svm: %s\n", msg);
561 return 0;
562 }
563
564 return 1;
565 }
566
567 static void svm_hardware_disable(void *garbage)
568 {
569 cpu_svm_disable();
570 }
571
572 static int svm_hardware_enable(void *garbage)
573 {
574
575 struct svm_cpu_data *sd;
576 uint64_t efer;
577 struct desc_ptr gdt_descr;
578 struct desc_struct *gdt;
579 int me = raw_smp_processor_id();
580
581 rdmsrl(MSR_EFER, efer);
582 if (efer & EFER_SVME)
583 return -EBUSY;
584
585 if (!has_svm()) {
586 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
587 me);
588 return -EINVAL;
589 }
590 sd = per_cpu(svm_data, me);
591
592 if (!sd) {
593 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
594 me);
595 return -EINVAL;
596 }
597
598 sd->asid_generation = 1;
599 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
600 sd->next_asid = sd->max_asid + 1;
601
602 native_store_gdt(&gdt_descr);
603 gdt = (struct desc_struct *)gdt_descr.address;
604 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
605
606 wrmsrl(MSR_EFER, efer | EFER_SVME);
607
608 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
609
610 svm_init_erratum_383();
611
612 return 0;
613 }
614
615 static void svm_cpu_uninit(int cpu)
616 {
617 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
618
619 if (!sd)
620 return;
621
622 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
623 __free_page(sd->save_area);
624 kfree(sd);
625 }
626
627 static int svm_cpu_init(int cpu)
628 {
629 struct svm_cpu_data *sd;
630 int r;
631
632 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
633 if (!sd)
634 return -ENOMEM;
635 sd->cpu = cpu;
636 sd->save_area = alloc_page(GFP_KERNEL);
637 r = -ENOMEM;
638 if (!sd->save_area)
639 goto err_1;
640
641 per_cpu(svm_data, cpu) = sd;
642
643 return 0;
644
645 err_1:
646 kfree(sd);
647 return r;
648
649 }
650
651 static bool valid_msr_intercept(u32 index)
652 {
653 int i;
654
655 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
656 if (direct_access_msrs[i].index == index)
657 return true;
658
659 return false;
660 }
661
662 static void set_msr_interception(u32 *msrpm, unsigned msr,
663 int read, int write)
664 {
665 u8 bit_read, bit_write;
666 unsigned long tmp;
667 u32 offset;
668
669 /*
670 * If this warning triggers extend the direct_access_msrs list at the
671 * beginning of the file
672 */
673 WARN_ON(!valid_msr_intercept(msr));
674
675 offset = svm_msrpm_offset(msr);
676 bit_read = 2 * (msr & 0x0f);
677 bit_write = 2 * (msr & 0x0f) + 1;
678 tmp = msrpm[offset];
679
680 BUG_ON(offset == MSR_INVALID);
681
682 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
683 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
684
685 msrpm[offset] = tmp;
686 }
687
688 static void svm_vcpu_init_msrpm(u32 *msrpm)
689 {
690 int i;
691
692 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
693
694 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
695 if (!direct_access_msrs[i].always)
696 continue;
697
698 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
699 }
700 }
701
702 static void add_msr_offset(u32 offset)
703 {
704 int i;
705
706 for (i = 0; i < MSRPM_OFFSETS; ++i) {
707
708 /* Offset already in list? */
709 if (msrpm_offsets[i] == offset)
710 return;
711
712 /* Slot used by another offset? */
713 if (msrpm_offsets[i] != MSR_INVALID)
714 continue;
715
716 /* Add offset to list */
717 msrpm_offsets[i] = offset;
718
719 return;
720 }
721
722 /*
723 * If this BUG triggers the msrpm_offsets table has an overflow. Just
724 * increase MSRPM_OFFSETS in this case.
725 */
726 BUG();
727 }
728
729 static void init_msrpm_offsets(void)
730 {
731 int i;
732
733 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
734
735 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
736 u32 offset;
737
738 offset = svm_msrpm_offset(direct_access_msrs[i].index);
739 BUG_ON(offset == MSR_INVALID);
740
741 add_msr_offset(offset);
742 }
743 }
744
745 static void svm_enable_lbrv(struct vcpu_svm *svm)
746 {
747 u32 *msrpm = svm->msrpm;
748
749 svm->vmcb->control.lbr_ctl = 1;
750 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
751 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
752 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
753 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
754 }
755
756 static void svm_disable_lbrv(struct vcpu_svm *svm)
757 {
758 u32 *msrpm = svm->msrpm;
759
760 svm->vmcb->control.lbr_ctl = 0;
761 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
762 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
763 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
764 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
765 }
766
767 static __init int svm_hardware_setup(void)
768 {
769 int cpu;
770 struct page *iopm_pages;
771 void *iopm_va;
772 int r;
773
774 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
775
776 if (!iopm_pages)
777 return -ENOMEM;
778
779 iopm_va = page_address(iopm_pages);
780 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
781 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
782
783 init_msrpm_offsets();
784
785 if (boot_cpu_has(X86_FEATURE_NX))
786 kvm_enable_efer_bits(EFER_NX);
787
788 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
789 kvm_enable_efer_bits(EFER_FFXSR);
790
791 if (nested) {
792 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
793 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
794 }
795
796 for_each_possible_cpu(cpu) {
797 r = svm_cpu_init(cpu);
798 if (r)
799 goto err;
800 }
801
802 svm_features = cpuid_edx(SVM_CPUID_FUNC);
803
804 if (!boot_cpu_has(X86_FEATURE_NPT))
805 npt_enabled = false;
806
807 if (npt_enabled && !npt) {
808 printk(KERN_INFO "kvm: Nested Paging disabled\n");
809 npt_enabled = false;
810 }
811
812 if (npt_enabled) {
813 printk(KERN_INFO "kvm: Nested Paging enabled\n");
814 kvm_enable_tdp();
815 } else
816 kvm_disable_tdp();
817
818 return 0;
819
820 err:
821 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
822 iopm_base = 0;
823 return r;
824 }
825
826 static __exit void svm_hardware_unsetup(void)
827 {
828 int cpu;
829
830 for_each_possible_cpu(cpu)
831 svm_cpu_uninit(cpu);
832
833 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
834 iopm_base = 0;
835 }
836
837 static void init_seg(struct vmcb_seg *seg)
838 {
839 seg->selector = 0;
840 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
841 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
842 seg->limit = 0xffff;
843 seg->base = 0;
844 }
845
846 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
847 {
848 seg->selector = 0;
849 seg->attrib = SVM_SELECTOR_P_MASK | type;
850 seg->limit = 0xffff;
851 seg->base = 0;
852 }
853
854 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
855 {
856 struct vcpu_svm *svm = to_svm(vcpu);
857 u64 g_tsc_offset = 0;
858
859 if (is_guest_mode(vcpu)) {
860 g_tsc_offset = svm->vmcb->control.tsc_offset -
861 svm->nested.hsave->control.tsc_offset;
862 svm->nested.hsave->control.tsc_offset = offset;
863 }
864
865 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
866
867 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
868 }
869
870 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
871 {
872 struct vcpu_svm *svm = to_svm(vcpu);
873
874 svm->vmcb->control.tsc_offset += adjustment;
875 if (is_guest_mode(vcpu))
876 svm->nested.hsave->control.tsc_offset += adjustment;
877 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
878 }
879
880 static void init_vmcb(struct vcpu_svm *svm)
881 {
882 struct vmcb_control_area *control = &svm->vmcb->control;
883 struct vmcb_save_area *save = &svm->vmcb->save;
884
885 svm->vcpu.fpu_active = 1;
886 svm->vcpu.arch.hflags = 0;
887
888 set_cr_intercept(svm, INTERCEPT_CR0_READ);
889 set_cr_intercept(svm, INTERCEPT_CR3_READ);
890 set_cr_intercept(svm, INTERCEPT_CR4_READ);
891 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
892 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
893 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
894 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
895
896 set_dr_intercept(svm, INTERCEPT_DR0_READ);
897 set_dr_intercept(svm, INTERCEPT_DR1_READ);
898 set_dr_intercept(svm, INTERCEPT_DR2_READ);
899 set_dr_intercept(svm, INTERCEPT_DR3_READ);
900 set_dr_intercept(svm, INTERCEPT_DR4_READ);
901 set_dr_intercept(svm, INTERCEPT_DR5_READ);
902 set_dr_intercept(svm, INTERCEPT_DR6_READ);
903 set_dr_intercept(svm, INTERCEPT_DR7_READ);
904
905 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
913
914 set_exception_intercept(svm, PF_VECTOR);
915 set_exception_intercept(svm, UD_VECTOR);
916 set_exception_intercept(svm, MC_VECTOR);
917
918 set_intercept(svm, INTERCEPT_INTR);
919 set_intercept(svm, INTERCEPT_NMI);
920 set_intercept(svm, INTERCEPT_SMI);
921 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
922 set_intercept(svm, INTERCEPT_CPUID);
923 set_intercept(svm, INTERCEPT_INVD);
924 set_intercept(svm, INTERCEPT_HLT);
925 set_intercept(svm, INTERCEPT_INVLPG);
926 set_intercept(svm, INTERCEPT_INVLPGA);
927 set_intercept(svm, INTERCEPT_IOIO_PROT);
928 set_intercept(svm, INTERCEPT_MSR_PROT);
929 set_intercept(svm, INTERCEPT_TASK_SWITCH);
930 set_intercept(svm, INTERCEPT_SHUTDOWN);
931 set_intercept(svm, INTERCEPT_VMRUN);
932 set_intercept(svm, INTERCEPT_VMMCALL);
933 set_intercept(svm, INTERCEPT_VMLOAD);
934 set_intercept(svm, INTERCEPT_VMSAVE);
935 set_intercept(svm, INTERCEPT_STGI);
936 set_intercept(svm, INTERCEPT_CLGI);
937 set_intercept(svm, INTERCEPT_SKINIT);
938 set_intercept(svm, INTERCEPT_WBINVD);
939 set_intercept(svm, INTERCEPT_MONITOR);
940 set_intercept(svm, INTERCEPT_MWAIT);
941
942 control->iopm_base_pa = iopm_base;
943 control->msrpm_base_pa = __pa(svm->msrpm);
944 control->int_ctl = V_INTR_MASKING_MASK;
945
946 init_seg(&save->es);
947 init_seg(&save->ss);
948 init_seg(&save->ds);
949 init_seg(&save->fs);
950 init_seg(&save->gs);
951
952 save->cs.selector = 0xf000;
953 /* Executable/Readable Code Segment */
954 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
955 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
956 save->cs.limit = 0xffff;
957 /*
958 * cs.base should really be 0xffff0000, but vmx can't handle that, so
959 * be consistent with it.
960 *
961 * Replace when we have real mode working for vmx.
962 */
963 save->cs.base = 0xf0000;
964
965 save->gdtr.limit = 0xffff;
966 save->idtr.limit = 0xffff;
967
968 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
969 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
970
971 svm_set_efer(&svm->vcpu, 0);
972 save->dr6 = 0xffff0ff0;
973 save->dr7 = 0x400;
974 save->rflags = 2;
975 save->rip = 0x0000fff0;
976 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
977
978 /*
979 * This is the guest-visible cr0 value.
980 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
981 */
982 svm->vcpu.arch.cr0 = 0;
983 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
984
985 save->cr4 = X86_CR4_PAE;
986 /* rdx = ?? */
987
988 if (npt_enabled) {
989 /* Setup VMCB for Nested Paging */
990 control->nested_ctl = 1;
991 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
992 clr_intercept(svm, INTERCEPT_INVLPG);
993 clr_exception_intercept(svm, PF_VECTOR);
994 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
995 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
996 save->g_pat = 0x0007040600070406ULL;
997 save->cr3 = 0;
998 save->cr4 = 0;
999 }
1000 force_new_asid(&svm->vcpu);
1001
1002 svm->nested.vmcb = 0;
1003 svm->vcpu.arch.hflags = 0;
1004
1005 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1006 control->pause_filter_count = 3000;
1007 set_intercept(svm, INTERCEPT_PAUSE);
1008 }
1009
1010 mark_all_dirty(svm->vmcb);
1011
1012 enable_gif(svm);
1013 }
1014
1015 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1016 {
1017 struct vcpu_svm *svm = to_svm(vcpu);
1018
1019 init_vmcb(svm);
1020
1021 if (!kvm_vcpu_is_bsp(vcpu)) {
1022 kvm_rip_write(vcpu, 0);
1023 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1024 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1025 }
1026 vcpu->arch.regs_avail = ~0;
1027 vcpu->arch.regs_dirty = ~0;
1028
1029 return 0;
1030 }
1031
1032 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1033 {
1034 struct vcpu_svm *svm;
1035 struct page *page;
1036 struct page *msrpm_pages;
1037 struct page *hsave_page;
1038 struct page *nested_msrpm_pages;
1039 int err;
1040
1041 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1042 if (!svm) {
1043 err = -ENOMEM;
1044 goto out;
1045 }
1046
1047 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1048 if (err)
1049 goto free_svm;
1050
1051 err = -ENOMEM;
1052 page = alloc_page(GFP_KERNEL);
1053 if (!page)
1054 goto uninit;
1055
1056 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1057 if (!msrpm_pages)
1058 goto free_page1;
1059
1060 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1061 if (!nested_msrpm_pages)
1062 goto free_page2;
1063
1064 hsave_page = alloc_page(GFP_KERNEL);
1065 if (!hsave_page)
1066 goto free_page3;
1067
1068 svm->nested.hsave = page_address(hsave_page);
1069
1070 svm->msrpm = page_address(msrpm_pages);
1071 svm_vcpu_init_msrpm(svm->msrpm);
1072
1073 svm->nested.msrpm = page_address(nested_msrpm_pages);
1074 svm_vcpu_init_msrpm(svm->nested.msrpm);
1075
1076 svm->vmcb = page_address(page);
1077 clear_page(svm->vmcb);
1078 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1079 svm->asid_generation = 0;
1080 init_vmcb(svm);
1081 kvm_write_tsc(&svm->vcpu, 0);
1082
1083 err = fx_init(&svm->vcpu);
1084 if (err)
1085 goto free_page4;
1086
1087 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1088 if (kvm_vcpu_is_bsp(&svm->vcpu))
1089 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1090
1091 return &svm->vcpu;
1092
1093 free_page4:
1094 __free_page(hsave_page);
1095 free_page3:
1096 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1097 free_page2:
1098 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1099 free_page1:
1100 __free_page(page);
1101 uninit:
1102 kvm_vcpu_uninit(&svm->vcpu);
1103 free_svm:
1104 kmem_cache_free(kvm_vcpu_cache, svm);
1105 out:
1106 return ERR_PTR(err);
1107 }
1108
1109 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1110 {
1111 struct vcpu_svm *svm = to_svm(vcpu);
1112
1113 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1114 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1115 __free_page(virt_to_page(svm->nested.hsave));
1116 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1117 kvm_vcpu_uninit(vcpu);
1118 kmem_cache_free(kvm_vcpu_cache, svm);
1119 }
1120
1121 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1122 {
1123 struct vcpu_svm *svm = to_svm(vcpu);
1124 int i;
1125
1126 if (unlikely(cpu != vcpu->cpu)) {
1127 svm->asid_generation = 0;
1128 mark_all_dirty(svm->vmcb);
1129 }
1130
1131 #ifdef CONFIG_X86_64
1132 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1133 #endif
1134 savesegment(fs, svm->host.fs);
1135 savesegment(gs, svm->host.gs);
1136 svm->host.ldt = kvm_read_ldt();
1137
1138 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1139 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1140 }
1141
1142 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1143 {
1144 struct vcpu_svm *svm = to_svm(vcpu);
1145 int i;
1146
1147 ++vcpu->stat.host_state_reload;
1148 kvm_load_ldt(svm->host.ldt);
1149 #ifdef CONFIG_X86_64
1150 loadsegment(fs, svm->host.fs);
1151 load_gs_index(svm->host.gs);
1152 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1153 #else
1154 loadsegment(gs, svm->host.gs);
1155 #endif
1156 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1157 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1158 }
1159
1160 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1161 {
1162 return to_svm(vcpu)->vmcb->save.rflags;
1163 }
1164
1165 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1166 {
1167 to_svm(vcpu)->vmcb->save.rflags = rflags;
1168 }
1169
1170 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1171 {
1172 switch (reg) {
1173 case VCPU_EXREG_PDPTR:
1174 BUG_ON(!npt_enabled);
1175 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1176 break;
1177 default:
1178 BUG();
1179 }
1180 }
1181
1182 static void svm_set_vintr(struct vcpu_svm *svm)
1183 {
1184 set_intercept(svm, INTERCEPT_VINTR);
1185 }
1186
1187 static void svm_clear_vintr(struct vcpu_svm *svm)
1188 {
1189 clr_intercept(svm, INTERCEPT_VINTR);
1190 }
1191
1192 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1193 {
1194 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1195
1196 switch (seg) {
1197 case VCPU_SREG_CS: return &save->cs;
1198 case VCPU_SREG_DS: return &save->ds;
1199 case VCPU_SREG_ES: return &save->es;
1200 case VCPU_SREG_FS: return &save->fs;
1201 case VCPU_SREG_GS: return &save->gs;
1202 case VCPU_SREG_SS: return &save->ss;
1203 case VCPU_SREG_TR: return &save->tr;
1204 case VCPU_SREG_LDTR: return &save->ldtr;
1205 }
1206 BUG();
1207 return NULL;
1208 }
1209
1210 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1211 {
1212 struct vmcb_seg *s = svm_seg(vcpu, seg);
1213
1214 return s->base;
1215 }
1216
1217 static void svm_get_segment(struct kvm_vcpu *vcpu,
1218 struct kvm_segment *var, int seg)
1219 {
1220 struct vmcb_seg *s = svm_seg(vcpu, seg);
1221
1222 var->base = s->base;
1223 var->limit = s->limit;
1224 var->selector = s->selector;
1225 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1226 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1227 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1228 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1229 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1230 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1231 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1232 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1233
1234 /*
1235 * AMD's VMCB does not have an explicit unusable field, so emulate it
1236 * for cross vendor migration purposes by "not present"
1237 */
1238 var->unusable = !var->present || (var->type == 0);
1239
1240 switch (seg) {
1241 case VCPU_SREG_CS:
1242 /*
1243 * SVM always stores 0 for the 'G' bit in the CS selector in
1244 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1245 * Intel's VMENTRY has a check on the 'G' bit.
1246 */
1247 var->g = s->limit > 0xfffff;
1248 break;
1249 case VCPU_SREG_TR:
1250 /*
1251 * Work around a bug where the busy flag in the tr selector
1252 * isn't exposed
1253 */
1254 var->type |= 0x2;
1255 break;
1256 case VCPU_SREG_DS:
1257 case VCPU_SREG_ES:
1258 case VCPU_SREG_FS:
1259 case VCPU_SREG_GS:
1260 /*
1261 * The accessed bit must always be set in the segment
1262 * descriptor cache, although it can be cleared in the
1263 * descriptor, the cached bit always remains at 1. Since
1264 * Intel has a check on this, set it here to support
1265 * cross-vendor migration.
1266 */
1267 if (!var->unusable)
1268 var->type |= 0x1;
1269 break;
1270 case VCPU_SREG_SS:
1271 /*
1272 * On AMD CPUs sometimes the DB bit in the segment
1273 * descriptor is left as 1, although the whole segment has
1274 * been made unusable. Clear it here to pass an Intel VMX
1275 * entry check when cross vendor migrating.
1276 */
1277 if (var->unusable)
1278 var->db = 0;
1279 break;
1280 }
1281 }
1282
1283 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1284 {
1285 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1286
1287 return save->cpl;
1288 }
1289
1290 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1291 {
1292 struct vcpu_svm *svm = to_svm(vcpu);
1293
1294 dt->size = svm->vmcb->save.idtr.limit;
1295 dt->address = svm->vmcb->save.idtr.base;
1296 }
1297
1298 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1299 {
1300 struct vcpu_svm *svm = to_svm(vcpu);
1301
1302 svm->vmcb->save.idtr.limit = dt->size;
1303 svm->vmcb->save.idtr.base = dt->address ;
1304 }
1305
1306 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1307 {
1308 struct vcpu_svm *svm = to_svm(vcpu);
1309
1310 dt->size = svm->vmcb->save.gdtr.limit;
1311 dt->address = svm->vmcb->save.gdtr.base;
1312 }
1313
1314 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1315 {
1316 struct vcpu_svm *svm = to_svm(vcpu);
1317
1318 svm->vmcb->save.gdtr.limit = dt->size;
1319 svm->vmcb->save.gdtr.base = dt->address ;
1320 }
1321
1322 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1323 {
1324 }
1325
1326 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1327 {
1328 }
1329
1330 static void update_cr0_intercept(struct vcpu_svm *svm)
1331 {
1332 ulong gcr0 = svm->vcpu.arch.cr0;
1333 u64 *hcr0 = &svm->vmcb->save.cr0;
1334
1335 if (!svm->vcpu.fpu_active)
1336 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1337 else
1338 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1339 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1340
1341
1342 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1343 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1344 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1345 } else {
1346 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1347 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1348 }
1349 }
1350
1351 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1352 {
1353 struct vcpu_svm *svm = to_svm(vcpu);
1354
1355 if (is_guest_mode(vcpu)) {
1356 /*
1357 * We are here because we run in nested mode, the host kvm
1358 * intercepts cr0 writes but the l1 hypervisor does not.
1359 * But the L1 hypervisor may intercept selective cr0 writes.
1360 * This needs to be checked here.
1361 */
1362 unsigned long old, new;
1363
1364 /* Remove bits that would trigger a real cr0 write intercept */
1365 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1366 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1367
1368 if (old == new) {
1369 /* cr0 write with ts and mp unchanged */
1370 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1371 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1372 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1373 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1374 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1375 return;
1376 }
1377 }
1378 }
1379
1380 #ifdef CONFIG_X86_64
1381 if (vcpu->arch.efer & EFER_LME) {
1382 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1383 vcpu->arch.efer |= EFER_LMA;
1384 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1385 }
1386
1387 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1388 vcpu->arch.efer &= ~EFER_LMA;
1389 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1390 }
1391 }
1392 #endif
1393 vcpu->arch.cr0 = cr0;
1394
1395 if (!npt_enabled)
1396 cr0 |= X86_CR0_PG | X86_CR0_WP;
1397
1398 if (!vcpu->fpu_active)
1399 cr0 |= X86_CR0_TS;
1400 /*
1401 * re-enable caching here because the QEMU bios
1402 * does not do it - this results in some delay at
1403 * reboot
1404 */
1405 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1406 svm->vmcb->save.cr0 = cr0;
1407 update_cr0_intercept(svm);
1408 }
1409
1410 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1411 {
1412 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1413 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1414
1415 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1416 force_new_asid(vcpu);
1417
1418 vcpu->arch.cr4 = cr4;
1419 if (!npt_enabled)
1420 cr4 |= X86_CR4_PAE;
1421 cr4 |= host_cr4_mce;
1422 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1423 }
1424
1425 static void svm_set_segment(struct kvm_vcpu *vcpu,
1426 struct kvm_segment *var, int seg)
1427 {
1428 struct vcpu_svm *svm = to_svm(vcpu);
1429 struct vmcb_seg *s = svm_seg(vcpu, seg);
1430
1431 s->base = var->base;
1432 s->limit = var->limit;
1433 s->selector = var->selector;
1434 if (var->unusable)
1435 s->attrib = 0;
1436 else {
1437 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1438 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1439 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1440 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1441 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1442 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1443 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1444 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1445 }
1446 if (seg == VCPU_SREG_CS)
1447 svm->vmcb->save.cpl
1448 = (svm->vmcb->save.cs.attrib
1449 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1450
1451 }
1452
1453 static void update_db_intercept(struct kvm_vcpu *vcpu)
1454 {
1455 struct vcpu_svm *svm = to_svm(vcpu);
1456
1457 clr_exception_intercept(svm, DB_VECTOR);
1458 clr_exception_intercept(svm, BP_VECTOR);
1459
1460 if (svm->nmi_singlestep)
1461 set_exception_intercept(svm, DB_VECTOR);
1462
1463 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1464 if (vcpu->guest_debug &
1465 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1466 set_exception_intercept(svm, DB_VECTOR);
1467 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1468 set_exception_intercept(svm, BP_VECTOR);
1469 } else
1470 vcpu->guest_debug = 0;
1471 }
1472
1473 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1474 {
1475 struct vcpu_svm *svm = to_svm(vcpu);
1476
1477 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1478 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1479 else
1480 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1481
1482 update_db_intercept(vcpu);
1483 }
1484
1485 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1486 {
1487 if (sd->next_asid > sd->max_asid) {
1488 ++sd->asid_generation;
1489 sd->next_asid = 1;
1490 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1491 }
1492
1493 svm->asid_generation = sd->asid_generation;
1494 svm->vmcb->control.asid = sd->next_asid++;
1495
1496 mark_dirty(svm->vmcb, VMCB_ASID);
1497 }
1498
1499 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1500 {
1501 struct vcpu_svm *svm = to_svm(vcpu);
1502
1503 svm->vmcb->save.dr7 = value;
1504 }
1505
1506 static int pf_interception(struct vcpu_svm *svm)
1507 {
1508 u64 fault_address = svm->vmcb->control.exit_info_2;
1509 u32 error_code;
1510 int r = 1;
1511
1512 switch (svm->apf_reason) {
1513 default:
1514 error_code = svm->vmcb->control.exit_info_1;
1515
1516 trace_kvm_page_fault(fault_address, error_code);
1517 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1518 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1519 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1520 break;
1521 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1522 svm->apf_reason = 0;
1523 local_irq_disable();
1524 kvm_async_pf_task_wait(fault_address);
1525 local_irq_enable();
1526 break;
1527 case KVM_PV_REASON_PAGE_READY:
1528 svm->apf_reason = 0;
1529 local_irq_disable();
1530 kvm_async_pf_task_wake(fault_address);
1531 local_irq_enable();
1532 break;
1533 }
1534 return r;
1535 }
1536
1537 static int db_interception(struct vcpu_svm *svm)
1538 {
1539 struct kvm_run *kvm_run = svm->vcpu.run;
1540
1541 if (!(svm->vcpu.guest_debug &
1542 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1543 !svm->nmi_singlestep) {
1544 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1545 return 1;
1546 }
1547
1548 if (svm->nmi_singlestep) {
1549 svm->nmi_singlestep = false;
1550 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1551 svm->vmcb->save.rflags &=
1552 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1553 update_db_intercept(&svm->vcpu);
1554 }
1555
1556 if (svm->vcpu.guest_debug &
1557 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1558 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1559 kvm_run->debug.arch.pc =
1560 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1561 kvm_run->debug.arch.exception = DB_VECTOR;
1562 return 0;
1563 }
1564
1565 return 1;
1566 }
1567
1568 static int bp_interception(struct vcpu_svm *svm)
1569 {
1570 struct kvm_run *kvm_run = svm->vcpu.run;
1571
1572 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1573 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1574 kvm_run->debug.arch.exception = BP_VECTOR;
1575 return 0;
1576 }
1577
1578 static int ud_interception(struct vcpu_svm *svm)
1579 {
1580 int er;
1581
1582 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1583 if (er != EMULATE_DONE)
1584 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1585 return 1;
1586 }
1587
1588 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1589 {
1590 struct vcpu_svm *svm = to_svm(vcpu);
1591
1592 clr_exception_intercept(svm, NM_VECTOR);
1593
1594 svm->vcpu.fpu_active = 1;
1595 update_cr0_intercept(svm);
1596 }
1597
1598 static int nm_interception(struct vcpu_svm *svm)
1599 {
1600 svm_fpu_activate(&svm->vcpu);
1601 return 1;
1602 }
1603
1604 static bool is_erratum_383(void)
1605 {
1606 int err, i;
1607 u64 value;
1608
1609 if (!erratum_383_found)
1610 return false;
1611
1612 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1613 if (err)
1614 return false;
1615
1616 /* Bit 62 may or may not be set for this mce */
1617 value &= ~(1ULL << 62);
1618
1619 if (value != 0xb600000000010015ULL)
1620 return false;
1621
1622 /* Clear MCi_STATUS registers */
1623 for (i = 0; i < 6; ++i)
1624 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1625
1626 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1627 if (!err) {
1628 u32 low, high;
1629
1630 value &= ~(1ULL << 2);
1631 low = lower_32_bits(value);
1632 high = upper_32_bits(value);
1633
1634 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1635 }
1636
1637 /* Flush tlb to evict multi-match entries */
1638 __flush_tlb_all();
1639
1640 return true;
1641 }
1642
1643 static void svm_handle_mce(struct vcpu_svm *svm)
1644 {
1645 if (is_erratum_383()) {
1646 /*
1647 * Erratum 383 triggered. Guest state is corrupt so kill the
1648 * guest.
1649 */
1650 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1651
1652 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1653
1654 return;
1655 }
1656
1657 /*
1658 * On an #MC intercept the MCE handler is not called automatically in
1659 * the host. So do it by hand here.
1660 */
1661 asm volatile (
1662 "int $0x12\n");
1663 /* not sure if we ever come back to this point */
1664
1665 return;
1666 }
1667
1668 static int mc_interception(struct vcpu_svm *svm)
1669 {
1670 return 1;
1671 }
1672
1673 static int shutdown_interception(struct vcpu_svm *svm)
1674 {
1675 struct kvm_run *kvm_run = svm->vcpu.run;
1676
1677 /*
1678 * VMCB is undefined after a SHUTDOWN intercept
1679 * so reinitialize it.
1680 */
1681 clear_page(svm->vmcb);
1682 init_vmcb(svm);
1683
1684 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1685 return 0;
1686 }
1687
1688 static int io_interception(struct vcpu_svm *svm)
1689 {
1690 struct kvm_vcpu *vcpu = &svm->vcpu;
1691 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1692 int size, in, string;
1693 unsigned port;
1694
1695 ++svm->vcpu.stat.io_exits;
1696 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1697 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1698 if (string || in)
1699 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1700
1701 port = io_info >> 16;
1702 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1703 svm->next_rip = svm->vmcb->control.exit_info_2;
1704 skip_emulated_instruction(&svm->vcpu);
1705
1706 return kvm_fast_pio_out(vcpu, size, port);
1707 }
1708
1709 static int nmi_interception(struct vcpu_svm *svm)
1710 {
1711 return 1;
1712 }
1713
1714 static int intr_interception(struct vcpu_svm *svm)
1715 {
1716 ++svm->vcpu.stat.irq_exits;
1717 return 1;
1718 }
1719
1720 static int nop_on_interception(struct vcpu_svm *svm)
1721 {
1722 return 1;
1723 }
1724
1725 static int halt_interception(struct vcpu_svm *svm)
1726 {
1727 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1728 skip_emulated_instruction(&svm->vcpu);
1729 return kvm_emulate_halt(&svm->vcpu);
1730 }
1731
1732 static int vmmcall_interception(struct vcpu_svm *svm)
1733 {
1734 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1735 skip_emulated_instruction(&svm->vcpu);
1736 kvm_emulate_hypercall(&svm->vcpu);
1737 return 1;
1738 }
1739
1740 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1741 {
1742 struct vcpu_svm *svm = to_svm(vcpu);
1743
1744 return svm->nested.nested_cr3;
1745 }
1746
1747 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1748 unsigned long root)
1749 {
1750 struct vcpu_svm *svm = to_svm(vcpu);
1751
1752 svm->vmcb->control.nested_cr3 = root;
1753 mark_dirty(svm->vmcb, VMCB_NPT);
1754 force_new_asid(vcpu);
1755 }
1756
1757 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1758 struct x86_exception *fault)
1759 {
1760 struct vcpu_svm *svm = to_svm(vcpu);
1761
1762 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1763 svm->vmcb->control.exit_code_hi = 0;
1764 svm->vmcb->control.exit_info_1 = fault->error_code;
1765 svm->vmcb->control.exit_info_2 = fault->address;
1766
1767 nested_svm_vmexit(svm);
1768 }
1769
1770 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1771 {
1772 int r;
1773
1774 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1775
1776 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1777 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1778 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1779 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1780 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1781
1782 return r;
1783 }
1784
1785 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1786 {
1787 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1788 }
1789
1790 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1791 {
1792 if (!(svm->vcpu.arch.efer & EFER_SVME)
1793 || !is_paging(&svm->vcpu)) {
1794 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1795 return 1;
1796 }
1797
1798 if (svm->vmcb->save.cpl) {
1799 kvm_inject_gp(&svm->vcpu, 0);
1800 return 1;
1801 }
1802
1803 return 0;
1804 }
1805
1806 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1807 bool has_error_code, u32 error_code)
1808 {
1809 int vmexit;
1810
1811 if (!is_guest_mode(&svm->vcpu))
1812 return 0;
1813
1814 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1815 svm->vmcb->control.exit_code_hi = 0;
1816 svm->vmcb->control.exit_info_1 = error_code;
1817 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1818
1819 vmexit = nested_svm_intercept(svm);
1820 if (vmexit == NESTED_EXIT_DONE)
1821 svm->nested.exit_required = true;
1822
1823 return vmexit;
1824 }
1825
1826 /* This function returns true if it is save to enable the irq window */
1827 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1828 {
1829 if (!is_guest_mode(&svm->vcpu))
1830 return true;
1831
1832 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1833 return true;
1834
1835 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1836 return false;
1837
1838 /*
1839 * if vmexit was already requested (by intercepted exception
1840 * for instance) do not overwrite it with "external interrupt"
1841 * vmexit.
1842 */
1843 if (svm->nested.exit_required)
1844 return false;
1845
1846 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1847 svm->vmcb->control.exit_info_1 = 0;
1848 svm->vmcb->control.exit_info_2 = 0;
1849
1850 if (svm->nested.intercept & 1ULL) {
1851 /*
1852 * The #vmexit can't be emulated here directly because this
1853 * code path runs with irqs and preemtion disabled. A
1854 * #vmexit emulation might sleep. Only signal request for
1855 * the #vmexit here.
1856 */
1857 svm->nested.exit_required = true;
1858 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1859 return false;
1860 }
1861
1862 return true;
1863 }
1864
1865 /* This function returns true if it is save to enable the nmi window */
1866 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1867 {
1868 if (!is_guest_mode(&svm->vcpu))
1869 return true;
1870
1871 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1872 return true;
1873
1874 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1875 svm->nested.exit_required = true;
1876
1877 return false;
1878 }
1879
1880 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1881 {
1882 struct page *page;
1883
1884 might_sleep();
1885
1886 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1887 if (is_error_page(page))
1888 goto error;
1889
1890 *_page = page;
1891
1892 return kmap(page);
1893
1894 error:
1895 kvm_release_page_clean(page);
1896 kvm_inject_gp(&svm->vcpu, 0);
1897
1898 return NULL;
1899 }
1900
1901 static void nested_svm_unmap(struct page *page)
1902 {
1903 kunmap(page);
1904 kvm_release_page_dirty(page);
1905 }
1906
1907 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1908 {
1909 unsigned port;
1910 u8 val, bit;
1911 u64 gpa;
1912
1913 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1914 return NESTED_EXIT_HOST;
1915
1916 port = svm->vmcb->control.exit_info_1 >> 16;
1917 gpa = svm->nested.vmcb_iopm + (port / 8);
1918 bit = port % 8;
1919 val = 0;
1920
1921 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1922 val &= (1 << bit);
1923
1924 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1925 }
1926
1927 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1928 {
1929 u32 offset, msr, value;
1930 int write, mask;
1931
1932 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1933 return NESTED_EXIT_HOST;
1934
1935 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1936 offset = svm_msrpm_offset(msr);
1937 write = svm->vmcb->control.exit_info_1 & 1;
1938 mask = 1 << ((2 * (msr & 0xf)) + write);
1939
1940 if (offset == MSR_INVALID)
1941 return NESTED_EXIT_DONE;
1942
1943 /* Offset is in 32 bit units but need in 8 bit units */
1944 offset *= 4;
1945
1946 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1947 return NESTED_EXIT_DONE;
1948
1949 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1950 }
1951
1952 static int nested_svm_exit_special(struct vcpu_svm *svm)
1953 {
1954 u32 exit_code = svm->vmcb->control.exit_code;
1955
1956 switch (exit_code) {
1957 case SVM_EXIT_INTR:
1958 case SVM_EXIT_NMI:
1959 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1960 return NESTED_EXIT_HOST;
1961 case SVM_EXIT_NPF:
1962 /* For now we are always handling NPFs when using them */
1963 if (npt_enabled)
1964 return NESTED_EXIT_HOST;
1965 break;
1966 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1967 /* When we're shadowing, trap PFs, but not async PF */
1968 if (!npt_enabled && svm->apf_reason == 0)
1969 return NESTED_EXIT_HOST;
1970 break;
1971 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1972 nm_interception(svm);
1973 break;
1974 default:
1975 break;
1976 }
1977
1978 return NESTED_EXIT_CONTINUE;
1979 }
1980
1981 /*
1982 * If this function returns true, this #vmexit was already handled
1983 */
1984 static int nested_svm_intercept(struct vcpu_svm *svm)
1985 {
1986 u32 exit_code = svm->vmcb->control.exit_code;
1987 int vmexit = NESTED_EXIT_HOST;
1988
1989 switch (exit_code) {
1990 case SVM_EXIT_MSR:
1991 vmexit = nested_svm_exit_handled_msr(svm);
1992 break;
1993 case SVM_EXIT_IOIO:
1994 vmexit = nested_svm_intercept_ioio(svm);
1995 break;
1996 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1997 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1998 if (svm->nested.intercept_cr & bit)
1999 vmexit = NESTED_EXIT_DONE;
2000 break;
2001 }
2002 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2003 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2004 if (svm->nested.intercept_dr & bit)
2005 vmexit = NESTED_EXIT_DONE;
2006 break;
2007 }
2008 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2009 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2010 if (svm->nested.intercept_exceptions & excp_bits)
2011 vmexit = NESTED_EXIT_DONE;
2012 /* async page fault always cause vmexit */
2013 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2014 svm->apf_reason != 0)
2015 vmexit = NESTED_EXIT_DONE;
2016 break;
2017 }
2018 case SVM_EXIT_ERR: {
2019 vmexit = NESTED_EXIT_DONE;
2020 break;
2021 }
2022 default: {
2023 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2024 if (svm->nested.intercept & exit_bits)
2025 vmexit = NESTED_EXIT_DONE;
2026 }
2027 }
2028
2029 return vmexit;
2030 }
2031
2032 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2033 {
2034 int vmexit;
2035
2036 vmexit = nested_svm_intercept(svm);
2037
2038 if (vmexit == NESTED_EXIT_DONE)
2039 nested_svm_vmexit(svm);
2040
2041 return vmexit;
2042 }
2043
2044 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2045 {
2046 struct vmcb_control_area *dst = &dst_vmcb->control;
2047 struct vmcb_control_area *from = &from_vmcb->control;
2048
2049 dst->intercept_cr = from->intercept_cr;
2050 dst->intercept_dr = from->intercept_dr;
2051 dst->intercept_exceptions = from->intercept_exceptions;
2052 dst->intercept = from->intercept;
2053 dst->iopm_base_pa = from->iopm_base_pa;
2054 dst->msrpm_base_pa = from->msrpm_base_pa;
2055 dst->tsc_offset = from->tsc_offset;
2056 dst->asid = from->asid;
2057 dst->tlb_ctl = from->tlb_ctl;
2058 dst->int_ctl = from->int_ctl;
2059 dst->int_vector = from->int_vector;
2060 dst->int_state = from->int_state;
2061 dst->exit_code = from->exit_code;
2062 dst->exit_code_hi = from->exit_code_hi;
2063 dst->exit_info_1 = from->exit_info_1;
2064 dst->exit_info_2 = from->exit_info_2;
2065 dst->exit_int_info = from->exit_int_info;
2066 dst->exit_int_info_err = from->exit_int_info_err;
2067 dst->nested_ctl = from->nested_ctl;
2068 dst->event_inj = from->event_inj;
2069 dst->event_inj_err = from->event_inj_err;
2070 dst->nested_cr3 = from->nested_cr3;
2071 dst->lbr_ctl = from->lbr_ctl;
2072 }
2073
2074 static int nested_svm_vmexit(struct vcpu_svm *svm)
2075 {
2076 struct vmcb *nested_vmcb;
2077 struct vmcb *hsave = svm->nested.hsave;
2078 struct vmcb *vmcb = svm->vmcb;
2079 struct page *page;
2080
2081 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2082 vmcb->control.exit_info_1,
2083 vmcb->control.exit_info_2,
2084 vmcb->control.exit_int_info,
2085 vmcb->control.exit_int_info_err);
2086
2087 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2088 if (!nested_vmcb)
2089 return 1;
2090
2091 /* Exit Guest-Mode */
2092 leave_guest_mode(&svm->vcpu);
2093 svm->nested.vmcb = 0;
2094
2095 /* Give the current vmcb to the guest */
2096 disable_gif(svm);
2097
2098 nested_vmcb->save.es = vmcb->save.es;
2099 nested_vmcb->save.cs = vmcb->save.cs;
2100 nested_vmcb->save.ss = vmcb->save.ss;
2101 nested_vmcb->save.ds = vmcb->save.ds;
2102 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2103 nested_vmcb->save.idtr = vmcb->save.idtr;
2104 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2105 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2106 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2107 nested_vmcb->save.cr2 = vmcb->save.cr2;
2108 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2109 nested_vmcb->save.rflags = vmcb->save.rflags;
2110 nested_vmcb->save.rip = vmcb->save.rip;
2111 nested_vmcb->save.rsp = vmcb->save.rsp;
2112 nested_vmcb->save.rax = vmcb->save.rax;
2113 nested_vmcb->save.dr7 = vmcb->save.dr7;
2114 nested_vmcb->save.dr6 = vmcb->save.dr6;
2115 nested_vmcb->save.cpl = vmcb->save.cpl;
2116
2117 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2118 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2119 nested_vmcb->control.int_state = vmcb->control.int_state;
2120 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2121 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2122 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2123 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2124 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2125 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2126 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2127
2128 /*
2129 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2130 * to make sure that we do not lose injected events. So check event_inj
2131 * here and copy it to exit_int_info if it is valid.
2132 * Exit_int_info and event_inj can't be both valid because the case
2133 * below only happens on a VMRUN instruction intercept which has
2134 * no valid exit_int_info set.
2135 */
2136 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2137 struct vmcb_control_area *nc = &nested_vmcb->control;
2138
2139 nc->exit_int_info = vmcb->control.event_inj;
2140 nc->exit_int_info_err = vmcb->control.event_inj_err;
2141 }
2142
2143 nested_vmcb->control.tlb_ctl = 0;
2144 nested_vmcb->control.event_inj = 0;
2145 nested_vmcb->control.event_inj_err = 0;
2146
2147 /* We always set V_INTR_MASKING and remember the old value in hflags */
2148 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2149 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2150
2151 /* Restore the original control entries */
2152 copy_vmcb_control_area(vmcb, hsave);
2153
2154 kvm_clear_exception_queue(&svm->vcpu);
2155 kvm_clear_interrupt_queue(&svm->vcpu);
2156
2157 svm->nested.nested_cr3 = 0;
2158
2159 /* Restore selected save entries */
2160 svm->vmcb->save.es = hsave->save.es;
2161 svm->vmcb->save.cs = hsave->save.cs;
2162 svm->vmcb->save.ss = hsave->save.ss;
2163 svm->vmcb->save.ds = hsave->save.ds;
2164 svm->vmcb->save.gdtr = hsave->save.gdtr;
2165 svm->vmcb->save.idtr = hsave->save.idtr;
2166 svm->vmcb->save.rflags = hsave->save.rflags;
2167 svm_set_efer(&svm->vcpu, hsave->save.efer);
2168 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2169 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2170 if (npt_enabled) {
2171 svm->vmcb->save.cr3 = hsave->save.cr3;
2172 svm->vcpu.arch.cr3 = hsave->save.cr3;
2173 } else {
2174 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2175 }
2176 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2177 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2178 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2179 svm->vmcb->save.dr7 = 0;
2180 svm->vmcb->save.cpl = 0;
2181 svm->vmcb->control.exit_int_info = 0;
2182
2183 mark_all_dirty(svm->vmcb);
2184
2185 nested_svm_unmap(page);
2186
2187 nested_svm_uninit_mmu_context(&svm->vcpu);
2188 kvm_mmu_reset_context(&svm->vcpu);
2189 kvm_mmu_load(&svm->vcpu);
2190
2191 return 0;
2192 }
2193
2194 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2195 {
2196 /*
2197 * This function merges the msr permission bitmaps of kvm and the
2198 * nested vmcb. It is omptimized in that it only merges the parts where
2199 * the kvm msr permission bitmap may contain zero bits
2200 */
2201 int i;
2202
2203 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2204 return true;
2205
2206 for (i = 0; i < MSRPM_OFFSETS; i++) {
2207 u32 value, p;
2208 u64 offset;
2209
2210 if (msrpm_offsets[i] == 0xffffffff)
2211 break;
2212
2213 p = msrpm_offsets[i];
2214 offset = svm->nested.vmcb_msrpm + (p * 4);
2215
2216 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2217 return false;
2218
2219 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2220 }
2221
2222 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2223
2224 return true;
2225 }
2226
2227 static bool nested_vmcb_checks(struct vmcb *vmcb)
2228 {
2229 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2230 return false;
2231
2232 if (vmcb->control.asid == 0)
2233 return false;
2234
2235 if (vmcb->control.nested_ctl && !npt_enabled)
2236 return false;
2237
2238 return true;
2239 }
2240
2241 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2242 {
2243 struct vmcb *nested_vmcb;
2244 struct vmcb *hsave = svm->nested.hsave;
2245 struct vmcb *vmcb = svm->vmcb;
2246 struct page *page;
2247 u64 vmcb_gpa;
2248
2249 vmcb_gpa = svm->vmcb->save.rax;
2250
2251 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2252 if (!nested_vmcb)
2253 return false;
2254
2255 if (!nested_vmcb_checks(nested_vmcb)) {
2256 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2257 nested_vmcb->control.exit_code_hi = 0;
2258 nested_vmcb->control.exit_info_1 = 0;
2259 nested_vmcb->control.exit_info_2 = 0;
2260
2261 nested_svm_unmap(page);
2262
2263 return false;
2264 }
2265
2266 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2267 nested_vmcb->save.rip,
2268 nested_vmcb->control.int_ctl,
2269 nested_vmcb->control.event_inj,
2270 nested_vmcb->control.nested_ctl);
2271
2272 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2273 nested_vmcb->control.intercept_cr >> 16,
2274 nested_vmcb->control.intercept_exceptions,
2275 nested_vmcb->control.intercept);
2276
2277 /* Clear internal status */
2278 kvm_clear_exception_queue(&svm->vcpu);
2279 kvm_clear_interrupt_queue(&svm->vcpu);
2280
2281 /*
2282 * Save the old vmcb, so we don't need to pick what we save, but can
2283 * restore everything when a VMEXIT occurs
2284 */
2285 hsave->save.es = vmcb->save.es;
2286 hsave->save.cs = vmcb->save.cs;
2287 hsave->save.ss = vmcb->save.ss;
2288 hsave->save.ds = vmcb->save.ds;
2289 hsave->save.gdtr = vmcb->save.gdtr;
2290 hsave->save.idtr = vmcb->save.idtr;
2291 hsave->save.efer = svm->vcpu.arch.efer;
2292 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2293 hsave->save.cr4 = svm->vcpu.arch.cr4;
2294 hsave->save.rflags = vmcb->save.rflags;
2295 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2296 hsave->save.rsp = vmcb->save.rsp;
2297 hsave->save.rax = vmcb->save.rax;
2298 if (npt_enabled)
2299 hsave->save.cr3 = vmcb->save.cr3;
2300 else
2301 hsave->save.cr3 = svm->vcpu.arch.cr3;
2302
2303 copy_vmcb_control_area(hsave, vmcb);
2304
2305 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2306 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2307 else
2308 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2309
2310 if (nested_vmcb->control.nested_ctl) {
2311 kvm_mmu_unload(&svm->vcpu);
2312 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2313 nested_svm_init_mmu_context(&svm->vcpu);
2314 }
2315
2316 /* Load the nested guest state */
2317 svm->vmcb->save.es = nested_vmcb->save.es;
2318 svm->vmcb->save.cs = nested_vmcb->save.cs;
2319 svm->vmcb->save.ss = nested_vmcb->save.ss;
2320 svm->vmcb->save.ds = nested_vmcb->save.ds;
2321 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2322 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2323 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2324 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2325 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2326 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2327 if (npt_enabled) {
2328 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2329 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2330 } else
2331 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2332
2333 /* Guest paging mode is active - reset mmu */
2334 kvm_mmu_reset_context(&svm->vcpu);
2335
2336 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2337 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2338 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2339 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2340
2341 /* In case we don't even reach vcpu_run, the fields are not updated */
2342 svm->vmcb->save.rax = nested_vmcb->save.rax;
2343 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2344 svm->vmcb->save.rip = nested_vmcb->save.rip;
2345 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2346 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2347 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2348
2349 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2350 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2351
2352 /* cache intercepts */
2353 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2354 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2355 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2356 svm->nested.intercept = nested_vmcb->control.intercept;
2357
2358 force_new_asid(&svm->vcpu);
2359 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2360 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2361 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2362 else
2363 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2364
2365 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2366 /* We only want the cr8 intercept bits of the guest */
2367 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2368 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2369 }
2370
2371 /* We don't want to see VMMCALLs from a nested guest */
2372 clr_intercept(svm, INTERCEPT_VMMCALL);
2373
2374 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2375 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2376 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2377 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2378 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2379 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2380
2381 nested_svm_unmap(page);
2382
2383 /* Enter Guest-Mode */
2384 enter_guest_mode(&svm->vcpu);
2385
2386 /*
2387 * Merge guest and host intercepts - must be called with vcpu in
2388 * guest-mode to take affect here
2389 */
2390 recalc_intercepts(svm);
2391
2392 svm->nested.vmcb = vmcb_gpa;
2393
2394 enable_gif(svm);
2395
2396 mark_all_dirty(svm->vmcb);
2397
2398 return true;
2399 }
2400
2401 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2402 {
2403 to_vmcb->save.fs = from_vmcb->save.fs;
2404 to_vmcb->save.gs = from_vmcb->save.gs;
2405 to_vmcb->save.tr = from_vmcb->save.tr;
2406 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2407 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2408 to_vmcb->save.star = from_vmcb->save.star;
2409 to_vmcb->save.lstar = from_vmcb->save.lstar;
2410 to_vmcb->save.cstar = from_vmcb->save.cstar;
2411 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2412 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2413 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2414 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2415 }
2416
2417 static int vmload_interception(struct vcpu_svm *svm)
2418 {
2419 struct vmcb *nested_vmcb;
2420 struct page *page;
2421
2422 if (nested_svm_check_permissions(svm))
2423 return 1;
2424
2425 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2426 skip_emulated_instruction(&svm->vcpu);
2427
2428 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2429 if (!nested_vmcb)
2430 return 1;
2431
2432 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2433 nested_svm_unmap(page);
2434
2435 return 1;
2436 }
2437
2438 static int vmsave_interception(struct vcpu_svm *svm)
2439 {
2440 struct vmcb *nested_vmcb;
2441 struct page *page;
2442
2443 if (nested_svm_check_permissions(svm))
2444 return 1;
2445
2446 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2447 skip_emulated_instruction(&svm->vcpu);
2448
2449 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2450 if (!nested_vmcb)
2451 return 1;
2452
2453 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2454 nested_svm_unmap(page);
2455
2456 return 1;
2457 }
2458
2459 static int vmrun_interception(struct vcpu_svm *svm)
2460 {
2461 if (nested_svm_check_permissions(svm))
2462 return 1;
2463
2464 /* Save rip after vmrun instruction */
2465 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2466
2467 if (!nested_svm_vmrun(svm))
2468 return 1;
2469
2470 if (!nested_svm_vmrun_msrpm(svm))
2471 goto failed;
2472
2473 return 1;
2474
2475 failed:
2476
2477 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2478 svm->vmcb->control.exit_code_hi = 0;
2479 svm->vmcb->control.exit_info_1 = 0;
2480 svm->vmcb->control.exit_info_2 = 0;
2481
2482 nested_svm_vmexit(svm);
2483
2484 return 1;
2485 }
2486
2487 static int stgi_interception(struct vcpu_svm *svm)
2488 {
2489 if (nested_svm_check_permissions(svm))
2490 return 1;
2491
2492 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2493 skip_emulated_instruction(&svm->vcpu);
2494 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2495
2496 enable_gif(svm);
2497
2498 return 1;
2499 }
2500
2501 static int clgi_interception(struct vcpu_svm *svm)
2502 {
2503 if (nested_svm_check_permissions(svm))
2504 return 1;
2505
2506 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2507 skip_emulated_instruction(&svm->vcpu);
2508
2509 disable_gif(svm);
2510
2511 /* After a CLGI no interrupts should come */
2512 svm_clear_vintr(svm);
2513 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2514
2515 mark_dirty(svm->vmcb, VMCB_INTR);
2516
2517 return 1;
2518 }
2519
2520 static int invlpga_interception(struct vcpu_svm *svm)
2521 {
2522 struct kvm_vcpu *vcpu = &svm->vcpu;
2523
2524 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2525 vcpu->arch.regs[VCPU_REGS_RAX]);
2526
2527 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2528 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2529
2530 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2531 skip_emulated_instruction(&svm->vcpu);
2532 return 1;
2533 }
2534
2535 static int skinit_interception(struct vcpu_svm *svm)
2536 {
2537 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2538
2539 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2540 return 1;
2541 }
2542
2543 static int invalid_op_interception(struct vcpu_svm *svm)
2544 {
2545 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2546 return 1;
2547 }
2548
2549 static int task_switch_interception(struct vcpu_svm *svm)
2550 {
2551 u16 tss_selector;
2552 int reason;
2553 int int_type = svm->vmcb->control.exit_int_info &
2554 SVM_EXITINTINFO_TYPE_MASK;
2555 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2556 uint32_t type =
2557 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2558 uint32_t idt_v =
2559 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2560 bool has_error_code = false;
2561 u32 error_code = 0;
2562
2563 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2564
2565 if (svm->vmcb->control.exit_info_2 &
2566 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2567 reason = TASK_SWITCH_IRET;
2568 else if (svm->vmcb->control.exit_info_2 &
2569 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2570 reason = TASK_SWITCH_JMP;
2571 else if (idt_v)
2572 reason = TASK_SWITCH_GATE;
2573 else
2574 reason = TASK_SWITCH_CALL;
2575
2576 if (reason == TASK_SWITCH_GATE) {
2577 switch (type) {
2578 case SVM_EXITINTINFO_TYPE_NMI:
2579 svm->vcpu.arch.nmi_injected = false;
2580 break;
2581 case SVM_EXITINTINFO_TYPE_EXEPT:
2582 if (svm->vmcb->control.exit_info_2 &
2583 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2584 has_error_code = true;
2585 error_code =
2586 (u32)svm->vmcb->control.exit_info_2;
2587 }
2588 kvm_clear_exception_queue(&svm->vcpu);
2589 break;
2590 case SVM_EXITINTINFO_TYPE_INTR:
2591 kvm_clear_interrupt_queue(&svm->vcpu);
2592 break;
2593 default:
2594 break;
2595 }
2596 }
2597
2598 if (reason != TASK_SWITCH_GATE ||
2599 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2600 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2601 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2602 skip_emulated_instruction(&svm->vcpu);
2603
2604 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2605 has_error_code, error_code) == EMULATE_FAIL) {
2606 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2607 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2608 svm->vcpu.run->internal.ndata = 0;
2609 return 0;
2610 }
2611 return 1;
2612 }
2613
2614 static int cpuid_interception(struct vcpu_svm *svm)
2615 {
2616 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2617 kvm_emulate_cpuid(&svm->vcpu);
2618 return 1;
2619 }
2620
2621 static int iret_interception(struct vcpu_svm *svm)
2622 {
2623 ++svm->vcpu.stat.nmi_window_exits;
2624 clr_intercept(svm, INTERCEPT_IRET);
2625 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2626 return 1;
2627 }
2628
2629 static int invlpg_interception(struct vcpu_svm *svm)
2630 {
2631 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2632 }
2633
2634 static int emulate_on_interception(struct vcpu_svm *svm)
2635 {
2636 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2637 }
2638
2639 static int cr0_write_interception(struct vcpu_svm *svm)
2640 {
2641 struct kvm_vcpu *vcpu = &svm->vcpu;
2642 int r;
2643
2644 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2645
2646 if (svm->nested.vmexit_rip) {
2647 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2648 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2649 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2650 svm->nested.vmexit_rip = 0;
2651 }
2652
2653 return r == EMULATE_DONE;
2654 }
2655
2656 static int cr8_write_interception(struct vcpu_svm *svm)
2657 {
2658 struct kvm_run *kvm_run = svm->vcpu.run;
2659
2660 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2661 /* instruction emulation calls kvm_set_cr8() */
2662 emulate_instruction(&svm->vcpu, 0, 0, 0);
2663 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2664 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2665 return 1;
2666 }
2667 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2668 return 1;
2669 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2670 return 0;
2671 }
2672
2673 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2674 {
2675 struct vcpu_svm *svm = to_svm(vcpu);
2676
2677 switch (ecx) {
2678 case MSR_IA32_TSC: {
2679 struct vmcb *vmcb = get_host_vmcb(svm);
2680
2681 *data = vmcb->control.tsc_offset + native_read_tsc();
2682 break;
2683 }
2684 case MSR_STAR:
2685 *data = svm->vmcb->save.star;
2686 break;
2687 #ifdef CONFIG_X86_64
2688 case MSR_LSTAR:
2689 *data = svm->vmcb->save.lstar;
2690 break;
2691 case MSR_CSTAR:
2692 *data = svm->vmcb->save.cstar;
2693 break;
2694 case MSR_KERNEL_GS_BASE:
2695 *data = svm->vmcb->save.kernel_gs_base;
2696 break;
2697 case MSR_SYSCALL_MASK:
2698 *data = svm->vmcb->save.sfmask;
2699 break;
2700 #endif
2701 case MSR_IA32_SYSENTER_CS:
2702 *data = svm->vmcb->save.sysenter_cs;
2703 break;
2704 case MSR_IA32_SYSENTER_EIP:
2705 *data = svm->sysenter_eip;
2706 break;
2707 case MSR_IA32_SYSENTER_ESP:
2708 *data = svm->sysenter_esp;
2709 break;
2710 /*
2711 * Nobody will change the following 5 values in the VMCB so we can
2712 * safely return them on rdmsr. They will always be 0 until LBRV is
2713 * implemented.
2714 */
2715 case MSR_IA32_DEBUGCTLMSR:
2716 *data = svm->vmcb->save.dbgctl;
2717 break;
2718 case MSR_IA32_LASTBRANCHFROMIP:
2719 *data = svm->vmcb->save.br_from;
2720 break;
2721 case MSR_IA32_LASTBRANCHTOIP:
2722 *data = svm->vmcb->save.br_to;
2723 break;
2724 case MSR_IA32_LASTINTFROMIP:
2725 *data = svm->vmcb->save.last_excp_from;
2726 break;
2727 case MSR_IA32_LASTINTTOIP:
2728 *data = svm->vmcb->save.last_excp_to;
2729 break;
2730 case MSR_VM_HSAVE_PA:
2731 *data = svm->nested.hsave_msr;
2732 break;
2733 case MSR_VM_CR:
2734 *data = svm->nested.vm_cr_msr;
2735 break;
2736 case MSR_IA32_UCODE_REV:
2737 *data = 0x01000065;
2738 break;
2739 default:
2740 return kvm_get_msr_common(vcpu, ecx, data);
2741 }
2742 return 0;
2743 }
2744
2745 static int rdmsr_interception(struct vcpu_svm *svm)
2746 {
2747 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2748 u64 data;
2749
2750 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2751 trace_kvm_msr_read_ex(ecx);
2752 kvm_inject_gp(&svm->vcpu, 0);
2753 } else {
2754 trace_kvm_msr_read(ecx, data);
2755
2756 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2757 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2758 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2759 skip_emulated_instruction(&svm->vcpu);
2760 }
2761 return 1;
2762 }
2763
2764 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2765 {
2766 struct vcpu_svm *svm = to_svm(vcpu);
2767 int svm_dis, chg_mask;
2768
2769 if (data & ~SVM_VM_CR_VALID_MASK)
2770 return 1;
2771
2772 chg_mask = SVM_VM_CR_VALID_MASK;
2773
2774 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2775 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2776
2777 svm->nested.vm_cr_msr &= ~chg_mask;
2778 svm->nested.vm_cr_msr |= (data & chg_mask);
2779
2780 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2781
2782 /* check for svm_disable while efer.svme is set */
2783 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2784 return 1;
2785
2786 return 0;
2787 }
2788
2789 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2790 {
2791 struct vcpu_svm *svm = to_svm(vcpu);
2792
2793 switch (ecx) {
2794 case MSR_IA32_TSC:
2795 kvm_write_tsc(vcpu, data);
2796 break;
2797 case MSR_STAR:
2798 svm->vmcb->save.star = data;
2799 break;
2800 #ifdef CONFIG_X86_64
2801 case MSR_LSTAR:
2802 svm->vmcb->save.lstar = data;
2803 break;
2804 case MSR_CSTAR:
2805 svm->vmcb->save.cstar = data;
2806 break;
2807 case MSR_KERNEL_GS_BASE:
2808 svm->vmcb->save.kernel_gs_base = data;
2809 break;
2810 case MSR_SYSCALL_MASK:
2811 svm->vmcb->save.sfmask = data;
2812 break;
2813 #endif
2814 case MSR_IA32_SYSENTER_CS:
2815 svm->vmcb->save.sysenter_cs = data;
2816 break;
2817 case MSR_IA32_SYSENTER_EIP:
2818 svm->sysenter_eip = data;
2819 svm->vmcb->save.sysenter_eip = data;
2820 break;
2821 case MSR_IA32_SYSENTER_ESP:
2822 svm->sysenter_esp = data;
2823 svm->vmcb->save.sysenter_esp = data;
2824 break;
2825 case MSR_IA32_DEBUGCTLMSR:
2826 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2827 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2828 __func__, data);
2829 break;
2830 }
2831 if (data & DEBUGCTL_RESERVED_BITS)
2832 return 1;
2833
2834 svm->vmcb->save.dbgctl = data;
2835 if (data & (1ULL<<0))
2836 svm_enable_lbrv(svm);
2837 else
2838 svm_disable_lbrv(svm);
2839 break;
2840 case MSR_VM_HSAVE_PA:
2841 svm->nested.hsave_msr = data;
2842 break;
2843 case MSR_VM_CR:
2844 return svm_set_vm_cr(vcpu, data);
2845 case MSR_VM_IGNNE:
2846 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2847 break;
2848 default:
2849 return kvm_set_msr_common(vcpu, ecx, data);
2850 }
2851 return 0;
2852 }
2853
2854 static int wrmsr_interception(struct vcpu_svm *svm)
2855 {
2856 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2857 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2858 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2859
2860
2861 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2862 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2863 trace_kvm_msr_write_ex(ecx, data);
2864 kvm_inject_gp(&svm->vcpu, 0);
2865 } else {
2866 trace_kvm_msr_write(ecx, data);
2867 skip_emulated_instruction(&svm->vcpu);
2868 }
2869 return 1;
2870 }
2871
2872 static int msr_interception(struct vcpu_svm *svm)
2873 {
2874 if (svm->vmcb->control.exit_info_1)
2875 return wrmsr_interception(svm);
2876 else
2877 return rdmsr_interception(svm);
2878 }
2879
2880 static int interrupt_window_interception(struct vcpu_svm *svm)
2881 {
2882 struct kvm_run *kvm_run = svm->vcpu.run;
2883
2884 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2885 svm_clear_vintr(svm);
2886 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2887 mark_dirty(svm->vmcb, VMCB_INTR);
2888 /*
2889 * If the user space waits to inject interrupts, exit as soon as
2890 * possible
2891 */
2892 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2893 kvm_run->request_interrupt_window &&
2894 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2895 ++svm->vcpu.stat.irq_window_exits;
2896 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2897 return 0;
2898 }
2899
2900 return 1;
2901 }
2902
2903 static int pause_interception(struct vcpu_svm *svm)
2904 {
2905 kvm_vcpu_on_spin(&(svm->vcpu));
2906 return 1;
2907 }
2908
2909 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2910 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2911 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2912 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2913 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2914 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2915 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2916 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2917 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2918 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2919 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2920 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2921 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2922 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2923 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2924 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2925 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2926 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2927 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2928 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2929 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2930 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2931 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2932 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2933 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2934 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2935 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2936 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2937 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2938 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2939 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2940 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2941 [SVM_EXIT_INTR] = intr_interception,
2942 [SVM_EXIT_NMI] = nmi_interception,
2943 [SVM_EXIT_SMI] = nop_on_interception,
2944 [SVM_EXIT_INIT] = nop_on_interception,
2945 [SVM_EXIT_VINTR] = interrupt_window_interception,
2946 [SVM_EXIT_CPUID] = cpuid_interception,
2947 [SVM_EXIT_IRET] = iret_interception,
2948 [SVM_EXIT_INVD] = emulate_on_interception,
2949 [SVM_EXIT_PAUSE] = pause_interception,
2950 [SVM_EXIT_HLT] = halt_interception,
2951 [SVM_EXIT_INVLPG] = invlpg_interception,
2952 [SVM_EXIT_INVLPGA] = invlpga_interception,
2953 [SVM_EXIT_IOIO] = io_interception,
2954 [SVM_EXIT_MSR] = msr_interception,
2955 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2956 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2957 [SVM_EXIT_VMRUN] = vmrun_interception,
2958 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2959 [SVM_EXIT_VMLOAD] = vmload_interception,
2960 [SVM_EXIT_VMSAVE] = vmsave_interception,
2961 [SVM_EXIT_STGI] = stgi_interception,
2962 [SVM_EXIT_CLGI] = clgi_interception,
2963 [SVM_EXIT_SKINIT] = skinit_interception,
2964 [SVM_EXIT_WBINVD] = emulate_on_interception,
2965 [SVM_EXIT_MONITOR] = invalid_op_interception,
2966 [SVM_EXIT_MWAIT] = invalid_op_interception,
2967 [SVM_EXIT_NPF] = pf_interception,
2968 };
2969
2970 void dump_vmcb(struct kvm_vcpu *vcpu)
2971 {
2972 struct vcpu_svm *svm = to_svm(vcpu);
2973 struct vmcb_control_area *control = &svm->vmcb->control;
2974 struct vmcb_save_area *save = &svm->vmcb->save;
2975
2976 pr_err("VMCB Control Area:\n");
2977 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2978 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2979 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2980 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2981 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2982 pr_err("intercepts: %016llx\n", control->intercept);
2983 pr_err("pause filter count: %d\n", control->pause_filter_count);
2984 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2985 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2986 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2987 pr_err("asid: %d\n", control->asid);
2988 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2989 pr_err("int_ctl: %08x\n", control->int_ctl);
2990 pr_err("int_vector: %08x\n", control->int_vector);
2991 pr_err("int_state: %08x\n", control->int_state);
2992 pr_err("exit_code: %08x\n", control->exit_code);
2993 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2994 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2995 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2996 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2997 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2998 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2999 pr_err("event_inj: %08x\n", control->event_inj);
3000 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3001 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3002 pr_err("next_rip: %016llx\n", control->next_rip);
3003 pr_err("VMCB State Save Area:\n");
3004 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3005 save->es.selector, save->es.attrib,
3006 save->es.limit, save->es.base);
3007 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3008 save->cs.selector, save->cs.attrib,
3009 save->cs.limit, save->cs.base);
3010 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3011 save->ss.selector, save->ss.attrib,
3012 save->ss.limit, save->ss.base);
3013 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3014 save->ds.selector, save->ds.attrib,
3015 save->ds.limit, save->ds.base);
3016 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3017 save->fs.selector, save->fs.attrib,
3018 save->fs.limit, save->fs.base);
3019 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3020 save->gs.selector, save->gs.attrib,
3021 save->gs.limit, save->gs.base);
3022 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3023 save->gdtr.selector, save->gdtr.attrib,
3024 save->gdtr.limit, save->gdtr.base);
3025 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3026 save->ldtr.selector, save->ldtr.attrib,
3027 save->ldtr.limit, save->ldtr.base);
3028 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3029 save->idtr.selector, save->idtr.attrib,
3030 save->idtr.limit, save->idtr.base);
3031 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3032 save->tr.selector, save->tr.attrib,
3033 save->tr.limit, save->tr.base);
3034 pr_err("cpl: %d efer: %016llx\n",
3035 save->cpl, save->efer);
3036 pr_err("cr0: %016llx cr2: %016llx\n",
3037 save->cr0, save->cr2);
3038 pr_err("cr3: %016llx cr4: %016llx\n",
3039 save->cr3, save->cr4);
3040 pr_err("dr6: %016llx dr7: %016llx\n",
3041 save->dr6, save->dr7);
3042 pr_err("rip: %016llx rflags: %016llx\n",
3043 save->rip, save->rflags);
3044 pr_err("rsp: %016llx rax: %016llx\n",
3045 save->rsp, save->rax);
3046 pr_err("star: %016llx lstar: %016llx\n",
3047 save->star, save->lstar);
3048 pr_err("cstar: %016llx sfmask: %016llx\n",
3049 save->cstar, save->sfmask);
3050 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3051 save->kernel_gs_base, save->sysenter_cs);
3052 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3053 save->sysenter_esp, save->sysenter_eip);
3054 pr_err("gpat: %016llx dbgctl: %016llx\n",
3055 save->g_pat, save->dbgctl);
3056 pr_err("br_from: %016llx br_to: %016llx\n",
3057 save->br_from, save->br_to);
3058 pr_err("excp_from: %016llx excp_to: %016llx\n",
3059 save->last_excp_from, save->last_excp_to);
3060
3061 }
3062
3063 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3064 {
3065 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3066
3067 *info1 = control->exit_info_1;
3068 *info2 = control->exit_info_2;
3069 }
3070
3071 static int handle_exit(struct kvm_vcpu *vcpu)
3072 {
3073 struct vcpu_svm *svm = to_svm(vcpu);
3074 struct kvm_run *kvm_run = vcpu->run;
3075 u32 exit_code = svm->vmcb->control.exit_code;
3076
3077 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3078
3079 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3080 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3081 if (npt_enabled)
3082 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3083
3084 if (unlikely(svm->nested.exit_required)) {
3085 nested_svm_vmexit(svm);
3086 svm->nested.exit_required = false;
3087
3088 return 1;
3089 }
3090
3091 if (is_guest_mode(vcpu)) {
3092 int vmexit;
3093
3094 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3095 svm->vmcb->control.exit_info_1,
3096 svm->vmcb->control.exit_info_2,
3097 svm->vmcb->control.exit_int_info,
3098 svm->vmcb->control.exit_int_info_err);
3099
3100 vmexit = nested_svm_exit_special(svm);
3101
3102 if (vmexit == NESTED_EXIT_CONTINUE)
3103 vmexit = nested_svm_exit_handled(svm);
3104
3105 if (vmexit == NESTED_EXIT_DONE)
3106 return 1;
3107 }
3108
3109 svm_complete_interrupts(svm);
3110
3111 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3112 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3113 kvm_run->fail_entry.hardware_entry_failure_reason
3114 = svm->vmcb->control.exit_code;
3115 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3116 dump_vmcb(vcpu);
3117 return 0;
3118 }
3119
3120 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3121 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3122 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3123 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3124 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3125 "exit_code 0x%x\n",
3126 __func__, svm->vmcb->control.exit_int_info,
3127 exit_code);
3128
3129 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3130 || !svm_exit_handlers[exit_code]) {
3131 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3132 kvm_run->hw.hardware_exit_reason = exit_code;
3133 return 0;
3134 }
3135
3136 return svm_exit_handlers[exit_code](svm);
3137 }
3138
3139 static void reload_tss(struct kvm_vcpu *vcpu)
3140 {
3141 int cpu = raw_smp_processor_id();
3142
3143 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3144 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3145 load_TR_desc();
3146 }
3147
3148 static void pre_svm_run(struct vcpu_svm *svm)
3149 {
3150 int cpu = raw_smp_processor_id();
3151
3152 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3153
3154 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3155 /* FIXME: handle wraparound of asid_generation */
3156 if (svm->asid_generation != sd->asid_generation)
3157 new_asid(svm, sd);
3158 }
3159
3160 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3161 {
3162 struct vcpu_svm *svm = to_svm(vcpu);
3163
3164 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3165 vcpu->arch.hflags |= HF_NMI_MASK;
3166 set_intercept(svm, INTERCEPT_IRET);
3167 ++vcpu->stat.nmi_injections;
3168 }
3169
3170 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3171 {
3172 struct vmcb_control_area *control;
3173
3174 control = &svm->vmcb->control;
3175 control->int_vector = irq;
3176 control->int_ctl &= ~V_INTR_PRIO_MASK;
3177 control->int_ctl |= V_IRQ_MASK |
3178 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3179 mark_dirty(svm->vmcb, VMCB_INTR);
3180 }
3181
3182 static void svm_set_irq(struct kvm_vcpu *vcpu)
3183 {
3184 struct vcpu_svm *svm = to_svm(vcpu);
3185
3186 BUG_ON(!(gif_set(svm)));
3187
3188 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3189 ++vcpu->stat.irq_injections;
3190
3191 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3192 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3193 }
3194
3195 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3196 {
3197 struct vcpu_svm *svm = to_svm(vcpu);
3198
3199 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3200 return;
3201
3202 if (irr == -1)
3203 return;
3204
3205 if (tpr >= irr)
3206 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3207 }
3208
3209 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3210 {
3211 struct vcpu_svm *svm = to_svm(vcpu);
3212 struct vmcb *vmcb = svm->vmcb;
3213 int ret;
3214 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3215 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3216 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3217
3218 return ret;
3219 }
3220
3221 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3222 {
3223 struct vcpu_svm *svm = to_svm(vcpu);
3224
3225 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3226 }
3227
3228 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3229 {
3230 struct vcpu_svm *svm = to_svm(vcpu);
3231
3232 if (masked) {
3233 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3234 set_intercept(svm, INTERCEPT_IRET);
3235 } else {
3236 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3237 clr_intercept(svm, INTERCEPT_IRET);
3238 }
3239 }
3240
3241 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3242 {
3243 struct vcpu_svm *svm = to_svm(vcpu);
3244 struct vmcb *vmcb = svm->vmcb;
3245 int ret;
3246
3247 if (!gif_set(svm) ||
3248 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3249 return 0;
3250
3251 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3252
3253 if (is_guest_mode(vcpu))
3254 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3255
3256 return ret;
3257 }
3258
3259 static void enable_irq_window(struct kvm_vcpu *vcpu)
3260 {
3261 struct vcpu_svm *svm = to_svm(vcpu);
3262
3263 /*
3264 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3265 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3266 * get that intercept, this function will be called again though and
3267 * we'll get the vintr intercept.
3268 */
3269 if (gif_set(svm) && nested_svm_intr(svm)) {
3270 svm_set_vintr(svm);
3271 svm_inject_irq(svm, 0x0);
3272 }
3273 }
3274
3275 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3276 {
3277 struct vcpu_svm *svm = to_svm(vcpu);
3278
3279 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3280 == HF_NMI_MASK)
3281 return; /* IRET will cause a vm exit */
3282
3283 /*
3284 * Something prevents NMI from been injected. Single step over possible
3285 * problem (IRET or exception injection or interrupt shadow)
3286 */
3287 svm->nmi_singlestep = true;
3288 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3289 update_db_intercept(vcpu);
3290 }
3291
3292 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3293 {
3294 return 0;
3295 }
3296
3297 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3298 {
3299 force_new_asid(vcpu);
3300 }
3301
3302 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3303 {
3304 }
3305
3306 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3307 {
3308 struct vcpu_svm *svm = to_svm(vcpu);
3309
3310 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3311 return;
3312
3313 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3314 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3315 kvm_set_cr8(vcpu, cr8);
3316 }
3317 }
3318
3319 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3320 {
3321 struct vcpu_svm *svm = to_svm(vcpu);
3322 u64 cr8;
3323
3324 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3325 return;
3326
3327 cr8 = kvm_get_cr8(vcpu);
3328 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3329 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3330 }
3331
3332 static void svm_complete_interrupts(struct vcpu_svm *svm)
3333 {
3334 u8 vector;
3335 int type;
3336 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3337 unsigned int3_injected = svm->int3_injected;
3338
3339 svm->int3_injected = 0;
3340
3341 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3342 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3343 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3344 }
3345
3346 svm->vcpu.arch.nmi_injected = false;
3347 kvm_clear_exception_queue(&svm->vcpu);
3348 kvm_clear_interrupt_queue(&svm->vcpu);
3349
3350 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3351 return;
3352
3353 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3354
3355 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3356 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3357
3358 switch (type) {
3359 case SVM_EXITINTINFO_TYPE_NMI:
3360 svm->vcpu.arch.nmi_injected = true;
3361 break;
3362 case SVM_EXITINTINFO_TYPE_EXEPT:
3363 /*
3364 * In case of software exceptions, do not reinject the vector,
3365 * but re-execute the instruction instead. Rewind RIP first
3366 * if we emulated INT3 before.
3367 */
3368 if (kvm_exception_is_soft(vector)) {
3369 if (vector == BP_VECTOR && int3_injected &&
3370 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3371 kvm_rip_write(&svm->vcpu,
3372 kvm_rip_read(&svm->vcpu) -
3373 int3_injected);
3374 break;
3375 }
3376 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3377 u32 err = svm->vmcb->control.exit_int_info_err;
3378 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3379
3380 } else
3381 kvm_requeue_exception(&svm->vcpu, vector);
3382 break;
3383 case SVM_EXITINTINFO_TYPE_INTR:
3384 kvm_queue_interrupt(&svm->vcpu, vector, false);
3385 break;
3386 default:
3387 break;
3388 }
3389 }
3390
3391 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3392 {
3393 struct vcpu_svm *svm = to_svm(vcpu);
3394 struct vmcb_control_area *control = &svm->vmcb->control;
3395
3396 control->exit_int_info = control->event_inj;
3397 control->exit_int_info_err = control->event_inj_err;
3398 control->event_inj = 0;
3399 svm_complete_interrupts(svm);
3400 }
3401
3402 #ifdef CONFIG_X86_64
3403 #define R "r"
3404 #else
3405 #define R "e"
3406 #endif
3407
3408 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3409 {
3410 struct vcpu_svm *svm = to_svm(vcpu);
3411
3412 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3413 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3414 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3415
3416 /*
3417 * A vmexit emulation is required before the vcpu can be executed
3418 * again.
3419 */
3420 if (unlikely(svm->nested.exit_required))
3421 return;
3422
3423 pre_svm_run(svm);
3424
3425 sync_lapic_to_cr8(vcpu);
3426
3427 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3428
3429 clgi();
3430
3431 local_irq_enable();
3432
3433 asm volatile (
3434 "push %%"R"bp; \n\t"
3435 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3436 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3437 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3438 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3439 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3440 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3441 #ifdef CONFIG_X86_64
3442 "mov %c[r8](%[svm]), %%r8 \n\t"
3443 "mov %c[r9](%[svm]), %%r9 \n\t"
3444 "mov %c[r10](%[svm]), %%r10 \n\t"
3445 "mov %c[r11](%[svm]), %%r11 \n\t"
3446 "mov %c[r12](%[svm]), %%r12 \n\t"
3447 "mov %c[r13](%[svm]), %%r13 \n\t"
3448 "mov %c[r14](%[svm]), %%r14 \n\t"
3449 "mov %c[r15](%[svm]), %%r15 \n\t"
3450 #endif
3451
3452 /* Enter guest mode */
3453 "push %%"R"ax \n\t"
3454 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3455 __ex(SVM_VMLOAD) "\n\t"
3456 __ex(SVM_VMRUN) "\n\t"
3457 __ex(SVM_VMSAVE) "\n\t"
3458 "pop %%"R"ax \n\t"
3459
3460 /* Save guest registers, load host registers */
3461 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3462 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3463 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3464 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3465 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3466 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3467 #ifdef CONFIG_X86_64
3468 "mov %%r8, %c[r8](%[svm]) \n\t"
3469 "mov %%r9, %c[r9](%[svm]) \n\t"
3470 "mov %%r10, %c[r10](%[svm]) \n\t"
3471 "mov %%r11, %c[r11](%[svm]) \n\t"
3472 "mov %%r12, %c[r12](%[svm]) \n\t"
3473 "mov %%r13, %c[r13](%[svm]) \n\t"
3474 "mov %%r14, %c[r14](%[svm]) \n\t"
3475 "mov %%r15, %c[r15](%[svm]) \n\t"
3476 #endif
3477 "pop %%"R"bp"
3478 :
3479 : [svm]"a"(svm),
3480 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3481 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3482 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3483 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3484 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3485 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3486 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3487 #ifdef CONFIG_X86_64
3488 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3489 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3490 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3491 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3492 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3493 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3494 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3495 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3496 #endif
3497 : "cc", "memory"
3498 , R"bx", R"cx", R"dx", R"si", R"di"
3499 #ifdef CONFIG_X86_64
3500 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3501 #endif
3502 );
3503
3504 #ifdef CONFIG_X86_64
3505 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3506 #else
3507 loadsegment(fs, svm->host.fs);
3508 #endif
3509
3510 reload_tss(vcpu);
3511
3512 local_irq_disable();
3513
3514 stgi();
3515
3516 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3517 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3518 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3519 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3520
3521 sync_cr8_to_lapic(vcpu);
3522
3523 svm->next_rip = 0;
3524
3525 /* if exit due to PF check for async PF */
3526 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3527 svm->apf_reason = kvm_read_and_reset_pf_reason();
3528
3529 if (npt_enabled) {
3530 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3531 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3532 }
3533
3534 /*
3535 * We need to handle MC intercepts here before the vcpu has a chance to
3536 * change the physical cpu
3537 */
3538 if (unlikely(svm->vmcb->control.exit_code ==
3539 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3540 svm_handle_mce(svm);
3541
3542 mark_all_clean(svm->vmcb);
3543 }
3544
3545 #undef R
3546
3547 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3548 {
3549 struct vcpu_svm *svm = to_svm(vcpu);
3550
3551 svm->vmcb->save.cr3 = root;
3552 force_new_asid(vcpu);
3553 }
3554
3555 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3556 {
3557 struct vcpu_svm *svm = to_svm(vcpu);
3558
3559 svm->vmcb->control.nested_cr3 = root;
3560 mark_dirty(svm->vmcb, VMCB_NPT);
3561
3562 /* Also sync guest cr3 here in case we live migrate */
3563 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3564
3565 force_new_asid(vcpu);
3566 }
3567
3568 static int is_disabled(void)
3569 {
3570 u64 vm_cr;
3571
3572 rdmsrl(MSR_VM_CR, vm_cr);
3573 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3574 return 1;
3575
3576 return 0;
3577 }
3578
3579 static void
3580 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3581 {
3582 /*
3583 * Patch in the VMMCALL instruction:
3584 */
3585 hypercall[0] = 0x0f;
3586 hypercall[1] = 0x01;
3587 hypercall[2] = 0xd9;
3588 }
3589
3590 static void svm_check_processor_compat(void *rtn)
3591 {
3592 *(int *)rtn = 0;
3593 }
3594
3595 static bool svm_cpu_has_accelerated_tpr(void)
3596 {
3597 return false;
3598 }
3599
3600 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3601 {
3602 return 0;
3603 }
3604
3605 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3606 {
3607 }
3608
3609 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3610 {
3611 switch (func) {
3612 case 0x00000001:
3613 /* Mask out xsave bit as long as it is not supported by SVM */
3614 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3615 break;
3616 case 0x80000001:
3617 if (nested)
3618 entry->ecx |= (1 << 2); /* Set SVM bit */
3619 break;
3620 case 0x8000000A:
3621 entry->eax = 1; /* SVM revision 1 */
3622 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3623 ASID emulation to nested SVM */
3624 entry->ecx = 0; /* Reserved */
3625 entry->edx = 0; /* Per default do not support any
3626 additional features */
3627
3628 /* Support next_rip if host supports it */
3629 if (boot_cpu_has(X86_FEATURE_NRIPS))
3630 entry->edx |= SVM_FEATURE_NRIP;
3631
3632 /* Support NPT for the guest if enabled */
3633 if (npt_enabled)
3634 entry->edx |= SVM_FEATURE_NPT;
3635
3636 break;
3637 }
3638 }
3639
3640 static const struct trace_print_flags svm_exit_reasons_str[] = {
3641 { SVM_EXIT_READ_CR0, "read_cr0" },
3642 { SVM_EXIT_READ_CR3, "read_cr3" },
3643 { SVM_EXIT_READ_CR4, "read_cr4" },
3644 { SVM_EXIT_READ_CR8, "read_cr8" },
3645 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3646 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3647 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3648 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3649 { SVM_EXIT_READ_DR0, "read_dr0" },
3650 { SVM_EXIT_READ_DR1, "read_dr1" },
3651 { SVM_EXIT_READ_DR2, "read_dr2" },
3652 { SVM_EXIT_READ_DR3, "read_dr3" },
3653 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3654 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3655 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3656 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3657 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3658 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3659 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3660 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3661 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3662 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3663 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3664 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3665 { SVM_EXIT_INTR, "interrupt" },
3666 { SVM_EXIT_NMI, "nmi" },
3667 { SVM_EXIT_SMI, "smi" },
3668 { SVM_EXIT_INIT, "init" },
3669 { SVM_EXIT_VINTR, "vintr" },
3670 { SVM_EXIT_CPUID, "cpuid" },
3671 { SVM_EXIT_INVD, "invd" },
3672 { SVM_EXIT_HLT, "hlt" },
3673 { SVM_EXIT_INVLPG, "invlpg" },
3674 { SVM_EXIT_INVLPGA, "invlpga" },
3675 { SVM_EXIT_IOIO, "io" },
3676 { SVM_EXIT_MSR, "msr" },
3677 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3678 { SVM_EXIT_SHUTDOWN, "shutdown" },
3679 { SVM_EXIT_VMRUN, "vmrun" },
3680 { SVM_EXIT_VMMCALL, "hypercall" },
3681 { SVM_EXIT_VMLOAD, "vmload" },
3682 { SVM_EXIT_VMSAVE, "vmsave" },
3683 { SVM_EXIT_STGI, "stgi" },
3684 { SVM_EXIT_CLGI, "clgi" },
3685 { SVM_EXIT_SKINIT, "skinit" },
3686 { SVM_EXIT_WBINVD, "wbinvd" },
3687 { SVM_EXIT_MONITOR, "monitor" },
3688 { SVM_EXIT_MWAIT, "mwait" },
3689 { SVM_EXIT_NPF, "npf" },
3690 { -1, NULL }
3691 };
3692
3693 static int svm_get_lpage_level(void)
3694 {
3695 return PT_PDPE_LEVEL;
3696 }
3697
3698 static bool svm_rdtscp_supported(void)
3699 {
3700 return false;
3701 }
3702
3703 static bool svm_has_wbinvd_exit(void)
3704 {
3705 return true;
3706 }
3707
3708 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3709 {
3710 struct vcpu_svm *svm = to_svm(vcpu);
3711
3712 set_exception_intercept(svm, NM_VECTOR);
3713 update_cr0_intercept(svm);
3714 }
3715
3716 static struct kvm_x86_ops svm_x86_ops = {
3717 .cpu_has_kvm_support = has_svm,
3718 .disabled_by_bios = is_disabled,
3719 .hardware_setup = svm_hardware_setup,
3720 .hardware_unsetup = svm_hardware_unsetup,
3721 .check_processor_compatibility = svm_check_processor_compat,
3722 .hardware_enable = svm_hardware_enable,
3723 .hardware_disable = svm_hardware_disable,
3724 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3725
3726 .vcpu_create = svm_create_vcpu,
3727 .vcpu_free = svm_free_vcpu,
3728 .vcpu_reset = svm_vcpu_reset,
3729
3730 .prepare_guest_switch = svm_prepare_guest_switch,
3731 .vcpu_load = svm_vcpu_load,
3732 .vcpu_put = svm_vcpu_put,
3733
3734 .set_guest_debug = svm_guest_debug,
3735 .get_msr = svm_get_msr,
3736 .set_msr = svm_set_msr,
3737 .get_segment_base = svm_get_segment_base,
3738 .get_segment = svm_get_segment,
3739 .set_segment = svm_set_segment,
3740 .get_cpl = svm_get_cpl,
3741 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3742 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3743 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3744 .set_cr0 = svm_set_cr0,
3745 .set_cr3 = svm_set_cr3,
3746 .set_cr4 = svm_set_cr4,
3747 .set_efer = svm_set_efer,
3748 .get_idt = svm_get_idt,
3749 .set_idt = svm_set_idt,
3750 .get_gdt = svm_get_gdt,
3751 .set_gdt = svm_set_gdt,
3752 .set_dr7 = svm_set_dr7,
3753 .cache_reg = svm_cache_reg,
3754 .get_rflags = svm_get_rflags,
3755 .set_rflags = svm_set_rflags,
3756 .fpu_activate = svm_fpu_activate,
3757 .fpu_deactivate = svm_fpu_deactivate,
3758
3759 .tlb_flush = svm_flush_tlb,
3760
3761 .run = svm_vcpu_run,
3762 .handle_exit = handle_exit,
3763 .skip_emulated_instruction = skip_emulated_instruction,
3764 .set_interrupt_shadow = svm_set_interrupt_shadow,
3765 .get_interrupt_shadow = svm_get_interrupt_shadow,
3766 .patch_hypercall = svm_patch_hypercall,
3767 .set_irq = svm_set_irq,
3768 .set_nmi = svm_inject_nmi,
3769 .queue_exception = svm_queue_exception,
3770 .cancel_injection = svm_cancel_injection,
3771 .interrupt_allowed = svm_interrupt_allowed,
3772 .nmi_allowed = svm_nmi_allowed,
3773 .get_nmi_mask = svm_get_nmi_mask,
3774 .set_nmi_mask = svm_set_nmi_mask,
3775 .enable_nmi_window = enable_nmi_window,
3776 .enable_irq_window = enable_irq_window,
3777 .update_cr8_intercept = update_cr8_intercept,
3778
3779 .set_tss_addr = svm_set_tss_addr,
3780 .get_tdp_level = get_npt_level,
3781 .get_mt_mask = svm_get_mt_mask,
3782
3783 .get_exit_info = svm_get_exit_info,
3784 .exit_reasons_str = svm_exit_reasons_str,
3785
3786 .get_lpage_level = svm_get_lpage_level,
3787
3788 .cpuid_update = svm_cpuid_update,
3789
3790 .rdtscp_supported = svm_rdtscp_supported,
3791
3792 .set_supported_cpuid = svm_set_supported_cpuid,
3793
3794 .has_wbinvd_exit = svm_has_wbinvd_exit,
3795
3796 .write_tsc_offset = svm_write_tsc_offset,
3797 .adjust_tsc_offset = svm_adjust_tsc_offset,
3798
3799 .set_tdp_cr3 = set_tdp_cr3,
3800 };
3801
3802 static int __init svm_init(void)
3803 {
3804 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3805 __alignof__(struct vcpu_svm), THIS_MODULE);
3806 }
3807
3808 static void __exit svm_exit(void)
3809 {
3810 kvm_exit();
3811 }
3812
3813 module_init(svm_init)
3814 module_exit(svm_exit)
Linux kernel - Deliverables
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