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KVM: SVM: Add clean-bit for LBR state
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_CR, /* CR0, CR3, CR4, EFER */
196 VMCB_DR, /* DR6, DR7 */
197 VMCB_DT, /* GDT, IDT */
198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
199 VMCB_CR2, /* CR2 only */
200 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
201 VMCB_DIRTY_MAX,
202 };
203
204 /* TPR and CR2 are always written before VMRUN */
205 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
206
207 static inline void mark_all_dirty(struct vmcb *vmcb)
208 {
209 vmcb->control.clean = 0;
210 }
211
212 static inline void mark_all_clean(struct vmcb *vmcb)
213 {
214 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
215 & ~VMCB_ALWAYS_DIRTY_MASK;
216 }
217
218 static inline void mark_dirty(struct vmcb *vmcb, int bit)
219 {
220 vmcb->control.clean &= ~(1 << bit);
221 }
222
223 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
224 {
225 return container_of(vcpu, struct vcpu_svm, vcpu);
226 }
227
228 static void recalc_intercepts(struct vcpu_svm *svm)
229 {
230 struct vmcb_control_area *c, *h;
231 struct nested_state *g;
232
233 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
234
235 if (!is_guest_mode(&svm->vcpu))
236 return;
237
238 c = &svm->vmcb->control;
239 h = &svm->nested.hsave->control;
240 g = &svm->nested;
241
242 c->intercept_cr = h->intercept_cr | g->intercept_cr;
243 c->intercept_dr = h->intercept_dr | g->intercept_dr;
244 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
245 c->intercept = h->intercept | g->intercept;
246 }
247
248 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
249 {
250 if (is_guest_mode(&svm->vcpu))
251 return svm->nested.hsave;
252 else
253 return svm->vmcb;
254 }
255
256 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
257 {
258 struct vmcb *vmcb = get_host_vmcb(svm);
259
260 vmcb->control.intercept_cr |= (1U << bit);
261
262 recalc_intercepts(svm);
263 }
264
265 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
266 {
267 struct vmcb *vmcb = get_host_vmcb(svm);
268
269 vmcb->control.intercept_cr &= ~(1U << bit);
270
271 recalc_intercepts(svm);
272 }
273
274 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
275 {
276 struct vmcb *vmcb = get_host_vmcb(svm);
277
278 return vmcb->control.intercept_cr & (1U << bit);
279 }
280
281 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_dr |= (1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_dr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297 }
298
299 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
300 {
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 vmcb->control.intercept_exceptions |= (1U << bit);
304
305 recalc_intercepts(svm);
306 }
307
308 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
309 {
310 struct vmcb *vmcb = get_host_vmcb(svm);
311
312 vmcb->control.intercept_exceptions &= ~(1U << bit);
313
314 recalc_intercepts(svm);
315 }
316
317 static inline void set_intercept(struct vcpu_svm *svm, int bit)
318 {
319 struct vmcb *vmcb = get_host_vmcb(svm);
320
321 vmcb->control.intercept |= (1ULL << bit);
322
323 recalc_intercepts(svm);
324 }
325
326 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
327 {
328 struct vmcb *vmcb = get_host_vmcb(svm);
329
330 vmcb->control.intercept &= ~(1ULL << bit);
331
332 recalc_intercepts(svm);
333 }
334
335 static inline void enable_gif(struct vcpu_svm *svm)
336 {
337 svm->vcpu.arch.hflags |= HF_GIF_MASK;
338 }
339
340 static inline void disable_gif(struct vcpu_svm *svm)
341 {
342 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
343 }
344
345 static inline bool gif_set(struct vcpu_svm *svm)
346 {
347 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
348 }
349
350 static unsigned long iopm_base;
351
352 struct kvm_ldttss_desc {
353 u16 limit0;
354 u16 base0;
355 unsigned base1:8, type:5, dpl:2, p:1;
356 unsigned limit1:4, zero0:3, g:1, base2:8;
357 u32 base3;
358 u32 zero1;
359 } __attribute__((packed));
360
361 struct svm_cpu_data {
362 int cpu;
363
364 u64 asid_generation;
365 u32 max_asid;
366 u32 next_asid;
367 struct kvm_ldttss_desc *tss_desc;
368
369 struct page *save_area;
370 };
371
372 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
373 static uint32_t svm_features;
374
375 struct svm_init_data {
376 int cpu;
377 int r;
378 };
379
380 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
381
382 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
383 #define MSRS_RANGE_SIZE 2048
384 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
385
386 static u32 svm_msrpm_offset(u32 msr)
387 {
388 u32 offset;
389 int i;
390
391 for (i = 0; i < NUM_MSR_MAPS; i++) {
392 if (msr < msrpm_ranges[i] ||
393 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
394 continue;
395
396 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
397 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
398
399 /* Now we have the u8 offset - but need the u32 offset */
400 return offset / 4;
401 }
402
403 /* MSR not in any range */
404 return MSR_INVALID;
405 }
406
407 #define MAX_INST_SIZE 15
408
409 static inline void clgi(void)
410 {
411 asm volatile (__ex(SVM_CLGI));
412 }
413
414 static inline void stgi(void)
415 {
416 asm volatile (__ex(SVM_STGI));
417 }
418
419 static inline void invlpga(unsigned long addr, u32 asid)
420 {
421 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
422 }
423
424 static inline void force_new_asid(struct kvm_vcpu *vcpu)
425 {
426 to_svm(vcpu)->asid_generation--;
427 }
428
429 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
430 {
431 force_new_asid(vcpu);
432 }
433
434 static int get_npt_level(void)
435 {
436 #ifdef CONFIG_X86_64
437 return PT64_ROOT_LEVEL;
438 #else
439 return PT32E_ROOT_LEVEL;
440 #endif
441 }
442
443 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
444 {
445 vcpu->arch.efer = efer;
446 if (!npt_enabled && !(efer & EFER_LMA))
447 efer &= ~EFER_LME;
448
449 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
450 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
451 }
452
453 static int is_external_interrupt(u32 info)
454 {
455 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
456 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
457 }
458
459 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
460 {
461 struct vcpu_svm *svm = to_svm(vcpu);
462 u32 ret = 0;
463
464 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
465 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
466 return ret & mask;
467 }
468
469 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
470 {
471 struct vcpu_svm *svm = to_svm(vcpu);
472
473 if (mask == 0)
474 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
475 else
476 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
477
478 }
479
480 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
481 {
482 struct vcpu_svm *svm = to_svm(vcpu);
483
484 if (svm->vmcb->control.next_rip != 0)
485 svm->next_rip = svm->vmcb->control.next_rip;
486
487 if (!svm->next_rip) {
488 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
489 EMULATE_DONE)
490 printk(KERN_DEBUG "%s: NOP\n", __func__);
491 return;
492 }
493 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
494 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
495 __func__, kvm_rip_read(vcpu), svm->next_rip);
496
497 kvm_rip_write(vcpu, svm->next_rip);
498 svm_set_interrupt_shadow(vcpu, 0);
499 }
500
501 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
502 bool has_error_code, u32 error_code,
503 bool reinject)
504 {
505 struct vcpu_svm *svm = to_svm(vcpu);
506
507 /*
508 * If we are within a nested VM we'd better #VMEXIT and let the guest
509 * handle the exception
510 */
511 if (!reinject &&
512 nested_svm_check_exception(svm, nr, has_error_code, error_code))
513 return;
514
515 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
516 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
517
518 /*
519 * For guest debugging where we have to reinject #BP if some
520 * INT3 is guest-owned:
521 * Emulate nRIP by moving RIP forward. Will fail if injection
522 * raises a fault that is not intercepted. Still better than
523 * failing in all cases.
524 */
525 skip_emulated_instruction(&svm->vcpu);
526 rip = kvm_rip_read(&svm->vcpu);
527 svm->int3_rip = rip + svm->vmcb->save.cs.base;
528 svm->int3_injected = rip - old_rip;
529 }
530
531 svm->vmcb->control.event_inj = nr
532 | SVM_EVTINJ_VALID
533 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
534 | SVM_EVTINJ_TYPE_EXEPT;
535 svm->vmcb->control.event_inj_err = error_code;
536 }
537
538 static void svm_init_erratum_383(void)
539 {
540 u32 low, high;
541 int err;
542 u64 val;
543
544 if (!cpu_has_amd_erratum(amd_erratum_383))
545 return;
546
547 /* Use _safe variants to not break nested virtualization */
548 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
549 if (err)
550 return;
551
552 val |= (1ULL << 47);
553
554 low = lower_32_bits(val);
555 high = upper_32_bits(val);
556
557 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
558
559 erratum_383_found = true;
560 }
561
562 static int has_svm(void)
563 {
564 const char *msg;
565
566 if (!cpu_has_svm(&msg)) {
567 printk(KERN_INFO "has_svm: %s\n", msg);
568 return 0;
569 }
570
571 return 1;
572 }
573
574 static void svm_hardware_disable(void *garbage)
575 {
576 cpu_svm_disable();
577 }
578
579 static int svm_hardware_enable(void *garbage)
580 {
581
582 struct svm_cpu_data *sd;
583 uint64_t efer;
584 struct desc_ptr gdt_descr;
585 struct desc_struct *gdt;
586 int me = raw_smp_processor_id();
587
588 rdmsrl(MSR_EFER, efer);
589 if (efer & EFER_SVME)
590 return -EBUSY;
591
592 if (!has_svm()) {
593 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
594 me);
595 return -EINVAL;
596 }
597 sd = per_cpu(svm_data, me);
598
599 if (!sd) {
600 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
601 me);
602 return -EINVAL;
603 }
604
605 sd->asid_generation = 1;
606 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
607 sd->next_asid = sd->max_asid + 1;
608
609 native_store_gdt(&gdt_descr);
610 gdt = (struct desc_struct *)gdt_descr.address;
611 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
612
613 wrmsrl(MSR_EFER, efer | EFER_SVME);
614
615 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
616
617 svm_init_erratum_383();
618
619 return 0;
620 }
621
622 static void svm_cpu_uninit(int cpu)
623 {
624 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
625
626 if (!sd)
627 return;
628
629 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
630 __free_page(sd->save_area);
631 kfree(sd);
632 }
633
634 static int svm_cpu_init(int cpu)
635 {
636 struct svm_cpu_data *sd;
637 int r;
638
639 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
640 if (!sd)
641 return -ENOMEM;
642 sd->cpu = cpu;
643 sd->save_area = alloc_page(GFP_KERNEL);
644 r = -ENOMEM;
645 if (!sd->save_area)
646 goto err_1;
647
648 per_cpu(svm_data, cpu) = sd;
649
650 return 0;
651
652 err_1:
653 kfree(sd);
654 return r;
655
656 }
657
658 static bool valid_msr_intercept(u32 index)
659 {
660 int i;
661
662 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
663 if (direct_access_msrs[i].index == index)
664 return true;
665
666 return false;
667 }
668
669 static void set_msr_interception(u32 *msrpm, unsigned msr,
670 int read, int write)
671 {
672 u8 bit_read, bit_write;
673 unsigned long tmp;
674 u32 offset;
675
676 /*
677 * If this warning triggers extend the direct_access_msrs list at the
678 * beginning of the file
679 */
680 WARN_ON(!valid_msr_intercept(msr));
681
682 offset = svm_msrpm_offset(msr);
683 bit_read = 2 * (msr & 0x0f);
684 bit_write = 2 * (msr & 0x0f) + 1;
685 tmp = msrpm[offset];
686
687 BUG_ON(offset == MSR_INVALID);
688
689 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
690 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
691
692 msrpm[offset] = tmp;
693 }
694
695 static void svm_vcpu_init_msrpm(u32 *msrpm)
696 {
697 int i;
698
699 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
700
701 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
702 if (!direct_access_msrs[i].always)
703 continue;
704
705 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
706 }
707 }
708
709 static void add_msr_offset(u32 offset)
710 {
711 int i;
712
713 for (i = 0; i < MSRPM_OFFSETS; ++i) {
714
715 /* Offset already in list? */
716 if (msrpm_offsets[i] == offset)
717 return;
718
719 /* Slot used by another offset? */
720 if (msrpm_offsets[i] != MSR_INVALID)
721 continue;
722
723 /* Add offset to list */
724 msrpm_offsets[i] = offset;
725
726 return;
727 }
728
729 /*
730 * If this BUG triggers the msrpm_offsets table has an overflow. Just
731 * increase MSRPM_OFFSETS in this case.
732 */
733 BUG();
734 }
735
736 static void init_msrpm_offsets(void)
737 {
738 int i;
739
740 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
741
742 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
743 u32 offset;
744
745 offset = svm_msrpm_offset(direct_access_msrs[i].index);
746 BUG_ON(offset == MSR_INVALID);
747
748 add_msr_offset(offset);
749 }
750 }
751
752 static void svm_enable_lbrv(struct vcpu_svm *svm)
753 {
754 u32 *msrpm = svm->msrpm;
755
756 svm->vmcb->control.lbr_ctl = 1;
757 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
758 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
759 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
760 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
761 }
762
763 static void svm_disable_lbrv(struct vcpu_svm *svm)
764 {
765 u32 *msrpm = svm->msrpm;
766
767 svm->vmcb->control.lbr_ctl = 0;
768 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
769 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
770 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
771 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
772 }
773
774 static __init int svm_hardware_setup(void)
775 {
776 int cpu;
777 struct page *iopm_pages;
778 void *iopm_va;
779 int r;
780
781 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
782
783 if (!iopm_pages)
784 return -ENOMEM;
785
786 iopm_va = page_address(iopm_pages);
787 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
788 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
789
790 init_msrpm_offsets();
791
792 if (boot_cpu_has(X86_FEATURE_NX))
793 kvm_enable_efer_bits(EFER_NX);
794
795 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
796 kvm_enable_efer_bits(EFER_FFXSR);
797
798 if (nested) {
799 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
800 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
801 }
802
803 for_each_possible_cpu(cpu) {
804 r = svm_cpu_init(cpu);
805 if (r)
806 goto err;
807 }
808
809 svm_features = cpuid_edx(SVM_CPUID_FUNC);
810
811 if (!boot_cpu_has(X86_FEATURE_NPT))
812 npt_enabled = false;
813
814 if (npt_enabled && !npt) {
815 printk(KERN_INFO "kvm: Nested Paging disabled\n");
816 npt_enabled = false;
817 }
818
819 if (npt_enabled) {
820 printk(KERN_INFO "kvm: Nested Paging enabled\n");
821 kvm_enable_tdp();
822 } else
823 kvm_disable_tdp();
824
825 return 0;
826
827 err:
828 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
829 iopm_base = 0;
830 return r;
831 }
832
833 static __exit void svm_hardware_unsetup(void)
834 {
835 int cpu;
836
837 for_each_possible_cpu(cpu)
838 svm_cpu_uninit(cpu);
839
840 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
841 iopm_base = 0;
842 }
843
844 static void init_seg(struct vmcb_seg *seg)
845 {
846 seg->selector = 0;
847 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
848 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
849 seg->limit = 0xffff;
850 seg->base = 0;
851 }
852
853 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
854 {
855 seg->selector = 0;
856 seg->attrib = SVM_SELECTOR_P_MASK | type;
857 seg->limit = 0xffff;
858 seg->base = 0;
859 }
860
861 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
862 {
863 struct vcpu_svm *svm = to_svm(vcpu);
864 u64 g_tsc_offset = 0;
865
866 if (is_guest_mode(vcpu)) {
867 g_tsc_offset = svm->vmcb->control.tsc_offset -
868 svm->nested.hsave->control.tsc_offset;
869 svm->nested.hsave->control.tsc_offset = offset;
870 }
871
872 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
873
874 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
875 }
876
877 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
878 {
879 struct vcpu_svm *svm = to_svm(vcpu);
880
881 svm->vmcb->control.tsc_offset += adjustment;
882 if (is_guest_mode(vcpu))
883 svm->nested.hsave->control.tsc_offset += adjustment;
884 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
885 }
886
887 static void init_vmcb(struct vcpu_svm *svm)
888 {
889 struct vmcb_control_area *control = &svm->vmcb->control;
890 struct vmcb_save_area *save = &svm->vmcb->save;
891
892 svm->vcpu.fpu_active = 1;
893 svm->vcpu.arch.hflags = 0;
894
895 set_cr_intercept(svm, INTERCEPT_CR0_READ);
896 set_cr_intercept(svm, INTERCEPT_CR3_READ);
897 set_cr_intercept(svm, INTERCEPT_CR4_READ);
898 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
899 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
900 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
901 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
902
903 set_dr_intercept(svm, INTERCEPT_DR0_READ);
904 set_dr_intercept(svm, INTERCEPT_DR1_READ);
905 set_dr_intercept(svm, INTERCEPT_DR2_READ);
906 set_dr_intercept(svm, INTERCEPT_DR3_READ);
907 set_dr_intercept(svm, INTERCEPT_DR4_READ);
908 set_dr_intercept(svm, INTERCEPT_DR5_READ);
909 set_dr_intercept(svm, INTERCEPT_DR6_READ);
910 set_dr_intercept(svm, INTERCEPT_DR7_READ);
911
912 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
914 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
915 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
916 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
917 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
918 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
919 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
920
921 set_exception_intercept(svm, PF_VECTOR);
922 set_exception_intercept(svm, UD_VECTOR);
923 set_exception_intercept(svm, MC_VECTOR);
924
925 set_intercept(svm, INTERCEPT_INTR);
926 set_intercept(svm, INTERCEPT_NMI);
927 set_intercept(svm, INTERCEPT_SMI);
928 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
929 set_intercept(svm, INTERCEPT_CPUID);
930 set_intercept(svm, INTERCEPT_INVD);
931 set_intercept(svm, INTERCEPT_HLT);
932 set_intercept(svm, INTERCEPT_INVLPG);
933 set_intercept(svm, INTERCEPT_INVLPGA);
934 set_intercept(svm, INTERCEPT_IOIO_PROT);
935 set_intercept(svm, INTERCEPT_MSR_PROT);
936 set_intercept(svm, INTERCEPT_TASK_SWITCH);
937 set_intercept(svm, INTERCEPT_SHUTDOWN);
938 set_intercept(svm, INTERCEPT_VMRUN);
939 set_intercept(svm, INTERCEPT_VMMCALL);
940 set_intercept(svm, INTERCEPT_VMLOAD);
941 set_intercept(svm, INTERCEPT_VMSAVE);
942 set_intercept(svm, INTERCEPT_STGI);
943 set_intercept(svm, INTERCEPT_CLGI);
944 set_intercept(svm, INTERCEPT_SKINIT);
945 set_intercept(svm, INTERCEPT_WBINVD);
946 set_intercept(svm, INTERCEPT_MONITOR);
947 set_intercept(svm, INTERCEPT_MWAIT);
948
949 control->iopm_base_pa = iopm_base;
950 control->msrpm_base_pa = __pa(svm->msrpm);
951 control->int_ctl = V_INTR_MASKING_MASK;
952
953 init_seg(&save->es);
954 init_seg(&save->ss);
955 init_seg(&save->ds);
956 init_seg(&save->fs);
957 init_seg(&save->gs);
958
959 save->cs.selector = 0xf000;
960 /* Executable/Readable Code Segment */
961 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
962 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
963 save->cs.limit = 0xffff;
964 /*
965 * cs.base should really be 0xffff0000, but vmx can't handle that, so
966 * be consistent with it.
967 *
968 * Replace when we have real mode working for vmx.
969 */
970 save->cs.base = 0xf0000;
971
972 save->gdtr.limit = 0xffff;
973 save->idtr.limit = 0xffff;
974
975 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
976 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
977
978 svm_set_efer(&svm->vcpu, 0);
979 save->dr6 = 0xffff0ff0;
980 save->dr7 = 0x400;
981 save->rflags = 2;
982 save->rip = 0x0000fff0;
983 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
984
985 /*
986 * This is the guest-visible cr0 value.
987 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
988 */
989 svm->vcpu.arch.cr0 = 0;
990 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
991
992 save->cr4 = X86_CR4_PAE;
993 /* rdx = ?? */
994
995 if (npt_enabled) {
996 /* Setup VMCB for Nested Paging */
997 control->nested_ctl = 1;
998 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
999 clr_intercept(svm, INTERCEPT_INVLPG);
1000 clr_exception_intercept(svm, PF_VECTOR);
1001 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1002 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1003 save->g_pat = 0x0007040600070406ULL;
1004 save->cr3 = 0;
1005 save->cr4 = 0;
1006 }
1007 force_new_asid(&svm->vcpu);
1008
1009 svm->nested.vmcb = 0;
1010 svm->vcpu.arch.hflags = 0;
1011
1012 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1013 control->pause_filter_count = 3000;
1014 set_intercept(svm, INTERCEPT_PAUSE);
1015 }
1016
1017 mark_all_dirty(svm->vmcb);
1018
1019 enable_gif(svm);
1020 }
1021
1022 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1023 {
1024 struct vcpu_svm *svm = to_svm(vcpu);
1025
1026 init_vmcb(svm);
1027
1028 if (!kvm_vcpu_is_bsp(vcpu)) {
1029 kvm_rip_write(vcpu, 0);
1030 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1031 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1032 }
1033 vcpu->arch.regs_avail = ~0;
1034 vcpu->arch.regs_dirty = ~0;
1035
1036 return 0;
1037 }
1038
1039 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1040 {
1041 struct vcpu_svm *svm;
1042 struct page *page;
1043 struct page *msrpm_pages;
1044 struct page *hsave_page;
1045 struct page *nested_msrpm_pages;
1046 int err;
1047
1048 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1049 if (!svm) {
1050 err = -ENOMEM;
1051 goto out;
1052 }
1053
1054 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1055 if (err)
1056 goto free_svm;
1057
1058 err = -ENOMEM;
1059 page = alloc_page(GFP_KERNEL);
1060 if (!page)
1061 goto uninit;
1062
1063 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1064 if (!msrpm_pages)
1065 goto free_page1;
1066
1067 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1068 if (!nested_msrpm_pages)
1069 goto free_page2;
1070
1071 hsave_page = alloc_page(GFP_KERNEL);
1072 if (!hsave_page)
1073 goto free_page3;
1074
1075 svm->nested.hsave = page_address(hsave_page);
1076
1077 svm->msrpm = page_address(msrpm_pages);
1078 svm_vcpu_init_msrpm(svm->msrpm);
1079
1080 svm->nested.msrpm = page_address(nested_msrpm_pages);
1081 svm_vcpu_init_msrpm(svm->nested.msrpm);
1082
1083 svm->vmcb = page_address(page);
1084 clear_page(svm->vmcb);
1085 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1086 svm->asid_generation = 0;
1087 init_vmcb(svm);
1088 kvm_write_tsc(&svm->vcpu, 0);
1089
1090 err = fx_init(&svm->vcpu);
1091 if (err)
1092 goto free_page4;
1093
1094 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1095 if (kvm_vcpu_is_bsp(&svm->vcpu))
1096 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1097
1098 return &svm->vcpu;
1099
1100 free_page4:
1101 __free_page(hsave_page);
1102 free_page3:
1103 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1104 free_page2:
1105 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1106 free_page1:
1107 __free_page(page);
1108 uninit:
1109 kvm_vcpu_uninit(&svm->vcpu);
1110 free_svm:
1111 kmem_cache_free(kvm_vcpu_cache, svm);
1112 out:
1113 return ERR_PTR(err);
1114 }
1115
1116 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1117 {
1118 struct vcpu_svm *svm = to_svm(vcpu);
1119
1120 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1121 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1122 __free_page(virt_to_page(svm->nested.hsave));
1123 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1124 kvm_vcpu_uninit(vcpu);
1125 kmem_cache_free(kvm_vcpu_cache, svm);
1126 }
1127
1128 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1129 {
1130 struct vcpu_svm *svm = to_svm(vcpu);
1131 int i;
1132
1133 if (unlikely(cpu != vcpu->cpu)) {
1134 svm->asid_generation = 0;
1135 mark_all_dirty(svm->vmcb);
1136 }
1137
1138 #ifdef CONFIG_X86_64
1139 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1140 #endif
1141 savesegment(fs, svm->host.fs);
1142 savesegment(gs, svm->host.gs);
1143 svm->host.ldt = kvm_read_ldt();
1144
1145 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1146 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1147 }
1148
1149 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1150 {
1151 struct vcpu_svm *svm = to_svm(vcpu);
1152 int i;
1153
1154 ++vcpu->stat.host_state_reload;
1155 kvm_load_ldt(svm->host.ldt);
1156 #ifdef CONFIG_X86_64
1157 loadsegment(fs, svm->host.fs);
1158 load_gs_index(svm->host.gs);
1159 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1160 #else
1161 loadsegment(gs, svm->host.gs);
1162 #endif
1163 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1164 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1165 }
1166
1167 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1168 {
1169 return to_svm(vcpu)->vmcb->save.rflags;
1170 }
1171
1172 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1173 {
1174 to_svm(vcpu)->vmcb->save.rflags = rflags;
1175 }
1176
1177 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1178 {
1179 switch (reg) {
1180 case VCPU_EXREG_PDPTR:
1181 BUG_ON(!npt_enabled);
1182 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1183 break;
1184 default:
1185 BUG();
1186 }
1187 }
1188
1189 static void svm_set_vintr(struct vcpu_svm *svm)
1190 {
1191 set_intercept(svm, INTERCEPT_VINTR);
1192 }
1193
1194 static void svm_clear_vintr(struct vcpu_svm *svm)
1195 {
1196 clr_intercept(svm, INTERCEPT_VINTR);
1197 }
1198
1199 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1200 {
1201 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1202
1203 switch (seg) {
1204 case VCPU_SREG_CS: return &save->cs;
1205 case VCPU_SREG_DS: return &save->ds;
1206 case VCPU_SREG_ES: return &save->es;
1207 case VCPU_SREG_FS: return &save->fs;
1208 case VCPU_SREG_GS: return &save->gs;
1209 case VCPU_SREG_SS: return &save->ss;
1210 case VCPU_SREG_TR: return &save->tr;
1211 case VCPU_SREG_LDTR: return &save->ldtr;
1212 }
1213 BUG();
1214 return NULL;
1215 }
1216
1217 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1218 {
1219 struct vmcb_seg *s = svm_seg(vcpu, seg);
1220
1221 return s->base;
1222 }
1223
1224 static void svm_get_segment(struct kvm_vcpu *vcpu,
1225 struct kvm_segment *var, int seg)
1226 {
1227 struct vmcb_seg *s = svm_seg(vcpu, seg);
1228
1229 var->base = s->base;
1230 var->limit = s->limit;
1231 var->selector = s->selector;
1232 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1233 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1234 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1235 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1236 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1237 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1238 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1239 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1240
1241 /*
1242 * AMD's VMCB does not have an explicit unusable field, so emulate it
1243 * for cross vendor migration purposes by "not present"
1244 */
1245 var->unusable = !var->present || (var->type == 0);
1246
1247 switch (seg) {
1248 case VCPU_SREG_CS:
1249 /*
1250 * SVM always stores 0 for the 'G' bit in the CS selector in
1251 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1252 * Intel's VMENTRY has a check on the 'G' bit.
1253 */
1254 var->g = s->limit > 0xfffff;
1255 break;
1256 case VCPU_SREG_TR:
1257 /*
1258 * Work around a bug where the busy flag in the tr selector
1259 * isn't exposed
1260 */
1261 var->type |= 0x2;
1262 break;
1263 case VCPU_SREG_DS:
1264 case VCPU_SREG_ES:
1265 case VCPU_SREG_FS:
1266 case VCPU_SREG_GS:
1267 /*
1268 * The accessed bit must always be set in the segment
1269 * descriptor cache, although it can be cleared in the
1270 * descriptor, the cached bit always remains at 1. Since
1271 * Intel has a check on this, set it here to support
1272 * cross-vendor migration.
1273 */
1274 if (!var->unusable)
1275 var->type |= 0x1;
1276 break;
1277 case VCPU_SREG_SS:
1278 /*
1279 * On AMD CPUs sometimes the DB bit in the segment
1280 * descriptor is left as 1, although the whole segment has
1281 * been made unusable. Clear it here to pass an Intel VMX
1282 * entry check when cross vendor migrating.
1283 */
1284 if (var->unusable)
1285 var->db = 0;
1286 break;
1287 }
1288 }
1289
1290 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1291 {
1292 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1293
1294 return save->cpl;
1295 }
1296
1297 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1298 {
1299 struct vcpu_svm *svm = to_svm(vcpu);
1300
1301 dt->size = svm->vmcb->save.idtr.limit;
1302 dt->address = svm->vmcb->save.idtr.base;
1303 }
1304
1305 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1306 {
1307 struct vcpu_svm *svm = to_svm(vcpu);
1308
1309 svm->vmcb->save.idtr.limit = dt->size;
1310 svm->vmcb->save.idtr.base = dt->address ;
1311 mark_dirty(svm->vmcb, VMCB_DT);
1312 }
1313
1314 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1315 {
1316 struct vcpu_svm *svm = to_svm(vcpu);
1317
1318 dt->size = svm->vmcb->save.gdtr.limit;
1319 dt->address = svm->vmcb->save.gdtr.base;
1320 }
1321
1322 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1323 {
1324 struct vcpu_svm *svm = to_svm(vcpu);
1325
1326 svm->vmcb->save.gdtr.limit = dt->size;
1327 svm->vmcb->save.gdtr.base = dt->address ;
1328 mark_dirty(svm->vmcb, VMCB_DT);
1329 }
1330
1331 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1332 {
1333 }
1334
1335 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1336 {
1337 }
1338
1339 static void update_cr0_intercept(struct vcpu_svm *svm)
1340 {
1341 ulong gcr0 = svm->vcpu.arch.cr0;
1342 u64 *hcr0 = &svm->vmcb->save.cr0;
1343
1344 if (!svm->vcpu.fpu_active)
1345 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1346 else
1347 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1348 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1349
1350 mark_dirty(svm->vmcb, VMCB_CR);
1351
1352 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1353 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1354 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1355 } else {
1356 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1357 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1358 }
1359 }
1360
1361 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1362 {
1363 struct vcpu_svm *svm = to_svm(vcpu);
1364
1365 if (is_guest_mode(vcpu)) {
1366 /*
1367 * We are here because we run in nested mode, the host kvm
1368 * intercepts cr0 writes but the l1 hypervisor does not.
1369 * But the L1 hypervisor may intercept selective cr0 writes.
1370 * This needs to be checked here.
1371 */
1372 unsigned long old, new;
1373
1374 /* Remove bits that would trigger a real cr0 write intercept */
1375 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1376 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1377
1378 if (old == new) {
1379 /* cr0 write with ts and mp unchanged */
1380 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1381 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1382 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1383 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1384 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1385 return;
1386 }
1387 }
1388 }
1389
1390 #ifdef CONFIG_X86_64
1391 if (vcpu->arch.efer & EFER_LME) {
1392 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1393 vcpu->arch.efer |= EFER_LMA;
1394 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1395 }
1396
1397 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1398 vcpu->arch.efer &= ~EFER_LMA;
1399 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1400 }
1401 }
1402 #endif
1403 vcpu->arch.cr0 = cr0;
1404
1405 if (!npt_enabled)
1406 cr0 |= X86_CR0_PG | X86_CR0_WP;
1407
1408 if (!vcpu->fpu_active)
1409 cr0 |= X86_CR0_TS;
1410 /*
1411 * re-enable caching here because the QEMU bios
1412 * does not do it - this results in some delay at
1413 * reboot
1414 */
1415 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1416 svm->vmcb->save.cr0 = cr0;
1417 mark_dirty(svm->vmcb, VMCB_CR);
1418 update_cr0_intercept(svm);
1419 }
1420
1421 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1422 {
1423 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1424 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1425
1426 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1427 force_new_asid(vcpu);
1428
1429 vcpu->arch.cr4 = cr4;
1430 if (!npt_enabled)
1431 cr4 |= X86_CR4_PAE;
1432 cr4 |= host_cr4_mce;
1433 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1434 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1435 }
1436
1437 static void svm_set_segment(struct kvm_vcpu *vcpu,
1438 struct kvm_segment *var, int seg)
1439 {
1440 struct vcpu_svm *svm = to_svm(vcpu);
1441 struct vmcb_seg *s = svm_seg(vcpu, seg);
1442
1443 s->base = var->base;
1444 s->limit = var->limit;
1445 s->selector = var->selector;
1446 if (var->unusable)
1447 s->attrib = 0;
1448 else {
1449 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1450 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1451 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1452 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1453 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1454 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1455 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1456 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1457 }
1458 if (seg == VCPU_SREG_CS)
1459 svm->vmcb->save.cpl
1460 = (svm->vmcb->save.cs.attrib
1461 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1462
1463 mark_dirty(svm->vmcb, VMCB_SEG);
1464 }
1465
1466 static void update_db_intercept(struct kvm_vcpu *vcpu)
1467 {
1468 struct vcpu_svm *svm = to_svm(vcpu);
1469
1470 clr_exception_intercept(svm, DB_VECTOR);
1471 clr_exception_intercept(svm, BP_VECTOR);
1472
1473 if (svm->nmi_singlestep)
1474 set_exception_intercept(svm, DB_VECTOR);
1475
1476 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1477 if (vcpu->guest_debug &
1478 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1479 set_exception_intercept(svm, DB_VECTOR);
1480 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1481 set_exception_intercept(svm, BP_VECTOR);
1482 } else
1483 vcpu->guest_debug = 0;
1484 }
1485
1486 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1487 {
1488 struct vcpu_svm *svm = to_svm(vcpu);
1489
1490 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1491 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1492 else
1493 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1494
1495 mark_dirty(svm->vmcb, VMCB_DR);
1496
1497 update_db_intercept(vcpu);
1498 }
1499
1500 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1501 {
1502 if (sd->next_asid > sd->max_asid) {
1503 ++sd->asid_generation;
1504 sd->next_asid = 1;
1505 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1506 }
1507
1508 svm->asid_generation = sd->asid_generation;
1509 svm->vmcb->control.asid = sd->next_asid++;
1510
1511 mark_dirty(svm->vmcb, VMCB_ASID);
1512 }
1513
1514 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1515 {
1516 struct vcpu_svm *svm = to_svm(vcpu);
1517
1518 svm->vmcb->save.dr7 = value;
1519 mark_dirty(svm->vmcb, VMCB_DR);
1520 }
1521
1522 static int pf_interception(struct vcpu_svm *svm)
1523 {
1524 u64 fault_address = svm->vmcb->control.exit_info_2;
1525 u32 error_code;
1526 int r = 1;
1527
1528 switch (svm->apf_reason) {
1529 default:
1530 error_code = svm->vmcb->control.exit_info_1;
1531
1532 trace_kvm_page_fault(fault_address, error_code);
1533 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1534 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1535 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1536 break;
1537 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1538 svm->apf_reason = 0;
1539 local_irq_disable();
1540 kvm_async_pf_task_wait(fault_address);
1541 local_irq_enable();
1542 break;
1543 case KVM_PV_REASON_PAGE_READY:
1544 svm->apf_reason = 0;
1545 local_irq_disable();
1546 kvm_async_pf_task_wake(fault_address);
1547 local_irq_enable();
1548 break;
1549 }
1550 return r;
1551 }
1552
1553 static int db_interception(struct vcpu_svm *svm)
1554 {
1555 struct kvm_run *kvm_run = svm->vcpu.run;
1556
1557 if (!(svm->vcpu.guest_debug &
1558 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1559 !svm->nmi_singlestep) {
1560 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1561 return 1;
1562 }
1563
1564 if (svm->nmi_singlestep) {
1565 svm->nmi_singlestep = false;
1566 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1567 svm->vmcb->save.rflags &=
1568 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1569 update_db_intercept(&svm->vcpu);
1570 }
1571
1572 if (svm->vcpu.guest_debug &
1573 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1574 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1575 kvm_run->debug.arch.pc =
1576 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1577 kvm_run->debug.arch.exception = DB_VECTOR;
1578 return 0;
1579 }
1580
1581 return 1;
1582 }
1583
1584 static int bp_interception(struct vcpu_svm *svm)
1585 {
1586 struct kvm_run *kvm_run = svm->vcpu.run;
1587
1588 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1589 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1590 kvm_run->debug.arch.exception = BP_VECTOR;
1591 return 0;
1592 }
1593
1594 static int ud_interception(struct vcpu_svm *svm)
1595 {
1596 int er;
1597
1598 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1599 if (er != EMULATE_DONE)
1600 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1601 return 1;
1602 }
1603
1604 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1605 {
1606 struct vcpu_svm *svm = to_svm(vcpu);
1607
1608 clr_exception_intercept(svm, NM_VECTOR);
1609
1610 svm->vcpu.fpu_active = 1;
1611 update_cr0_intercept(svm);
1612 }
1613
1614 static int nm_interception(struct vcpu_svm *svm)
1615 {
1616 svm_fpu_activate(&svm->vcpu);
1617 return 1;
1618 }
1619
1620 static bool is_erratum_383(void)
1621 {
1622 int err, i;
1623 u64 value;
1624
1625 if (!erratum_383_found)
1626 return false;
1627
1628 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1629 if (err)
1630 return false;
1631
1632 /* Bit 62 may or may not be set for this mce */
1633 value &= ~(1ULL << 62);
1634
1635 if (value != 0xb600000000010015ULL)
1636 return false;
1637
1638 /* Clear MCi_STATUS registers */
1639 for (i = 0; i < 6; ++i)
1640 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1641
1642 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1643 if (!err) {
1644 u32 low, high;
1645
1646 value &= ~(1ULL << 2);
1647 low = lower_32_bits(value);
1648 high = upper_32_bits(value);
1649
1650 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1651 }
1652
1653 /* Flush tlb to evict multi-match entries */
1654 __flush_tlb_all();
1655
1656 return true;
1657 }
1658
1659 static void svm_handle_mce(struct vcpu_svm *svm)
1660 {
1661 if (is_erratum_383()) {
1662 /*
1663 * Erratum 383 triggered. Guest state is corrupt so kill the
1664 * guest.
1665 */
1666 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1667
1668 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1669
1670 return;
1671 }
1672
1673 /*
1674 * On an #MC intercept the MCE handler is not called automatically in
1675 * the host. So do it by hand here.
1676 */
1677 asm volatile (
1678 "int $0x12\n");
1679 /* not sure if we ever come back to this point */
1680
1681 return;
1682 }
1683
1684 static int mc_interception(struct vcpu_svm *svm)
1685 {
1686 return 1;
1687 }
1688
1689 static int shutdown_interception(struct vcpu_svm *svm)
1690 {
1691 struct kvm_run *kvm_run = svm->vcpu.run;
1692
1693 /*
1694 * VMCB is undefined after a SHUTDOWN intercept
1695 * so reinitialize it.
1696 */
1697 clear_page(svm->vmcb);
1698 init_vmcb(svm);
1699
1700 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1701 return 0;
1702 }
1703
1704 static int io_interception(struct vcpu_svm *svm)
1705 {
1706 struct kvm_vcpu *vcpu = &svm->vcpu;
1707 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1708 int size, in, string;
1709 unsigned port;
1710
1711 ++svm->vcpu.stat.io_exits;
1712 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1713 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1714 if (string || in)
1715 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1716
1717 port = io_info >> 16;
1718 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1719 svm->next_rip = svm->vmcb->control.exit_info_2;
1720 skip_emulated_instruction(&svm->vcpu);
1721
1722 return kvm_fast_pio_out(vcpu, size, port);
1723 }
1724
1725 static int nmi_interception(struct vcpu_svm *svm)
1726 {
1727 return 1;
1728 }
1729
1730 static int intr_interception(struct vcpu_svm *svm)
1731 {
1732 ++svm->vcpu.stat.irq_exits;
1733 return 1;
1734 }
1735
1736 static int nop_on_interception(struct vcpu_svm *svm)
1737 {
1738 return 1;
1739 }
1740
1741 static int halt_interception(struct vcpu_svm *svm)
1742 {
1743 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1744 skip_emulated_instruction(&svm->vcpu);
1745 return kvm_emulate_halt(&svm->vcpu);
1746 }
1747
1748 static int vmmcall_interception(struct vcpu_svm *svm)
1749 {
1750 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1751 skip_emulated_instruction(&svm->vcpu);
1752 kvm_emulate_hypercall(&svm->vcpu);
1753 return 1;
1754 }
1755
1756 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1757 {
1758 struct vcpu_svm *svm = to_svm(vcpu);
1759
1760 return svm->nested.nested_cr3;
1761 }
1762
1763 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1764 unsigned long root)
1765 {
1766 struct vcpu_svm *svm = to_svm(vcpu);
1767
1768 svm->vmcb->control.nested_cr3 = root;
1769 mark_dirty(svm->vmcb, VMCB_NPT);
1770 force_new_asid(vcpu);
1771 }
1772
1773 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1774 struct x86_exception *fault)
1775 {
1776 struct vcpu_svm *svm = to_svm(vcpu);
1777
1778 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1779 svm->vmcb->control.exit_code_hi = 0;
1780 svm->vmcb->control.exit_info_1 = fault->error_code;
1781 svm->vmcb->control.exit_info_2 = fault->address;
1782
1783 nested_svm_vmexit(svm);
1784 }
1785
1786 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1787 {
1788 int r;
1789
1790 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1791
1792 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1793 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1794 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1795 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1796 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1797
1798 return r;
1799 }
1800
1801 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1802 {
1803 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1804 }
1805
1806 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1807 {
1808 if (!(svm->vcpu.arch.efer & EFER_SVME)
1809 || !is_paging(&svm->vcpu)) {
1810 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1811 return 1;
1812 }
1813
1814 if (svm->vmcb->save.cpl) {
1815 kvm_inject_gp(&svm->vcpu, 0);
1816 return 1;
1817 }
1818
1819 return 0;
1820 }
1821
1822 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1823 bool has_error_code, u32 error_code)
1824 {
1825 int vmexit;
1826
1827 if (!is_guest_mode(&svm->vcpu))
1828 return 0;
1829
1830 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1831 svm->vmcb->control.exit_code_hi = 0;
1832 svm->vmcb->control.exit_info_1 = error_code;
1833 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1834
1835 vmexit = nested_svm_intercept(svm);
1836 if (vmexit == NESTED_EXIT_DONE)
1837 svm->nested.exit_required = true;
1838
1839 return vmexit;
1840 }
1841
1842 /* This function returns true if it is save to enable the irq window */
1843 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1844 {
1845 if (!is_guest_mode(&svm->vcpu))
1846 return true;
1847
1848 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1849 return true;
1850
1851 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1852 return false;
1853
1854 /*
1855 * if vmexit was already requested (by intercepted exception
1856 * for instance) do not overwrite it with "external interrupt"
1857 * vmexit.
1858 */
1859 if (svm->nested.exit_required)
1860 return false;
1861
1862 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1863 svm->vmcb->control.exit_info_1 = 0;
1864 svm->vmcb->control.exit_info_2 = 0;
1865
1866 if (svm->nested.intercept & 1ULL) {
1867 /*
1868 * The #vmexit can't be emulated here directly because this
1869 * code path runs with irqs and preemtion disabled. A
1870 * #vmexit emulation might sleep. Only signal request for
1871 * the #vmexit here.
1872 */
1873 svm->nested.exit_required = true;
1874 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1875 return false;
1876 }
1877
1878 return true;
1879 }
1880
1881 /* This function returns true if it is save to enable the nmi window */
1882 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1883 {
1884 if (!is_guest_mode(&svm->vcpu))
1885 return true;
1886
1887 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1888 return true;
1889
1890 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1891 svm->nested.exit_required = true;
1892
1893 return false;
1894 }
1895
1896 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1897 {
1898 struct page *page;
1899
1900 might_sleep();
1901
1902 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1903 if (is_error_page(page))
1904 goto error;
1905
1906 *_page = page;
1907
1908 return kmap(page);
1909
1910 error:
1911 kvm_release_page_clean(page);
1912 kvm_inject_gp(&svm->vcpu, 0);
1913
1914 return NULL;
1915 }
1916
1917 static void nested_svm_unmap(struct page *page)
1918 {
1919 kunmap(page);
1920 kvm_release_page_dirty(page);
1921 }
1922
1923 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1924 {
1925 unsigned port;
1926 u8 val, bit;
1927 u64 gpa;
1928
1929 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1930 return NESTED_EXIT_HOST;
1931
1932 port = svm->vmcb->control.exit_info_1 >> 16;
1933 gpa = svm->nested.vmcb_iopm + (port / 8);
1934 bit = port % 8;
1935 val = 0;
1936
1937 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1938 val &= (1 << bit);
1939
1940 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1941 }
1942
1943 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1944 {
1945 u32 offset, msr, value;
1946 int write, mask;
1947
1948 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1949 return NESTED_EXIT_HOST;
1950
1951 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1952 offset = svm_msrpm_offset(msr);
1953 write = svm->vmcb->control.exit_info_1 & 1;
1954 mask = 1 << ((2 * (msr & 0xf)) + write);
1955
1956 if (offset == MSR_INVALID)
1957 return NESTED_EXIT_DONE;
1958
1959 /* Offset is in 32 bit units but need in 8 bit units */
1960 offset *= 4;
1961
1962 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1963 return NESTED_EXIT_DONE;
1964
1965 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1966 }
1967
1968 static int nested_svm_exit_special(struct vcpu_svm *svm)
1969 {
1970 u32 exit_code = svm->vmcb->control.exit_code;
1971
1972 switch (exit_code) {
1973 case SVM_EXIT_INTR:
1974 case SVM_EXIT_NMI:
1975 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1976 return NESTED_EXIT_HOST;
1977 case SVM_EXIT_NPF:
1978 /* For now we are always handling NPFs when using them */
1979 if (npt_enabled)
1980 return NESTED_EXIT_HOST;
1981 break;
1982 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1983 /* When we're shadowing, trap PFs, but not async PF */
1984 if (!npt_enabled && svm->apf_reason == 0)
1985 return NESTED_EXIT_HOST;
1986 break;
1987 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1988 nm_interception(svm);
1989 break;
1990 default:
1991 break;
1992 }
1993
1994 return NESTED_EXIT_CONTINUE;
1995 }
1996
1997 /*
1998 * If this function returns true, this #vmexit was already handled
1999 */
2000 static int nested_svm_intercept(struct vcpu_svm *svm)
2001 {
2002 u32 exit_code = svm->vmcb->control.exit_code;
2003 int vmexit = NESTED_EXIT_HOST;
2004
2005 switch (exit_code) {
2006 case SVM_EXIT_MSR:
2007 vmexit = nested_svm_exit_handled_msr(svm);
2008 break;
2009 case SVM_EXIT_IOIO:
2010 vmexit = nested_svm_intercept_ioio(svm);
2011 break;
2012 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2013 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2014 if (svm->nested.intercept_cr & bit)
2015 vmexit = NESTED_EXIT_DONE;
2016 break;
2017 }
2018 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2019 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2020 if (svm->nested.intercept_dr & bit)
2021 vmexit = NESTED_EXIT_DONE;
2022 break;
2023 }
2024 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2025 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2026 if (svm->nested.intercept_exceptions & excp_bits)
2027 vmexit = NESTED_EXIT_DONE;
2028 /* async page fault always cause vmexit */
2029 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2030 svm->apf_reason != 0)
2031 vmexit = NESTED_EXIT_DONE;
2032 break;
2033 }
2034 case SVM_EXIT_ERR: {
2035 vmexit = NESTED_EXIT_DONE;
2036 break;
2037 }
2038 default: {
2039 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2040 if (svm->nested.intercept & exit_bits)
2041 vmexit = NESTED_EXIT_DONE;
2042 }
2043 }
2044
2045 return vmexit;
2046 }
2047
2048 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2049 {
2050 int vmexit;
2051
2052 vmexit = nested_svm_intercept(svm);
2053
2054 if (vmexit == NESTED_EXIT_DONE)
2055 nested_svm_vmexit(svm);
2056
2057 return vmexit;
2058 }
2059
2060 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2061 {
2062 struct vmcb_control_area *dst = &dst_vmcb->control;
2063 struct vmcb_control_area *from = &from_vmcb->control;
2064
2065 dst->intercept_cr = from->intercept_cr;
2066 dst->intercept_dr = from->intercept_dr;
2067 dst->intercept_exceptions = from->intercept_exceptions;
2068 dst->intercept = from->intercept;
2069 dst->iopm_base_pa = from->iopm_base_pa;
2070 dst->msrpm_base_pa = from->msrpm_base_pa;
2071 dst->tsc_offset = from->tsc_offset;
2072 dst->asid = from->asid;
2073 dst->tlb_ctl = from->tlb_ctl;
2074 dst->int_ctl = from->int_ctl;
2075 dst->int_vector = from->int_vector;
2076 dst->int_state = from->int_state;
2077 dst->exit_code = from->exit_code;
2078 dst->exit_code_hi = from->exit_code_hi;
2079 dst->exit_info_1 = from->exit_info_1;
2080 dst->exit_info_2 = from->exit_info_2;
2081 dst->exit_int_info = from->exit_int_info;
2082 dst->exit_int_info_err = from->exit_int_info_err;
2083 dst->nested_ctl = from->nested_ctl;
2084 dst->event_inj = from->event_inj;
2085 dst->event_inj_err = from->event_inj_err;
2086 dst->nested_cr3 = from->nested_cr3;
2087 dst->lbr_ctl = from->lbr_ctl;
2088 }
2089
2090 static int nested_svm_vmexit(struct vcpu_svm *svm)
2091 {
2092 struct vmcb *nested_vmcb;
2093 struct vmcb *hsave = svm->nested.hsave;
2094 struct vmcb *vmcb = svm->vmcb;
2095 struct page *page;
2096
2097 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2098 vmcb->control.exit_info_1,
2099 vmcb->control.exit_info_2,
2100 vmcb->control.exit_int_info,
2101 vmcb->control.exit_int_info_err);
2102
2103 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2104 if (!nested_vmcb)
2105 return 1;
2106
2107 /* Exit Guest-Mode */
2108 leave_guest_mode(&svm->vcpu);
2109 svm->nested.vmcb = 0;
2110
2111 /* Give the current vmcb to the guest */
2112 disable_gif(svm);
2113
2114 nested_vmcb->save.es = vmcb->save.es;
2115 nested_vmcb->save.cs = vmcb->save.cs;
2116 nested_vmcb->save.ss = vmcb->save.ss;
2117 nested_vmcb->save.ds = vmcb->save.ds;
2118 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2119 nested_vmcb->save.idtr = vmcb->save.idtr;
2120 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2121 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2122 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2123 nested_vmcb->save.cr2 = vmcb->save.cr2;
2124 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2125 nested_vmcb->save.rflags = vmcb->save.rflags;
2126 nested_vmcb->save.rip = vmcb->save.rip;
2127 nested_vmcb->save.rsp = vmcb->save.rsp;
2128 nested_vmcb->save.rax = vmcb->save.rax;
2129 nested_vmcb->save.dr7 = vmcb->save.dr7;
2130 nested_vmcb->save.dr6 = vmcb->save.dr6;
2131 nested_vmcb->save.cpl = vmcb->save.cpl;
2132
2133 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2134 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2135 nested_vmcb->control.int_state = vmcb->control.int_state;
2136 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2137 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2138 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2139 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2140 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2141 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2142 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2143
2144 /*
2145 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2146 * to make sure that we do not lose injected events. So check event_inj
2147 * here and copy it to exit_int_info if it is valid.
2148 * Exit_int_info and event_inj can't be both valid because the case
2149 * below only happens on a VMRUN instruction intercept which has
2150 * no valid exit_int_info set.
2151 */
2152 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2153 struct vmcb_control_area *nc = &nested_vmcb->control;
2154
2155 nc->exit_int_info = vmcb->control.event_inj;
2156 nc->exit_int_info_err = vmcb->control.event_inj_err;
2157 }
2158
2159 nested_vmcb->control.tlb_ctl = 0;
2160 nested_vmcb->control.event_inj = 0;
2161 nested_vmcb->control.event_inj_err = 0;
2162
2163 /* We always set V_INTR_MASKING and remember the old value in hflags */
2164 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2165 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2166
2167 /* Restore the original control entries */
2168 copy_vmcb_control_area(vmcb, hsave);
2169
2170 kvm_clear_exception_queue(&svm->vcpu);
2171 kvm_clear_interrupt_queue(&svm->vcpu);
2172
2173 svm->nested.nested_cr3 = 0;
2174
2175 /* Restore selected save entries */
2176 svm->vmcb->save.es = hsave->save.es;
2177 svm->vmcb->save.cs = hsave->save.cs;
2178 svm->vmcb->save.ss = hsave->save.ss;
2179 svm->vmcb->save.ds = hsave->save.ds;
2180 svm->vmcb->save.gdtr = hsave->save.gdtr;
2181 svm->vmcb->save.idtr = hsave->save.idtr;
2182 svm->vmcb->save.rflags = hsave->save.rflags;
2183 svm_set_efer(&svm->vcpu, hsave->save.efer);
2184 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2185 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2186 if (npt_enabled) {
2187 svm->vmcb->save.cr3 = hsave->save.cr3;
2188 svm->vcpu.arch.cr3 = hsave->save.cr3;
2189 } else {
2190 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2191 }
2192 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2193 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2194 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2195 svm->vmcb->save.dr7 = 0;
2196 svm->vmcb->save.cpl = 0;
2197 svm->vmcb->control.exit_int_info = 0;
2198
2199 mark_all_dirty(svm->vmcb);
2200
2201 nested_svm_unmap(page);
2202
2203 nested_svm_uninit_mmu_context(&svm->vcpu);
2204 kvm_mmu_reset_context(&svm->vcpu);
2205 kvm_mmu_load(&svm->vcpu);
2206
2207 return 0;
2208 }
2209
2210 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2211 {
2212 /*
2213 * This function merges the msr permission bitmaps of kvm and the
2214 * nested vmcb. It is omptimized in that it only merges the parts where
2215 * the kvm msr permission bitmap may contain zero bits
2216 */
2217 int i;
2218
2219 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2220 return true;
2221
2222 for (i = 0; i < MSRPM_OFFSETS; i++) {
2223 u32 value, p;
2224 u64 offset;
2225
2226 if (msrpm_offsets[i] == 0xffffffff)
2227 break;
2228
2229 p = msrpm_offsets[i];
2230 offset = svm->nested.vmcb_msrpm + (p * 4);
2231
2232 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2233 return false;
2234
2235 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2236 }
2237
2238 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2239
2240 return true;
2241 }
2242
2243 static bool nested_vmcb_checks(struct vmcb *vmcb)
2244 {
2245 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2246 return false;
2247
2248 if (vmcb->control.asid == 0)
2249 return false;
2250
2251 if (vmcb->control.nested_ctl && !npt_enabled)
2252 return false;
2253
2254 return true;
2255 }
2256
2257 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2258 {
2259 struct vmcb *nested_vmcb;
2260 struct vmcb *hsave = svm->nested.hsave;
2261 struct vmcb *vmcb = svm->vmcb;
2262 struct page *page;
2263 u64 vmcb_gpa;
2264
2265 vmcb_gpa = svm->vmcb->save.rax;
2266
2267 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2268 if (!nested_vmcb)
2269 return false;
2270
2271 if (!nested_vmcb_checks(nested_vmcb)) {
2272 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2273 nested_vmcb->control.exit_code_hi = 0;
2274 nested_vmcb->control.exit_info_1 = 0;
2275 nested_vmcb->control.exit_info_2 = 0;
2276
2277 nested_svm_unmap(page);
2278
2279 return false;
2280 }
2281
2282 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2283 nested_vmcb->save.rip,
2284 nested_vmcb->control.int_ctl,
2285 nested_vmcb->control.event_inj,
2286 nested_vmcb->control.nested_ctl);
2287
2288 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2289 nested_vmcb->control.intercept_cr >> 16,
2290 nested_vmcb->control.intercept_exceptions,
2291 nested_vmcb->control.intercept);
2292
2293 /* Clear internal status */
2294 kvm_clear_exception_queue(&svm->vcpu);
2295 kvm_clear_interrupt_queue(&svm->vcpu);
2296
2297 /*
2298 * Save the old vmcb, so we don't need to pick what we save, but can
2299 * restore everything when a VMEXIT occurs
2300 */
2301 hsave->save.es = vmcb->save.es;
2302 hsave->save.cs = vmcb->save.cs;
2303 hsave->save.ss = vmcb->save.ss;
2304 hsave->save.ds = vmcb->save.ds;
2305 hsave->save.gdtr = vmcb->save.gdtr;
2306 hsave->save.idtr = vmcb->save.idtr;
2307 hsave->save.efer = svm->vcpu.arch.efer;
2308 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2309 hsave->save.cr4 = svm->vcpu.arch.cr4;
2310 hsave->save.rflags = vmcb->save.rflags;
2311 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2312 hsave->save.rsp = vmcb->save.rsp;
2313 hsave->save.rax = vmcb->save.rax;
2314 if (npt_enabled)
2315 hsave->save.cr3 = vmcb->save.cr3;
2316 else
2317 hsave->save.cr3 = svm->vcpu.arch.cr3;
2318
2319 copy_vmcb_control_area(hsave, vmcb);
2320
2321 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2322 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2323 else
2324 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2325
2326 if (nested_vmcb->control.nested_ctl) {
2327 kvm_mmu_unload(&svm->vcpu);
2328 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2329 nested_svm_init_mmu_context(&svm->vcpu);
2330 }
2331
2332 /* Load the nested guest state */
2333 svm->vmcb->save.es = nested_vmcb->save.es;
2334 svm->vmcb->save.cs = nested_vmcb->save.cs;
2335 svm->vmcb->save.ss = nested_vmcb->save.ss;
2336 svm->vmcb->save.ds = nested_vmcb->save.ds;
2337 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2338 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2339 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2340 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2341 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2342 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2343 if (npt_enabled) {
2344 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2345 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2346 } else
2347 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2348
2349 /* Guest paging mode is active - reset mmu */
2350 kvm_mmu_reset_context(&svm->vcpu);
2351
2352 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2353 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2354 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2355 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2356
2357 /* In case we don't even reach vcpu_run, the fields are not updated */
2358 svm->vmcb->save.rax = nested_vmcb->save.rax;
2359 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2360 svm->vmcb->save.rip = nested_vmcb->save.rip;
2361 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2362 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2363 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2364
2365 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2366 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2367
2368 /* cache intercepts */
2369 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2370 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2371 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2372 svm->nested.intercept = nested_vmcb->control.intercept;
2373
2374 force_new_asid(&svm->vcpu);
2375 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2376 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2377 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2378 else
2379 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2380
2381 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2382 /* We only want the cr8 intercept bits of the guest */
2383 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2384 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2385 }
2386
2387 /* We don't want to see VMMCALLs from a nested guest */
2388 clr_intercept(svm, INTERCEPT_VMMCALL);
2389
2390 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2391 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2392 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2393 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2394 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2395 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2396
2397 nested_svm_unmap(page);
2398
2399 /* Enter Guest-Mode */
2400 enter_guest_mode(&svm->vcpu);
2401
2402 /*
2403 * Merge guest and host intercepts - must be called with vcpu in
2404 * guest-mode to take affect here
2405 */
2406 recalc_intercepts(svm);
2407
2408 svm->nested.vmcb = vmcb_gpa;
2409
2410 enable_gif(svm);
2411
2412 mark_all_dirty(svm->vmcb);
2413
2414 return true;
2415 }
2416
2417 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2418 {
2419 to_vmcb->save.fs = from_vmcb->save.fs;
2420 to_vmcb->save.gs = from_vmcb->save.gs;
2421 to_vmcb->save.tr = from_vmcb->save.tr;
2422 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2423 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2424 to_vmcb->save.star = from_vmcb->save.star;
2425 to_vmcb->save.lstar = from_vmcb->save.lstar;
2426 to_vmcb->save.cstar = from_vmcb->save.cstar;
2427 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2428 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2429 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2430 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2431 }
2432
2433 static int vmload_interception(struct vcpu_svm *svm)
2434 {
2435 struct vmcb *nested_vmcb;
2436 struct page *page;
2437
2438 if (nested_svm_check_permissions(svm))
2439 return 1;
2440
2441 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2442 skip_emulated_instruction(&svm->vcpu);
2443
2444 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2445 if (!nested_vmcb)
2446 return 1;
2447
2448 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2449 nested_svm_unmap(page);
2450
2451 return 1;
2452 }
2453
2454 static int vmsave_interception(struct vcpu_svm *svm)
2455 {
2456 struct vmcb *nested_vmcb;
2457 struct page *page;
2458
2459 if (nested_svm_check_permissions(svm))
2460 return 1;
2461
2462 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2463 skip_emulated_instruction(&svm->vcpu);
2464
2465 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2466 if (!nested_vmcb)
2467 return 1;
2468
2469 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2470 nested_svm_unmap(page);
2471
2472 return 1;
2473 }
2474
2475 static int vmrun_interception(struct vcpu_svm *svm)
2476 {
2477 if (nested_svm_check_permissions(svm))
2478 return 1;
2479
2480 /* Save rip after vmrun instruction */
2481 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2482
2483 if (!nested_svm_vmrun(svm))
2484 return 1;
2485
2486 if (!nested_svm_vmrun_msrpm(svm))
2487 goto failed;
2488
2489 return 1;
2490
2491 failed:
2492
2493 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2494 svm->vmcb->control.exit_code_hi = 0;
2495 svm->vmcb->control.exit_info_1 = 0;
2496 svm->vmcb->control.exit_info_2 = 0;
2497
2498 nested_svm_vmexit(svm);
2499
2500 return 1;
2501 }
2502
2503 static int stgi_interception(struct vcpu_svm *svm)
2504 {
2505 if (nested_svm_check_permissions(svm))
2506 return 1;
2507
2508 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2509 skip_emulated_instruction(&svm->vcpu);
2510 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2511
2512 enable_gif(svm);
2513
2514 return 1;
2515 }
2516
2517 static int clgi_interception(struct vcpu_svm *svm)
2518 {
2519 if (nested_svm_check_permissions(svm))
2520 return 1;
2521
2522 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2523 skip_emulated_instruction(&svm->vcpu);
2524
2525 disable_gif(svm);
2526
2527 /* After a CLGI no interrupts should come */
2528 svm_clear_vintr(svm);
2529 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2530
2531 mark_dirty(svm->vmcb, VMCB_INTR);
2532
2533 return 1;
2534 }
2535
2536 static int invlpga_interception(struct vcpu_svm *svm)
2537 {
2538 struct kvm_vcpu *vcpu = &svm->vcpu;
2539
2540 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2541 vcpu->arch.regs[VCPU_REGS_RAX]);
2542
2543 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2544 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2545
2546 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2547 skip_emulated_instruction(&svm->vcpu);
2548 return 1;
2549 }
2550
2551 static int skinit_interception(struct vcpu_svm *svm)
2552 {
2553 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2554
2555 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2556 return 1;
2557 }
2558
2559 static int invalid_op_interception(struct vcpu_svm *svm)
2560 {
2561 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2562 return 1;
2563 }
2564
2565 static int task_switch_interception(struct vcpu_svm *svm)
2566 {
2567 u16 tss_selector;
2568 int reason;
2569 int int_type = svm->vmcb->control.exit_int_info &
2570 SVM_EXITINTINFO_TYPE_MASK;
2571 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2572 uint32_t type =
2573 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2574 uint32_t idt_v =
2575 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2576 bool has_error_code = false;
2577 u32 error_code = 0;
2578
2579 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2580
2581 if (svm->vmcb->control.exit_info_2 &
2582 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2583 reason = TASK_SWITCH_IRET;
2584 else if (svm->vmcb->control.exit_info_2 &
2585 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2586 reason = TASK_SWITCH_JMP;
2587 else if (idt_v)
2588 reason = TASK_SWITCH_GATE;
2589 else
2590 reason = TASK_SWITCH_CALL;
2591
2592 if (reason == TASK_SWITCH_GATE) {
2593 switch (type) {
2594 case SVM_EXITINTINFO_TYPE_NMI:
2595 svm->vcpu.arch.nmi_injected = false;
2596 break;
2597 case SVM_EXITINTINFO_TYPE_EXEPT:
2598 if (svm->vmcb->control.exit_info_2 &
2599 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2600 has_error_code = true;
2601 error_code =
2602 (u32)svm->vmcb->control.exit_info_2;
2603 }
2604 kvm_clear_exception_queue(&svm->vcpu);
2605 break;
2606 case SVM_EXITINTINFO_TYPE_INTR:
2607 kvm_clear_interrupt_queue(&svm->vcpu);
2608 break;
2609 default:
2610 break;
2611 }
2612 }
2613
2614 if (reason != TASK_SWITCH_GATE ||
2615 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2616 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2617 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2618 skip_emulated_instruction(&svm->vcpu);
2619
2620 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2621 has_error_code, error_code) == EMULATE_FAIL) {
2622 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2623 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2624 svm->vcpu.run->internal.ndata = 0;
2625 return 0;
2626 }
2627 return 1;
2628 }
2629
2630 static int cpuid_interception(struct vcpu_svm *svm)
2631 {
2632 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2633 kvm_emulate_cpuid(&svm->vcpu);
2634 return 1;
2635 }
2636
2637 static int iret_interception(struct vcpu_svm *svm)
2638 {
2639 ++svm->vcpu.stat.nmi_window_exits;
2640 clr_intercept(svm, INTERCEPT_IRET);
2641 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2642 return 1;
2643 }
2644
2645 static int invlpg_interception(struct vcpu_svm *svm)
2646 {
2647 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2648 }
2649
2650 static int emulate_on_interception(struct vcpu_svm *svm)
2651 {
2652 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2653 }
2654
2655 static int cr0_write_interception(struct vcpu_svm *svm)
2656 {
2657 struct kvm_vcpu *vcpu = &svm->vcpu;
2658 int r;
2659
2660 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2661
2662 if (svm->nested.vmexit_rip) {
2663 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2664 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2665 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2666 svm->nested.vmexit_rip = 0;
2667 }
2668
2669 return r == EMULATE_DONE;
2670 }
2671
2672 static int cr8_write_interception(struct vcpu_svm *svm)
2673 {
2674 struct kvm_run *kvm_run = svm->vcpu.run;
2675
2676 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2677 /* instruction emulation calls kvm_set_cr8() */
2678 emulate_instruction(&svm->vcpu, 0, 0, 0);
2679 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2680 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2681 return 1;
2682 }
2683 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2684 return 1;
2685 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2686 return 0;
2687 }
2688
2689 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2690 {
2691 struct vcpu_svm *svm = to_svm(vcpu);
2692
2693 switch (ecx) {
2694 case MSR_IA32_TSC: {
2695 struct vmcb *vmcb = get_host_vmcb(svm);
2696
2697 *data = vmcb->control.tsc_offset + native_read_tsc();
2698 break;
2699 }
2700 case MSR_STAR:
2701 *data = svm->vmcb->save.star;
2702 break;
2703 #ifdef CONFIG_X86_64
2704 case MSR_LSTAR:
2705 *data = svm->vmcb->save.lstar;
2706 break;
2707 case MSR_CSTAR:
2708 *data = svm->vmcb->save.cstar;
2709 break;
2710 case MSR_KERNEL_GS_BASE:
2711 *data = svm->vmcb->save.kernel_gs_base;
2712 break;
2713 case MSR_SYSCALL_MASK:
2714 *data = svm->vmcb->save.sfmask;
2715 break;
2716 #endif
2717 case MSR_IA32_SYSENTER_CS:
2718 *data = svm->vmcb->save.sysenter_cs;
2719 break;
2720 case MSR_IA32_SYSENTER_EIP:
2721 *data = svm->sysenter_eip;
2722 break;
2723 case MSR_IA32_SYSENTER_ESP:
2724 *data = svm->sysenter_esp;
2725 break;
2726 /*
2727 * Nobody will change the following 5 values in the VMCB so we can
2728 * safely return them on rdmsr. They will always be 0 until LBRV is
2729 * implemented.
2730 */
2731 case MSR_IA32_DEBUGCTLMSR:
2732 *data = svm->vmcb->save.dbgctl;
2733 break;
2734 case MSR_IA32_LASTBRANCHFROMIP:
2735 *data = svm->vmcb->save.br_from;
2736 break;
2737 case MSR_IA32_LASTBRANCHTOIP:
2738 *data = svm->vmcb->save.br_to;
2739 break;
2740 case MSR_IA32_LASTINTFROMIP:
2741 *data = svm->vmcb->save.last_excp_from;
2742 break;
2743 case MSR_IA32_LASTINTTOIP:
2744 *data = svm->vmcb->save.last_excp_to;
2745 break;
2746 case MSR_VM_HSAVE_PA:
2747 *data = svm->nested.hsave_msr;
2748 break;
2749 case MSR_VM_CR:
2750 *data = svm->nested.vm_cr_msr;
2751 break;
2752 case MSR_IA32_UCODE_REV:
2753 *data = 0x01000065;
2754 break;
2755 default:
2756 return kvm_get_msr_common(vcpu, ecx, data);
2757 }
2758 return 0;
2759 }
2760
2761 static int rdmsr_interception(struct vcpu_svm *svm)
2762 {
2763 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2764 u64 data;
2765
2766 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2767 trace_kvm_msr_read_ex(ecx);
2768 kvm_inject_gp(&svm->vcpu, 0);
2769 } else {
2770 trace_kvm_msr_read(ecx, data);
2771
2772 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2773 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2774 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2775 skip_emulated_instruction(&svm->vcpu);
2776 }
2777 return 1;
2778 }
2779
2780 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2781 {
2782 struct vcpu_svm *svm = to_svm(vcpu);
2783 int svm_dis, chg_mask;
2784
2785 if (data & ~SVM_VM_CR_VALID_MASK)
2786 return 1;
2787
2788 chg_mask = SVM_VM_CR_VALID_MASK;
2789
2790 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2791 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2792
2793 svm->nested.vm_cr_msr &= ~chg_mask;
2794 svm->nested.vm_cr_msr |= (data & chg_mask);
2795
2796 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2797
2798 /* check for svm_disable while efer.svme is set */
2799 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2800 return 1;
2801
2802 return 0;
2803 }
2804
2805 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2806 {
2807 struct vcpu_svm *svm = to_svm(vcpu);
2808
2809 switch (ecx) {
2810 case MSR_IA32_TSC:
2811 kvm_write_tsc(vcpu, data);
2812 break;
2813 case MSR_STAR:
2814 svm->vmcb->save.star = data;
2815 break;
2816 #ifdef CONFIG_X86_64
2817 case MSR_LSTAR:
2818 svm->vmcb->save.lstar = data;
2819 break;
2820 case MSR_CSTAR:
2821 svm->vmcb->save.cstar = data;
2822 break;
2823 case MSR_KERNEL_GS_BASE:
2824 svm->vmcb->save.kernel_gs_base = data;
2825 break;
2826 case MSR_SYSCALL_MASK:
2827 svm->vmcb->save.sfmask = data;
2828 break;
2829 #endif
2830 case MSR_IA32_SYSENTER_CS:
2831 svm->vmcb->save.sysenter_cs = data;
2832 break;
2833 case MSR_IA32_SYSENTER_EIP:
2834 svm->sysenter_eip = data;
2835 svm->vmcb->save.sysenter_eip = data;
2836 break;
2837 case MSR_IA32_SYSENTER_ESP:
2838 svm->sysenter_esp = data;
2839 svm->vmcb->save.sysenter_esp = data;
2840 break;
2841 case MSR_IA32_DEBUGCTLMSR:
2842 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2843 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2844 __func__, data);
2845 break;
2846 }
2847 if (data & DEBUGCTL_RESERVED_BITS)
2848 return 1;
2849
2850 svm->vmcb->save.dbgctl = data;
2851 mark_dirty(svm->vmcb, VMCB_LBR);
2852 if (data & (1ULL<<0))
2853 svm_enable_lbrv(svm);
2854 else
2855 svm_disable_lbrv(svm);
2856 break;
2857 case MSR_VM_HSAVE_PA:
2858 svm->nested.hsave_msr = data;
2859 break;
2860 case MSR_VM_CR:
2861 return svm_set_vm_cr(vcpu, data);
2862 case MSR_VM_IGNNE:
2863 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2864 break;
2865 default:
2866 return kvm_set_msr_common(vcpu, ecx, data);
2867 }
2868 return 0;
2869 }
2870
2871 static int wrmsr_interception(struct vcpu_svm *svm)
2872 {
2873 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2874 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2875 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2876
2877
2878 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2879 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2880 trace_kvm_msr_write_ex(ecx, data);
2881 kvm_inject_gp(&svm->vcpu, 0);
2882 } else {
2883 trace_kvm_msr_write(ecx, data);
2884 skip_emulated_instruction(&svm->vcpu);
2885 }
2886 return 1;
2887 }
2888
2889 static int msr_interception(struct vcpu_svm *svm)
2890 {
2891 if (svm->vmcb->control.exit_info_1)
2892 return wrmsr_interception(svm);
2893 else
2894 return rdmsr_interception(svm);
2895 }
2896
2897 static int interrupt_window_interception(struct vcpu_svm *svm)
2898 {
2899 struct kvm_run *kvm_run = svm->vcpu.run;
2900
2901 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2902 svm_clear_vintr(svm);
2903 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2904 mark_dirty(svm->vmcb, VMCB_INTR);
2905 /*
2906 * If the user space waits to inject interrupts, exit as soon as
2907 * possible
2908 */
2909 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2910 kvm_run->request_interrupt_window &&
2911 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2912 ++svm->vcpu.stat.irq_window_exits;
2913 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2914 return 0;
2915 }
2916
2917 return 1;
2918 }
2919
2920 static int pause_interception(struct vcpu_svm *svm)
2921 {
2922 kvm_vcpu_on_spin(&(svm->vcpu));
2923 return 1;
2924 }
2925
2926 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2927 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2928 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2929 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2930 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2931 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2932 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2933 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2934 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2935 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2936 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2937 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2938 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2939 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2940 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2941 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2942 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2943 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2944 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2945 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2946 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2947 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2948 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2949 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2950 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2951 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2952 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2953 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2954 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2955 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2956 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2957 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2958 [SVM_EXIT_INTR] = intr_interception,
2959 [SVM_EXIT_NMI] = nmi_interception,
2960 [SVM_EXIT_SMI] = nop_on_interception,
2961 [SVM_EXIT_INIT] = nop_on_interception,
2962 [SVM_EXIT_VINTR] = interrupt_window_interception,
2963 [SVM_EXIT_CPUID] = cpuid_interception,
2964 [SVM_EXIT_IRET] = iret_interception,
2965 [SVM_EXIT_INVD] = emulate_on_interception,
2966 [SVM_EXIT_PAUSE] = pause_interception,
2967 [SVM_EXIT_HLT] = halt_interception,
2968 [SVM_EXIT_INVLPG] = invlpg_interception,
2969 [SVM_EXIT_INVLPGA] = invlpga_interception,
2970 [SVM_EXIT_IOIO] = io_interception,
2971 [SVM_EXIT_MSR] = msr_interception,
2972 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2973 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2974 [SVM_EXIT_VMRUN] = vmrun_interception,
2975 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2976 [SVM_EXIT_VMLOAD] = vmload_interception,
2977 [SVM_EXIT_VMSAVE] = vmsave_interception,
2978 [SVM_EXIT_STGI] = stgi_interception,
2979 [SVM_EXIT_CLGI] = clgi_interception,
2980 [SVM_EXIT_SKINIT] = skinit_interception,
2981 [SVM_EXIT_WBINVD] = emulate_on_interception,
2982 [SVM_EXIT_MONITOR] = invalid_op_interception,
2983 [SVM_EXIT_MWAIT] = invalid_op_interception,
2984 [SVM_EXIT_NPF] = pf_interception,
2985 };
2986
2987 void dump_vmcb(struct kvm_vcpu *vcpu)
2988 {
2989 struct vcpu_svm *svm = to_svm(vcpu);
2990 struct vmcb_control_area *control = &svm->vmcb->control;
2991 struct vmcb_save_area *save = &svm->vmcb->save;
2992
2993 pr_err("VMCB Control Area:\n");
2994 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2995 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2996 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2997 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2998 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2999 pr_err("intercepts: %016llx\n", control->intercept);
3000 pr_err("pause filter count: %d\n", control->pause_filter_count);
3001 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
3002 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
3003 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
3004 pr_err("asid: %d\n", control->asid);
3005 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3006 pr_err("int_ctl: %08x\n", control->int_ctl);
3007 pr_err("int_vector: %08x\n", control->int_vector);
3008 pr_err("int_state: %08x\n", control->int_state);
3009 pr_err("exit_code: %08x\n", control->exit_code);
3010 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3011 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3012 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3013 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3014 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3015 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3016 pr_err("event_inj: %08x\n", control->event_inj);
3017 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3018 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3019 pr_err("next_rip: %016llx\n", control->next_rip);
3020 pr_err("VMCB State Save Area:\n");
3021 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3022 save->es.selector, save->es.attrib,
3023 save->es.limit, save->es.base);
3024 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3025 save->cs.selector, save->cs.attrib,
3026 save->cs.limit, save->cs.base);
3027 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3028 save->ss.selector, save->ss.attrib,
3029 save->ss.limit, save->ss.base);
3030 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3031 save->ds.selector, save->ds.attrib,
3032 save->ds.limit, save->ds.base);
3033 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3034 save->fs.selector, save->fs.attrib,
3035 save->fs.limit, save->fs.base);
3036 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3037 save->gs.selector, save->gs.attrib,
3038 save->gs.limit, save->gs.base);
3039 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3040 save->gdtr.selector, save->gdtr.attrib,
3041 save->gdtr.limit, save->gdtr.base);
3042 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3043 save->ldtr.selector, save->ldtr.attrib,
3044 save->ldtr.limit, save->ldtr.base);
3045 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3046 save->idtr.selector, save->idtr.attrib,
3047 save->idtr.limit, save->idtr.base);
3048 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3049 save->tr.selector, save->tr.attrib,
3050 save->tr.limit, save->tr.base);
3051 pr_err("cpl: %d efer: %016llx\n",
3052 save->cpl, save->efer);
3053 pr_err("cr0: %016llx cr2: %016llx\n",
3054 save->cr0, save->cr2);
3055 pr_err("cr3: %016llx cr4: %016llx\n",
3056 save->cr3, save->cr4);
3057 pr_err("dr6: %016llx dr7: %016llx\n",
3058 save->dr6, save->dr7);
3059 pr_err("rip: %016llx rflags: %016llx\n",
3060 save->rip, save->rflags);
3061 pr_err("rsp: %016llx rax: %016llx\n",
3062 save->rsp, save->rax);
3063 pr_err("star: %016llx lstar: %016llx\n",
3064 save->star, save->lstar);
3065 pr_err("cstar: %016llx sfmask: %016llx\n",
3066 save->cstar, save->sfmask);
3067 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3068 save->kernel_gs_base, save->sysenter_cs);
3069 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3070 save->sysenter_esp, save->sysenter_eip);
3071 pr_err("gpat: %016llx dbgctl: %016llx\n",
3072 save->g_pat, save->dbgctl);
3073 pr_err("br_from: %016llx br_to: %016llx\n",
3074 save->br_from, save->br_to);
3075 pr_err("excp_from: %016llx excp_to: %016llx\n",
3076 save->last_excp_from, save->last_excp_to);
3077
3078 }
3079
3080 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3081 {
3082 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3083
3084 *info1 = control->exit_info_1;
3085 *info2 = control->exit_info_2;
3086 }
3087
3088 static int handle_exit(struct kvm_vcpu *vcpu)
3089 {
3090 struct vcpu_svm *svm = to_svm(vcpu);
3091 struct kvm_run *kvm_run = vcpu->run;
3092 u32 exit_code = svm->vmcb->control.exit_code;
3093
3094 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3095
3096 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3097 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3098 if (npt_enabled)
3099 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3100
3101 if (unlikely(svm->nested.exit_required)) {
3102 nested_svm_vmexit(svm);
3103 svm->nested.exit_required = false;
3104
3105 return 1;
3106 }
3107
3108 if (is_guest_mode(vcpu)) {
3109 int vmexit;
3110
3111 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3112 svm->vmcb->control.exit_info_1,
3113 svm->vmcb->control.exit_info_2,
3114 svm->vmcb->control.exit_int_info,
3115 svm->vmcb->control.exit_int_info_err);
3116
3117 vmexit = nested_svm_exit_special(svm);
3118
3119 if (vmexit == NESTED_EXIT_CONTINUE)
3120 vmexit = nested_svm_exit_handled(svm);
3121
3122 if (vmexit == NESTED_EXIT_DONE)
3123 return 1;
3124 }
3125
3126 svm_complete_interrupts(svm);
3127
3128 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3129 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3130 kvm_run->fail_entry.hardware_entry_failure_reason
3131 = svm->vmcb->control.exit_code;
3132 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3133 dump_vmcb(vcpu);
3134 return 0;
3135 }
3136
3137 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3138 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3139 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3140 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3141 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3142 "exit_code 0x%x\n",
3143 __func__, svm->vmcb->control.exit_int_info,
3144 exit_code);
3145
3146 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3147 || !svm_exit_handlers[exit_code]) {
3148 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3149 kvm_run->hw.hardware_exit_reason = exit_code;
3150 return 0;
3151 }
3152
3153 return svm_exit_handlers[exit_code](svm);
3154 }
3155
3156 static void reload_tss(struct kvm_vcpu *vcpu)
3157 {
3158 int cpu = raw_smp_processor_id();
3159
3160 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3161 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3162 load_TR_desc();
3163 }
3164
3165 static void pre_svm_run(struct vcpu_svm *svm)
3166 {
3167 int cpu = raw_smp_processor_id();
3168
3169 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3170
3171 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3172 /* FIXME: handle wraparound of asid_generation */
3173 if (svm->asid_generation != sd->asid_generation)
3174 new_asid(svm, sd);
3175 }
3176
3177 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3178 {
3179 struct vcpu_svm *svm = to_svm(vcpu);
3180
3181 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3182 vcpu->arch.hflags |= HF_NMI_MASK;
3183 set_intercept(svm, INTERCEPT_IRET);
3184 ++vcpu->stat.nmi_injections;
3185 }
3186
3187 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3188 {
3189 struct vmcb_control_area *control;
3190
3191 control = &svm->vmcb->control;
3192 control->int_vector = irq;
3193 control->int_ctl &= ~V_INTR_PRIO_MASK;
3194 control->int_ctl |= V_IRQ_MASK |
3195 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3196 mark_dirty(svm->vmcb, VMCB_INTR);
3197 }
3198
3199 static void svm_set_irq(struct kvm_vcpu *vcpu)
3200 {
3201 struct vcpu_svm *svm = to_svm(vcpu);
3202
3203 BUG_ON(!(gif_set(svm)));
3204
3205 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3206 ++vcpu->stat.irq_injections;
3207
3208 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3209 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3210 }
3211
3212 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3213 {
3214 struct vcpu_svm *svm = to_svm(vcpu);
3215
3216 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3217 return;
3218
3219 if (irr == -1)
3220 return;
3221
3222 if (tpr >= irr)
3223 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3224 }
3225
3226 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3227 {
3228 struct vcpu_svm *svm = to_svm(vcpu);
3229 struct vmcb *vmcb = svm->vmcb;
3230 int ret;
3231 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3232 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3233 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3234
3235 return ret;
3236 }
3237
3238 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3239 {
3240 struct vcpu_svm *svm = to_svm(vcpu);
3241
3242 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3243 }
3244
3245 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3246 {
3247 struct vcpu_svm *svm = to_svm(vcpu);
3248
3249 if (masked) {
3250 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3251 set_intercept(svm, INTERCEPT_IRET);
3252 } else {
3253 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3254 clr_intercept(svm, INTERCEPT_IRET);
3255 }
3256 }
3257
3258 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3259 {
3260 struct vcpu_svm *svm = to_svm(vcpu);
3261 struct vmcb *vmcb = svm->vmcb;
3262 int ret;
3263
3264 if (!gif_set(svm) ||
3265 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3266 return 0;
3267
3268 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3269
3270 if (is_guest_mode(vcpu))
3271 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3272
3273 return ret;
3274 }
3275
3276 static void enable_irq_window(struct kvm_vcpu *vcpu)
3277 {
3278 struct vcpu_svm *svm = to_svm(vcpu);
3279
3280 /*
3281 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3282 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3283 * get that intercept, this function will be called again though and
3284 * we'll get the vintr intercept.
3285 */
3286 if (gif_set(svm) && nested_svm_intr(svm)) {
3287 svm_set_vintr(svm);
3288 svm_inject_irq(svm, 0x0);
3289 }
3290 }
3291
3292 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3293 {
3294 struct vcpu_svm *svm = to_svm(vcpu);
3295
3296 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3297 == HF_NMI_MASK)
3298 return; /* IRET will cause a vm exit */
3299
3300 /*
3301 * Something prevents NMI from been injected. Single step over possible
3302 * problem (IRET or exception injection or interrupt shadow)
3303 */
3304 svm->nmi_singlestep = true;
3305 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3306 update_db_intercept(vcpu);
3307 }
3308
3309 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3310 {
3311 return 0;
3312 }
3313
3314 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3315 {
3316 force_new_asid(vcpu);
3317 }
3318
3319 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3320 {
3321 }
3322
3323 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3324 {
3325 struct vcpu_svm *svm = to_svm(vcpu);
3326
3327 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3328 return;
3329
3330 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3331 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3332 kvm_set_cr8(vcpu, cr8);
3333 }
3334 }
3335
3336 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3337 {
3338 struct vcpu_svm *svm = to_svm(vcpu);
3339 u64 cr8;
3340
3341 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3342 return;
3343
3344 cr8 = kvm_get_cr8(vcpu);
3345 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3346 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3347 }
3348
3349 static void svm_complete_interrupts(struct vcpu_svm *svm)
3350 {
3351 u8 vector;
3352 int type;
3353 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3354 unsigned int3_injected = svm->int3_injected;
3355
3356 svm->int3_injected = 0;
3357
3358 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3359 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3360 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3361 }
3362
3363 svm->vcpu.arch.nmi_injected = false;
3364 kvm_clear_exception_queue(&svm->vcpu);
3365 kvm_clear_interrupt_queue(&svm->vcpu);
3366
3367 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3368 return;
3369
3370 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3371
3372 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3373 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3374
3375 switch (type) {
3376 case SVM_EXITINTINFO_TYPE_NMI:
3377 svm->vcpu.arch.nmi_injected = true;
3378 break;
3379 case SVM_EXITINTINFO_TYPE_EXEPT:
3380 /*
3381 * In case of software exceptions, do not reinject the vector,
3382 * but re-execute the instruction instead. Rewind RIP first
3383 * if we emulated INT3 before.
3384 */
3385 if (kvm_exception_is_soft(vector)) {
3386 if (vector == BP_VECTOR && int3_injected &&
3387 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3388 kvm_rip_write(&svm->vcpu,
3389 kvm_rip_read(&svm->vcpu) -
3390 int3_injected);
3391 break;
3392 }
3393 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3394 u32 err = svm->vmcb->control.exit_int_info_err;
3395 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3396
3397 } else
3398 kvm_requeue_exception(&svm->vcpu, vector);
3399 break;
3400 case SVM_EXITINTINFO_TYPE_INTR:
3401 kvm_queue_interrupt(&svm->vcpu, vector, false);
3402 break;
3403 default:
3404 break;
3405 }
3406 }
3407
3408 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3409 {
3410 struct vcpu_svm *svm = to_svm(vcpu);
3411 struct vmcb_control_area *control = &svm->vmcb->control;
3412
3413 control->exit_int_info = control->event_inj;
3414 control->exit_int_info_err = control->event_inj_err;
3415 control->event_inj = 0;
3416 svm_complete_interrupts(svm);
3417 }
3418
3419 #ifdef CONFIG_X86_64
3420 #define R "r"
3421 #else
3422 #define R "e"
3423 #endif
3424
3425 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3426 {
3427 struct vcpu_svm *svm = to_svm(vcpu);
3428
3429 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3430 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3431 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3432
3433 /*
3434 * A vmexit emulation is required before the vcpu can be executed
3435 * again.
3436 */
3437 if (unlikely(svm->nested.exit_required))
3438 return;
3439
3440 pre_svm_run(svm);
3441
3442 sync_lapic_to_cr8(vcpu);
3443
3444 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3445
3446 clgi();
3447
3448 local_irq_enable();
3449
3450 asm volatile (
3451 "push %%"R"bp; \n\t"
3452 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3453 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3454 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3455 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3456 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3457 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3458 #ifdef CONFIG_X86_64
3459 "mov %c[r8](%[svm]), %%r8 \n\t"
3460 "mov %c[r9](%[svm]), %%r9 \n\t"
3461 "mov %c[r10](%[svm]), %%r10 \n\t"
3462 "mov %c[r11](%[svm]), %%r11 \n\t"
3463 "mov %c[r12](%[svm]), %%r12 \n\t"
3464 "mov %c[r13](%[svm]), %%r13 \n\t"
3465 "mov %c[r14](%[svm]), %%r14 \n\t"
3466 "mov %c[r15](%[svm]), %%r15 \n\t"
3467 #endif
3468
3469 /* Enter guest mode */
3470 "push %%"R"ax \n\t"
3471 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3472 __ex(SVM_VMLOAD) "\n\t"
3473 __ex(SVM_VMRUN) "\n\t"
3474 __ex(SVM_VMSAVE) "\n\t"
3475 "pop %%"R"ax \n\t"
3476
3477 /* Save guest registers, load host registers */
3478 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3479 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3480 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3481 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3482 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3483 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3484 #ifdef CONFIG_X86_64
3485 "mov %%r8, %c[r8](%[svm]) \n\t"
3486 "mov %%r9, %c[r9](%[svm]) \n\t"
3487 "mov %%r10, %c[r10](%[svm]) \n\t"
3488 "mov %%r11, %c[r11](%[svm]) \n\t"
3489 "mov %%r12, %c[r12](%[svm]) \n\t"
3490 "mov %%r13, %c[r13](%[svm]) \n\t"
3491 "mov %%r14, %c[r14](%[svm]) \n\t"
3492 "mov %%r15, %c[r15](%[svm]) \n\t"
3493 #endif
3494 "pop %%"R"bp"
3495 :
3496 : [svm]"a"(svm),
3497 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3498 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3499 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3500 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3501 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3502 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3503 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3504 #ifdef CONFIG_X86_64
3505 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3506 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3507 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3508 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3509 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3510 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3511 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3512 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3513 #endif
3514 : "cc", "memory"
3515 , R"bx", R"cx", R"dx", R"si", R"di"
3516 #ifdef CONFIG_X86_64
3517 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3518 #endif
3519 );
3520
3521 #ifdef CONFIG_X86_64
3522 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3523 #else
3524 loadsegment(fs, svm->host.fs);
3525 #endif
3526
3527 reload_tss(vcpu);
3528
3529 local_irq_disable();
3530
3531 stgi();
3532
3533 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3534 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3535 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3536 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3537
3538 sync_cr8_to_lapic(vcpu);
3539
3540 svm->next_rip = 0;
3541
3542 /* if exit due to PF check for async PF */
3543 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3544 svm->apf_reason = kvm_read_and_reset_pf_reason();
3545
3546 if (npt_enabled) {
3547 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3548 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3549 }
3550
3551 /*
3552 * We need to handle MC intercepts here before the vcpu has a chance to
3553 * change the physical cpu
3554 */
3555 if (unlikely(svm->vmcb->control.exit_code ==
3556 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3557 svm_handle_mce(svm);
3558
3559 mark_all_clean(svm->vmcb);
3560 }
3561
3562 #undef R
3563
3564 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3565 {
3566 struct vcpu_svm *svm = to_svm(vcpu);
3567
3568 svm->vmcb->save.cr3 = root;
3569 mark_dirty(svm->vmcb, VMCB_CR);
3570 force_new_asid(vcpu);
3571 }
3572
3573 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3574 {
3575 struct vcpu_svm *svm = to_svm(vcpu);
3576
3577 svm->vmcb->control.nested_cr3 = root;
3578 mark_dirty(svm->vmcb, VMCB_NPT);
3579
3580 /* Also sync guest cr3 here in case we live migrate */
3581 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3582 mark_dirty(svm->vmcb, VMCB_CR);
3583
3584 force_new_asid(vcpu);
3585 }
3586
3587 static int is_disabled(void)
3588 {
3589 u64 vm_cr;
3590
3591 rdmsrl(MSR_VM_CR, vm_cr);
3592 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3593 return 1;
3594
3595 return 0;
3596 }
3597
3598 static void
3599 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3600 {
3601 /*
3602 * Patch in the VMMCALL instruction:
3603 */
3604 hypercall[0] = 0x0f;
3605 hypercall[1] = 0x01;
3606 hypercall[2] = 0xd9;
3607 }
3608
3609 static void svm_check_processor_compat(void *rtn)
3610 {
3611 *(int *)rtn = 0;
3612 }
3613
3614 static bool svm_cpu_has_accelerated_tpr(void)
3615 {
3616 return false;
3617 }
3618
3619 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3620 {
3621 return 0;
3622 }
3623
3624 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3625 {
3626 }
3627
3628 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3629 {
3630 switch (func) {
3631 case 0x00000001:
3632 /* Mask out xsave bit as long as it is not supported by SVM */
3633 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3634 break;
3635 case 0x80000001:
3636 if (nested)
3637 entry->ecx |= (1 << 2); /* Set SVM bit */
3638 break;
3639 case 0x8000000A:
3640 entry->eax = 1; /* SVM revision 1 */
3641 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3642 ASID emulation to nested SVM */
3643 entry->ecx = 0; /* Reserved */
3644 entry->edx = 0; /* Per default do not support any
3645 additional features */
3646
3647 /* Support next_rip if host supports it */
3648 if (boot_cpu_has(X86_FEATURE_NRIPS))
3649 entry->edx |= SVM_FEATURE_NRIP;
3650
3651 /* Support NPT for the guest if enabled */
3652 if (npt_enabled)
3653 entry->edx |= SVM_FEATURE_NPT;
3654
3655 break;
3656 }
3657 }
3658
3659 static const struct trace_print_flags svm_exit_reasons_str[] = {
3660 { SVM_EXIT_READ_CR0, "read_cr0" },
3661 { SVM_EXIT_READ_CR3, "read_cr3" },
3662 { SVM_EXIT_READ_CR4, "read_cr4" },
3663 { SVM_EXIT_READ_CR8, "read_cr8" },
3664 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3665 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3666 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3667 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3668 { SVM_EXIT_READ_DR0, "read_dr0" },
3669 { SVM_EXIT_READ_DR1, "read_dr1" },
3670 { SVM_EXIT_READ_DR2, "read_dr2" },
3671 { SVM_EXIT_READ_DR3, "read_dr3" },
3672 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3673 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3674 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3675 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3676 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3677 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3678 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3679 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3680 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3681 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3682 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3683 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3684 { SVM_EXIT_INTR, "interrupt" },
3685 { SVM_EXIT_NMI, "nmi" },
3686 { SVM_EXIT_SMI, "smi" },
3687 { SVM_EXIT_INIT, "init" },
3688 { SVM_EXIT_VINTR, "vintr" },
3689 { SVM_EXIT_CPUID, "cpuid" },
3690 { SVM_EXIT_INVD, "invd" },
3691 { SVM_EXIT_HLT, "hlt" },
3692 { SVM_EXIT_INVLPG, "invlpg" },
3693 { SVM_EXIT_INVLPGA, "invlpga" },
3694 { SVM_EXIT_IOIO, "io" },
3695 { SVM_EXIT_MSR, "msr" },
3696 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3697 { SVM_EXIT_SHUTDOWN, "shutdown" },
3698 { SVM_EXIT_VMRUN, "vmrun" },
3699 { SVM_EXIT_VMMCALL, "hypercall" },
3700 { SVM_EXIT_VMLOAD, "vmload" },
3701 { SVM_EXIT_VMSAVE, "vmsave" },
3702 { SVM_EXIT_STGI, "stgi" },
3703 { SVM_EXIT_CLGI, "clgi" },
3704 { SVM_EXIT_SKINIT, "skinit" },
3705 { SVM_EXIT_WBINVD, "wbinvd" },
3706 { SVM_EXIT_MONITOR, "monitor" },
3707 { SVM_EXIT_MWAIT, "mwait" },
3708 { SVM_EXIT_NPF, "npf" },
3709 { -1, NULL }
3710 };
3711
3712 static int svm_get_lpage_level(void)
3713 {
3714 return PT_PDPE_LEVEL;
3715 }
3716
3717 static bool svm_rdtscp_supported(void)
3718 {
3719 return false;
3720 }
3721
3722 static bool svm_has_wbinvd_exit(void)
3723 {
3724 return true;
3725 }
3726
3727 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3728 {
3729 struct vcpu_svm *svm = to_svm(vcpu);
3730
3731 set_exception_intercept(svm, NM_VECTOR);
3732 update_cr0_intercept(svm);
3733 }
3734
3735 static struct kvm_x86_ops svm_x86_ops = {
3736 .cpu_has_kvm_support = has_svm,
3737 .disabled_by_bios = is_disabled,
3738 .hardware_setup = svm_hardware_setup,
3739 .hardware_unsetup = svm_hardware_unsetup,
3740 .check_processor_compatibility = svm_check_processor_compat,
3741 .hardware_enable = svm_hardware_enable,
3742 .hardware_disable = svm_hardware_disable,
3743 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3744
3745 .vcpu_create = svm_create_vcpu,
3746 .vcpu_free = svm_free_vcpu,
3747 .vcpu_reset = svm_vcpu_reset,
3748
3749 .prepare_guest_switch = svm_prepare_guest_switch,
3750 .vcpu_load = svm_vcpu_load,
3751 .vcpu_put = svm_vcpu_put,
3752
3753 .set_guest_debug = svm_guest_debug,
3754 .get_msr = svm_get_msr,
3755 .set_msr = svm_set_msr,
3756 .get_segment_base = svm_get_segment_base,
3757 .get_segment = svm_get_segment,
3758 .set_segment = svm_set_segment,
3759 .get_cpl = svm_get_cpl,
3760 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3761 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3762 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3763 .set_cr0 = svm_set_cr0,
3764 .set_cr3 = svm_set_cr3,
3765 .set_cr4 = svm_set_cr4,
3766 .set_efer = svm_set_efer,
3767 .get_idt = svm_get_idt,
3768 .set_idt = svm_set_idt,
3769 .get_gdt = svm_get_gdt,
3770 .set_gdt = svm_set_gdt,
3771 .set_dr7 = svm_set_dr7,
3772 .cache_reg = svm_cache_reg,
3773 .get_rflags = svm_get_rflags,
3774 .set_rflags = svm_set_rflags,
3775 .fpu_activate = svm_fpu_activate,
3776 .fpu_deactivate = svm_fpu_deactivate,
3777
3778 .tlb_flush = svm_flush_tlb,
3779
3780 .run = svm_vcpu_run,
3781 .handle_exit = handle_exit,
3782 .skip_emulated_instruction = skip_emulated_instruction,
3783 .set_interrupt_shadow = svm_set_interrupt_shadow,
3784 .get_interrupt_shadow = svm_get_interrupt_shadow,
3785 .patch_hypercall = svm_patch_hypercall,
3786 .set_irq = svm_set_irq,
3787 .set_nmi = svm_inject_nmi,
3788 .queue_exception = svm_queue_exception,
3789 .cancel_injection = svm_cancel_injection,
3790 .interrupt_allowed = svm_interrupt_allowed,
3791 .nmi_allowed = svm_nmi_allowed,
3792 .get_nmi_mask = svm_get_nmi_mask,
3793 .set_nmi_mask = svm_set_nmi_mask,
3794 .enable_nmi_window = enable_nmi_window,
3795 .enable_irq_window = enable_irq_window,
3796 .update_cr8_intercept = update_cr8_intercept,
3797
3798 .set_tss_addr = svm_set_tss_addr,
3799 .get_tdp_level = get_npt_level,
3800 .get_mt_mask = svm_get_mt_mask,
3801
3802 .get_exit_info = svm_get_exit_info,
3803 .exit_reasons_str = svm_exit_reasons_str,
3804
3805 .get_lpage_level = svm_get_lpage_level,
3806
3807 .cpuid_update = svm_cpuid_update,
3808
3809 .rdtscp_supported = svm_rdtscp_supported,
3810
3811 .set_supported_cpuid = svm_set_supported_cpuid,
3812
3813 .has_wbinvd_exit = svm_has_wbinvd_exit,
3814
3815 .write_tsc_offset = svm_write_tsc_offset,
3816 .adjust_tsc_offset = svm_adjust_tsc_offset,
3817
3818 .set_tdp_cr3 = set_tdp_cr3,
3819 };
3820
3821 static int __init svm_init(void)
3822 {
3823 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3824 __alignof__(struct vcpu_svm), THIS_MODULE);
3825 }
3826
3827 static void __exit svm_exit(void)
3828 {
3829 kvm_exit();
3830 }
3831
3832 module_init(svm_init)
3833 module_exit(svm_exit)
Linux kernel - Deliverables
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