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Revert "KVM: svm: handle KVM_X86_QUIRK_CD_NW_CLEARED in svm_get_mt_mask"
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24 #include "pmu.h"
25
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
37 #include <asm/desc.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
40
41 #include <asm/virtext.h>
42 #include "trace.h"
43
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
48
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
51 {}
52 };
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
57
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
60
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
80
81 static bool erratum_383_found __read_mostly;
82
83 static const u32 host_save_user_msrs[] = {
84 #ifdef CONFIG_X86_64
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
86 MSR_FS_BASE,
87 #endif
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
89 };
90
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
92
93 struct kvm_vcpu;
94
95 struct nested_state {
96 struct vmcb *hsave;
97 u64 hsave_msr;
98 u64 vm_cr_msr;
99 u64 vmcb;
100
101 /* These are the merged vectors */
102 u32 *msrpm;
103
104 /* gpa pointers to the real vectors */
105 u64 vmcb_msrpm;
106 u64 vmcb_iopm;
107
108 /* A VMEXIT is required but not yet emulated */
109 bool exit_required;
110
111 /* cache for intercepts of the guest */
112 u32 intercept_cr;
113 u32 intercept_dr;
114 u32 intercept_exceptions;
115 u64 intercept;
116
117 /* Nested Paging related state */
118 u64 nested_cr3;
119 };
120
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
123
124 /*
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
127 */
128 static uint64_t osvw_len = 4, osvw_status;
129
130 struct vcpu_svm {
131 struct kvm_vcpu vcpu;
132 struct vmcb *vmcb;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
138
139 u64 next_rip;
140
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
142 struct {
143 u16 fs;
144 u16 gs;
145 u16 ldt;
146 u64 gs_base;
147 } host;
148
149 u32 *msrpm;
150
151 ulong nmi_iret_rip;
152
153 struct nested_state nested;
154
155 bool nmi_singlestep;
156
157 unsigned int3_injected;
158 unsigned long int3_rip;
159 u32 apf_reason;
160
161 u64 tsc_ratio;
162 };
163
164 static DEFINE_PER_CPU(u64, current_tsc_ratio);
165 #define TSC_RATIO_DEFAULT 0x0100000000ULL
166
167 #define MSR_INVALID 0xffffffffU
168
169 static const struct svm_direct_access_msrs {
170 u32 index; /* Index of the MSR */
171 bool always; /* True if intercept is always on */
172 } direct_access_msrs[] = {
173 { .index = MSR_STAR, .always = true },
174 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175 #ifdef CONFIG_X86_64
176 { .index = MSR_GS_BASE, .always = true },
177 { .index = MSR_FS_BASE, .always = true },
178 { .index = MSR_KERNEL_GS_BASE, .always = true },
179 { .index = MSR_LSTAR, .always = true },
180 { .index = MSR_CSTAR, .always = true },
181 { .index = MSR_SYSCALL_MASK, .always = true },
182 #endif
183 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
184 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
185 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
186 { .index = MSR_IA32_LASTINTTOIP, .always = false },
187 { .index = MSR_INVALID, .always = false },
188 };
189
190 /* enable NPT for AMD64 and X86 with PAE */
191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192 static bool npt_enabled = true;
193 #else
194 static bool npt_enabled;
195 #endif
196
197 /* allow nested paging (virtualized MMU) for all guests */
198 static int npt = true;
199 module_param(npt, int, S_IRUGO);
200
201 /* allow nested virtualization in KVM/SVM */
202 static int nested = true;
203 module_param(nested, int, S_IRUGO);
204
205 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
206 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
207 static void svm_complete_interrupts(struct vcpu_svm *svm);
208
209 static int nested_svm_exit_handled(struct vcpu_svm *svm);
210 static int nested_svm_intercept(struct vcpu_svm *svm);
211 static int nested_svm_vmexit(struct vcpu_svm *svm);
212 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
213 bool has_error_code, u32 error_code);
214 static u64 __scale_tsc(u64 ratio, u64 tsc);
215
216 enum {
217 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
218 pause filter count */
219 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
220 VMCB_ASID, /* ASID */
221 VMCB_INTR, /* int_ctl, int_vector */
222 VMCB_NPT, /* npt_en, nCR3, gPAT */
223 VMCB_CR, /* CR0, CR3, CR4, EFER */
224 VMCB_DR, /* DR6, DR7 */
225 VMCB_DT, /* GDT, IDT */
226 VMCB_SEG, /* CS, DS, SS, ES, CPL */
227 VMCB_CR2, /* CR2 only */
228 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
229 VMCB_DIRTY_MAX,
230 };
231
232 /* TPR and CR2 are always written before VMRUN */
233 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
234
235 static inline void mark_all_dirty(struct vmcb *vmcb)
236 {
237 vmcb->control.clean = 0;
238 }
239
240 static inline void mark_all_clean(struct vmcb *vmcb)
241 {
242 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
243 & ~VMCB_ALWAYS_DIRTY_MASK;
244 }
245
246 static inline void mark_dirty(struct vmcb *vmcb, int bit)
247 {
248 vmcb->control.clean &= ~(1 << bit);
249 }
250
251 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
252 {
253 return container_of(vcpu, struct vcpu_svm, vcpu);
254 }
255
256 static void recalc_intercepts(struct vcpu_svm *svm)
257 {
258 struct vmcb_control_area *c, *h;
259 struct nested_state *g;
260
261 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
262
263 if (!is_guest_mode(&svm->vcpu))
264 return;
265
266 c = &svm->vmcb->control;
267 h = &svm->nested.hsave->control;
268 g = &svm->nested;
269
270 c->intercept_cr = h->intercept_cr | g->intercept_cr;
271 c->intercept_dr = h->intercept_dr | g->intercept_dr;
272 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
273 c->intercept = h->intercept | g->intercept;
274 }
275
276 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
277 {
278 if (is_guest_mode(&svm->vcpu))
279 return svm->nested.hsave;
280 else
281 return svm->vmcb;
282 }
283
284 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
285 {
286 struct vmcb *vmcb = get_host_vmcb(svm);
287
288 vmcb->control.intercept_cr |= (1U << bit);
289
290 recalc_intercepts(svm);
291 }
292
293 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
294 {
295 struct vmcb *vmcb = get_host_vmcb(svm);
296
297 vmcb->control.intercept_cr &= ~(1U << bit);
298
299 recalc_intercepts(svm);
300 }
301
302 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
303 {
304 struct vmcb *vmcb = get_host_vmcb(svm);
305
306 return vmcb->control.intercept_cr & (1U << bit);
307 }
308
309 static inline void set_dr_intercepts(struct vcpu_svm *svm)
310 {
311 struct vmcb *vmcb = get_host_vmcb(svm);
312
313 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
314 | (1 << INTERCEPT_DR1_READ)
315 | (1 << INTERCEPT_DR2_READ)
316 | (1 << INTERCEPT_DR3_READ)
317 | (1 << INTERCEPT_DR4_READ)
318 | (1 << INTERCEPT_DR5_READ)
319 | (1 << INTERCEPT_DR6_READ)
320 | (1 << INTERCEPT_DR7_READ)
321 | (1 << INTERCEPT_DR0_WRITE)
322 | (1 << INTERCEPT_DR1_WRITE)
323 | (1 << INTERCEPT_DR2_WRITE)
324 | (1 << INTERCEPT_DR3_WRITE)
325 | (1 << INTERCEPT_DR4_WRITE)
326 | (1 << INTERCEPT_DR5_WRITE)
327 | (1 << INTERCEPT_DR6_WRITE)
328 | (1 << INTERCEPT_DR7_WRITE);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
334 {
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_dr = 0;
338
339 recalc_intercepts(svm);
340 }
341
342 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
343 {
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept_exceptions |= (1U << bit);
347
348 recalc_intercepts(svm);
349 }
350
351 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
352 {
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept_exceptions &= ~(1U << bit);
356
357 recalc_intercepts(svm);
358 }
359
360 static inline void set_intercept(struct vcpu_svm *svm, int bit)
361 {
362 struct vmcb *vmcb = get_host_vmcb(svm);
363
364 vmcb->control.intercept |= (1ULL << bit);
365
366 recalc_intercepts(svm);
367 }
368
369 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
370 {
371 struct vmcb *vmcb = get_host_vmcb(svm);
372
373 vmcb->control.intercept &= ~(1ULL << bit);
374
375 recalc_intercepts(svm);
376 }
377
378 static inline void enable_gif(struct vcpu_svm *svm)
379 {
380 svm->vcpu.arch.hflags |= HF_GIF_MASK;
381 }
382
383 static inline void disable_gif(struct vcpu_svm *svm)
384 {
385 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
386 }
387
388 static inline bool gif_set(struct vcpu_svm *svm)
389 {
390 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
391 }
392
393 static unsigned long iopm_base;
394
395 struct kvm_ldttss_desc {
396 u16 limit0;
397 u16 base0;
398 unsigned base1:8, type:5, dpl:2, p:1;
399 unsigned limit1:4, zero0:3, g:1, base2:8;
400 u32 base3;
401 u32 zero1;
402 } __attribute__((packed));
403
404 struct svm_cpu_data {
405 int cpu;
406
407 u64 asid_generation;
408 u32 max_asid;
409 u32 next_asid;
410 struct kvm_ldttss_desc *tss_desc;
411
412 struct page *save_area;
413 };
414
415 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
416
417 struct svm_init_data {
418 int cpu;
419 int r;
420 };
421
422 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
423
424 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
425 #define MSRS_RANGE_SIZE 2048
426 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
427
428 static u32 svm_msrpm_offset(u32 msr)
429 {
430 u32 offset;
431 int i;
432
433 for (i = 0; i < NUM_MSR_MAPS; i++) {
434 if (msr < msrpm_ranges[i] ||
435 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
436 continue;
437
438 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
439 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
440
441 /* Now we have the u8 offset - but need the u32 offset */
442 return offset / 4;
443 }
444
445 /* MSR not in any range */
446 return MSR_INVALID;
447 }
448
449 #define MAX_INST_SIZE 15
450
451 static inline void clgi(void)
452 {
453 asm volatile (__ex(SVM_CLGI));
454 }
455
456 static inline void stgi(void)
457 {
458 asm volatile (__ex(SVM_STGI));
459 }
460
461 static inline void invlpga(unsigned long addr, u32 asid)
462 {
463 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
464 }
465
466 static int get_npt_level(void)
467 {
468 #ifdef CONFIG_X86_64
469 return PT64_ROOT_LEVEL;
470 #else
471 return PT32E_ROOT_LEVEL;
472 #endif
473 }
474
475 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
476 {
477 vcpu->arch.efer = efer;
478 if (!npt_enabled && !(efer & EFER_LMA))
479 efer &= ~EFER_LME;
480
481 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
482 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
483 }
484
485 static int is_external_interrupt(u32 info)
486 {
487 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
488 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
489 }
490
491 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
492 {
493 struct vcpu_svm *svm = to_svm(vcpu);
494 u32 ret = 0;
495
496 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
497 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
498 return ret;
499 }
500
501 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
502 {
503 struct vcpu_svm *svm = to_svm(vcpu);
504
505 if (mask == 0)
506 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
507 else
508 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
509
510 }
511
512 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
513 {
514 struct vcpu_svm *svm = to_svm(vcpu);
515
516 if (svm->vmcb->control.next_rip != 0) {
517 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS));
518 svm->next_rip = svm->vmcb->control.next_rip;
519 }
520
521 if (!svm->next_rip) {
522 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
523 EMULATE_DONE)
524 printk(KERN_DEBUG "%s: NOP\n", __func__);
525 return;
526 }
527 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
528 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
529 __func__, kvm_rip_read(vcpu), svm->next_rip);
530
531 kvm_rip_write(vcpu, svm->next_rip);
532 svm_set_interrupt_shadow(vcpu, 0);
533 }
534
535 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
536 bool has_error_code, u32 error_code,
537 bool reinject)
538 {
539 struct vcpu_svm *svm = to_svm(vcpu);
540
541 /*
542 * If we are within a nested VM we'd better #VMEXIT and let the guest
543 * handle the exception
544 */
545 if (!reinject &&
546 nested_svm_check_exception(svm, nr, has_error_code, error_code))
547 return;
548
549 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
550 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
551
552 /*
553 * For guest debugging where we have to reinject #BP if some
554 * INT3 is guest-owned:
555 * Emulate nRIP by moving RIP forward. Will fail if injection
556 * raises a fault that is not intercepted. Still better than
557 * failing in all cases.
558 */
559 skip_emulated_instruction(&svm->vcpu);
560 rip = kvm_rip_read(&svm->vcpu);
561 svm->int3_rip = rip + svm->vmcb->save.cs.base;
562 svm->int3_injected = rip - old_rip;
563 }
564
565 svm->vmcb->control.event_inj = nr
566 | SVM_EVTINJ_VALID
567 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
568 | SVM_EVTINJ_TYPE_EXEPT;
569 svm->vmcb->control.event_inj_err = error_code;
570 }
571
572 static void svm_init_erratum_383(void)
573 {
574 u32 low, high;
575 int err;
576 u64 val;
577
578 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
579 return;
580
581 /* Use _safe variants to not break nested virtualization */
582 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
583 if (err)
584 return;
585
586 val |= (1ULL << 47);
587
588 low = lower_32_bits(val);
589 high = upper_32_bits(val);
590
591 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
592
593 erratum_383_found = true;
594 }
595
596 static void svm_init_osvw(struct kvm_vcpu *vcpu)
597 {
598 /*
599 * Guests should see errata 400 and 415 as fixed (assuming that
600 * HLT and IO instructions are intercepted).
601 */
602 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
603 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
604
605 /*
606 * By increasing VCPU's osvw.length to 3 we are telling the guest that
607 * all osvw.status bits inside that length, including bit 0 (which is
608 * reserved for erratum 298), are valid. However, if host processor's
609 * osvw_len is 0 then osvw_status[0] carries no information. We need to
610 * be conservative here and therefore we tell the guest that erratum 298
611 * is present (because we really don't know).
612 */
613 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
614 vcpu->arch.osvw.status |= 1;
615 }
616
617 static int has_svm(void)
618 {
619 const char *msg;
620
621 if (!cpu_has_svm(&msg)) {
622 printk(KERN_INFO "has_svm: %s\n", msg);
623 return 0;
624 }
625
626 return 1;
627 }
628
629 static void svm_hardware_disable(void)
630 {
631 /* Make sure we clean up behind us */
632 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
633 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
634
635 cpu_svm_disable();
636
637 amd_pmu_disable_virt();
638 }
639
640 static int svm_hardware_enable(void)
641 {
642
643 struct svm_cpu_data *sd;
644 uint64_t efer;
645 struct desc_ptr gdt_descr;
646 struct desc_struct *gdt;
647 int me = raw_smp_processor_id();
648
649 rdmsrl(MSR_EFER, efer);
650 if (efer & EFER_SVME)
651 return -EBUSY;
652
653 if (!has_svm()) {
654 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
655 return -EINVAL;
656 }
657 sd = per_cpu(svm_data, me);
658 if (!sd) {
659 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
660 return -EINVAL;
661 }
662
663 sd->asid_generation = 1;
664 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
665 sd->next_asid = sd->max_asid + 1;
666
667 native_store_gdt(&gdt_descr);
668 gdt = (struct desc_struct *)gdt_descr.address;
669 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
670
671 wrmsrl(MSR_EFER, efer | EFER_SVME);
672
673 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
674
675 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
676 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
677 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
678 }
679
680
681 /*
682 * Get OSVW bits.
683 *
684 * Note that it is possible to have a system with mixed processor
685 * revisions and therefore different OSVW bits. If bits are not the same
686 * on different processors then choose the worst case (i.e. if erratum
687 * is present on one processor and not on another then assume that the
688 * erratum is present everywhere).
689 */
690 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
691 uint64_t len, status = 0;
692 int err;
693
694 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
695 if (!err)
696 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
697 &err);
698
699 if (err)
700 osvw_status = osvw_len = 0;
701 else {
702 if (len < osvw_len)
703 osvw_len = len;
704 osvw_status |= status;
705 osvw_status &= (1ULL << osvw_len) - 1;
706 }
707 } else
708 osvw_status = osvw_len = 0;
709
710 svm_init_erratum_383();
711
712 amd_pmu_enable_virt();
713
714 return 0;
715 }
716
717 static void svm_cpu_uninit(int cpu)
718 {
719 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
720
721 if (!sd)
722 return;
723
724 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
725 __free_page(sd->save_area);
726 kfree(sd);
727 }
728
729 static int svm_cpu_init(int cpu)
730 {
731 struct svm_cpu_data *sd;
732 int r;
733
734 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
735 if (!sd)
736 return -ENOMEM;
737 sd->cpu = cpu;
738 sd->save_area = alloc_page(GFP_KERNEL);
739 r = -ENOMEM;
740 if (!sd->save_area)
741 goto err_1;
742
743 per_cpu(svm_data, cpu) = sd;
744
745 return 0;
746
747 err_1:
748 kfree(sd);
749 return r;
750
751 }
752
753 static bool valid_msr_intercept(u32 index)
754 {
755 int i;
756
757 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
758 if (direct_access_msrs[i].index == index)
759 return true;
760
761 return false;
762 }
763
764 static void set_msr_interception(u32 *msrpm, unsigned msr,
765 int read, int write)
766 {
767 u8 bit_read, bit_write;
768 unsigned long tmp;
769 u32 offset;
770
771 /*
772 * If this warning triggers extend the direct_access_msrs list at the
773 * beginning of the file
774 */
775 WARN_ON(!valid_msr_intercept(msr));
776
777 offset = svm_msrpm_offset(msr);
778 bit_read = 2 * (msr & 0x0f);
779 bit_write = 2 * (msr & 0x0f) + 1;
780 tmp = msrpm[offset];
781
782 BUG_ON(offset == MSR_INVALID);
783
784 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
785 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
786
787 msrpm[offset] = tmp;
788 }
789
790 static void svm_vcpu_init_msrpm(u32 *msrpm)
791 {
792 int i;
793
794 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
795
796 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
797 if (!direct_access_msrs[i].always)
798 continue;
799
800 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
801 }
802 }
803
804 static void add_msr_offset(u32 offset)
805 {
806 int i;
807
808 for (i = 0; i < MSRPM_OFFSETS; ++i) {
809
810 /* Offset already in list? */
811 if (msrpm_offsets[i] == offset)
812 return;
813
814 /* Slot used by another offset? */
815 if (msrpm_offsets[i] != MSR_INVALID)
816 continue;
817
818 /* Add offset to list */
819 msrpm_offsets[i] = offset;
820
821 return;
822 }
823
824 /*
825 * If this BUG triggers the msrpm_offsets table has an overflow. Just
826 * increase MSRPM_OFFSETS in this case.
827 */
828 BUG();
829 }
830
831 static void init_msrpm_offsets(void)
832 {
833 int i;
834
835 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
836
837 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
838 u32 offset;
839
840 offset = svm_msrpm_offset(direct_access_msrs[i].index);
841 BUG_ON(offset == MSR_INVALID);
842
843 add_msr_offset(offset);
844 }
845 }
846
847 static void svm_enable_lbrv(struct vcpu_svm *svm)
848 {
849 u32 *msrpm = svm->msrpm;
850
851 svm->vmcb->control.lbr_ctl = 1;
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
855 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
856 }
857
858 static void svm_disable_lbrv(struct vcpu_svm *svm)
859 {
860 u32 *msrpm = svm->msrpm;
861
862 svm->vmcb->control.lbr_ctl = 0;
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
866 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
867 }
868
869 #define MTRR_TYPE_UC_MINUS 7
870 #define MTRR2PROTVAL_INVALID 0xff
871
872 static u8 mtrr2protval[8];
873
874 static u8 fallback_mtrr_type(int mtrr)
875 {
876 /*
877 * WT and WP aren't always available in the host PAT. Treat
878 * them as UC and UC- respectively. Everything else should be
879 * there.
880 */
881 switch (mtrr)
882 {
883 case MTRR_TYPE_WRTHROUGH:
884 return MTRR_TYPE_UNCACHABLE;
885 case MTRR_TYPE_WRPROT:
886 return MTRR_TYPE_UC_MINUS;
887 default:
888 BUG();
889 }
890 }
891
892 static void build_mtrr2protval(void)
893 {
894 int i;
895 u64 pat;
896
897 for (i = 0; i < 8; i++)
898 mtrr2protval[i] = MTRR2PROTVAL_INVALID;
899
900 /* Ignore the invalid MTRR types. */
901 mtrr2protval[2] = 0;
902 mtrr2protval[3] = 0;
903
904 /*
905 * Use host PAT value to figure out the mapping from guest MTRR
906 * values to nested page table PAT/PCD/PWT values. We do not
907 * want to change the host PAT value every time we enter the
908 * guest.
909 */
910 rdmsrl(MSR_IA32_CR_PAT, pat);
911 for (i = 0; i < 8; i++) {
912 u8 mtrr = pat >> (8 * i);
913
914 if (mtrr2protval[mtrr] == MTRR2PROTVAL_INVALID)
915 mtrr2protval[mtrr] = __cm_idx2pte(i);
916 }
917
918 for (i = 0; i < 8; i++) {
919 if (mtrr2protval[i] == MTRR2PROTVAL_INVALID) {
920 u8 fallback = fallback_mtrr_type(i);
921 mtrr2protval[i] = mtrr2protval[fallback];
922 BUG_ON(mtrr2protval[i] == MTRR2PROTVAL_INVALID);
923 }
924 }
925 }
926
927 static __init int svm_hardware_setup(void)
928 {
929 int cpu;
930 struct page *iopm_pages;
931 void *iopm_va;
932 int r;
933
934 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
935
936 if (!iopm_pages)
937 return -ENOMEM;
938
939 iopm_va = page_address(iopm_pages);
940 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
941 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
942
943 init_msrpm_offsets();
944
945 if (boot_cpu_has(X86_FEATURE_NX))
946 kvm_enable_efer_bits(EFER_NX);
947
948 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
949 kvm_enable_efer_bits(EFER_FFXSR);
950
951 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
952 u64 max;
953
954 kvm_has_tsc_control = true;
955
956 /*
957 * Make sure the user can only configure tsc_khz values that
958 * fit into a signed integer.
959 * A min value is not calculated needed because it will always
960 * be 1 on all machines and a value of 0 is used to disable
961 * tsc-scaling for the vcpu.
962 */
963 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
964
965 kvm_max_guest_tsc_khz = max;
966 }
967
968 if (nested) {
969 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
970 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
971 }
972
973 for_each_possible_cpu(cpu) {
974 r = svm_cpu_init(cpu);
975 if (r)
976 goto err;
977 }
978
979 if (!boot_cpu_has(X86_FEATURE_NPT))
980 npt_enabled = false;
981
982 if (npt_enabled && !npt) {
983 printk(KERN_INFO "kvm: Nested Paging disabled\n");
984 npt_enabled = false;
985 }
986
987 if (npt_enabled) {
988 printk(KERN_INFO "kvm: Nested Paging enabled\n");
989 kvm_enable_tdp();
990 } else
991 kvm_disable_tdp();
992
993 build_mtrr2protval();
994 return 0;
995
996 err:
997 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
998 iopm_base = 0;
999 return r;
1000 }
1001
1002 static __exit void svm_hardware_unsetup(void)
1003 {
1004 int cpu;
1005
1006 for_each_possible_cpu(cpu)
1007 svm_cpu_uninit(cpu);
1008
1009 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1010 iopm_base = 0;
1011 }
1012
1013 static void init_seg(struct vmcb_seg *seg)
1014 {
1015 seg->selector = 0;
1016 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1017 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1018 seg->limit = 0xffff;
1019 seg->base = 0;
1020 }
1021
1022 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1023 {
1024 seg->selector = 0;
1025 seg->attrib = SVM_SELECTOR_P_MASK | type;
1026 seg->limit = 0xffff;
1027 seg->base = 0;
1028 }
1029
1030 static u64 __scale_tsc(u64 ratio, u64 tsc)
1031 {
1032 u64 mult, frac, _tsc;
1033
1034 mult = ratio >> 32;
1035 frac = ratio & ((1ULL << 32) - 1);
1036
1037 _tsc = tsc;
1038 _tsc *= mult;
1039 _tsc += (tsc >> 32) * frac;
1040 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
1041
1042 return _tsc;
1043 }
1044
1045 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1046 {
1047 struct vcpu_svm *svm = to_svm(vcpu);
1048 u64 _tsc = tsc;
1049
1050 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1051 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
1052
1053 return _tsc;
1054 }
1055
1056 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1057 {
1058 struct vcpu_svm *svm = to_svm(vcpu);
1059 u64 ratio;
1060 u64 khz;
1061
1062 /* Guest TSC same frequency as host TSC? */
1063 if (!scale) {
1064 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1065 return;
1066 }
1067
1068 /* TSC scaling supported? */
1069 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1070 if (user_tsc_khz > tsc_khz) {
1071 vcpu->arch.tsc_catchup = 1;
1072 vcpu->arch.tsc_always_catchup = 1;
1073 } else
1074 WARN(1, "user requested TSC rate below hardware speed\n");
1075 return;
1076 }
1077
1078 khz = user_tsc_khz;
1079
1080 /* TSC scaling required - calculate ratio */
1081 ratio = khz << 32;
1082 do_div(ratio, tsc_khz);
1083
1084 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1085 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1086 user_tsc_khz);
1087 return;
1088 }
1089 svm->tsc_ratio = ratio;
1090 }
1091
1092 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1093 {
1094 struct vcpu_svm *svm = to_svm(vcpu);
1095
1096 return svm->vmcb->control.tsc_offset;
1097 }
1098
1099 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1100 {
1101 struct vcpu_svm *svm = to_svm(vcpu);
1102 u64 g_tsc_offset = 0;
1103
1104 if (is_guest_mode(vcpu)) {
1105 g_tsc_offset = svm->vmcb->control.tsc_offset -
1106 svm->nested.hsave->control.tsc_offset;
1107 svm->nested.hsave->control.tsc_offset = offset;
1108 } else
1109 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1110 svm->vmcb->control.tsc_offset,
1111 offset);
1112
1113 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1114
1115 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1116 }
1117
1118 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1119 {
1120 struct vcpu_svm *svm = to_svm(vcpu);
1121
1122 if (host) {
1123 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1124 WARN_ON(adjustment < 0);
1125 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1126 }
1127
1128 svm->vmcb->control.tsc_offset += adjustment;
1129 if (is_guest_mode(vcpu))
1130 svm->nested.hsave->control.tsc_offset += adjustment;
1131 else
1132 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1133 svm->vmcb->control.tsc_offset - adjustment,
1134 svm->vmcb->control.tsc_offset);
1135
1136 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1137 }
1138
1139 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1140 {
1141 u64 tsc;
1142
1143 tsc = svm_scale_tsc(vcpu, rdtsc());
1144
1145 return target_tsc - tsc;
1146 }
1147
1148 static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
1149 {
1150 struct kvm_vcpu *vcpu = &svm->vcpu;
1151
1152 /* Unlike Intel, AMD takes the guest's CR0.CD into account.
1153 *
1154 * AMD does not have IPAT. To emulate it for the case of guests
1155 * with no assigned devices, just set everything to WB. If guests
1156 * have assigned devices, however, we cannot force WB for RAM
1157 * pages only, so use the guest PAT directly.
1158 */
1159 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1160 *g_pat = 0x0606060606060606;
1161 else
1162 *g_pat = vcpu->arch.pat;
1163 }
1164
1165 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
1166 {
1167 u8 mtrr;
1168
1169 /*
1170 * 1. MMIO: always map as UC
1171 * 2. No passthrough: always map as WB, and force guest PAT to WB as well
1172 * 3. Passthrough: can't guarantee the result, try to trust guest.
1173 */
1174 if (is_mmio)
1175 return _PAGE_NOCACHE;
1176
1177 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1178 return 0;
1179
1180 mtrr = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
1181 return mtrr2protval[mtrr];
1182 }
1183
1184 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1185 {
1186 struct vmcb_control_area *control = &svm->vmcb->control;
1187 struct vmcb_save_area *save = &svm->vmcb->save;
1188
1189 svm->vcpu.fpu_active = 1;
1190 svm->vcpu.arch.hflags = 0;
1191
1192 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1193 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1194 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1195 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1196 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1197 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1198 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1199
1200 set_dr_intercepts(svm);
1201
1202 set_exception_intercept(svm, PF_VECTOR);
1203 set_exception_intercept(svm, UD_VECTOR);
1204 set_exception_intercept(svm, MC_VECTOR);
1205
1206 set_intercept(svm, INTERCEPT_INTR);
1207 set_intercept(svm, INTERCEPT_NMI);
1208 set_intercept(svm, INTERCEPT_SMI);
1209 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1210 set_intercept(svm, INTERCEPT_RDPMC);
1211 set_intercept(svm, INTERCEPT_CPUID);
1212 set_intercept(svm, INTERCEPT_INVD);
1213 set_intercept(svm, INTERCEPT_HLT);
1214 set_intercept(svm, INTERCEPT_INVLPG);
1215 set_intercept(svm, INTERCEPT_INVLPGA);
1216 set_intercept(svm, INTERCEPT_IOIO_PROT);
1217 set_intercept(svm, INTERCEPT_MSR_PROT);
1218 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1219 set_intercept(svm, INTERCEPT_SHUTDOWN);
1220 set_intercept(svm, INTERCEPT_VMRUN);
1221 set_intercept(svm, INTERCEPT_VMMCALL);
1222 set_intercept(svm, INTERCEPT_VMLOAD);
1223 set_intercept(svm, INTERCEPT_VMSAVE);
1224 set_intercept(svm, INTERCEPT_STGI);
1225 set_intercept(svm, INTERCEPT_CLGI);
1226 set_intercept(svm, INTERCEPT_SKINIT);
1227 set_intercept(svm, INTERCEPT_WBINVD);
1228 set_intercept(svm, INTERCEPT_MONITOR);
1229 set_intercept(svm, INTERCEPT_MWAIT);
1230 set_intercept(svm, INTERCEPT_XSETBV);
1231
1232 control->iopm_base_pa = iopm_base;
1233 control->msrpm_base_pa = __pa(svm->msrpm);
1234 control->int_ctl = V_INTR_MASKING_MASK;
1235
1236 init_seg(&save->es);
1237 init_seg(&save->ss);
1238 init_seg(&save->ds);
1239 init_seg(&save->fs);
1240 init_seg(&save->gs);
1241
1242 save->cs.selector = 0xf000;
1243 save->cs.base = 0xffff0000;
1244 /* Executable/Readable Code Segment */
1245 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1246 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1247 save->cs.limit = 0xffff;
1248
1249 save->gdtr.limit = 0xffff;
1250 save->idtr.limit = 0xffff;
1251
1252 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1253 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1254
1255 if (!init_event)
1256 svm_set_efer(&svm->vcpu, 0);
1257 save->dr6 = 0xffff0ff0;
1258 kvm_set_rflags(&svm->vcpu, 2);
1259 save->rip = 0x0000fff0;
1260 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1261
1262 /*
1263 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1264 * It also updates the guest-visible cr0 value.
1265 */
1266 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1267 kvm_mmu_reset_context(&svm->vcpu);
1268
1269 save->cr4 = X86_CR4_PAE;
1270 /* rdx = ?? */
1271
1272 if (npt_enabled) {
1273 /* Setup VMCB for Nested Paging */
1274 control->nested_ctl = 1;
1275 clr_intercept(svm, INTERCEPT_INVLPG);
1276 clr_exception_intercept(svm, PF_VECTOR);
1277 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1278 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1279 save->g_pat = svm->vcpu.arch.pat;
1280 svm_set_guest_pat(svm, &save->g_pat);
1281 save->cr3 = 0;
1282 save->cr4 = 0;
1283 }
1284 svm->asid_generation = 0;
1285
1286 svm->nested.vmcb = 0;
1287 svm->vcpu.arch.hflags = 0;
1288
1289 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1290 control->pause_filter_count = 3000;
1291 set_intercept(svm, INTERCEPT_PAUSE);
1292 }
1293
1294 mark_all_dirty(svm->vmcb);
1295
1296 enable_gif(svm);
1297 }
1298
1299 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1300 {
1301 struct vcpu_svm *svm = to_svm(vcpu);
1302 u32 dummy;
1303 u32 eax = 1;
1304
1305 if (!init_event) {
1306 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1307 MSR_IA32_APICBASE_ENABLE;
1308 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1309 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1310 }
1311 init_vmcb(svm, init_event);
1312
1313 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1314 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1315 }
1316
1317 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1318 {
1319 struct vcpu_svm *svm;
1320 struct page *page;
1321 struct page *msrpm_pages;
1322 struct page *hsave_page;
1323 struct page *nested_msrpm_pages;
1324 int err;
1325
1326 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1327 if (!svm) {
1328 err = -ENOMEM;
1329 goto out;
1330 }
1331
1332 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1333
1334 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1335 if (err)
1336 goto free_svm;
1337
1338 err = -ENOMEM;
1339 page = alloc_page(GFP_KERNEL);
1340 if (!page)
1341 goto uninit;
1342
1343 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1344 if (!msrpm_pages)
1345 goto free_page1;
1346
1347 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1348 if (!nested_msrpm_pages)
1349 goto free_page2;
1350
1351 hsave_page = alloc_page(GFP_KERNEL);
1352 if (!hsave_page)
1353 goto free_page3;
1354
1355 svm->nested.hsave = page_address(hsave_page);
1356
1357 svm->msrpm = page_address(msrpm_pages);
1358 svm_vcpu_init_msrpm(svm->msrpm);
1359
1360 svm->nested.msrpm = page_address(nested_msrpm_pages);
1361 svm_vcpu_init_msrpm(svm->nested.msrpm);
1362
1363 svm->vmcb = page_address(page);
1364 clear_page(svm->vmcb);
1365 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1366 svm->asid_generation = 0;
1367 init_vmcb(svm, false);
1368
1369 svm_init_osvw(&svm->vcpu);
1370
1371 return &svm->vcpu;
1372
1373 free_page3:
1374 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1375 free_page2:
1376 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1377 free_page1:
1378 __free_page(page);
1379 uninit:
1380 kvm_vcpu_uninit(&svm->vcpu);
1381 free_svm:
1382 kmem_cache_free(kvm_vcpu_cache, svm);
1383 out:
1384 return ERR_PTR(err);
1385 }
1386
1387 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1388 {
1389 struct vcpu_svm *svm = to_svm(vcpu);
1390
1391 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1392 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1393 __free_page(virt_to_page(svm->nested.hsave));
1394 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1395 kvm_vcpu_uninit(vcpu);
1396 kmem_cache_free(kvm_vcpu_cache, svm);
1397 }
1398
1399 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1400 {
1401 struct vcpu_svm *svm = to_svm(vcpu);
1402 int i;
1403
1404 if (unlikely(cpu != vcpu->cpu)) {
1405 svm->asid_generation = 0;
1406 mark_all_dirty(svm->vmcb);
1407 }
1408
1409 #ifdef CONFIG_X86_64
1410 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1411 #endif
1412 savesegment(fs, svm->host.fs);
1413 savesegment(gs, svm->host.gs);
1414 svm->host.ldt = kvm_read_ldt();
1415
1416 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1417 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1418
1419 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1420 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1421 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1422 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1423 }
1424 }
1425
1426 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1427 {
1428 struct vcpu_svm *svm = to_svm(vcpu);
1429 int i;
1430
1431 ++vcpu->stat.host_state_reload;
1432 kvm_load_ldt(svm->host.ldt);
1433 #ifdef CONFIG_X86_64
1434 loadsegment(fs, svm->host.fs);
1435 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1436 load_gs_index(svm->host.gs);
1437 #else
1438 #ifdef CONFIG_X86_32_LAZY_GS
1439 loadsegment(gs, svm->host.gs);
1440 #endif
1441 #endif
1442 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1443 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1444 }
1445
1446 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1447 {
1448 return to_svm(vcpu)->vmcb->save.rflags;
1449 }
1450
1451 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1452 {
1453 /*
1454 * Any change of EFLAGS.VM is accompained by a reload of SS
1455 * (caused by either a task switch or an inter-privilege IRET),
1456 * so we do not need to update the CPL here.
1457 */
1458 to_svm(vcpu)->vmcb->save.rflags = rflags;
1459 }
1460
1461 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1462 {
1463 switch (reg) {
1464 case VCPU_EXREG_PDPTR:
1465 BUG_ON(!npt_enabled);
1466 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1467 break;
1468 default:
1469 BUG();
1470 }
1471 }
1472
1473 static void svm_set_vintr(struct vcpu_svm *svm)
1474 {
1475 set_intercept(svm, INTERCEPT_VINTR);
1476 }
1477
1478 static void svm_clear_vintr(struct vcpu_svm *svm)
1479 {
1480 clr_intercept(svm, INTERCEPT_VINTR);
1481 }
1482
1483 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1484 {
1485 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1486
1487 switch (seg) {
1488 case VCPU_SREG_CS: return &save->cs;
1489 case VCPU_SREG_DS: return &save->ds;
1490 case VCPU_SREG_ES: return &save->es;
1491 case VCPU_SREG_FS: return &save->fs;
1492 case VCPU_SREG_GS: return &save->gs;
1493 case VCPU_SREG_SS: return &save->ss;
1494 case VCPU_SREG_TR: return &save->tr;
1495 case VCPU_SREG_LDTR: return &save->ldtr;
1496 }
1497 BUG();
1498 return NULL;
1499 }
1500
1501 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1502 {
1503 struct vmcb_seg *s = svm_seg(vcpu, seg);
1504
1505 return s->base;
1506 }
1507
1508 static void svm_get_segment(struct kvm_vcpu *vcpu,
1509 struct kvm_segment *var, int seg)
1510 {
1511 struct vmcb_seg *s = svm_seg(vcpu, seg);
1512
1513 var->base = s->base;
1514 var->limit = s->limit;
1515 var->selector = s->selector;
1516 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1517 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1518 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1519 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1520 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1521 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1522 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1523
1524 /*
1525 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1526 * However, the SVM spec states that the G bit is not observed by the
1527 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1528 * So let's synthesize a legal G bit for all segments, this helps
1529 * running KVM nested. It also helps cross-vendor migration, because
1530 * Intel's vmentry has a check on the 'G' bit.
1531 */
1532 var->g = s->limit > 0xfffff;
1533
1534 /*
1535 * AMD's VMCB does not have an explicit unusable field, so emulate it
1536 * for cross vendor migration purposes by "not present"
1537 */
1538 var->unusable = !var->present || (var->type == 0);
1539
1540 switch (seg) {
1541 case VCPU_SREG_TR:
1542 /*
1543 * Work around a bug where the busy flag in the tr selector
1544 * isn't exposed
1545 */
1546 var->type |= 0x2;
1547 break;
1548 case VCPU_SREG_DS:
1549 case VCPU_SREG_ES:
1550 case VCPU_SREG_FS:
1551 case VCPU_SREG_GS:
1552 /*
1553 * The accessed bit must always be set in the segment
1554 * descriptor cache, although it can be cleared in the
1555 * descriptor, the cached bit always remains at 1. Since
1556 * Intel has a check on this, set it here to support
1557 * cross-vendor migration.
1558 */
1559 if (!var->unusable)
1560 var->type |= 0x1;
1561 break;
1562 case VCPU_SREG_SS:
1563 /*
1564 * On AMD CPUs sometimes the DB bit in the segment
1565 * descriptor is left as 1, although the whole segment has
1566 * been made unusable. Clear it here to pass an Intel VMX
1567 * entry check when cross vendor migrating.
1568 */
1569 if (var->unusable)
1570 var->db = 0;
1571 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1572 break;
1573 }
1574 }
1575
1576 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1577 {
1578 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1579
1580 return save->cpl;
1581 }
1582
1583 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1584 {
1585 struct vcpu_svm *svm = to_svm(vcpu);
1586
1587 dt->size = svm->vmcb->save.idtr.limit;
1588 dt->address = svm->vmcb->save.idtr.base;
1589 }
1590
1591 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1592 {
1593 struct vcpu_svm *svm = to_svm(vcpu);
1594
1595 svm->vmcb->save.idtr.limit = dt->size;
1596 svm->vmcb->save.idtr.base = dt->address ;
1597 mark_dirty(svm->vmcb, VMCB_DT);
1598 }
1599
1600 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1601 {
1602 struct vcpu_svm *svm = to_svm(vcpu);
1603
1604 dt->size = svm->vmcb->save.gdtr.limit;
1605 dt->address = svm->vmcb->save.gdtr.base;
1606 }
1607
1608 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1609 {
1610 struct vcpu_svm *svm = to_svm(vcpu);
1611
1612 svm->vmcb->save.gdtr.limit = dt->size;
1613 svm->vmcb->save.gdtr.base = dt->address ;
1614 mark_dirty(svm->vmcb, VMCB_DT);
1615 }
1616
1617 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1618 {
1619 }
1620
1621 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1622 {
1623 }
1624
1625 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1626 {
1627 }
1628
1629 static void update_cr0_intercept(struct vcpu_svm *svm)
1630 {
1631 ulong gcr0 = svm->vcpu.arch.cr0;
1632 u64 *hcr0 = &svm->vmcb->save.cr0;
1633
1634 if (!svm->vcpu.fpu_active)
1635 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1636 else
1637 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1638 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1639
1640 mark_dirty(svm->vmcb, VMCB_CR);
1641
1642 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1643 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1644 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1645 } else {
1646 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1647 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1648 }
1649 }
1650
1651 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1652 {
1653 struct vcpu_svm *svm = to_svm(vcpu);
1654
1655 #ifdef CONFIG_X86_64
1656 if (vcpu->arch.efer & EFER_LME) {
1657 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1658 vcpu->arch.efer |= EFER_LMA;
1659 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1660 }
1661
1662 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1663 vcpu->arch.efer &= ~EFER_LMA;
1664 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1665 }
1666 }
1667 #endif
1668 vcpu->arch.cr0 = cr0;
1669
1670 if (!npt_enabled)
1671 cr0 |= X86_CR0_PG | X86_CR0_WP;
1672
1673 if (!vcpu->fpu_active)
1674 cr0 |= X86_CR0_TS;
1675 /*
1676 * re-enable caching here because the QEMU bios
1677 * does not do it - this results in some delay at
1678 * reboot
1679 */
1680 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1681 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1682 svm->vmcb->save.cr0 = cr0;
1683 mark_dirty(svm->vmcb, VMCB_CR);
1684 update_cr0_intercept(svm);
1685 }
1686
1687 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1688 {
1689 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1690 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1691
1692 if (cr4 & X86_CR4_VMXE)
1693 return 1;
1694
1695 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1696 svm_flush_tlb(vcpu);
1697
1698 vcpu->arch.cr4 = cr4;
1699 if (!npt_enabled)
1700 cr4 |= X86_CR4_PAE;
1701 cr4 |= host_cr4_mce;
1702 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1703 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1704 return 0;
1705 }
1706
1707 static void svm_set_segment(struct kvm_vcpu *vcpu,
1708 struct kvm_segment *var, int seg)
1709 {
1710 struct vcpu_svm *svm = to_svm(vcpu);
1711 struct vmcb_seg *s = svm_seg(vcpu, seg);
1712
1713 s->base = var->base;
1714 s->limit = var->limit;
1715 s->selector = var->selector;
1716 if (var->unusable)
1717 s->attrib = 0;
1718 else {
1719 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1720 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1721 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1722 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1723 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1724 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1725 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1726 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1727 }
1728
1729 /*
1730 * This is always accurate, except if SYSRET returned to a segment
1731 * with SS.DPL != 3. Intel does not have this quirk, and always
1732 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1733 * would entail passing the CPL to userspace and back.
1734 */
1735 if (seg == VCPU_SREG_SS)
1736 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1737
1738 mark_dirty(svm->vmcb, VMCB_SEG);
1739 }
1740
1741 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1742 {
1743 struct vcpu_svm *svm = to_svm(vcpu);
1744
1745 clr_exception_intercept(svm, DB_VECTOR);
1746 clr_exception_intercept(svm, BP_VECTOR);
1747
1748 if (svm->nmi_singlestep)
1749 set_exception_intercept(svm, DB_VECTOR);
1750
1751 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1752 if (vcpu->guest_debug &
1753 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1754 set_exception_intercept(svm, DB_VECTOR);
1755 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1756 set_exception_intercept(svm, BP_VECTOR);
1757 } else
1758 vcpu->guest_debug = 0;
1759 }
1760
1761 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1762 {
1763 if (sd->next_asid > sd->max_asid) {
1764 ++sd->asid_generation;
1765 sd->next_asid = 1;
1766 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1767 }
1768
1769 svm->asid_generation = sd->asid_generation;
1770 svm->vmcb->control.asid = sd->next_asid++;
1771
1772 mark_dirty(svm->vmcb, VMCB_ASID);
1773 }
1774
1775 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1776 {
1777 return to_svm(vcpu)->vmcb->save.dr6;
1778 }
1779
1780 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1781 {
1782 struct vcpu_svm *svm = to_svm(vcpu);
1783
1784 svm->vmcb->save.dr6 = value;
1785 mark_dirty(svm->vmcb, VMCB_DR);
1786 }
1787
1788 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1789 {
1790 struct vcpu_svm *svm = to_svm(vcpu);
1791
1792 get_debugreg(vcpu->arch.db[0], 0);
1793 get_debugreg(vcpu->arch.db[1], 1);
1794 get_debugreg(vcpu->arch.db[2], 2);
1795 get_debugreg(vcpu->arch.db[3], 3);
1796 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1797 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1798
1799 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1800 set_dr_intercepts(svm);
1801 }
1802
1803 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1804 {
1805 struct vcpu_svm *svm = to_svm(vcpu);
1806
1807 svm->vmcb->save.dr7 = value;
1808 mark_dirty(svm->vmcb, VMCB_DR);
1809 }
1810
1811 static int pf_interception(struct vcpu_svm *svm)
1812 {
1813 u64 fault_address = svm->vmcb->control.exit_info_2;
1814 u32 error_code;
1815 int r = 1;
1816
1817 switch (svm->apf_reason) {
1818 default:
1819 error_code = svm->vmcb->control.exit_info_1;
1820
1821 trace_kvm_page_fault(fault_address, error_code);
1822 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1823 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1824 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1825 svm->vmcb->control.insn_bytes,
1826 svm->vmcb->control.insn_len);
1827 break;
1828 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1829 svm->apf_reason = 0;
1830 local_irq_disable();
1831 kvm_async_pf_task_wait(fault_address);
1832 local_irq_enable();
1833 break;
1834 case KVM_PV_REASON_PAGE_READY:
1835 svm->apf_reason = 0;
1836 local_irq_disable();
1837 kvm_async_pf_task_wake(fault_address);
1838 local_irq_enable();
1839 break;
1840 }
1841 return r;
1842 }
1843
1844 static int db_interception(struct vcpu_svm *svm)
1845 {
1846 struct kvm_run *kvm_run = svm->vcpu.run;
1847
1848 if (!(svm->vcpu.guest_debug &
1849 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1850 !svm->nmi_singlestep) {
1851 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1852 return 1;
1853 }
1854
1855 if (svm->nmi_singlestep) {
1856 svm->nmi_singlestep = false;
1857 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1858 svm->vmcb->save.rflags &=
1859 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1860 update_db_bp_intercept(&svm->vcpu);
1861 }
1862
1863 if (svm->vcpu.guest_debug &
1864 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1865 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1866 kvm_run->debug.arch.pc =
1867 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1868 kvm_run->debug.arch.exception = DB_VECTOR;
1869 return 0;
1870 }
1871
1872 return 1;
1873 }
1874
1875 static int bp_interception(struct vcpu_svm *svm)
1876 {
1877 struct kvm_run *kvm_run = svm->vcpu.run;
1878
1879 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1880 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1881 kvm_run->debug.arch.exception = BP_VECTOR;
1882 return 0;
1883 }
1884
1885 static int ud_interception(struct vcpu_svm *svm)
1886 {
1887 int er;
1888
1889 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1890 if (er != EMULATE_DONE)
1891 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1892 return 1;
1893 }
1894
1895 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1896 {
1897 struct vcpu_svm *svm = to_svm(vcpu);
1898
1899 clr_exception_intercept(svm, NM_VECTOR);
1900
1901 svm->vcpu.fpu_active = 1;
1902 update_cr0_intercept(svm);
1903 }
1904
1905 static int nm_interception(struct vcpu_svm *svm)
1906 {
1907 svm_fpu_activate(&svm->vcpu);
1908 return 1;
1909 }
1910
1911 static bool is_erratum_383(void)
1912 {
1913 int err, i;
1914 u64 value;
1915
1916 if (!erratum_383_found)
1917 return false;
1918
1919 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1920 if (err)
1921 return false;
1922
1923 /* Bit 62 may or may not be set for this mce */
1924 value &= ~(1ULL << 62);
1925
1926 if (value != 0xb600000000010015ULL)
1927 return false;
1928
1929 /* Clear MCi_STATUS registers */
1930 for (i = 0; i < 6; ++i)
1931 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1932
1933 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1934 if (!err) {
1935 u32 low, high;
1936
1937 value &= ~(1ULL << 2);
1938 low = lower_32_bits(value);
1939 high = upper_32_bits(value);
1940
1941 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1942 }
1943
1944 /* Flush tlb to evict multi-match entries */
1945 __flush_tlb_all();
1946
1947 return true;
1948 }
1949
1950 static void svm_handle_mce(struct vcpu_svm *svm)
1951 {
1952 if (is_erratum_383()) {
1953 /*
1954 * Erratum 383 triggered. Guest state is corrupt so kill the
1955 * guest.
1956 */
1957 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1958
1959 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1960
1961 return;
1962 }
1963
1964 /*
1965 * On an #MC intercept the MCE handler is not called automatically in
1966 * the host. So do it by hand here.
1967 */
1968 asm volatile (
1969 "int $0x12\n");
1970 /* not sure if we ever come back to this point */
1971
1972 return;
1973 }
1974
1975 static int mc_interception(struct vcpu_svm *svm)
1976 {
1977 return 1;
1978 }
1979
1980 static int shutdown_interception(struct vcpu_svm *svm)
1981 {
1982 struct kvm_run *kvm_run = svm->vcpu.run;
1983
1984 /*
1985 * VMCB is undefined after a SHUTDOWN intercept
1986 * so reinitialize it.
1987 */
1988 clear_page(svm->vmcb);
1989 init_vmcb(svm, false);
1990
1991 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1992 return 0;
1993 }
1994
1995 static int io_interception(struct vcpu_svm *svm)
1996 {
1997 struct kvm_vcpu *vcpu = &svm->vcpu;
1998 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1999 int size, in, string;
2000 unsigned port;
2001
2002 ++svm->vcpu.stat.io_exits;
2003 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2004 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2005 if (string || in)
2006 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2007
2008 port = io_info >> 16;
2009 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2010 svm->next_rip = svm->vmcb->control.exit_info_2;
2011 skip_emulated_instruction(&svm->vcpu);
2012
2013 return kvm_fast_pio_out(vcpu, size, port);
2014 }
2015
2016 static int nmi_interception(struct vcpu_svm *svm)
2017 {
2018 return 1;
2019 }
2020
2021 static int intr_interception(struct vcpu_svm *svm)
2022 {
2023 ++svm->vcpu.stat.irq_exits;
2024 return 1;
2025 }
2026
2027 static int nop_on_interception(struct vcpu_svm *svm)
2028 {
2029 return 1;
2030 }
2031
2032 static int halt_interception(struct vcpu_svm *svm)
2033 {
2034 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2035 return kvm_emulate_halt(&svm->vcpu);
2036 }
2037
2038 static int vmmcall_interception(struct vcpu_svm *svm)
2039 {
2040 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2041 kvm_emulate_hypercall(&svm->vcpu);
2042 return 1;
2043 }
2044
2045 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2046 {
2047 struct vcpu_svm *svm = to_svm(vcpu);
2048
2049 return svm->nested.nested_cr3;
2050 }
2051
2052 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2053 {
2054 struct vcpu_svm *svm = to_svm(vcpu);
2055 u64 cr3 = svm->nested.nested_cr3;
2056 u64 pdpte;
2057 int ret;
2058
2059 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2060 offset_in_page(cr3) + index * 8, 8);
2061 if (ret)
2062 return 0;
2063 return pdpte;
2064 }
2065
2066 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2067 unsigned long root)
2068 {
2069 struct vcpu_svm *svm = to_svm(vcpu);
2070
2071 svm->vmcb->control.nested_cr3 = root;
2072 mark_dirty(svm->vmcb, VMCB_NPT);
2073 svm_flush_tlb(vcpu);
2074 }
2075
2076 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2077 struct x86_exception *fault)
2078 {
2079 struct vcpu_svm *svm = to_svm(vcpu);
2080
2081 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2082 /*
2083 * TODO: track the cause of the nested page fault, and
2084 * correctly fill in the high bits of exit_info_1.
2085 */
2086 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2087 svm->vmcb->control.exit_code_hi = 0;
2088 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2089 svm->vmcb->control.exit_info_2 = fault->address;
2090 }
2091
2092 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2093 svm->vmcb->control.exit_info_1 |= fault->error_code;
2094
2095 /*
2096 * The present bit is always zero for page structure faults on real
2097 * hardware.
2098 */
2099 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2100 svm->vmcb->control.exit_info_1 &= ~1;
2101
2102 nested_svm_vmexit(svm);
2103 }
2104
2105 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2106 {
2107 WARN_ON(mmu_is_nested(vcpu));
2108 kvm_init_shadow_mmu(vcpu);
2109 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2110 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2111 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2112 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2113 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2114 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2115 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2116 }
2117
2118 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2119 {
2120 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2121 }
2122
2123 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2124 {
2125 if (!(svm->vcpu.arch.efer & EFER_SVME)
2126 || !is_paging(&svm->vcpu)) {
2127 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2128 return 1;
2129 }
2130
2131 if (svm->vmcb->save.cpl) {
2132 kvm_inject_gp(&svm->vcpu, 0);
2133 return 1;
2134 }
2135
2136 return 0;
2137 }
2138
2139 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2140 bool has_error_code, u32 error_code)
2141 {
2142 int vmexit;
2143
2144 if (!is_guest_mode(&svm->vcpu))
2145 return 0;
2146
2147 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2148 svm->vmcb->control.exit_code_hi = 0;
2149 svm->vmcb->control.exit_info_1 = error_code;
2150 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2151
2152 vmexit = nested_svm_intercept(svm);
2153 if (vmexit == NESTED_EXIT_DONE)
2154 svm->nested.exit_required = true;
2155
2156 return vmexit;
2157 }
2158
2159 /* This function returns true if it is save to enable the irq window */
2160 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2161 {
2162 if (!is_guest_mode(&svm->vcpu))
2163 return true;
2164
2165 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2166 return true;
2167
2168 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2169 return false;
2170
2171 /*
2172 * if vmexit was already requested (by intercepted exception
2173 * for instance) do not overwrite it with "external interrupt"
2174 * vmexit.
2175 */
2176 if (svm->nested.exit_required)
2177 return false;
2178
2179 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2180 svm->vmcb->control.exit_info_1 = 0;
2181 svm->vmcb->control.exit_info_2 = 0;
2182
2183 if (svm->nested.intercept & 1ULL) {
2184 /*
2185 * The #vmexit can't be emulated here directly because this
2186 * code path runs with irqs and preemption disabled. A
2187 * #vmexit emulation might sleep. Only signal request for
2188 * the #vmexit here.
2189 */
2190 svm->nested.exit_required = true;
2191 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2192 return false;
2193 }
2194
2195 return true;
2196 }
2197
2198 /* This function returns true if it is save to enable the nmi window */
2199 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2200 {
2201 if (!is_guest_mode(&svm->vcpu))
2202 return true;
2203
2204 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2205 return true;
2206
2207 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2208 svm->nested.exit_required = true;
2209
2210 return false;
2211 }
2212
2213 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2214 {
2215 struct page *page;
2216
2217 might_sleep();
2218
2219 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2220 if (is_error_page(page))
2221 goto error;
2222
2223 *_page = page;
2224
2225 return kmap(page);
2226
2227 error:
2228 kvm_inject_gp(&svm->vcpu, 0);
2229
2230 return NULL;
2231 }
2232
2233 static void nested_svm_unmap(struct page *page)
2234 {
2235 kunmap(page);
2236 kvm_release_page_dirty(page);
2237 }
2238
2239 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2240 {
2241 unsigned port, size, iopm_len;
2242 u16 val, mask;
2243 u8 start_bit;
2244 u64 gpa;
2245
2246 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2247 return NESTED_EXIT_HOST;
2248
2249 port = svm->vmcb->control.exit_info_1 >> 16;
2250 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2251 SVM_IOIO_SIZE_SHIFT;
2252 gpa = svm->nested.vmcb_iopm + (port / 8);
2253 start_bit = port % 8;
2254 iopm_len = (start_bit + size > 8) ? 2 : 1;
2255 mask = (0xf >> (4 - size)) << start_bit;
2256 val = 0;
2257
2258 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2259 return NESTED_EXIT_DONE;
2260
2261 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2262 }
2263
2264 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2265 {
2266 u32 offset, msr, value;
2267 int write, mask;
2268
2269 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2270 return NESTED_EXIT_HOST;
2271
2272 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2273 offset = svm_msrpm_offset(msr);
2274 write = svm->vmcb->control.exit_info_1 & 1;
2275 mask = 1 << ((2 * (msr & 0xf)) + write);
2276
2277 if (offset == MSR_INVALID)
2278 return NESTED_EXIT_DONE;
2279
2280 /* Offset is in 32 bit units but need in 8 bit units */
2281 offset *= 4;
2282
2283 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2284 return NESTED_EXIT_DONE;
2285
2286 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2287 }
2288
2289 static int nested_svm_exit_special(struct vcpu_svm *svm)
2290 {
2291 u32 exit_code = svm->vmcb->control.exit_code;
2292
2293 switch (exit_code) {
2294 case SVM_EXIT_INTR:
2295 case SVM_EXIT_NMI:
2296 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2297 return NESTED_EXIT_HOST;
2298 case SVM_EXIT_NPF:
2299 /* For now we are always handling NPFs when using them */
2300 if (npt_enabled)
2301 return NESTED_EXIT_HOST;
2302 break;
2303 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2304 /* When we're shadowing, trap PFs, but not async PF */
2305 if (!npt_enabled && svm->apf_reason == 0)
2306 return NESTED_EXIT_HOST;
2307 break;
2308 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2309 nm_interception(svm);
2310 break;
2311 default:
2312 break;
2313 }
2314
2315 return NESTED_EXIT_CONTINUE;
2316 }
2317
2318 /*
2319 * If this function returns true, this #vmexit was already handled
2320 */
2321 static int nested_svm_intercept(struct vcpu_svm *svm)
2322 {
2323 u32 exit_code = svm->vmcb->control.exit_code;
2324 int vmexit = NESTED_EXIT_HOST;
2325
2326 switch (exit_code) {
2327 case SVM_EXIT_MSR:
2328 vmexit = nested_svm_exit_handled_msr(svm);
2329 break;
2330 case SVM_EXIT_IOIO:
2331 vmexit = nested_svm_intercept_ioio(svm);
2332 break;
2333 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2334 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2335 if (svm->nested.intercept_cr & bit)
2336 vmexit = NESTED_EXIT_DONE;
2337 break;
2338 }
2339 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2340 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2341 if (svm->nested.intercept_dr & bit)
2342 vmexit = NESTED_EXIT_DONE;
2343 break;
2344 }
2345 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2346 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2347 if (svm->nested.intercept_exceptions & excp_bits)
2348 vmexit = NESTED_EXIT_DONE;
2349 /* async page fault always cause vmexit */
2350 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2351 svm->apf_reason != 0)
2352 vmexit = NESTED_EXIT_DONE;
2353 break;
2354 }
2355 case SVM_EXIT_ERR: {
2356 vmexit = NESTED_EXIT_DONE;
2357 break;
2358 }
2359 default: {
2360 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2361 if (svm->nested.intercept & exit_bits)
2362 vmexit = NESTED_EXIT_DONE;
2363 }
2364 }
2365
2366 return vmexit;
2367 }
2368
2369 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2370 {
2371 int vmexit;
2372
2373 vmexit = nested_svm_intercept(svm);
2374
2375 if (vmexit == NESTED_EXIT_DONE)
2376 nested_svm_vmexit(svm);
2377
2378 return vmexit;
2379 }
2380
2381 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2382 {
2383 struct vmcb_control_area *dst = &dst_vmcb->control;
2384 struct vmcb_control_area *from = &from_vmcb->control;
2385
2386 dst->intercept_cr = from->intercept_cr;
2387 dst->intercept_dr = from->intercept_dr;
2388 dst->intercept_exceptions = from->intercept_exceptions;
2389 dst->intercept = from->intercept;
2390 dst->iopm_base_pa = from->iopm_base_pa;
2391 dst->msrpm_base_pa = from->msrpm_base_pa;
2392 dst->tsc_offset = from->tsc_offset;
2393 dst->asid = from->asid;
2394 dst->tlb_ctl = from->tlb_ctl;
2395 dst->int_ctl = from->int_ctl;
2396 dst->int_vector = from->int_vector;
2397 dst->int_state = from->int_state;
2398 dst->exit_code = from->exit_code;
2399 dst->exit_code_hi = from->exit_code_hi;
2400 dst->exit_info_1 = from->exit_info_1;
2401 dst->exit_info_2 = from->exit_info_2;
2402 dst->exit_int_info = from->exit_int_info;
2403 dst->exit_int_info_err = from->exit_int_info_err;
2404 dst->nested_ctl = from->nested_ctl;
2405 dst->event_inj = from->event_inj;
2406 dst->event_inj_err = from->event_inj_err;
2407 dst->nested_cr3 = from->nested_cr3;
2408 dst->lbr_ctl = from->lbr_ctl;
2409 }
2410
2411 static int nested_svm_vmexit(struct vcpu_svm *svm)
2412 {
2413 struct vmcb *nested_vmcb;
2414 struct vmcb *hsave = svm->nested.hsave;
2415 struct vmcb *vmcb = svm->vmcb;
2416 struct page *page;
2417
2418 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2419 vmcb->control.exit_info_1,
2420 vmcb->control.exit_info_2,
2421 vmcb->control.exit_int_info,
2422 vmcb->control.exit_int_info_err,
2423 KVM_ISA_SVM);
2424
2425 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2426 if (!nested_vmcb)
2427 return 1;
2428
2429 /* Exit Guest-Mode */
2430 leave_guest_mode(&svm->vcpu);
2431 svm->nested.vmcb = 0;
2432
2433 /* Give the current vmcb to the guest */
2434 disable_gif(svm);
2435
2436 nested_vmcb->save.es = vmcb->save.es;
2437 nested_vmcb->save.cs = vmcb->save.cs;
2438 nested_vmcb->save.ss = vmcb->save.ss;
2439 nested_vmcb->save.ds = vmcb->save.ds;
2440 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2441 nested_vmcb->save.idtr = vmcb->save.idtr;
2442 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2443 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2444 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2445 nested_vmcb->save.cr2 = vmcb->save.cr2;
2446 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2447 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2448 nested_vmcb->save.rip = vmcb->save.rip;
2449 nested_vmcb->save.rsp = vmcb->save.rsp;
2450 nested_vmcb->save.rax = vmcb->save.rax;
2451 nested_vmcb->save.dr7 = vmcb->save.dr7;
2452 nested_vmcb->save.dr6 = vmcb->save.dr6;
2453 nested_vmcb->save.cpl = vmcb->save.cpl;
2454
2455 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2456 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2457 nested_vmcb->control.int_state = vmcb->control.int_state;
2458 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2459 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2460 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2461 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2462 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2463 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2464 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2465
2466 /*
2467 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2468 * to make sure that we do not lose injected events. So check event_inj
2469 * here and copy it to exit_int_info if it is valid.
2470 * Exit_int_info and event_inj can't be both valid because the case
2471 * below only happens on a VMRUN instruction intercept which has
2472 * no valid exit_int_info set.
2473 */
2474 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2475 struct vmcb_control_area *nc = &nested_vmcb->control;
2476
2477 nc->exit_int_info = vmcb->control.event_inj;
2478 nc->exit_int_info_err = vmcb->control.event_inj_err;
2479 }
2480
2481 nested_vmcb->control.tlb_ctl = 0;
2482 nested_vmcb->control.event_inj = 0;
2483 nested_vmcb->control.event_inj_err = 0;
2484
2485 /* We always set V_INTR_MASKING and remember the old value in hflags */
2486 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2487 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2488
2489 /* Restore the original control entries */
2490 copy_vmcb_control_area(vmcb, hsave);
2491
2492 kvm_clear_exception_queue(&svm->vcpu);
2493 kvm_clear_interrupt_queue(&svm->vcpu);
2494
2495 svm->nested.nested_cr3 = 0;
2496
2497 /* Restore selected save entries */
2498 svm->vmcb->save.es = hsave->save.es;
2499 svm->vmcb->save.cs = hsave->save.cs;
2500 svm->vmcb->save.ss = hsave->save.ss;
2501 svm->vmcb->save.ds = hsave->save.ds;
2502 svm->vmcb->save.gdtr = hsave->save.gdtr;
2503 svm->vmcb->save.idtr = hsave->save.idtr;
2504 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2505 svm_set_efer(&svm->vcpu, hsave->save.efer);
2506 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2507 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2508 if (npt_enabled) {
2509 svm->vmcb->save.cr3 = hsave->save.cr3;
2510 svm->vcpu.arch.cr3 = hsave->save.cr3;
2511 } else {
2512 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2513 }
2514 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2515 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2516 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2517 svm->vmcb->save.dr7 = 0;
2518 svm->vmcb->save.cpl = 0;
2519 svm->vmcb->control.exit_int_info = 0;
2520
2521 mark_all_dirty(svm->vmcb);
2522
2523 nested_svm_unmap(page);
2524
2525 nested_svm_uninit_mmu_context(&svm->vcpu);
2526 kvm_mmu_reset_context(&svm->vcpu);
2527 kvm_mmu_load(&svm->vcpu);
2528
2529 return 0;
2530 }
2531
2532 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2533 {
2534 /*
2535 * This function merges the msr permission bitmaps of kvm and the
2536 * nested vmcb. It is optimized in that it only merges the parts where
2537 * the kvm msr permission bitmap may contain zero bits
2538 */
2539 int i;
2540
2541 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2542 return true;
2543
2544 for (i = 0; i < MSRPM_OFFSETS; i++) {
2545 u32 value, p;
2546 u64 offset;
2547
2548 if (msrpm_offsets[i] == 0xffffffff)
2549 break;
2550
2551 p = msrpm_offsets[i];
2552 offset = svm->nested.vmcb_msrpm + (p * 4);
2553
2554 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2555 return false;
2556
2557 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2558 }
2559
2560 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2561
2562 return true;
2563 }
2564
2565 static bool nested_vmcb_checks(struct vmcb *vmcb)
2566 {
2567 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2568 return false;
2569
2570 if (vmcb->control.asid == 0)
2571 return false;
2572
2573 if (vmcb->control.nested_ctl && !npt_enabled)
2574 return false;
2575
2576 return true;
2577 }
2578
2579 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2580 {
2581 struct vmcb *nested_vmcb;
2582 struct vmcb *hsave = svm->nested.hsave;
2583 struct vmcb *vmcb = svm->vmcb;
2584 struct page *page;
2585 u64 vmcb_gpa;
2586
2587 vmcb_gpa = svm->vmcb->save.rax;
2588
2589 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2590 if (!nested_vmcb)
2591 return false;
2592
2593 if (!nested_vmcb_checks(nested_vmcb)) {
2594 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2595 nested_vmcb->control.exit_code_hi = 0;
2596 nested_vmcb->control.exit_info_1 = 0;
2597 nested_vmcb->control.exit_info_2 = 0;
2598
2599 nested_svm_unmap(page);
2600
2601 return false;
2602 }
2603
2604 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2605 nested_vmcb->save.rip,
2606 nested_vmcb->control.int_ctl,
2607 nested_vmcb->control.event_inj,
2608 nested_vmcb->control.nested_ctl);
2609
2610 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2611 nested_vmcb->control.intercept_cr >> 16,
2612 nested_vmcb->control.intercept_exceptions,
2613 nested_vmcb->control.intercept);
2614
2615 /* Clear internal status */
2616 kvm_clear_exception_queue(&svm->vcpu);
2617 kvm_clear_interrupt_queue(&svm->vcpu);
2618
2619 /*
2620 * Save the old vmcb, so we don't need to pick what we save, but can
2621 * restore everything when a VMEXIT occurs
2622 */
2623 hsave->save.es = vmcb->save.es;
2624 hsave->save.cs = vmcb->save.cs;
2625 hsave->save.ss = vmcb->save.ss;
2626 hsave->save.ds = vmcb->save.ds;
2627 hsave->save.gdtr = vmcb->save.gdtr;
2628 hsave->save.idtr = vmcb->save.idtr;
2629 hsave->save.efer = svm->vcpu.arch.efer;
2630 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2631 hsave->save.cr4 = svm->vcpu.arch.cr4;
2632 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2633 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2634 hsave->save.rsp = vmcb->save.rsp;
2635 hsave->save.rax = vmcb->save.rax;
2636 if (npt_enabled)
2637 hsave->save.cr3 = vmcb->save.cr3;
2638 else
2639 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2640
2641 copy_vmcb_control_area(hsave, vmcb);
2642
2643 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2644 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2645 else
2646 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2647
2648 if (nested_vmcb->control.nested_ctl) {
2649 kvm_mmu_unload(&svm->vcpu);
2650 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2651 nested_svm_init_mmu_context(&svm->vcpu);
2652 }
2653
2654 /* Load the nested guest state */
2655 svm->vmcb->save.es = nested_vmcb->save.es;
2656 svm->vmcb->save.cs = nested_vmcb->save.cs;
2657 svm->vmcb->save.ss = nested_vmcb->save.ss;
2658 svm->vmcb->save.ds = nested_vmcb->save.ds;
2659 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2660 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2661 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2662 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2663 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2664 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2665 if (npt_enabled) {
2666 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2667 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2668 } else
2669 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2670
2671 /* Guest paging mode is active - reset mmu */
2672 kvm_mmu_reset_context(&svm->vcpu);
2673
2674 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2675 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2676 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2677 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2678
2679 /* In case we don't even reach vcpu_run, the fields are not updated */
2680 svm->vmcb->save.rax = nested_vmcb->save.rax;
2681 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2682 svm->vmcb->save.rip = nested_vmcb->save.rip;
2683 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2684 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2685 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2686
2687 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2688 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2689
2690 /* cache intercepts */
2691 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2692 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2693 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2694 svm->nested.intercept = nested_vmcb->control.intercept;
2695
2696 svm_flush_tlb(&svm->vcpu);
2697 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2698 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2699 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2700 else
2701 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2702
2703 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2704 /* We only want the cr8 intercept bits of the guest */
2705 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2706 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2707 }
2708
2709 /* We don't want to see VMMCALLs from a nested guest */
2710 clr_intercept(svm, INTERCEPT_VMMCALL);
2711
2712 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2713 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2714 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2715 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2716 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2717 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2718
2719 nested_svm_unmap(page);
2720
2721 /* Enter Guest-Mode */
2722 enter_guest_mode(&svm->vcpu);
2723
2724 /*
2725 * Merge guest and host intercepts - must be called with vcpu in
2726 * guest-mode to take affect here
2727 */
2728 recalc_intercepts(svm);
2729
2730 svm->nested.vmcb = vmcb_gpa;
2731
2732 enable_gif(svm);
2733
2734 mark_all_dirty(svm->vmcb);
2735
2736 return true;
2737 }
2738
2739 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2740 {
2741 to_vmcb->save.fs = from_vmcb->save.fs;
2742 to_vmcb->save.gs = from_vmcb->save.gs;
2743 to_vmcb->save.tr = from_vmcb->save.tr;
2744 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2745 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2746 to_vmcb->save.star = from_vmcb->save.star;
2747 to_vmcb->save.lstar = from_vmcb->save.lstar;
2748 to_vmcb->save.cstar = from_vmcb->save.cstar;
2749 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2750 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2751 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2752 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2753 }
2754
2755 static int vmload_interception(struct vcpu_svm *svm)
2756 {
2757 struct vmcb *nested_vmcb;
2758 struct page *page;
2759
2760 if (nested_svm_check_permissions(svm))
2761 return 1;
2762
2763 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2764 if (!nested_vmcb)
2765 return 1;
2766
2767 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2768 skip_emulated_instruction(&svm->vcpu);
2769
2770 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2771 nested_svm_unmap(page);
2772
2773 return 1;
2774 }
2775
2776 static int vmsave_interception(struct vcpu_svm *svm)
2777 {
2778 struct vmcb *nested_vmcb;
2779 struct page *page;
2780
2781 if (nested_svm_check_permissions(svm))
2782 return 1;
2783
2784 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2785 if (!nested_vmcb)
2786 return 1;
2787
2788 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2789 skip_emulated_instruction(&svm->vcpu);
2790
2791 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2792 nested_svm_unmap(page);
2793
2794 return 1;
2795 }
2796
2797 static int vmrun_interception(struct vcpu_svm *svm)
2798 {
2799 if (nested_svm_check_permissions(svm))
2800 return 1;
2801
2802 /* Save rip after vmrun instruction */
2803 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2804
2805 if (!nested_svm_vmrun(svm))
2806 return 1;
2807
2808 if (!nested_svm_vmrun_msrpm(svm))
2809 goto failed;
2810
2811 return 1;
2812
2813 failed:
2814
2815 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2816 svm->vmcb->control.exit_code_hi = 0;
2817 svm->vmcb->control.exit_info_1 = 0;
2818 svm->vmcb->control.exit_info_2 = 0;
2819
2820 nested_svm_vmexit(svm);
2821
2822 return 1;
2823 }
2824
2825 static int stgi_interception(struct vcpu_svm *svm)
2826 {
2827 if (nested_svm_check_permissions(svm))
2828 return 1;
2829
2830 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2831 skip_emulated_instruction(&svm->vcpu);
2832 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2833
2834 enable_gif(svm);
2835
2836 return 1;
2837 }
2838
2839 static int clgi_interception(struct vcpu_svm *svm)
2840 {
2841 if (nested_svm_check_permissions(svm))
2842 return 1;
2843
2844 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2845 skip_emulated_instruction(&svm->vcpu);
2846
2847 disable_gif(svm);
2848
2849 /* After a CLGI no interrupts should come */
2850 svm_clear_vintr(svm);
2851 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2852
2853 mark_dirty(svm->vmcb, VMCB_INTR);
2854
2855 return 1;
2856 }
2857
2858 static int invlpga_interception(struct vcpu_svm *svm)
2859 {
2860 struct kvm_vcpu *vcpu = &svm->vcpu;
2861
2862 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2863 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2864
2865 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2866 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2867
2868 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2869 skip_emulated_instruction(&svm->vcpu);
2870 return 1;
2871 }
2872
2873 static int skinit_interception(struct vcpu_svm *svm)
2874 {
2875 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2876
2877 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2878 return 1;
2879 }
2880
2881 static int wbinvd_interception(struct vcpu_svm *svm)
2882 {
2883 kvm_emulate_wbinvd(&svm->vcpu);
2884 return 1;
2885 }
2886
2887 static int xsetbv_interception(struct vcpu_svm *svm)
2888 {
2889 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2890 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2891
2892 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2893 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2894 skip_emulated_instruction(&svm->vcpu);
2895 }
2896
2897 return 1;
2898 }
2899
2900 static int task_switch_interception(struct vcpu_svm *svm)
2901 {
2902 u16 tss_selector;
2903 int reason;
2904 int int_type = svm->vmcb->control.exit_int_info &
2905 SVM_EXITINTINFO_TYPE_MASK;
2906 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2907 uint32_t type =
2908 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2909 uint32_t idt_v =
2910 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2911 bool has_error_code = false;
2912 u32 error_code = 0;
2913
2914 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2915
2916 if (svm->vmcb->control.exit_info_2 &
2917 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2918 reason = TASK_SWITCH_IRET;
2919 else if (svm->vmcb->control.exit_info_2 &
2920 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2921 reason = TASK_SWITCH_JMP;
2922 else if (idt_v)
2923 reason = TASK_SWITCH_GATE;
2924 else
2925 reason = TASK_SWITCH_CALL;
2926
2927 if (reason == TASK_SWITCH_GATE) {
2928 switch (type) {
2929 case SVM_EXITINTINFO_TYPE_NMI:
2930 svm->vcpu.arch.nmi_injected = false;
2931 break;
2932 case SVM_EXITINTINFO_TYPE_EXEPT:
2933 if (svm->vmcb->control.exit_info_2 &
2934 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2935 has_error_code = true;
2936 error_code =
2937 (u32)svm->vmcb->control.exit_info_2;
2938 }
2939 kvm_clear_exception_queue(&svm->vcpu);
2940 break;
2941 case SVM_EXITINTINFO_TYPE_INTR:
2942 kvm_clear_interrupt_queue(&svm->vcpu);
2943 break;
2944 default:
2945 break;
2946 }
2947 }
2948
2949 if (reason != TASK_SWITCH_GATE ||
2950 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2951 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2952 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2953 skip_emulated_instruction(&svm->vcpu);
2954
2955 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2956 int_vec = -1;
2957
2958 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2959 has_error_code, error_code) == EMULATE_FAIL) {
2960 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2961 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2962 svm->vcpu.run->internal.ndata = 0;
2963 return 0;
2964 }
2965 return 1;
2966 }
2967
2968 static int cpuid_interception(struct vcpu_svm *svm)
2969 {
2970 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2971 kvm_emulate_cpuid(&svm->vcpu);
2972 return 1;
2973 }
2974
2975 static int iret_interception(struct vcpu_svm *svm)
2976 {
2977 ++svm->vcpu.stat.nmi_window_exits;
2978 clr_intercept(svm, INTERCEPT_IRET);
2979 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2980 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2981 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2982 return 1;
2983 }
2984
2985 static int invlpg_interception(struct vcpu_svm *svm)
2986 {
2987 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2988 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2989
2990 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2991 skip_emulated_instruction(&svm->vcpu);
2992 return 1;
2993 }
2994
2995 static int emulate_on_interception(struct vcpu_svm *svm)
2996 {
2997 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2998 }
2999
3000 static int rdpmc_interception(struct vcpu_svm *svm)
3001 {
3002 int err;
3003
3004 if (!static_cpu_has(X86_FEATURE_NRIPS))
3005 return emulate_on_interception(svm);
3006
3007 err = kvm_rdpmc(&svm->vcpu);
3008 kvm_complete_insn_gp(&svm->vcpu, err);
3009
3010 return 1;
3011 }
3012
3013 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3014 unsigned long val)
3015 {
3016 unsigned long cr0 = svm->vcpu.arch.cr0;
3017 bool ret = false;
3018 u64 intercept;
3019
3020 intercept = svm->nested.intercept;
3021
3022 if (!is_guest_mode(&svm->vcpu) ||
3023 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3024 return false;
3025
3026 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3027 val &= ~SVM_CR0_SELECTIVE_MASK;
3028
3029 if (cr0 ^ val) {
3030 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3031 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3032 }
3033
3034 return ret;
3035 }
3036
3037 #define CR_VALID (1ULL << 63)
3038
3039 static int cr_interception(struct vcpu_svm *svm)
3040 {
3041 int reg, cr;
3042 unsigned long val;
3043 int err;
3044
3045 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3046 return emulate_on_interception(svm);
3047
3048 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3049 return emulate_on_interception(svm);
3050
3051 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3052 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3053 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3054 else
3055 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3056
3057 err = 0;
3058 if (cr >= 16) { /* mov to cr */
3059 cr -= 16;
3060 val = kvm_register_read(&svm->vcpu, reg);
3061 switch (cr) {
3062 case 0:
3063 if (!check_selective_cr0_intercepted(svm, val))
3064 err = kvm_set_cr0(&svm->vcpu, val);
3065 else
3066 return 1;
3067
3068 break;
3069 case 3:
3070 err = kvm_set_cr3(&svm->vcpu, val);
3071 break;
3072 case 4:
3073 err = kvm_set_cr4(&svm->vcpu, val);
3074 break;
3075 case 8:
3076 err = kvm_set_cr8(&svm->vcpu, val);
3077 break;
3078 default:
3079 WARN(1, "unhandled write to CR%d", cr);
3080 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3081 return 1;
3082 }
3083 } else { /* mov from cr */
3084 switch (cr) {
3085 case 0:
3086 val = kvm_read_cr0(&svm->vcpu);
3087 break;
3088 case 2:
3089 val = svm->vcpu.arch.cr2;
3090 break;
3091 case 3:
3092 val = kvm_read_cr3(&svm->vcpu);
3093 break;
3094 case 4:
3095 val = kvm_read_cr4(&svm->vcpu);
3096 break;
3097 case 8:
3098 val = kvm_get_cr8(&svm->vcpu);
3099 break;
3100 default:
3101 WARN(1, "unhandled read from CR%d", cr);
3102 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3103 return 1;
3104 }
3105 kvm_register_write(&svm->vcpu, reg, val);
3106 }
3107 kvm_complete_insn_gp(&svm->vcpu, err);
3108
3109 return 1;
3110 }
3111
3112 static int dr_interception(struct vcpu_svm *svm)
3113 {
3114 int reg, dr;
3115 unsigned long val;
3116
3117 if (svm->vcpu.guest_debug == 0) {
3118 /*
3119 * No more DR vmexits; force a reload of the debug registers
3120 * and reenter on this instruction. The next vmexit will
3121 * retrieve the full state of the debug registers.
3122 */
3123 clr_dr_intercepts(svm);
3124 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3125 return 1;
3126 }
3127
3128 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3129 return emulate_on_interception(svm);
3130
3131 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3132 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3133
3134 if (dr >= 16) { /* mov to DRn */
3135 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3136 return 1;
3137 val = kvm_register_read(&svm->vcpu, reg);
3138 kvm_set_dr(&svm->vcpu, dr - 16, val);
3139 } else {
3140 if (!kvm_require_dr(&svm->vcpu, dr))
3141 return 1;
3142 kvm_get_dr(&svm->vcpu, dr, &val);
3143 kvm_register_write(&svm->vcpu, reg, val);
3144 }
3145
3146 skip_emulated_instruction(&svm->vcpu);
3147
3148 return 1;
3149 }
3150
3151 static int cr8_write_interception(struct vcpu_svm *svm)
3152 {
3153 struct kvm_run *kvm_run = svm->vcpu.run;
3154 int r;
3155
3156 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3157 /* instruction emulation calls kvm_set_cr8() */
3158 r = cr_interception(svm);
3159 if (irqchip_in_kernel(svm->vcpu.kvm))
3160 return r;
3161 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3162 return r;
3163 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3164 return 0;
3165 }
3166
3167 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3168 {
3169 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3170 return vmcb->control.tsc_offset +
3171 svm_scale_tsc(vcpu, host_tsc);
3172 }
3173
3174 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3175 {
3176 struct vcpu_svm *svm = to_svm(vcpu);
3177
3178 switch (msr_info->index) {
3179 case MSR_IA32_TSC: {
3180 msr_info->data = svm->vmcb->control.tsc_offset +
3181 svm_scale_tsc(vcpu, rdtsc());
3182
3183 break;
3184 }
3185 case MSR_STAR:
3186 msr_info->data = svm->vmcb->save.star;
3187 break;
3188 #ifdef CONFIG_X86_64
3189 case MSR_LSTAR:
3190 msr_info->data = svm->vmcb->save.lstar;
3191 break;
3192 case MSR_CSTAR:
3193 msr_info->data = svm->vmcb->save.cstar;
3194 break;
3195 case MSR_KERNEL_GS_BASE:
3196 msr_info->data = svm->vmcb->save.kernel_gs_base;
3197 break;
3198 case MSR_SYSCALL_MASK:
3199 msr_info->data = svm->vmcb->save.sfmask;
3200 break;
3201 #endif
3202 case MSR_IA32_SYSENTER_CS:
3203 msr_info->data = svm->vmcb->save.sysenter_cs;
3204 break;
3205 case MSR_IA32_SYSENTER_EIP:
3206 msr_info->data = svm->sysenter_eip;
3207 break;
3208 case MSR_IA32_SYSENTER_ESP:
3209 msr_info->data = svm->sysenter_esp;
3210 break;
3211 /*
3212 * Nobody will change the following 5 values in the VMCB so we can
3213 * safely return them on rdmsr. They will always be 0 until LBRV is
3214 * implemented.
3215 */
3216 case MSR_IA32_DEBUGCTLMSR:
3217 msr_info->data = svm->vmcb->save.dbgctl;
3218 break;
3219 case MSR_IA32_LASTBRANCHFROMIP:
3220 msr_info->data = svm->vmcb->save.br_from;
3221 break;
3222 case MSR_IA32_LASTBRANCHTOIP:
3223 msr_info->data = svm->vmcb->save.br_to;
3224 break;
3225 case MSR_IA32_LASTINTFROMIP:
3226 msr_info->data = svm->vmcb->save.last_excp_from;
3227 break;
3228 case MSR_IA32_LASTINTTOIP:
3229 msr_info->data = svm->vmcb->save.last_excp_to;
3230 break;
3231 case MSR_VM_HSAVE_PA:
3232 msr_info->data = svm->nested.hsave_msr;
3233 break;
3234 case MSR_VM_CR:
3235 msr_info->data = svm->nested.vm_cr_msr;
3236 break;
3237 case MSR_IA32_UCODE_REV:
3238 msr_info->data = 0x01000065;
3239 break;
3240 default:
3241 return kvm_get_msr_common(vcpu, msr_info);
3242 }
3243 return 0;
3244 }
3245
3246 static int rdmsr_interception(struct vcpu_svm *svm)
3247 {
3248 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3249 struct msr_data msr_info;
3250
3251 msr_info.index = ecx;
3252 msr_info.host_initiated = false;
3253 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3254 trace_kvm_msr_read_ex(ecx);
3255 kvm_inject_gp(&svm->vcpu, 0);
3256 } else {
3257 trace_kvm_msr_read(ecx, msr_info.data);
3258
3259 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3260 msr_info.data & 0xffffffff);
3261 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3262 msr_info.data >> 32);
3263 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3264 skip_emulated_instruction(&svm->vcpu);
3265 }
3266 return 1;
3267 }
3268
3269 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3270 {
3271 struct vcpu_svm *svm = to_svm(vcpu);
3272 int svm_dis, chg_mask;
3273
3274 if (data & ~SVM_VM_CR_VALID_MASK)
3275 return 1;
3276
3277 chg_mask = SVM_VM_CR_VALID_MASK;
3278
3279 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3280 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3281
3282 svm->nested.vm_cr_msr &= ~chg_mask;
3283 svm->nested.vm_cr_msr |= (data & chg_mask);
3284
3285 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3286
3287 /* check for svm_disable while efer.svme is set */
3288 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3289 return 1;
3290
3291 return 0;
3292 }
3293
3294 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3295 {
3296 struct vcpu_svm *svm = to_svm(vcpu);
3297
3298 u32 ecx = msr->index;
3299 u64 data = msr->data;
3300 switch (ecx) {
3301 case MSR_IA32_TSC:
3302 kvm_write_tsc(vcpu, msr);
3303 break;
3304 case MSR_STAR:
3305 svm->vmcb->save.star = data;
3306 break;
3307 #ifdef CONFIG_X86_64
3308 case MSR_LSTAR:
3309 svm->vmcb->save.lstar = data;
3310 break;
3311 case MSR_CSTAR:
3312 svm->vmcb->save.cstar = data;
3313 break;
3314 case MSR_KERNEL_GS_BASE:
3315 svm->vmcb->save.kernel_gs_base = data;
3316 break;
3317 case MSR_SYSCALL_MASK:
3318 svm->vmcb->save.sfmask = data;
3319 break;
3320 #endif
3321 case MSR_IA32_SYSENTER_CS:
3322 svm->vmcb->save.sysenter_cs = data;
3323 break;
3324 case MSR_IA32_SYSENTER_EIP:
3325 svm->sysenter_eip = data;
3326 svm->vmcb->save.sysenter_eip = data;
3327 break;
3328 case MSR_IA32_SYSENTER_ESP:
3329 svm->sysenter_esp = data;
3330 svm->vmcb->save.sysenter_esp = data;
3331 break;
3332 case MSR_IA32_DEBUGCTLMSR:
3333 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3334 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3335 __func__, data);
3336 break;
3337 }
3338 if (data & DEBUGCTL_RESERVED_BITS)
3339 return 1;
3340
3341 svm->vmcb->save.dbgctl = data;
3342 mark_dirty(svm->vmcb, VMCB_LBR);
3343 if (data & (1ULL<<0))
3344 svm_enable_lbrv(svm);
3345 else
3346 svm_disable_lbrv(svm);
3347 break;
3348 case MSR_VM_HSAVE_PA:
3349 svm->nested.hsave_msr = data;
3350 break;
3351 case MSR_VM_CR:
3352 return svm_set_vm_cr(vcpu, data);
3353 case MSR_VM_IGNNE:
3354 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3355 break;
3356 default:
3357 return kvm_set_msr_common(vcpu, msr);
3358 }
3359 return 0;
3360 }
3361
3362 static int wrmsr_interception(struct vcpu_svm *svm)
3363 {
3364 struct msr_data msr;
3365 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3366 u64 data = kvm_read_edx_eax(&svm->vcpu);
3367
3368 msr.data = data;
3369 msr.index = ecx;
3370 msr.host_initiated = false;
3371
3372 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3373 if (kvm_set_msr(&svm->vcpu, &msr)) {
3374 trace_kvm_msr_write_ex(ecx, data);
3375 kvm_inject_gp(&svm->vcpu, 0);
3376 } else {
3377 trace_kvm_msr_write(ecx, data);
3378 skip_emulated_instruction(&svm->vcpu);
3379 }
3380 return 1;
3381 }
3382
3383 static int msr_interception(struct vcpu_svm *svm)
3384 {
3385 if (svm->vmcb->control.exit_info_1)
3386 return wrmsr_interception(svm);
3387 else
3388 return rdmsr_interception(svm);
3389 }
3390
3391 static int interrupt_window_interception(struct vcpu_svm *svm)
3392 {
3393 struct kvm_run *kvm_run = svm->vcpu.run;
3394
3395 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3396 svm_clear_vintr(svm);
3397 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3398 mark_dirty(svm->vmcb, VMCB_INTR);
3399 ++svm->vcpu.stat.irq_window_exits;
3400 /*
3401 * If the user space waits to inject interrupts, exit as soon as
3402 * possible
3403 */
3404 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3405 kvm_run->request_interrupt_window &&
3406 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3407 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3408 return 0;
3409 }
3410
3411 return 1;
3412 }
3413
3414 static int pause_interception(struct vcpu_svm *svm)
3415 {
3416 kvm_vcpu_on_spin(&(svm->vcpu));
3417 return 1;
3418 }
3419
3420 static int nop_interception(struct vcpu_svm *svm)
3421 {
3422 skip_emulated_instruction(&(svm->vcpu));
3423 return 1;
3424 }
3425
3426 static int monitor_interception(struct vcpu_svm *svm)
3427 {
3428 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3429 return nop_interception(svm);
3430 }
3431
3432 static int mwait_interception(struct vcpu_svm *svm)
3433 {
3434 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3435 return nop_interception(svm);
3436 }
3437
3438 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3439 [SVM_EXIT_READ_CR0] = cr_interception,
3440 [SVM_EXIT_READ_CR3] = cr_interception,
3441 [SVM_EXIT_READ_CR4] = cr_interception,
3442 [SVM_EXIT_READ_CR8] = cr_interception,
3443 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3444 [SVM_EXIT_WRITE_CR0] = cr_interception,
3445 [SVM_EXIT_WRITE_CR3] = cr_interception,
3446 [SVM_EXIT_WRITE_CR4] = cr_interception,
3447 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3448 [SVM_EXIT_READ_DR0] = dr_interception,
3449 [SVM_EXIT_READ_DR1] = dr_interception,
3450 [SVM_EXIT_READ_DR2] = dr_interception,
3451 [SVM_EXIT_READ_DR3] = dr_interception,
3452 [SVM_EXIT_READ_DR4] = dr_interception,
3453 [SVM_EXIT_READ_DR5] = dr_interception,
3454 [SVM_EXIT_READ_DR6] = dr_interception,
3455 [SVM_EXIT_READ_DR7] = dr_interception,
3456 [SVM_EXIT_WRITE_DR0] = dr_interception,
3457 [SVM_EXIT_WRITE_DR1] = dr_interception,
3458 [SVM_EXIT_WRITE_DR2] = dr_interception,
3459 [SVM_EXIT_WRITE_DR3] = dr_interception,
3460 [SVM_EXIT_WRITE_DR4] = dr_interception,
3461 [SVM_EXIT_WRITE_DR5] = dr_interception,
3462 [SVM_EXIT_WRITE_DR6] = dr_interception,
3463 [SVM_EXIT_WRITE_DR7] = dr_interception,
3464 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3465 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3466 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3467 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3468 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3469 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3470 [SVM_EXIT_INTR] = intr_interception,
3471 [SVM_EXIT_NMI] = nmi_interception,
3472 [SVM_EXIT_SMI] = nop_on_interception,
3473 [SVM_EXIT_INIT] = nop_on_interception,
3474 [SVM_EXIT_VINTR] = interrupt_window_interception,
3475 [SVM_EXIT_RDPMC] = rdpmc_interception,
3476 [SVM_EXIT_CPUID] = cpuid_interception,
3477 [SVM_EXIT_IRET] = iret_interception,
3478 [SVM_EXIT_INVD] = emulate_on_interception,
3479 [SVM_EXIT_PAUSE] = pause_interception,
3480 [SVM_EXIT_HLT] = halt_interception,
3481 [SVM_EXIT_INVLPG] = invlpg_interception,
3482 [SVM_EXIT_INVLPGA] = invlpga_interception,
3483 [SVM_EXIT_IOIO] = io_interception,
3484 [SVM_EXIT_MSR] = msr_interception,
3485 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3486 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3487 [SVM_EXIT_VMRUN] = vmrun_interception,
3488 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3489 [SVM_EXIT_VMLOAD] = vmload_interception,
3490 [SVM_EXIT_VMSAVE] = vmsave_interception,
3491 [SVM_EXIT_STGI] = stgi_interception,
3492 [SVM_EXIT_CLGI] = clgi_interception,
3493 [SVM_EXIT_SKINIT] = skinit_interception,
3494 [SVM_EXIT_WBINVD] = wbinvd_interception,
3495 [SVM_EXIT_MONITOR] = monitor_interception,
3496 [SVM_EXIT_MWAIT] = mwait_interception,
3497 [SVM_EXIT_XSETBV] = xsetbv_interception,
3498 [SVM_EXIT_NPF] = pf_interception,
3499 [SVM_EXIT_RSM] = emulate_on_interception,
3500 };
3501
3502 static void dump_vmcb(struct kvm_vcpu *vcpu)
3503 {
3504 struct vcpu_svm *svm = to_svm(vcpu);
3505 struct vmcb_control_area *control = &svm->vmcb->control;
3506 struct vmcb_save_area *save = &svm->vmcb->save;
3507
3508 pr_err("VMCB Control Area:\n");
3509 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3510 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3511 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3512 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3513 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3514 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3515 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3516 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3517 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3518 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3519 pr_err("%-20s%d\n", "asid:", control->asid);
3520 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3521 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3522 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3523 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3524 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3525 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3526 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3527 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3528 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3529 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3530 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3531 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3532 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3533 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3534 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3535 pr_err("VMCB State Save Area:\n");
3536 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3537 "es:",
3538 save->es.selector, save->es.attrib,
3539 save->es.limit, save->es.base);
3540 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3541 "cs:",
3542 save->cs.selector, save->cs.attrib,
3543 save->cs.limit, save->cs.base);
3544 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3545 "ss:",
3546 save->ss.selector, save->ss.attrib,
3547 save->ss.limit, save->ss.base);
3548 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3549 "ds:",
3550 save->ds.selector, save->ds.attrib,
3551 save->ds.limit, save->ds.base);
3552 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3553 "fs:",
3554 save->fs.selector, save->fs.attrib,
3555 save->fs.limit, save->fs.base);
3556 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3557 "gs:",
3558 save->gs.selector, save->gs.attrib,
3559 save->gs.limit, save->gs.base);
3560 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3561 "gdtr:",
3562 save->gdtr.selector, save->gdtr.attrib,
3563 save->gdtr.limit, save->gdtr.base);
3564 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3565 "ldtr:",
3566 save->ldtr.selector, save->ldtr.attrib,
3567 save->ldtr.limit, save->ldtr.base);
3568 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3569 "idtr:",
3570 save->idtr.selector, save->idtr.attrib,
3571 save->idtr.limit, save->idtr.base);
3572 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3573 "tr:",
3574 save->tr.selector, save->tr.attrib,
3575 save->tr.limit, save->tr.base);
3576 pr_err("cpl: %d efer: %016llx\n",
3577 save->cpl, save->efer);
3578 pr_err("%-15s %016llx %-13s %016llx\n",
3579 "cr0:", save->cr0, "cr2:", save->cr2);
3580 pr_err("%-15s %016llx %-13s %016llx\n",
3581 "cr3:", save->cr3, "cr4:", save->cr4);
3582 pr_err("%-15s %016llx %-13s %016llx\n",
3583 "dr6:", save->dr6, "dr7:", save->dr7);
3584 pr_err("%-15s %016llx %-13s %016llx\n",
3585 "rip:", save->rip, "rflags:", save->rflags);
3586 pr_err("%-15s %016llx %-13s %016llx\n",
3587 "rsp:", save->rsp, "rax:", save->rax);
3588 pr_err("%-15s %016llx %-13s %016llx\n",
3589 "star:", save->star, "lstar:", save->lstar);
3590 pr_err("%-15s %016llx %-13s %016llx\n",
3591 "cstar:", save->cstar, "sfmask:", save->sfmask);
3592 pr_err("%-15s %016llx %-13s %016llx\n",
3593 "kernel_gs_base:", save->kernel_gs_base,
3594 "sysenter_cs:", save->sysenter_cs);
3595 pr_err("%-15s %016llx %-13s %016llx\n",
3596 "sysenter_esp:", save->sysenter_esp,
3597 "sysenter_eip:", save->sysenter_eip);
3598 pr_err("%-15s %016llx %-13s %016llx\n",
3599 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3600 pr_err("%-15s %016llx %-13s %016llx\n",
3601 "br_from:", save->br_from, "br_to:", save->br_to);
3602 pr_err("%-15s %016llx %-13s %016llx\n",
3603 "excp_from:", save->last_excp_from,
3604 "excp_to:", save->last_excp_to);
3605 }
3606
3607 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3608 {
3609 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3610
3611 *info1 = control->exit_info_1;
3612 *info2 = control->exit_info_2;
3613 }
3614
3615 static int handle_exit(struct kvm_vcpu *vcpu)
3616 {
3617 struct vcpu_svm *svm = to_svm(vcpu);
3618 struct kvm_run *kvm_run = vcpu->run;
3619 u32 exit_code = svm->vmcb->control.exit_code;
3620
3621 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3622 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3623 if (npt_enabled)
3624 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3625
3626 if (unlikely(svm->nested.exit_required)) {
3627 nested_svm_vmexit(svm);
3628 svm->nested.exit_required = false;
3629
3630 return 1;
3631 }
3632
3633 if (is_guest_mode(vcpu)) {
3634 int vmexit;
3635
3636 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3637 svm->vmcb->control.exit_info_1,
3638 svm->vmcb->control.exit_info_2,
3639 svm->vmcb->control.exit_int_info,
3640 svm->vmcb->control.exit_int_info_err,
3641 KVM_ISA_SVM);
3642
3643 vmexit = nested_svm_exit_special(svm);
3644
3645 if (vmexit == NESTED_EXIT_CONTINUE)
3646 vmexit = nested_svm_exit_handled(svm);
3647
3648 if (vmexit == NESTED_EXIT_DONE)
3649 return 1;
3650 }
3651
3652 svm_complete_interrupts(svm);
3653
3654 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3655 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3656 kvm_run->fail_entry.hardware_entry_failure_reason
3657 = svm->vmcb->control.exit_code;
3658 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3659 dump_vmcb(vcpu);
3660 return 0;
3661 }
3662
3663 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3664 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3665 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3666 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3667 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3668 "exit_code 0x%x\n",
3669 __func__, svm->vmcb->control.exit_int_info,
3670 exit_code);
3671
3672 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3673 || !svm_exit_handlers[exit_code]) {
3674 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3675 kvm_queue_exception(vcpu, UD_VECTOR);
3676 return 1;
3677 }
3678
3679 return svm_exit_handlers[exit_code](svm);
3680 }
3681
3682 static void reload_tss(struct kvm_vcpu *vcpu)
3683 {
3684 int cpu = raw_smp_processor_id();
3685
3686 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3687 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3688 load_TR_desc();
3689 }
3690
3691 static void pre_svm_run(struct vcpu_svm *svm)
3692 {
3693 int cpu = raw_smp_processor_id();
3694
3695 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3696
3697 /* FIXME: handle wraparound of asid_generation */
3698 if (svm->asid_generation != sd->asid_generation)
3699 new_asid(svm, sd);
3700 }
3701
3702 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3703 {
3704 struct vcpu_svm *svm = to_svm(vcpu);
3705
3706 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3707 vcpu->arch.hflags |= HF_NMI_MASK;
3708 set_intercept(svm, INTERCEPT_IRET);
3709 ++vcpu->stat.nmi_injections;
3710 }
3711
3712 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3713 {
3714 struct vmcb_control_area *control;
3715
3716 control = &svm->vmcb->control;
3717 control->int_vector = irq;
3718 control->int_ctl &= ~V_INTR_PRIO_MASK;
3719 control->int_ctl |= V_IRQ_MASK |
3720 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3721 mark_dirty(svm->vmcb, VMCB_INTR);
3722 }
3723
3724 static void svm_set_irq(struct kvm_vcpu *vcpu)
3725 {
3726 struct vcpu_svm *svm = to_svm(vcpu);
3727
3728 BUG_ON(!(gif_set(svm)));
3729
3730 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3731 ++vcpu->stat.irq_injections;
3732
3733 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3734 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3735 }
3736
3737 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3738 {
3739 struct vcpu_svm *svm = to_svm(vcpu);
3740
3741 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3742 return;
3743
3744 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3745
3746 if (irr == -1)
3747 return;
3748
3749 if (tpr >= irr)
3750 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3751 }
3752
3753 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3754 {
3755 return;
3756 }
3757
3758 static int svm_vm_has_apicv(struct kvm *kvm)
3759 {
3760 return 0;
3761 }
3762
3763 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3764 {
3765 return;
3766 }
3767
3768 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3769 {
3770 return;
3771 }
3772
3773 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3774 {
3775 struct vcpu_svm *svm = to_svm(vcpu);
3776 struct vmcb *vmcb = svm->vmcb;
3777 int ret;
3778 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3779 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3780 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3781
3782 return ret;
3783 }
3784
3785 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3786 {
3787 struct vcpu_svm *svm = to_svm(vcpu);
3788
3789 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3790 }
3791
3792 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3793 {
3794 struct vcpu_svm *svm = to_svm(vcpu);
3795
3796 if (masked) {
3797 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3798 set_intercept(svm, INTERCEPT_IRET);
3799 } else {
3800 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3801 clr_intercept(svm, INTERCEPT_IRET);
3802 }
3803 }
3804
3805 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3806 {
3807 struct vcpu_svm *svm = to_svm(vcpu);
3808 struct vmcb *vmcb = svm->vmcb;
3809 int ret;
3810
3811 if (!gif_set(svm) ||
3812 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3813 return 0;
3814
3815 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3816
3817 if (is_guest_mode(vcpu))
3818 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3819
3820 return ret;
3821 }
3822
3823 static void enable_irq_window(struct kvm_vcpu *vcpu)
3824 {
3825 struct vcpu_svm *svm = to_svm(vcpu);
3826
3827 /*
3828 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3829 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3830 * get that intercept, this function will be called again though and
3831 * we'll get the vintr intercept.
3832 */
3833 if (gif_set(svm) && nested_svm_intr(svm)) {
3834 svm_set_vintr(svm);
3835 svm_inject_irq(svm, 0x0);
3836 }
3837 }
3838
3839 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3840 {
3841 struct vcpu_svm *svm = to_svm(vcpu);
3842
3843 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3844 == HF_NMI_MASK)
3845 return; /* IRET will cause a vm exit */
3846
3847 /*
3848 * Something prevents NMI from been injected. Single step over possible
3849 * problem (IRET or exception injection or interrupt shadow)
3850 */
3851 svm->nmi_singlestep = true;
3852 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3853 update_db_bp_intercept(vcpu);
3854 }
3855
3856 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3857 {
3858 return 0;
3859 }
3860
3861 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3862 {
3863 struct vcpu_svm *svm = to_svm(vcpu);
3864
3865 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3866 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3867 else
3868 svm->asid_generation--;
3869 }
3870
3871 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3872 {
3873 }
3874
3875 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3876 {
3877 struct vcpu_svm *svm = to_svm(vcpu);
3878
3879 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3880 return;
3881
3882 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3883 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3884 kvm_set_cr8(vcpu, cr8);
3885 }
3886 }
3887
3888 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3889 {
3890 struct vcpu_svm *svm = to_svm(vcpu);
3891 u64 cr8;
3892
3893 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3894 return;
3895
3896 cr8 = kvm_get_cr8(vcpu);
3897 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3898 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3899 }
3900
3901 static void svm_complete_interrupts(struct vcpu_svm *svm)
3902 {
3903 u8 vector;
3904 int type;
3905 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3906 unsigned int3_injected = svm->int3_injected;
3907
3908 svm->int3_injected = 0;
3909
3910 /*
3911 * If we've made progress since setting HF_IRET_MASK, we've
3912 * executed an IRET and can allow NMI injection.
3913 */
3914 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3915 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3916 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3917 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3918 }
3919
3920 svm->vcpu.arch.nmi_injected = false;
3921 kvm_clear_exception_queue(&svm->vcpu);
3922 kvm_clear_interrupt_queue(&svm->vcpu);
3923
3924 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3925 return;
3926
3927 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3928
3929 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3930 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3931
3932 switch (type) {
3933 case SVM_EXITINTINFO_TYPE_NMI:
3934 svm->vcpu.arch.nmi_injected = true;
3935 break;
3936 case SVM_EXITINTINFO_TYPE_EXEPT:
3937 /*
3938 * In case of software exceptions, do not reinject the vector,
3939 * but re-execute the instruction instead. Rewind RIP first
3940 * if we emulated INT3 before.
3941 */
3942 if (kvm_exception_is_soft(vector)) {
3943 if (vector == BP_VECTOR && int3_injected &&
3944 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3945 kvm_rip_write(&svm->vcpu,
3946 kvm_rip_read(&svm->vcpu) -
3947 int3_injected);
3948 break;
3949 }
3950 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3951 u32 err = svm->vmcb->control.exit_int_info_err;
3952 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3953
3954 } else
3955 kvm_requeue_exception(&svm->vcpu, vector);
3956 break;
3957 case SVM_EXITINTINFO_TYPE_INTR:
3958 kvm_queue_interrupt(&svm->vcpu, vector, false);
3959 break;
3960 default:
3961 break;
3962 }
3963 }
3964
3965 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3966 {
3967 struct vcpu_svm *svm = to_svm(vcpu);
3968 struct vmcb_control_area *control = &svm->vmcb->control;
3969
3970 control->exit_int_info = control->event_inj;
3971 control->exit_int_info_err = control->event_inj_err;
3972 control->event_inj = 0;
3973 svm_complete_interrupts(svm);
3974 }
3975
3976 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3977 {
3978 struct vcpu_svm *svm = to_svm(vcpu);
3979
3980 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3981 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3982 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3983
3984 /*
3985 * A vmexit emulation is required before the vcpu can be executed
3986 * again.
3987 */
3988 if (unlikely(svm->nested.exit_required))
3989 return;
3990
3991 pre_svm_run(svm);
3992
3993 sync_lapic_to_cr8(vcpu);
3994
3995 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3996
3997 clgi();
3998
3999 local_irq_enable();
4000
4001 asm volatile (
4002 "push %%" _ASM_BP "; \n\t"
4003 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4004 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4005 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4006 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4007 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4008 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4009 #ifdef CONFIG_X86_64
4010 "mov %c[r8](%[svm]), %%r8 \n\t"
4011 "mov %c[r9](%[svm]), %%r9 \n\t"
4012 "mov %c[r10](%[svm]), %%r10 \n\t"
4013 "mov %c[r11](%[svm]), %%r11 \n\t"
4014 "mov %c[r12](%[svm]), %%r12 \n\t"
4015 "mov %c[r13](%[svm]), %%r13 \n\t"
4016 "mov %c[r14](%[svm]), %%r14 \n\t"
4017 "mov %c[r15](%[svm]), %%r15 \n\t"
4018 #endif
4019
4020 /* Enter guest mode */
4021 "push %%" _ASM_AX " \n\t"
4022 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4023 __ex(SVM_VMLOAD) "\n\t"
4024 __ex(SVM_VMRUN) "\n\t"
4025 __ex(SVM_VMSAVE) "\n\t"
4026 "pop %%" _ASM_AX " \n\t"
4027
4028 /* Save guest registers, load host registers */
4029 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4030 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4031 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4032 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4033 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4034 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4035 #ifdef CONFIG_X86_64
4036 "mov %%r8, %c[r8](%[svm]) \n\t"
4037 "mov %%r9, %c[r9](%[svm]) \n\t"
4038 "mov %%r10, %c[r10](%[svm]) \n\t"
4039 "mov %%r11, %c[r11](%[svm]) \n\t"
4040 "mov %%r12, %c[r12](%[svm]) \n\t"
4041 "mov %%r13, %c[r13](%[svm]) \n\t"
4042 "mov %%r14, %c[r14](%[svm]) \n\t"
4043 "mov %%r15, %c[r15](%[svm]) \n\t"
4044 #endif
4045 "pop %%" _ASM_BP
4046 :
4047 : [svm]"a"(svm),
4048 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4049 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4050 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4051 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4052 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4053 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4054 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4055 #ifdef CONFIG_X86_64
4056 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4057 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4058 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4059 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4060 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4061 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4062 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4063 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4064 #endif
4065 : "cc", "memory"
4066 #ifdef CONFIG_X86_64
4067 , "rbx", "rcx", "rdx", "rsi", "rdi"
4068 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4069 #else
4070 , "ebx", "ecx", "edx", "esi", "edi"
4071 #endif
4072 );
4073
4074 #ifdef CONFIG_X86_64
4075 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4076 #else
4077 loadsegment(fs, svm->host.fs);
4078 #ifndef CONFIG_X86_32_LAZY_GS
4079 loadsegment(gs, svm->host.gs);
4080 #endif
4081 #endif
4082
4083 reload_tss(vcpu);
4084
4085 local_irq_disable();
4086
4087 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4088 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4089 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4090 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4091
4092 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
4093
4094 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4095 kvm_before_handle_nmi(&svm->vcpu);
4096
4097 stgi();
4098
4099 /* Any pending NMI will happen here */
4100
4101 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4102 kvm_after_handle_nmi(&svm->vcpu);
4103
4104 sync_cr8_to_lapic(vcpu);
4105
4106 svm->next_rip = 0;
4107
4108 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4109
4110 /* if exit due to PF check for async PF */
4111 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4112 svm->apf_reason = kvm_read_and_reset_pf_reason();
4113
4114 if (npt_enabled) {
4115 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4116 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4117 }
4118
4119 /*
4120 * We need to handle MC intercepts here before the vcpu has a chance to
4121 * change the physical cpu
4122 */
4123 if (unlikely(svm->vmcb->control.exit_code ==
4124 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4125 svm_handle_mce(svm);
4126
4127 mark_all_clean(svm->vmcb);
4128 }
4129
4130 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4131 {
4132 struct vcpu_svm *svm = to_svm(vcpu);
4133
4134 svm->vmcb->save.cr3 = root;
4135 mark_dirty(svm->vmcb, VMCB_CR);
4136 svm_flush_tlb(vcpu);
4137 }
4138
4139 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4140 {
4141 struct vcpu_svm *svm = to_svm(vcpu);
4142
4143 svm->vmcb->control.nested_cr3 = root;
4144 mark_dirty(svm->vmcb, VMCB_NPT);
4145
4146 /* Also sync guest cr3 here in case we live migrate */
4147 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4148 mark_dirty(svm->vmcb, VMCB_CR);
4149
4150 svm_flush_tlb(vcpu);
4151 }
4152
4153 static int is_disabled(void)
4154 {
4155 u64 vm_cr;
4156
4157 rdmsrl(MSR_VM_CR, vm_cr);
4158 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4159 return 1;
4160
4161 return 0;
4162 }
4163
4164 static void
4165 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4166 {
4167 /*
4168 * Patch in the VMMCALL instruction:
4169 */
4170 hypercall[0] = 0x0f;
4171 hypercall[1] = 0x01;
4172 hypercall[2] = 0xd9;
4173 }
4174
4175 static void svm_check_processor_compat(void *rtn)
4176 {
4177 *(int *)rtn = 0;
4178 }
4179
4180 static bool svm_cpu_has_accelerated_tpr(void)
4181 {
4182 return false;
4183 }
4184
4185 static bool svm_has_high_real_mode_segbase(void)
4186 {
4187 return true;
4188 }
4189
4190 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4191 {
4192 }
4193
4194 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4195 {
4196 switch (func) {
4197 case 0x80000001:
4198 if (nested)
4199 entry->ecx |= (1 << 2); /* Set SVM bit */
4200 break;
4201 case 0x8000000A:
4202 entry->eax = 1; /* SVM revision 1 */
4203 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4204 ASID emulation to nested SVM */
4205 entry->ecx = 0; /* Reserved */
4206 entry->edx = 0; /* Per default do not support any
4207 additional features */
4208
4209 /* Support next_rip if host supports it */
4210 if (boot_cpu_has(X86_FEATURE_NRIPS))
4211 entry->edx |= SVM_FEATURE_NRIP;
4212
4213 /* Support NPT for the guest if enabled */
4214 if (npt_enabled)
4215 entry->edx |= SVM_FEATURE_NPT;
4216
4217 break;
4218 }
4219 }
4220
4221 static int svm_get_lpage_level(void)
4222 {
4223 return PT_PDPE_LEVEL;
4224 }
4225
4226 static bool svm_rdtscp_supported(void)
4227 {
4228 return false;
4229 }
4230
4231 static bool svm_invpcid_supported(void)
4232 {
4233 return false;
4234 }
4235
4236 static bool svm_mpx_supported(void)
4237 {
4238 return false;
4239 }
4240
4241 static bool svm_xsaves_supported(void)
4242 {
4243 return false;
4244 }
4245
4246 static bool svm_has_wbinvd_exit(void)
4247 {
4248 return true;
4249 }
4250
4251 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4252 {
4253 struct vcpu_svm *svm = to_svm(vcpu);
4254
4255 set_exception_intercept(svm, NM_VECTOR);
4256 update_cr0_intercept(svm);
4257 }
4258
4259 #define PRE_EX(exit) { .exit_code = (exit), \
4260 .stage = X86_ICPT_PRE_EXCEPT, }
4261 #define POST_EX(exit) { .exit_code = (exit), \
4262 .stage = X86_ICPT_POST_EXCEPT, }
4263 #define POST_MEM(exit) { .exit_code = (exit), \
4264 .stage = X86_ICPT_POST_MEMACCESS, }
4265
4266 static const struct __x86_intercept {
4267 u32 exit_code;
4268 enum x86_intercept_stage stage;
4269 } x86_intercept_map[] = {
4270 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4271 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4272 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4273 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4274 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4275 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4276 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4277 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4278 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4279 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4280 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4281 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4282 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4283 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4284 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4285 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4286 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4287 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4288 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4289 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4290 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4291 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4292 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4293 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4294 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4295 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4296 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4297 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4298 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4299 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4300 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4301 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4302 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4303 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4304 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4305 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4306 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4307 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4308 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4309 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4310 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4311 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4312 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4313 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4314 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4315 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4316 };
4317
4318 #undef PRE_EX
4319 #undef POST_EX
4320 #undef POST_MEM
4321
4322 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4323 struct x86_instruction_info *info,
4324 enum x86_intercept_stage stage)
4325 {
4326 struct vcpu_svm *svm = to_svm(vcpu);
4327 int vmexit, ret = X86EMUL_CONTINUE;
4328 struct __x86_intercept icpt_info;
4329 struct vmcb *vmcb = svm->vmcb;
4330
4331 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4332 goto out;
4333
4334 icpt_info = x86_intercept_map[info->intercept];
4335
4336 if (stage != icpt_info.stage)
4337 goto out;
4338
4339 switch (icpt_info.exit_code) {
4340 case SVM_EXIT_READ_CR0:
4341 if (info->intercept == x86_intercept_cr_read)
4342 icpt_info.exit_code += info->modrm_reg;
4343 break;
4344 case SVM_EXIT_WRITE_CR0: {
4345 unsigned long cr0, val;
4346 u64 intercept;
4347
4348 if (info->intercept == x86_intercept_cr_write)
4349 icpt_info.exit_code += info->modrm_reg;
4350
4351 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4352 info->intercept == x86_intercept_clts)
4353 break;
4354
4355 intercept = svm->nested.intercept;
4356
4357 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4358 break;
4359
4360 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4361 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4362
4363 if (info->intercept == x86_intercept_lmsw) {
4364 cr0 &= 0xfUL;
4365 val &= 0xfUL;
4366 /* lmsw can't clear PE - catch this here */
4367 if (cr0 & X86_CR0_PE)
4368 val |= X86_CR0_PE;
4369 }
4370
4371 if (cr0 ^ val)
4372 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4373
4374 break;
4375 }
4376 case SVM_EXIT_READ_DR0:
4377 case SVM_EXIT_WRITE_DR0:
4378 icpt_info.exit_code += info->modrm_reg;
4379 break;
4380 case SVM_EXIT_MSR:
4381 if (info->intercept == x86_intercept_wrmsr)
4382 vmcb->control.exit_info_1 = 1;
4383 else
4384 vmcb->control.exit_info_1 = 0;
4385 break;
4386 case SVM_EXIT_PAUSE:
4387 /*
4388 * We get this for NOP only, but pause
4389 * is rep not, check this here
4390 */
4391 if (info->rep_prefix != REPE_PREFIX)
4392 goto out;
4393 case SVM_EXIT_IOIO: {
4394 u64 exit_info;
4395 u32 bytes;
4396
4397 if (info->intercept == x86_intercept_in ||
4398 info->intercept == x86_intercept_ins) {
4399 exit_info = ((info->src_val & 0xffff) << 16) |
4400 SVM_IOIO_TYPE_MASK;
4401 bytes = info->dst_bytes;
4402 } else {
4403 exit_info = (info->dst_val & 0xffff) << 16;
4404 bytes = info->src_bytes;
4405 }
4406
4407 if (info->intercept == x86_intercept_outs ||
4408 info->intercept == x86_intercept_ins)
4409 exit_info |= SVM_IOIO_STR_MASK;
4410
4411 if (info->rep_prefix)
4412 exit_info |= SVM_IOIO_REP_MASK;
4413
4414 bytes = min(bytes, 4u);
4415
4416 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4417
4418 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4419
4420 vmcb->control.exit_info_1 = exit_info;
4421 vmcb->control.exit_info_2 = info->next_rip;
4422
4423 break;
4424 }
4425 default:
4426 break;
4427 }
4428
4429 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4430 if (static_cpu_has(X86_FEATURE_NRIPS))
4431 vmcb->control.next_rip = info->next_rip;
4432 vmcb->control.exit_code = icpt_info.exit_code;
4433 vmexit = nested_svm_exit_handled(svm);
4434
4435 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4436 : X86EMUL_CONTINUE;
4437
4438 out:
4439 return ret;
4440 }
4441
4442 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4443 {
4444 local_irq_enable();
4445 }
4446
4447 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4448 {
4449 }
4450
4451 static struct kvm_x86_ops svm_x86_ops = {
4452 .cpu_has_kvm_support = has_svm,
4453 .disabled_by_bios = is_disabled,
4454 .hardware_setup = svm_hardware_setup,
4455 .hardware_unsetup = svm_hardware_unsetup,
4456 .check_processor_compatibility = svm_check_processor_compat,
4457 .hardware_enable = svm_hardware_enable,
4458 .hardware_disable = svm_hardware_disable,
4459 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4460 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4461
4462 .vcpu_create = svm_create_vcpu,
4463 .vcpu_free = svm_free_vcpu,
4464 .vcpu_reset = svm_vcpu_reset,
4465
4466 .prepare_guest_switch = svm_prepare_guest_switch,
4467 .vcpu_load = svm_vcpu_load,
4468 .vcpu_put = svm_vcpu_put,
4469
4470 .update_db_bp_intercept = update_db_bp_intercept,
4471 .get_msr = svm_get_msr,
4472 .set_msr = svm_set_msr,
4473 .get_segment_base = svm_get_segment_base,
4474 .get_segment = svm_get_segment,
4475 .set_segment = svm_set_segment,
4476 .get_cpl = svm_get_cpl,
4477 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4478 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4479 .decache_cr3 = svm_decache_cr3,
4480 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4481 .set_cr0 = svm_set_cr0,
4482 .set_cr3 = svm_set_cr3,
4483 .set_cr4 = svm_set_cr4,
4484 .set_efer = svm_set_efer,
4485 .get_idt = svm_get_idt,
4486 .set_idt = svm_set_idt,
4487 .get_gdt = svm_get_gdt,
4488 .set_gdt = svm_set_gdt,
4489 .get_dr6 = svm_get_dr6,
4490 .set_dr6 = svm_set_dr6,
4491 .set_dr7 = svm_set_dr7,
4492 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4493 .cache_reg = svm_cache_reg,
4494 .get_rflags = svm_get_rflags,
4495 .set_rflags = svm_set_rflags,
4496 .fpu_activate = svm_fpu_activate,
4497 .fpu_deactivate = svm_fpu_deactivate,
4498
4499 .tlb_flush = svm_flush_tlb,
4500
4501 .run = svm_vcpu_run,
4502 .handle_exit = handle_exit,
4503 .skip_emulated_instruction = skip_emulated_instruction,
4504 .set_interrupt_shadow = svm_set_interrupt_shadow,
4505 .get_interrupt_shadow = svm_get_interrupt_shadow,
4506 .patch_hypercall = svm_patch_hypercall,
4507 .set_irq = svm_set_irq,
4508 .set_nmi = svm_inject_nmi,
4509 .queue_exception = svm_queue_exception,
4510 .cancel_injection = svm_cancel_injection,
4511 .interrupt_allowed = svm_interrupt_allowed,
4512 .nmi_allowed = svm_nmi_allowed,
4513 .get_nmi_mask = svm_get_nmi_mask,
4514 .set_nmi_mask = svm_set_nmi_mask,
4515 .enable_nmi_window = enable_nmi_window,
4516 .enable_irq_window = enable_irq_window,
4517 .update_cr8_intercept = update_cr8_intercept,
4518 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4519 .vm_has_apicv = svm_vm_has_apicv,
4520 .load_eoi_exitmap = svm_load_eoi_exitmap,
4521 .sync_pir_to_irr = svm_sync_pir_to_irr,
4522
4523 .set_tss_addr = svm_set_tss_addr,
4524 .get_tdp_level = get_npt_level,
4525 .get_mt_mask = svm_get_mt_mask,
4526
4527 .get_exit_info = svm_get_exit_info,
4528
4529 .get_lpage_level = svm_get_lpage_level,
4530
4531 .cpuid_update = svm_cpuid_update,
4532
4533 .rdtscp_supported = svm_rdtscp_supported,
4534 .invpcid_supported = svm_invpcid_supported,
4535 .mpx_supported = svm_mpx_supported,
4536 .xsaves_supported = svm_xsaves_supported,
4537
4538 .set_supported_cpuid = svm_set_supported_cpuid,
4539
4540 .has_wbinvd_exit = svm_has_wbinvd_exit,
4541
4542 .set_tsc_khz = svm_set_tsc_khz,
4543 .read_tsc_offset = svm_read_tsc_offset,
4544 .write_tsc_offset = svm_write_tsc_offset,
4545 .adjust_tsc_offset = svm_adjust_tsc_offset,
4546 .compute_tsc_offset = svm_compute_tsc_offset,
4547 .read_l1_tsc = svm_read_l1_tsc,
4548
4549 .set_tdp_cr3 = set_tdp_cr3,
4550
4551 .check_intercept = svm_check_intercept,
4552 .handle_external_intr = svm_handle_external_intr,
4553
4554 .sched_in = svm_sched_in,
4555
4556 .pmu_ops = &amd_pmu_ops,
4557 };
4558
4559 static int __init svm_init(void)
4560 {
4561 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4562 __alignof__(struct vcpu_svm), THIS_MODULE);
4563 }
4564
4565 static void __exit svm_exit(void)
4566 {
4567 kvm_exit();
4568 }
4569
4570 module_init(svm_init)
4571 module_exit(svm_exit)
Linux kernel - Deliverables
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