projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: SVM: Set the 'busy' flag of the TR selector
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28
29 #include <asm/desc.h>
30
31 #define __ex(x) __kvm_handle_fault_on_reboot(x)
32
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
35
36 #define IOPM_ALLOC_ORDER 2
37 #define MSRPM_ALLOC_ORDER 1
38
39 #define DR7_GD_MASK (1 << 13)
40 #define DR6_BD_MASK (1 << 13)
41
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
44
45 #define SVM_FEATURE_NPT (1 << 0)
46 #define SVM_FEATURE_LBRV (1 << 1)
47 #define SVM_FEATURE_SVML (1 << 2)
48
49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50
51 /* enable NPT for AMD64 and X86 with PAE */
52 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
53 static bool npt_enabled = true;
54 #else
55 static bool npt_enabled = false;
56 #endif
57 static int npt = 1;
58
59 module_param(npt, int, S_IRUGO);
60
61 static void kvm_reput_irq(struct vcpu_svm *svm);
62 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
63
64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
65 {
66 return container_of(vcpu, struct vcpu_svm, vcpu);
67 }
68
69 static unsigned long iopm_base;
70
71 struct kvm_ldttss_desc {
72 u16 limit0;
73 u16 base0;
74 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
75 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
76 u32 base3;
77 u32 zero1;
78 } __attribute__((packed));
79
80 struct svm_cpu_data {
81 int cpu;
82
83 u64 asid_generation;
84 u32 max_asid;
85 u32 next_asid;
86 struct kvm_ldttss_desc *tss_desc;
87
88 struct page *save_area;
89 };
90
91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
92 static uint32_t svm_features;
93
94 struct svm_init_data {
95 int cpu;
96 int r;
97 };
98
99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
100
101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
102 #define MSRS_RANGE_SIZE 2048
103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
104
105 #define MAX_INST_SIZE 15
106
107 static inline u32 svm_has(u32 feat)
108 {
109 return svm_features & feat;
110 }
111
112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
113 {
114 int word_index = __ffs(vcpu->arch.irq_summary);
115 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
116 int irq = word_index * BITS_PER_LONG + bit_index;
117
118 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
119 if (!vcpu->arch.irq_pending[word_index])
120 clear_bit(word_index, &vcpu->arch.irq_summary);
121 return irq;
122 }
123
124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
125 {
126 set_bit(irq, vcpu->arch.irq_pending);
127 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
128 }
129
130 static inline void clgi(void)
131 {
132 asm volatile (__ex(SVM_CLGI));
133 }
134
135 static inline void stgi(void)
136 {
137 asm volatile (__ex(SVM_STGI));
138 }
139
140 static inline void invlpga(unsigned long addr, u32 asid)
141 {
142 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
143 }
144
145 static inline unsigned long kvm_read_cr2(void)
146 {
147 unsigned long cr2;
148
149 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
150 return cr2;
151 }
152
153 static inline void kvm_write_cr2(unsigned long val)
154 {
155 asm volatile ("mov %0, %%cr2" :: "r" (val));
156 }
157
158 static inline unsigned long read_dr6(void)
159 {
160 unsigned long dr6;
161
162 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
163 return dr6;
164 }
165
166 static inline void write_dr6(unsigned long val)
167 {
168 asm volatile ("mov %0, %%dr6" :: "r" (val));
169 }
170
171 static inline unsigned long read_dr7(void)
172 {
173 unsigned long dr7;
174
175 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
176 return dr7;
177 }
178
179 static inline void write_dr7(unsigned long val)
180 {
181 asm volatile ("mov %0, %%dr7" :: "r" (val));
182 }
183
184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
185 {
186 to_svm(vcpu)->asid_generation--;
187 }
188
189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
190 {
191 force_new_asid(vcpu);
192 }
193
194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
195 {
196 if (!npt_enabled && !(efer & EFER_LMA))
197 efer &= ~EFER_LME;
198
199 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
200 vcpu->arch.shadow_efer = efer;
201 }
202
203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
204 bool has_error_code, u32 error_code)
205 {
206 struct vcpu_svm *svm = to_svm(vcpu);
207
208 svm->vmcb->control.event_inj = nr
209 | SVM_EVTINJ_VALID
210 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
211 | SVM_EVTINJ_TYPE_EXEPT;
212 svm->vmcb->control.event_inj_err = error_code;
213 }
214
215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
216 {
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
220 }
221
222 static int is_external_interrupt(u32 info)
223 {
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226 }
227
228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229 {
230 struct vcpu_svm *svm = to_svm(vcpu);
231
232 if (!svm->next_rip) {
233 printk(KERN_DEBUG "%s: NOP\n", __func__);
234 return;
235 }
236 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
237 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
238 __func__, kvm_rip_read(vcpu), svm->next_rip);
239
240 kvm_rip_write(vcpu, svm->next_rip);
241 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
242
243 vcpu->arch.interrupt_window_open = 1;
244 }
245
246 static int has_svm(void)
247 {
248 uint32_t eax, ebx, ecx, edx;
249
250 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
251 printk(KERN_INFO "has_svm: not amd\n");
252 return 0;
253 }
254
255 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
256 if (eax < SVM_CPUID_FUNC) {
257 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
258 return 0;
259 }
260
261 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
262 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
263 printk(KERN_DEBUG "has_svm: svm not available\n");
264 return 0;
265 }
266 return 1;
267 }
268
269 static void svm_hardware_disable(void *garbage)
270 {
271 uint64_t efer;
272
273 wrmsrl(MSR_VM_HSAVE_PA, 0);
274 rdmsrl(MSR_EFER, efer);
275 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
276 }
277
278 static void svm_hardware_enable(void *garbage)
279 {
280
281 struct svm_cpu_data *svm_data;
282 uint64_t efer;
283 struct desc_ptr gdt_descr;
284 struct desc_struct *gdt;
285 int me = raw_smp_processor_id();
286
287 if (!has_svm()) {
288 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
289 return;
290 }
291 svm_data = per_cpu(svm_data, me);
292
293 if (!svm_data) {
294 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
295 me);
296 return;
297 }
298
299 svm_data->asid_generation = 1;
300 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
301 svm_data->next_asid = svm_data->max_asid + 1;
302
303 asm volatile ("sgdt %0" : "=m"(gdt_descr));
304 gdt = (struct desc_struct *)gdt_descr.address;
305 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
306
307 rdmsrl(MSR_EFER, efer);
308 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
309
310 wrmsrl(MSR_VM_HSAVE_PA,
311 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
312 }
313
314 static void svm_cpu_uninit(int cpu)
315 {
316 struct svm_cpu_data *svm_data
317 = per_cpu(svm_data, raw_smp_processor_id());
318
319 if (!svm_data)
320 return;
321
322 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
323 __free_page(svm_data->save_area);
324 kfree(svm_data);
325 }
326
327 static int svm_cpu_init(int cpu)
328 {
329 struct svm_cpu_data *svm_data;
330 int r;
331
332 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
333 if (!svm_data)
334 return -ENOMEM;
335 svm_data->cpu = cpu;
336 svm_data->save_area = alloc_page(GFP_KERNEL);
337 r = -ENOMEM;
338 if (!svm_data->save_area)
339 goto err_1;
340
341 per_cpu(svm_data, cpu) = svm_data;
342
343 return 0;
344
345 err_1:
346 kfree(svm_data);
347 return r;
348
349 }
350
351 static void set_msr_interception(u32 *msrpm, unsigned msr,
352 int read, int write)
353 {
354 int i;
355
356 for (i = 0; i < NUM_MSR_MAPS; i++) {
357 if (msr >= msrpm_ranges[i] &&
358 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
359 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
360 msrpm_ranges[i]) * 2;
361
362 u32 *base = msrpm + (msr_offset / 32);
363 u32 msr_shift = msr_offset % 32;
364 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
365 *base = (*base & ~(0x3 << msr_shift)) |
366 (mask << msr_shift);
367 return;
368 }
369 }
370 BUG();
371 }
372
373 static void svm_vcpu_init_msrpm(u32 *msrpm)
374 {
375 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
376
377 #ifdef CONFIG_X86_64
378 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
379 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
380 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
381 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
382 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
383 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
384 #endif
385 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
386 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
387 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
388 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
389 }
390
391 static void svm_enable_lbrv(struct vcpu_svm *svm)
392 {
393 u32 *msrpm = svm->msrpm;
394
395 svm->vmcb->control.lbr_ctl = 1;
396 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
397 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
398 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
399 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
400 }
401
402 static void svm_disable_lbrv(struct vcpu_svm *svm)
403 {
404 u32 *msrpm = svm->msrpm;
405
406 svm->vmcb->control.lbr_ctl = 0;
407 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
408 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
409 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
410 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
411 }
412
413 static __init int svm_hardware_setup(void)
414 {
415 int cpu;
416 struct page *iopm_pages;
417 void *iopm_va;
418 int r;
419
420 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
421
422 if (!iopm_pages)
423 return -ENOMEM;
424
425 iopm_va = page_address(iopm_pages);
426 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
427 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
428 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
429
430 if (boot_cpu_has(X86_FEATURE_NX))
431 kvm_enable_efer_bits(EFER_NX);
432
433 for_each_online_cpu(cpu) {
434 r = svm_cpu_init(cpu);
435 if (r)
436 goto err;
437 }
438
439 svm_features = cpuid_edx(SVM_CPUID_FUNC);
440
441 if (!svm_has(SVM_FEATURE_NPT))
442 npt_enabled = false;
443
444 if (npt_enabled && !npt) {
445 printk(KERN_INFO "kvm: Nested Paging disabled\n");
446 npt_enabled = false;
447 }
448
449 if (npt_enabled) {
450 printk(KERN_INFO "kvm: Nested Paging enabled\n");
451 kvm_enable_tdp();
452 } else
453 kvm_disable_tdp();
454
455 return 0;
456
457 err:
458 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
459 iopm_base = 0;
460 return r;
461 }
462
463 static __exit void svm_hardware_unsetup(void)
464 {
465 int cpu;
466
467 for_each_online_cpu(cpu)
468 svm_cpu_uninit(cpu);
469
470 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
471 iopm_base = 0;
472 }
473
474 static void init_seg(struct vmcb_seg *seg)
475 {
476 seg->selector = 0;
477 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
478 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
479 seg->limit = 0xffff;
480 seg->base = 0;
481 }
482
483 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
484 {
485 seg->selector = 0;
486 seg->attrib = SVM_SELECTOR_P_MASK | type;
487 seg->limit = 0xffff;
488 seg->base = 0;
489 }
490
491 static void init_vmcb(struct vcpu_svm *svm)
492 {
493 struct vmcb_control_area *control = &svm->vmcb->control;
494 struct vmcb_save_area *save = &svm->vmcb->save;
495
496 control->intercept_cr_read = INTERCEPT_CR0_MASK |
497 INTERCEPT_CR3_MASK |
498 INTERCEPT_CR4_MASK;
499
500 control->intercept_cr_write = INTERCEPT_CR0_MASK |
501 INTERCEPT_CR3_MASK |
502 INTERCEPT_CR4_MASK |
503 INTERCEPT_CR8_MASK;
504
505 control->intercept_dr_read = INTERCEPT_DR0_MASK |
506 INTERCEPT_DR1_MASK |
507 INTERCEPT_DR2_MASK |
508 INTERCEPT_DR3_MASK;
509
510 control->intercept_dr_write = INTERCEPT_DR0_MASK |
511 INTERCEPT_DR1_MASK |
512 INTERCEPT_DR2_MASK |
513 INTERCEPT_DR3_MASK |
514 INTERCEPT_DR5_MASK |
515 INTERCEPT_DR7_MASK;
516
517 control->intercept_exceptions = (1 << PF_VECTOR) |
518 (1 << UD_VECTOR) |
519 (1 << MC_VECTOR);
520
521
522 control->intercept = (1ULL << INTERCEPT_INTR) |
523 (1ULL << INTERCEPT_NMI) |
524 (1ULL << INTERCEPT_SMI) |
525 (1ULL << INTERCEPT_CPUID) |
526 (1ULL << INTERCEPT_INVD) |
527 (1ULL << INTERCEPT_HLT) |
528 (1ULL << INTERCEPT_INVLPG) |
529 (1ULL << INTERCEPT_INVLPGA) |
530 (1ULL << INTERCEPT_IOIO_PROT) |
531 (1ULL << INTERCEPT_MSR_PROT) |
532 (1ULL << INTERCEPT_TASK_SWITCH) |
533 (1ULL << INTERCEPT_SHUTDOWN) |
534 (1ULL << INTERCEPT_VMRUN) |
535 (1ULL << INTERCEPT_VMMCALL) |
536 (1ULL << INTERCEPT_VMLOAD) |
537 (1ULL << INTERCEPT_VMSAVE) |
538 (1ULL << INTERCEPT_STGI) |
539 (1ULL << INTERCEPT_CLGI) |
540 (1ULL << INTERCEPT_SKINIT) |
541 (1ULL << INTERCEPT_WBINVD) |
542 (1ULL << INTERCEPT_MONITOR) |
543 (1ULL << INTERCEPT_MWAIT);
544
545 control->iopm_base_pa = iopm_base;
546 control->msrpm_base_pa = __pa(svm->msrpm);
547 control->tsc_offset = 0;
548 control->int_ctl = V_INTR_MASKING_MASK;
549
550 init_seg(&save->es);
551 init_seg(&save->ss);
552 init_seg(&save->ds);
553 init_seg(&save->fs);
554 init_seg(&save->gs);
555
556 save->cs.selector = 0xf000;
557 /* Executable/Readable Code Segment */
558 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
559 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
560 save->cs.limit = 0xffff;
561 /*
562 * cs.base should really be 0xffff0000, but vmx can't handle that, so
563 * be consistent with it.
564 *
565 * Replace when we have real mode working for vmx.
566 */
567 save->cs.base = 0xf0000;
568
569 save->gdtr.limit = 0xffff;
570 save->idtr.limit = 0xffff;
571
572 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
573 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
574
575 save->efer = MSR_EFER_SVME_MASK;
576 save->dr6 = 0xffff0ff0;
577 save->dr7 = 0x400;
578 save->rflags = 2;
579 save->rip = 0x0000fff0;
580 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
581
582 /*
583 * cr0 val on cpu init should be 0x60000010, we enable cpu
584 * cache by default. the orderly way is to enable cache in bios.
585 */
586 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
587 save->cr4 = X86_CR4_PAE;
588 /* rdx = ?? */
589
590 if (npt_enabled) {
591 /* Setup VMCB for Nested Paging */
592 control->nested_ctl = 1;
593 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
594 (1ULL << INTERCEPT_INVLPG));
595 control->intercept_exceptions &= ~(1 << PF_VECTOR);
596 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
597 INTERCEPT_CR3_MASK);
598 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
599 INTERCEPT_CR3_MASK);
600 save->g_pat = 0x0007040600070406ULL;
601 /* enable caching because the QEMU Bios doesn't enable it */
602 save->cr0 = X86_CR0_ET;
603 save->cr3 = 0;
604 save->cr4 = 0;
605 }
606 force_new_asid(&svm->vcpu);
607 }
608
609 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
610 {
611 struct vcpu_svm *svm = to_svm(vcpu);
612
613 init_vmcb(svm);
614
615 if (vcpu->vcpu_id != 0) {
616 kvm_rip_write(vcpu, 0);
617 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
618 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
619 }
620 vcpu->arch.regs_avail = ~0;
621 vcpu->arch.regs_dirty = ~0;
622
623 return 0;
624 }
625
626 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
627 {
628 struct vcpu_svm *svm;
629 struct page *page;
630 struct page *msrpm_pages;
631 int err;
632
633 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
634 if (!svm) {
635 err = -ENOMEM;
636 goto out;
637 }
638
639 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
640 if (err)
641 goto free_svm;
642
643 page = alloc_page(GFP_KERNEL);
644 if (!page) {
645 err = -ENOMEM;
646 goto uninit;
647 }
648
649 err = -ENOMEM;
650 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
651 if (!msrpm_pages)
652 goto uninit;
653 svm->msrpm = page_address(msrpm_pages);
654 svm_vcpu_init_msrpm(svm->msrpm);
655
656 svm->vmcb = page_address(page);
657 clear_page(svm->vmcb);
658 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
659 svm->asid_generation = 0;
660 memset(svm->db_regs, 0, sizeof(svm->db_regs));
661 init_vmcb(svm);
662
663 fx_init(&svm->vcpu);
664 svm->vcpu.fpu_active = 1;
665 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
666 if (svm->vcpu.vcpu_id == 0)
667 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
668
669 return &svm->vcpu;
670
671 uninit:
672 kvm_vcpu_uninit(&svm->vcpu);
673 free_svm:
674 kmem_cache_free(kvm_vcpu_cache, svm);
675 out:
676 return ERR_PTR(err);
677 }
678
679 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
680 {
681 struct vcpu_svm *svm = to_svm(vcpu);
682
683 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
684 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
685 kvm_vcpu_uninit(vcpu);
686 kmem_cache_free(kvm_vcpu_cache, svm);
687 }
688
689 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
690 {
691 struct vcpu_svm *svm = to_svm(vcpu);
692 int i;
693
694 if (unlikely(cpu != vcpu->cpu)) {
695 u64 tsc_this, delta;
696
697 /*
698 * Make sure that the guest sees a monotonically
699 * increasing TSC.
700 */
701 rdtscll(tsc_this);
702 delta = vcpu->arch.host_tsc - tsc_this;
703 svm->vmcb->control.tsc_offset += delta;
704 vcpu->cpu = cpu;
705 kvm_migrate_timers(vcpu);
706 }
707
708 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
709 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
710 }
711
712 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
713 {
714 struct vcpu_svm *svm = to_svm(vcpu);
715 int i;
716
717 ++vcpu->stat.host_state_reload;
718 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
719 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
720
721 rdtscll(vcpu->arch.host_tsc);
722 }
723
724 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
725 {
726 return to_svm(vcpu)->vmcb->save.rflags;
727 }
728
729 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
730 {
731 to_svm(vcpu)->vmcb->save.rflags = rflags;
732 }
733
734 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
735 {
736 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
737
738 switch (seg) {
739 case VCPU_SREG_CS: return &save->cs;
740 case VCPU_SREG_DS: return &save->ds;
741 case VCPU_SREG_ES: return &save->es;
742 case VCPU_SREG_FS: return &save->fs;
743 case VCPU_SREG_GS: return &save->gs;
744 case VCPU_SREG_SS: return &save->ss;
745 case VCPU_SREG_TR: return &save->tr;
746 case VCPU_SREG_LDTR: return &save->ldtr;
747 }
748 BUG();
749 return NULL;
750 }
751
752 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
753 {
754 struct vmcb_seg *s = svm_seg(vcpu, seg);
755
756 return s->base;
757 }
758
759 static void svm_get_segment(struct kvm_vcpu *vcpu,
760 struct kvm_segment *var, int seg)
761 {
762 struct vmcb_seg *s = svm_seg(vcpu, seg);
763
764 var->base = s->base;
765 var->limit = s->limit;
766 var->selector = s->selector;
767 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
768 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
769 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
770 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
771 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
772 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
773 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
774 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
775
776 /*
777 * SVM always stores 0 for the 'G' bit in the CS selector in
778 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
779 * Intel's VMENTRY has a check on the 'G' bit.
780 */
781 if (seg == VCPU_SREG_CS)
782 var->g = s->limit > 0xfffff;
783
784 /*
785 * Work around a bug where the busy flag in the tr selector
786 * isn't exposed
787 */
788 if (seg == VCPU_SREG_TR)
789 var->type |= 0x2;
790
791 var->unusable = !var->present;
792 }
793
794 static int svm_get_cpl(struct kvm_vcpu *vcpu)
795 {
796 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
797
798 return save->cpl;
799 }
800
801 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
802 {
803 struct vcpu_svm *svm = to_svm(vcpu);
804
805 dt->limit = svm->vmcb->save.idtr.limit;
806 dt->base = svm->vmcb->save.idtr.base;
807 }
808
809 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
810 {
811 struct vcpu_svm *svm = to_svm(vcpu);
812
813 svm->vmcb->save.idtr.limit = dt->limit;
814 svm->vmcb->save.idtr.base = dt->base ;
815 }
816
817 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
818 {
819 struct vcpu_svm *svm = to_svm(vcpu);
820
821 dt->limit = svm->vmcb->save.gdtr.limit;
822 dt->base = svm->vmcb->save.gdtr.base;
823 }
824
825 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
826 {
827 struct vcpu_svm *svm = to_svm(vcpu);
828
829 svm->vmcb->save.gdtr.limit = dt->limit;
830 svm->vmcb->save.gdtr.base = dt->base ;
831 }
832
833 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
834 {
835 }
836
837 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
838 {
839 struct vcpu_svm *svm = to_svm(vcpu);
840
841 #ifdef CONFIG_X86_64
842 if (vcpu->arch.shadow_efer & EFER_LME) {
843 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
844 vcpu->arch.shadow_efer |= EFER_LMA;
845 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
846 }
847
848 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
849 vcpu->arch.shadow_efer &= ~EFER_LMA;
850 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
851 }
852 }
853 #endif
854 if (npt_enabled)
855 goto set;
856
857 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
858 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
859 vcpu->fpu_active = 1;
860 }
861
862 vcpu->arch.cr0 = cr0;
863 cr0 |= X86_CR0_PG | X86_CR0_WP;
864 if (!vcpu->fpu_active) {
865 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
866 cr0 |= X86_CR0_TS;
867 }
868 set:
869 /*
870 * re-enable caching here because the QEMU bios
871 * does not do it - this results in some delay at
872 * reboot
873 */
874 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
875 svm->vmcb->save.cr0 = cr0;
876 }
877
878 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
879 {
880 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
881 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
882
883 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
884 force_new_asid(vcpu);
885
886 vcpu->arch.cr4 = cr4;
887 if (!npt_enabled)
888 cr4 |= X86_CR4_PAE;
889 cr4 |= host_cr4_mce;
890 to_svm(vcpu)->vmcb->save.cr4 = cr4;
891 }
892
893 static void svm_set_segment(struct kvm_vcpu *vcpu,
894 struct kvm_segment *var, int seg)
895 {
896 struct vcpu_svm *svm = to_svm(vcpu);
897 struct vmcb_seg *s = svm_seg(vcpu, seg);
898
899 s->base = var->base;
900 s->limit = var->limit;
901 s->selector = var->selector;
902 if (var->unusable)
903 s->attrib = 0;
904 else {
905 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
906 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
907 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
908 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
909 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
910 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
911 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
912 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
913 }
914 if (seg == VCPU_SREG_CS)
915 svm->vmcb->save.cpl
916 = (svm->vmcb->save.cs.attrib
917 >> SVM_SELECTOR_DPL_SHIFT) & 3;
918
919 }
920
921 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
922 {
923 return -EOPNOTSUPP;
924 }
925
926 static int svm_get_irq(struct kvm_vcpu *vcpu)
927 {
928 struct vcpu_svm *svm = to_svm(vcpu);
929 u32 exit_int_info = svm->vmcb->control.exit_int_info;
930
931 if (is_external_interrupt(exit_int_info))
932 return exit_int_info & SVM_EVTINJ_VEC_MASK;
933 return -1;
934 }
935
936 static void load_host_msrs(struct kvm_vcpu *vcpu)
937 {
938 #ifdef CONFIG_X86_64
939 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
940 #endif
941 }
942
943 static void save_host_msrs(struct kvm_vcpu *vcpu)
944 {
945 #ifdef CONFIG_X86_64
946 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
947 #endif
948 }
949
950 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
951 {
952 if (svm_data->next_asid > svm_data->max_asid) {
953 ++svm_data->asid_generation;
954 svm_data->next_asid = 1;
955 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
956 }
957
958 svm->vcpu.cpu = svm_data->cpu;
959 svm->asid_generation = svm_data->asid_generation;
960 svm->vmcb->control.asid = svm_data->next_asid++;
961 }
962
963 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
964 {
965 unsigned long val = to_svm(vcpu)->db_regs[dr];
966 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
967 return val;
968 }
969
970 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
971 int *exception)
972 {
973 struct vcpu_svm *svm = to_svm(vcpu);
974
975 *exception = 0;
976
977 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
978 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
979 svm->vmcb->save.dr6 |= DR6_BD_MASK;
980 *exception = DB_VECTOR;
981 return;
982 }
983
984 switch (dr) {
985 case 0 ... 3:
986 svm->db_regs[dr] = value;
987 return;
988 case 4 ... 5:
989 if (vcpu->arch.cr4 & X86_CR4_DE) {
990 *exception = UD_VECTOR;
991 return;
992 }
993 case 7: {
994 if (value & ~((1ULL << 32) - 1)) {
995 *exception = GP_VECTOR;
996 return;
997 }
998 svm->vmcb->save.dr7 = value;
999 return;
1000 }
1001 default:
1002 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1003 __func__, dr);
1004 *exception = UD_VECTOR;
1005 return;
1006 }
1007 }
1008
1009 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1010 {
1011 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1012 struct kvm *kvm = svm->vcpu.kvm;
1013 u64 fault_address;
1014 u32 error_code;
1015 bool event_injection = false;
1016
1017 if (!irqchip_in_kernel(kvm) &&
1018 is_external_interrupt(exit_int_info)) {
1019 event_injection = true;
1020 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1021 }
1022
1023 fault_address = svm->vmcb->control.exit_info_2;
1024 error_code = svm->vmcb->control.exit_info_1;
1025
1026 if (!npt_enabled)
1027 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1028 (u32)fault_address, (u32)(fault_address >> 32),
1029 handler);
1030 else
1031 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1032 (u32)fault_address, (u32)(fault_address >> 32),
1033 handler);
1034 /*
1035 * FIXME: Tis shouldn't be necessary here, but there is a flush
1036 * missing in the MMU code. Until we find this bug, flush the
1037 * complete TLB here on an NPF
1038 */
1039 if (npt_enabled)
1040 svm_flush_tlb(&svm->vcpu);
1041
1042 if (!npt_enabled && event_injection)
1043 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1044 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1045 }
1046
1047 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1048 {
1049 int er;
1050
1051 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1052 if (er != EMULATE_DONE)
1053 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1054 return 1;
1055 }
1056
1057 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1060 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1061 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1062 svm->vcpu.fpu_active = 1;
1063
1064 return 1;
1065 }
1066
1067 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1068 {
1069 /*
1070 * On an #MC intercept the MCE handler is not called automatically in
1071 * the host. So do it by hand here.
1072 */
1073 asm volatile (
1074 "int $0x12\n");
1075 /* not sure if we ever come back to this point */
1076
1077 return 1;
1078 }
1079
1080 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082 /*
1083 * VMCB is undefined after a SHUTDOWN intercept
1084 * so reinitialize it.
1085 */
1086 clear_page(svm->vmcb);
1087 init_vmcb(svm);
1088
1089 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1090 return 0;
1091 }
1092
1093 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1094 {
1095 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1096 int size, down, in, string, rep;
1097 unsigned port;
1098
1099 ++svm->vcpu.stat.io_exits;
1100
1101 svm->next_rip = svm->vmcb->control.exit_info_2;
1102
1103 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1104
1105 if (string) {
1106 if (emulate_instruction(&svm->vcpu,
1107 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1108 return 0;
1109 return 1;
1110 }
1111
1112 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1113 port = io_info >> 16;
1114 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1115 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1116 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1117
1118 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1119 }
1120
1121 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1122 {
1123 KVMTRACE_0D(NMI, &svm->vcpu, handler);
1124 return 1;
1125 }
1126
1127 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128 {
1129 ++svm->vcpu.stat.irq_exits;
1130 KVMTRACE_0D(INTR, &svm->vcpu, handler);
1131 return 1;
1132 }
1133
1134 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1135 {
1136 return 1;
1137 }
1138
1139 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1140 {
1141 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1142 skip_emulated_instruction(&svm->vcpu);
1143 return kvm_emulate_halt(&svm->vcpu);
1144 }
1145
1146 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1147 {
1148 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1149 skip_emulated_instruction(&svm->vcpu);
1150 kvm_emulate_hypercall(&svm->vcpu);
1151 return 1;
1152 }
1153
1154 static int invalid_op_interception(struct vcpu_svm *svm,
1155 struct kvm_run *kvm_run)
1156 {
1157 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1158 return 1;
1159 }
1160
1161 static int task_switch_interception(struct vcpu_svm *svm,
1162 struct kvm_run *kvm_run)
1163 {
1164 u16 tss_selector;
1165
1166 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1167 if (svm->vmcb->control.exit_info_2 &
1168 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1169 return kvm_task_switch(&svm->vcpu, tss_selector,
1170 TASK_SWITCH_IRET);
1171 if (svm->vmcb->control.exit_info_2 &
1172 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1173 return kvm_task_switch(&svm->vcpu, tss_selector,
1174 TASK_SWITCH_JMP);
1175 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1176 }
1177
1178 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1179 {
1180 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1181 kvm_emulate_cpuid(&svm->vcpu);
1182 return 1;
1183 }
1184
1185 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1186 {
1187 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1188 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1189 return 1;
1190 }
1191
1192 static int emulate_on_interception(struct vcpu_svm *svm,
1193 struct kvm_run *kvm_run)
1194 {
1195 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1196 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1197 return 1;
1198 }
1199
1200 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1201 {
1202 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1203 if (irqchip_in_kernel(svm->vcpu.kvm))
1204 return 1;
1205 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1206 return 0;
1207 }
1208
1209 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1210 {
1211 struct vcpu_svm *svm = to_svm(vcpu);
1212
1213 switch (ecx) {
1214 case MSR_IA32_TIME_STAMP_COUNTER: {
1215 u64 tsc;
1216
1217 rdtscll(tsc);
1218 *data = svm->vmcb->control.tsc_offset + tsc;
1219 break;
1220 }
1221 case MSR_K6_STAR:
1222 *data = svm->vmcb->save.star;
1223 break;
1224 #ifdef CONFIG_X86_64
1225 case MSR_LSTAR:
1226 *data = svm->vmcb->save.lstar;
1227 break;
1228 case MSR_CSTAR:
1229 *data = svm->vmcb->save.cstar;
1230 break;
1231 case MSR_KERNEL_GS_BASE:
1232 *data = svm->vmcb->save.kernel_gs_base;
1233 break;
1234 case MSR_SYSCALL_MASK:
1235 *data = svm->vmcb->save.sfmask;
1236 break;
1237 #endif
1238 case MSR_IA32_SYSENTER_CS:
1239 *data = svm->vmcb->save.sysenter_cs;
1240 break;
1241 case MSR_IA32_SYSENTER_EIP:
1242 *data = svm->vmcb->save.sysenter_eip;
1243 break;
1244 case MSR_IA32_SYSENTER_ESP:
1245 *data = svm->vmcb->save.sysenter_esp;
1246 break;
1247 /* Nobody will change the following 5 values in the VMCB so
1248 we can safely return them on rdmsr. They will always be 0
1249 until LBRV is implemented. */
1250 case MSR_IA32_DEBUGCTLMSR:
1251 *data = svm->vmcb->save.dbgctl;
1252 break;
1253 case MSR_IA32_LASTBRANCHFROMIP:
1254 *data = svm->vmcb->save.br_from;
1255 break;
1256 case MSR_IA32_LASTBRANCHTOIP:
1257 *data = svm->vmcb->save.br_to;
1258 break;
1259 case MSR_IA32_LASTINTFROMIP:
1260 *data = svm->vmcb->save.last_excp_from;
1261 break;
1262 case MSR_IA32_LASTINTTOIP:
1263 *data = svm->vmcb->save.last_excp_to;
1264 break;
1265 default:
1266 return kvm_get_msr_common(vcpu, ecx, data);
1267 }
1268 return 0;
1269 }
1270
1271 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1272 {
1273 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1274 u64 data;
1275
1276 if (svm_get_msr(&svm->vcpu, ecx, &data))
1277 kvm_inject_gp(&svm->vcpu, 0);
1278 else {
1279 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1280 (u32)(data >> 32), handler);
1281
1282 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1283 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1284 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1285 skip_emulated_instruction(&svm->vcpu);
1286 }
1287 return 1;
1288 }
1289
1290 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1291 {
1292 struct vcpu_svm *svm = to_svm(vcpu);
1293
1294 switch (ecx) {
1295 case MSR_IA32_TIME_STAMP_COUNTER: {
1296 u64 tsc;
1297
1298 rdtscll(tsc);
1299 svm->vmcb->control.tsc_offset = data - tsc;
1300 break;
1301 }
1302 case MSR_K6_STAR:
1303 svm->vmcb->save.star = data;
1304 break;
1305 #ifdef CONFIG_X86_64
1306 case MSR_LSTAR:
1307 svm->vmcb->save.lstar = data;
1308 break;
1309 case MSR_CSTAR:
1310 svm->vmcb->save.cstar = data;
1311 break;
1312 case MSR_KERNEL_GS_BASE:
1313 svm->vmcb->save.kernel_gs_base = data;
1314 break;
1315 case MSR_SYSCALL_MASK:
1316 svm->vmcb->save.sfmask = data;
1317 break;
1318 #endif
1319 case MSR_IA32_SYSENTER_CS:
1320 svm->vmcb->save.sysenter_cs = data;
1321 break;
1322 case MSR_IA32_SYSENTER_EIP:
1323 svm->vmcb->save.sysenter_eip = data;
1324 break;
1325 case MSR_IA32_SYSENTER_ESP:
1326 svm->vmcb->save.sysenter_esp = data;
1327 break;
1328 case MSR_IA32_DEBUGCTLMSR:
1329 if (!svm_has(SVM_FEATURE_LBRV)) {
1330 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1331 __func__, data);
1332 break;
1333 }
1334 if (data & DEBUGCTL_RESERVED_BITS)
1335 return 1;
1336
1337 svm->vmcb->save.dbgctl = data;
1338 if (data & (1ULL<<0))
1339 svm_enable_lbrv(svm);
1340 else
1341 svm_disable_lbrv(svm);
1342 break;
1343 case MSR_K7_EVNTSEL0:
1344 case MSR_K7_EVNTSEL1:
1345 case MSR_K7_EVNTSEL2:
1346 case MSR_K7_EVNTSEL3:
1347 case MSR_K7_PERFCTR0:
1348 case MSR_K7_PERFCTR1:
1349 case MSR_K7_PERFCTR2:
1350 case MSR_K7_PERFCTR3:
1351 /*
1352 * Just discard all writes to the performance counters; this
1353 * should keep both older linux and windows 64-bit guests
1354 * happy
1355 */
1356 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1357
1358 break;
1359 default:
1360 return kvm_set_msr_common(vcpu, ecx, data);
1361 }
1362 return 0;
1363 }
1364
1365 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1366 {
1367 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1368 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1369 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1370
1371 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1372 handler);
1373
1374 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1375 if (svm_set_msr(&svm->vcpu, ecx, data))
1376 kvm_inject_gp(&svm->vcpu, 0);
1377 else
1378 skip_emulated_instruction(&svm->vcpu);
1379 return 1;
1380 }
1381
1382 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1383 {
1384 if (svm->vmcb->control.exit_info_1)
1385 return wrmsr_interception(svm, kvm_run);
1386 else
1387 return rdmsr_interception(svm, kvm_run);
1388 }
1389
1390 static int interrupt_window_interception(struct vcpu_svm *svm,
1391 struct kvm_run *kvm_run)
1392 {
1393 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1394
1395 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1396 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1397 /*
1398 * If the user space waits to inject interrupts, exit as soon as
1399 * possible
1400 */
1401 if (kvm_run->request_interrupt_window &&
1402 !svm->vcpu.arch.irq_summary) {
1403 ++svm->vcpu.stat.irq_window_exits;
1404 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1405 return 0;
1406 }
1407
1408 return 1;
1409 }
1410
1411 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1412 struct kvm_run *kvm_run) = {
1413 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1414 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1415 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1416 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1417 /* for now: */
1418 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1419 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1420 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1421 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1422 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1423 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1424 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1425 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1426 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1427 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1428 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1429 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1430 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1431 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1432 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1433 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1434 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1435 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
1436 [SVM_EXIT_INTR] = intr_interception,
1437 [SVM_EXIT_NMI] = nmi_interception,
1438 [SVM_EXIT_SMI] = nop_on_interception,
1439 [SVM_EXIT_INIT] = nop_on_interception,
1440 [SVM_EXIT_VINTR] = interrupt_window_interception,
1441 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1442 [SVM_EXIT_CPUID] = cpuid_interception,
1443 [SVM_EXIT_INVD] = emulate_on_interception,
1444 [SVM_EXIT_HLT] = halt_interception,
1445 [SVM_EXIT_INVLPG] = invlpg_interception,
1446 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1447 [SVM_EXIT_IOIO] = io_interception,
1448 [SVM_EXIT_MSR] = msr_interception,
1449 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1450 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1451 [SVM_EXIT_VMRUN] = invalid_op_interception,
1452 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1453 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1454 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1455 [SVM_EXIT_STGI] = invalid_op_interception,
1456 [SVM_EXIT_CLGI] = invalid_op_interception,
1457 [SVM_EXIT_SKINIT] = invalid_op_interception,
1458 [SVM_EXIT_WBINVD] = emulate_on_interception,
1459 [SVM_EXIT_MONITOR] = invalid_op_interception,
1460 [SVM_EXIT_MWAIT] = invalid_op_interception,
1461 [SVM_EXIT_NPF] = pf_interception,
1462 };
1463
1464 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1465 {
1466 struct vcpu_svm *svm = to_svm(vcpu);
1467 u32 exit_code = svm->vmcb->control.exit_code;
1468
1469 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1470 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1471
1472 if (npt_enabled) {
1473 int mmu_reload = 0;
1474 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1475 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1476 mmu_reload = 1;
1477 }
1478 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1479 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1480 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1481 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1482 kvm_inject_gp(vcpu, 0);
1483 return 1;
1484 }
1485 }
1486 if (mmu_reload) {
1487 kvm_mmu_reset_context(vcpu);
1488 kvm_mmu_load(vcpu);
1489 }
1490 }
1491
1492 kvm_reput_irq(svm);
1493
1494 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1495 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1496 kvm_run->fail_entry.hardware_entry_failure_reason
1497 = svm->vmcb->control.exit_code;
1498 return 0;
1499 }
1500
1501 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1502 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1503 exit_code != SVM_EXIT_NPF)
1504 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1505 "exit_code 0x%x\n",
1506 __func__, svm->vmcb->control.exit_int_info,
1507 exit_code);
1508
1509 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1510 || !svm_exit_handlers[exit_code]) {
1511 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1512 kvm_run->hw.hardware_exit_reason = exit_code;
1513 return 0;
1514 }
1515
1516 return svm_exit_handlers[exit_code](svm, kvm_run);
1517 }
1518
1519 static void reload_tss(struct kvm_vcpu *vcpu)
1520 {
1521 int cpu = raw_smp_processor_id();
1522
1523 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1524 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1525 load_TR_desc();
1526 }
1527
1528 static void pre_svm_run(struct vcpu_svm *svm)
1529 {
1530 int cpu = raw_smp_processor_id();
1531
1532 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1533
1534 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1535 if (svm->vcpu.cpu != cpu ||
1536 svm->asid_generation != svm_data->asid_generation)
1537 new_asid(svm, svm_data);
1538 }
1539
1540
1541 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1542 {
1543 struct vmcb_control_area *control;
1544
1545 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1546
1547 ++svm->vcpu.stat.irq_injections;
1548 control = &svm->vmcb->control;
1549 control->int_vector = irq;
1550 control->int_ctl &= ~V_INTR_PRIO_MASK;
1551 control->int_ctl |= V_IRQ_MASK |
1552 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1553 }
1554
1555 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1556 {
1557 struct vcpu_svm *svm = to_svm(vcpu);
1558
1559 svm_inject_irq(svm, irq);
1560 }
1561
1562 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1563 {
1564 struct vcpu_svm *svm = to_svm(vcpu);
1565 struct vmcb *vmcb = svm->vmcb;
1566 int max_irr, tpr;
1567
1568 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1569 return;
1570
1571 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1572
1573 max_irr = kvm_lapic_find_highest_irr(vcpu);
1574 if (max_irr == -1)
1575 return;
1576
1577 tpr = kvm_lapic_get_cr8(vcpu) << 4;
1578
1579 if (tpr >= (max_irr & 0xf0))
1580 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1581 }
1582
1583 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1584 {
1585 struct vcpu_svm *svm = to_svm(vcpu);
1586 struct vmcb *vmcb = svm->vmcb;
1587 int intr_vector = -1;
1588
1589 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1590 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1591 intr_vector = vmcb->control.exit_int_info &
1592 SVM_EVTINJ_VEC_MASK;
1593 vmcb->control.exit_int_info = 0;
1594 svm_inject_irq(svm, intr_vector);
1595 goto out;
1596 }
1597
1598 if (vmcb->control.int_ctl & V_IRQ_MASK)
1599 goto out;
1600
1601 if (!kvm_cpu_has_interrupt(vcpu))
1602 goto out;
1603
1604 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1605 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1606 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1607 /* unable to deliver irq, set pending irq */
1608 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1609 svm_inject_irq(svm, 0x0);
1610 goto out;
1611 }
1612 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1613 intr_vector = kvm_cpu_get_interrupt(vcpu);
1614 svm_inject_irq(svm, intr_vector);
1615 kvm_timer_intr_post(vcpu, intr_vector);
1616 out:
1617 update_cr8_intercept(vcpu);
1618 }
1619
1620 static void kvm_reput_irq(struct vcpu_svm *svm)
1621 {
1622 struct vmcb_control_area *control = &svm->vmcb->control;
1623
1624 if ((control->int_ctl & V_IRQ_MASK)
1625 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1626 control->int_ctl &= ~V_IRQ_MASK;
1627 push_irq(&svm->vcpu, control->int_vector);
1628 }
1629
1630 svm->vcpu.arch.interrupt_window_open =
1631 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1632 }
1633
1634 static void svm_do_inject_vector(struct vcpu_svm *svm)
1635 {
1636 struct kvm_vcpu *vcpu = &svm->vcpu;
1637 int word_index = __ffs(vcpu->arch.irq_summary);
1638 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1639 int irq = word_index * BITS_PER_LONG + bit_index;
1640
1641 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1642 if (!vcpu->arch.irq_pending[word_index])
1643 clear_bit(word_index, &vcpu->arch.irq_summary);
1644 svm_inject_irq(svm, irq);
1645 }
1646
1647 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1648 struct kvm_run *kvm_run)
1649 {
1650 struct vcpu_svm *svm = to_svm(vcpu);
1651 struct vmcb_control_area *control = &svm->vmcb->control;
1652
1653 svm->vcpu.arch.interrupt_window_open =
1654 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1655 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1656
1657 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1658 /*
1659 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1660 */
1661 svm_do_inject_vector(svm);
1662
1663 /*
1664 * Interrupts blocked. Wait for unblock.
1665 */
1666 if (!svm->vcpu.arch.interrupt_window_open &&
1667 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1668 control->intercept |= 1ULL << INTERCEPT_VINTR;
1669 else
1670 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1671 }
1672
1673 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1674 {
1675 return 0;
1676 }
1677
1678 static void save_db_regs(unsigned long *db_regs)
1679 {
1680 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1681 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1682 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1683 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1684 }
1685
1686 static void load_db_regs(unsigned long *db_regs)
1687 {
1688 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1689 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1690 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1691 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1692 }
1693
1694 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1695 {
1696 force_new_asid(vcpu);
1697 }
1698
1699 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1700 {
1701 }
1702
1703 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1704 {
1705 struct vcpu_svm *svm = to_svm(vcpu);
1706
1707 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1708 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1709 kvm_lapic_set_tpr(vcpu, cr8);
1710 }
1711 }
1712
1713 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1714 {
1715 struct vcpu_svm *svm = to_svm(vcpu);
1716 u64 cr8;
1717
1718 if (!irqchip_in_kernel(vcpu->kvm))
1719 return;
1720
1721 cr8 = kvm_get_cr8(vcpu);
1722 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1723 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1724 }
1725
1726 #ifdef CONFIG_X86_64
1727 #define R "r"
1728 #else
1729 #define R "e"
1730 #endif
1731
1732 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1733 {
1734 struct vcpu_svm *svm = to_svm(vcpu);
1735 u16 fs_selector;
1736 u16 gs_selector;
1737 u16 ldt_selector;
1738
1739 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1740 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1741 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1742
1743 pre_svm_run(svm);
1744
1745 sync_lapic_to_cr8(vcpu);
1746
1747 save_host_msrs(vcpu);
1748 fs_selector = kvm_read_fs();
1749 gs_selector = kvm_read_gs();
1750 ldt_selector = kvm_read_ldt();
1751 svm->host_cr2 = kvm_read_cr2();
1752 svm->host_dr6 = read_dr6();
1753 svm->host_dr7 = read_dr7();
1754 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1755 /* required for live migration with NPT */
1756 if (npt_enabled)
1757 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1758
1759 if (svm->vmcb->save.dr7 & 0xff) {
1760 write_dr7(0);
1761 save_db_regs(svm->host_db_regs);
1762 load_db_regs(svm->db_regs);
1763 }
1764
1765 clgi();
1766
1767 local_irq_enable();
1768
1769 asm volatile (
1770 "push %%"R"bp; \n\t"
1771 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1772 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1773 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1774 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1775 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1776 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1777 #ifdef CONFIG_X86_64
1778 "mov %c[r8](%[svm]), %%r8 \n\t"
1779 "mov %c[r9](%[svm]), %%r9 \n\t"
1780 "mov %c[r10](%[svm]), %%r10 \n\t"
1781 "mov %c[r11](%[svm]), %%r11 \n\t"
1782 "mov %c[r12](%[svm]), %%r12 \n\t"
1783 "mov %c[r13](%[svm]), %%r13 \n\t"
1784 "mov %c[r14](%[svm]), %%r14 \n\t"
1785 "mov %c[r15](%[svm]), %%r15 \n\t"
1786 #endif
1787
1788 /* Enter guest mode */
1789 "push %%"R"ax \n\t"
1790 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1791 __ex(SVM_VMLOAD) "\n\t"
1792 __ex(SVM_VMRUN) "\n\t"
1793 __ex(SVM_VMSAVE) "\n\t"
1794 "pop %%"R"ax \n\t"
1795
1796 /* Save guest registers, load host registers */
1797 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1798 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1799 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1800 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1801 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1802 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1803 #ifdef CONFIG_X86_64
1804 "mov %%r8, %c[r8](%[svm]) \n\t"
1805 "mov %%r9, %c[r9](%[svm]) \n\t"
1806 "mov %%r10, %c[r10](%[svm]) \n\t"
1807 "mov %%r11, %c[r11](%[svm]) \n\t"
1808 "mov %%r12, %c[r12](%[svm]) \n\t"
1809 "mov %%r13, %c[r13](%[svm]) \n\t"
1810 "mov %%r14, %c[r14](%[svm]) \n\t"
1811 "mov %%r15, %c[r15](%[svm]) \n\t"
1812 #endif
1813 "pop %%"R"bp"
1814 :
1815 : [svm]"a"(svm),
1816 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1817 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1818 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1819 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1820 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1821 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1822 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1823 #ifdef CONFIG_X86_64
1824 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1825 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1826 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1827 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1828 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1829 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1830 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1831 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1832 #endif
1833 : "cc", "memory"
1834 , R"bx", R"cx", R"dx", R"si", R"di"
1835 #ifdef CONFIG_X86_64
1836 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1837 #endif
1838 );
1839
1840 if ((svm->vmcb->save.dr7 & 0xff))
1841 load_db_regs(svm->host_db_regs);
1842
1843 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1844 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1845 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1846 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1847
1848 write_dr6(svm->host_dr6);
1849 write_dr7(svm->host_dr7);
1850 kvm_write_cr2(svm->host_cr2);
1851
1852 kvm_load_fs(fs_selector);
1853 kvm_load_gs(gs_selector);
1854 kvm_load_ldt(ldt_selector);
1855 load_host_msrs(vcpu);
1856
1857 reload_tss(vcpu);
1858
1859 local_irq_disable();
1860
1861 stgi();
1862
1863 sync_cr8_to_lapic(vcpu);
1864
1865 svm->next_rip = 0;
1866 }
1867
1868 #undef R
1869
1870 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1871 {
1872 struct vcpu_svm *svm = to_svm(vcpu);
1873
1874 if (npt_enabled) {
1875 svm->vmcb->control.nested_cr3 = root;
1876 force_new_asid(vcpu);
1877 return;
1878 }
1879
1880 svm->vmcb->save.cr3 = root;
1881 force_new_asid(vcpu);
1882
1883 if (vcpu->fpu_active) {
1884 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1885 svm->vmcb->save.cr0 |= X86_CR0_TS;
1886 vcpu->fpu_active = 0;
1887 }
1888 }
1889
1890 static int is_disabled(void)
1891 {
1892 u64 vm_cr;
1893
1894 rdmsrl(MSR_VM_CR, vm_cr);
1895 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1896 return 1;
1897
1898 return 0;
1899 }
1900
1901 static void
1902 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1903 {
1904 /*
1905 * Patch in the VMMCALL instruction:
1906 */
1907 hypercall[0] = 0x0f;
1908 hypercall[1] = 0x01;
1909 hypercall[2] = 0xd9;
1910 }
1911
1912 static void svm_check_processor_compat(void *rtn)
1913 {
1914 *(int *)rtn = 0;
1915 }
1916
1917 static bool svm_cpu_has_accelerated_tpr(void)
1918 {
1919 return false;
1920 }
1921
1922 static int get_npt_level(void)
1923 {
1924 #ifdef CONFIG_X86_64
1925 return PT64_ROOT_LEVEL;
1926 #else
1927 return PT32E_ROOT_LEVEL;
1928 #endif
1929 }
1930
1931 static int svm_get_mt_mask_shift(void)
1932 {
1933 return 0;
1934 }
1935
1936 static struct kvm_x86_ops svm_x86_ops = {
1937 .cpu_has_kvm_support = has_svm,
1938 .disabled_by_bios = is_disabled,
1939 .hardware_setup = svm_hardware_setup,
1940 .hardware_unsetup = svm_hardware_unsetup,
1941 .check_processor_compatibility = svm_check_processor_compat,
1942 .hardware_enable = svm_hardware_enable,
1943 .hardware_disable = svm_hardware_disable,
1944 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1945
1946 .vcpu_create = svm_create_vcpu,
1947 .vcpu_free = svm_free_vcpu,
1948 .vcpu_reset = svm_vcpu_reset,
1949
1950 .prepare_guest_switch = svm_prepare_guest_switch,
1951 .vcpu_load = svm_vcpu_load,
1952 .vcpu_put = svm_vcpu_put,
1953
1954 .set_guest_debug = svm_guest_debug,
1955 .get_msr = svm_get_msr,
1956 .set_msr = svm_set_msr,
1957 .get_segment_base = svm_get_segment_base,
1958 .get_segment = svm_get_segment,
1959 .set_segment = svm_set_segment,
1960 .get_cpl = svm_get_cpl,
1961 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1962 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1963 .set_cr0 = svm_set_cr0,
1964 .set_cr3 = svm_set_cr3,
1965 .set_cr4 = svm_set_cr4,
1966 .set_efer = svm_set_efer,
1967 .get_idt = svm_get_idt,
1968 .set_idt = svm_set_idt,
1969 .get_gdt = svm_get_gdt,
1970 .set_gdt = svm_set_gdt,
1971 .get_dr = svm_get_dr,
1972 .set_dr = svm_set_dr,
1973 .get_rflags = svm_get_rflags,
1974 .set_rflags = svm_set_rflags,
1975
1976 .tlb_flush = svm_flush_tlb,
1977
1978 .run = svm_vcpu_run,
1979 .handle_exit = handle_exit,
1980 .skip_emulated_instruction = skip_emulated_instruction,
1981 .patch_hypercall = svm_patch_hypercall,
1982 .get_irq = svm_get_irq,
1983 .set_irq = svm_set_irq,
1984 .queue_exception = svm_queue_exception,
1985 .exception_injected = svm_exception_injected,
1986 .inject_pending_irq = svm_intr_assist,
1987 .inject_pending_vectors = do_interrupt_requests,
1988
1989 .set_tss_addr = svm_set_tss_addr,
1990 .get_tdp_level = get_npt_level,
1991 .get_mt_mask_shift = svm_get_mt_mask_shift,
1992 };
1993
1994 static int __init svm_init(void)
1995 {
1996 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1997 THIS_MODULE);
1998 }
1999
2000 static void __exit svm_exit(void)
2001 {
2002 kvm_exit();
2003 }
2004
2005 module_init(svm_init)
2006 module_exit(svm_exit)
Linux kernel - Deliverables
This page took 0.072713 seconds and 6 git commands to generate.