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Merge tag 'edac/v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24 #include "pmu.h"
25
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
37 #include <asm/desc.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
40
41 #include <asm/virtext.h>
42 #include "trace.h"
43
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
48
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
51 {}
52 };
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
57
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
60
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
80
81 static bool erratum_383_found __read_mostly;
82
83 static const u32 host_save_user_msrs[] = {
84 #ifdef CONFIG_X86_64
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
86 MSR_FS_BASE,
87 #endif
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
89 };
90
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
92
93 struct kvm_vcpu;
94
95 struct nested_state {
96 struct vmcb *hsave;
97 u64 hsave_msr;
98 u64 vm_cr_msr;
99 u64 vmcb;
100
101 /* These are the merged vectors */
102 u32 *msrpm;
103
104 /* gpa pointers to the real vectors */
105 u64 vmcb_msrpm;
106 u64 vmcb_iopm;
107
108 /* A VMEXIT is required but not yet emulated */
109 bool exit_required;
110
111 /* cache for intercepts of the guest */
112 u32 intercept_cr;
113 u32 intercept_dr;
114 u32 intercept_exceptions;
115 u64 intercept;
116
117 /* Nested Paging related state */
118 u64 nested_cr3;
119 };
120
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
123
124 /*
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
127 */
128 static uint64_t osvw_len = 4, osvw_status;
129
130 struct vcpu_svm {
131 struct kvm_vcpu vcpu;
132 struct vmcb *vmcb;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
138
139 u64 next_rip;
140
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
142 struct {
143 u16 fs;
144 u16 gs;
145 u16 ldt;
146 u64 gs_base;
147 } host;
148
149 u32 *msrpm;
150
151 ulong nmi_iret_rip;
152
153 struct nested_state nested;
154
155 bool nmi_singlestep;
156
157 unsigned int3_injected;
158 unsigned long int3_rip;
159 u32 apf_reason;
160
161 u64 tsc_ratio;
162 };
163
164 static DEFINE_PER_CPU(u64, current_tsc_ratio);
165 #define TSC_RATIO_DEFAULT 0x0100000000ULL
166
167 #define MSR_INVALID 0xffffffffU
168
169 static const struct svm_direct_access_msrs {
170 u32 index; /* Index of the MSR */
171 bool always; /* True if intercept is always on */
172 } direct_access_msrs[] = {
173 { .index = MSR_STAR, .always = true },
174 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175 #ifdef CONFIG_X86_64
176 { .index = MSR_GS_BASE, .always = true },
177 { .index = MSR_FS_BASE, .always = true },
178 { .index = MSR_KERNEL_GS_BASE, .always = true },
179 { .index = MSR_LSTAR, .always = true },
180 { .index = MSR_CSTAR, .always = true },
181 { .index = MSR_SYSCALL_MASK, .always = true },
182 #endif
183 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
184 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
185 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
186 { .index = MSR_IA32_LASTINTTOIP, .always = false },
187 { .index = MSR_INVALID, .always = false },
188 };
189
190 /* enable NPT for AMD64 and X86 with PAE */
191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192 static bool npt_enabled = true;
193 #else
194 static bool npt_enabled;
195 #endif
196
197 /* allow nested paging (virtualized MMU) for all guests */
198 static int npt = true;
199 module_param(npt, int, S_IRUGO);
200
201 /* allow nested virtualization in KVM/SVM */
202 static int nested = true;
203 module_param(nested, int, S_IRUGO);
204
205 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
206 static void svm_complete_interrupts(struct vcpu_svm *svm);
207
208 static int nested_svm_exit_handled(struct vcpu_svm *svm);
209 static int nested_svm_intercept(struct vcpu_svm *svm);
210 static int nested_svm_vmexit(struct vcpu_svm *svm);
211 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
212 bool has_error_code, u32 error_code);
213 static u64 __scale_tsc(u64 ratio, u64 tsc);
214
215 enum {
216 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
217 pause filter count */
218 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
219 VMCB_ASID, /* ASID */
220 VMCB_INTR, /* int_ctl, int_vector */
221 VMCB_NPT, /* npt_en, nCR3, gPAT */
222 VMCB_CR, /* CR0, CR3, CR4, EFER */
223 VMCB_DR, /* DR6, DR7 */
224 VMCB_DT, /* GDT, IDT */
225 VMCB_SEG, /* CS, DS, SS, ES, CPL */
226 VMCB_CR2, /* CR2 only */
227 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
228 VMCB_DIRTY_MAX,
229 };
230
231 /* TPR and CR2 are always written before VMRUN */
232 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
233
234 static inline void mark_all_dirty(struct vmcb *vmcb)
235 {
236 vmcb->control.clean = 0;
237 }
238
239 static inline void mark_all_clean(struct vmcb *vmcb)
240 {
241 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
242 & ~VMCB_ALWAYS_DIRTY_MASK;
243 }
244
245 static inline void mark_dirty(struct vmcb *vmcb, int bit)
246 {
247 vmcb->control.clean &= ~(1 << bit);
248 }
249
250 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
251 {
252 return container_of(vcpu, struct vcpu_svm, vcpu);
253 }
254
255 static void recalc_intercepts(struct vcpu_svm *svm)
256 {
257 struct vmcb_control_area *c, *h;
258 struct nested_state *g;
259
260 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
261
262 if (!is_guest_mode(&svm->vcpu))
263 return;
264
265 c = &svm->vmcb->control;
266 h = &svm->nested.hsave->control;
267 g = &svm->nested;
268
269 c->intercept_cr = h->intercept_cr | g->intercept_cr;
270 c->intercept_dr = h->intercept_dr | g->intercept_dr;
271 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
272 c->intercept = h->intercept | g->intercept;
273 }
274
275 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
276 {
277 if (is_guest_mode(&svm->vcpu))
278 return svm->nested.hsave;
279 else
280 return svm->vmcb;
281 }
282
283 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
284 {
285 struct vmcb *vmcb = get_host_vmcb(svm);
286
287 vmcb->control.intercept_cr |= (1U << bit);
288
289 recalc_intercepts(svm);
290 }
291
292 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
293 {
294 struct vmcb *vmcb = get_host_vmcb(svm);
295
296 vmcb->control.intercept_cr &= ~(1U << bit);
297
298 recalc_intercepts(svm);
299 }
300
301 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
302 {
303 struct vmcb *vmcb = get_host_vmcb(svm);
304
305 return vmcb->control.intercept_cr & (1U << bit);
306 }
307
308 static inline void set_dr_intercepts(struct vcpu_svm *svm)
309 {
310 struct vmcb *vmcb = get_host_vmcb(svm);
311
312 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
313 | (1 << INTERCEPT_DR1_READ)
314 | (1 << INTERCEPT_DR2_READ)
315 | (1 << INTERCEPT_DR3_READ)
316 | (1 << INTERCEPT_DR4_READ)
317 | (1 << INTERCEPT_DR5_READ)
318 | (1 << INTERCEPT_DR6_READ)
319 | (1 << INTERCEPT_DR7_READ)
320 | (1 << INTERCEPT_DR0_WRITE)
321 | (1 << INTERCEPT_DR1_WRITE)
322 | (1 << INTERCEPT_DR2_WRITE)
323 | (1 << INTERCEPT_DR3_WRITE)
324 | (1 << INTERCEPT_DR4_WRITE)
325 | (1 << INTERCEPT_DR5_WRITE)
326 | (1 << INTERCEPT_DR6_WRITE)
327 | (1 << INTERCEPT_DR7_WRITE);
328
329 recalc_intercepts(svm);
330 }
331
332 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
333 {
334 struct vmcb *vmcb = get_host_vmcb(svm);
335
336 vmcb->control.intercept_dr = 0;
337
338 recalc_intercepts(svm);
339 }
340
341 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
342 {
343 struct vmcb *vmcb = get_host_vmcb(svm);
344
345 vmcb->control.intercept_exceptions |= (1U << bit);
346
347 recalc_intercepts(svm);
348 }
349
350 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
351 {
352 struct vmcb *vmcb = get_host_vmcb(svm);
353
354 vmcb->control.intercept_exceptions &= ~(1U << bit);
355
356 recalc_intercepts(svm);
357 }
358
359 static inline void set_intercept(struct vcpu_svm *svm, int bit)
360 {
361 struct vmcb *vmcb = get_host_vmcb(svm);
362
363 vmcb->control.intercept |= (1ULL << bit);
364
365 recalc_intercepts(svm);
366 }
367
368 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
369 {
370 struct vmcb *vmcb = get_host_vmcb(svm);
371
372 vmcb->control.intercept &= ~(1ULL << bit);
373
374 recalc_intercepts(svm);
375 }
376
377 static inline void enable_gif(struct vcpu_svm *svm)
378 {
379 svm->vcpu.arch.hflags |= HF_GIF_MASK;
380 }
381
382 static inline void disable_gif(struct vcpu_svm *svm)
383 {
384 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
385 }
386
387 static inline bool gif_set(struct vcpu_svm *svm)
388 {
389 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
390 }
391
392 static unsigned long iopm_base;
393
394 struct kvm_ldttss_desc {
395 u16 limit0;
396 u16 base0;
397 unsigned base1:8, type:5, dpl:2, p:1;
398 unsigned limit1:4, zero0:3, g:1, base2:8;
399 u32 base3;
400 u32 zero1;
401 } __attribute__((packed));
402
403 struct svm_cpu_data {
404 int cpu;
405
406 u64 asid_generation;
407 u32 max_asid;
408 u32 next_asid;
409 struct kvm_ldttss_desc *tss_desc;
410
411 struct page *save_area;
412 };
413
414 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
415
416 struct svm_init_data {
417 int cpu;
418 int r;
419 };
420
421 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
422
423 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
424 #define MSRS_RANGE_SIZE 2048
425 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
426
427 static u32 svm_msrpm_offset(u32 msr)
428 {
429 u32 offset;
430 int i;
431
432 for (i = 0; i < NUM_MSR_MAPS; i++) {
433 if (msr < msrpm_ranges[i] ||
434 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
435 continue;
436
437 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
438 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
439
440 /* Now we have the u8 offset - but need the u32 offset */
441 return offset / 4;
442 }
443
444 /* MSR not in any range */
445 return MSR_INVALID;
446 }
447
448 #define MAX_INST_SIZE 15
449
450 static inline void clgi(void)
451 {
452 asm volatile (__ex(SVM_CLGI));
453 }
454
455 static inline void stgi(void)
456 {
457 asm volatile (__ex(SVM_STGI));
458 }
459
460 static inline void invlpga(unsigned long addr, u32 asid)
461 {
462 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
463 }
464
465 static int get_npt_level(void)
466 {
467 #ifdef CONFIG_X86_64
468 return PT64_ROOT_LEVEL;
469 #else
470 return PT32E_ROOT_LEVEL;
471 #endif
472 }
473
474 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
475 {
476 vcpu->arch.efer = efer;
477 if (!npt_enabled && !(efer & EFER_LMA))
478 efer &= ~EFER_LME;
479
480 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
481 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
482 }
483
484 static int is_external_interrupt(u32 info)
485 {
486 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
487 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
488 }
489
490 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
491 {
492 struct vcpu_svm *svm = to_svm(vcpu);
493 u32 ret = 0;
494
495 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
496 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
497 return ret;
498 }
499
500 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
501 {
502 struct vcpu_svm *svm = to_svm(vcpu);
503
504 if (mask == 0)
505 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
506 else
507 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
508
509 }
510
511 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
512 {
513 struct vcpu_svm *svm = to_svm(vcpu);
514
515 if (svm->vmcb->control.next_rip != 0) {
516 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS));
517 svm->next_rip = svm->vmcb->control.next_rip;
518 }
519
520 if (!svm->next_rip) {
521 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
522 EMULATE_DONE)
523 printk(KERN_DEBUG "%s: NOP\n", __func__);
524 return;
525 }
526 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
527 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
528 __func__, kvm_rip_read(vcpu), svm->next_rip);
529
530 kvm_rip_write(vcpu, svm->next_rip);
531 svm_set_interrupt_shadow(vcpu, 0);
532 }
533
534 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
535 bool has_error_code, u32 error_code,
536 bool reinject)
537 {
538 struct vcpu_svm *svm = to_svm(vcpu);
539
540 /*
541 * If we are within a nested VM we'd better #VMEXIT and let the guest
542 * handle the exception
543 */
544 if (!reinject &&
545 nested_svm_check_exception(svm, nr, has_error_code, error_code))
546 return;
547
548 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
549 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
550
551 /*
552 * For guest debugging where we have to reinject #BP if some
553 * INT3 is guest-owned:
554 * Emulate nRIP by moving RIP forward. Will fail if injection
555 * raises a fault that is not intercepted. Still better than
556 * failing in all cases.
557 */
558 skip_emulated_instruction(&svm->vcpu);
559 rip = kvm_rip_read(&svm->vcpu);
560 svm->int3_rip = rip + svm->vmcb->save.cs.base;
561 svm->int3_injected = rip - old_rip;
562 }
563
564 svm->vmcb->control.event_inj = nr
565 | SVM_EVTINJ_VALID
566 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
567 | SVM_EVTINJ_TYPE_EXEPT;
568 svm->vmcb->control.event_inj_err = error_code;
569 }
570
571 static void svm_init_erratum_383(void)
572 {
573 u32 low, high;
574 int err;
575 u64 val;
576
577 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
578 return;
579
580 /* Use _safe variants to not break nested virtualization */
581 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
582 if (err)
583 return;
584
585 val |= (1ULL << 47);
586
587 low = lower_32_bits(val);
588 high = upper_32_bits(val);
589
590 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
591
592 erratum_383_found = true;
593 }
594
595 static void svm_init_osvw(struct kvm_vcpu *vcpu)
596 {
597 /*
598 * Guests should see errata 400 and 415 as fixed (assuming that
599 * HLT and IO instructions are intercepted).
600 */
601 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
602 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
603
604 /*
605 * By increasing VCPU's osvw.length to 3 we are telling the guest that
606 * all osvw.status bits inside that length, including bit 0 (which is
607 * reserved for erratum 298), are valid. However, if host processor's
608 * osvw_len is 0 then osvw_status[0] carries no information. We need to
609 * be conservative here and therefore we tell the guest that erratum 298
610 * is present (because we really don't know).
611 */
612 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
613 vcpu->arch.osvw.status |= 1;
614 }
615
616 static int has_svm(void)
617 {
618 const char *msg;
619
620 if (!cpu_has_svm(&msg)) {
621 printk(KERN_INFO "has_svm: %s\n", msg);
622 return 0;
623 }
624
625 return 1;
626 }
627
628 static void svm_hardware_disable(void)
629 {
630 /* Make sure we clean up behind us */
631 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
632 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
633
634 cpu_svm_disable();
635
636 amd_pmu_disable_virt();
637 }
638
639 static int svm_hardware_enable(void)
640 {
641
642 struct svm_cpu_data *sd;
643 uint64_t efer;
644 struct desc_ptr gdt_descr;
645 struct desc_struct *gdt;
646 int me = raw_smp_processor_id();
647
648 rdmsrl(MSR_EFER, efer);
649 if (efer & EFER_SVME)
650 return -EBUSY;
651
652 if (!has_svm()) {
653 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
654 return -EINVAL;
655 }
656 sd = per_cpu(svm_data, me);
657 if (!sd) {
658 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
659 return -EINVAL;
660 }
661
662 sd->asid_generation = 1;
663 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
664 sd->next_asid = sd->max_asid + 1;
665
666 native_store_gdt(&gdt_descr);
667 gdt = (struct desc_struct *)gdt_descr.address;
668 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
669
670 wrmsrl(MSR_EFER, efer | EFER_SVME);
671
672 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
673
674 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
675 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
676 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
677 }
678
679
680 /*
681 * Get OSVW bits.
682 *
683 * Note that it is possible to have a system with mixed processor
684 * revisions and therefore different OSVW bits. If bits are not the same
685 * on different processors then choose the worst case (i.e. if erratum
686 * is present on one processor and not on another then assume that the
687 * erratum is present everywhere).
688 */
689 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
690 uint64_t len, status = 0;
691 int err;
692
693 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
694 if (!err)
695 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
696 &err);
697
698 if (err)
699 osvw_status = osvw_len = 0;
700 else {
701 if (len < osvw_len)
702 osvw_len = len;
703 osvw_status |= status;
704 osvw_status &= (1ULL << osvw_len) - 1;
705 }
706 } else
707 osvw_status = osvw_len = 0;
708
709 svm_init_erratum_383();
710
711 amd_pmu_enable_virt();
712
713 return 0;
714 }
715
716 static void svm_cpu_uninit(int cpu)
717 {
718 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
719
720 if (!sd)
721 return;
722
723 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
724 __free_page(sd->save_area);
725 kfree(sd);
726 }
727
728 static int svm_cpu_init(int cpu)
729 {
730 struct svm_cpu_data *sd;
731 int r;
732
733 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
734 if (!sd)
735 return -ENOMEM;
736 sd->cpu = cpu;
737 sd->save_area = alloc_page(GFP_KERNEL);
738 r = -ENOMEM;
739 if (!sd->save_area)
740 goto err_1;
741
742 per_cpu(svm_data, cpu) = sd;
743
744 return 0;
745
746 err_1:
747 kfree(sd);
748 return r;
749
750 }
751
752 static bool valid_msr_intercept(u32 index)
753 {
754 int i;
755
756 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
757 if (direct_access_msrs[i].index == index)
758 return true;
759
760 return false;
761 }
762
763 static void set_msr_interception(u32 *msrpm, unsigned msr,
764 int read, int write)
765 {
766 u8 bit_read, bit_write;
767 unsigned long tmp;
768 u32 offset;
769
770 /*
771 * If this warning triggers extend the direct_access_msrs list at the
772 * beginning of the file
773 */
774 WARN_ON(!valid_msr_intercept(msr));
775
776 offset = svm_msrpm_offset(msr);
777 bit_read = 2 * (msr & 0x0f);
778 bit_write = 2 * (msr & 0x0f) + 1;
779 tmp = msrpm[offset];
780
781 BUG_ON(offset == MSR_INVALID);
782
783 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
784 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
785
786 msrpm[offset] = tmp;
787 }
788
789 static void svm_vcpu_init_msrpm(u32 *msrpm)
790 {
791 int i;
792
793 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
794
795 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
796 if (!direct_access_msrs[i].always)
797 continue;
798
799 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
800 }
801 }
802
803 static void add_msr_offset(u32 offset)
804 {
805 int i;
806
807 for (i = 0; i < MSRPM_OFFSETS; ++i) {
808
809 /* Offset already in list? */
810 if (msrpm_offsets[i] == offset)
811 return;
812
813 /* Slot used by another offset? */
814 if (msrpm_offsets[i] != MSR_INVALID)
815 continue;
816
817 /* Add offset to list */
818 msrpm_offsets[i] = offset;
819
820 return;
821 }
822
823 /*
824 * If this BUG triggers the msrpm_offsets table has an overflow. Just
825 * increase MSRPM_OFFSETS in this case.
826 */
827 BUG();
828 }
829
830 static void init_msrpm_offsets(void)
831 {
832 int i;
833
834 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
835
836 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
837 u32 offset;
838
839 offset = svm_msrpm_offset(direct_access_msrs[i].index);
840 BUG_ON(offset == MSR_INVALID);
841
842 add_msr_offset(offset);
843 }
844 }
845
846 static void svm_enable_lbrv(struct vcpu_svm *svm)
847 {
848 u32 *msrpm = svm->msrpm;
849
850 svm->vmcb->control.lbr_ctl = 1;
851 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
855 }
856
857 static void svm_disable_lbrv(struct vcpu_svm *svm)
858 {
859 u32 *msrpm = svm->msrpm;
860
861 svm->vmcb->control.lbr_ctl = 0;
862 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
866 }
867
868 #define MTRR_TYPE_UC_MINUS 7
869 #define MTRR2PROTVAL_INVALID 0xff
870
871 static u8 mtrr2protval[8];
872
873 static u8 fallback_mtrr_type(int mtrr)
874 {
875 /*
876 * WT and WP aren't always available in the host PAT. Treat
877 * them as UC and UC- respectively. Everything else should be
878 * there.
879 */
880 switch (mtrr)
881 {
882 case MTRR_TYPE_WRTHROUGH:
883 return MTRR_TYPE_UNCACHABLE;
884 case MTRR_TYPE_WRPROT:
885 return MTRR_TYPE_UC_MINUS;
886 default:
887 BUG();
888 }
889 }
890
891 static void build_mtrr2protval(void)
892 {
893 int i;
894 u64 pat;
895
896 for (i = 0; i < 8; i++)
897 mtrr2protval[i] = MTRR2PROTVAL_INVALID;
898
899 /* Ignore the invalid MTRR types. */
900 mtrr2protval[2] = 0;
901 mtrr2protval[3] = 0;
902
903 /*
904 * Use host PAT value to figure out the mapping from guest MTRR
905 * values to nested page table PAT/PCD/PWT values. We do not
906 * want to change the host PAT value every time we enter the
907 * guest.
908 */
909 rdmsrl(MSR_IA32_CR_PAT, pat);
910 for (i = 0; i < 8; i++) {
911 u8 mtrr = pat >> (8 * i);
912
913 if (mtrr2protval[mtrr] == MTRR2PROTVAL_INVALID)
914 mtrr2protval[mtrr] = __cm_idx2pte(i);
915 }
916
917 for (i = 0; i < 8; i++) {
918 if (mtrr2protval[i] == MTRR2PROTVAL_INVALID) {
919 u8 fallback = fallback_mtrr_type(i);
920 mtrr2protval[i] = mtrr2protval[fallback];
921 BUG_ON(mtrr2protval[i] == MTRR2PROTVAL_INVALID);
922 }
923 }
924 }
925
926 static __init int svm_hardware_setup(void)
927 {
928 int cpu;
929 struct page *iopm_pages;
930 void *iopm_va;
931 int r;
932
933 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
934
935 if (!iopm_pages)
936 return -ENOMEM;
937
938 iopm_va = page_address(iopm_pages);
939 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
940 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
941
942 init_msrpm_offsets();
943
944 if (boot_cpu_has(X86_FEATURE_NX))
945 kvm_enable_efer_bits(EFER_NX);
946
947 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
948 kvm_enable_efer_bits(EFER_FFXSR);
949
950 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
951 u64 max;
952
953 kvm_has_tsc_control = true;
954
955 /*
956 * Make sure the user can only configure tsc_khz values that
957 * fit into a signed integer.
958 * A min value is not calculated needed because it will always
959 * be 1 on all machines and a value of 0 is used to disable
960 * tsc-scaling for the vcpu.
961 */
962 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
963
964 kvm_max_guest_tsc_khz = max;
965 }
966
967 if (nested) {
968 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
969 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
970 }
971
972 for_each_possible_cpu(cpu) {
973 r = svm_cpu_init(cpu);
974 if (r)
975 goto err;
976 }
977
978 if (!boot_cpu_has(X86_FEATURE_NPT))
979 npt_enabled = false;
980
981 if (npt_enabled && !npt) {
982 printk(KERN_INFO "kvm: Nested Paging disabled\n");
983 npt_enabled = false;
984 }
985
986 if (npt_enabled) {
987 printk(KERN_INFO "kvm: Nested Paging enabled\n");
988 kvm_enable_tdp();
989 } else
990 kvm_disable_tdp();
991
992 build_mtrr2protval();
993 return 0;
994
995 err:
996 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
997 iopm_base = 0;
998 return r;
999 }
1000
1001 static __exit void svm_hardware_unsetup(void)
1002 {
1003 int cpu;
1004
1005 for_each_possible_cpu(cpu)
1006 svm_cpu_uninit(cpu);
1007
1008 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1009 iopm_base = 0;
1010 }
1011
1012 static void init_seg(struct vmcb_seg *seg)
1013 {
1014 seg->selector = 0;
1015 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1016 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1017 seg->limit = 0xffff;
1018 seg->base = 0;
1019 }
1020
1021 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1022 {
1023 seg->selector = 0;
1024 seg->attrib = SVM_SELECTOR_P_MASK | type;
1025 seg->limit = 0xffff;
1026 seg->base = 0;
1027 }
1028
1029 static u64 __scale_tsc(u64 ratio, u64 tsc)
1030 {
1031 u64 mult, frac, _tsc;
1032
1033 mult = ratio >> 32;
1034 frac = ratio & ((1ULL << 32) - 1);
1035
1036 _tsc = tsc;
1037 _tsc *= mult;
1038 _tsc += (tsc >> 32) * frac;
1039 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
1040
1041 return _tsc;
1042 }
1043
1044 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1045 {
1046 struct vcpu_svm *svm = to_svm(vcpu);
1047 u64 _tsc = tsc;
1048
1049 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1050 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
1051
1052 return _tsc;
1053 }
1054
1055 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1056 {
1057 struct vcpu_svm *svm = to_svm(vcpu);
1058 u64 ratio;
1059 u64 khz;
1060
1061 /* Guest TSC same frequency as host TSC? */
1062 if (!scale) {
1063 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1064 return;
1065 }
1066
1067 /* TSC scaling supported? */
1068 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1069 if (user_tsc_khz > tsc_khz) {
1070 vcpu->arch.tsc_catchup = 1;
1071 vcpu->arch.tsc_always_catchup = 1;
1072 } else
1073 WARN(1, "user requested TSC rate below hardware speed\n");
1074 return;
1075 }
1076
1077 khz = user_tsc_khz;
1078
1079 /* TSC scaling required - calculate ratio */
1080 ratio = khz << 32;
1081 do_div(ratio, tsc_khz);
1082
1083 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1084 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1085 user_tsc_khz);
1086 return;
1087 }
1088 svm->tsc_ratio = ratio;
1089 }
1090
1091 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1092 {
1093 struct vcpu_svm *svm = to_svm(vcpu);
1094
1095 return svm->vmcb->control.tsc_offset;
1096 }
1097
1098 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1099 {
1100 struct vcpu_svm *svm = to_svm(vcpu);
1101 u64 g_tsc_offset = 0;
1102
1103 if (is_guest_mode(vcpu)) {
1104 g_tsc_offset = svm->vmcb->control.tsc_offset -
1105 svm->nested.hsave->control.tsc_offset;
1106 svm->nested.hsave->control.tsc_offset = offset;
1107 } else
1108 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1109 svm->vmcb->control.tsc_offset,
1110 offset);
1111
1112 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1113
1114 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1115 }
1116
1117 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1118 {
1119 struct vcpu_svm *svm = to_svm(vcpu);
1120
1121 if (host) {
1122 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1123 WARN_ON(adjustment < 0);
1124 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1125 }
1126
1127 svm->vmcb->control.tsc_offset += adjustment;
1128 if (is_guest_mode(vcpu))
1129 svm->nested.hsave->control.tsc_offset += adjustment;
1130 else
1131 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1132 svm->vmcb->control.tsc_offset - adjustment,
1133 svm->vmcb->control.tsc_offset);
1134
1135 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1136 }
1137
1138 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1139 {
1140 u64 tsc;
1141
1142 tsc = svm_scale_tsc(vcpu, rdtsc());
1143
1144 return target_tsc - tsc;
1145 }
1146
1147 static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
1148 {
1149 struct kvm_vcpu *vcpu = &svm->vcpu;
1150
1151 /* Unlike Intel, AMD takes the guest's CR0.CD into account.
1152 *
1153 * AMD does not have IPAT. To emulate it for the case of guests
1154 * with no assigned devices, just set everything to WB. If guests
1155 * have assigned devices, however, we cannot force WB for RAM
1156 * pages only, so use the guest PAT directly.
1157 */
1158 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1159 *g_pat = 0x0606060606060606;
1160 else
1161 *g_pat = vcpu->arch.pat;
1162 }
1163
1164 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
1165 {
1166 u8 mtrr;
1167
1168 /*
1169 * 1. MMIO: trust guest MTRR, so same as item 3.
1170 * 2. No passthrough: always map as WB, and force guest PAT to WB as well
1171 * 3. Passthrough: can't guarantee the result, try to trust guest.
1172 */
1173 if (!is_mmio && !kvm_arch_has_assigned_device(vcpu->kvm))
1174 return 0;
1175
1176 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED) &&
1177 kvm_read_cr0(vcpu) & X86_CR0_CD)
1178 return _PAGE_NOCACHE;
1179
1180 mtrr = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
1181 return mtrr2protval[mtrr];
1182 }
1183
1184 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1185 {
1186 struct vmcb_control_area *control = &svm->vmcb->control;
1187 struct vmcb_save_area *save = &svm->vmcb->save;
1188
1189 svm->vcpu.fpu_active = 1;
1190 svm->vcpu.arch.hflags = 0;
1191
1192 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1193 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1194 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1195 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1196 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1197 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1198 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1199
1200 set_dr_intercepts(svm);
1201
1202 set_exception_intercept(svm, PF_VECTOR);
1203 set_exception_intercept(svm, UD_VECTOR);
1204 set_exception_intercept(svm, MC_VECTOR);
1205
1206 set_intercept(svm, INTERCEPT_INTR);
1207 set_intercept(svm, INTERCEPT_NMI);
1208 set_intercept(svm, INTERCEPT_SMI);
1209 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1210 set_intercept(svm, INTERCEPT_RDPMC);
1211 set_intercept(svm, INTERCEPT_CPUID);
1212 set_intercept(svm, INTERCEPT_INVD);
1213 set_intercept(svm, INTERCEPT_HLT);
1214 set_intercept(svm, INTERCEPT_INVLPG);
1215 set_intercept(svm, INTERCEPT_INVLPGA);
1216 set_intercept(svm, INTERCEPT_IOIO_PROT);
1217 set_intercept(svm, INTERCEPT_MSR_PROT);
1218 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1219 set_intercept(svm, INTERCEPT_SHUTDOWN);
1220 set_intercept(svm, INTERCEPT_VMRUN);
1221 set_intercept(svm, INTERCEPT_VMMCALL);
1222 set_intercept(svm, INTERCEPT_VMLOAD);
1223 set_intercept(svm, INTERCEPT_VMSAVE);
1224 set_intercept(svm, INTERCEPT_STGI);
1225 set_intercept(svm, INTERCEPT_CLGI);
1226 set_intercept(svm, INTERCEPT_SKINIT);
1227 set_intercept(svm, INTERCEPT_WBINVD);
1228 set_intercept(svm, INTERCEPT_MONITOR);
1229 set_intercept(svm, INTERCEPT_MWAIT);
1230 set_intercept(svm, INTERCEPT_XSETBV);
1231
1232 control->iopm_base_pa = iopm_base;
1233 control->msrpm_base_pa = __pa(svm->msrpm);
1234 control->int_ctl = V_INTR_MASKING_MASK;
1235
1236 init_seg(&save->es);
1237 init_seg(&save->ss);
1238 init_seg(&save->ds);
1239 init_seg(&save->fs);
1240 init_seg(&save->gs);
1241
1242 save->cs.selector = 0xf000;
1243 save->cs.base = 0xffff0000;
1244 /* Executable/Readable Code Segment */
1245 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1246 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1247 save->cs.limit = 0xffff;
1248
1249 save->gdtr.limit = 0xffff;
1250 save->idtr.limit = 0xffff;
1251
1252 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1253 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1254
1255 if (!init_event)
1256 svm_set_efer(&svm->vcpu, 0);
1257 save->dr6 = 0xffff0ff0;
1258 kvm_set_rflags(&svm->vcpu, 2);
1259 save->rip = 0x0000fff0;
1260 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1261
1262 /*
1263 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1264 * It also updates the guest-visible cr0 value.
1265 */
1266 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1267
1268 save->cr4 = X86_CR4_PAE;
1269 /* rdx = ?? */
1270
1271 if (npt_enabled) {
1272 /* Setup VMCB for Nested Paging */
1273 control->nested_ctl = 1;
1274 clr_intercept(svm, INTERCEPT_INVLPG);
1275 clr_exception_intercept(svm, PF_VECTOR);
1276 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1277 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1278 save->g_pat = svm->vcpu.arch.pat;
1279 svm_set_guest_pat(svm, &save->g_pat);
1280 save->cr3 = 0;
1281 save->cr4 = 0;
1282 }
1283 svm->asid_generation = 0;
1284
1285 svm->nested.vmcb = 0;
1286 svm->vcpu.arch.hflags = 0;
1287
1288 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1289 control->pause_filter_count = 3000;
1290 set_intercept(svm, INTERCEPT_PAUSE);
1291 }
1292
1293 mark_all_dirty(svm->vmcb);
1294
1295 enable_gif(svm);
1296 }
1297
1298 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1299 {
1300 struct vcpu_svm *svm = to_svm(vcpu);
1301 u32 dummy;
1302 u32 eax = 1;
1303
1304 if (!init_event) {
1305 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1306 MSR_IA32_APICBASE_ENABLE;
1307 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1308 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1309 }
1310 init_vmcb(svm, init_event);
1311
1312 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1313 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1314 }
1315
1316 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1317 {
1318 struct vcpu_svm *svm;
1319 struct page *page;
1320 struct page *msrpm_pages;
1321 struct page *hsave_page;
1322 struct page *nested_msrpm_pages;
1323 int err;
1324
1325 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1326 if (!svm) {
1327 err = -ENOMEM;
1328 goto out;
1329 }
1330
1331 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1332
1333 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1334 if (err)
1335 goto free_svm;
1336
1337 err = -ENOMEM;
1338 page = alloc_page(GFP_KERNEL);
1339 if (!page)
1340 goto uninit;
1341
1342 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1343 if (!msrpm_pages)
1344 goto free_page1;
1345
1346 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1347 if (!nested_msrpm_pages)
1348 goto free_page2;
1349
1350 hsave_page = alloc_page(GFP_KERNEL);
1351 if (!hsave_page)
1352 goto free_page3;
1353
1354 svm->nested.hsave = page_address(hsave_page);
1355
1356 svm->msrpm = page_address(msrpm_pages);
1357 svm_vcpu_init_msrpm(svm->msrpm);
1358
1359 svm->nested.msrpm = page_address(nested_msrpm_pages);
1360 svm_vcpu_init_msrpm(svm->nested.msrpm);
1361
1362 svm->vmcb = page_address(page);
1363 clear_page(svm->vmcb);
1364 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1365 svm->asid_generation = 0;
1366 init_vmcb(svm, false);
1367
1368 svm_init_osvw(&svm->vcpu);
1369
1370 return &svm->vcpu;
1371
1372 free_page3:
1373 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1374 free_page2:
1375 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1376 free_page1:
1377 __free_page(page);
1378 uninit:
1379 kvm_vcpu_uninit(&svm->vcpu);
1380 free_svm:
1381 kmem_cache_free(kvm_vcpu_cache, svm);
1382 out:
1383 return ERR_PTR(err);
1384 }
1385
1386 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1387 {
1388 struct vcpu_svm *svm = to_svm(vcpu);
1389
1390 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1391 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1392 __free_page(virt_to_page(svm->nested.hsave));
1393 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1394 kvm_vcpu_uninit(vcpu);
1395 kmem_cache_free(kvm_vcpu_cache, svm);
1396 }
1397
1398 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1399 {
1400 struct vcpu_svm *svm = to_svm(vcpu);
1401 int i;
1402
1403 if (unlikely(cpu != vcpu->cpu)) {
1404 svm->asid_generation = 0;
1405 mark_all_dirty(svm->vmcb);
1406 }
1407
1408 #ifdef CONFIG_X86_64
1409 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1410 #endif
1411 savesegment(fs, svm->host.fs);
1412 savesegment(gs, svm->host.gs);
1413 svm->host.ldt = kvm_read_ldt();
1414
1415 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1416 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1417
1418 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1419 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1420 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1421 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1422 }
1423 }
1424
1425 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1426 {
1427 struct vcpu_svm *svm = to_svm(vcpu);
1428 int i;
1429
1430 ++vcpu->stat.host_state_reload;
1431 kvm_load_ldt(svm->host.ldt);
1432 #ifdef CONFIG_X86_64
1433 loadsegment(fs, svm->host.fs);
1434 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1435 load_gs_index(svm->host.gs);
1436 #else
1437 #ifdef CONFIG_X86_32_LAZY_GS
1438 loadsegment(gs, svm->host.gs);
1439 #endif
1440 #endif
1441 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1442 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1443 }
1444
1445 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1446 {
1447 return to_svm(vcpu)->vmcb->save.rflags;
1448 }
1449
1450 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1451 {
1452 /*
1453 * Any change of EFLAGS.VM is accompained by a reload of SS
1454 * (caused by either a task switch or an inter-privilege IRET),
1455 * so we do not need to update the CPL here.
1456 */
1457 to_svm(vcpu)->vmcb->save.rflags = rflags;
1458 }
1459
1460 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1461 {
1462 switch (reg) {
1463 case VCPU_EXREG_PDPTR:
1464 BUG_ON(!npt_enabled);
1465 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1466 break;
1467 default:
1468 BUG();
1469 }
1470 }
1471
1472 static void svm_set_vintr(struct vcpu_svm *svm)
1473 {
1474 set_intercept(svm, INTERCEPT_VINTR);
1475 }
1476
1477 static void svm_clear_vintr(struct vcpu_svm *svm)
1478 {
1479 clr_intercept(svm, INTERCEPT_VINTR);
1480 }
1481
1482 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1483 {
1484 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1485
1486 switch (seg) {
1487 case VCPU_SREG_CS: return &save->cs;
1488 case VCPU_SREG_DS: return &save->ds;
1489 case VCPU_SREG_ES: return &save->es;
1490 case VCPU_SREG_FS: return &save->fs;
1491 case VCPU_SREG_GS: return &save->gs;
1492 case VCPU_SREG_SS: return &save->ss;
1493 case VCPU_SREG_TR: return &save->tr;
1494 case VCPU_SREG_LDTR: return &save->ldtr;
1495 }
1496 BUG();
1497 return NULL;
1498 }
1499
1500 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1501 {
1502 struct vmcb_seg *s = svm_seg(vcpu, seg);
1503
1504 return s->base;
1505 }
1506
1507 static void svm_get_segment(struct kvm_vcpu *vcpu,
1508 struct kvm_segment *var, int seg)
1509 {
1510 struct vmcb_seg *s = svm_seg(vcpu, seg);
1511
1512 var->base = s->base;
1513 var->limit = s->limit;
1514 var->selector = s->selector;
1515 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1516 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1517 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1518 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1519 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1520 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1521 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1522
1523 /*
1524 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1525 * However, the SVM spec states that the G bit is not observed by the
1526 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1527 * So let's synthesize a legal G bit for all segments, this helps
1528 * running KVM nested. It also helps cross-vendor migration, because
1529 * Intel's vmentry has a check on the 'G' bit.
1530 */
1531 var->g = s->limit > 0xfffff;
1532
1533 /*
1534 * AMD's VMCB does not have an explicit unusable field, so emulate it
1535 * for cross vendor migration purposes by "not present"
1536 */
1537 var->unusable = !var->present || (var->type == 0);
1538
1539 switch (seg) {
1540 case VCPU_SREG_TR:
1541 /*
1542 * Work around a bug where the busy flag in the tr selector
1543 * isn't exposed
1544 */
1545 var->type |= 0x2;
1546 break;
1547 case VCPU_SREG_DS:
1548 case VCPU_SREG_ES:
1549 case VCPU_SREG_FS:
1550 case VCPU_SREG_GS:
1551 /*
1552 * The accessed bit must always be set in the segment
1553 * descriptor cache, although it can be cleared in the
1554 * descriptor, the cached bit always remains at 1. Since
1555 * Intel has a check on this, set it here to support
1556 * cross-vendor migration.
1557 */
1558 if (!var->unusable)
1559 var->type |= 0x1;
1560 break;
1561 case VCPU_SREG_SS:
1562 /*
1563 * On AMD CPUs sometimes the DB bit in the segment
1564 * descriptor is left as 1, although the whole segment has
1565 * been made unusable. Clear it here to pass an Intel VMX
1566 * entry check when cross vendor migrating.
1567 */
1568 if (var->unusable)
1569 var->db = 0;
1570 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1571 break;
1572 }
1573 }
1574
1575 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1576 {
1577 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1578
1579 return save->cpl;
1580 }
1581
1582 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1583 {
1584 struct vcpu_svm *svm = to_svm(vcpu);
1585
1586 dt->size = svm->vmcb->save.idtr.limit;
1587 dt->address = svm->vmcb->save.idtr.base;
1588 }
1589
1590 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1591 {
1592 struct vcpu_svm *svm = to_svm(vcpu);
1593
1594 svm->vmcb->save.idtr.limit = dt->size;
1595 svm->vmcb->save.idtr.base = dt->address ;
1596 mark_dirty(svm->vmcb, VMCB_DT);
1597 }
1598
1599 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1600 {
1601 struct vcpu_svm *svm = to_svm(vcpu);
1602
1603 dt->size = svm->vmcb->save.gdtr.limit;
1604 dt->address = svm->vmcb->save.gdtr.base;
1605 }
1606
1607 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1608 {
1609 struct vcpu_svm *svm = to_svm(vcpu);
1610
1611 svm->vmcb->save.gdtr.limit = dt->size;
1612 svm->vmcb->save.gdtr.base = dt->address ;
1613 mark_dirty(svm->vmcb, VMCB_DT);
1614 }
1615
1616 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1617 {
1618 }
1619
1620 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1621 {
1622 }
1623
1624 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1625 {
1626 }
1627
1628 static void update_cr0_intercept(struct vcpu_svm *svm)
1629 {
1630 ulong gcr0 = svm->vcpu.arch.cr0;
1631 u64 *hcr0 = &svm->vmcb->save.cr0;
1632
1633 if (!svm->vcpu.fpu_active)
1634 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1635 else
1636 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1637 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1638
1639 mark_dirty(svm->vmcb, VMCB_CR);
1640
1641 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1642 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1643 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1644 } else {
1645 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1646 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1647 }
1648 }
1649
1650 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1651 {
1652 struct vcpu_svm *svm = to_svm(vcpu);
1653
1654 #ifdef CONFIG_X86_64
1655 if (vcpu->arch.efer & EFER_LME) {
1656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1657 vcpu->arch.efer |= EFER_LMA;
1658 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1659 }
1660
1661 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1662 vcpu->arch.efer &= ~EFER_LMA;
1663 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1664 }
1665 }
1666 #endif
1667 vcpu->arch.cr0 = cr0;
1668
1669 if (!npt_enabled)
1670 cr0 |= X86_CR0_PG | X86_CR0_WP;
1671
1672 if (!vcpu->fpu_active)
1673 cr0 |= X86_CR0_TS;
1674
1675 /* These are emulated via page tables. */
1676 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1677
1678 svm->vmcb->save.cr0 = cr0;
1679 mark_dirty(svm->vmcb, VMCB_CR);
1680 update_cr0_intercept(svm);
1681 }
1682
1683 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1684 {
1685 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1686 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1687
1688 if (cr4 & X86_CR4_VMXE)
1689 return 1;
1690
1691 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1692 svm_flush_tlb(vcpu);
1693
1694 vcpu->arch.cr4 = cr4;
1695 if (!npt_enabled)
1696 cr4 |= X86_CR4_PAE;
1697 cr4 |= host_cr4_mce;
1698 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1699 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1700 return 0;
1701 }
1702
1703 static void svm_set_segment(struct kvm_vcpu *vcpu,
1704 struct kvm_segment *var, int seg)
1705 {
1706 struct vcpu_svm *svm = to_svm(vcpu);
1707 struct vmcb_seg *s = svm_seg(vcpu, seg);
1708
1709 s->base = var->base;
1710 s->limit = var->limit;
1711 s->selector = var->selector;
1712 if (var->unusable)
1713 s->attrib = 0;
1714 else {
1715 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1716 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1717 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1718 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1719 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1720 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1721 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1722 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1723 }
1724
1725 /*
1726 * This is always accurate, except if SYSRET returned to a segment
1727 * with SS.DPL != 3. Intel does not have this quirk, and always
1728 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1729 * would entail passing the CPL to userspace and back.
1730 */
1731 if (seg == VCPU_SREG_SS)
1732 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1733
1734 mark_dirty(svm->vmcb, VMCB_SEG);
1735 }
1736
1737 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1738 {
1739 struct vcpu_svm *svm = to_svm(vcpu);
1740
1741 clr_exception_intercept(svm, DB_VECTOR);
1742 clr_exception_intercept(svm, BP_VECTOR);
1743
1744 if (svm->nmi_singlestep)
1745 set_exception_intercept(svm, DB_VECTOR);
1746
1747 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1748 if (vcpu->guest_debug &
1749 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1750 set_exception_intercept(svm, DB_VECTOR);
1751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1752 set_exception_intercept(svm, BP_VECTOR);
1753 } else
1754 vcpu->guest_debug = 0;
1755 }
1756
1757 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1758 {
1759 if (sd->next_asid > sd->max_asid) {
1760 ++sd->asid_generation;
1761 sd->next_asid = 1;
1762 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1763 }
1764
1765 svm->asid_generation = sd->asid_generation;
1766 svm->vmcb->control.asid = sd->next_asid++;
1767
1768 mark_dirty(svm->vmcb, VMCB_ASID);
1769 }
1770
1771 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1772 {
1773 return to_svm(vcpu)->vmcb->save.dr6;
1774 }
1775
1776 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1777 {
1778 struct vcpu_svm *svm = to_svm(vcpu);
1779
1780 svm->vmcb->save.dr6 = value;
1781 mark_dirty(svm->vmcb, VMCB_DR);
1782 }
1783
1784 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1785 {
1786 struct vcpu_svm *svm = to_svm(vcpu);
1787
1788 get_debugreg(vcpu->arch.db[0], 0);
1789 get_debugreg(vcpu->arch.db[1], 1);
1790 get_debugreg(vcpu->arch.db[2], 2);
1791 get_debugreg(vcpu->arch.db[3], 3);
1792 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1793 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1794
1795 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1796 set_dr_intercepts(svm);
1797 }
1798
1799 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1800 {
1801 struct vcpu_svm *svm = to_svm(vcpu);
1802
1803 svm->vmcb->save.dr7 = value;
1804 mark_dirty(svm->vmcb, VMCB_DR);
1805 }
1806
1807 static int pf_interception(struct vcpu_svm *svm)
1808 {
1809 u64 fault_address = svm->vmcb->control.exit_info_2;
1810 u32 error_code;
1811 int r = 1;
1812
1813 switch (svm->apf_reason) {
1814 default:
1815 error_code = svm->vmcb->control.exit_info_1;
1816
1817 trace_kvm_page_fault(fault_address, error_code);
1818 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1819 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1820 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1821 svm->vmcb->control.insn_bytes,
1822 svm->vmcb->control.insn_len);
1823 break;
1824 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1825 svm->apf_reason = 0;
1826 local_irq_disable();
1827 kvm_async_pf_task_wait(fault_address);
1828 local_irq_enable();
1829 break;
1830 case KVM_PV_REASON_PAGE_READY:
1831 svm->apf_reason = 0;
1832 local_irq_disable();
1833 kvm_async_pf_task_wake(fault_address);
1834 local_irq_enable();
1835 break;
1836 }
1837 return r;
1838 }
1839
1840 static int db_interception(struct vcpu_svm *svm)
1841 {
1842 struct kvm_run *kvm_run = svm->vcpu.run;
1843
1844 if (!(svm->vcpu.guest_debug &
1845 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1846 !svm->nmi_singlestep) {
1847 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1848 return 1;
1849 }
1850
1851 if (svm->nmi_singlestep) {
1852 svm->nmi_singlestep = false;
1853 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1854 svm->vmcb->save.rflags &=
1855 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1856 update_db_bp_intercept(&svm->vcpu);
1857 }
1858
1859 if (svm->vcpu.guest_debug &
1860 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1861 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1862 kvm_run->debug.arch.pc =
1863 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1864 kvm_run->debug.arch.exception = DB_VECTOR;
1865 return 0;
1866 }
1867
1868 return 1;
1869 }
1870
1871 static int bp_interception(struct vcpu_svm *svm)
1872 {
1873 struct kvm_run *kvm_run = svm->vcpu.run;
1874
1875 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1876 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1877 kvm_run->debug.arch.exception = BP_VECTOR;
1878 return 0;
1879 }
1880
1881 static int ud_interception(struct vcpu_svm *svm)
1882 {
1883 int er;
1884
1885 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1886 if (er != EMULATE_DONE)
1887 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1888 return 1;
1889 }
1890
1891 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1892 {
1893 struct vcpu_svm *svm = to_svm(vcpu);
1894
1895 clr_exception_intercept(svm, NM_VECTOR);
1896
1897 svm->vcpu.fpu_active = 1;
1898 update_cr0_intercept(svm);
1899 }
1900
1901 static int nm_interception(struct vcpu_svm *svm)
1902 {
1903 svm_fpu_activate(&svm->vcpu);
1904 return 1;
1905 }
1906
1907 static bool is_erratum_383(void)
1908 {
1909 int err, i;
1910 u64 value;
1911
1912 if (!erratum_383_found)
1913 return false;
1914
1915 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1916 if (err)
1917 return false;
1918
1919 /* Bit 62 may or may not be set for this mce */
1920 value &= ~(1ULL << 62);
1921
1922 if (value != 0xb600000000010015ULL)
1923 return false;
1924
1925 /* Clear MCi_STATUS registers */
1926 for (i = 0; i < 6; ++i)
1927 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1928
1929 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1930 if (!err) {
1931 u32 low, high;
1932
1933 value &= ~(1ULL << 2);
1934 low = lower_32_bits(value);
1935 high = upper_32_bits(value);
1936
1937 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1938 }
1939
1940 /* Flush tlb to evict multi-match entries */
1941 __flush_tlb_all();
1942
1943 return true;
1944 }
1945
1946 static void svm_handle_mce(struct vcpu_svm *svm)
1947 {
1948 if (is_erratum_383()) {
1949 /*
1950 * Erratum 383 triggered. Guest state is corrupt so kill the
1951 * guest.
1952 */
1953 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1954
1955 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1956
1957 return;
1958 }
1959
1960 /*
1961 * On an #MC intercept the MCE handler is not called automatically in
1962 * the host. So do it by hand here.
1963 */
1964 asm volatile (
1965 "int $0x12\n");
1966 /* not sure if we ever come back to this point */
1967
1968 return;
1969 }
1970
1971 static int mc_interception(struct vcpu_svm *svm)
1972 {
1973 return 1;
1974 }
1975
1976 static int shutdown_interception(struct vcpu_svm *svm)
1977 {
1978 struct kvm_run *kvm_run = svm->vcpu.run;
1979
1980 /*
1981 * VMCB is undefined after a SHUTDOWN intercept
1982 * so reinitialize it.
1983 */
1984 clear_page(svm->vmcb);
1985 init_vmcb(svm, false);
1986
1987 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1988 return 0;
1989 }
1990
1991 static int io_interception(struct vcpu_svm *svm)
1992 {
1993 struct kvm_vcpu *vcpu = &svm->vcpu;
1994 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1995 int size, in, string;
1996 unsigned port;
1997
1998 ++svm->vcpu.stat.io_exits;
1999 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2000 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2001 if (string || in)
2002 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2003
2004 port = io_info >> 16;
2005 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2006 svm->next_rip = svm->vmcb->control.exit_info_2;
2007 skip_emulated_instruction(&svm->vcpu);
2008
2009 return kvm_fast_pio_out(vcpu, size, port);
2010 }
2011
2012 static int nmi_interception(struct vcpu_svm *svm)
2013 {
2014 return 1;
2015 }
2016
2017 static int intr_interception(struct vcpu_svm *svm)
2018 {
2019 ++svm->vcpu.stat.irq_exits;
2020 return 1;
2021 }
2022
2023 static int nop_on_interception(struct vcpu_svm *svm)
2024 {
2025 return 1;
2026 }
2027
2028 static int halt_interception(struct vcpu_svm *svm)
2029 {
2030 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2031 return kvm_emulate_halt(&svm->vcpu);
2032 }
2033
2034 static int vmmcall_interception(struct vcpu_svm *svm)
2035 {
2036 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2037 kvm_emulate_hypercall(&svm->vcpu);
2038 return 1;
2039 }
2040
2041 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2042 {
2043 struct vcpu_svm *svm = to_svm(vcpu);
2044
2045 return svm->nested.nested_cr3;
2046 }
2047
2048 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2049 {
2050 struct vcpu_svm *svm = to_svm(vcpu);
2051 u64 cr3 = svm->nested.nested_cr3;
2052 u64 pdpte;
2053 int ret;
2054
2055 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2056 offset_in_page(cr3) + index * 8, 8);
2057 if (ret)
2058 return 0;
2059 return pdpte;
2060 }
2061
2062 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2063 unsigned long root)
2064 {
2065 struct vcpu_svm *svm = to_svm(vcpu);
2066
2067 svm->vmcb->control.nested_cr3 = root;
2068 mark_dirty(svm->vmcb, VMCB_NPT);
2069 svm_flush_tlb(vcpu);
2070 }
2071
2072 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2073 struct x86_exception *fault)
2074 {
2075 struct vcpu_svm *svm = to_svm(vcpu);
2076
2077 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2078 /*
2079 * TODO: track the cause of the nested page fault, and
2080 * correctly fill in the high bits of exit_info_1.
2081 */
2082 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2083 svm->vmcb->control.exit_code_hi = 0;
2084 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2085 svm->vmcb->control.exit_info_2 = fault->address;
2086 }
2087
2088 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2089 svm->vmcb->control.exit_info_1 |= fault->error_code;
2090
2091 /*
2092 * The present bit is always zero for page structure faults on real
2093 * hardware.
2094 */
2095 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2096 svm->vmcb->control.exit_info_1 &= ~1;
2097
2098 nested_svm_vmexit(svm);
2099 }
2100
2101 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2102 {
2103 WARN_ON(mmu_is_nested(vcpu));
2104 kvm_init_shadow_mmu(vcpu);
2105 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2106 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2107 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2108 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2109 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2110 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2111 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2112 }
2113
2114 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2115 {
2116 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2117 }
2118
2119 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2120 {
2121 if (!(svm->vcpu.arch.efer & EFER_SVME)
2122 || !is_paging(&svm->vcpu)) {
2123 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2124 return 1;
2125 }
2126
2127 if (svm->vmcb->save.cpl) {
2128 kvm_inject_gp(&svm->vcpu, 0);
2129 return 1;
2130 }
2131
2132 return 0;
2133 }
2134
2135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2136 bool has_error_code, u32 error_code)
2137 {
2138 int vmexit;
2139
2140 if (!is_guest_mode(&svm->vcpu))
2141 return 0;
2142
2143 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2144 svm->vmcb->control.exit_code_hi = 0;
2145 svm->vmcb->control.exit_info_1 = error_code;
2146 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2147
2148 vmexit = nested_svm_intercept(svm);
2149 if (vmexit == NESTED_EXIT_DONE)
2150 svm->nested.exit_required = true;
2151
2152 return vmexit;
2153 }
2154
2155 /* This function returns true if it is save to enable the irq window */
2156 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2157 {
2158 if (!is_guest_mode(&svm->vcpu))
2159 return true;
2160
2161 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2162 return true;
2163
2164 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2165 return false;
2166
2167 /*
2168 * if vmexit was already requested (by intercepted exception
2169 * for instance) do not overwrite it with "external interrupt"
2170 * vmexit.
2171 */
2172 if (svm->nested.exit_required)
2173 return false;
2174
2175 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2176 svm->vmcb->control.exit_info_1 = 0;
2177 svm->vmcb->control.exit_info_2 = 0;
2178
2179 if (svm->nested.intercept & 1ULL) {
2180 /*
2181 * The #vmexit can't be emulated here directly because this
2182 * code path runs with irqs and preemption disabled. A
2183 * #vmexit emulation might sleep. Only signal request for
2184 * the #vmexit here.
2185 */
2186 svm->nested.exit_required = true;
2187 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2188 return false;
2189 }
2190
2191 return true;
2192 }
2193
2194 /* This function returns true if it is save to enable the nmi window */
2195 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2196 {
2197 if (!is_guest_mode(&svm->vcpu))
2198 return true;
2199
2200 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2201 return true;
2202
2203 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2204 svm->nested.exit_required = true;
2205
2206 return false;
2207 }
2208
2209 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2210 {
2211 struct page *page;
2212
2213 might_sleep();
2214
2215 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2216 if (is_error_page(page))
2217 goto error;
2218
2219 *_page = page;
2220
2221 return kmap(page);
2222
2223 error:
2224 kvm_inject_gp(&svm->vcpu, 0);
2225
2226 return NULL;
2227 }
2228
2229 static void nested_svm_unmap(struct page *page)
2230 {
2231 kunmap(page);
2232 kvm_release_page_dirty(page);
2233 }
2234
2235 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2236 {
2237 unsigned port, size, iopm_len;
2238 u16 val, mask;
2239 u8 start_bit;
2240 u64 gpa;
2241
2242 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2243 return NESTED_EXIT_HOST;
2244
2245 port = svm->vmcb->control.exit_info_1 >> 16;
2246 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2247 SVM_IOIO_SIZE_SHIFT;
2248 gpa = svm->nested.vmcb_iopm + (port / 8);
2249 start_bit = port % 8;
2250 iopm_len = (start_bit + size > 8) ? 2 : 1;
2251 mask = (0xf >> (4 - size)) << start_bit;
2252 val = 0;
2253
2254 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2255 return NESTED_EXIT_DONE;
2256
2257 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2258 }
2259
2260 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2261 {
2262 u32 offset, msr, value;
2263 int write, mask;
2264
2265 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2266 return NESTED_EXIT_HOST;
2267
2268 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2269 offset = svm_msrpm_offset(msr);
2270 write = svm->vmcb->control.exit_info_1 & 1;
2271 mask = 1 << ((2 * (msr & 0xf)) + write);
2272
2273 if (offset == MSR_INVALID)
2274 return NESTED_EXIT_DONE;
2275
2276 /* Offset is in 32 bit units but need in 8 bit units */
2277 offset *= 4;
2278
2279 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2280 return NESTED_EXIT_DONE;
2281
2282 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2283 }
2284
2285 static int nested_svm_exit_special(struct vcpu_svm *svm)
2286 {
2287 u32 exit_code = svm->vmcb->control.exit_code;
2288
2289 switch (exit_code) {
2290 case SVM_EXIT_INTR:
2291 case SVM_EXIT_NMI:
2292 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2293 return NESTED_EXIT_HOST;
2294 case SVM_EXIT_NPF:
2295 /* For now we are always handling NPFs when using them */
2296 if (npt_enabled)
2297 return NESTED_EXIT_HOST;
2298 break;
2299 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2300 /* When we're shadowing, trap PFs, but not async PF */
2301 if (!npt_enabled && svm->apf_reason == 0)
2302 return NESTED_EXIT_HOST;
2303 break;
2304 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2305 nm_interception(svm);
2306 break;
2307 default:
2308 break;
2309 }
2310
2311 return NESTED_EXIT_CONTINUE;
2312 }
2313
2314 /*
2315 * If this function returns true, this #vmexit was already handled
2316 */
2317 static int nested_svm_intercept(struct vcpu_svm *svm)
2318 {
2319 u32 exit_code = svm->vmcb->control.exit_code;
2320 int vmexit = NESTED_EXIT_HOST;
2321
2322 switch (exit_code) {
2323 case SVM_EXIT_MSR:
2324 vmexit = nested_svm_exit_handled_msr(svm);
2325 break;
2326 case SVM_EXIT_IOIO:
2327 vmexit = nested_svm_intercept_ioio(svm);
2328 break;
2329 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2330 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2331 if (svm->nested.intercept_cr & bit)
2332 vmexit = NESTED_EXIT_DONE;
2333 break;
2334 }
2335 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2336 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2337 if (svm->nested.intercept_dr & bit)
2338 vmexit = NESTED_EXIT_DONE;
2339 break;
2340 }
2341 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2342 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2343 if (svm->nested.intercept_exceptions & excp_bits)
2344 vmexit = NESTED_EXIT_DONE;
2345 /* async page fault always cause vmexit */
2346 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2347 svm->apf_reason != 0)
2348 vmexit = NESTED_EXIT_DONE;
2349 break;
2350 }
2351 case SVM_EXIT_ERR: {
2352 vmexit = NESTED_EXIT_DONE;
2353 break;
2354 }
2355 default: {
2356 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2357 if (svm->nested.intercept & exit_bits)
2358 vmexit = NESTED_EXIT_DONE;
2359 }
2360 }
2361
2362 return vmexit;
2363 }
2364
2365 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2366 {
2367 int vmexit;
2368
2369 vmexit = nested_svm_intercept(svm);
2370
2371 if (vmexit == NESTED_EXIT_DONE)
2372 nested_svm_vmexit(svm);
2373
2374 return vmexit;
2375 }
2376
2377 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2378 {
2379 struct vmcb_control_area *dst = &dst_vmcb->control;
2380 struct vmcb_control_area *from = &from_vmcb->control;
2381
2382 dst->intercept_cr = from->intercept_cr;
2383 dst->intercept_dr = from->intercept_dr;
2384 dst->intercept_exceptions = from->intercept_exceptions;
2385 dst->intercept = from->intercept;
2386 dst->iopm_base_pa = from->iopm_base_pa;
2387 dst->msrpm_base_pa = from->msrpm_base_pa;
2388 dst->tsc_offset = from->tsc_offset;
2389 dst->asid = from->asid;
2390 dst->tlb_ctl = from->tlb_ctl;
2391 dst->int_ctl = from->int_ctl;
2392 dst->int_vector = from->int_vector;
2393 dst->int_state = from->int_state;
2394 dst->exit_code = from->exit_code;
2395 dst->exit_code_hi = from->exit_code_hi;
2396 dst->exit_info_1 = from->exit_info_1;
2397 dst->exit_info_2 = from->exit_info_2;
2398 dst->exit_int_info = from->exit_int_info;
2399 dst->exit_int_info_err = from->exit_int_info_err;
2400 dst->nested_ctl = from->nested_ctl;
2401 dst->event_inj = from->event_inj;
2402 dst->event_inj_err = from->event_inj_err;
2403 dst->nested_cr3 = from->nested_cr3;
2404 dst->lbr_ctl = from->lbr_ctl;
2405 }
2406
2407 static int nested_svm_vmexit(struct vcpu_svm *svm)
2408 {
2409 struct vmcb *nested_vmcb;
2410 struct vmcb *hsave = svm->nested.hsave;
2411 struct vmcb *vmcb = svm->vmcb;
2412 struct page *page;
2413
2414 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2415 vmcb->control.exit_info_1,
2416 vmcb->control.exit_info_2,
2417 vmcb->control.exit_int_info,
2418 vmcb->control.exit_int_info_err,
2419 KVM_ISA_SVM);
2420
2421 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2422 if (!nested_vmcb)
2423 return 1;
2424
2425 /* Exit Guest-Mode */
2426 leave_guest_mode(&svm->vcpu);
2427 svm->nested.vmcb = 0;
2428
2429 /* Give the current vmcb to the guest */
2430 disable_gif(svm);
2431
2432 nested_vmcb->save.es = vmcb->save.es;
2433 nested_vmcb->save.cs = vmcb->save.cs;
2434 nested_vmcb->save.ss = vmcb->save.ss;
2435 nested_vmcb->save.ds = vmcb->save.ds;
2436 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2437 nested_vmcb->save.idtr = vmcb->save.idtr;
2438 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2439 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2440 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2441 nested_vmcb->save.cr2 = vmcb->save.cr2;
2442 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2443 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2444 nested_vmcb->save.rip = vmcb->save.rip;
2445 nested_vmcb->save.rsp = vmcb->save.rsp;
2446 nested_vmcb->save.rax = vmcb->save.rax;
2447 nested_vmcb->save.dr7 = vmcb->save.dr7;
2448 nested_vmcb->save.dr6 = vmcb->save.dr6;
2449 nested_vmcb->save.cpl = vmcb->save.cpl;
2450
2451 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2452 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2453 nested_vmcb->control.int_state = vmcb->control.int_state;
2454 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2455 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2456 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2457 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2458 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2459 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2460 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2461
2462 /*
2463 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2464 * to make sure that we do not lose injected events. So check event_inj
2465 * here and copy it to exit_int_info if it is valid.
2466 * Exit_int_info and event_inj can't be both valid because the case
2467 * below only happens on a VMRUN instruction intercept which has
2468 * no valid exit_int_info set.
2469 */
2470 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2471 struct vmcb_control_area *nc = &nested_vmcb->control;
2472
2473 nc->exit_int_info = vmcb->control.event_inj;
2474 nc->exit_int_info_err = vmcb->control.event_inj_err;
2475 }
2476
2477 nested_vmcb->control.tlb_ctl = 0;
2478 nested_vmcb->control.event_inj = 0;
2479 nested_vmcb->control.event_inj_err = 0;
2480
2481 /* We always set V_INTR_MASKING and remember the old value in hflags */
2482 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2483 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2484
2485 /* Restore the original control entries */
2486 copy_vmcb_control_area(vmcb, hsave);
2487
2488 kvm_clear_exception_queue(&svm->vcpu);
2489 kvm_clear_interrupt_queue(&svm->vcpu);
2490
2491 svm->nested.nested_cr3 = 0;
2492
2493 /* Restore selected save entries */
2494 svm->vmcb->save.es = hsave->save.es;
2495 svm->vmcb->save.cs = hsave->save.cs;
2496 svm->vmcb->save.ss = hsave->save.ss;
2497 svm->vmcb->save.ds = hsave->save.ds;
2498 svm->vmcb->save.gdtr = hsave->save.gdtr;
2499 svm->vmcb->save.idtr = hsave->save.idtr;
2500 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2501 svm_set_efer(&svm->vcpu, hsave->save.efer);
2502 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2503 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2504 if (npt_enabled) {
2505 svm->vmcb->save.cr3 = hsave->save.cr3;
2506 svm->vcpu.arch.cr3 = hsave->save.cr3;
2507 } else {
2508 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2509 }
2510 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2511 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2512 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2513 svm->vmcb->save.dr7 = 0;
2514 svm->vmcb->save.cpl = 0;
2515 svm->vmcb->control.exit_int_info = 0;
2516
2517 mark_all_dirty(svm->vmcb);
2518
2519 nested_svm_unmap(page);
2520
2521 nested_svm_uninit_mmu_context(&svm->vcpu);
2522 kvm_mmu_reset_context(&svm->vcpu);
2523 kvm_mmu_load(&svm->vcpu);
2524
2525 return 0;
2526 }
2527
2528 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2529 {
2530 /*
2531 * This function merges the msr permission bitmaps of kvm and the
2532 * nested vmcb. It is optimized in that it only merges the parts where
2533 * the kvm msr permission bitmap may contain zero bits
2534 */
2535 int i;
2536
2537 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2538 return true;
2539
2540 for (i = 0; i < MSRPM_OFFSETS; i++) {
2541 u32 value, p;
2542 u64 offset;
2543
2544 if (msrpm_offsets[i] == 0xffffffff)
2545 break;
2546
2547 p = msrpm_offsets[i];
2548 offset = svm->nested.vmcb_msrpm + (p * 4);
2549
2550 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2551 return false;
2552
2553 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2554 }
2555
2556 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2557
2558 return true;
2559 }
2560
2561 static bool nested_vmcb_checks(struct vmcb *vmcb)
2562 {
2563 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2564 return false;
2565
2566 if (vmcb->control.asid == 0)
2567 return false;
2568
2569 if (vmcb->control.nested_ctl && !npt_enabled)
2570 return false;
2571
2572 return true;
2573 }
2574
2575 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2576 {
2577 struct vmcb *nested_vmcb;
2578 struct vmcb *hsave = svm->nested.hsave;
2579 struct vmcb *vmcb = svm->vmcb;
2580 struct page *page;
2581 u64 vmcb_gpa;
2582
2583 vmcb_gpa = svm->vmcb->save.rax;
2584
2585 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2586 if (!nested_vmcb)
2587 return false;
2588
2589 if (!nested_vmcb_checks(nested_vmcb)) {
2590 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2591 nested_vmcb->control.exit_code_hi = 0;
2592 nested_vmcb->control.exit_info_1 = 0;
2593 nested_vmcb->control.exit_info_2 = 0;
2594
2595 nested_svm_unmap(page);
2596
2597 return false;
2598 }
2599
2600 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2601 nested_vmcb->save.rip,
2602 nested_vmcb->control.int_ctl,
2603 nested_vmcb->control.event_inj,
2604 nested_vmcb->control.nested_ctl);
2605
2606 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2607 nested_vmcb->control.intercept_cr >> 16,
2608 nested_vmcb->control.intercept_exceptions,
2609 nested_vmcb->control.intercept);
2610
2611 /* Clear internal status */
2612 kvm_clear_exception_queue(&svm->vcpu);
2613 kvm_clear_interrupt_queue(&svm->vcpu);
2614
2615 /*
2616 * Save the old vmcb, so we don't need to pick what we save, but can
2617 * restore everything when a VMEXIT occurs
2618 */
2619 hsave->save.es = vmcb->save.es;
2620 hsave->save.cs = vmcb->save.cs;
2621 hsave->save.ss = vmcb->save.ss;
2622 hsave->save.ds = vmcb->save.ds;
2623 hsave->save.gdtr = vmcb->save.gdtr;
2624 hsave->save.idtr = vmcb->save.idtr;
2625 hsave->save.efer = svm->vcpu.arch.efer;
2626 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2627 hsave->save.cr4 = svm->vcpu.arch.cr4;
2628 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2629 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2630 hsave->save.rsp = vmcb->save.rsp;
2631 hsave->save.rax = vmcb->save.rax;
2632 if (npt_enabled)
2633 hsave->save.cr3 = vmcb->save.cr3;
2634 else
2635 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2636
2637 copy_vmcb_control_area(hsave, vmcb);
2638
2639 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2640 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2641 else
2642 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2643
2644 if (nested_vmcb->control.nested_ctl) {
2645 kvm_mmu_unload(&svm->vcpu);
2646 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2647 nested_svm_init_mmu_context(&svm->vcpu);
2648 }
2649
2650 /* Load the nested guest state */
2651 svm->vmcb->save.es = nested_vmcb->save.es;
2652 svm->vmcb->save.cs = nested_vmcb->save.cs;
2653 svm->vmcb->save.ss = nested_vmcb->save.ss;
2654 svm->vmcb->save.ds = nested_vmcb->save.ds;
2655 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2656 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2657 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2658 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2659 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2660 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2661 if (npt_enabled) {
2662 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2663 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2664 } else
2665 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2666
2667 /* Guest paging mode is active - reset mmu */
2668 kvm_mmu_reset_context(&svm->vcpu);
2669
2670 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2671 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2672 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2673 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2674
2675 /* In case we don't even reach vcpu_run, the fields are not updated */
2676 svm->vmcb->save.rax = nested_vmcb->save.rax;
2677 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2678 svm->vmcb->save.rip = nested_vmcb->save.rip;
2679 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2680 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2681 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2682
2683 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2684 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2685
2686 /* cache intercepts */
2687 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2688 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2689 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2690 svm->nested.intercept = nested_vmcb->control.intercept;
2691
2692 svm_flush_tlb(&svm->vcpu);
2693 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2694 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2695 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2696 else
2697 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2698
2699 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2700 /* We only want the cr8 intercept bits of the guest */
2701 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2702 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2703 }
2704
2705 /* We don't want to see VMMCALLs from a nested guest */
2706 clr_intercept(svm, INTERCEPT_VMMCALL);
2707
2708 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2709 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2710 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2711 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2712 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2713 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2714
2715 nested_svm_unmap(page);
2716
2717 /* Enter Guest-Mode */
2718 enter_guest_mode(&svm->vcpu);
2719
2720 /*
2721 * Merge guest and host intercepts - must be called with vcpu in
2722 * guest-mode to take affect here
2723 */
2724 recalc_intercepts(svm);
2725
2726 svm->nested.vmcb = vmcb_gpa;
2727
2728 enable_gif(svm);
2729
2730 mark_all_dirty(svm->vmcb);
2731
2732 return true;
2733 }
2734
2735 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2736 {
2737 to_vmcb->save.fs = from_vmcb->save.fs;
2738 to_vmcb->save.gs = from_vmcb->save.gs;
2739 to_vmcb->save.tr = from_vmcb->save.tr;
2740 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2741 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2742 to_vmcb->save.star = from_vmcb->save.star;
2743 to_vmcb->save.lstar = from_vmcb->save.lstar;
2744 to_vmcb->save.cstar = from_vmcb->save.cstar;
2745 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2746 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2747 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2748 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2749 }
2750
2751 static int vmload_interception(struct vcpu_svm *svm)
2752 {
2753 struct vmcb *nested_vmcb;
2754 struct page *page;
2755
2756 if (nested_svm_check_permissions(svm))
2757 return 1;
2758
2759 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2760 if (!nested_vmcb)
2761 return 1;
2762
2763 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2764 skip_emulated_instruction(&svm->vcpu);
2765
2766 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2767 nested_svm_unmap(page);
2768
2769 return 1;
2770 }
2771
2772 static int vmsave_interception(struct vcpu_svm *svm)
2773 {
2774 struct vmcb *nested_vmcb;
2775 struct page *page;
2776
2777 if (nested_svm_check_permissions(svm))
2778 return 1;
2779
2780 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2781 if (!nested_vmcb)
2782 return 1;
2783
2784 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2785 skip_emulated_instruction(&svm->vcpu);
2786
2787 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2788 nested_svm_unmap(page);
2789
2790 return 1;
2791 }
2792
2793 static int vmrun_interception(struct vcpu_svm *svm)
2794 {
2795 if (nested_svm_check_permissions(svm))
2796 return 1;
2797
2798 /* Save rip after vmrun instruction */
2799 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2800
2801 if (!nested_svm_vmrun(svm))
2802 return 1;
2803
2804 if (!nested_svm_vmrun_msrpm(svm))
2805 goto failed;
2806
2807 return 1;
2808
2809 failed:
2810
2811 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2812 svm->vmcb->control.exit_code_hi = 0;
2813 svm->vmcb->control.exit_info_1 = 0;
2814 svm->vmcb->control.exit_info_2 = 0;
2815
2816 nested_svm_vmexit(svm);
2817
2818 return 1;
2819 }
2820
2821 static int stgi_interception(struct vcpu_svm *svm)
2822 {
2823 if (nested_svm_check_permissions(svm))
2824 return 1;
2825
2826 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2827 skip_emulated_instruction(&svm->vcpu);
2828 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2829
2830 enable_gif(svm);
2831
2832 return 1;
2833 }
2834
2835 static int clgi_interception(struct vcpu_svm *svm)
2836 {
2837 if (nested_svm_check_permissions(svm))
2838 return 1;
2839
2840 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2841 skip_emulated_instruction(&svm->vcpu);
2842
2843 disable_gif(svm);
2844
2845 /* After a CLGI no interrupts should come */
2846 svm_clear_vintr(svm);
2847 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2848
2849 mark_dirty(svm->vmcb, VMCB_INTR);
2850
2851 return 1;
2852 }
2853
2854 static int invlpga_interception(struct vcpu_svm *svm)
2855 {
2856 struct kvm_vcpu *vcpu = &svm->vcpu;
2857
2858 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2859 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2860
2861 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2862 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2863
2864 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2865 skip_emulated_instruction(&svm->vcpu);
2866 return 1;
2867 }
2868
2869 static int skinit_interception(struct vcpu_svm *svm)
2870 {
2871 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2872
2873 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2874 return 1;
2875 }
2876
2877 static int wbinvd_interception(struct vcpu_svm *svm)
2878 {
2879 kvm_emulate_wbinvd(&svm->vcpu);
2880 return 1;
2881 }
2882
2883 static int xsetbv_interception(struct vcpu_svm *svm)
2884 {
2885 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2886 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2887
2888 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2889 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2890 skip_emulated_instruction(&svm->vcpu);
2891 }
2892
2893 return 1;
2894 }
2895
2896 static int task_switch_interception(struct vcpu_svm *svm)
2897 {
2898 u16 tss_selector;
2899 int reason;
2900 int int_type = svm->vmcb->control.exit_int_info &
2901 SVM_EXITINTINFO_TYPE_MASK;
2902 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2903 uint32_t type =
2904 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2905 uint32_t idt_v =
2906 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2907 bool has_error_code = false;
2908 u32 error_code = 0;
2909
2910 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2911
2912 if (svm->vmcb->control.exit_info_2 &
2913 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2914 reason = TASK_SWITCH_IRET;
2915 else if (svm->vmcb->control.exit_info_2 &
2916 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2917 reason = TASK_SWITCH_JMP;
2918 else if (idt_v)
2919 reason = TASK_SWITCH_GATE;
2920 else
2921 reason = TASK_SWITCH_CALL;
2922
2923 if (reason == TASK_SWITCH_GATE) {
2924 switch (type) {
2925 case SVM_EXITINTINFO_TYPE_NMI:
2926 svm->vcpu.arch.nmi_injected = false;
2927 break;
2928 case SVM_EXITINTINFO_TYPE_EXEPT:
2929 if (svm->vmcb->control.exit_info_2 &
2930 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2931 has_error_code = true;
2932 error_code =
2933 (u32)svm->vmcb->control.exit_info_2;
2934 }
2935 kvm_clear_exception_queue(&svm->vcpu);
2936 break;
2937 case SVM_EXITINTINFO_TYPE_INTR:
2938 kvm_clear_interrupt_queue(&svm->vcpu);
2939 break;
2940 default:
2941 break;
2942 }
2943 }
2944
2945 if (reason != TASK_SWITCH_GATE ||
2946 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2947 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2948 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2949 skip_emulated_instruction(&svm->vcpu);
2950
2951 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2952 int_vec = -1;
2953
2954 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2955 has_error_code, error_code) == EMULATE_FAIL) {
2956 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2957 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2958 svm->vcpu.run->internal.ndata = 0;
2959 return 0;
2960 }
2961 return 1;
2962 }
2963
2964 static int cpuid_interception(struct vcpu_svm *svm)
2965 {
2966 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2967 kvm_emulate_cpuid(&svm->vcpu);
2968 return 1;
2969 }
2970
2971 static int iret_interception(struct vcpu_svm *svm)
2972 {
2973 ++svm->vcpu.stat.nmi_window_exits;
2974 clr_intercept(svm, INTERCEPT_IRET);
2975 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2976 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2977 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2978 return 1;
2979 }
2980
2981 static int invlpg_interception(struct vcpu_svm *svm)
2982 {
2983 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2984 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2985
2986 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2987 skip_emulated_instruction(&svm->vcpu);
2988 return 1;
2989 }
2990
2991 static int emulate_on_interception(struct vcpu_svm *svm)
2992 {
2993 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2994 }
2995
2996 static int rdpmc_interception(struct vcpu_svm *svm)
2997 {
2998 int err;
2999
3000 if (!static_cpu_has(X86_FEATURE_NRIPS))
3001 return emulate_on_interception(svm);
3002
3003 err = kvm_rdpmc(&svm->vcpu);
3004 kvm_complete_insn_gp(&svm->vcpu, err);
3005
3006 return 1;
3007 }
3008
3009 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3010 unsigned long val)
3011 {
3012 unsigned long cr0 = svm->vcpu.arch.cr0;
3013 bool ret = false;
3014 u64 intercept;
3015
3016 intercept = svm->nested.intercept;
3017
3018 if (!is_guest_mode(&svm->vcpu) ||
3019 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3020 return false;
3021
3022 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3023 val &= ~SVM_CR0_SELECTIVE_MASK;
3024
3025 if (cr0 ^ val) {
3026 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3027 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3028 }
3029
3030 return ret;
3031 }
3032
3033 #define CR_VALID (1ULL << 63)
3034
3035 static int cr_interception(struct vcpu_svm *svm)
3036 {
3037 int reg, cr;
3038 unsigned long val;
3039 int err;
3040
3041 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3042 return emulate_on_interception(svm);
3043
3044 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3045 return emulate_on_interception(svm);
3046
3047 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3048 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3049 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3050 else
3051 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3052
3053 err = 0;
3054 if (cr >= 16) { /* mov to cr */
3055 cr -= 16;
3056 val = kvm_register_read(&svm->vcpu, reg);
3057 switch (cr) {
3058 case 0:
3059 if (!check_selective_cr0_intercepted(svm, val))
3060 err = kvm_set_cr0(&svm->vcpu, val);
3061 else
3062 return 1;
3063
3064 break;
3065 case 3:
3066 err = kvm_set_cr3(&svm->vcpu, val);
3067 break;
3068 case 4:
3069 err = kvm_set_cr4(&svm->vcpu, val);
3070 break;
3071 case 8:
3072 err = kvm_set_cr8(&svm->vcpu, val);
3073 break;
3074 default:
3075 WARN(1, "unhandled write to CR%d", cr);
3076 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3077 return 1;
3078 }
3079 } else { /* mov from cr */
3080 switch (cr) {
3081 case 0:
3082 val = kvm_read_cr0(&svm->vcpu);
3083 break;
3084 case 2:
3085 val = svm->vcpu.arch.cr2;
3086 break;
3087 case 3:
3088 val = kvm_read_cr3(&svm->vcpu);
3089 break;
3090 case 4:
3091 val = kvm_read_cr4(&svm->vcpu);
3092 break;
3093 case 8:
3094 val = kvm_get_cr8(&svm->vcpu);
3095 break;
3096 default:
3097 WARN(1, "unhandled read from CR%d", cr);
3098 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3099 return 1;
3100 }
3101 kvm_register_write(&svm->vcpu, reg, val);
3102 }
3103 kvm_complete_insn_gp(&svm->vcpu, err);
3104
3105 return 1;
3106 }
3107
3108 static int dr_interception(struct vcpu_svm *svm)
3109 {
3110 int reg, dr;
3111 unsigned long val;
3112
3113 if (svm->vcpu.guest_debug == 0) {
3114 /*
3115 * No more DR vmexits; force a reload of the debug registers
3116 * and reenter on this instruction. The next vmexit will
3117 * retrieve the full state of the debug registers.
3118 */
3119 clr_dr_intercepts(svm);
3120 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3121 return 1;
3122 }
3123
3124 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3125 return emulate_on_interception(svm);
3126
3127 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3128 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3129
3130 if (dr >= 16) { /* mov to DRn */
3131 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3132 return 1;
3133 val = kvm_register_read(&svm->vcpu, reg);
3134 kvm_set_dr(&svm->vcpu, dr - 16, val);
3135 } else {
3136 if (!kvm_require_dr(&svm->vcpu, dr))
3137 return 1;
3138 kvm_get_dr(&svm->vcpu, dr, &val);
3139 kvm_register_write(&svm->vcpu, reg, val);
3140 }
3141
3142 skip_emulated_instruction(&svm->vcpu);
3143
3144 return 1;
3145 }
3146
3147 static int cr8_write_interception(struct vcpu_svm *svm)
3148 {
3149 struct kvm_run *kvm_run = svm->vcpu.run;
3150 int r;
3151
3152 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3153 /* instruction emulation calls kvm_set_cr8() */
3154 r = cr_interception(svm);
3155 if (irqchip_in_kernel(svm->vcpu.kvm))
3156 return r;
3157 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3158 return r;
3159 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3160 return 0;
3161 }
3162
3163 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3164 {
3165 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3166 return vmcb->control.tsc_offset +
3167 svm_scale_tsc(vcpu, host_tsc);
3168 }
3169
3170 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3171 {
3172 struct vcpu_svm *svm = to_svm(vcpu);
3173
3174 switch (msr_info->index) {
3175 case MSR_IA32_TSC: {
3176 msr_info->data = svm->vmcb->control.tsc_offset +
3177 svm_scale_tsc(vcpu, rdtsc());
3178
3179 break;
3180 }
3181 case MSR_STAR:
3182 msr_info->data = svm->vmcb->save.star;
3183 break;
3184 #ifdef CONFIG_X86_64
3185 case MSR_LSTAR:
3186 msr_info->data = svm->vmcb->save.lstar;
3187 break;
3188 case MSR_CSTAR:
3189 msr_info->data = svm->vmcb->save.cstar;
3190 break;
3191 case MSR_KERNEL_GS_BASE:
3192 msr_info->data = svm->vmcb->save.kernel_gs_base;
3193 break;
3194 case MSR_SYSCALL_MASK:
3195 msr_info->data = svm->vmcb->save.sfmask;
3196 break;
3197 #endif
3198 case MSR_IA32_SYSENTER_CS:
3199 msr_info->data = svm->vmcb->save.sysenter_cs;
3200 break;
3201 case MSR_IA32_SYSENTER_EIP:
3202 msr_info->data = svm->sysenter_eip;
3203 break;
3204 case MSR_IA32_SYSENTER_ESP:
3205 msr_info->data = svm->sysenter_esp;
3206 break;
3207 /*
3208 * Nobody will change the following 5 values in the VMCB so we can
3209 * safely return them on rdmsr. They will always be 0 until LBRV is
3210 * implemented.
3211 */
3212 case MSR_IA32_DEBUGCTLMSR:
3213 msr_info->data = svm->vmcb->save.dbgctl;
3214 break;
3215 case MSR_IA32_LASTBRANCHFROMIP:
3216 msr_info->data = svm->vmcb->save.br_from;
3217 break;
3218 case MSR_IA32_LASTBRANCHTOIP:
3219 msr_info->data = svm->vmcb->save.br_to;
3220 break;
3221 case MSR_IA32_LASTINTFROMIP:
3222 msr_info->data = svm->vmcb->save.last_excp_from;
3223 break;
3224 case MSR_IA32_LASTINTTOIP:
3225 msr_info->data = svm->vmcb->save.last_excp_to;
3226 break;
3227 case MSR_VM_HSAVE_PA:
3228 msr_info->data = svm->nested.hsave_msr;
3229 break;
3230 case MSR_VM_CR:
3231 msr_info->data = svm->nested.vm_cr_msr;
3232 break;
3233 case MSR_IA32_UCODE_REV:
3234 msr_info->data = 0x01000065;
3235 break;
3236 default:
3237 return kvm_get_msr_common(vcpu, msr_info);
3238 }
3239 return 0;
3240 }
3241
3242 static int rdmsr_interception(struct vcpu_svm *svm)
3243 {
3244 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3245 struct msr_data msr_info;
3246
3247 msr_info.index = ecx;
3248 msr_info.host_initiated = false;
3249 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3250 trace_kvm_msr_read_ex(ecx);
3251 kvm_inject_gp(&svm->vcpu, 0);
3252 } else {
3253 trace_kvm_msr_read(ecx, msr_info.data);
3254
3255 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3256 msr_info.data & 0xffffffff);
3257 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3258 msr_info.data >> 32);
3259 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3260 skip_emulated_instruction(&svm->vcpu);
3261 }
3262 return 1;
3263 }
3264
3265 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3266 {
3267 struct vcpu_svm *svm = to_svm(vcpu);
3268 int svm_dis, chg_mask;
3269
3270 if (data & ~SVM_VM_CR_VALID_MASK)
3271 return 1;
3272
3273 chg_mask = SVM_VM_CR_VALID_MASK;
3274
3275 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3276 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3277
3278 svm->nested.vm_cr_msr &= ~chg_mask;
3279 svm->nested.vm_cr_msr |= (data & chg_mask);
3280
3281 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3282
3283 /* check for svm_disable while efer.svme is set */
3284 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3285 return 1;
3286
3287 return 0;
3288 }
3289
3290 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3291 {
3292 struct vcpu_svm *svm = to_svm(vcpu);
3293
3294 u32 ecx = msr->index;
3295 u64 data = msr->data;
3296 switch (ecx) {
3297 case MSR_IA32_TSC:
3298 kvm_write_tsc(vcpu, msr);
3299 break;
3300 case MSR_STAR:
3301 svm->vmcb->save.star = data;
3302 break;
3303 #ifdef CONFIG_X86_64
3304 case MSR_LSTAR:
3305 svm->vmcb->save.lstar = data;
3306 break;
3307 case MSR_CSTAR:
3308 svm->vmcb->save.cstar = data;
3309 break;
3310 case MSR_KERNEL_GS_BASE:
3311 svm->vmcb->save.kernel_gs_base = data;
3312 break;
3313 case MSR_SYSCALL_MASK:
3314 svm->vmcb->save.sfmask = data;
3315 break;
3316 #endif
3317 case MSR_IA32_SYSENTER_CS:
3318 svm->vmcb->save.sysenter_cs = data;
3319 break;
3320 case MSR_IA32_SYSENTER_EIP:
3321 svm->sysenter_eip = data;
3322 svm->vmcb->save.sysenter_eip = data;
3323 break;
3324 case MSR_IA32_SYSENTER_ESP:
3325 svm->sysenter_esp = data;
3326 svm->vmcb->save.sysenter_esp = data;
3327 break;
3328 case MSR_IA32_DEBUGCTLMSR:
3329 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3330 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3331 __func__, data);
3332 break;
3333 }
3334 if (data & DEBUGCTL_RESERVED_BITS)
3335 return 1;
3336
3337 svm->vmcb->save.dbgctl = data;
3338 mark_dirty(svm->vmcb, VMCB_LBR);
3339 if (data & (1ULL<<0))
3340 svm_enable_lbrv(svm);
3341 else
3342 svm_disable_lbrv(svm);
3343 break;
3344 case MSR_VM_HSAVE_PA:
3345 svm->nested.hsave_msr = data;
3346 break;
3347 case MSR_VM_CR:
3348 return svm_set_vm_cr(vcpu, data);
3349 case MSR_VM_IGNNE:
3350 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3351 break;
3352 case MSR_IA32_CR_PAT:
3353 if (npt_enabled) {
3354 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3355 return 1;
3356 vcpu->arch.pat = data;
3357 svm_set_guest_pat(svm, &svm->vmcb->save.g_pat);
3358 mark_dirty(svm->vmcb, VMCB_NPT);
3359 break;
3360 }
3361 /* fall through */
3362 default:
3363 return kvm_set_msr_common(vcpu, msr);
3364 }
3365 return 0;
3366 }
3367
3368 static int wrmsr_interception(struct vcpu_svm *svm)
3369 {
3370 struct msr_data msr;
3371 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3372 u64 data = kvm_read_edx_eax(&svm->vcpu);
3373
3374 msr.data = data;
3375 msr.index = ecx;
3376 msr.host_initiated = false;
3377
3378 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3379 if (kvm_set_msr(&svm->vcpu, &msr)) {
3380 trace_kvm_msr_write_ex(ecx, data);
3381 kvm_inject_gp(&svm->vcpu, 0);
3382 } else {
3383 trace_kvm_msr_write(ecx, data);
3384 skip_emulated_instruction(&svm->vcpu);
3385 }
3386 return 1;
3387 }
3388
3389 static int msr_interception(struct vcpu_svm *svm)
3390 {
3391 if (svm->vmcb->control.exit_info_1)
3392 return wrmsr_interception(svm);
3393 else
3394 return rdmsr_interception(svm);
3395 }
3396
3397 static int interrupt_window_interception(struct vcpu_svm *svm)
3398 {
3399 struct kvm_run *kvm_run = svm->vcpu.run;
3400
3401 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3402 svm_clear_vintr(svm);
3403 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3404 mark_dirty(svm->vmcb, VMCB_INTR);
3405 ++svm->vcpu.stat.irq_window_exits;
3406 /*
3407 * If the user space waits to inject interrupts, exit as soon as
3408 * possible
3409 */
3410 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3411 kvm_run->request_interrupt_window &&
3412 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3413 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3414 return 0;
3415 }
3416
3417 return 1;
3418 }
3419
3420 static int pause_interception(struct vcpu_svm *svm)
3421 {
3422 kvm_vcpu_on_spin(&(svm->vcpu));
3423 return 1;
3424 }
3425
3426 static int nop_interception(struct vcpu_svm *svm)
3427 {
3428 skip_emulated_instruction(&(svm->vcpu));
3429 return 1;
3430 }
3431
3432 static int monitor_interception(struct vcpu_svm *svm)
3433 {
3434 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3435 return nop_interception(svm);
3436 }
3437
3438 static int mwait_interception(struct vcpu_svm *svm)
3439 {
3440 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3441 return nop_interception(svm);
3442 }
3443
3444 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3445 [SVM_EXIT_READ_CR0] = cr_interception,
3446 [SVM_EXIT_READ_CR3] = cr_interception,
3447 [SVM_EXIT_READ_CR4] = cr_interception,
3448 [SVM_EXIT_READ_CR8] = cr_interception,
3449 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3450 [SVM_EXIT_WRITE_CR0] = cr_interception,
3451 [SVM_EXIT_WRITE_CR3] = cr_interception,
3452 [SVM_EXIT_WRITE_CR4] = cr_interception,
3453 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3454 [SVM_EXIT_READ_DR0] = dr_interception,
3455 [SVM_EXIT_READ_DR1] = dr_interception,
3456 [SVM_EXIT_READ_DR2] = dr_interception,
3457 [SVM_EXIT_READ_DR3] = dr_interception,
3458 [SVM_EXIT_READ_DR4] = dr_interception,
3459 [SVM_EXIT_READ_DR5] = dr_interception,
3460 [SVM_EXIT_READ_DR6] = dr_interception,
3461 [SVM_EXIT_READ_DR7] = dr_interception,
3462 [SVM_EXIT_WRITE_DR0] = dr_interception,
3463 [SVM_EXIT_WRITE_DR1] = dr_interception,
3464 [SVM_EXIT_WRITE_DR2] = dr_interception,
3465 [SVM_EXIT_WRITE_DR3] = dr_interception,
3466 [SVM_EXIT_WRITE_DR4] = dr_interception,
3467 [SVM_EXIT_WRITE_DR5] = dr_interception,
3468 [SVM_EXIT_WRITE_DR6] = dr_interception,
3469 [SVM_EXIT_WRITE_DR7] = dr_interception,
3470 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3471 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3472 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3473 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3474 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3475 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3476 [SVM_EXIT_INTR] = intr_interception,
3477 [SVM_EXIT_NMI] = nmi_interception,
3478 [SVM_EXIT_SMI] = nop_on_interception,
3479 [SVM_EXIT_INIT] = nop_on_interception,
3480 [SVM_EXIT_VINTR] = interrupt_window_interception,
3481 [SVM_EXIT_RDPMC] = rdpmc_interception,
3482 [SVM_EXIT_CPUID] = cpuid_interception,
3483 [SVM_EXIT_IRET] = iret_interception,
3484 [SVM_EXIT_INVD] = emulate_on_interception,
3485 [SVM_EXIT_PAUSE] = pause_interception,
3486 [SVM_EXIT_HLT] = halt_interception,
3487 [SVM_EXIT_INVLPG] = invlpg_interception,
3488 [SVM_EXIT_INVLPGA] = invlpga_interception,
3489 [SVM_EXIT_IOIO] = io_interception,
3490 [SVM_EXIT_MSR] = msr_interception,
3491 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3492 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3493 [SVM_EXIT_VMRUN] = vmrun_interception,
3494 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3495 [SVM_EXIT_VMLOAD] = vmload_interception,
3496 [SVM_EXIT_VMSAVE] = vmsave_interception,
3497 [SVM_EXIT_STGI] = stgi_interception,
3498 [SVM_EXIT_CLGI] = clgi_interception,
3499 [SVM_EXIT_SKINIT] = skinit_interception,
3500 [SVM_EXIT_WBINVD] = wbinvd_interception,
3501 [SVM_EXIT_MONITOR] = monitor_interception,
3502 [SVM_EXIT_MWAIT] = mwait_interception,
3503 [SVM_EXIT_XSETBV] = xsetbv_interception,
3504 [SVM_EXIT_NPF] = pf_interception,
3505 [SVM_EXIT_RSM] = emulate_on_interception,
3506 };
3507
3508 static void dump_vmcb(struct kvm_vcpu *vcpu)
3509 {
3510 struct vcpu_svm *svm = to_svm(vcpu);
3511 struct vmcb_control_area *control = &svm->vmcb->control;
3512 struct vmcb_save_area *save = &svm->vmcb->save;
3513
3514 pr_err("VMCB Control Area:\n");
3515 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3516 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3517 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3518 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3519 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3520 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3521 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3522 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3523 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3524 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3525 pr_err("%-20s%d\n", "asid:", control->asid);
3526 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3527 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3528 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3529 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3530 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3531 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3532 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3533 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3534 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3535 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3536 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3537 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3538 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3539 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3540 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3541 pr_err("VMCB State Save Area:\n");
3542 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3543 "es:",
3544 save->es.selector, save->es.attrib,
3545 save->es.limit, save->es.base);
3546 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3547 "cs:",
3548 save->cs.selector, save->cs.attrib,
3549 save->cs.limit, save->cs.base);
3550 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3551 "ss:",
3552 save->ss.selector, save->ss.attrib,
3553 save->ss.limit, save->ss.base);
3554 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3555 "ds:",
3556 save->ds.selector, save->ds.attrib,
3557 save->ds.limit, save->ds.base);
3558 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3559 "fs:",
3560 save->fs.selector, save->fs.attrib,
3561 save->fs.limit, save->fs.base);
3562 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3563 "gs:",
3564 save->gs.selector, save->gs.attrib,
3565 save->gs.limit, save->gs.base);
3566 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3567 "gdtr:",
3568 save->gdtr.selector, save->gdtr.attrib,
3569 save->gdtr.limit, save->gdtr.base);
3570 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3571 "ldtr:",
3572 save->ldtr.selector, save->ldtr.attrib,
3573 save->ldtr.limit, save->ldtr.base);
3574 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3575 "idtr:",
3576 save->idtr.selector, save->idtr.attrib,
3577 save->idtr.limit, save->idtr.base);
3578 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3579 "tr:",
3580 save->tr.selector, save->tr.attrib,
3581 save->tr.limit, save->tr.base);
3582 pr_err("cpl: %d efer: %016llx\n",
3583 save->cpl, save->efer);
3584 pr_err("%-15s %016llx %-13s %016llx\n",
3585 "cr0:", save->cr0, "cr2:", save->cr2);
3586 pr_err("%-15s %016llx %-13s %016llx\n",
3587 "cr3:", save->cr3, "cr4:", save->cr4);
3588 pr_err("%-15s %016llx %-13s %016llx\n",
3589 "dr6:", save->dr6, "dr7:", save->dr7);
3590 pr_err("%-15s %016llx %-13s %016llx\n",
3591 "rip:", save->rip, "rflags:", save->rflags);
3592 pr_err("%-15s %016llx %-13s %016llx\n",
3593 "rsp:", save->rsp, "rax:", save->rax);
3594 pr_err("%-15s %016llx %-13s %016llx\n",
3595 "star:", save->star, "lstar:", save->lstar);
3596 pr_err("%-15s %016llx %-13s %016llx\n",
3597 "cstar:", save->cstar, "sfmask:", save->sfmask);
3598 pr_err("%-15s %016llx %-13s %016llx\n",
3599 "kernel_gs_base:", save->kernel_gs_base,
3600 "sysenter_cs:", save->sysenter_cs);
3601 pr_err("%-15s %016llx %-13s %016llx\n",
3602 "sysenter_esp:", save->sysenter_esp,
3603 "sysenter_eip:", save->sysenter_eip);
3604 pr_err("%-15s %016llx %-13s %016llx\n",
3605 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3606 pr_err("%-15s %016llx %-13s %016llx\n",
3607 "br_from:", save->br_from, "br_to:", save->br_to);
3608 pr_err("%-15s %016llx %-13s %016llx\n",
3609 "excp_from:", save->last_excp_from,
3610 "excp_to:", save->last_excp_to);
3611 }
3612
3613 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3614 {
3615 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3616
3617 *info1 = control->exit_info_1;
3618 *info2 = control->exit_info_2;
3619 }
3620
3621 static int handle_exit(struct kvm_vcpu *vcpu)
3622 {
3623 struct vcpu_svm *svm = to_svm(vcpu);
3624 struct kvm_run *kvm_run = vcpu->run;
3625 u32 exit_code = svm->vmcb->control.exit_code;
3626
3627 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3628 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3629 if (npt_enabled)
3630 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3631
3632 if (unlikely(svm->nested.exit_required)) {
3633 nested_svm_vmexit(svm);
3634 svm->nested.exit_required = false;
3635
3636 return 1;
3637 }
3638
3639 if (is_guest_mode(vcpu)) {
3640 int vmexit;
3641
3642 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3643 svm->vmcb->control.exit_info_1,
3644 svm->vmcb->control.exit_info_2,
3645 svm->vmcb->control.exit_int_info,
3646 svm->vmcb->control.exit_int_info_err,
3647 KVM_ISA_SVM);
3648
3649 vmexit = nested_svm_exit_special(svm);
3650
3651 if (vmexit == NESTED_EXIT_CONTINUE)
3652 vmexit = nested_svm_exit_handled(svm);
3653
3654 if (vmexit == NESTED_EXIT_DONE)
3655 return 1;
3656 }
3657
3658 svm_complete_interrupts(svm);
3659
3660 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3661 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3662 kvm_run->fail_entry.hardware_entry_failure_reason
3663 = svm->vmcb->control.exit_code;
3664 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3665 dump_vmcb(vcpu);
3666 return 0;
3667 }
3668
3669 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3670 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3671 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3672 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3673 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3674 "exit_code 0x%x\n",
3675 __func__, svm->vmcb->control.exit_int_info,
3676 exit_code);
3677
3678 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3679 || !svm_exit_handlers[exit_code]) {
3680 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3681 kvm_queue_exception(vcpu, UD_VECTOR);
3682 return 1;
3683 }
3684
3685 return svm_exit_handlers[exit_code](svm);
3686 }
3687
3688 static void reload_tss(struct kvm_vcpu *vcpu)
3689 {
3690 int cpu = raw_smp_processor_id();
3691
3692 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3693 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3694 load_TR_desc();
3695 }
3696
3697 static void pre_svm_run(struct vcpu_svm *svm)
3698 {
3699 int cpu = raw_smp_processor_id();
3700
3701 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3702
3703 /* FIXME: handle wraparound of asid_generation */
3704 if (svm->asid_generation != sd->asid_generation)
3705 new_asid(svm, sd);
3706 }
3707
3708 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3709 {
3710 struct vcpu_svm *svm = to_svm(vcpu);
3711
3712 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3713 vcpu->arch.hflags |= HF_NMI_MASK;
3714 set_intercept(svm, INTERCEPT_IRET);
3715 ++vcpu->stat.nmi_injections;
3716 }
3717
3718 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3719 {
3720 struct vmcb_control_area *control;
3721
3722 control = &svm->vmcb->control;
3723 control->int_vector = irq;
3724 control->int_ctl &= ~V_INTR_PRIO_MASK;
3725 control->int_ctl |= V_IRQ_MASK |
3726 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3727 mark_dirty(svm->vmcb, VMCB_INTR);
3728 }
3729
3730 static void svm_set_irq(struct kvm_vcpu *vcpu)
3731 {
3732 struct vcpu_svm *svm = to_svm(vcpu);
3733
3734 BUG_ON(!(gif_set(svm)));
3735
3736 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3737 ++vcpu->stat.irq_injections;
3738
3739 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3740 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3741 }
3742
3743 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3744 {
3745 struct vcpu_svm *svm = to_svm(vcpu);
3746
3747 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3748 return;
3749
3750 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3751
3752 if (irr == -1)
3753 return;
3754
3755 if (tpr >= irr)
3756 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3757 }
3758
3759 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3760 {
3761 return;
3762 }
3763
3764 static int svm_vm_has_apicv(struct kvm *kvm)
3765 {
3766 return 0;
3767 }
3768
3769 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3770 {
3771 return;
3772 }
3773
3774 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3775 {
3776 return;
3777 }
3778
3779 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3780 {
3781 struct vcpu_svm *svm = to_svm(vcpu);
3782 struct vmcb *vmcb = svm->vmcb;
3783 int ret;
3784 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3785 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3786 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3787
3788 return ret;
3789 }
3790
3791 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3792 {
3793 struct vcpu_svm *svm = to_svm(vcpu);
3794
3795 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3796 }
3797
3798 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3799 {
3800 struct vcpu_svm *svm = to_svm(vcpu);
3801
3802 if (masked) {
3803 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3804 set_intercept(svm, INTERCEPT_IRET);
3805 } else {
3806 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3807 clr_intercept(svm, INTERCEPT_IRET);
3808 }
3809 }
3810
3811 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3812 {
3813 struct vcpu_svm *svm = to_svm(vcpu);
3814 struct vmcb *vmcb = svm->vmcb;
3815 int ret;
3816
3817 if (!gif_set(svm) ||
3818 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3819 return 0;
3820
3821 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3822
3823 if (is_guest_mode(vcpu))
3824 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3825
3826 return ret;
3827 }
3828
3829 static void enable_irq_window(struct kvm_vcpu *vcpu)
3830 {
3831 struct vcpu_svm *svm = to_svm(vcpu);
3832
3833 /*
3834 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3835 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3836 * get that intercept, this function will be called again though and
3837 * we'll get the vintr intercept.
3838 */
3839 if (gif_set(svm) && nested_svm_intr(svm)) {
3840 svm_set_vintr(svm);
3841 svm_inject_irq(svm, 0x0);
3842 }
3843 }
3844
3845 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3846 {
3847 struct vcpu_svm *svm = to_svm(vcpu);
3848
3849 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3850 == HF_NMI_MASK)
3851 return; /* IRET will cause a vm exit */
3852
3853 /*
3854 * Something prevents NMI from been injected. Single step over possible
3855 * problem (IRET or exception injection or interrupt shadow)
3856 */
3857 svm->nmi_singlestep = true;
3858 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3859 update_db_bp_intercept(vcpu);
3860 }
3861
3862 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3863 {
3864 return 0;
3865 }
3866
3867 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3868 {
3869 struct vcpu_svm *svm = to_svm(vcpu);
3870
3871 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3872 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3873 else
3874 svm->asid_generation--;
3875 }
3876
3877 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3878 {
3879 }
3880
3881 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3882 {
3883 struct vcpu_svm *svm = to_svm(vcpu);
3884
3885 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3886 return;
3887
3888 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3889 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3890 kvm_set_cr8(vcpu, cr8);
3891 }
3892 }
3893
3894 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3895 {
3896 struct vcpu_svm *svm = to_svm(vcpu);
3897 u64 cr8;
3898
3899 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3900 return;
3901
3902 cr8 = kvm_get_cr8(vcpu);
3903 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3904 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3905 }
3906
3907 static void svm_complete_interrupts(struct vcpu_svm *svm)
3908 {
3909 u8 vector;
3910 int type;
3911 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3912 unsigned int3_injected = svm->int3_injected;
3913
3914 svm->int3_injected = 0;
3915
3916 /*
3917 * If we've made progress since setting HF_IRET_MASK, we've
3918 * executed an IRET and can allow NMI injection.
3919 */
3920 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3921 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3922 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3923 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3924 }
3925
3926 svm->vcpu.arch.nmi_injected = false;
3927 kvm_clear_exception_queue(&svm->vcpu);
3928 kvm_clear_interrupt_queue(&svm->vcpu);
3929
3930 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3931 return;
3932
3933 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3934
3935 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3936 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3937
3938 switch (type) {
3939 case SVM_EXITINTINFO_TYPE_NMI:
3940 svm->vcpu.arch.nmi_injected = true;
3941 break;
3942 case SVM_EXITINTINFO_TYPE_EXEPT:
3943 /*
3944 * In case of software exceptions, do not reinject the vector,
3945 * but re-execute the instruction instead. Rewind RIP first
3946 * if we emulated INT3 before.
3947 */
3948 if (kvm_exception_is_soft(vector)) {
3949 if (vector == BP_VECTOR && int3_injected &&
3950 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3951 kvm_rip_write(&svm->vcpu,
3952 kvm_rip_read(&svm->vcpu) -
3953 int3_injected);
3954 break;
3955 }
3956 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3957 u32 err = svm->vmcb->control.exit_int_info_err;
3958 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3959
3960 } else
3961 kvm_requeue_exception(&svm->vcpu, vector);
3962 break;
3963 case SVM_EXITINTINFO_TYPE_INTR:
3964 kvm_queue_interrupt(&svm->vcpu, vector, false);
3965 break;
3966 default:
3967 break;
3968 }
3969 }
3970
3971 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3972 {
3973 struct vcpu_svm *svm = to_svm(vcpu);
3974 struct vmcb_control_area *control = &svm->vmcb->control;
3975
3976 control->exit_int_info = control->event_inj;
3977 control->exit_int_info_err = control->event_inj_err;
3978 control->event_inj = 0;
3979 svm_complete_interrupts(svm);
3980 }
3981
3982 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3983 {
3984 struct vcpu_svm *svm = to_svm(vcpu);
3985
3986 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3987 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3988 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3989
3990 /*
3991 * A vmexit emulation is required before the vcpu can be executed
3992 * again.
3993 */
3994 if (unlikely(svm->nested.exit_required))
3995 return;
3996
3997 pre_svm_run(svm);
3998
3999 sync_lapic_to_cr8(vcpu);
4000
4001 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4002
4003 clgi();
4004
4005 local_irq_enable();
4006
4007 asm volatile (
4008 "push %%" _ASM_BP "; \n\t"
4009 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4010 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4011 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4012 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4013 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4014 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4015 #ifdef CONFIG_X86_64
4016 "mov %c[r8](%[svm]), %%r8 \n\t"
4017 "mov %c[r9](%[svm]), %%r9 \n\t"
4018 "mov %c[r10](%[svm]), %%r10 \n\t"
4019 "mov %c[r11](%[svm]), %%r11 \n\t"
4020 "mov %c[r12](%[svm]), %%r12 \n\t"
4021 "mov %c[r13](%[svm]), %%r13 \n\t"
4022 "mov %c[r14](%[svm]), %%r14 \n\t"
4023 "mov %c[r15](%[svm]), %%r15 \n\t"
4024 #endif
4025
4026 /* Enter guest mode */
4027 "push %%" _ASM_AX " \n\t"
4028 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4029 __ex(SVM_VMLOAD) "\n\t"
4030 __ex(SVM_VMRUN) "\n\t"
4031 __ex(SVM_VMSAVE) "\n\t"
4032 "pop %%" _ASM_AX " \n\t"
4033
4034 /* Save guest registers, load host registers */
4035 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4036 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4037 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4038 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4039 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4040 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4041 #ifdef CONFIG_X86_64
4042 "mov %%r8, %c[r8](%[svm]) \n\t"
4043 "mov %%r9, %c[r9](%[svm]) \n\t"
4044 "mov %%r10, %c[r10](%[svm]) \n\t"
4045 "mov %%r11, %c[r11](%[svm]) \n\t"
4046 "mov %%r12, %c[r12](%[svm]) \n\t"
4047 "mov %%r13, %c[r13](%[svm]) \n\t"
4048 "mov %%r14, %c[r14](%[svm]) \n\t"
4049 "mov %%r15, %c[r15](%[svm]) \n\t"
4050 #endif
4051 "pop %%" _ASM_BP
4052 :
4053 : [svm]"a"(svm),
4054 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4055 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4056 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4057 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4058 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4059 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4060 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4061 #ifdef CONFIG_X86_64
4062 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4063 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4064 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4065 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4066 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4067 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4068 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4069 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4070 #endif
4071 : "cc", "memory"
4072 #ifdef CONFIG_X86_64
4073 , "rbx", "rcx", "rdx", "rsi", "rdi"
4074 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4075 #else
4076 , "ebx", "ecx", "edx", "esi", "edi"
4077 #endif
4078 );
4079
4080 #ifdef CONFIG_X86_64
4081 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4082 #else
4083 loadsegment(fs, svm->host.fs);
4084 #ifndef CONFIG_X86_32_LAZY_GS
4085 loadsegment(gs, svm->host.gs);
4086 #endif
4087 #endif
4088
4089 reload_tss(vcpu);
4090
4091 local_irq_disable();
4092
4093 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4094 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4095 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4096 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4097
4098 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
4099
4100 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4101 kvm_before_handle_nmi(&svm->vcpu);
4102
4103 stgi();
4104
4105 /* Any pending NMI will happen here */
4106
4107 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4108 kvm_after_handle_nmi(&svm->vcpu);
4109
4110 sync_cr8_to_lapic(vcpu);
4111
4112 svm->next_rip = 0;
4113
4114 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4115
4116 /* if exit due to PF check for async PF */
4117 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4118 svm->apf_reason = kvm_read_and_reset_pf_reason();
4119
4120 if (npt_enabled) {
4121 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4122 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4123 }
4124
4125 /*
4126 * We need to handle MC intercepts here before the vcpu has a chance to
4127 * change the physical cpu
4128 */
4129 if (unlikely(svm->vmcb->control.exit_code ==
4130 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4131 svm_handle_mce(svm);
4132
4133 mark_all_clean(svm->vmcb);
4134 }
4135
4136 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4137 {
4138 struct vcpu_svm *svm = to_svm(vcpu);
4139
4140 svm->vmcb->save.cr3 = root;
4141 mark_dirty(svm->vmcb, VMCB_CR);
4142 svm_flush_tlb(vcpu);
4143 }
4144
4145 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4146 {
4147 struct vcpu_svm *svm = to_svm(vcpu);
4148
4149 svm->vmcb->control.nested_cr3 = root;
4150 mark_dirty(svm->vmcb, VMCB_NPT);
4151
4152 /* Also sync guest cr3 here in case we live migrate */
4153 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4154 mark_dirty(svm->vmcb, VMCB_CR);
4155
4156 svm_flush_tlb(vcpu);
4157 }
4158
4159 static int is_disabled(void)
4160 {
4161 u64 vm_cr;
4162
4163 rdmsrl(MSR_VM_CR, vm_cr);
4164 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4165 return 1;
4166
4167 return 0;
4168 }
4169
4170 static void
4171 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4172 {
4173 /*
4174 * Patch in the VMMCALL instruction:
4175 */
4176 hypercall[0] = 0x0f;
4177 hypercall[1] = 0x01;
4178 hypercall[2] = 0xd9;
4179 }
4180
4181 static void svm_check_processor_compat(void *rtn)
4182 {
4183 *(int *)rtn = 0;
4184 }
4185
4186 static bool svm_cpu_has_accelerated_tpr(void)
4187 {
4188 return false;
4189 }
4190
4191 static bool svm_has_high_real_mode_segbase(void)
4192 {
4193 return true;
4194 }
4195
4196 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4197 {
4198 }
4199
4200 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4201 {
4202 switch (func) {
4203 case 0x80000001:
4204 if (nested)
4205 entry->ecx |= (1 << 2); /* Set SVM bit */
4206 break;
4207 case 0x8000000A:
4208 entry->eax = 1; /* SVM revision 1 */
4209 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4210 ASID emulation to nested SVM */
4211 entry->ecx = 0; /* Reserved */
4212 entry->edx = 0; /* Per default do not support any
4213 additional features */
4214
4215 /* Support next_rip if host supports it */
4216 if (boot_cpu_has(X86_FEATURE_NRIPS))
4217 entry->edx |= SVM_FEATURE_NRIP;
4218
4219 /* Support NPT for the guest if enabled */
4220 if (npt_enabled)
4221 entry->edx |= SVM_FEATURE_NPT;
4222
4223 break;
4224 }
4225 }
4226
4227 static int svm_get_lpage_level(void)
4228 {
4229 return PT_PDPE_LEVEL;
4230 }
4231
4232 static bool svm_rdtscp_supported(void)
4233 {
4234 return false;
4235 }
4236
4237 static bool svm_invpcid_supported(void)
4238 {
4239 return false;
4240 }
4241
4242 static bool svm_mpx_supported(void)
4243 {
4244 return false;
4245 }
4246
4247 static bool svm_xsaves_supported(void)
4248 {
4249 return false;
4250 }
4251
4252 static bool svm_has_wbinvd_exit(void)
4253 {
4254 return true;
4255 }
4256
4257 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4258 {
4259 struct vcpu_svm *svm = to_svm(vcpu);
4260
4261 set_exception_intercept(svm, NM_VECTOR);
4262 update_cr0_intercept(svm);
4263 }
4264
4265 #define PRE_EX(exit) { .exit_code = (exit), \
4266 .stage = X86_ICPT_PRE_EXCEPT, }
4267 #define POST_EX(exit) { .exit_code = (exit), \
4268 .stage = X86_ICPT_POST_EXCEPT, }
4269 #define POST_MEM(exit) { .exit_code = (exit), \
4270 .stage = X86_ICPT_POST_MEMACCESS, }
4271
4272 static const struct __x86_intercept {
4273 u32 exit_code;
4274 enum x86_intercept_stage stage;
4275 } x86_intercept_map[] = {
4276 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4277 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4278 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4279 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4280 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4281 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4282 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4283 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4284 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4285 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4286 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4287 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4288 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4289 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4290 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4291 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4292 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4293 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4294 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4295 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4296 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4297 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4298 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4299 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4300 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4301 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4302 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4303 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4304 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4305 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4306 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4307 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4308 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4309 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4310 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4311 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4312 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4313 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4314 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4315 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4316 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4317 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4318 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4319 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4320 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4321 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4322 };
4323
4324 #undef PRE_EX
4325 #undef POST_EX
4326 #undef POST_MEM
4327
4328 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4329 struct x86_instruction_info *info,
4330 enum x86_intercept_stage stage)
4331 {
4332 struct vcpu_svm *svm = to_svm(vcpu);
4333 int vmexit, ret = X86EMUL_CONTINUE;
4334 struct __x86_intercept icpt_info;
4335 struct vmcb *vmcb = svm->vmcb;
4336
4337 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4338 goto out;
4339
4340 icpt_info = x86_intercept_map[info->intercept];
4341
4342 if (stage != icpt_info.stage)
4343 goto out;
4344
4345 switch (icpt_info.exit_code) {
4346 case SVM_EXIT_READ_CR0:
4347 if (info->intercept == x86_intercept_cr_read)
4348 icpt_info.exit_code += info->modrm_reg;
4349 break;
4350 case SVM_EXIT_WRITE_CR0: {
4351 unsigned long cr0, val;
4352 u64 intercept;
4353
4354 if (info->intercept == x86_intercept_cr_write)
4355 icpt_info.exit_code += info->modrm_reg;
4356
4357 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4358 info->intercept == x86_intercept_clts)
4359 break;
4360
4361 intercept = svm->nested.intercept;
4362
4363 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4364 break;
4365
4366 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4367 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4368
4369 if (info->intercept == x86_intercept_lmsw) {
4370 cr0 &= 0xfUL;
4371 val &= 0xfUL;
4372 /* lmsw can't clear PE - catch this here */
4373 if (cr0 & X86_CR0_PE)
4374 val |= X86_CR0_PE;
4375 }
4376
4377 if (cr0 ^ val)
4378 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4379
4380 break;
4381 }
4382 case SVM_EXIT_READ_DR0:
4383 case SVM_EXIT_WRITE_DR0:
4384 icpt_info.exit_code += info->modrm_reg;
4385 break;
4386 case SVM_EXIT_MSR:
4387 if (info->intercept == x86_intercept_wrmsr)
4388 vmcb->control.exit_info_1 = 1;
4389 else
4390 vmcb->control.exit_info_1 = 0;
4391 break;
4392 case SVM_EXIT_PAUSE:
4393 /*
4394 * We get this for NOP only, but pause
4395 * is rep not, check this here
4396 */
4397 if (info->rep_prefix != REPE_PREFIX)
4398 goto out;
4399 case SVM_EXIT_IOIO: {
4400 u64 exit_info;
4401 u32 bytes;
4402
4403 if (info->intercept == x86_intercept_in ||
4404 info->intercept == x86_intercept_ins) {
4405 exit_info = ((info->src_val & 0xffff) << 16) |
4406 SVM_IOIO_TYPE_MASK;
4407 bytes = info->dst_bytes;
4408 } else {
4409 exit_info = (info->dst_val & 0xffff) << 16;
4410 bytes = info->src_bytes;
4411 }
4412
4413 if (info->intercept == x86_intercept_outs ||
4414 info->intercept == x86_intercept_ins)
4415 exit_info |= SVM_IOIO_STR_MASK;
4416
4417 if (info->rep_prefix)
4418 exit_info |= SVM_IOIO_REP_MASK;
4419
4420 bytes = min(bytes, 4u);
4421
4422 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4423
4424 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4425
4426 vmcb->control.exit_info_1 = exit_info;
4427 vmcb->control.exit_info_2 = info->next_rip;
4428
4429 break;
4430 }
4431 default:
4432 break;
4433 }
4434
4435 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4436 if (static_cpu_has(X86_FEATURE_NRIPS))
4437 vmcb->control.next_rip = info->next_rip;
4438 vmcb->control.exit_code = icpt_info.exit_code;
4439 vmexit = nested_svm_exit_handled(svm);
4440
4441 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4442 : X86EMUL_CONTINUE;
4443
4444 out:
4445 return ret;
4446 }
4447
4448 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4449 {
4450 local_irq_enable();
4451 }
4452
4453 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4454 {
4455 }
4456
4457 static struct kvm_x86_ops svm_x86_ops = {
4458 .cpu_has_kvm_support = has_svm,
4459 .disabled_by_bios = is_disabled,
4460 .hardware_setup = svm_hardware_setup,
4461 .hardware_unsetup = svm_hardware_unsetup,
4462 .check_processor_compatibility = svm_check_processor_compat,
4463 .hardware_enable = svm_hardware_enable,
4464 .hardware_disable = svm_hardware_disable,
4465 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4466 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4467
4468 .vcpu_create = svm_create_vcpu,
4469 .vcpu_free = svm_free_vcpu,
4470 .vcpu_reset = svm_vcpu_reset,
4471
4472 .prepare_guest_switch = svm_prepare_guest_switch,
4473 .vcpu_load = svm_vcpu_load,
4474 .vcpu_put = svm_vcpu_put,
4475
4476 .update_db_bp_intercept = update_db_bp_intercept,
4477 .get_msr = svm_get_msr,
4478 .set_msr = svm_set_msr,
4479 .get_segment_base = svm_get_segment_base,
4480 .get_segment = svm_get_segment,
4481 .set_segment = svm_set_segment,
4482 .get_cpl = svm_get_cpl,
4483 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4484 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4485 .decache_cr3 = svm_decache_cr3,
4486 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4487 .set_cr0 = svm_set_cr0,
4488 .set_cr3 = svm_set_cr3,
4489 .set_cr4 = svm_set_cr4,
4490 .set_efer = svm_set_efer,
4491 .get_idt = svm_get_idt,
4492 .set_idt = svm_set_idt,
4493 .get_gdt = svm_get_gdt,
4494 .set_gdt = svm_set_gdt,
4495 .get_dr6 = svm_get_dr6,
4496 .set_dr6 = svm_set_dr6,
4497 .set_dr7 = svm_set_dr7,
4498 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4499 .cache_reg = svm_cache_reg,
4500 .get_rflags = svm_get_rflags,
4501 .set_rflags = svm_set_rflags,
4502 .fpu_activate = svm_fpu_activate,
4503 .fpu_deactivate = svm_fpu_deactivate,
4504
4505 .tlb_flush = svm_flush_tlb,
4506
4507 .run = svm_vcpu_run,
4508 .handle_exit = handle_exit,
4509 .skip_emulated_instruction = skip_emulated_instruction,
4510 .set_interrupt_shadow = svm_set_interrupt_shadow,
4511 .get_interrupt_shadow = svm_get_interrupt_shadow,
4512 .patch_hypercall = svm_patch_hypercall,
4513 .set_irq = svm_set_irq,
4514 .set_nmi = svm_inject_nmi,
4515 .queue_exception = svm_queue_exception,
4516 .cancel_injection = svm_cancel_injection,
4517 .interrupt_allowed = svm_interrupt_allowed,
4518 .nmi_allowed = svm_nmi_allowed,
4519 .get_nmi_mask = svm_get_nmi_mask,
4520 .set_nmi_mask = svm_set_nmi_mask,
4521 .enable_nmi_window = enable_nmi_window,
4522 .enable_irq_window = enable_irq_window,
4523 .update_cr8_intercept = update_cr8_intercept,
4524 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4525 .vm_has_apicv = svm_vm_has_apicv,
4526 .load_eoi_exitmap = svm_load_eoi_exitmap,
4527 .sync_pir_to_irr = svm_sync_pir_to_irr,
4528
4529 .set_tss_addr = svm_set_tss_addr,
4530 .get_tdp_level = get_npt_level,
4531 .get_mt_mask = svm_get_mt_mask,
4532
4533 .get_exit_info = svm_get_exit_info,
4534
4535 .get_lpage_level = svm_get_lpage_level,
4536
4537 .cpuid_update = svm_cpuid_update,
4538
4539 .rdtscp_supported = svm_rdtscp_supported,
4540 .invpcid_supported = svm_invpcid_supported,
4541 .mpx_supported = svm_mpx_supported,
4542 .xsaves_supported = svm_xsaves_supported,
4543
4544 .set_supported_cpuid = svm_set_supported_cpuid,
4545
4546 .has_wbinvd_exit = svm_has_wbinvd_exit,
4547
4548 .set_tsc_khz = svm_set_tsc_khz,
4549 .read_tsc_offset = svm_read_tsc_offset,
4550 .write_tsc_offset = svm_write_tsc_offset,
4551 .adjust_tsc_offset = svm_adjust_tsc_offset,
4552 .compute_tsc_offset = svm_compute_tsc_offset,
4553 .read_l1_tsc = svm_read_l1_tsc,
4554
4555 .set_tdp_cr3 = set_tdp_cr3,
4556
4557 .check_intercept = svm_check_intercept,
4558 .handle_external_intr = svm_handle_external_intr,
4559
4560 .sched_in = svm_sched_in,
4561
4562 .pmu_ops = &amd_pmu_ops,
4563 };
4564
4565 static int __init svm_init(void)
4566 {
4567 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4568 __alignof__(struct vcpu_svm), THIS_MODULE);
4569 }
4570
4571 static void __exit svm_exit(void)
4572 {
4573 kvm_exit();
4574 }
4575
4576 module_init(svm_init)
4577 module_exit(svm_exit)
Linux kernel - Deliverables
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