2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
35 #include <asm/virtext.h>
38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40 MODULE_AUTHOR("Qumranet");
41 MODULE_LICENSE("GPL");
43 #define IOPM_ALLOC_ORDER 2
44 #define MSRPM_ALLOC_ORDER 1
46 #define SEG_TYPE_LDT 2
47 #define SEG_TYPE_BUSY_TSS16 3
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_FEATURE_SVML (1 << 2)
52 #define SVM_FEATURE_NRIP (1 << 3)
53 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61 static bool erratum_383_found __read_mostly
;
63 static const u32 host_save_user_msrs
[] = {
65 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
68 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81 /* These are the merged vectors */
84 /* gpa pointers to the real vectors */
88 /* A VMEXIT is required but not yet emulated */
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
95 unsigned long vmexit_rip
;
96 unsigned long vmexit_rsp
;
97 unsigned long vmexit_rax
;
99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read
;
101 u16 intercept_cr_write
;
102 u16 intercept_dr_read
;
103 u16 intercept_dr_write
;
104 u32 intercept_exceptions
;
107 /* Nested Paging related state */
111 #define MSRPM_OFFSETS 16
112 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
115 struct kvm_vcpu vcpu
;
117 unsigned long vmcb_pa
;
118 struct svm_cpu_data
*svm_data
;
119 uint64_t asid_generation
;
120 uint64_t sysenter_esp
;
121 uint64_t sysenter_eip
;
125 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
130 struct nested_state nested
;
134 unsigned int3_injected
;
135 unsigned long int3_rip
;
138 #define MSR_INVALID 0xffffffffU
140 static struct svm_direct_access_msrs
{
141 u32 index
; /* Index of the MSR */
142 bool always
; /* True if intercept is always on */
143 } direct_access_msrs
[] = {
144 { .index
= MSR_STAR
, .always
= true },
145 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
147 { .index
= MSR_GS_BASE
, .always
= true },
148 { .index
= MSR_FS_BASE
, .always
= true },
149 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
150 { .index
= MSR_LSTAR
, .always
= true },
151 { .index
= MSR_CSTAR
, .always
= true },
152 { .index
= MSR_SYSCALL_MASK
, .always
= true },
154 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
155 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
156 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
157 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
158 { .index
= MSR_INVALID
, .always
= false },
161 /* enable NPT for AMD64 and X86 with PAE */
162 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
163 static bool npt_enabled
= true;
165 static bool npt_enabled
;
169 module_param(npt
, int, S_IRUGO
);
171 static int nested
= 1;
172 module_param(nested
, int, S_IRUGO
);
174 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
175 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
177 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
178 static int nested_svm_intercept(struct vcpu_svm
*svm
);
179 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
180 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
181 bool has_error_code
, u32 error_code
);
183 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
185 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
188 static inline bool is_nested(struct vcpu_svm
*svm
)
190 return svm
->nested
.vmcb
;
193 static inline void enable_gif(struct vcpu_svm
*svm
)
195 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
198 static inline void disable_gif(struct vcpu_svm
*svm
)
200 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
203 static inline bool gif_set(struct vcpu_svm
*svm
)
205 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
208 static unsigned long iopm_base
;
210 struct kvm_ldttss_desc
{
213 unsigned base1
:8, type
:5, dpl
:2, p
:1;
214 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
217 } __attribute__((packed
));
219 struct svm_cpu_data
{
225 struct kvm_ldttss_desc
*tss_desc
;
227 struct page
*save_area
;
230 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
231 static uint32_t svm_features
;
233 struct svm_init_data
{
238 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
240 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
241 #define MSRS_RANGE_SIZE 2048
242 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
244 static u32
svm_msrpm_offset(u32 msr
)
249 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
250 if (msr
< msrpm_ranges
[i
] ||
251 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
254 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
255 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
257 /* Now we have the u8 offset - but need the u32 offset */
261 /* MSR not in any range */
265 #define MAX_INST_SIZE 15
267 static inline u32
svm_has(u32 feat
)
269 return svm_features
& feat
;
272 static inline void clgi(void)
274 asm volatile (__ex(SVM_CLGI
));
277 static inline void stgi(void)
279 asm volatile (__ex(SVM_STGI
));
282 static inline void invlpga(unsigned long addr
, u32 asid
)
284 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
287 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
289 to_svm(vcpu
)->asid_generation
--;
292 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
294 force_new_asid(vcpu
);
297 static int get_npt_level(void)
300 return PT64_ROOT_LEVEL
;
302 return PT32E_ROOT_LEVEL
;
306 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
308 vcpu
->arch
.efer
= efer
;
309 if (!npt_enabled
&& !(efer
& EFER_LMA
))
312 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
315 static int is_external_interrupt(u32 info
)
317 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
318 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
321 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
323 struct vcpu_svm
*svm
= to_svm(vcpu
);
326 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
327 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
331 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
333 struct vcpu_svm
*svm
= to_svm(vcpu
);
336 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
338 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
342 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
344 struct vcpu_svm
*svm
= to_svm(vcpu
);
346 if (svm
->vmcb
->control
.next_rip
!= 0)
347 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
349 if (!svm
->next_rip
) {
350 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
352 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
355 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
356 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
357 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
359 kvm_rip_write(vcpu
, svm
->next_rip
);
360 svm_set_interrupt_shadow(vcpu
, 0);
363 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
364 bool has_error_code
, u32 error_code
,
367 struct vcpu_svm
*svm
= to_svm(vcpu
);
370 * If we are within a nested VM we'd better #VMEXIT and let the guest
371 * handle the exception
374 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
377 if (nr
== BP_VECTOR
&& !svm_has(SVM_FEATURE_NRIP
)) {
378 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
381 * For guest debugging where we have to reinject #BP if some
382 * INT3 is guest-owned:
383 * Emulate nRIP by moving RIP forward. Will fail if injection
384 * raises a fault that is not intercepted. Still better than
385 * failing in all cases.
387 skip_emulated_instruction(&svm
->vcpu
);
388 rip
= kvm_rip_read(&svm
->vcpu
);
389 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
390 svm
->int3_injected
= rip
- old_rip
;
393 svm
->vmcb
->control
.event_inj
= nr
395 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
396 | SVM_EVTINJ_TYPE_EXEPT
;
397 svm
->vmcb
->control
.event_inj_err
= error_code
;
400 static void svm_init_erratum_383(void)
406 if (!cpu_has_amd_erratum(amd_erratum_383
))
409 /* Use _safe variants to not break nested virtualization */
410 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
416 low
= lower_32_bits(val
);
417 high
= upper_32_bits(val
);
419 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
421 erratum_383_found
= true;
424 static int has_svm(void)
428 if (!cpu_has_svm(&msg
)) {
429 printk(KERN_INFO
"has_svm: %s\n", msg
);
436 static void svm_hardware_disable(void *garbage
)
441 static int svm_hardware_enable(void *garbage
)
444 struct svm_cpu_data
*sd
;
446 struct desc_ptr gdt_descr
;
447 struct desc_struct
*gdt
;
448 int me
= raw_smp_processor_id();
450 rdmsrl(MSR_EFER
, efer
);
451 if (efer
& EFER_SVME
)
455 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
459 sd
= per_cpu(svm_data
, me
);
462 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
467 sd
->asid_generation
= 1;
468 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
469 sd
->next_asid
= sd
->max_asid
+ 1;
471 native_store_gdt(&gdt_descr
);
472 gdt
= (struct desc_struct
*)gdt_descr
.address
;
473 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
475 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
477 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
479 svm_init_erratum_383();
484 static void svm_cpu_uninit(int cpu
)
486 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
491 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
492 __free_page(sd
->save_area
);
496 static int svm_cpu_init(int cpu
)
498 struct svm_cpu_data
*sd
;
501 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
505 sd
->save_area
= alloc_page(GFP_KERNEL
);
510 per_cpu(svm_data
, cpu
) = sd
;
520 static bool valid_msr_intercept(u32 index
)
524 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
525 if (direct_access_msrs
[i
].index
== index
)
531 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
534 u8 bit_read
, bit_write
;
539 * If this warning triggers extend the direct_access_msrs list at the
540 * beginning of the file
542 WARN_ON(!valid_msr_intercept(msr
));
544 offset
= svm_msrpm_offset(msr
);
545 bit_read
= 2 * (msr
& 0x0f);
546 bit_write
= 2 * (msr
& 0x0f) + 1;
549 BUG_ON(offset
== MSR_INVALID
);
551 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
552 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
557 static void svm_vcpu_init_msrpm(u32
*msrpm
)
561 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
563 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
564 if (!direct_access_msrs
[i
].always
)
567 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
571 static void add_msr_offset(u32 offset
)
575 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
577 /* Offset already in list? */
578 if (msrpm_offsets
[i
] == offset
)
581 /* Slot used by another offset? */
582 if (msrpm_offsets
[i
] != MSR_INVALID
)
585 /* Add offset to list */
586 msrpm_offsets
[i
] = offset
;
592 * If this BUG triggers the msrpm_offsets table has an overflow. Just
593 * increase MSRPM_OFFSETS in this case.
598 static void init_msrpm_offsets(void)
602 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
604 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
607 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
608 BUG_ON(offset
== MSR_INVALID
);
610 add_msr_offset(offset
);
614 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
616 u32
*msrpm
= svm
->msrpm
;
618 svm
->vmcb
->control
.lbr_ctl
= 1;
619 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
620 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
621 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
622 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
625 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
627 u32
*msrpm
= svm
->msrpm
;
629 svm
->vmcb
->control
.lbr_ctl
= 0;
630 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
631 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
632 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
633 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
636 static __init
int svm_hardware_setup(void)
639 struct page
*iopm_pages
;
643 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
648 iopm_va
= page_address(iopm_pages
);
649 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
650 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
652 init_msrpm_offsets();
654 if (boot_cpu_has(X86_FEATURE_NX
))
655 kvm_enable_efer_bits(EFER_NX
);
657 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
658 kvm_enable_efer_bits(EFER_FFXSR
);
661 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
662 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
665 for_each_possible_cpu(cpu
) {
666 r
= svm_cpu_init(cpu
);
671 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
673 if (!svm_has(SVM_FEATURE_NPT
))
676 if (npt_enabled
&& !npt
) {
677 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
682 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
690 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
695 static __exit
void svm_hardware_unsetup(void)
699 for_each_possible_cpu(cpu
)
702 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
706 static void init_seg(struct vmcb_seg
*seg
)
709 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
710 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
715 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
718 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
723 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
725 struct vcpu_svm
*svm
= to_svm(vcpu
);
726 u64 g_tsc_offset
= 0;
728 if (is_nested(svm
)) {
729 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
730 svm
->nested
.hsave
->control
.tsc_offset
;
731 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
734 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
737 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
739 struct vcpu_svm
*svm
= to_svm(vcpu
);
741 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
743 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
746 static void init_vmcb(struct vcpu_svm
*svm
)
748 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
749 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
751 svm
->vcpu
.fpu_active
= 1;
753 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
757 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
762 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
771 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
780 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
785 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
786 (1ULL << INTERCEPT_NMI
) |
787 (1ULL << INTERCEPT_SMI
) |
788 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
789 (1ULL << INTERCEPT_CPUID
) |
790 (1ULL << INTERCEPT_INVD
) |
791 (1ULL << INTERCEPT_HLT
) |
792 (1ULL << INTERCEPT_INVLPG
) |
793 (1ULL << INTERCEPT_INVLPGA
) |
794 (1ULL << INTERCEPT_IOIO_PROT
) |
795 (1ULL << INTERCEPT_MSR_PROT
) |
796 (1ULL << INTERCEPT_TASK_SWITCH
) |
797 (1ULL << INTERCEPT_SHUTDOWN
) |
798 (1ULL << INTERCEPT_VMRUN
) |
799 (1ULL << INTERCEPT_VMMCALL
) |
800 (1ULL << INTERCEPT_VMLOAD
) |
801 (1ULL << INTERCEPT_VMSAVE
) |
802 (1ULL << INTERCEPT_STGI
) |
803 (1ULL << INTERCEPT_CLGI
) |
804 (1ULL << INTERCEPT_SKINIT
) |
805 (1ULL << INTERCEPT_WBINVD
) |
806 (1ULL << INTERCEPT_MONITOR
) |
807 (1ULL << INTERCEPT_MWAIT
);
809 control
->iopm_base_pa
= iopm_base
;
810 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
811 control
->int_ctl
= V_INTR_MASKING_MASK
;
819 save
->cs
.selector
= 0xf000;
820 /* Executable/Readable Code Segment */
821 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
822 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
823 save
->cs
.limit
= 0xffff;
825 * cs.base should really be 0xffff0000, but vmx can't handle that, so
826 * be consistent with it.
828 * Replace when we have real mode working for vmx.
830 save
->cs
.base
= 0xf0000;
832 save
->gdtr
.limit
= 0xffff;
833 save
->idtr
.limit
= 0xffff;
835 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
836 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
838 svm_set_efer(&svm
->vcpu
, 0);
839 save
->dr6
= 0xffff0ff0;
842 save
->rip
= 0x0000fff0;
843 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
846 * This is the guest-visible cr0 value.
847 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
849 svm
->vcpu
.arch
.cr0
= 0;
850 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
852 save
->cr4
= X86_CR4_PAE
;
856 /* Setup VMCB for Nested Paging */
857 control
->nested_ctl
= 1;
858 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
859 (1ULL << INTERCEPT_INVLPG
));
860 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
861 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
862 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
863 save
->g_pat
= 0x0007040600070406ULL
;
867 force_new_asid(&svm
->vcpu
);
869 svm
->nested
.vmcb
= 0;
870 svm
->vcpu
.arch
.hflags
= 0;
872 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
873 control
->pause_filter_count
= 3000;
874 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
880 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
882 struct vcpu_svm
*svm
= to_svm(vcpu
);
886 if (!kvm_vcpu_is_bsp(vcpu
)) {
887 kvm_rip_write(vcpu
, 0);
888 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
889 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
891 vcpu
->arch
.regs_avail
= ~0;
892 vcpu
->arch
.regs_dirty
= ~0;
897 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
899 struct vcpu_svm
*svm
;
901 struct page
*msrpm_pages
;
902 struct page
*hsave_page
;
903 struct page
*nested_msrpm_pages
;
906 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
912 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
917 page
= alloc_page(GFP_KERNEL
);
921 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
925 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
926 if (!nested_msrpm_pages
)
929 hsave_page
= alloc_page(GFP_KERNEL
);
933 svm
->nested
.hsave
= page_address(hsave_page
);
935 svm
->msrpm
= page_address(msrpm_pages
);
936 svm_vcpu_init_msrpm(svm
->msrpm
);
938 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
939 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
941 svm
->vmcb
= page_address(page
);
942 clear_page(svm
->vmcb
);
943 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
944 svm
->asid_generation
= 0;
946 kvm_write_tsc(&svm
->vcpu
, 0);
948 err
= fx_init(&svm
->vcpu
);
952 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
953 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
954 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
959 __free_page(hsave_page
);
961 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
963 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
967 kvm_vcpu_uninit(&svm
->vcpu
);
969 kmem_cache_free(kvm_vcpu_cache
, svm
);
974 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
976 struct vcpu_svm
*svm
= to_svm(vcpu
);
978 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
979 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
980 __free_page(virt_to_page(svm
->nested
.hsave
));
981 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
982 kvm_vcpu_uninit(vcpu
);
983 kmem_cache_free(kvm_vcpu_cache
, svm
);
986 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
988 struct vcpu_svm
*svm
= to_svm(vcpu
);
991 if (unlikely(cpu
!= vcpu
->cpu
)) {
992 svm
->asid_generation
= 0;
995 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
996 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
999 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1001 struct vcpu_svm
*svm
= to_svm(vcpu
);
1004 ++vcpu
->stat
.host_state_reload
;
1005 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1006 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1009 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1011 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1014 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1016 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1019 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1022 case VCPU_EXREG_PDPTR
:
1023 BUG_ON(!npt_enabled
);
1024 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, vcpu
->arch
.cr3
);
1031 static void svm_set_vintr(struct vcpu_svm
*svm
)
1033 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
1036 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1038 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
1041 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1043 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1046 case VCPU_SREG_CS
: return &save
->cs
;
1047 case VCPU_SREG_DS
: return &save
->ds
;
1048 case VCPU_SREG_ES
: return &save
->es
;
1049 case VCPU_SREG_FS
: return &save
->fs
;
1050 case VCPU_SREG_GS
: return &save
->gs
;
1051 case VCPU_SREG_SS
: return &save
->ss
;
1052 case VCPU_SREG_TR
: return &save
->tr
;
1053 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1059 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1061 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1066 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1067 struct kvm_segment
*var
, int seg
)
1069 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1071 var
->base
= s
->base
;
1072 var
->limit
= s
->limit
;
1073 var
->selector
= s
->selector
;
1074 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1075 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1076 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1077 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1078 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1079 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1080 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1081 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1084 * AMD's VMCB does not have an explicit unusable field, so emulate it
1085 * for cross vendor migration purposes by "not present"
1087 var
->unusable
= !var
->present
|| (var
->type
== 0);
1092 * SVM always stores 0 for the 'G' bit in the CS selector in
1093 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1094 * Intel's VMENTRY has a check on the 'G' bit.
1096 var
->g
= s
->limit
> 0xfffff;
1100 * Work around a bug where the busy flag in the tr selector
1110 * The accessed bit must always be set in the segment
1111 * descriptor cache, although it can be cleared in the
1112 * descriptor, the cached bit always remains at 1. Since
1113 * Intel has a check on this, set it here to support
1114 * cross-vendor migration.
1121 * On AMD CPUs sometimes the DB bit in the segment
1122 * descriptor is left as 1, although the whole segment has
1123 * been made unusable. Clear it here to pass an Intel VMX
1124 * entry check when cross vendor migrating.
1132 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1134 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1139 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1141 struct vcpu_svm
*svm
= to_svm(vcpu
);
1143 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1144 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1147 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1149 struct vcpu_svm
*svm
= to_svm(vcpu
);
1151 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1152 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1155 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1157 struct vcpu_svm
*svm
= to_svm(vcpu
);
1159 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1160 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1163 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1165 struct vcpu_svm
*svm
= to_svm(vcpu
);
1167 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1168 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1171 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1175 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1179 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1181 struct vmcb
*vmcb
= svm
->vmcb
;
1182 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1183 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1185 if (!svm
->vcpu
.fpu_active
)
1186 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1188 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1189 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1192 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1193 vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1194 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1195 if (is_nested(svm
)) {
1196 struct vmcb
*hsave
= svm
->nested
.hsave
;
1198 hsave
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1199 hsave
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1200 vmcb
->control
.intercept_cr_read
|= svm
->nested
.intercept_cr_read
;
1201 vmcb
->control
.intercept_cr_write
|= svm
->nested
.intercept_cr_write
;
1204 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1205 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1206 if (is_nested(svm
)) {
1207 struct vmcb
*hsave
= svm
->nested
.hsave
;
1209 hsave
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1210 hsave
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1215 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1217 struct vcpu_svm
*svm
= to_svm(vcpu
);
1219 if (is_nested(svm
)) {
1221 * We are here because we run in nested mode, the host kvm
1222 * intercepts cr0 writes but the l1 hypervisor does not.
1223 * But the L1 hypervisor may intercept selective cr0 writes.
1224 * This needs to be checked here.
1226 unsigned long old
, new;
1228 /* Remove bits that would trigger a real cr0 write intercept */
1229 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1230 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1233 /* cr0 write with ts and mp unchanged */
1234 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1235 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1236 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1237 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1238 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1244 #ifdef CONFIG_X86_64
1245 if (vcpu
->arch
.efer
& EFER_LME
) {
1246 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1247 vcpu
->arch
.efer
|= EFER_LMA
;
1248 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1251 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1252 vcpu
->arch
.efer
&= ~EFER_LMA
;
1253 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1257 vcpu
->arch
.cr0
= cr0
;
1260 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1262 if (!vcpu
->fpu_active
)
1265 * re-enable caching here because the QEMU bios
1266 * does not do it - this results in some delay at
1269 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1270 svm
->vmcb
->save
.cr0
= cr0
;
1271 update_cr0_intercept(svm
);
1274 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1276 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1277 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1279 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1280 force_new_asid(vcpu
);
1282 vcpu
->arch
.cr4
= cr4
;
1285 cr4
|= host_cr4_mce
;
1286 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1289 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1290 struct kvm_segment
*var
, int seg
)
1292 struct vcpu_svm
*svm
= to_svm(vcpu
);
1293 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1295 s
->base
= var
->base
;
1296 s
->limit
= var
->limit
;
1297 s
->selector
= var
->selector
;
1301 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1302 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1303 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1304 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1305 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1306 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1307 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1308 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1310 if (seg
== VCPU_SREG_CS
)
1312 = (svm
->vmcb
->save
.cs
.attrib
1313 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1317 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1319 struct vcpu_svm
*svm
= to_svm(vcpu
);
1321 svm
->vmcb
->control
.intercept_exceptions
&=
1322 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1324 if (svm
->nmi_singlestep
)
1325 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1327 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1328 if (vcpu
->guest_debug
&
1329 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1330 svm
->vmcb
->control
.intercept_exceptions
|=
1332 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1333 svm
->vmcb
->control
.intercept_exceptions
|=
1336 vcpu
->guest_debug
= 0;
1339 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1341 struct vcpu_svm
*svm
= to_svm(vcpu
);
1343 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1344 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1346 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1348 update_db_intercept(vcpu
);
1351 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1353 #ifdef CONFIG_X86_64
1354 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1358 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1360 #ifdef CONFIG_X86_64
1361 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1365 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1367 if (sd
->next_asid
> sd
->max_asid
) {
1368 ++sd
->asid_generation
;
1370 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1373 svm
->asid_generation
= sd
->asid_generation
;
1374 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1377 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1379 struct vcpu_svm
*svm
= to_svm(vcpu
);
1381 svm
->vmcb
->save
.dr7
= value
;
1384 static int pf_interception(struct vcpu_svm
*svm
)
1389 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1390 error_code
= svm
->vmcb
->control
.exit_info_1
;
1392 trace_kvm_page_fault(fault_address
, error_code
);
1393 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1394 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1395 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1398 static int db_interception(struct vcpu_svm
*svm
)
1400 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1402 if (!(svm
->vcpu
.guest_debug
&
1403 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1404 !svm
->nmi_singlestep
) {
1405 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1409 if (svm
->nmi_singlestep
) {
1410 svm
->nmi_singlestep
= false;
1411 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1412 svm
->vmcb
->save
.rflags
&=
1413 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1414 update_db_intercept(&svm
->vcpu
);
1417 if (svm
->vcpu
.guest_debug
&
1418 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1419 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1420 kvm_run
->debug
.arch
.pc
=
1421 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1422 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1429 static int bp_interception(struct vcpu_svm
*svm
)
1431 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1433 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1434 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1435 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1439 static int ud_interception(struct vcpu_svm
*svm
)
1443 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1444 if (er
!= EMULATE_DONE
)
1445 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1449 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1451 struct vcpu_svm
*svm
= to_svm(vcpu
);
1454 if (is_nested(svm
)) {
1457 h_excp
= svm
->nested
.hsave
->control
.intercept_exceptions
;
1458 n_excp
= svm
->nested
.intercept_exceptions
;
1459 h_excp
&= ~(1 << NM_VECTOR
);
1460 excp
= h_excp
| n_excp
;
1462 excp
= svm
->vmcb
->control
.intercept_exceptions
;
1463 excp
&= ~(1 << NM_VECTOR
);
1466 svm
->vmcb
->control
.intercept_exceptions
= excp
;
1468 svm
->vcpu
.fpu_active
= 1;
1469 update_cr0_intercept(svm
);
1472 static int nm_interception(struct vcpu_svm
*svm
)
1474 svm_fpu_activate(&svm
->vcpu
);
1478 static bool is_erratum_383(void)
1483 if (!erratum_383_found
)
1486 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1490 /* Bit 62 may or may not be set for this mce */
1491 value
&= ~(1ULL << 62);
1493 if (value
!= 0xb600000000010015ULL
)
1496 /* Clear MCi_STATUS registers */
1497 for (i
= 0; i
< 6; ++i
)
1498 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1500 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1504 value
&= ~(1ULL << 2);
1505 low
= lower_32_bits(value
);
1506 high
= upper_32_bits(value
);
1508 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1511 /* Flush tlb to evict multi-match entries */
1517 static void svm_handle_mce(struct vcpu_svm
*svm
)
1519 if (is_erratum_383()) {
1521 * Erratum 383 triggered. Guest state is corrupt so kill the
1524 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1526 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1532 * On an #MC intercept the MCE handler is not called automatically in
1533 * the host. So do it by hand here.
1537 /* not sure if we ever come back to this point */
1542 static int mc_interception(struct vcpu_svm
*svm
)
1547 static int shutdown_interception(struct vcpu_svm
*svm
)
1549 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1552 * VMCB is undefined after a SHUTDOWN intercept
1553 * so reinitialize it.
1555 clear_page(svm
->vmcb
);
1558 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1562 static int io_interception(struct vcpu_svm
*svm
)
1564 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1565 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1566 int size
, in
, string
;
1569 ++svm
->vcpu
.stat
.io_exits
;
1570 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1571 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1573 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1575 port
= io_info
>> 16;
1576 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1577 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1578 skip_emulated_instruction(&svm
->vcpu
);
1580 return kvm_fast_pio_out(vcpu
, size
, port
);
1583 static int nmi_interception(struct vcpu_svm
*svm
)
1588 static int intr_interception(struct vcpu_svm
*svm
)
1590 ++svm
->vcpu
.stat
.irq_exits
;
1594 static int nop_on_interception(struct vcpu_svm
*svm
)
1599 static int halt_interception(struct vcpu_svm
*svm
)
1601 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1602 skip_emulated_instruction(&svm
->vcpu
);
1603 return kvm_emulate_halt(&svm
->vcpu
);
1606 static int vmmcall_interception(struct vcpu_svm
*svm
)
1608 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1609 skip_emulated_instruction(&svm
->vcpu
);
1610 kvm_emulate_hypercall(&svm
->vcpu
);
1614 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1616 struct vcpu_svm
*svm
= to_svm(vcpu
);
1618 return svm
->nested
.nested_cr3
;
1621 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1624 struct vcpu_svm
*svm
= to_svm(vcpu
);
1626 svm
->vmcb
->control
.nested_cr3
= root
;
1627 force_new_asid(vcpu
);
1630 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
)
1632 struct vcpu_svm
*svm
= to_svm(vcpu
);
1634 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1635 svm
->vmcb
->control
.exit_code_hi
= 0;
1636 svm
->vmcb
->control
.exit_info_1
= vcpu
->arch
.fault
.error_code
;
1637 svm
->vmcb
->control
.exit_info_2
= vcpu
->arch
.fault
.address
;
1639 nested_svm_vmexit(svm
);
1642 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1646 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1648 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1649 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1650 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1651 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1652 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1657 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1659 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1662 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1664 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1665 || !is_paging(&svm
->vcpu
)) {
1666 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1670 if (svm
->vmcb
->save
.cpl
) {
1671 kvm_inject_gp(&svm
->vcpu
, 0);
1678 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1679 bool has_error_code
, u32 error_code
)
1683 if (!is_nested(svm
))
1686 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1687 svm
->vmcb
->control
.exit_code_hi
= 0;
1688 svm
->vmcb
->control
.exit_info_1
= error_code
;
1689 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1691 vmexit
= nested_svm_intercept(svm
);
1692 if (vmexit
== NESTED_EXIT_DONE
)
1693 svm
->nested
.exit_required
= true;
1698 /* This function returns true if it is save to enable the irq window */
1699 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1701 if (!is_nested(svm
))
1704 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1707 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1711 * if vmexit was already requested (by intercepted exception
1712 * for instance) do not overwrite it with "external interrupt"
1715 if (svm
->nested
.exit_required
)
1718 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1719 svm
->vmcb
->control
.exit_info_1
= 0;
1720 svm
->vmcb
->control
.exit_info_2
= 0;
1722 if (svm
->nested
.intercept
& 1ULL) {
1724 * The #vmexit can't be emulated here directly because this
1725 * code path runs with irqs and preemtion disabled. A
1726 * #vmexit emulation might sleep. Only signal request for
1729 svm
->nested
.exit_required
= true;
1730 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1737 /* This function returns true if it is save to enable the nmi window */
1738 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1740 if (!is_nested(svm
))
1743 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1746 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1747 svm
->nested
.exit_required
= true;
1752 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1758 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1759 if (is_error_page(page
))
1767 kvm_release_page_clean(page
);
1768 kvm_inject_gp(&svm
->vcpu
, 0);
1773 static void nested_svm_unmap(struct page
*page
)
1776 kvm_release_page_dirty(page
);
1779 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1785 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1786 return NESTED_EXIT_HOST
;
1788 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1789 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1793 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1796 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1799 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1801 u32 offset
, msr
, value
;
1804 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1805 return NESTED_EXIT_HOST
;
1807 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1808 offset
= svm_msrpm_offset(msr
);
1809 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1810 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1812 if (offset
== MSR_INVALID
)
1813 return NESTED_EXIT_DONE
;
1815 /* Offset is in 32 bit units but need in 8 bit units */
1818 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1819 return NESTED_EXIT_DONE
;
1821 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1824 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1826 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1828 switch (exit_code
) {
1831 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1832 return NESTED_EXIT_HOST
;
1834 /* For now we are always handling NPFs when using them */
1836 return NESTED_EXIT_HOST
;
1838 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1839 /* When we're shadowing, trap PFs */
1841 return NESTED_EXIT_HOST
;
1843 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1844 nm_interception(svm
);
1850 return NESTED_EXIT_CONTINUE
;
1854 * If this function returns true, this #vmexit was already handled
1856 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1858 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1859 int vmexit
= NESTED_EXIT_HOST
;
1861 switch (exit_code
) {
1863 vmexit
= nested_svm_exit_handled_msr(svm
);
1866 vmexit
= nested_svm_intercept_ioio(svm
);
1868 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1869 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1870 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1871 vmexit
= NESTED_EXIT_DONE
;
1874 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1875 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1876 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1877 vmexit
= NESTED_EXIT_DONE
;
1880 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1881 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1882 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1883 vmexit
= NESTED_EXIT_DONE
;
1886 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1887 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1888 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1889 vmexit
= NESTED_EXIT_DONE
;
1892 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1893 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1894 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1895 vmexit
= NESTED_EXIT_DONE
;
1898 case SVM_EXIT_ERR
: {
1899 vmexit
= NESTED_EXIT_DONE
;
1903 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1904 if (svm
->nested
.intercept
& exit_bits
)
1905 vmexit
= NESTED_EXIT_DONE
;
1912 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1916 vmexit
= nested_svm_intercept(svm
);
1918 if (vmexit
== NESTED_EXIT_DONE
)
1919 nested_svm_vmexit(svm
);
1924 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1926 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1927 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1929 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1930 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1931 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1932 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1933 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1934 dst
->intercept
= from
->intercept
;
1935 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1936 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1937 dst
->tsc_offset
= from
->tsc_offset
;
1938 dst
->asid
= from
->asid
;
1939 dst
->tlb_ctl
= from
->tlb_ctl
;
1940 dst
->int_ctl
= from
->int_ctl
;
1941 dst
->int_vector
= from
->int_vector
;
1942 dst
->int_state
= from
->int_state
;
1943 dst
->exit_code
= from
->exit_code
;
1944 dst
->exit_code_hi
= from
->exit_code_hi
;
1945 dst
->exit_info_1
= from
->exit_info_1
;
1946 dst
->exit_info_2
= from
->exit_info_2
;
1947 dst
->exit_int_info
= from
->exit_int_info
;
1948 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1949 dst
->nested_ctl
= from
->nested_ctl
;
1950 dst
->event_inj
= from
->event_inj
;
1951 dst
->event_inj_err
= from
->event_inj_err
;
1952 dst
->nested_cr3
= from
->nested_cr3
;
1953 dst
->lbr_ctl
= from
->lbr_ctl
;
1956 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1958 struct vmcb
*nested_vmcb
;
1959 struct vmcb
*hsave
= svm
->nested
.hsave
;
1960 struct vmcb
*vmcb
= svm
->vmcb
;
1963 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1964 vmcb
->control
.exit_info_1
,
1965 vmcb
->control
.exit_info_2
,
1966 vmcb
->control
.exit_int_info
,
1967 vmcb
->control
.exit_int_info_err
);
1969 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1973 /* Exit nested SVM mode */
1974 svm
->nested
.vmcb
= 0;
1976 /* Give the current vmcb to the guest */
1979 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1980 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1981 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1982 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1983 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1984 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1985 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
1986 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1987 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1988 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1989 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1990 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1991 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1992 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1993 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1994 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1995 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1996 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1998 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1999 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2000 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2001 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2002 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2003 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2004 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2005 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2006 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2007 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2010 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2011 * to make sure that we do not lose injected events. So check event_inj
2012 * here and copy it to exit_int_info if it is valid.
2013 * Exit_int_info and event_inj can't be both valid because the case
2014 * below only happens on a VMRUN instruction intercept which has
2015 * no valid exit_int_info set.
2017 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2018 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2020 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2021 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2024 nested_vmcb
->control
.tlb_ctl
= 0;
2025 nested_vmcb
->control
.event_inj
= 0;
2026 nested_vmcb
->control
.event_inj_err
= 0;
2028 /* We always set V_INTR_MASKING and remember the old value in hflags */
2029 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2030 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2032 /* Restore the original control entries */
2033 copy_vmcb_control_area(vmcb
, hsave
);
2035 kvm_clear_exception_queue(&svm
->vcpu
);
2036 kvm_clear_interrupt_queue(&svm
->vcpu
);
2038 svm
->nested
.nested_cr3
= 0;
2040 /* Restore selected save entries */
2041 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2042 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2043 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2044 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2045 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2046 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2047 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
2048 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2049 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2050 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2052 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2053 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2055 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2057 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2058 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2059 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2060 svm
->vmcb
->save
.dr7
= 0;
2061 svm
->vmcb
->save
.cpl
= 0;
2062 svm
->vmcb
->control
.exit_int_info
= 0;
2064 nested_svm_unmap(page
);
2066 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2067 kvm_mmu_reset_context(&svm
->vcpu
);
2068 kvm_mmu_load(&svm
->vcpu
);
2073 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2076 * This function merges the msr permission bitmaps of kvm and the
2077 * nested vmcb. It is omptimized in that it only merges the parts where
2078 * the kvm msr permission bitmap may contain zero bits
2082 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2085 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2089 if (msrpm_offsets
[i
] == 0xffffffff)
2092 p
= msrpm_offsets
[i
];
2093 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2095 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2098 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2101 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2106 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2108 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2111 if (vmcb
->control
.asid
== 0)
2114 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2120 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2122 struct vmcb
*nested_vmcb
;
2123 struct vmcb
*hsave
= svm
->nested
.hsave
;
2124 struct vmcb
*vmcb
= svm
->vmcb
;
2128 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2130 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2134 if (!nested_vmcb_checks(nested_vmcb
)) {
2135 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2136 nested_vmcb
->control
.exit_code_hi
= 0;
2137 nested_vmcb
->control
.exit_info_1
= 0;
2138 nested_vmcb
->control
.exit_info_2
= 0;
2140 nested_svm_unmap(page
);
2145 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2146 nested_vmcb
->save
.rip
,
2147 nested_vmcb
->control
.int_ctl
,
2148 nested_vmcb
->control
.event_inj
,
2149 nested_vmcb
->control
.nested_ctl
);
2151 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr_read
,
2152 nested_vmcb
->control
.intercept_cr_write
,
2153 nested_vmcb
->control
.intercept_exceptions
,
2154 nested_vmcb
->control
.intercept
);
2156 /* Clear internal status */
2157 kvm_clear_exception_queue(&svm
->vcpu
);
2158 kvm_clear_interrupt_queue(&svm
->vcpu
);
2161 * Save the old vmcb, so we don't need to pick what we save, but can
2162 * restore everything when a VMEXIT occurs
2164 hsave
->save
.es
= vmcb
->save
.es
;
2165 hsave
->save
.cs
= vmcb
->save
.cs
;
2166 hsave
->save
.ss
= vmcb
->save
.ss
;
2167 hsave
->save
.ds
= vmcb
->save
.ds
;
2168 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2169 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2170 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2171 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2172 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2173 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2174 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2175 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2176 hsave
->save
.rax
= vmcb
->save
.rax
;
2178 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2180 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2182 copy_vmcb_control_area(hsave
, vmcb
);
2184 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2185 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2187 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2189 if (nested_vmcb
->control
.nested_ctl
) {
2190 kvm_mmu_unload(&svm
->vcpu
);
2191 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2192 nested_svm_init_mmu_context(&svm
->vcpu
);
2195 /* Load the nested guest state */
2196 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2197 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2198 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2199 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2200 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2201 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2202 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2203 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2204 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2205 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2207 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2208 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2210 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2212 /* Guest paging mode is active - reset mmu */
2213 kvm_mmu_reset_context(&svm
->vcpu
);
2215 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2216 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2217 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2218 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2220 /* In case we don't even reach vcpu_run, the fields are not updated */
2221 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2222 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2223 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2224 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2225 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2226 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2228 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2229 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2231 /* cache intercepts */
2232 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
2233 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
2234 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
2235 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
2236 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2237 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2239 force_new_asid(&svm
->vcpu
);
2240 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2241 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2242 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2244 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2246 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2247 /* We only want the cr8 intercept bits of the guest */
2248 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
2249 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2252 /* We don't want to see VMMCALLs from a nested guest */
2253 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VMMCALL
);
2256 * We don't want a nested guest to be more powerful than the guest, so
2257 * all intercepts are ORed
2259 svm
->vmcb
->control
.intercept_cr_read
|=
2260 nested_vmcb
->control
.intercept_cr_read
;
2261 svm
->vmcb
->control
.intercept_cr_write
|=
2262 nested_vmcb
->control
.intercept_cr_write
;
2263 svm
->vmcb
->control
.intercept_dr_read
|=
2264 nested_vmcb
->control
.intercept_dr_read
;
2265 svm
->vmcb
->control
.intercept_dr_write
|=
2266 nested_vmcb
->control
.intercept_dr_write
;
2267 svm
->vmcb
->control
.intercept_exceptions
|=
2268 nested_vmcb
->control
.intercept_exceptions
;
2270 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
2272 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2273 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2274 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2275 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2276 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2277 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2279 nested_svm_unmap(page
);
2281 /* nested_vmcb is our indicator if nested SVM is activated */
2282 svm
->nested
.vmcb
= vmcb_gpa
;
2289 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2291 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2292 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2293 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2294 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2295 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2296 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2297 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2298 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2299 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2300 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2301 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2302 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2305 static int vmload_interception(struct vcpu_svm
*svm
)
2307 struct vmcb
*nested_vmcb
;
2310 if (nested_svm_check_permissions(svm
))
2313 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2314 skip_emulated_instruction(&svm
->vcpu
);
2316 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2320 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2321 nested_svm_unmap(page
);
2326 static int vmsave_interception(struct vcpu_svm
*svm
)
2328 struct vmcb
*nested_vmcb
;
2331 if (nested_svm_check_permissions(svm
))
2334 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2335 skip_emulated_instruction(&svm
->vcpu
);
2337 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2341 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2342 nested_svm_unmap(page
);
2347 static int vmrun_interception(struct vcpu_svm
*svm
)
2349 if (nested_svm_check_permissions(svm
))
2352 /* Save rip after vmrun instruction */
2353 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2355 if (!nested_svm_vmrun(svm
))
2358 if (!nested_svm_vmrun_msrpm(svm
))
2365 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2366 svm
->vmcb
->control
.exit_code_hi
= 0;
2367 svm
->vmcb
->control
.exit_info_1
= 0;
2368 svm
->vmcb
->control
.exit_info_2
= 0;
2370 nested_svm_vmexit(svm
);
2375 static int stgi_interception(struct vcpu_svm
*svm
)
2377 if (nested_svm_check_permissions(svm
))
2380 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2381 skip_emulated_instruction(&svm
->vcpu
);
2382 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2389 static int clgi_interception(struct vcpu_svm
*svm
)
2391 if (nested_svm_check_permissions(svm
))
2394 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2395 skip_emulated_instruction(&svm
->vcpu
);
2399 /* After a CLGI no interrupts should come */
2400 svm_clear_vintr(svm
);
2401 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2406 static int invlpga_interception(struct vcpu_svm
*svm
)
2408 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2410 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2411 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2413 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2414 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2416 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2417 skip_emulated_instruction(&svm
->vcpu
);
2421 static int skinit_interception(struct vcpu_svm
*svm
)
2423 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2425 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2429 static int invalid_op_interception(struct vcpu_svm
*svm
)
2431 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2435 static int task_switch_interception(struct vcpu_svm
*svm
)
2439 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2440 SVM_EXITINTINFO_TYPE_MASK
;
2441 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2443 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2445 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2446 bool has_error_code
= false;
2449 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2451 if (svm
->vmcb
->control
.exit_info_2
&
2452 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2453 reason
= TASK_SWITCH_IRET
;
2454 else if (svm
->vmcb
->control
.exit_info_2
&
2455 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2456 reason
= TASK_SWITCH_JMP
;
2458 reason
= TASK_SWITCH_GATE
;
2460 reason
= TASK_SWITCH_CALL
;
2462 if (reason
== TASK_SWITCH_GATE
) {
2464 case SVM_EXITINTINFO_TYPE_NMI
:
2465 svm
->vcpu
.arch
.nmi_injected
= false;
2467 case SVM_EXITINTINFO_TYPE_EXEPT
:
2468 if (svm
->vmcb
->control
.exit_info_2
&
2469 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2470 has_error_code
= true;
2472 (u32
)svm
->vmcb
->control
.exit_info_2
;
2474 kvm_clear_exception_queue(&svm
->vcpu
);
2476 case SVM_EXITINTINFO_TYPE_INTR
:
2477 kvm_clear_interrupt_queue(&svm
->vcpu
);
2484 if (reason
!= TASK_SWITCH_GATE
||
2485 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2486 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2487 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2488 skip_emulated_instruction(&svm
->vcpu
);
2490 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2491 has_error_code
, error_code
) == EMULATE_FAIL
) {
2492 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2493 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2494 svm
->vcpu
.run
->internal
.ndata
= 0;
2500 static int cpuid_interception(struct vcpu_svm
*svm
)
2502 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2503 kvm_emulate_cpuid(&svm
->vcpu
);
2507 static int iret_interception(struct vcpu_svm
*svm
)
2509 ++svm
->vcpu
.stat
.nmi_window_exits
;
2510 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
2511 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2515 static int invlpg_interception(struct vcpu_svm
*svm
)
2517 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2520 static int emulate_on_interception(struct vcpu_svm
*svm
)
2522 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2525 static int cr0_write_interception(struct vcpu_svm
*svm
)
2527 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2530 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2532 if (svm
->nested
.vmexit_rip
) {
2533 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2534 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2535 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2536 svm
->nested
.vmexit_rip
= 0;
2539 return r
== EMULATE_DONE
;
2542 static int cr8_write_interception(struct vcpu_svm
*svm
)
2544 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2546 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2547 /* instruction emulation calls kvm_set_cr8() */
2548 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2549 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2550 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2553 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2555 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2559 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2561 struct vcpu_svm
*svm
= to_svm(vcpu
);
2564 case MSR_IA32_TSC
: {
2568 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2570 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2572 *data
= tsc_offset
+ native_read_tsc();
2576 *data
= svm
->vmcb
->save
.star
;
2578 #ifdef CONFIG_X86_64
2580 *data
= svm
->vmcb
->save
.lstar
;
2583 *data
= svm
->vmcb
->save
.cstar
;
2585 case MSR_KERNEL_GS_BASE
:
2586 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2588 case MSR_SYSCALL_MASK
:
2589 *data
= svm
->vmcb
->save
.sfmask
;
2592 case MSR_IA32_SYSENTER_CS
:
2593 *data
= svm
->vmcb
->save
.sysenter_cs
;
2595 case MSR_IA32_SYSENTER_EIP
:
2596 *data
= svm
->sysenter_eip
;
2598 case MSR_IA32_SYSENTER_ESP
:
2599 *data
= svm
->sysenter_esp
;
2602 * Nobody will change the following 5 values in the VMCB so we can
2603 * safely return them on rdmsr. They will always be 0 until LBRV is
2606 case MSR_IA32_DEBUGCTLMSR
:
2607 *data
= svm
->vmcb
->save
.dbgctl
;
2609 case MSR_IA32_LASTBRANCHFROMIP
:
2610 *data
= svm
->vmcb
->save
.br_from
;
2612 case MSR_IA32_LASTBRANCHTOIP
:
2613 *data
= svm
->vmcb
->save
.br_to
;
2615 case MSR_IA32_LASTINTFROMIP
:
2616 *data
= svm
->vmcb
->save
.last_excp_from
;
2618 case MSR_IA32_LASTINTTOIP
:
2619 *data
= svm
->vmcb
->save
.last_excp_to
;
2621 case MSR_VM_HSAVE_PA
:
2622 *data
= svm
->nested
.hsave_msr
;
2625 *data
= svm
->nested
.vm_cr_msr
;
2627 case MSR_IA32_UCODE_REV
:
2631 return kvm_get_msr_common(vcpu
, ecx
, data
);
2636 static int rdmsr_interception(struct vcpu_svm
*svm
)
2638 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2641 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2642 trace_kvm_msr_read_ex(ecx
);
2643 kvm_inject_gp(&svm
->vcpu
, 0);
2645 trace_kvm_msr_read(ecx
, data
);
2647 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2648 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2649 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2650 skip_emulated_instruction(&svm
->vcpu
);
2655 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2657 struct vcpu_svm
*svm
= to_svm(vcpu
);
2658 int svm_dis
, chg_mask
;
2660 if (data
& ~SVM_VM_CR_VALID_MASK
)
2663 chg_mask
= SVM_VM_CR_VALID_MASK
;
2665 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2666 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2668 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2669 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2671 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2673 /* check for svm_disable while efer.svme is set */
2674 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2680 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2682 struct vcpu_svm
*svm
= to_svm(vcpu
);
2686 kvm_write_tsc(vcpu
, data
);
2689 svm
->vmcb
->save
.star
= data
;
2691 #ifdef CONFIG_X86_64
2693 svm
->vmcb
->save
.lstar
= data
;
2696 svm
->vmcb
->save
.cstar
= data
;
2698 case MSR_KERNEL_GS_BASE
:
2699 svm
->vmcb
->save
.kernel_gs_base
= data
;
2701 case MSR_SYSCALL_MASK
:
2702 svm
->vmcb
->save
.sfmask
= data
;
2705 case MSR_IA32_SYSENTER_CS
:
2706 svm
->vmcb
->save
.sysenter_cs
= data
;
2708 case MSR_IA32_SYSENTER_EIP
:
2709 svm
->sysenter_eip
= data
;
2710 svm
->vmcb
->save
.sysenter_eip
= data
;
2712 case MSR_IA32_SYSENTER_ESP
:
2713 svm
->sysenter_esp
= data
;
2714 svm
->vmcb
->save
.sysenter_esp
= data
;
2716 case MSR_IA32_DEBUGCTLMSR
:
2717 if (!svm_has(SVM_FEATURE_LBRV
)) {
2718 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2722 if (data
& DEBUGCTL_RESERVED_BITS
)
2725 svm
->vmcb
->save
.dbgctl
= data
;
2726 if (data
& (1ULL<<0))
2727 svm_enable_lbrv(svm
);
2729 svm_disable_lbrv(svm
);
2731 case MSR_VM_HSAVE_PA
:
2732 svm
->nested
.hsave_msr
= data
;
2735 return svm_set_vm_cr(vcpu
, data
);
2737 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2740 return kvm_set_msr_common(vcpu
, ecx
, data
);
2745 static int wrmsr_interception(struct vcpu_svm
*svm
)
2747 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2748 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2749 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2752 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2753 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2754 trace_kvm_msr_write_ex(ecx
, data
);
2755 kvm_inject_gp(&svm
->vcpu
, 0);
2757 trace_kvm_msr_write(ecx
, data
);
2758 skip_emulated_instruction(&svm
->vcpu
);
2763 static int msr_interception(struct vcpu_svm
*svm
)
2765 if (svm
->vmcb
->control
.exit_info_1
)
2766 return wrmsr_interception(svm
);
2768 return rdmsr_interception(svm
);
2771 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2773 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2775 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2776 svm_clear_vintr(svm
);
2777 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2779 * If the user space waits to inject interrupts, exit as soon as
2782 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2783 kvm_run
->request_interrupt_window
&&
2784 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2785 ++svm
->vcpu
.stat
.irq_window_exits
;
2786 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2793 static int pause_interception(struct vcpu_svm
*svm
)
2795 kvm_vcpu_on_spin(&(svm
->vcpu
));
2799 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2800 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2801 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2802 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2803 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2804 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2805 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
2806 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2807 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2808 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2809 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2810 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2811 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2812 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2813 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2814 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2815 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2816 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2817 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2818 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2819 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2820 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2821 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2822 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2823 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2824 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2825 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2826 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2827 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2828 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2829 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2830 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2831 [SVM_EXIT_INTR
] = intr_interception
,
2832 [SVM_EXIT_NMI
] = nmi_interception
,
2833 [SVM_EXIT_SMI
] = nop_on_interception
,
2834 [SVM_EXIT_INIT
] = nop_on_interception
,
2835 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2836 [SVM_EXIT_CPUID
] = cpuid_interception
,
2837 [SVM_EXIT_IRET
] = iret_interception
,
2838 [SVM_EXIT_INVD
] = emulate_on_interception
,
2839 [SVM_EXIT_PAUSE
] = pause_interception
,
2840 [SVM_EXIT_HLT
] = halt_interception
,
2841 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2842 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2843 [SVM_EXIT_IOIO
] = io_interception
,
2844 [SVM_EXIT_MSR
] = msr_interception
,
2845 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2846 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2847 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2848 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2849 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2850 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2851 [SVM_EXIT_STGI
] = stgi_interception
,
2852 [SVM_EXIT_CLGI
] = clgi_interception
,
2853 [SVM_EXIT_SKINIT
] = skinit_interception
,
2854 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2855 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2856 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2857 [SVM_EXIT_NPF
] = pf_interception
,
2860 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2862 struct vcpu_svm
*svm
= to_svm(vcpu
);
2863 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2864 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2866 pr_err("VMCB Control Area:\n");
2867 pr_err("cr_read: %04x\n", control
->intercept_cr_read
);
2868 pr_err("cr_write: %04x\n", control
->intercept_cr_write
);
2869 pr_err("dr_read: %04x\n", control
->intercept_dr_read
);
2870 pr_err("dr_write: %04x\n", control
->intercept_dr_write
);
2871 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
2872 pr_err("intercepts: %016llx\n", control
->intercept
);
2873 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
2874 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
2875 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
2876 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
2877 pr_err("asid: %d\n", control
->asid
);
2878 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
2879 pr_err("int_ctl: %08x\n", control
->int_ctl
);
2880 pr_err("int_vector: %08x\n", control
->int_vector
);
2881 pr_err("int_state: %08x\n", control
->int_state
);
2882 pr_err("exit_code: %08x\n", control
->exit_code
);
2883 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
2884 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
2885 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
2886 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
2887 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
2888 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
2889 pr_err("event_inj: %08x\n", control
->event_inj
);
2890 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
2891 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
2892 pr_err("next_rip: %016llx\n", control
->next_rip
);
2893 pr_err("VMCB State Save Area:\n");
2894 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2895 save
->es
.selector
, save
->es
.attrib
,
2896 save
->es
.limit
, save
->es
.base
);
2897 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2898 save
->cs
.selector
, save
->cs
.attrib
,
2899 save
->cs
.limit
, save
->cs
.base
);
2900 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2901 save
->ss
.selector
, save
->ss
.attrib
,
2902 save
->ss
.limit
, save
->ss
.base
);
2903 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2904 save
->ds
.selector
, save
->ds
.attrib
,
2905 save
->ds
.limit
, save
->ds
.base
);
2906 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2907 save
->fs
.selector
, save
->fs
.attrib
,
2908 save
->fs
.limit
, save
->fs
.base
);
2909 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2910 save
->gs
.selector
, save
->gs
.attrib
,
2911 save
->gs
.limit
, save
->gs
.base
);
2912 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2913 save
->gdtr
.selector
, save
->gdtr
.attrib
,
2914 save
->gdtr
.limit
, save
->gdtr
.base
);
2915 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2916 save
->ldtr
.selector
, save
->ldtr
.attrib
,
2917 save
->ldtr
.limit
, save
->ldtr
.base
);
2918 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2919 save
->idtr
.selector
, save
->idtr
.attrib
,
2920 save
->idtr
.limit
, save
->idtr
.base
);
2921 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2922 save
->tr
.selector
, save
->tr
.attrib
,
2923 save
->tr
.limit
, save
->tr
.base
);
2924 pr_err("cpl: %d efer: %016llx\n",
2925 save
->cpl
, save
->efer
);
2926 pr_err("cr0: %016llx cr2: %016llx\n",
2927 save
->cr0
, save
->cr2
);
2928 pr_err("cr3: %016llx cr4: %016llx\n",
2929 save
->cr3
, save
->cr4
);
2930 pr_err("dr6: %016llx dr7: %016llx\n",
2931 save
->dr6
, save
->dr7
);
2932 pr_err("rip: %016llx rflags: %016llx\n",
2933 save
->rip
, save
->rflags
);
2934 pr_err("rsp: %016llx rax: %016llx\n",
2935 save
->rsp
, save
->rax
);
2936 pr_err("star: %016llx lstar: %016llx\n",
2937 save
->star
, save
->lstar
);
2938 pr_err("cstar: %016llx sfmask: %016llx\n",
2939 save
->cstar
, save
->sfmask
);
2940 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2941 save
->kernel_gs_base
, save
->sysenter_cs
);
2942 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2943 save
->sysenter_esp
, save
->sysenter_eip
);
2944 pr_err("gpat: %016llx dbgctl: %016llx\n",
2945 save
->g_pat
, save
->dbgctl
);
2946 pr_err("br_from: %016llx br_to: %016llx\n",
2947 save
->br_from
, save
->br_to
);
2948 pr_err("excp_from: %016llx excp_to: %016llx\n",
2949 save
->last_excp_from
, save
->last_excp_to
);
2953 static int handle_exit(struct kvm_vcpu
*vcpu
)
2955 struct vcpu_svm
*svm
= to_svm(vcpu
);
2956 struct kvm_run
*kvm_run
= vcpu
->run
;
2957 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2959 trace_kvm_exit(exit_code
, vcpu
);
2961 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2962 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2964 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2966 if (unlikely(svm
->nested
.exit_required
)) {
2967 nested_svm_vmexit(svm
);
2968 svm
->nested
.exit_required
= false;
2973 if (is_nested(svm
)) {
2976 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2977 svm
->vmcb
->control
.exit_info_1
,
2978 svm
->vmcb
->control
.exit_info_2
,
2979 svm
->vmcb
->control
.exit_int_info
,
2980 svm
->vmcb
->control
.exit_int_info_err
);
2982 vmexit
= nested_svm_exit_special(svm
);
2984 if (vmexit
== NESTED_EXIT_CONTINUE
)
2985 vmexit
= nested_svm_exit_handled(svm
);
2987 if (vmexit
== NESTED_EXIT_DONE
)
2991 svm_complete_interrupts(svm
);
2993 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2994 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2995 kvm_run
->fail_entry
.hardware_entry_failure_reason
2996 = svm
->vmcb
->control
.exit_code
;
2997 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3002 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3003 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3004 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3005 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3006 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3008 __func__
, svm
->vmcb
->control
.exit_int_info
,
3011 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3012 || !svm_exit_handlers
[exit_code
]) {
3013 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3014 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3018 return svm_exit_handlers
[exit_code
](svm
);
3021 static void reload_tss(struct kvm_vcpu
*vcpu
)
3023 int cpu
= raw_smp_processor_id();
3025 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3026 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3030 static void pre_svm_run(struct vcpu_svm
*svm
)
3032 int cpu
= raw_smp_processor_id();
3034 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3036 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3037 /* FIXME: handle wraparound of asid_generation */
3038 if (svm
->asid_generation
!= sd
->asid_generation
)
3042 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3044 struct vcpu_svm
*svm
= to_svm(vcpu
);
3046 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3047 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3048 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
3049 ++vcpu
->stat
.nmi_injections
;
3052 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3054 struct vmcb_control_area
*control
;
3056 control
= &svm
->vmcb
->control
;
3057 control
->int_vector
= irq
;
3058 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3059 control
->int_ctl
|= V_IRQ_MASK
|
3060 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3063 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3065 struct vcpu_svm
*svm
= to_svm(vcpu
);
3067 BUG_ON(!(gif_set(svm
)));
3069 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3070 ++vcpu
->stat
.irq_injections
;
3072 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3073 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3076 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3078 struct vcpu_svm
*svm
= to_svm(vcpu
);
3080 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3087 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
3090 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3092 struct vcpu_svm
*svm
= to_svm(vcpu
);
3093 struct vmcb
*vmcb
= svm
->vmcb
;
3095 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3096 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3097 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3102 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3104 struct vcpu_svm
*svm
= to_svm(vcpu
);
3106 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3109 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3111 struct vcpu_svm
*svm
= to_svm(vcpu
);
3114 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3115 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
3117 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3118 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
3122 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3124 struct vcpu_svm
*svm
= to_svm(vcpu
);
3125 struct vmcb
*vmcb
= svm
->vmcb
;
3128 if (!gif_set(svm
) ||
3129 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3132 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3135 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3140 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3142 struct vcpu_svm
*svm
= to_svm(vcpu
);
3145 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3146 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3147 * get that intercept, this function will be called again though and
3148 * we'll get the vintr intercept.
3150 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3152 svm_inject_irq(svm
, 0x0);
3156 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3158 struct vcpu_svm
*svm
= to_svm(vcpu
);
3160 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3162 return; /* IRET will cause a vm exit */
3165 * Something prevents NMI from been injected. Single step over possible
3166 * problem (IRET or exception injection or interrupt shadow)
3168 svm
->nmi_singlestep
= true;
3169 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3170 update_db_intercept(vcpu
);
3173 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3178 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3180 force_new_asid(vcpu
);
3183 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3187 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3189 struct vcpu_svm
*svm
= to_svm(vcpu
);
3191 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3194 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
3195 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3196 kvm_set_cr8(vcpu
, cr8
);
3200 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3202 struct vcpu_svm
*svm
= to_svm(vcpu
);
3205 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3208 cr8
= kvm_get_cr8(vcpu
);
3209 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3210 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3213 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3217 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3218 unsigned int3_injected
= svm
->int3_injected
;
3220 svm
->int3_injected
= 0;
3222 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) {
3223 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3224 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3227 svm
->vcpu
.arch
.nmi_injected
= false;
3228 kvm_clear_exception_queue(&svm
->vcpu
);
3229 kvm_clear_interrupt_queue(&svm
->vcpu
);
3231 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3234 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3236 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3237 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3240 case SVM_EXITINTINFO_TYPE_NMI
:
3241 svm
->vcpu
.arch
.nmi_injected
= true;
3243 case SVM_EXITINTINFO_TYPE_EXEPT
:
3245 * In case of software exceptions, do not reinject the vector,
3246 * but re-execute the instruction instead. Rewind RIP first
3247 * if we emulated INT3 before.
3249 if (kvm_exception_is_soft(vector
)) {
3250 if (vector
== BP_VECTOR
&& int3_injected
&&
3251 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3252 kvm_rip_write(&svm
->vcpu
,
3253 kvm_rip_read(&svm
->vcpu
) -
3257 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3258 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3259 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3262 kvm_requeue_exception(&svm
->vcpu
, vector
);
3264 case SVM_EXITINTINFO_TYPE_INTR
:
3265 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3272 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3274 struct vcpu_svm
*svm
= to_svm(vcpu
);
3275 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3277 control
->exit_int_info
= control
->event_inj
;
3278 control
->exit_int_info_err
= control
->event_inj_err
;
3279 control
->event_inj
= 0;
3280 svm_complete_interrupts(svm
);
3283 #ifdef CONFIG_X86_64
3289 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3291 struct vcpu_svm
*svm
= to_svm(vcpu
);
3296 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3297 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3298 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3301 * A vmexit emulation is required before the vcpu can be executed
3304 if (unlikely(svm
->nested
.exit_required
))
3309 sync_lapic_to_cr8(vcpu
);
3311 save_host_msrs(vcpu
);
3312 savesegment(fs
, fs_selector
);
3313 savesegment(gs
, gs_selector
);
3314 ldt_selector
= kvm_read_ldt();
3315 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3322 "push %%"R
"bp; \n\t"
3323 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3324 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3325 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3326 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3327 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3328 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3329 #ifdef CONFIG_X86_64
3330 "mov %c[r8](%[svm]), %%r8 \n\t"
3331 "mov %c[r9](%[svm]), %%r9 \n\t"
3332 "mov %c[r10](%[svm]), %%r10 \n\t"
3333 "mov %c[r11](%[svm]), %%r11 \n\t"
3334 "mov %c[r12](%[svm]), %%r12 \n\t"
3335 "mov %c[r13](%[svm]), %%r13 \n\t"
3336 "mov %c[r14](%[svm]), %%r14 \n\t"
3337 "mov %c[r15](%[svm]), %%r15 \n\t"
3340 /* Enter guest mode */
3342 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3343 __ex(SVM_VMLOAD
) "\n\t"
3344 __ex(SVM_VMRUN
) "\n\t"
3345 __ex(SVM_VMSAVE
) "\n\t"
3348 /* Save guest registers, load host registers */
3349 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3350 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3351 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3352 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3353 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3354 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3355 #ifdef CONFIG_X86_64
3356 "mov %%r8, %c[r8](%[svm]) \n\t"
3357 "mov %%r9, %c[r9](%[svm]) \n\t"
3358 "mov %%r10, %c[r10](%[svm]) \n\t"
3359 "mov %%r11, %c[r11](%[svm]) \n\t"
3360 "mov %%r12, %c[r12](%[svm]) \n\t"
3361 "mov %%r13, %c[r13](%[svm]) \n\t"
3362 "mov %%r14, %c[r14](%[svm]) \n\t"
3363 "mov %%r15, %c[r15](%[svm]) \n\t"
3368 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3369 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3370 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3371 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3372 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3373 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3374 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3375 #ifdef CONFIG_X86_64
3376 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3377 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3378 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3379 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3380 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3381 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3382 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3383 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3386 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3387 #ifdef CONFIG_X86_64
3388 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3392 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3393 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3394 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3395 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3397 load_host_msrs(vcpu
);
3398 kvm_load_ldt(ldt_selector
);
3399 loadsegment(fs
, fs_selector
);
3400 #ifdef CONFIG_X86_64
3401 load_gs_index(gs_selector
);
3402 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
3404 loadsegment(gs
, gs_selector
);
3409 local_irq_disable();
3413 sync_cr8_to_lapic(vcpu
);
3418 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3419 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3423 * We need to handle MC intercepts here before the vcpu has a chance to
3424 * change the physical cpu
3426 if (unlikely(svm
->vmcb
->control
.exit_code
==
3427 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3428 svm_handle_mce(svm
);
3433 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3435 struct vcpu_svm
*svm
= to_svm(vcpu
);
3437 svm
->vmcb
->save
.cr3
= root
;
3438 force_new_asid(vcpu
);
3441 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3443 struct vcpu_svm
*svm
= to_svm(vcpu
);
3445 svm
->vmcb
->control
.nested_cr3
= root
;
3447 /* Also sync guest cr3 here in case we live migrate */
3448 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3450 force_new_asid(vcpu
);
3453 static int is_disabled(void)
3457 rdmsrl(MSR_VM_CR
, vm_cr
);
3458 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3465 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3468 * Patch in the VMMCALL instruction:
3470 hypercall
[0] = 0x0f;
3471 hypercall
[1] = 0x01;
3472 hypercall
[2] = 0xd9;
3475 static void svm_check_processor_compat(void *rtn
)
3480 static bool svm_cpu_has_accelerated_tpr(void)
3485 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3490 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3494 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3499 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3502 entry
->eax
= 1; /* SVM revision 1 */
3503 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3504 ASID emulation to nested SVM */
3505 entry
->ecx
= 0; /* Reserved */
3506 entry
->edx
= 0; /* Per default do not support any
3507 additional features */
3509 /* Support next_rip if host supports it */
3510 if (svm_has(SVM_FEATURE_NRIP
))
3511 entry
->edx
|= SVM_FEATURE_NRIP
;
3513 /* Support NPT for the guest if enabled */
3515 entry
->edx
|= SVM_FEATURE_NPT
;
3521 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3522 { SVM_EXIT_READ_CR0
, "read_cr0" },
3523 { SVM_EXIT_READ_CR3
, "read_cr3" },
3524 { SVM_EXIT_READ_CR4
, "read_cr4" },
3525 { SVM_EXIT_READ_CR8
, "read_cr8" },
3526 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3527 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3528 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3529 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3530 { SVM_EXIT_READ_DR0
, "read_dr0" },
3531 { SVM_EXIT_READ_DR1
, "read_dr1" },
3532 { SVM_EXIT_READ_DR2
, "read_dr2" },
3533 { SVM_EXIT_READ_DR3
, "read_dr3" },
3534 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3535 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3536 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3537 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3538 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3539 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3540 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3541 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3542 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3543 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3544 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3545 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3546 { SVM_EXIT_INTR
, "interrupt" },
3547 { SVM_EXIT_NMI
, "nmi" },
3548 { SVM_EXIT_SMI
, "smi" },
3549 { SVM_EXIT_INIT
, "init" },
3550 { SVM_EXIT_VINTR
, "vintr" },
3551 { SVM_EXIT_CPUID
, "cpuid" },
3552 { SVM_EXIT_INVD
, "invd" },
3553 { SVM_EXIT_HLT
, "hlt" },
3554 { SVM_EXIT_INVLPG
, "invlpg" },
3555 { SVM_EXIT_INVLPGA
, "invlpga" },
3556 { SVM_EXIT_IOIO
, "io" },
3557 { SVM_EXIT_MSR
, "msr" },
3558 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3559 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3560 { SVM_EXIT_VMRUN
, "vmrun" },
3561 { SVM_EXIT_VMMCALL
, "hypercall" },
3562 { SVM_EXIT_VMLOAD
, "vmload" },
3563 { SVM_EXIT_VMSAVE
, "vmsave" },
3564 { SVM_EXIT_STGI
, "stgi" },
3565 { SVM_EXIT_CLGI
, "clgi" },
3566 { SVM_EXIT_SKINIT
, "skinit" },
3567 { SVM_EXIT_WBINVD
, "wbinvd" },
3568 { SVM_EXIT_MONITOR
, "monitor" },
3569 { SVM_EXIT_MWAIT
, "mwait" },
3570 { SVM_EXIT_NPF
, "npf" },
3574 static int svm_get_lpage_level(void)
3576 return PT_PDPE_LEVEL
;
3579 static bool svm_rdtscp_supported(void)
3584 static bool svm_has_wbinvd_exit(void)
3589 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3591 struct vcpu_svm
*svm
= to_svm(vcpu
);
3593 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3595 svm
->nested
.hsave
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3596 update_cr0_intercept(svm
);
3599 static struct kvm_x86_ops svm_x86_ops
= {
3600 .cpu_has_kvm_support
= has_svm
,
3601 .disabled_by_bios
= is_disabled
,
3602 .hardware_setup
= svm_hardware_setup
,
3603 .hardware_unsetup
= svm_hardware_unsetup
,
3604 .check_processor_compatibility
= svm_check_processor_compat
,
3605 .hardware_enable
= svm_hardware_enable
,
3606 .hardware_disable
= svm_hardware_disable
,
3607 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3609 .vcpu_create
= svm_create_vcpu
,
3610 .vcpu_free
= svm_free_vcpu
,
3611 .vcpu_reset
= svm_vcpu_reset
,
3613 .prepare_guest_switch
= svm_prepare_guest_switch
,
3614 .vcpu_load
= svm_vcpu_load
,
3615 .vcpu_put
= svm_vcpu_put
,
3617 .set_guest_debug
= svm_guest_debug
,
3618 .get_msr
= svm_get_msr
,
3619 .set_msr
= svm_set_msr
,
3620 .get_segment_base
= svm_get_segment_base
,
3621 .get_segment
= svm_get_segment
,
3622 .set_segment
= svm_set_segment
,
3623 .get_cpl
= svm_get_cpl
,
3624 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3625 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3626 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3627 .set_cr0
= svm_set_cr0
,
3628 .set_cr3
= svm_set_cr3
,
3629 .set_cr4
= svm_set_cr4
,
3630 .set_efer
= svm_set_efer
,
3631 .get_idt
= svm_get_idt
,
3632 .set_idt
= svm_set_idt
,
3633 .get_gdt
= svm_get_gdt
,
3634 .set_gdt
= svm_set_gdt
,
3635 .set_dr7
= svm_set_dr7
,
3636 .cache_reg
= svm_cache_reg
,
3637 .get_rflags
= svm_get_rflags
,
3638 .set_rflags
= svm_set_rflags
,
3639 .fpu_activate
= svm_fpu_activate
,
3640 .fpu_deactivate
= svm_fpu_deactivate
,
3642 .tlb_flush
= svm_flush_tlb
,
3644 .run
= svm_vcpu_run
,
3645 .handle_exit
= handle_exit
,
3646 .skip_emulated_instruction
= skip_emulated_instruction
,
3647 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3648 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3649 .patch_hypercall
= svm_patch_hypercall
,
3650 .set_irq
= svm_set_irq
,
3651 .set_nmi
= svm_inject_nmi
,
3652 .queue_exception
= svm_queue_exception
,
3653 .cancel_injection
= svm_cancel_injection
,
3654 .interrupt_allowed
= svm_interrupt_allowed
,
3655 .nmi_allowed
= svm_nmi_allowed
,
3656 .get_nmi_mask
= svm_get_nmi_mask
,
3657 .set_nmi_mask
= svm_set_nmi_mask
,
3658 .enable_nmi_window
= enable_nmi_window
,
3659 .enable_irq_window
= enable_irq_window
,
3660 .update_cr8_intercept
= update_cr8_intercept
,
3662 .set_tss_addr
= svm_set_tss_addr
,
3663 .get_tdp_level
= get_npt_level
,
3664 .get_mt_mask
= svm_get_mt_mask
,
3666 .exit_reasons_str
= svm_exit_reasons_str
,
3667 .get_lpage_level
= svm_get_lpage_level
,
3669 .cpuid_update
= svm_cpuid_update
,
3671 .rdtscp_supported
= svm_rdtscp_supported
,
3673 .set_supported_cpuid
= svm_set_supported_cpuid
,
3675 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3677 .write_tsc_offset
= svm_write_tsc_offset
,
3678 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3680 .set_tdp_cr3
= set_tdp_cr3
,
3683 static int __init
svm_init(void)
3685 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3686 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3689 static void __exit
svm_exit(void)
3694 module_init(svm_init
)
3695 module_exit(svm_exit
)