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KVM: SVM: Add clean-bit for IOPM_BASE and MSRPM_BASE
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_DIRTY_MAX,
193 };
194
195 #define VMCB_ALWAYS_DIRTY_MASK 0U
196
197 static inline void mark_all_dirty(struct vmcb *vmcb)
198 {
199 vmcb->control.clean = 0;
200 }
201
202 static inline void mark_all_clean(struct vmcb *vmcb)
203 {
204 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
205 & ~VMCB_ALWAYS_DIRTY_MASK;
206 }
207
208 static inline void mark_dirty(struct vmcb *vmcb, int bit)
209 {
210 vmcb->control.clean &= ~(1 << bit);
211 }
212
213 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
214 {
215 return container_of(vcpu, struct vcpu_svm, vcpu);
216 }
217
218 static void recalc_intercepts(struct vcpu_svm *svm)
219 {
220 struct vmcb_control_area *c, *h;
221 struct nested_state *g;
222
223 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
224
225 if (!is_guest_mode(&svm->vcpu))
226 return;
227
228 c = &svm->vmcb->control;
229 h = &svm->nested.hsave->control;
230 g = &svm->nested;
231
232 c->intercept_cr = h->intercept_cr | g->intercept_cr;
233 c->intercept_dr = h->intercept_dr | g->intercept_dr;
234 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
235 c->intercept = h->intercept | g->intercept;
236 }
237
238 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
239 {
240 if (is_guest_mode(&svm->vcpu))
241 return svm->nested.hsave;
242 else
243 return svm->vmcb;
244 }
245
246 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
247 {
248 struct vmcb *vmcb = get_host_vmcb(svm);
249
250 vmcb->control.intercept_cr |= (1U << bit);
251
252 recalc_intercepts(svm);
253 }
254
255 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
256 {
257 struct vmcb *vmcb = get_host_vmcb(svm);
258
259 vmcb->control.intercept_cr &= ~(1U << bit);
260
261 recalc_intercepts(svm);
262 }
263
264 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
265 {
266 struct vmcb *vmcb = get_host_vmcb(svm);
267
268 return vmcb->control.intercept_cr & (1U << bit);
269 }
270
271 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
272 {
273 struct vmcb *vmcb = get_host_vmcb(svm);
274
275 vmcb->control.intercept_dr |= (1U << bit);
276
277 recalc_intercepts(svm);
278 }
279
280 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
281 {
282 struct vmcb *vmcb = get_host_vmcb(svm);
283
284 vmcb->control.intercept_dr &= ~(1U << bit);
285
286 recalc_intercepts(svm);
287 }
288
289 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
290 {
291 struct vmcb *vmcb = get_host_vmcb(svm);
292
293 vmcb->control.intercept_exceptions |= (1U << bit);
294
295 recalc_intercepts(svm);
296 }
297
298 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
299 {
300 struct vmcb *vmcb = get_host_vmcb(svm);
301
302 vmcb->control.intercept_exceptions &= ~(1U << bit);
303
304 recalc_intercepts(svm);
305 }
306
307 static inline void set_intercept(struct vcpu_svm *svm, int bit)
308 {
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept |= (1ULL << bit);
312
313 recalc_intercepts(svm);
314 }
315
316 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
317 {
318 struct vmcb *vmcb = get_host_vmcb(svm);
319
320 vmcb->control.intercept &= ~(1ULL << bit);
321
322 recalc_intercepts(svm);
323 }
324
325 static inline void enable_gif(struct vcpu_svm *svm)
326 {
327 svm->vcpu.arch.hflags |= HF_GIF_MASK;
328 }
329
330 static inline void disable_gif(struct vcpu_svm *svm)
331 {
332 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
333 }
334
335 static inline bool gif_set(struct vcpu_svm *svm)
336 {
337 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
338 }
339
340 static unsigned long iopm_base;
341
342 struct kvm_ldttss_desc {
343 u16 limit0;
344 u16 base0;
345 unsigned base1:8, type:5, dpl:2, p:1;
346 unsigned limit1:4, zero0:3, g:1, base2:8;
347 u32 base3;
348 u32 zero1;
349 } __attribute__((packed));
350
351 struct svm_cpu_data {
352 int cpu;
353
354 u64 asid_generation;
355 u32 max_asid;
356 u32 next_asid;
357 struct kvm_ldttss_desc *tss_desc;
358
359 struct page *save_area;
360 };
361
362 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
363 static uint32_t svm_features;
364
365 struct svm_init_data {
366 int cpu;
367 int r;
368 };
369
370 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
371
372 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
373 #define MSRS_RANGE_SIZE 2048
374 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
375
376 static u32 svm_msrpm_offset(u32 msr)
377 {
378 u32 offset;
379 int i;
380
381 for (i = 0; i < NUM_MSR_MAPS; i++) {
382 if (msr < msrpm_ranges[i] ||
383 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
384 continue;
385
386 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
387 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
388
389 /* Now we have the u8 offset - but need the u32 offset */
390 return offset / 4;
391 }
392
393 /* MSR not in any range */
394 return MSR_INVALID;
395 }
396
397 #define MAX_INST_SIZE 15
398
399 static inline void clgi(void)
400 {
401 asm volatile (__ex(SVM_CLGI));
402 }
403
404 static inline void stgi(void)
405 {
406 asm volatile (__ex(SVM_STGI));
407 }
408
409 static inline void invlpga(unsigned long addr, u32 asid)
410 {
411 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
412 }
413
414 static inline void force_new_asid(struct kvm_vcpu *vcpu)
415 {
416 to_svm(vcpu)->asid_generation--;
417 }
418
419 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
420 {
421 force_new_asid(vcpu);
422 }
423
424 static int get_npt_level(void)
425 {
426 #ifdef CONFIG_X86_64
427 return PT64_ROOT_LEVEL;
428 #else
429 return PT32E_ROOT_LEVEL;
430 #endif
431 }
432
433 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
434 {
435 vcpu->arch.efer = efer;
436 if (!npt_enabled && !(efer & EFER_LMA))
437 efer &= ~EFER_LME;
438
439 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
440 }
441
442 static int is_external_interrupt(u32 info)
443 {
444 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
445 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
446 }
447
448 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
449 {
450 struct vcpu_svm *svm = to_svm(vcpu);
451 u32 ret = 0;
452
453 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
454 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
455 return ret & mask;
456 }
457
458 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
459 {
460 struct vcpu_svm *svm = to_svm(vcpu);
461
462 if (mask == 0)
463 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
464 else
465 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
466
467 }
468
469 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
470 {
471 struct vcpu_svm *svm = to_svm(vcpu);
472
473 if (svm->vmcb->control.next_rip != 0)
474 svm->next_rip = svm->vmcb->control.next_rip;
475
476 if (!svm->next_rip) {
477 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
478 EMULATE_DONE)
479 printk(KERN_DEBUG "%s: NOP\n", __func__);
480 return;
481 }
482 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
483 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
484 __func__, kvm_rip_read(vcpu), svm->next_rip);
485
486 kvm_rip_write(vcpu, svm->next_rip);
487 svm_set_interrupt_shadow(vcpu, 0);
488 }
489
490 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
491 bool has_error_code, u32 error_code,
492 bool reinject)
493 {
494 struct vcpu_svm *svm = to_svm(vcpu);
495
496 /*
497 * If we are within a nested VM we'd better #VMEXIT and let the guest
498 * handle the exception
499 */
500 if (!reinject &&
501 nested_svm_check_exception(svm, nr, has_error_code, error_code))
502 return;
503
504 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
505 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
506
507 /*
508 * For guest debugging where we have to reinject #BP if some
509 * INT3 is guest-owned:
510 * Emulate nRIP by moving RIP forward. Will fail if injection
511 * raises a fault that is not intercepted. Still better than
512 * failing in all cases.
513 */
514 skip_emulated_instruction(&svm->vcpu);
515 rip = kvm_rip_read(&svm->vcpu);
516 svm->int3_rip = rip + svm->vmcb->save.cs.base;
517 svm->int3_injected = rip - old_rip;
518 }
519
520 svm->vmcb->control.event_inj = nr
521 | SVM_EVTINJ_VALID
522 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
523 | SVM_EVTINJ_TYPE_EXEPT;
524 svm->vmcb->control.event_inj_err = error_code;
525 }
526
527 static void svm_init_erratum_383(void)
528 {
529 u32 low, high;
530 int err;
531 u64 val;
532
533 if (!cpu_has_amd_erratum(amd_erratum_383))
534 return;
535
536 /* Use _safe variants to not break nested virtualization */
537 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
538 if (err)
539 return;
540
541 val |= (1ULL << 47);
542
543 low = lower_32_bits(val);
544 high = upper_32_bits(val);
545
546 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
547
548 erratum_383_found = true;
549 }
550
551 static int has_svm(void)
552 {
553 const char *msg;
554
555 if (!cpu_has_svm(&msg)) {
556 printk(KERN_INFO "has_svm: %s\n", msg);
557 return 0;
558 }
559
560 return 1;
561 }
562
563 static void svm_hardware_disable(void *garbage)
564 {
565 cpu_svm_disable();
566 }
567
568 static int svm_hardware_enable(void *garbage)
569 {
570
571 struct svm_cpu_data *sd;
572 uint64_t efer;
573 struct desc_ptr gdt_descr;
574 struct desc_struct *gdt;
575 int me = raw_smp_processor_id();
576
577 rdmsrl(MSR_EFER, efer);
578 if (efer & EFER_SVME)
579 return -EBUSY;
580
581 if (!has_svm()) {
582 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
583 me);
584 return -EINVAL;
585 }
586 sd = per_cpu(svm_data, me);
587
588 if (!sd) {
589 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
590 me);
591 return -EINVAL;
592 }
593
594 sd->asid_generation = 1;
595 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
596 sd->next_asid = sd->max_asid + 1;
597
598 native_store_gdt(&gdt_descr);
599 gdt = (struct desc_struct *)gdt_descr.address;
600 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
601
602 wrmsrl(MSR_EFER, efer | EFER_SVME);
603
604 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
605
606 svm_init_erratum_383();
607
608 return 0;
609 }
610
611 static void svm_cpu_uninit(int cpu)
612 {
613 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
614
615 if (!sd)
616 return;
617
618 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
619 __free_page(sd->save_area);
620 kfree(sd);
621 }
622
623 static int svm_cpu_init(int cpu)
624 {
625 struct svm_cpu_data *sd;
626 int r;
627
628 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
629 if (!sd)
630 return -ENOMEM;
631 sd->cpu = cpu;
632 sd->save_area = alloc_page(GFP_KERNEL);
633 r = -ENOMEM;
634 if (!sd->save_area)
635 goto err_1;
636
637 per_cpu(svm_data, cpu) = sd;
638
639 return 0;
640
641 err_1:
642 kfree(sd);
643 return r;
644
645 }
646
647 static bool valid_msr_intercept(u32 index)
648 {
649 int i;
650
651 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
652 if (direct_access_msrs[i].index == index)
653 return true;
654
655 return false;
656 }
657
658 static void set_msr_interception(u32 *msrpm, unsigned msr,
659 int read, int write)
660 {
661 u8 bit_read, bit_write;
662 unsigned long tmp;
663 u32 offset;
664
665 /*
666 * If this warning triggers extend the direct_access_msrs list at the
667 * beginning of the file
668 */
669 WARN_ON(!valid_msr_intercept(msr));
670
671 offset = svm_msrpm_offset(msr);
672 bit_read = 2 * (msr & 0x0f);
673 bit_write = 2 * (msr & 0x0f) + 1;
674 tmp = msrpm[offset];
675
676 BUG_ON(offset == MSR_INVALID);
677
678 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
679 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
680
681 msrpm[offset] = tmp;
682 }
683
684 static void svm_vcpu_init_msrpm(u32 *msrpm)
685 {
686 int i;
687
688 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
689
690 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
691 if (!direct_access_msrs[i].always)
692 continue;
693
694 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
695 }
696 }
697
698 static void add_msr_offset(u32 offset)
699 {
700 int i;
701
702 for (i = 0; i < MSRPM_OFFSETS; ++i) {
703
704 /* Offset already in list? */
705 if (msrpm_offsets[i] == offset)
706 return;
707
708 /* Slot used by another offset? */
709 if (msrpm_offsets[i] != MSR_INVALID)
710 continue;
711
712 /* Add offset to list */
713 msrpm_offsets[i] = offset;
714
715 return;
716 }
717
718 /*
719 * If this BUG triggers the msrpm_offsets table has an overflow. Just
720 * increase MSRPM_OFFSETS in this case.
721 */
722 BUG();
723 }
724
725 static void init_msrpm_offsets(void)
726 {
727 int i;
728
729 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
730
731 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
732 u32 offset;
733
734 offset = svm_msrpm_offset(direct_access_msrs[i].index);
735 BUG_ON(offset == MSR_INVALID);
736
737 add_msr_offset(offset);
738 }
739 }
740
741 static void svm_enable_lbrv(struct vcpu_svm *svm)
742 {
743 u32 *msrpm = svm->msrpm;
744
745 svm->vmcb->control.lbr_ctl = 1;
746 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
747 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
748 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
749 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
750 }
751
752 static void svm_disable_lbrv(struct vcpu_svm *svm)
753 {
754 u32 *msrpm = svm->msrpm;
755
756 svm->vmcb->control.lbr_ctl = 0;
757 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
758 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
759 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
760 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
761 }
762
763 static __init int svm_hardware_setup(void)
764 {
765 int cpu;
766 struct page *iopm_pages;
767 void *iopm_va;
768 int r;
769
770 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
771
772 if (!iopm_pages)
773 return -ENOMEM;
774
775 iopm_va = page_address(iopm_pages);
776 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
777 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
778
779 init_msrpm_offsets();
780
781 if (boot_cpu_has(X86_FEATURE_NX))
782 kvm_enable_efer_bits(EFER_NX);
783
784 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
785 kvm_enable_efer_bits(EFER_FFXSR);
786
787 if (nested) {
788 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
789 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
790 }
791
792 for_each_possible_cpu(cpu) {
793 r = svm_cpu_init(cpu);
794 if (r)
795 goto err;
796 }
797
798 svm_features = cpuid_edx(SVM_CPUID_FUNC);
799
800 if (!boot_cpu_has(X86_FEATURE_NPT))
801 npt_enabled = false;
802
803 if (npt_enabled && !npt) {
804 printk(KERN_INFO "kvm: Nested Paging disabled\n");
805 npt_enabled = false;
806 }
807
808 if (npt_enabled) {
809 printk(KERN_INFO "kvm: Nested Paging enabled\n");
810 kvm_enable_tdp();
811 } else
812 kvm_disable_tdp();
813
814 return 0;
815
816 err:
817 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
818 iopm_base = 0;
819 return r;
820 }
821
822 static __exit void svm_hardware_unsetup(void)
823 {
824 int cpu;
825
826 for_each_possible_cpu(cpu)
827 svm_cpu_uninit(cpu);
828
829 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
830 iopm_base = 0;
831 }
832
833 static void init_seg(struct vmcb_seg *seg)
834 {
835 seg->selector = 0;
836 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
837 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
838 seg->limit = 0xffff;
839 seg->base = 0;
840 }
841
842 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
843 {
844 seg->selector = 0;
845 seg->attrib = SVM_SELECTOR_P_MASK | type;
846 seg->limit = 0xffff;
847 seg->base = 0;
848 }
849
850 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
851 {
852 struct vcpu_svm *svm = to_svm(vcpu);
853 u64 g_tsc_offset = 0;
854
855 if (is_guest_mode(vcpu)) {
856 g_tsc_offset = svm->vmcb->control.tsc_offset -
857 svm->nested.hsave->control.tsc_offset;
858 svm->nested.hsave->control.tsc_offset = offset;
859 }
860
861 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
862
863 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
864 }
865
866 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
867 {
868 struct vcpu_svm *svm = to_svm(vcpu);
869
870 svm->vmcb->control.tsc_offset += adjustment;
871 if (is_guest_mode(vcpu))
872 svm->nested.hsave->control.tsc_offset += adjustment;
873 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
874 }
875
876 static void init_vmcb(struct vcpu_svm *svm)
877 {
878 struct vmcb_control_area *control = &svm->vmcb->control;
879 struct vmcb_save_area *save = &svm->vmcb->save;
880
881 svm->vcpu.fpu_active = 1;
882 svm->vcpu.arch.hflags = 0;
883
884 set_cr_intercept(svm, INTERCEPT_CR0_READ);
885 set_cr_intercept(svm, INTERCEPT_CR3_READ);
886 set_cr_intercept(svm, INTERCEPT_CR4_READ);
887 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
888 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
889 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
890 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
891
892 set_dr_intercept(svm, INTERCEPT_DR0_READ);
893 set_dr_intercept(svm, INTERCEPT_DR1_READ);
894 set_dr_intercept(svm, INTERCEPT_DR2_READ);
895 set_dr_intercept(svm, INTERCEPT_DR3_READ);
896 set_dr_intercept(svm, INTERCEPT_DR4_READ);
897 set_dr_intercept(svm, INTERCEPT_DR5_READ);
898 set_dr_intercept(svm, INTERCEPT_DR6_READ);
899 set_dr_intercept(svm, INTERCEPT_DR7_READ);
900
901 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
902 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
903 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
904 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
909
910 set_exception_intercept(svm, PF_VECTOR);
911 set_exception_intercept(svm, UD_VECTOR);
912 set_exception_intercept(svm, MC_VECTOR);
913
914 set_intercept(svm, INTERCEPT_INTR);
915 set_intercept(svm, INTERCEPT_NMI);
916 set_intercept(svm, INTERCEPT_SMI);
917 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
918 set_intercept(svm, INTERCEPT_CPUID);
919 set_intercept(svm, INTERCEPT_INVD);
920 set_intercept(svm, INTERCEPT_HLT);
921 set_intercept(svm, INTERCEPT_INVLPG);
922 set_intercept(svm, INTERCEPT_INVLPGA);
923 set_intercept(svm, INTERCEPT_IOIO_PROT);
924 set_intercept(svm, INTERCEPT_MSR_PROT);
925 set_intercept(svm, INTERCEPT_TASK_SWITCH);
926 set_intercept(svm, INTERCEPT_SHUTDOWN);
927 set_intercept(svm, INTERCEPT_VMRUN);
928 set_intercept(svm, INTERCEPT_VMMCALL);
929 set_intercept(svm, INTERCEPT_VMLOAD);
930 set_intercept(svm, INTERCEPT_VMSAVE);
931 set_intercept(svm, INTERCEPT_STGI);
932 set_intercept(svm, INTERCEPT_CLGI);
933 set_intercept(svm, INTERCEPT_SKINIT);
934 set_intercept(svm, INTERCEPT_WBINVD);
935 set_intercept(svm, INTERCEPT_MONITOR);
936 set_intercept(svm, INTERCEPT_MWAIT);
937
938 control->iopm_base_pa = iopm_base;
939 control->msrpm_base_pa = __pa(svm->msrpm);
940 control->int_ctl = V_INTR_MASKING_MASK;
941
942 init_seg(&save->es);
943 init_seg(&save->ss);
944 init_seg(&save->ds);
945 init_seg(&save->fs);
946 init_seg(&save->gs);
947
948 save->cs.selector = 0xf000;
949 /* Executable/Readable Code Segment */
950 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
951 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
952 save->cs.limit = 0xffff;
953 /*
954 * cs.base should really be 0xffff0000, but vmx can't handle that, so
955 * be consistent with it.
956 *
957 * Replace when we have real mode working for vmx.
958 */
959 save->cs.base = 0xf0000;
960
961 save->gdtr.limit = 0xffff;
962 save->idtr.limit = 0xffff;
963
964 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
965 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
966
967 svm_set_efer(&svm->vcpu, 0);
968 save->dr6 = 0xffff0ff0;
969 save->dr7 = 0x400;
970 save->rflags = 2;
971 save->rip = 0x0000fff0;
972 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
973
974 /*
975 * This is the guest-visible cr0 value.
976 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
977 */
978 svm->vcpu.arch.cr0 = 0;
979 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
980
981 save->cr4 = X86_CR4_PAE;
982 /* rdx = ?? */
983
984 if (npt_enabled) {
985 /* Setup VMCB for Nested Paging */
986 control->nested_ctl = 1;
987 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
988 clr_intercept(svm, INTERCEPT_INVLPG);
989 clr_exception_intercept(svm, PF_VECTOR);
990 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
991 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
992 save->g_pat = 0x0007040600070406ULL;
993 save->cr3 = 0;
994 save->cr4 = 0;
995 }
996 force_new_asid(&svm->vcpu);
997
998 svm->nested.vmcb = 0;
999 svm->vcpu.arch.hflags = 0;
1000
1001 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1002 control->pause_filter_count = 3000;
1003 set_intercept(svm, INTERCEPT_PAUSE);
1004 }
1005
1006 mark_all_dirty(svm->vmcb);
1007
1008 enable_gif(svm);
1009 }
1010
1011 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1012 {
1013 struct vcpu_svm *svm = to_svm(vcpu);
1014
1015 init_vmcb(svm);
1016
1017 if (!kvm_vcpu_is_bsp(vcpu)) {
1018 kvm_rip_write(vcpu, 0);
1019 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1020 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1021 }
1022 vcpu->arch.regs_avail = ~0;
1023 vcpu->arch.regs_dirty = ~0;
1024
1025 return 0;
1026 }
1027
1028 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1029 {
1030 struct vcpu_svm *svm;
1031 struct page *page;
1032 struct page *msrpm_pages;
1033 struct page *hsave_page;
1034 struct page *nested_msrpm_pages;
1035 int err;
1036
1037 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1038 if (!svm) {
1039 err = -ENOMEM;
1040 goto out;
1041 }
1042
1043 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1044 if (err)
1045 goto free_svm;
1046
1047 err = -ENOMEM;
1048 page = alloc_page(GFP_KERNEL);
1049 if (!page)
1050 goto uninit;
1051
1052 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1053 if (!msrpm_pages)
1054 goto free_page1;
1055
1056 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1057 if (!nested_msrpm_pages)
1058 goto free_page2;
1059
1060 hsave_page = alloc_page(GFP_KERNEL);
1061 if (!hsave_page)
1062 goto free_page3;
1063
1064 svm->nested.hsave = page_address(hsave_page);
1065
1066 svm->msrpm = page_address(msrpm_pages);
1067 svm_vcpu_init_msrpm(svm->msrpm);
1068
1069 svm->nested.msrpm = page_address(nested_msrpm_pages);
1070 svm_vcpu_init_msrpm(svm->nested.msrpm);
1071
1072 svm->vmcb = page_address(page);
1073 clear_page(svm->vmcb);
1074 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1075 svm->asid_generation = 0;
1076 init_vmcb(svm);
1077 kvm_write_tsc(&svm->vcpu, 0);
1078
1079 err = fx_init(&svm->vcpu);
1080 if (err)
1081 goto free_page4;
1082
1083 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1084 if (kvm_vcpu_is_bsp(&svm->vcpu))
1085 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1086
1087 return &svm->vcpu;
1088
1089 free_page4:
1090 __free_page(hsave_page);
1091 free_page3:
1092 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1093 free_page2:
1094 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1095 free_page1:
1096 __free_page(page);
1097 uninit:
1098 kvm_vcpu_uninit(&svm->vcpu);
1099 free_svm:
1100 kmem_cache_free(kvm_vcpu_cache, svm);
1101 out:
1102 return ERR_PTR(err);
1103 }
1104
1105 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1106 {
1107 struct vcpu_svm *svm = to_svm(vcpu);
1108
1109 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1110 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1111 __free_page(virt_to_page(svm->nested.hsave));
1112 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1113 kvm_vcpu_uninit(vcpu);
1114 kmem_cache_free(kvm_vcpu_cache, svm);
1115 }
1116
1117 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1118 {
1119 struct vcpu_svm *svm = to_svm(vcpu);
1120 int i;
1121
1122 if (unlikely(cpu != vcpu->cpu)) {
1123 svm->asid_generation = 0;
1124 mark_all_dirty(svm->vmcb);
1125 }
1126
1127 #ifdef CONFIG_X86_64
1128 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1129 #endif
1130 savesegment(fs, svm->host.fs);
1131 savesegment(gs, svm->host.gs);
1132 svm->host.ldt = kvm_read_ldt();
1133
1134 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1135 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1136 }
1137
1138 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1139 {
1140 struct vcpu_svm *svm = to_svm(vcpu);
1141 int i;
1142
1143 ++vcpu->stat.host_state_reload;
1144 kvm_load_ldt(svm->host.ldt);
1145 #ifdef CONFIG_X86_64
1146 loadsegment(fs, svm->host.fs);
1147 load_gs_index(svm->host.gs);
1148 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1149 #else
1150 loadsegment(gs, svm->host.gs);
1151 #endif
1152 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1153 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1154 }
1155
1156 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1157 {
1158 return to_svm(vcpu)->vmcb->save.rflags;
1159 }
1160
1161 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1162 {
1163 to_svm(vcpu)->vmcb->save.rflags = rflags;
1164 }
1165
1166 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1167 {
1168 switch (reg) {
1169 case VCPU_EXREG_PDPTR:
1170 BUG_ON(!npt_enabled);
1171 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1172 break;
1173 default:
1174 BUG();
1175 }
1176 }
1177
1178 static void svm_set_vintr(struct vcpu_svm *svm)
1179 {
1180 set_intercept(svm, INTERCEPT_VINTR);
1181 }
1182
1183 static void svm_clear_vintr(struct vcpu_svm *svm)
1184 {
1185 clr_intercept(svm, INTERCEPT_VINTR);
1186 }
1187
1188 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1189 {
1190 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1191
1192 switch (seg) {
1193 case VCPU_SREG_CS: return &save->cs;
1194 case VCPU_SREG_DS: return &save->ds;
1195 case VCPU_SREG_ES: return &save->es;
1196 case VCPU_SREG_FS: return &save->fs;
1197 case VCPU_SREG_GS: return &save->gs;
1198 case VCPU_SREG_SS: return &save->ss;
1199 case VCPU_SREG_TR: return &save->tr;
1200 case VCPU_SREG_LDTR: return &save->ldtr;
1201 }
1202 BUG();
1203 return NULL;
1204 }
1205
1206 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1207 {
1208 struct vmcb_seg *s = svm_seg(vcpu, seg);
1209
1210 return s->base;
1211 }
1212
1213 static void svm_get_segment(struct kvm_vcpu *vcpu,
1214 struct kvm_segment *var, int seg)
1215 {
1216 struct vmcb_seg *s = svm_seg(vcpu, seg);
1217
1218 var->base = s->base;
1219 var->limit = s->limit;
1220 var->selector = s->selector;
1221 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1222 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1223 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1224 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1225 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1226 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1227 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1228 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1229
1230 /*
1231 * AMD's VMCB does not have an explicit unusable field, so emulate it
1232 * for cross vendor migration purposes by "not present"
1233 */
1234 var->unusable = !var->present || (var->type == 0);
1235
1236 switch (seg) {
1237 case VCPU_SREG_CS:
1238 /*
1239 * SVM always stores 0 for the 'G' bit in the CS selector in
1240 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1241 * Intel's VMENTRY has a check on the 'G' bit.
1242 */
1243 var->g = s->limit > 0xfffff;
1244 break;
1245 case VCPU_SREG_TR:
1246 /*
1247 * Work around a bug where the busy flag in the tr selector
1248 * isn't exposed
1249 */
1250 var->type |= 0x2;
1251 break;
1252 case VCPU_SREG_DS:
1253 case VCPU_SREG_ES:
1254 case VCPU_SREG_FS:
1255 case VCPU_SREG_GS:
1256 /*
1257 * The accessed bit must always be set in the segment
1258 * descriptor cache, although it can be cleared in the
1259 * descriptor, the cached bit always remains at 1. Since
1260 * Intel has a check on this, set it here to support
1261 * cross-vendor migration.
1262 */
1263 if (!var->unusable)
1264 var->type |= 0x1;
1265 break;
1266 case VCPU_SREG_SS:
1267 /*
1268 * On AMD CPUs sometimes the DB bit in the segment
1269 * descriptor is left as 1, although the whole segment has
1270 * been made unusable. Clear it here to pass an Intel VMX
1271 * entry check when cross vendor migrating.
1272 */
1273 if (var->unusable)
1274 var->db = 0;
1275 break;
1276 }
1277 }
1278
1279 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1280 {
1281 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1282
1283 return save->cpl;
1284 }
1285
1286 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1287 {
1288 struct vcpu_svm *svm = to_svm(vcpu);
1289
1290 dt->size = svm->vmcb->save.idtr.limit;
1291 dt->address = svm->vmcb->save.idtr.base;
1292 }
1293
1294 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1295 {
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297
1298 svm->vmcb->save.idtr.limit = dt->size;
1299 svm->vmcb->save.idtr.base = dt->address ;
1300 }
1301
1302 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1303 {
1304 struct vcpu_svm *svm = to_svm(vcpu);
1305
1306 dt->size = svm->vmcb->save.gdtr.limit;
1307 dt->address = svm->vmcb->save.gdtr.base;
1308 }
1309
1310 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1311 {
1312 struct vcpu_svm *svm = to_svm(vcpu);
1313
1314 svm->vmcb->save.gdtr.limit = dt->size;
1315 svm->vmcb->save.gdtr.base = dt->address ;
1316 }
1317
1318 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1319 {
1320 }
1321
1322 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1323 {
1324 }
1325
1326 static void update_cr0_intercept(struct vcpu_svm *svm)
1327 {
1328 ulong gcr0 = svm->vcpu.arch.cr0;
1329 u64 *hcr0 = &svm->vmcb->save.cr0;
1330
1331 if (!svm->vcpu.fpu_active)
1332 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1333 else
1334 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1335 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1336
1337
1338 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1339 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1340 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1341 } else {
1342 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1343 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1344 }
1345 }
1346
1347 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1348 {
1349 struct vcpu_svm *svm = to_svm(vcpu);
1350
1351 if (is_guest_mode(vcpu)) {
1352 /*
1353 * We are here because we run in nested mode, the host kvm
1354 * intercepts cr0 writes but the l1 hypervisor does not.
1355 * But the L1 hypervisor may intercept selective cr0 writes.
1356 * This needs to be checked here.
1357 */
1358 unsigned long old, new;
1359
1360 /* Remove bits that would trigger a real cr0 write intercept */
1361 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1362 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1363
1364 if (old == new) {
1365 /* cr0 write with ts and mp unchanged */
1366 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1367 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1368 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1369 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1370 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1371 return;
1372 }
1373 }
1374 }
1375
1376 #ifdef CONFIG_X86_64
1377 if (vcpu->arch.efer & EFER_LME) {
1378 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1379 vcpu->arch.efer |= EFER_LMA;
1380 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1381 }
1382
1383 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1384 vcpu->arch.efer &= ~EFER_LMA;
1385 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1386 }
1387 }
1388 #endif
1389 vcpu->arch.cr0 = cr0;
1390
1391 if (!npt_enabled)
1392 cr0 |= X86_CR0_PG | X86_CR0_WP;
1393
1394 if (!vcpu->fpu_active)
1395 cr0 |= X86_CR0_TS;
1396 /*
1397 * re-enable caching here because the QEMU bios
1398 * does not do it - this results in some delay at
1399 * reboot
1400 */
1401 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1402 svm->vmcb->save.cr0 = cr0;
1403 update_cr0_intercept(svm);
1404 }
1405
1406 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1407 {
1408 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1409 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1410
1411 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1412 force_new_asid(vcpu);
1413
1414 vcpu->arch.cr4 = cr4;
1415 if (!npt_enabled)
1416 cr4 |= X86_CR4_PAE;
1417 cr4 |= host_cr4_mce;
1418 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1419 }
1420
1421 static void svm_set_segment(struct kvm_vcpu *vcpu,
1422 struct kvm_segment *var, int seg)
1423 {
1424 struct vcpu_svm *svm = to_svm(vcpu);
1425 struct vmcb_seg *s = svm_seg(vcpu, seg);
1426
1427 s->base = var->base;
1428 s->limit = var->limit;
1429 s->selector = var->selector;
1430 if (var->unusable)
1431 s->attrib = 0;
1432 else {
1433 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1434 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1435 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1436 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1437 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1438 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1439 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1440 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1441 }
1442 if (seg == VCPU_SREG_CS)
1443 svm->vmcb->save.cpl
1444 = (svm->vmcb->save.cs.attrib
1445 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1446
1447 }
1448
1449 static void update_db_intercept(struct kvm_vcpu *vcpu)
1450 {
1451 struct vcpu_svm *svm = to_svm(vcpu);
1452
1453 clr_exception_intercept(svm, DB_VECTOR);
1454 clr_exception_intercept(svm, BP_VECTOR);
1455
1456 if (svm->nmi_singlestep)
1457 set_exception_intercept(svm, DB_VECTOR);
1458
1459 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1460 if (vcpu->guest_debug &
1461 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1462 set_exception_intercept(svm, DB_VECTOR);
1463 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1464 set_exception_intercept(svm, BP_VECTOR);
1465 } else
1466 vcpu->guest_debug = 0;
1467 }
1468
1469 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1470 {
1471 struct vcpu_svm *svm = to_svm(vcpu);
1472
1473 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1474 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1475 else
1476 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1477
1478 update_db_intercept(vcpu);
1479 }
1480
1481 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1482 {
1483 if (sd->next_asid > sd->max_asid) {
1484 ++sd->asid_generation;
1485 sd->next_asid = 1;
1486 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1487 }
1488
1489 svm->asid_generation = sd->asid_generation;
1490 svm->vmcb->control.asid = sd->next_asid++;
1491 }
1492
1493 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1494 {
1495 struct vcpu_svm *svm = to_svm(vcpu);
1496
1497 svm->vmcb->save.dr7 = value;
1498 }
1499
1500 static int pf_interception(struct vcpu_svm *svm)
1501 {
1502 u64 fault_address = svm->vmcb->control.exit_info_2;
1503 u32 error_code;
1504 int r = 1;
1505
1506 switch (svm->apf_reason) {
1507 default:
1508 error_code = svm->vmcb->control.exit_info_1;
1509
1510 trace_kvm_page_fault(fault_address, error_code);
1511 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1512 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1513 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1514 break;
1515 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1516 svm->apf_reason = 0;
1517 local_irq_disable();
1518 kvm_async_pf_task_wait(fault_address);
1519 local_irq_enable();
1520 break;
1521 case KVM_PV_REASON_PAGE_READY:
1522 svm->apf_reason = 0;
1523 local_irq_disable();
1524 kvm_async_pf_task_wake(fault_address);
1525 local_irq_enable();
1526 break;
1527 }
1528 return r;
1529 }
1530
1531 static int db_interception(struct vcpu_svm *svm)
1532 {
1533 struct kvm_run *kvm_run = svm->vcpu.run;
1534
1535 if (!(svm->vcpu.guest_debug &
1536 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1537 !svm->nmi_singlestep) {
1538 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1539 return 1;
1540 }
1541
1542 if (svm->nmi_singlestep) {
1543 svm->nmi_singlestep = false;
1544 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1545 svm->vmcb->save.rflags &=
1546 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1547 update_db_intercept(&svm->vcpu);
1548 }
1549
1550 if (svm->vcpu.guest_debug &
1551 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1552 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1553 kvm_run->debug.arch.pc =
1554 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1555 kvm_run->debug.arch.exception = DB_VECTOR;
1556 return 0;
1557 }
1558
1559 return 1;
1560 }
1561
1562 static int bp_interception(struct vcpu_svm *svm)
1563 {
1564 struct kvm_run *kvm_run = svm->vcpu.run;
1565
1566 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1567 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1568 kvm_run->debug.arch.exception = BP_VECTOR;
1569 return 0;
1570 }
1571
1572 static int ud_interception(struct vcpu_svm *svm)
1573 {
1574 int er;
1575
1576 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1577 if (er != EMULATE_DONE)
1578 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1579 return 1;
1580 }
1581
1582 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1583 {
1584 struct vcpu_svm *svm = to_svm(vcpu);
1585
1586 clr_exception_intercept(svm, NM_VECTOR);
1587
1588 svm->vcpu.fpu_active = 1;
1589 update_cr0_intercept(svm);
1590 }
1591
1592 static int nm_interception(struct vcpu_svm *svm)
1593 {
1594 svm_fpu_activate(&svm->vcpu);
1595 return 1;
1596 }
1597
1598 static bool is_erratum_383(void)
1599 {
1600 int err, i;
1601 u64 value;
1602
1603 if (!erratum_383_found)
1604 return false;
1605
1606 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1607 if (err)
1608 return false;
1609
1610 /* Bit 62 may or may not be set for this mce */
1611 value &= ~(1ULL << 62);
1612
1613 if (value != 0xb600000000010015ULL)
1614 return false;
1615
1616 /* Clear MCi_STATUS registers */
1617 for (i = 0; i < 6; ++i)
1618 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1619
1620 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1621 if (!err) {
1622 u32 low, high;
1623
1624 value &= ~(1ULL << 2);
1625 low = lower_32_bits(value);
1626 high = upper_32_bits(value);
1627
1628 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1629 }
1630
1631 /* Flush tlb to evict multi-match entries */
1632 __flush_tlb_all();
1633
1634 return true;
1635 }
1636
1637 static void svm_handle_mce(struct vcpu_svm *svm)
1638 {
1639 if (is_erratum_383()) {
1640 /*
1641 * Erratum 383 triggered. Guest state is corrupt so kill the
1642 * guest.
1643 */
1644 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1645
1646 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1647
1648 return;
1649 }
1650
1651 /*
1652 * On an #MC intercept the MCE handler is not called automatically in
1653 * the host. So do it by hand here.
1654 */
1655 asm volatile (
1656 "int $0x12\n");
1657 /* not sure if we ever come back to this point */
1658
1659 return;
1660 }
1661
1662 static int mc_interception(struct vcpu_svm *svm)
1663 {
1664 return 1;
1665 }
1666
1667 static int shutdown_interception(struct vcpu_svm *svm)
1668 {
1669 struct kvm_run *kvm_run = svm->vcpu.run;
1670
1671 /*
1672 * VMCB is undefined after a SHUTDOWN intercept
1673 * so reinitialize it.
1674 */
1675 clear_page(svm->vmcb);
1676 init_vmcb(svm);
1677
1678 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1679 return 0;
1680 }
1681
1682 static int io_interception(struct vcpu_svm *svm)
1683 {
1684 struct kvm_vcpu *vcpu = &svm->vcpu;
1685 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1686 int size, in, string;
1687 unsigned port;
1688
1689 ++svm->vcpu.stat.io_exits;
1690 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1691 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1692 if (string || in)
1693 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1694
1695 port = io_info >> 16;
1696 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1697 svm->next_rip = svm->vmcb->control.exit_info_2;
1698 skip_emulated_instruction(&svm->vcpu);
1699
1700 return kvm_fast_pio_out(vcpu, size, port);
1701 }
1702
1703 static int nmi_interception(struct vcpu_svm *svm)
1704 {
1705 return 1;
1706 }
1707
1708 static int intr_interception(struct vcpu_svm *svm)
1709 {
1710 ++svm->vcpu.stat.irq_exits;
1711 return 1;
1712 }
1713
1714 static int nop_on_interception(struct vcpu_svm *svm)
1715 {
1716 return 1;
1717 }
1718
1719 static int halt_interception(struct vcpu_svm *svm)
1720 {
1721 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1722 skip_emulated_instruction(&svm->vcpu);
1723 return kvm_emulate_halt(&svm->vcpu);
1724 }
1725
1726 static int vmmcall_interception(struct vcpu_svm *svm)
1727 {
1728 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1729 skip_emulated_instruction(&svm->vcpu);
1730 kvm_emulate_hypercall(&svm->vcpu);
1731 return 1;
1732 }
1733
1734 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1735 {
1736 struct vcpu_svm *svm = to_svm(vcpu);
1737
1738 return svm->nested.nested_cr3;
1739 }
1740
1741 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1742 unsigned long root)
1743 {
1744 struct vcpu_svm *svm = to_svm(vcpu);
1745
1746 svm->vmcb->control.nested_cr3 = root;
1747 force_new_asid(vcpu);
1748 }
1749
1750 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1751 struct x86_exception *fault)
1752 {
1753 struct vcpu_svm *svm = to_svm(vcpu);
1754
1755 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1756 svm->vmcb->control.exit_code_hi = 0;
1757 svm->vmcb->control.exit_info_1 = fault->error_code;
1758 svm->vmcb->control.exit_info_2 = fault->address;
1759
1760 nested_svm_vmexit(svm);
1761 }
1762
1763 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1764 {
1765 int r;
1766
1767 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1768
1769 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1770 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1771 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1772 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1773 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1774
1775 return r;
1776 }
1777
1778 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1779 {
1780 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1781 }
1782
1783 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1784 {
1785 if (!(svm->vcpu.arch.efer & EFER_SVME)
1786 || !is_paging(&svm->vcpu)) {
1787 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1788 return 1;
1789 }
1790
1791 if (svm->vmcb->save.cpl) {
1792 kvm_inject_gp(&svm->vcpu, 0);
1793 return 1;
1794 }
1795
1796 return 0;
1797 }
1798
1799 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1800 bool has_error_code, u32 error_code)
1801 {
1802 int vmexit;
1803
1804 if (!is_guest_mode(&svm->vcpu))
1805 return 0;
1806
1807 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1808 svm->vmcb->control.exit_code_hi = 0;
1809 svm->vmcb->control.exit_info_1 = error_code;
1810 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1811
1812 vmexit = nested_svm_intercept(svm);
1813 if (vmexit == NESTED_EXIT_DONE)
1814 svm->nested.exit_required = true;
1815
1816 return vmexit;
1817 }
1818
1819 /* This function returns true if it is save to enable the irq window */
1820 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1821 {
1822 if (!is_guest_mode(&svm->vcpu))
1823 return true;
1824
1825 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1826 return true;
1827
1828 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1829 return false;
1830
1831 /*
1832 * if vmexit was already requested (by intercepted exception
1833 * for instance) do not overwrite it with "external interrupt"
1834 * vmexit.
1835 */
1836 if (svm->nested.exit_required)
1837 return false;
1838
1839 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1840 svm->vmcb->control.exit_info_1 = 0;
1841 svm->vmcb->control.exit_info_2 = 0;
1842
1843 if (svm->nested.intercept & 1ULL) {
1844 /*
1845 * The #vmexit can't be emulated here directly because this
1846 * code path runs with irqs and preemtion disabled. A
1847 * #vmexit emulation might sleep. Only signal request for
1848 * the #vmexit here.
1849 */
1850 svm->nested.exit_required = true;
1851 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1852 return false;
1853 }
1854
1855 return true;
1856 }
1857
1858 /* This function returns true if it is save to enable the nmi window */
1859 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1860 {
1861 if (!is_guest_mode(&svm->vcpu))
1862 return true;
1863
1864 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1865 return true;
1866
1867 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1868 svm->nested.exit_required = true;
1869
1870 return false;
1871 }
1872
1873 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1874 {
1875 struct page *page;
1876
1877 might_sleep();
1878
1879 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1880 if (is_error_page(page))
1881 goto error;
1882
1883 *_page = page;
1884
1885 return kmap(page);
1886
1887 error:
1888 kvm_release_page_clean(page);
1889 kvm_inject_gp(&svm->vcpu, 0);
1890
1891 return NULL;
1892 }
1893
1894 static void nested_svm_unmap(struct page *page)
1895 {
1896 kunmap(page);
1897 kvm_release_page_dirty(page);
1898 }
1899
1900 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1901 {
1902 unsigned port;
1903 u8 val, bit;
1904 u64 gpa;
1905
1906 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1907 return NESTED_EXIT_HOST;
1908
1909 port = svm->vmcb->control.exit_info_1 >> 16;
1910 gpa = svm->nested.vmcb_iopm + (port / 8);
1911 bit = port % 8;
1912 val = 0;
1913
1914 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1915 val &= (1 << bit);
1916
1917 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1918 }
1919
1920 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1921 {
1922 u32 offset, msr, value;
1923 int write, mask;
1924
1925 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1926 return NESTED_EXIT_HOST;
1927
1928 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1929 offset = svm_msrpm_offset(msr);
1930 write = svm->vmcb->control.exit_info_1 & 1;
1931 mask = 1 << ((2 * (msr & 0xf)) + write);
1932
1933 if (offset == MSR_INVALID)
1934 return NESTED_EXIT_DONE;
1935
1936 /* Offset is in 32 bit units but need in 8 bit units */
1937 offset *= 4;
1938
1939 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1940 return NESTED_EXIT_DONE;
1941
1942 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1943 }
1944
1945 static int nested_svm_exit_special(struct vcpu_svm *svm)
1946 {
1947 u32 exit_code = svm->vmcb->control.exit_code;
1948
1949 switch (exit_code) {
1950 case SVM_EXIT_INTR:
1951 case SVM_EXIT_NMI:
1952 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1953 return NESTED_EXIT_HOST;
1954 case SVM_EXIT_NPF:
1955 /* For now we are always handling NPFs when using them */
1956 if (npt_enabled)
1957 return NESTED_EXIT_HOST;
1958 break;
1959 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1960 /* When we're shadowing, trap PFs, but not async PF */
1961 if (!npt_enabled && svm->apf_reason == 0)
1962 return NESTED_EXIT_HOST;
1963 break;
1964 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1965 nm_interception(svm);
1966 break;
1967 default:
1968 break;
1969 }
1970
1971 return NESTED_EXIT_CONTINUE;
1972 }
1973
1974 /*
1975 * If this function returns true, this #vmexit was already handled
1976 */
1977 static int nested_svm_intercept(struct vcpu_svm *svm)
1978 {
1979 u32 exit_code = svm->vmcb->control.exit_code;
1980 int vmexit = NESTED_EXIT_HOST;
1981
1982 switch (exit_code) {
1983 case SVM_EXIT_MSR:
1984 vmexit = nested_svm_exit_handled_msr(svm);
1985 break;
1986 case SVM_EXIT_IOIO:
1987 vmexit = nested_svm_intercept_ioio(svm);
1988 break;
1989 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1990 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1991 if (svm->nested.intercept_cr & bit)
1992 vmexit = NESTED_EXIT_DONE;
1993 break;
1994 }
1995 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
1996 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
1997 if (svm->nested.intercept_dr & bit)
1998 vmexit = NESTED_EXIT_DONE;
1999 break;
2000 }
2001 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2002 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2003 if (svm->nested.intercept_exceptions & excp_bits)
2004 vmexit = NESTED_EXIT_DONE;
2005 /* async page fault always cause vmexit */
2006 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2007 svm->apf_reason != 0)
2008 vmexit = NESTED_EXIT_DONE;
2009 break;
2010 }
2011 case SVM_EXIT_ERR: {
2012 vmexit = NESTED_EXIT_DONE;
2013 break;
2014 }
2015 default: {
2016 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2017 if (svm->nested.intercept & exit_bits)
2018 vmexit = NESTED_EXIT_DONE;
2019 }
2020 }
2021
2022 return vmexit;
2023 }
2024
2025 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2026 {
2027 int vmexit;
2028
2029 vmexit = nested_svm_intercept(svm);
2030
2031 if (vmexit == NESTED_EXIT_DONE)
2032 nested_svm_vmexit(svm);
2033
2034 return vmexit;
2035 }
2036
2037 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2038 {
2039 struct vmcb_control_area *dst = &dst_vmcb->control;
2040 struct vmcb_control_area *from = &from_vmcb->control;
2041
2042 dst->intercept_cr = from->intercept_cr;
2043 dst->intercept_dr = from->intercept_dr;
2044 dst->intercept_exceptions = from->intercept_exceptions;
2045 dst->intercept = from->intercept;
2046 dst->iopm_base_pa = from->iopm_base_pa;
2047 dst->msrpm_base_pa = from->msrpm_base_pa;
2048 dst->tsc_offset = from->tsc_offset;
2049 dst->asid = from->asid;
2050 dst->tlb_ctl = from->tlb_ctl;
2051 dst->int_ctl = from->int_ctl;
2052 dst->int_vector = from->int_vector;
2053 dst->int_state = from->int_state;
2054 dst->exit_code = from->exit_code;
2055 dst->exit_code_hi = from->exit_code_hi;
2056 dst->exit_info_1 = from->exit_info_1;
2057 dst->exit_info_2 = from->exit_info_2;
2058 dst->exit_int_info = from->exit_int_info;
2059 dst->exit_int_info_err = from->exit_int_info_err;
2060 dst->nested_ctl = from->nested_ctl;
2061 dst->event_inj = from->event_inj;
2062 dst->event_inj_err = from->event_inj_err;
2063 dst->nested_cr3 = from->nested_cr3;
2064 dst->lbr_ctl = from->lbr_ctl;
2065 }
2066
2067 static int nested_svm_vmexit(struct vcpu_svm *svm)
2068 {
2069 struct vmcb *nested_vmcb;
2070 struct vmcb *hsave = svm->nested.hsave;
2071 struct vmcb *vmcb = svm->vmcb;
2072 struct page *page;
2073
2074 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2075 vmcb->control.exit_info_1,
2076 vmcb->control.exit_info_2,
2077 vmcb->control.exit_int_info,
2078 vmcb->control.exit_int_info_err);
2079
2080 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2081 if (!nested_vmcb)
2082 return 1;
2083
2084 /* Exit Guest-Mode */
2085 leave_guest_mode(&svm->vcpu);
2086 svm->nested.vmcb = 0;
2087
2088 /* Give the current vmcb to the guest */
2089 disable_gif(svm);
2090
2091 nested_vmcb->save.es = vmcb->save.es;
2092 nested_vmcb->save.cs = vmcb->save.cs;
2093 nested_vmcb->save.ss = vmcb->save.ss;
2094 nested_vmcb->save.ds = vmcb->save.ds;
2095 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2096 nested_vmcb->save.idtr = vmcb->save.idtr;
2097 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2098 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2099 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2100 nested_vmcb->save.cr2 = vmcb->save.cr2;
2101 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2102 nested_vmcb->save.rflags = vmcb->save.rflags;
2103 nested_vmcb->save.rip = vmcb->save.rip;
2104 nested_vmcb->save.rsp = vmcb->save.rsp;
2105 nested_vmcb->save.rax = vmcb->save.rax;
2106 nested_vmcb->save.dr7 = vmcb->save.dr7;
2107 nested_vmcb->save.dr6 = vmcb->save.dr6;
2108 nested_vmcb->save.cpl = vmcb->save.cpl;
2109
2110 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2111 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2112 nested_vmcb->control.int_state = vmcb->control.int_state;
2113 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2114 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2115 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2116 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2117 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2118 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2119 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2120
2121 /*
2122 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2123 * to make sure that we do not lose injected events. So check event_inj
2124 * here and copy it to exit_int_info if it is valid.
2125 * Exit_int_info and event_inj can't be both valid because the case
2126 * below only happens on a VMRUN instruction intercept which has
2127 * no valid exit_int_info set.
2128 */
2129 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2130 struct vmcb_control_area *nc = &nested_vmcb->control;
2131
2132 nc->exit_int_info = vmcb->control.event_inj;
2133 nc->exit_int_info_err = vmcb->control.event_inj_err;
2134 }
2135
2136 nested_vmcb->control.tlb_ctl = 0;
2137 nested_vmcb->control.event_inj = 0;
2138 nested_vmcb->control.event_inj_err = 0;
2139
2140 /* We always set V_INTR_MASKING and remember the old value in hflags */
2141 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2142 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2143
2144 /* Restore the original control entries */
2145 copy_vmcb_control_area(vmcb, hsave);
2146
2147 kvm_clear_exception_queue(&svm->vcpu);
2148 kvm_clear_interrupt_queue(&svm->vcpu);
2149
2150 svm->nested.nested_cr3 = 0;
2151
2152 /* Restore selected save entries */
2153 svm->vmcb->save.es = hsave->save.es;
2154 svm->vmcb->save.cs = hsave->save.cs;
2155 svm->vmcb->save.ss = hsave->save.ss;
2156 svm->vmcb->save.ds = hsave->save.ds;
2157 svm->vmcb->save.gdtr = hsave->save.gdtr;
2158 svm->vmcb->save.idtr = hsave->save.idtr;
2159 svm->vmcb->save.rflags = hsave->save.rflags;
2160 svm_set_efer(&svm->vcpu, hsave->save.efer);
2161 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2162 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2163 if (npt_enabled) {
2164 svm->vmcb->save.cr3 = hsave->save.cr3;
2165 svm->vcpu.arch.cr3 = hsave->save.cr3;
2166 } else {
2167 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2168 }
2169 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2170 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2171 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2172 svm->vmcb->save.dr7 = 0;
2173 svm->vmcb->save.cpl = 0;
2174 svm->vmcb->control.exit_int_info = 0;
2175
2176 mark_all_dirty(svm->vmcb);
2177
2178 nested_svm_unmap(page);
2179
2180 nested_svm_uninit_mmu_context(&svm->vcpu);
2181 kvm_mmu_reset_context(&svm->vcpu);
2182 kvm_mmu_load(&svm->vcpu);
2183
2184 return 0;
2185 }
2186
2187 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2188 {
2189 /*
2190 * This function merges the msr permission bitmaps of kvm and the
2191 * nested vmcb. It is omptimized in that it only merges the parts where
2192 * the kvm msr permission bitmap may contain zero bits
2193 */
2194 int i;
2195
2196 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2197 return true;
2198
2199 for (i = 0; i < MSRPM_OFFSETS; i++) {
2200 u32 value, p;
2201 u64 offset;
2202
2203 if (msrpm_offsets[i] == 0xffffffff)
2204 break;
2205
2206 p = msrpm_offsets[i];
2207 offset = svm->nested.vmcb_msrpm + (p * 4);
2208
2209 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2210 return false;
2211
2212 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2213 }
2214
2215 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2216
2217 return true;
2218 }
2219
2220 static bool nested_vmcb_checks(struct vmcb *vmcb)
2221 {
2222 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2223 return false;
2224
2225 if (vmcb->control.asid == 0)
2226 return false;
2227
2228 if (vmcb->control.nested_ctl && !npt_enabled)
2229 return false;
2230
2231 return true;
2232 }
2233
2234 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2235 {
2236 struct vmcb *nested_vmcb;
2237 struct vmcb *hsave = svm->nested.hsave;
2238 struct vmcb *vmcb = svm->vmcb;
2239 struct page *page;
2240 u64 vmcb_gpa;
2241
2242 vmcb_gpa = svm->vmcb->save.rax;
2243
2244 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2245 if (!nested_vmcb)
2246 return false;
2247
2248 if (!nested_vmcb_checks(nested_vmcb)) {
2249 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2250 nested_vmcb->control.exit_code_hi = 0;
2251 nested_vmcb->control.exit_info_1 = 0;
2252 nested_vmcb->control.exit_info_2 = 0;
2253
2254 nested_svm_unmap(page);
2255
2256 return false;
2257 }
2258
2259 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2260 nested_vmcb->save.rip,
2261 nested_vmcb->control.int_ctl,
2262 nested_vmcb->control.event_inj,
2263 nested_vmcb->control.nested_ctl);
2264
2265 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2266 nested_vmcb->control.intercept_cr >> 16,
2267 nested_vmcb->control.intercept_exceptions,
2268 nested_vmcb->control.intercept);
2269
2270 /* Clear internal status */
2271 kvm_clear_exception_queue(&svm->vcpu);
2272 kvm_clear_interrupt_queue(&svm->vcpu);
2273
2274 /*
2275 * Save the old vmcb, so we don't need to pick what we save, but can
2276 * restore everything when a VMEXIT occurs
2277 */
2278 hsave->save.es = vmcb->save.es;
2279 hsave->save.cs = vmcb->save.cs;
2280 hsave->save.ss = vmcb->save.ss;
2281 hsave->save.ds = vmcb->save.ds;
2282 hsave->save.gdtr = vmcb->save.gdtr;
2283 hsave->save.idtr = vmcb->save.idtr;
2284 hsave->save.efer = svm->vcpu.arch.efer;
2285 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2286 hsave->save.cr4 = svm->vcpu.arch.cr4;
2287 hsave->save.rflags = vmcb->save.rflags;
2288 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2289 hsave->save.rsp = vmcb->save.rsp;
2290 hsave->save.rax = vmcb->save.rax;
2291 if (npt_enabled)
2292 hsave->save.cr3 = vmcb->save.cr3;
2293 else
2294 hsave->save.cr3 = svm->vcpu.arch.cr3;
2295
2296 copy_vmcb_control_area(hsave, vmcb);
2297
2298 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2299 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2300 else
2301 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2302
2303 if (nested_vmcb->control.nested_ctl) {
2304 kvm_mmu_unload(&svm->vcpu);
2305 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2306 nested_svm_init_mmu_context(&svm->vcpu);
2307 }
2308
2309 /* Load the nested guest state */
2310 svm->vmcb->save.es = nested_vmcb->save.es;
2311 svm->vmcb->save.cs = nested_vmcb->save.cs;
2312 svm->vmcb->save.ss = nested_vmcb->save.ss;
2313 svm->vmcb->save.ds = nested_vmcb->save.ds;
2314 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2315 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2316 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2317 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2318 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2319 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2320 if (npt_enabled) {
2321 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2322 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2323 } else
2324 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2325
2326 /* Guest paging mode is active - reset mmu */
2327 kvm_mmu_reset_context(&svm->vcpu);
2328
2329 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2330 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2331 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2332 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2333
2334 /* In case we don't even reach vcpu_run, the fields are not updated */
2335 svm->vmcb->save.rax = nested_vmcb->save.rax;
2336 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2337 svm->vmcb->save.rip = nested_vmcb->save.rip;
2338 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2339 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2340 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2341
2342 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2343 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2344
2345 /* cache intercepts */
2346 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2347 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2348 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2349 svm->nested.intercept = nested_vmcb->control.intercept;
2350
2351 force_new_asid(&svm->vcpu);
2352 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2353 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2354 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2355 else
2356 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2357
2358 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2359 /* We only want the cr8 intercept bits of the guest */
2360 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2361 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2362 }
2363
2364 /* We don't want to see VMMCALLs from a nested guest */
2365 clr_intercept(svm, INTERCEPT_VMMCALL);
2366
2367 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2368 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2369 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2370 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2371 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2372 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2373
2374 nested_svm_unmap(page);
2375
2376 /* Enter Guest-Mode */
2377 enter_guest_mode(&svm->vcpu);
2378
2379 /*
2380 * Merge guest and host intercepts - must be called with vcpu in
2381 * guest-mode to take affect here
2382 */
2383 recalc_intercepts(svm);
2384
2385 svm->nested.vmcb = vmcb_gpa;
2386
2387 enable_gif(svm);
2388
2389 mark_all_dirty(svm->vmcb);
2390
2391 return true;
2392 }
2393
2394 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2395 {
2396 to_vmcb->save.fs = from_vmcb->save.fs;
2397 to_vmcb->save.gs = from_vmcb->save.gs;
2398 to_vmcb->save.tr = from_vmcb->save.tr;
2399 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2400 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2401 to_vmcb->save.star = from_vmcb->save.star;
2402 to_vmcb->save.lstar = from_vmcb->save.lstar;
2403 to_vmcb->save.cstar = from_vmcb->save.cstar;
2404 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2405 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2406 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2407 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2408 }
2409
2410 static int vmload_interception(struct vcpu_svm *svm)
2411 {
2412 struct vmcb *nested_vmcb;
2413 struct page *page;
2414
2415 if (nested_svm_check_permissions(svm))
2416 return 1;
2417
2418 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2419 skip_emulated_instruction(&svm->vcpu);
2420
2421 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2422 if (!nested_vmcb)
2423 return 1;
2424
2425 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2426 nested_svm_unmap(page);
2427
2428 return 1;
2429 }
2430
2431 static int vmsave_interception(struct vcpu_svm *svm)
2432 {
2433 struct vmcb *nested_vmcb;
2434 struct page *page;
2435
2436 if (nested_svm_check_permissions(svm))
2437 return 1;
2438
2439 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2440 skip_emulated_instruction(&svm->vcpu);
2441
2442 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2443 if (!nested_vmcb)
2444 return 1;
2445
2446 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2447 nested_svm_unmap(page);
2448
2449 return 1;
2450 }
2451
2452 static int vmrun_interception(struct vcpu_svm *svm)
2453 {
2454 if (nested_svm_check_permissions(svm))
2455 return 1;
2456
2457 /* Save rip after vmrun instruction */
2458 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2459
2460 if (!nested_svm_vmrun(svm))
2461 return 1;
2462
2463 if (!nested_svm_vmrun_msrpm(svm))
2464 goto failed;
2465
2466 return 1;
2467
2468 failed:
2469
2470 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2471 svm->vmcb->control.exit_code_hi = 0;
2472 svm->vmcb->control.exit_info_1 = 0;
2473 svm->vmcb->control.exit_info_2 = 0;
2474
2475 nested_svm_vmexit(svm);
2476
2477 return 1;
2478 }
2479
2480 static int stgi_interception(struct vcpu_svm *svm)
2481 {
2482 if (nested_svm_check_permissions(svm))
2483 return 1;
2484
2485 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2486 skip_emulated_instruction(&svm->vcpu);
2487 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2488
2489 enable_gif(svm);
2490
2491 return 1;
2492 }
2493
2494 static int clgi_interception(struct vcpu_svm *svm)
2495 {
2496 if (nested_svm_check_permissions(svm))
2497 return 1;
2498
2499 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2500 skip_emulated_instruction(&svm->vcpu);
2501
2502 disable_gif(svm);
2503
2504 /* After a CLGI no interrupts should come */
2505 svm_clear_vintr(svm);
2506 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2507
2508 return 1;
2509 }
2510
2511 static int invlpga_interception(struct vcpu_svm *svm)
2512 {
2513 struct kvm_vcpu *vcpu = &svm->vcpu;
2514
2515 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2516 vcpu->arch.regs[VCPU_REGS_RAX]);
2517
2518 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2519 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2520
2521 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2522 skip_emulated_instruction(&svm->vcpu);
2523 return 1;
2524 }
2525
2526 static int skinit_interception(struct vcpu_svm *svm)
2527 {
2528 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2529
2530 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2531 return 1;
2532 }
2533
2534 static int invalid_op_interception(struct vcpu_svm *svm)
2535 {
2536 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2537 return 1;
2538 }
2539
2540 static int task_switch_interception(struct vcpu_svm *svm)
2541 {
2542 u16 tss_selector;
2543 int reason;
2544 int int_type = svm->vmcb->control.exit_int_info &
2545 SVM_EXITINTINFO_TYPE_MASK;
2546 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2547 uint32_t type =
2548 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2549 uint32_t idt_v =
2550 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2551 bool has_error_code = false;
2552 u32 error_code = 0;
2553
2554 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2555
2556 if (svm->vmcb->control.exit_info_2 &
2557 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2558 reason = TASK_SWITCH_IRET;
2559 else if (svm->vmcb->control.exit_info_2 &
2560 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2561 reason = TASK_SWITCH_JMP;
2562 else if (idt_v)
2563 reason = TASK_SWITCH_GATE;
2564 else
2565 reason = TASK_SWITCH_CALL;
2566
2567 if (reason == TASK_SWITCH_GATE) {
2568 switch (type) {
2569 case SVM_EXITINTINFO_TYPE_NMI:
2570 svm->vcpu.arch.nmi_injected = false;
2571 break;
2572 case SVM_EXITINTINFO_TYPE_EXEPT:
2573 if (svm->vmcb->control.exit_info_2 &
2574 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2575 has_error_code = true;
2576 error_code =
2577 (u32)svm->vmcb->control.exit_info_2;
2578 }
2579 kvm_clear_exception_queue(&svm->vcpu);
2580 break;
2581 case SVM_EXITINTINFO_TYPE_INTR:
2582 kvm_clear_interrupt_queue(&svm->vcpu);
2583 break;
2584 default:
2585 break;
2586 }
2587 }
2588
2589 if (reason != TASK_SWITCH_GATE ||
2590 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2591 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2592 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2593 skip_emulated_instruction(&svm->vcpu);
2594
2595 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2596 has_error_code, error_code) == EMULATE_FAIL) {
2597 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2598 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2599 svm->vcpu.run->internal.ndata = 0;
2600 return 0;
2601 }
2602 return 1;
2603 }
2604
2605 static int cpuid_interception(struct vcpu_svm *svm)
2606 {
2607 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2608 kvm_emulate_cpuid(&svm->vcpu);
2609 return 1;
2610 }
2611
2612 static int iret_interception(struct vcpu_svm *svm)
2613 {
2614 ++svm->vcpu.stat.nmi_window_exits;
2615 clr_intercept(svm, INTERCEPT_IRET);
2616 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2617 return 1;
2618 }
2619
2620 static int invlpg_interception(struct vcpu_svm *svm)
2621 {
2622 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2623 }
2624
2625 static int emulate_on_interception(struct vcpu_svm *svm)
2626 {
2627 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2628 }
2629
2630 static int cr0_write_interception(struct vcpu_svm *svm)
2631 {
2632 struct kvm_vcpu *vcpu = &svm->vcpu;
2633 int r;
2634
2635 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2636
2637 if (svm->nested.vmexit_rip) {
2638 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2639 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2640 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2641 svm->nested.vmexit_rip = 0;
2642 }
2643
2644 return r == EMULATE_DONE;
2645 }
2646
2647 static int cr8_write_interception(struct vcpu_svm *svm)
2648 {
2649 struct kvm_run *kvm_run = svm->vcpu.run;
2650
2651 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2652 /* instruction emulation calls kvm_set_cr8() */
2653 emulate_instruction(&svm->vcpu, 0, 0, 0);
2654 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2655 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2656 return 1;
2657 }
2658 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2659 return 1;
2660 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2661 return 0;
2662 }
2663
2664 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2665 {
2666 struct vcpu_svm *svm = to_svm(vcpu);
2667
2668 switch (ecx) {
2669 case MSR_IA32_TSC: {
2670 struct vmcb *vmcb = get_host_vmcb(svm);
2671
2672 *data = vmcb->control.tsc_offset + native_read_tsc();
2673 break;
2674 }
2675 case MSR_STAR:
2676 *data = svm->vmcb->save.star;
2677 break;
2678 #ifdef CONFIG_X86_64
2679 case MSR_LSTAR:
2680 *data = svm->vmcb->save.lstar;
2681 break;
2682 case MSR_CSTAR:
2683 *data = svm->vmcb->save.cstar;
2684 break;
2685 case MSR_KERNEL_GS_BASE:
2686 *data = svm->vmcb->save.kernel_gs_base;
2687 break;
2688 case MSR_SYSCALL_MASK:
2689 *data = svm->vmcb->save.sfmask;
2690 break;
2691 #endif
2692 case MSR_IA32_SYSENTER_CS:
2693 *data = svm->vmcb->save.sysenter_cs;
2694 break;
2695 case MSR_IA32_SYSENTER_EIP:
2696 *data = svm->sysenter_eip;
2697 break;
2698 case MSR_IA32_SYSENTER_ESP:
2699 *data = svm->sysenter_esp;
2700 break;
2701 /*
2702 * Nobody will change the following 5 values in the VMCB so we can
2703 * safely return them on rdmsr. They will always be 0 until LBRV is
2704 * implemented.
2705 */
2706 case MSR_IA32_DEBUGCTLMSR:
2707 *data = svm->vmcb->save.dbgctl;
2708 break;
2709 case MSR_IA32_LASTBRANCHFROMIP:
2710 *data = svm->vmcb->save.br_from;
2711 break;
2712 case MSR_IA32_LASTBRANCHTOIP:
2713 *data = svm->vmcb->save.br_to;
2714 break;
2715 case MSR_IA32_LASTINTFROMIP:
2716 *data = svm->vmcb->save.last_excp_from;
2717 break;
2718 case MSR_IA32_LASTINTTOIP:
2719 *data = svm->vmcb->save.last_excp_to;
2720 break;
2721 case MSR_VM_HSAVE_PA:
2722 *data = svm->nested.hsave_msr;
2723 break;
2724 case MSR_VM_CR:
2725 *data = svm->nested.vm_cr_msr;
2726 break;
2727 case MSR_IA32_UCODE_REV:
2728 *data = 0x01000065;
2729 break;
2730 default:
2731 return kvm_get_msr_common(vcpu, ecx, data);
2732 }
2733 return 0;
2734 }
2735
2736 static int rdmsr_interception(struct vcpu_svm *svm)
2737 {
2738 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2739 u64 data;
2740
2741 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2742 trace_kvm_msr_read_ex(ecx);
2743 kvm_inject_gp(&svm->vcpu, 0);
2744 } else {
2745 trace_kvm_msr_read(ecx, data);
2746
2747 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2748 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2749 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2750 skip_emulated_instruction(&svm->vcpu);
2751 }
2752 return 1;
2753 }
2754
2755 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2756 {
2757 struct vcpu_svm *svm = to_svm(vcpu);
2758 int svm_dis, chg_mask;
2759
2760 if (data & ~SVM_VM_CR_VALID_MASK)
2761 return 1;
2762
2763 chg_mask = SVM_VM_CR_VALID_MASK;
2764
2765 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2766 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2767
2768 svm->nested.vm_cr_msr &= ~chg_mask;
2769 svm->nested.vm_cr_msr |= (data & chg_mask);
2770
2771 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2772
2773 /* check for svm_disable while efer.svme is set */
2774 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2775 return 1;
2776
2777 return 0;
2778 }
2779
2780 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2781 {
2782 struct vcpu_svm *svm = to_svm(vcpu);
2783
2784 switch (ecx) {
2785 case MSR_IA32_TSC:
2786 kvm_write_tsc(vcpu, data);
2787 break;
2788 case MSR_STAR:
2789 svm->vmcb->save.star = data;
2790 break;
2791 #ifdef CONFIG_X86_64
2792 case MSR_LSTAR:
2793 svm->vmcb->save.lstar = data;
2794 break;
2795 case MSR_CSTAR:
2796 svm->vmcb->save.cstar = data;
2797 break;
2798 case MSR_KERNEL_GS_BASE:
2799 svm->vmcb->save.kernel_gs_base = data;
2800 break;
2801 case MSR_SYSCALL_MASK:
2802 svm->vmcb->save.sfmask = data;
2803 break;
2804 #endif
2805 case MSR_IA32_SYSENTER_CS:
2806 svm->vmcb->save.sysenter_cs = data;
2807 break;
2808 case MSR_IA32_SYSENTER_EIP:
2809 svm->sysenter_eip = data;
2810 svm->vmcb->save.sysenter_eip = data;
2811 break;
2812 case MSR_IA32_SYSENTER_ESP:
2813 svm->sysenter_esp = data;
2814 svm->vmcb->save.sysenter_esp = data;
2815 break;
2816 case MSR_IA32_DEBUGCTLMSR:
2817 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2818 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2819 __func__, data);
2820 break;
2821 }
2822 if (data & DEBUGCTL_RESERVED_BITS)
2823 return 1;
2824
2825 svm->vmcb->save.dbgctl = data;
2826 if (data & (1ULL<<0))
2827 svm_enable_lbrv(svm);
2828 else
2829 svm_disable_lbrv(svm);
2830 break;
2831 case MSR_VM_HSAVE_PA:
2832 svm->nested.hsave_msr = data;
2833 break;
2834 case MSR_VM_CR:
2835 return svm_set_vm_cr(vcpu, data);
2836 case MSR_VM_IGNNE:
2837 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2838 break;
2839 default:
2840 return kvm_set_msr_common(vcpu, ecx, data);
2841 }
2842 return 0;
2843 }
2844
2845 static int wrmsr_interception(struct vcpu_svm *svm)
2846 {
2847 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2848 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2849 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2850
2851
2852 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2853 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2854 trace_kvm_msr_write_ex(ecx, data);
2855 kvm_inject_gp(&svm->vcpu, 0);
2856 } else {
2857 trace_kvm_msr_write(ecx, data);
2858 skip_emulated_instruction(&svm->vcpu);
2859 }
2860 return 1;
2861 }
2862
2863 static int msr_interception(struct vcpu_svm *svm)
2864 {
2865 if (svm->vmcb->control.exit_info_1)
2866 return wrmsr_interception(svm);
2867 else
2868 return rdmsr_interception(svm);
2869 }
2870
2871 static int interrupt_window_interception(struct vcpu_svm *svm)
2872 {
2873 struct kvm_run *kvm_run = svm->vcpu.run;
2874
2875 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2876 svm_clear_vintr(svm);
2877 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2878 /*
2879 * If the user space waits to inject interrupts, exit as soon as
2880 * possible
2881 */
2882 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2883 kvm_run->request_interrupt_window &&
2884 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2885 ++svm->vcpu.stat.irq_window_exits;
2886 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2887 return 0;
2888 }
2889
2890 return 1;
2891 }
2892
2893 static int pause_interception(struct vcpu_svm *svm)
2894 {
2895 kvm_vcpu_on_spin(&(svm->vcpu));
2896 return 1;
2897 }
2898
2899 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2900 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2901 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2902 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2903 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2904 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2905 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2906 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2907 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2908 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2909 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2910 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2911 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2912 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2913 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2914 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2915 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2916 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2917 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2918 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2919 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2920 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2921 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2922 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2923 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2924 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2925 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2926 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2927 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2928 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2929 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2930 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2931 [SVM_EXIT_INTR] = intr_interception,
2932 [SVM_EXIT_NMI] = nmi_interception,
2933 [SVM_EXIT_SMI] = nop_on_interception,
2934 [SVM_EXIT_INIT] = nop_on_interception,
2935 [SVM_EXIT_VINTR] = interrupt_window_interception,
2936 [SVM_EXIT_CPUID] = cpuid_interception,
2937 [SVM_EXIT_IRET] = iret_interception,
2938 [SVM_EXIT_INVD] = emulate_on_interception,
2939 [SVM_EXIT_PAUSE] = pause_interception,
2940 [SVM_EXIT_HLT] = halt_interception,
2941 [SVM_EXIT_INVLPG] = invlpg_interception,
2942 [SVM_EXIT_INVLPGA] = invlpga_interception,
2943 [SVM_EXIT_IOIO] = io_interception,
2944 [SVM_EXIT_MSR] = msr_interception,
2945 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2946 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2947 [SVM_EXIT_VMRUN] = vmrun_interception,
2948 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2949 [SVM_EXIT_VMLOAD] = vmload_interception,
2950 [SVM_EXIT_VMSAVE] = vmsave_interception,
2951 [SVM_EXIT_STGI] = stgi_interception,
2952 [SVM_EXIT_CLGI] = clgi_interception,
2953 [SVM_EXIT_SKINIT] = skinit_interception,
2954 [SVM_EXIT_WBINVD] = emulate_on_interception,
2955 [SVM_EXIT_MONITOR] = invalid_op_interception,
2956 [SVM_EXIT_MWAIT] = invalid_op_interception,
2957 [SVM_EXIT_NPF] = pf_interception,
2958 };
2959
2960 void dump_vmcb(struct kvm_vcpu *vcpu)
2961 {
2962 struct vcpu_svm *svm = to_svm(vcpu);
2963 struct vmcb_control_area *control = &svm->vmcb->control;
2964 struct vmcb_save_area *save = &svm->vmcb->save;
2965
2966 pr_err("VMCB Control Area:\n");
2967 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2968 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2969 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2970 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2971 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2972 pr_err("intercepts: %016llx\n", control->intercept);
2973 pr_err("pause filter count: %d\n", control->pause_filter_count);
2974 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2975 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2976 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2977 pr_err("asid: %d\n", control->asid);
2978 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2979 pr_err("int_ctl: %08x\n", control->int_ctl);
2980 pr_err("int_vector: %08x\n", control->int_vector);
2981 pr_err("int_state: %08x\n", control->int_state);
2982 pr_err("exit_code: %08x\n", control->exit_code);
2983 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2984 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2985 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2986 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2987 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2988 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2989 pr_err("event_inj: %08x\n", control->event_inj);
2990 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2991 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2992 pr_err("next_rip: %016llx\n", control->next_rip);
2993 pr_err("VMCB State Save Area:\n");
2994 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2995 save->es.selector, save->es.attrib,
2996 save->es.limit, save->es.base);
2997 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2998 save->cs.selector, save->cs.attrib,
2999 save->cs.limit, save->cs.base);
3000 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3001 save->ss.selector, save->ss.attrib,
3002 save->ss.limit, save->ss.base);
3003 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3004 save->ds.selector, save->ds.attrib,
3005 save->ds.limit, save->ds.base);
3006 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3007 save->fs.selector, save->fs.attrib,
3008 save->fs.limit, save->fs.base);
3009 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3010 save->gs.selector, save->gs.attrib,
3011 save->gs.limit, save->gs.base);
3012 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3013 save->gdtr.selector, save->gdtr.attrib,
3014 save->gdtr.limit, save->gdtr.base);
3015 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3016 save->ldtr.selector, save->ldtr.attrib,
3017 save->ldtr.limit, save->ldtr.base);
3018 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3019 save->idtr.selector, save->idtr.attrib,
3020 save->idtr.limit, save->idtr.base);
3021 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3022 save->tr.selector, save->tr.attrib,
3023 save->tr.limit, save->tr.base);
3024 pr_err("cpl: %d efer: %016llx\n",
3025 save->cpl, save->efer);
3026 pr_err("cr0: %016llx cr2: %016llx\n",
3027 save->cr0, save->cr2);
3028 pr_err("cr3: %016llx cr4: %016llx\n",
3029 save->cr3, save->cr4);
3030 pr_err("dr6: %016llx dr7: %016llx\n",
3031 save->dr6, save->dr7);
3032 pr_err("rip: %016llx rflags: %016llx\n",
3033 save->rip, save->rflags);
3034 pr_err("rsp: %016llx rax: %016llx\n",
3035 save->rsp, save->rax);
3036 pr_err("star: %016llx lstar: %016llx\n",
3037 save->star, save->lstar);
3038 pr_err("cstar: %016llx sfmask: %016llx\n",
3039 save->cstar, save->sfmask);
3040 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3041 save->kernel_gs_base, save->sysenter_cs);
3042 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3043 save->sysenter_esp, save->sysenter_eip);
3044 pr_err("gpat: %016llx dbgctl: %016llx\n",
3045 save->g_pat, save->dbgctl);
3046 pr_err("br_from: %016llx br_to: %016llx\n",
3047 save->br_from, save->br_to);
3048 pr_err("excp_from: %016llx excp_to: %016llx\n",
3049 save->last_excp_from, save->last_excp_to);
3050
3051 }
3052
3053 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3054 {
3055 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3056
3057 *info1 = control->exit_info_1;
3058 *info2 = control->exit_info_2;
3059 }
3060
3061 static int handle_exit(struct kvm_vcpu *vcpu)
3062 {
3063 struct vcpu_svm *svm = to_svm(vcpu);
3064 struct kvm_run *kvm_run = vcpu->run;
3065 u32 exit_code = svm->vmcb->control.exit_code;
3066
3067 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3068
3069 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3070 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3071 if (npt_enabled)
3072 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3073
3074 if (unlikely(svm->nested.exit_required)) {
3075 nested_svm_vmexit(svm);
3076 svm->nested.exit_required = false;
3077
3078 return 1;
3079 }
3080
3081 if (is_guest_mode(vcpu)) {
3082 int vmexit;
3083
3084 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3085 svm->vmcb->control.exit_info_1,
3086 svm->vmcb->control.exit_info_2,
3087 svm->vmcb->control.exit_int_info,
3088 svm->vmcb->control.exit_int_info_err);
3089
3090 vmexit = nested_svm_exit_special(svm);
3091
3092 if (vmexit == NESTED_EXIT_CONTINUE)
3093 vmexit = nested_svm_exit_handled(svm);
3094
3095 if (vmexit == NESTED_EXIT_DONE)
3096 return 1;
3097 }
3098
3099 svm_complete_interrupts(svm);
3100
3101 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3102 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3103 kvm_run->fail_entry.hardware_entry_failure_reason
3104 = svm->vmcb->control.exit_code;
3105 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3106 dump_vmcb(vcpu);
3107 return 0;
3108 }
3109
3110 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3111 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3112 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3113 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3114 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3115 "exit_code 0x%x\n",
3116 __func__, svm->vmcb->control.exit_int_info,
3117 exit_code);
3118
3119 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3120 || !svm_exit_handlers[exit_code]) {
3121 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3122 kvm_run->hw.hardware_exit_reason = exit_code;
3123 return 0;
3124 }
3125
3126 return svm_exit_handlers[exit_code](svm);
3127 }
3128
3129 static void reload_tss(struct kvm_vcpu *vcpu)
3130 {
3131 int cpu = raw_smp_processor_id();
3132
3133 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3134 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3135 load_TR_desc();
3136 }
3137
3138 static void pre_svm_run(struct vcpu_svm *svm)
3139 {
3140 int cpu = raw_smp_processor_id();
3141
3142 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3143
3144 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3145 /* FIXME: handle wraparound of asid_generation */
3146 if (svm->asid_generation != sd->asid_generation)
3147 new_asid(svm, sd);
3148 }
3149
3150 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3151 {
3152 struct vcpu_svm *svm = to_svm(vcpu);
3153
3154 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3155 vcpu->arch.hflags |= HF_NMI_MASK;
3156 set_intercept(svm, INTERCEPT_IRET);
3157 ++vcpu->stat.nmi_injections;
3158 }
3159
3160 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3161 {
3162 struct vmcb_control_area *control;
3163
3164 control = &svm->vmcb->control;
3165 control->int_vector = irq;
3166 control->int_ctl &= ~V_INTR_PRIO_MASK;
3167 control->int_ctl |= V_IRQ_MASK |
3168 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3169 }
3170
3171 static void svm_set_irq(struct kvm_vcpu *vcpu)
3172 {
3173 struct vcpu_svm *svm = to_svm(vcpu);
3174
3175 BUG_ON(!(gif_set(svm)));
3176
3177 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3178 ++vcpu->stat.irq_injections;
3179
3180 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3181 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3182 }
3183
3184 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3185 {
3186 struct vcpu_svm *svm = to_svm(vcpu);
3187
3188 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3189 return;
3190
3191 if (irr == -1)
3192 return;
3193
3194 if (tpr >= irr)
3195 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3196 }
3197
3198 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3199 {
3200 struct vcpu_svm *svm = to_svm(vcpu);
3201 struct vmcb *vmcb = svm->vmcb;
3202 int ret;
3203 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3204 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3205 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3206
3207 return ret;
3208 }
3209
3210 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3211 {
3212 struct vcpu_svm *svm = to_svm(vcpu);
3213
3214 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3215 }
3216
3217 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3218 {
3219 struct vcpu_svm *svm = to_svm(vcpu);
3220
3221 if (masked) {
3222 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3223 set_intercept(svm, INTERCEPT_IRET);
3224 } else {
3225 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3226 clr_intercept(svm, INTERCEPT_IRET);
3227 }
3228 }
3229
3230 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3231 {
3232 struct vcpu_svm *svm = to_svm(vcpu);
3233 struct vmcb *vmcb = svm->vmcb;
3234 int ret;
3235
3236 if (!gif_set(svm) ||
3237 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3238 return 0;
3239
3240 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3241
3242 if (is_guest_mode(vcpu))
3243 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3244
3245 return ret;
3246 }
3247
3248 static void enable_irq_window(struct kvm_vcpu *vcpu)
3249 {
3250 struct vcpu_svm *svm = to_svm(vcpu);
3251
3252 /*
3253 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3254 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3255 * get that intercept, this function will be called again though and
3256 * we'll get the vintr intercept.
3257 */
3258 if (gif_set(svm) && nested_svm_intr(svm)) {
3259 svm_set_vintr(svm);
3260 svm_inject_irq(svm, 0x0);
3261 }
3262 }
3263
3264 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3265 {
3266 struct vcpu_svm *svm = to_svm(vcpu);
3267
3268 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3269 == HF_NMI_MASK)
3270 return; /* IRET will cause a vm exit */
3271
3272 /*
3273 * Something prevents NMI from been injected. Single step over possible
3274 * problem (IRET or exception injection or interrupt shadow)
3275 */
3276 svm->nmi_singlestep = true;
3277 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3278 update_db_intercept(vcpu);
3279 }
3280
3281 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3282 {
3283 return 0;
3284 }
3285
3286 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3287 {
3288 force_new_asid(vcpu);
3289 }
3290
3291 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3292 {
3293 }
3294
3295 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3296 {
3297 struct vcpu_svm *svm = to_svm(vcpu);
3298
3299 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3300 return;
3301
3302 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3303 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3304 kvm_set_cr8(vcpu, cr8);
3305 }
3306 }
3307
3308 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3309 {
3310 struct vcpu_svm *svm = to_svm(vcpu);
3311 u64 cr8;
3312
3313 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3314 return;
3315
3316 cr8 = kvm_get_cr8(vcpu);
3317 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3318 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3319 }
3320
3321 static void svm_complete_interrupts(struct vcpu_svm *svm)
3322 {
3323 u8 vector;
3324 int type;
3325 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3326 unsigned int3_injected = svm->int3_injected;
3327
3328 svm->int3_injected = 0;
3329
3330 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3331 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3332 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3333 }
3334
3335 svm->vcpu.arch.nmi_injected = false;
3336 kvm_clear_exception_queue(&svm->vcpu);
3337 kvm_clear_interrupt_queue(&svm->vcpu);
3338
3339 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3340 return;
3341
3342 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3343
3344 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3345 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3346
3347 switch (type) {
3348 case SVM_EXITINTINFO_TYPE_NMI:
3349 svm->vcpu.arch.nmi_injected = true;
3350 break;
3351 case SVM_EXITINTINFO_TYPE_EXEPT:
3352 /*
3353 * In case of software exceptions, do not reinject the vector,
3354 * but re-execute the instruction instead. Rewind RIP first
3355 * if we emulated INT3 before.
3356 */
3357 if (kvm_exception_is_soft(vector)) {
3358 if (vector == BP_VECTOR && int3_injected &&
3359 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3360 kvm_rip_write(&svm->vcpu,
3361 kvm_rip_read(&svm->vcpu) -
3362 int3_injected);
3363 break;
3364 }
3365 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3366 u32 err = svm->vmcb->control.exit_int_info_err;
3367 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3368
3369 } else
3370 kvm_requeue_exception(&svm->vcpu, vector);
3371 break;
3372 case SVM_EXITINTINFO_TYPE_INTR:
3373 kvm_queue_interrupt(&svm->vcpu, vector, false);
3374 break;
3375 default:
3376 break;
3377 }
3378 }
3379
3380 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3381 {
3382 struct vcpu_svm *svm = to_svm(vcpu);
3383 struct vmcb_control_area *control = &svm->vmcb->control;
3384
3385 control->exit_int_info = control->event_inj;
3386 control->exit_int_info_err = control->event_inj_err;
3387 control->event_inj = 0;
3388 svm_complete_interrupts(svm);
3389 }
3390
3391 #ifdef CONFIG_X86_64
3392 #define R "r"
3393 #else
3394 #define R "e"
3395 #endif
3396
3397 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3398 {
3399 struct vcpu_svm *svm = to_svm(vcpu);
3400
3401 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3402 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3403 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3404
3405 /*
3406 * A vmexit emulation is required before the vcpu can be executed
3407 * again.
3408 */
3409 if (unlikely(svm->nested.exit_required))
3410 return;
3411
3412 pre_svm_run(svm);
3413
3414 sync_lapic_to_cr8(vcpu);
3415
3416 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3417
3418 clgi();
3419
3420 local_irq_enable();
3421
3422 asm volatile (
3423 "push %%"R"bp; \n\t"
3424 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3425 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3426 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3427 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3428 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3429 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3430 #ifdef CONFIG_X86_64
3431 "mov %c[r8](%[svm]), %%r8 \n\t"
3432 "mov %c[r9](%[svm]), %%r9 \n\t"
3433 "mov %c[r10](%[svm]), %%r10 \n\t"
3434 "mov %c[r11](%[svm]), %%r11 \n\t"
3435 "mov %c[r12](%[svm]), %%r12 \n\t"
3436 "mov %c[r13](%[svm]), %%r13 \n\t"
3437 "mov %c[r14](%[svm]), %%r14 \n\t"
3438 "mov %c[r15](%[svm]), %%r15 \n\t"
3439 #endif
3440
3441 /* Enter guest mode */
3442 "push %%"R"ax \n\t"
3443 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3444 __ex(SVM_VMLOAD) "\n\t"
3445 __ex(SVM_VMRUN) "\n\t"
3446 __ex(SVM_VMSAVE) "\n\t"
3447 "pop %%"R"ax \n\t"
3448
3449 /* Save guest registers, load host registers */
3450 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3451 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3452 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3453 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3454 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3455 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3456 #ifdef CONFIG_X86_64
3457 "mov %%r8, %c[r8](%[svm]) \n\t"
3458 "mov %%r9, %c[r9](%[svm]) \n\t"
3459 "mov %%r10, %c[r10](%[svm]) \n\t"
3460 "mov %%r11, %c[r11](%[svm]) \n\t"
3461 "mov %%r12, %c[r12](%[svm]) \n\t"
3462 "mov %%r13, %c[r13](%[svm]) \n\t"
3463 "mov %%r14, %c[r14](%[svm]) \n\t"
3464 "mov %%r15, %c[r15](%[svm]) \n\t"
3465 #endif
3466 "pop %%"R"bp"
3467 :
3468 : [svm]"a"(svm),
3469 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3470 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3471 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3472 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3473 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3474 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3475 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3476 #ifdef CONFIG_X86_64
3477 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3478 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3479 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3480 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3481 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3482 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3483 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3484 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3485 #endif
3486 : "cc", "memory"
3487 , R"bx", R"cx", R"dx", R"si", R"di"
3488 #ifdef CONFIG_X86_64
3489 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3490 #endif
3491 );
3492
3493 #ifdef CONFIG_X86_64
3494 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3495 #else
3496 loadsegment(fs, svm->host.fs);
3497 #endif
3498
3499 reload_tss(vcpu);
3500
3501 local_irq_disable();
3502
3503 stgi();
3504
3505 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3506 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3507 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3508 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3509
3510 sync_cr8_to_lapic(vcpu);
3511
3512 svm->next_rip = 0;
3513
3514 /* if exit due to PF check for async PF */
3515 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3516 svm->apf_reason = kvm_read_and_reset_pf_reason();
3517
3518 if (npt_enabled) {
3519 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3520 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3521 }
3522
3523 /*
3524 * We need to handle MC intercepts here before the vcpu has a chance to
3525 * change the physical cpu
3526 */
3527 if (unlikely(svm->vmcb->control.exit_code ==
3528 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3529 svm_handle_mce(svm);
3530
3531 mark_all_clean(svm->vmcb);
3532 }
3533
3534 #undef R
3535
3536 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3537 {
3538 struct vcpu_svm *svm = to_svm(vcpu);
3539
3540 svm->vmcb->save.cr3 = root;
3541 force_new_asid(vcpu);
3542 }
3543
3544 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3545 {
3546 struct vcpu_svm *svm = to_svm(vcpu);
3547
3548 svm->vmcb->control.nested_cr3 = root;
3549
3550 /* Also sync guest cr3 here in case we live migrate */
3551 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3552
3553 force_new_asid(vcpu);
3554 }
3555
3556 static int is_disabled(void)
3557 {
3558 u64 vm_cr;
3559
3560 rdmsrl(MSR_VM_CR, vm_cr);
3561 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3562 return 1;
3563
3564 return 0;
3565 }
3566
3567 static void
3568 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3569 {
3570 /*
3571 * Patch in the VMMCALL instruction:
3572 */
3573 hypercall[0] = 0x0f;
3574 hypercall[1] = 0x01;
3575 hypercall[2] = 0xd9;
3576 }
3577
3578 static void svm_check_processor_compat(void *rtn)
3579 {
3580 *(int *)rtn = 0;
3581 }
3582
3583 static bool svm_cpu_has_accelerated_tpr(void)
3584 {
3585 return false;
3586 }
3587
3588 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3589 {
3590 return 0;
3591 }
3592
3593 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3594 {
3595 }
3596
3597 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3598 {
3599 switch (func) {
3600 case 0x00000001:
3601 /* Mask out xsave bit as long as it is not supported by SVM */
3602 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3603 break;
3604 case 0x80000001:
3605 if (nested)
3606 entry->ecx |= (1 << 2); /* Set SVM bit */
3607 break;
3608 case 0x8000000A:
3609 entry->eax = 1; /* SVM revision 1 */
3610 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3611 ASID emulation to nested SVM */
3612 entry->ecx = 0; /* Reserved */
3613 entry->edx = 0; /* Per default do not support any
3614 additional features */
3615
3616 /* Support next_rip if host supports it */
3617 if (boot_cpu_has(X86_FEATURE_NRIPS))
3618 entry->edx |= SVM_FEATURE_NRIP;
3619
3620 /* Support NPT for the guest if enabled */
3621 if (npt_enabled)
3622 entry->edx |= SVM_FEATURE_NPT;
3623
3624 break;
3625 }
3626 }
3627
3628 static const struct trace_print_flags svm_exit_reasons_str[] = {
3629 { SVM_EXIT_READ_CR0, "read_cr0" },
3630 { SVM_EXIT_READ_CR3, "read_cr3" },
3631 { SVM_EXIT_READ_CR4, "read_cr4" },
3632 { SVM_EXIT_READ_CR8, "read_cr8" },
3633 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3634 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3635 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3636 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3637 { SVM_EXIT_READ_DR0, "read_dr0" },
3638 { SVM_EXIT_READ_DR1, "read_dr1" },
3639 { SVM_EXIT_READ_DR2, "read_dr2" },
3640 { SVM_EXIT_READ_DR3, "read_dr3" },
3641 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3642 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3643 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3644 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3645 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3646 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3647 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3648 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3649 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3650 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3651 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3652 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3653 { SVM_EXIT_INTR, "interrupt" },
3654 { SVM_EXIT_NMI, "nmi" },
3655 { SVM_EXIT_SMI, "smi" },
3656 { SVM_EXIT_INIT, "init" },
3657 { SVM_EXIT_VINTR, "vintr" },
3658 { SVM_EXIT_CPUID, "cpuid" },
3659 { SVM_EXIT_INVD, "invd" },
3660 { SVM_EXIT_HLT, "hlt" },
3661 { SVM_EXIT_INVLPG, "invlpg" },
3662 { SVM_EXIT_INVLPGA, "invlpga" },
3663 { SVM_EXIT_IOIO, "io" },
3664 { SVM_EXIT_MSR, "msr" },
3665 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3666 { SVM_EXIT_SHUTDOWN, "shutdown" },
3667 { SVM_EXIT_VMRUN, "vmrun" },
3668 { SVM_EXIT_VMMCALL, "hypercall" },
3669 { SVM_EXIT_VMLOAD, "vmload" },
3670 { SVM_EXIT_VMSAVE, "vmsave" },
3671 { SVM_EXIT_STGI, "stgi" },
3672 { SVM_EXIT_CLGI, "clgi" },
3673 { SVM_EXIT_SKINIT, "skinit" },
3674 { SVM_EXIT_WBINVD, "wbinvd" },
3675 { SVM_EXIT_MONITOR, "monitor" },
3676 { SVM_EXIT_MWAIT, "mwait" },
3677 { SVM_EXIT_NPF, "npf" },
3678 { -1, NULL }
3679 };
3680
3681 static int svm_get_lpage_level(void)
3682 {
3683 return PT_PDPE_LEVEL;
3684 }
3685
3686 static bool svm_rdtscp_supported(void)
3687 {
3688 return false;
3689 }
3690
3691 static bool svm_has_wbinvd_exit(void)
3692 {
3693 return true;
3694 }
3695
3696 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3697 {
3698 struct vcpu_svm *svm = to_svm(vcpu);
3699
3700 set_exception_intercept(svm, NM_VECTOR);
3701 update_cr0_intercept(svm);
3702 }
3703
3704 static struct kvm_x86_ops svm_x86_ops = {
3705 .cpu_has_kvm_support = has_svm,
3706 .disabled_by_bios = is_disabled,
3707 .hardware_setup = svm_hardware_setup,
3708 .hardware_unsetup = svm_hardware_unsetup,
3709 .check_processor_compatibility = svm_check_processor_compat,
3710 .hardware_enable = svm_hardware_enable,
3711 .hardware_disable = svm_hardware_disable,
3712 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3713
3714 .vcpu_create = svm_create_vcpu,
3715 .vcpu_free = svm_free_vcpu,
3716 .vcpu_reset = svm_vcpu_reset,
3717
3718 .prepare_guest_switch = svm_prepare_guest_switch,
3719 .vcpu_load = svm_vcpu_load,
3720 .vcpu_put = svm_vcpu_put,
3721
3722 .set_guest_debug = svm_guest_debug,
3723 .get_msr = svm_get_msr,
3724 .set_msr = svm_set_msr,
3725 .get_segment_base = svm_get_segment_base,
3726 .get_segment = svm_get_segment,
3727 .set_segment = svm_set_segment,
3728 .get_cpl = svm_get_cpl,
3729 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3730 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3731 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3732 .set_cr0 = svm_set_cr0,
3733 .set_cr3 = svm_set_cr3,
3734 .set_cr4 = svm_set_cr4,
3735 .set_efer = svm_set_efer,
3736 .get_idt = svm_get_idt,
3737 .set_idt = svm_set_idt,
3738 .get_gdt = svm_get_gdt,
3739 .set_gdt = svm_set_gdt,
3740 .set_dr7 = svm_set_dr7,
3741 .cache_reg = svm_cache_reg,
3742 .get_rflags = svm_get_rflags,
3743 .set_rflags = svm_set_rflags,
3744 .fpu_activate = svm_fpu_activate,
3745 .fpu_deactivate = svm_fpu_deactivate,
3746
3747 .tlb_flush = svm_flush_tlb,
3748
3749 .run = svm_vcpu_run,
3750 .handle_exit = handle_exit,
3751 .skip_emulated_instruction = skip_emulated_instruction,
3752 .set_interrupt_shadow = svm_set_interrupt_shadow,
3753 .get_interrupt_shadow = svm_get_interrupt_shadow,
3754 .patch_hypercall = svm_patch_hypercall,
3755 .set_irq = svm_set_irq,
3756 .set_nmi = svm_inject_nmi,
3757 .queue_exception = svm_queue_exception,
3758 .cancel_injection = svm_cancel_injection,
3759 .interrupt_allowed = svm_interrupt_allowed,
3760 .nmi_allowed = svm_nmi_allowed,
3761 .get_nmi_mask = svm_get_nmi_mask,
3762 .set_nmi_mask = svm_set_nmi_mask,
3763 .enable_nmi_window = enable_nmi_window,
3764 .enable_irq_window = enable_irq_window,
3765 .update_cr8_intercept = update_cr8_intercept,
3766
3767 .set_tss_addr = svm_set_tss_addr,
3768 .get_tdp_level = get_npt_level,
3769 .get_mt_mask = svm_get_mt_mask,
3770
3771 .get_exit_info = svm_get_exit_info,
3772 .exit_reasons_str = svm_exit_reasons_str,
3773
3774 .get_lpage_level = svm_get_lpage_level,
3775
3776 .cpuid_update = svm_cpuid_update,
3777
3778 .rdtscp_supported = svm_rdtscp_supported,
3779
3780 .set_supported_cpuid = svm_set_supported_cpuid,
3781
3782 .has_wbinvd_exit = svm_has_wbinvd_exit,
3783
3784 .write_tsc_offset = svm_write_tsc_offset,
3785 .adjust_tsc_offset = svm_adjust_tsc_offset,
3786
3787 .set_tdp_cr3 = set_tdp_cr3,
3788 };
3789
3790 static int __init svm_init(void)
3791 {
3792 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3793 __alignof__(struct vcpu_svm), THIS_MODULE);
3794 }
3795
3796 static void __exit svm_exit(void)
3797 {
3798 kvm_exit();
3799 }
3800
3801 module_init(svm_init)
3802 module_exit(svm_exit)
Linux kernel - Deliverables
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