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KVM: SVM: Remove flush_guest_tlb function
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_CR, /* CR0, CR3, CR4, EFER */
196 VMCB_DR, /* DR6, DR7 */
197 VMCB_DT, /* GDT, IDT */
198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
199 VMCB_CR2, /* CR2 only */
200 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
201 VMCB_DIRTY_MAX,
202 };
203
204 /* TPR and CR2 are always written before VMRUN */
205 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
206
207 static inline void mark_all_dirty(struct vmcb *vmcb)
208 {
209 vmcb->control.clean = 0;
210 }
211
212 static inline void mark_all_clean(struct vmcb *vmcb)
213 {
214 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
215 & ~VMCB_ALWAYS_DIRTY_MASK;
216 }
217
218 static inline void mark_dirty(struct vmcb *vmcb, int bit)
219 {
220 vmcb->control.clean &= ~(1 << bit);
221 }
222
223 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
224 {
225 return container_of(vcpu, struct vcpu_svm, vcpu);
226 }
227
228 static void recalc_intercepts(struct vcpu_svm *svm)
229 {
230 struct vmcb_control_area *c, *h;
231 struct nested_state *g;
232
233 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
234
235 if (!is_guest_mode(&svm->vcpu))
236 return;
237
238 c = &svm->vmcb->control;
239 h = &svm->nested.hsave->control;
240 g = &svm->nested;
241
242 c->intercept_cr = h->intercept_cr | g->intercept_cr;
243 c->intercept_dr = h->intercept_dr | g->intercept_dr;
244 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
245 c->intercept = h->intercept | g->intercept;
246 }
247
248 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
249 {
250 if (is_guest_mode(&svm->vcpu))
251 return svm->nested.hsave;
252 else
253 return svm->vmcb;
254 }
255
256 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
257 {
258 struct vmcb *vmcb = get_host_vmcb(svm);
259
260 vmcb->control.intercept_cr |= (1U << bit);
261
262 recalc_intercepts(svm);
263 }
264
265 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
266 {
267 struct vmcb *vmcb = get_host_vmcb(svm);
268
269 vmcb->control.intercept_cr &= ~(1U << bit);
270
271 recalc_intercepts(svm);
272 }
273
274 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
275 {
276 struct vmcb *vmcb = get_host_vmcb(svm);
277
278 return vmcb->control.intercept_cr & (1U << bit);
279 }
280
281 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_dr |= (1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_dr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297 }
298
299 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
300 {
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 vmcb->control.intercept_exceptions |= (1U << bit);
304
305 recalc_intercepts(svm);
306 }
307
308 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
309 {
310 struct vmcb *vmcb = get_host_vmcb(svm);
311
312 vmcb->control.intercept_exceptions &= ~(1U << bit);
313
314 recalc_intercepts(svm);
315 }
316
317 static inline void set_intercept(struct vcpu_svm *svm, int bit)
318 {
319 struct vmcb *vmcb = get_host_vmcb(svm);
320
321 vmcb->control.intercept |= (1ULL << bit);
322
323 recalc_intercepts(svm);
324 }
325
326 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
327 {
328 struct vmcb *vmcb = get_host_vmcb(svm);
329
330 vmcb->control.intercept &= ~(1ULL << bit);
331
332 recalc_intercepts(svm);
333 }
334
335 static inline void enable_gif(struct vcpu_svm *svm)
336 {
337 svm->vcpu.arch.hflags |= HF_GIF_MASK;
338 }
339
340 static inline void disable_gif(struct vcpu_svm *svm)
341 {
342 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
343 }
344
345 static inline bool gif_set(struct vcpu_svm *svm)
346 {
347 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
348 }
349
350 static unsigned long iopm_base;
351
352 struct kvm_ldttss_desc {
353 u16 limit0;
354 u16 base0;
355 unsigned base1:8, type:5, dpl:2, p:1;
356 unsigned limit1:4, zero0:3, g:1, base2:8;
357 u32 base3;
358 u32 zero1;
359 } __attribute__((packed));
360
361 struct svm_cpu_data {
362 int cpu;
363
364 u64 asid_generation;
365 u32 max_asid;
366 u32 next_asid;
367 struct kvm_ldttss_desc *tss_desc;
368
369 struct page *save_area;
370 };
371
372 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
373 static uint32_t svm_features;
374
375 struct svm_init_data {
376 int cpu;
377 int r;
378 };
379
380 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
381
382 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
383 #define MSRS_RANGE_SIZE 2048
384 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
385
386 static u32 svm_msrpm_offset(u32 msr)
387 {
388 u32 offset;
389 int i;
390
391 for (i = 0; i < NUM_MSR_MAPS; i++) {
392 if (msr < msrpm_ranges[i] ||
393 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
394 continue;
395
396 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
397 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
398
399 /* Now we have the u8 offset - but need the u32 offset */
400 return offset / 4;
401 }
402
403 /* MSR not in any range */
404 return MSR_INVALID;
405 }
406
407 #define MAX_INST_SIZE 15
408
409 static inline void clgi(void)
410 {
411 asm volatile (__ex(SVM_CLGI));
412 }
413
414 static inline void stgi(void)
415 {
416 asm volatile (__ex(SVM_STGI));
417 }
418
419 static inline void invlpga(unsigned long addr, u32 asid)
420 {
421 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
422 }
423
424 static inline void force_new_asid(struct kvm_vcpu *vcpu)
425 {
426 to_svm(vcpu)->asid_generation--;
427 }
428
429 static int get_npt_level(void)
430 {
431 #ifdef CONFIG_X86_64
432 return PT64_ROOT_LEVEL;
433 #else
434 return PT32E_ROOT_LEVEL;
435 #endif
436 }
437
438 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
439 {
440 vcpu->arch.efer = efer;
441 if (!npt_enabled && !(efer & EFER_LMA))
442 efer &= ~EFER_LME;
443
444 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
445 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
446 }
447
448 static int is_external_interrupt(u32 info)
449 {
450 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
451 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
452 }
453
454 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
455 {
456 struct vcpu_svm *svm = to_svm(vcpu);
457 u32 ret = 0;
458
459 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
460 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
461 return ret & mask;
462 }
463
464 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
465 {
466 struct vcpu_svm *svm = to_svm(vcpu);
467
468 if (mask == 0)
469 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
470 else
471 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
472
473 }
474
475 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
476 {
477 struct vcpu_svm *svm = to_svm(vcpu);
478
479 if (svm->vmcb->control.next_rip != 0)
480 svm->next_rip = svm->vmcb->control.next_rip;
481
482 if (!svm->next_rip) {
483 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
484 EMULATE_DONE)
485 printk(KERN_DEBUG "%s: NOP\n", __func__);
486 return;
487 }
488 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
489 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
490 __func__, kvm_rip_read(vcpu), svm->next_rip);
491
492 kvm_rip_write(vcpu, svm->next_rip);
493 svm_set_interrupt_shadow(vcpu, 0);
494 }
495
496 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
497 bool has_error_code, u32 error_code,
498 bool reinject)
499 {
500 struct vcpu_svm *svm = to_svm(vcpu);
501
502 /*
503 * If we are within a nested VM we'd better #VMEXIT and let the guest
504 * handle the exception
505 */
506 if (!reinject &&
507 nested_svm_check_exception(svm, nr, has_error_code, error_code))
508 return;
509
510 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
511 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
512
513 /*
514 * For guest debugging where we have to reinject #BP if some
515 * INT3 is guest-owned:
516 * Emulate nRIP by moving RIP forward. Will fail if injection
517 * raises a fault that is not intercepted. Still better than
518 * failing in all cases.
519 */
520 skip_emulated_instruction(&svm->vcpu);
521 rip = kvm_rip_read(&svm->vcpu);
522 svm->int3_rip = rip + svm->vmcb->save.cs.base;
523 svm->int3_injected = rip - old_rip;
524 }
525
526 svm->vmcb->control.event_inj = nr
527 | SVM_EVTINJ_VALID
528 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
529 | SVM_EVTINJ_TYPE_EXEPT;
530 svm->vmcb->control.event_inj_err = error_code;
531 }
532
533 static void svm_init_erratum_383(void)
534 {
535 u32 low, high;
536 int err;
537 u64 val;
538
539 if (!cpu_has_amd_erratum(amd_erratum_383))
540 return;
541
542 /* Use _safe variants to not break nested virtualization */
543 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
544 if (err)
545 return;
546
547 val |= (1ULL << 47);
548
549 low = lower_32_bits(val);
550 high = upper_32_bits(val);
551
552 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
553
554 erratum_383_found = true;
555 }
556
557 static int has_svm(void)
558 {
559 const char *msg;
560
561 if (!cpu_has_svm(&msg)) {
562 printk(KERN_INFO "has_svm: %s\n", msg);
563 return 0;
564 }
565
566 return 1;
567 }
568
569 static void svm_hardware_disable(void *garbage)
570 {
571 cpu_svm_disable();
572 }
573
574 static int svm_hardware_enable(void *garbage)
575 {
576
577 struct svm_cpu_data *sd;
578 uint64_t efer;
579 struct desc_ptr gdt_descr;
580 struct desc_struct *gdt;
581 int me = raw_smp_processor_id();
582
583 rdmsrl(MSR_EFER, efer);
584 if (efer & EFER_SVME)
585 return -EBUSY;
586
587 if (!has_svm()) {
588 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
589 me);
590 return -EINVAL;
591 }
592 sd = per_cpu(svm_data, me);
593
594 if (!sd) {
595 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
596 me);
597 return -EINVAL;
598 }
599
600 sd->asid_generation = 1;
601 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
602 sd->next_asid = sd->max_asid + 1;
603
604 native_store_gdt(&gdt_descr);
605 gdt = (struct desc_struct *)gdt_descr.address;
606 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
607
608 wrmsrl(MSR_EFER, efer | EFER_SVME);
609
610 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
611
612 svm_init_erratum_383();
613
614 return 0;
615 }
616
617 static void svm_cpu_uninit(int cpu)
618 {
619 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
620
621 if (!sd)
622 return;
623
624 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
625 __free_page(sd->save_area);
626 kfree(sd);
627 }
628
629 static int svm_cpu_init(int cpu)
630 {
631 struct svm_cpu_data *sd;
632 int r;
633
634 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
635 if (!sd)
636 return -ENOMEM;
637 sd->cpu = cpu;
638 sd->save_area = alloc_page(GFP_KERNEL);
639 r = -ENOMEM;
640 if (!sd->save_area)
641 goto err_1;
642
643 per_cpu(svm_data, cpu) = sd;
644
645 return 0;
646
647 err_1:
648 kfree(sd);
649 return r;
650
651 }
652
653 static bool valid_msr_intercept(u32 index)
654 {
655 int i;
656
657 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
658 if (direct_access_msrs[i].index == index)
659 return true;
660
661 return false;
662 }
663
664 static void set_msr_interception(u32 *msrpm, unsigned msr,
665 int read, int write)
666 {
667 u8 bit_read, bit_write;
668 unsigned long tmp;
669 u32 offset;
670
671 /*
672 * If this warning triggers extend the direct_access_msrs list at the
673 * beginning of the file
674 */
675 WARN_ON(!valid_msr_intercept(msr));
676
677 offset = svm_msrpm_offset(msr);
678 bit_read = 2 * (msr & 0x0f);
679 bit_write = 2 * (msr & 0x0f) + 1;
680 tmp = msrpm[offset];
681
682 BUG_ON(offset == MSR_INVALID);
683
684 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
685 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
686
687 msrpm[offset] = tmp;
688 }
689
690 static void svm_vcpu_init_msrpm(u32 *msrpm)
691 {
692 int i;
693
694 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
695
696 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
697 if (!direct_access_msrs[i].always)
698 continue;
699
700 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
701 }
702 }
703
704 static void add_msr_offset(u32 offset)
705 {
706 int i;
707
708 for (i = 0; i < MSRPM_OFFSETS; ++i) {
709
710 /* Offset already in list? */
711 if (msrpm_offsets[i] == offset)
712 return;
713
714 /* Slot used by another offset? */
715 if (msrpm_offsets[i] != MSR_INVALID)
716 continue;
717
718 /* Add offset to list */
719 msrpm_offsets[i] = offset;
720
721 return;
722 }
723
724 /*
725 * If this BUG triggers the msrpm_offsets table has an overflow. Just
726 * increase MSRPM_OFFSETS in this case.
727 */
728 BUG();
729 }
730
731 static void init_msrpm_offsets(void)
732 {
733 int i;
734
735 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
736
737 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
738 u32 offset;
739
740 offset = svm_msrpm_offset(direct_access_msrs[i].index);
741 BUG_ON(offset == MSR_INVALID);
742
743 add_msr_offset(offset);
744 }
745 }
746
747 static void svm_enable_lbrv(struct vcpu_svm *svm)
748 {
749 u32 *msrpm = svm->msrpm;
750
751 svm->vmcb->control.lbr_ctl = 1;
752 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
753 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
754 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
755 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
756 }
757
758 static void svm_disable_lbrv(struct vcpu_svm *svm)
759 {
760 u32 *msrpm = svm->msrpm;
761
762 svm->vmcb->control.lbr_ctl = 0;
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
764 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
766 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
767 }
768
769 static __init int svm_hardware_setup(void)
770 {
771 int cpu;
772 struct page *iopm_pages;
773 void *iopm_va;
774 int r;
775
776 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
777
778 if (!iopm_pages)
779 return -ENOMEM;
780
781 iopm_va = page_address(iopm_pages);
782 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
783 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
784
785 init_msrpm_offsets();
786
787 if (boot_cpu_has(X86_FEATURE_NX))
788 kvm_enable_efer_bits(EFER_NX);
789
790 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
791 kvm_enable_efer_bits(EFER_FFXSR);
792
793 if (nested) {
794 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
795 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
796 }
797
798 for_each_possible_cpu(cpu) {
799 r = svm_cpu_init(cpu);
800 if (r)
801 goto err;
802 }
803
804 svm_features = cpuid_edx(SVM_CPUID_FUNC);
805
806 if (!boot_cpu_has(X86_FEATURE_NPT))
807 npt_enabled = false;
808
809 if (npt_enabled && !npt) {
810 printk(KERN_INFO "kvm: Nested Paging disabled\n");
811 npt_enabled = false;
812 }
813
814 if (npt_enabled) {
815 printk(KERN_INFO "kvm: Nested Paging enabled\n");
816 kvm_enable_tdp();
817 } else
818 kvm_disable_tdp();
819
820 return 0;
821
822 err:
823 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
824 iopm_base = 0;
825 return r;
826 }
827
828 static __exit void svm_hardware_unsetup(void)
829 {
830 int cpu;
831
832 for_each_possible_cpu(cpu)
833 svm_cpu_uninit(cpu);
834
835 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
836 iopm_base = 0;
837 }
838
839 static void init_seg(struct vmcb_seg *seg)
840 {
841 seg->selector = 0;
842 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
843 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
844 seg->limit = 0xffff;
845 seg->base = 0;
846 }
847
848 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
849 {
850 seg->selector = 0;
851 seg->attrib = SVM_SELECTOR_P_MASK | type;
852 seg->limit = 0xffff;
853 seg->base = 0;
854 }
855
856 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
857 {
858 struct vcpu_svm *svm = to_svm(vcpu);
859 u64 g_tsc_offset = 0;
860
861 if (is_guest_mode(vcpu)) {
862 g_tsc_offset = svm->vmcb->control.tsc_offset -
863 svm->nested.hsave->control.tsc_offset;
864 svm->nested.hsave->control.tsc_offset = offset;
865 }
866
867 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
868
869 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
870 }
871
872 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
873 {
874 struct vcpu_svm *svm = to_svm(vcpu);
875
876 svm->vmcb->control.tsc_offset += adjustment;
877 if (is_guest_mode(vcpu))
878 svm->nested.hsave->control.tsc_offset += adjustment;
879 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
880 }
881
882 static void init_vmcb(struct vcpu_svm *svm)
883 {
884 struct vmcb_control_area *control = &svm->vmcb->control;
885 struct vmcb_save_area *save = &svm->vmcb->save;
886
887 svm->vcpu.fpu_active = 1;
888 svm->vcpu.arch.hflags = 0;
889
890 set_cr_intercept(svm, INTERCEPT_CR0_READ);
891 set_cr_intercept(svm, INTERCEPT_CR3_READ);
892 set_cr_intercept(svm, INTERCEPT_CR4_READ);
893 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
894 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
895 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
896 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
897
898 set_dr_intercept(svm, INTERCEPT_DR0_READ);
899 set_dr_intercept(svm, INTERCEPT_DR1_READ);
900 set_dr_intercept(svm, INTERCEPT_DR2_READ);
901 set_dr_intercept(svm, INTERCEPT_DR3_READ);
902 set_dr_intercept(svm, INTERCEPT_DR4_READ);
903 set_dr_intercept(svm, INTERCEPT_DR5_READ);
904 set_dr_intercept(svm, INTERCEPT_DR6_READ);
905 set_dr_intercept(svm, INTERCEPT_DR7_READ);
906
907 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
914 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
915
916 set_exception_intercept(svm, PF_VECTOR);
917 set_exception_intercept(svm, UD_VECTOR);
918 set_exception_intercept(svm, MC_VECTOR);
919
920 set_intercept(svm, INTERCEPT_INTR);
921 set_intercept(svm, INTERCEPT_NMI);
922 set_intercept(svm, INTERCEPT_SMI);
923 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
924 set_intercept(svm, INTERCEPT_CPUID);
925 set_intercept(svm, INTERCEPT_INVD);
926 set_intercept(svm, INTERCEPT_HLT);
927 set_intercept(svm, INTERCEPT_INVLPG);
928 set_intercept(svm, INTERCEPT_INVLPGA);
929 set_intercept(svm, INTERCEPT_IOIO_PROT);
930 set_intercept(svm, INTERCEPT_MSR_PROT);
931 set_intercept(svm, INTERCEPT_TASK_SWITCH);
932 set_intercept(svm, INTERCEPT_SHUTDOWN);
933 set_intercept(svm, INTERCEPT_VMRUN);
934 set_intercept(svm, INTERCEPT_VMMCALL);
935 set_intercept(svm, INTERCEPT_VMLOAD);
936 set_intercept(svm, INTERCEPT_VMSAVE);
937 set_intercept(svm, INTERCEPT_STGI);
938 set_intercept(svm, INTERCEPT_CLGI);
939 set_intercept(svm, INTERCEPT_SKINIT);
940 set_intercept(svm, INTERCEPT_WBINVD);
941 set_intercept(svm, INTERCEPT_MONITOR);
942 set_intercept(svm, INTERCEPT_MWAIT);
943
944 control->iopm_base_pa = iopm_base;
945 control->msrpm_base_pa = __pa(svm->msrpm);
946 control->int_ctl = V_INTR_MASKING_MASK;
947
948 init_seg(&save->es);
949 init_seg(&save->ss);
950 init_seg(&save->ds);
951 init_seg(&save->fs);
952 init_seg(&save->gs);
953
954 save->cs.selector = 0xf000;
955 /* Executable/Readable Code Segment */
956 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
957 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
958 save->cs.limit = 0xffff;
959 /*
960 * cs.base should really be 0xffff0000, but vmx can't handle that, so
961 * be consistent with it.
962 *
963 * Replace when we have real mode working for vmx.
964 */
965 save->cs.base = 0xf0000;
966
967 save->gdtr.limit = 0xffff;
968 save->idtr.limit = 0xffff;
969
970 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
971 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
972
973 svm_set_efer(&svm->vcpu, 0);
974 save->dr6 = 0xffff0ff0;
975 save->dr7 = 0x400;
976 save->rflags = 2;
977 save->rip = 0x0000fff0;
978 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
979
980 /*
981 * This is the guest-visible cr0 value.
982 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
983 */
984 svm->vcpu.arch.cr0 = 0;
985 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
986
987 save->cr4 = X86_CR4_PAE;
988 /* rdx = ?? */
989
990 if (npt_enabled) {
991 /* Setup VMCB for Nested Paging */
992 control->nested_ctl = 1;
993 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
994 clr_intercept(svm, INTERCEPT_INVLPG);
995 clr_exception_intercept(svm, PF_VECTOR);
996 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
997 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
998 save->g_pat = 0x0007040600070406ULL;
999 save->cr3 = 0;
1000 save->cr4 = 0;
1001 }
1002 force_new_asid(&svm->vcpu);
1003
1004 svm->nested.vmcb = 0;
1005 svm->vcpu.arch.hflags = 0;
1006
1007 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1008 control->pause_filter_count = 3000;
1009 set_intercept(svm, INTERCEPT_PAUSE);
1010 }
1011
1012 mark_all_dirty(svm->vmcb);
1013
1014 enable_gif(svm);
1015 }
1016
1017 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1018 {
1019 struct vcpu_svm *svm = to_svm(vcpu);
1020
1021 init_vmcb(svm);
1022
1023 if (!kvm_vcpu_is_bsp(vcpu)) {
1024 kvm_rip_write(vcpu, 0);
1025 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1026 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1027 }
1028 vcpu->arch.regs_avail = ~0;
1029 vcpu->arch.regs_dirty = ~0;
1030
1031 return 0;
1032 }
1033
1034 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1035 {
1036 struct vcpu_svm *svm;
1037 struct page *page;
1038 struct page *msrpm_pages;
1039 struct page *hsave_page;
1040 struct page *nested_msrpm_pages;
1041 int err;
1042
1043 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1044 if (!svm) {
1045 err = -ENOMEM;
1046 goto out;
1047 }
1048
1049 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1050 if (err)
1051 goto free_svm;
1052
1053 err = -ENOMEM;
1054 page = alloc_page(GFP_KERNEL);
1055 if (!page)
1056 goto uninit;
1057
1058 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1059 if (!msrpm_pages)
1060 goto free_page1;
1061
1062 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1063 if (!nested_msrpm_pages)
1064 goto free_page2;
1065
1066 hsave_page = alloc_page(GFP_KERNEL);
1067 if (!hsave_page)
1068 goto free_page3;
1069
1070 svm->nested.hsave = page_address(hsave_page);
1071
1072 svm->msrpm = page_address(msrpm_pages);
1073 svm_vcpu_init_msrpm(svm->msrpm);
1074
1075 svm->nested.msrpm = page_address(nested_msrpm_pages);
1076 svm_vcpu_init_msrpm(svm->nested.msrpm);
1077
1078 svm->vmcb = page_address(page);
1079 clear_page(svm->vmcb);
1080 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1081 svm->asid_generation = 0;
1082 init_vmcb(svm);
1083 kvm_write_tsc(&svm->vcpu, 0);
1084
1085 err = fx_init(&svm->vcpu);
1086 if (err)
1087 goto free_page4;
1088
1089 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1090 if (kvm_vcpu_is_bsp(&svm->vcpu))
1091 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1092
1093 return &svm->vcpu;
1094
1095 free_page4:
1096 __free_page(hsave_page);
1097 free_page3:
1098 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1099 free_page2:
1100 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1101 free_page1:
1102 __free_page(page);
1103 uninit:
1104 kvm_vcpu_uninit(&svm->vcpu);
1105 free_svm:
1106 kmem_cache_free(kvm_vcpu_cache, svm);
1107 out:
1108 return ERR_PTR(err);
1109 }
1110
1111 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1112 {
1113 struct vcpu_svm *svm = to_svm(vcpu);
1114
1115 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1116 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1117 __free_page(virt_to_page(svm->nested.hsave));
1118 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1119 kvm_vcpu_uninit(vcpu);
1120 kmem_cache_free(kvm_vcpu_cache, svm);
1121 }
1122
1123 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1124 {
1125 struct vcpu_svm *svm = to_svm(vcpu);
1126 int i;
1127
1128 if (unlikely(cpu != vcpu->cpu)) {
1129 svm->asid_generation = 0;
1130 mark_all_dirty(svm->vmcb);
1131 }
1132
1133 #ifdef CONFIG_X86_64
1134 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1135 #endif
1136 savesegment(fs, svm->host.fs);
1137 savesegment(gs, svm->host.gs);
1138 svm->host.ldt = kvm_read_ldt();
1139
1140 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1141 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1142 }
1143
1144 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1145 {
1146 struct vcpu_svm *svm = to_svm(vcpu);
1147 int i;
1148
1149 ++vcpu->stat.host_state_reload;
1150 kvm_load_ldt(svm->host.ldt);
1151 #ifdef CONFIG_X86_64
1152 loadsegment(fs, svm->host.fs);
1153 load_gs_index(svm->host.gs);
1154 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1155 #else
1156 loadsegment(gs, svm->host.gs);
1157 #endif
1158 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1159 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1160 }
1161
1162 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1163 {
1164 return to_svm(vcpu)->vmcb->save.rflags;
1165 }
1166
1167 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1168 {
1169 to_svm(vcpu)->vmcb->save.rflags = rflags;
1170 }
1171
1172 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1173 {
1174 switch (reg) {
1175 case VCPU_EXREG_PDPTR:
1176 BUG_ON(!npt_enabled);
1177 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1178 break;
1179 default:
1180 BUG();
1181 }
1182 }
1183
1184 static void svm_set_vintr(struct vcpu_svm *svm)
1185 {
1186 set_intercept(svm, INTERCEPT_VINTR);
1187 }
1188
1189 static void svm_clear_vintr(struct vcpu_svm *svm)
1190 {
1191 clr_intercept(svm, INTERCEPT_VINTR);
1192 }
1193
1194 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1195 {
1196 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1197
1198 switch (seg) {
1199 case VCPU_SREG_CS: return &save->cs;
1200 case VCPU_SREG_DS: return &save->ds;
1201 case VCPU_SREG_ES: return &save->es;
1202 case VCPU_SREG_FS: return &save->fs;
1203 case VCPU_SREG_GS: return &save->gs;
1204 case VCPU_SREG_SS: return &save->ss;
1205 case VCPU_SREG_TR: return &save->tr;
1206 case VCPU_SREG_LDTR: return &save->ldtr;
1207 }
1208 BUG();
1209 return NULL;
1210 }
1211
1212 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1213 {
1214 struct vmcb_seg *s = svm_seg(vcpu, seg);
1215
1216 return s->base;
1217 }
1218
1219 static void svm_get_segment(struct kvm_vcpu *vcpu,
1220 struct kvm_segment *var, int seg)
1221 {
1222 struct vmcb_seg *s = svm_seg(vcpu, seg);
1223
1224 var->base = s->base;
1225 var->limit = s->limit;
1226 var->selector = s->selector;
1227 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1228 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1229 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1230 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1231 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1232 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1233 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1234 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1235
1236 /*
1237 * AMD's VMCB does not have an explicit unusable field, so emulate it
1238 * for cross vendor migration purposes by "not present"
1239 */
1240 var->unusable = !var->present || (var->type == 0);
1241
1242 switch (seg) {
1243 case VCPU_SREG_CS:
1244 /*
1245 * SVM always stores 0 for the 'G' bit in the CS selector in
1246 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1247 * Intel's VMENTRY has a check on the 'G' bit.
1248 */
1249 var->g = s->limit > 0xfffff;
1250 break;
1251 case VCPU_SREG_TR:
1252 /*
1253 * Work around a bug where the busy flag in the tr selector
1254 * isn't exposed
1255 */
1256 var->type |= 0x2;
1257 break;
1258 case VCPU_SREG_DS:
1259 case VCPU_SREG_ES:
1260 case VCPU_SREG_FS:
1261 case VCPU_SREG_GS:
1262 /*
1263 * The accessed bit must always be set in the segment
1264 * descriptor cache, although it can be cleared in the
1265 * descriptor, the cached bit always remains at 1. Since
1266 * Intel has a check on this, set it here to support
1267 * cross-vendor migration.
1268 */
1269 if (!var->unusable)
1270 var->type |= 0x1;
1271 break;
1272 case VCPU_SREG_SS:
1273 /*
1274 * On AMD CPUs sometimes the DB bit in the segment
1275 * descriptor is left as 1, although the whole segment has
1276 * been made unusable. Clear it here to pass an Intel VMX
1277 * entry check when cross vendor migrating.
1278 */
1279 if (var->unusable)
1280 var->db = 0;
1281 break;
1282 }
1283 }
1284
1285 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1286 {
1287 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1288
1289 return save->cpl;
1290 }
1291
1292 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1293 {
1294 struct vcpu_svm *svm = to_svm(vcpu);
1295
1296 dt->size = svm->vmcb->save.idtr.limit;
1297 dt->address = svm->vmcb->save.idtr.base;
1298 }
1299
1300 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1301 {
1302 struct vcpu_svm *svm = to_svm(vcpu);
1303
1304 svm->vmcb->save.idtr.limit = dt->size;
1305 svm->vmcb->save.idtr.base = dt->address ;
1306 mark_dirty(svm->vmcb, VMCB_DT);
1307 }
1308
1309 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1310 {
1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
1313 dt->size = svm->vmcb->save.gdtr.limit;
1314 dt->address = svm->vmcb->save.gdtr.base;
1315 }
1316
1317 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1318 {
1319 struct vcpu_svm *svm = to_svm(vcpu);
1320
1321 svm->vmcb->save.gdtr.limit = dt->size;
1322 svm->vmcb->save.gdtr.base = dt->address ;
1323 mark_dirty(svm->vmcb, VMCB_DT);
1324 }
1325
1326 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1327 {
1328 }
1329
1330 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1331 {
1332 }
1333
1334 static void update_cr0_intercept(struct vcpu_svm *svm)
1335 {
1336 ulong gcr0 = svm->vcpu.arch.cr0;
1337 u64 *hcr0 = &svm->vmcb->save.cr0;
1338
1339 if (!svm->vcpu.fpu_active)
1340 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1341 else
1342 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1343 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1344
1345 mark_dirty(svm->vmcb, VMCB_CR);
1346
1347 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1348 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1349 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1350 } else {
1351 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1352 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1353 }
1354 }
1355
1356 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1357 {
1358 struct vcpu_svm *svm = to_svm(vcpu);
1359
1360 if (is_guest_mode(vcpu)) {
1361 /*
1362 * We are here because we run in nested mode, the host kvm
1363 * intercepts cr0 writes but the l1 hypervisor does not.
1364 * But the L1 hypervisor may intercept selective cr0 writes.
1365 * This needs to be checked here.
1366 */
1367 unsigned long old, new;
1368
1369 /* Remove bits that would trigger a real cr0 write intercept */
1370 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1371 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1372
1373 if (old == new) {
1374 /* cr0 write with ts and mp unchanged */
1375 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1376 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1377 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1378 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1379 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1380 return;
1381 }
1382 }
1383 }
1384
1385 #ifdef CONFIG_X86_64
1386 if (vcpu->arch.efer & EFER_LME) {
1387 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1388 vcpu->arch.efer |= EFER_LMA;
1389 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1390 }
1391
1392 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1393 vcpu->arch.efer &= ~EFER_LMA;
1394 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1395 }
1396 }
1397 #endif
1398 vcpu->arch.cr0 = cr0;
1399
1400 if (!npt_enabled)
1401 cr0 |= X86_CR0_PG | X86_CR0_WP;
1402
1403 if (!vcpu->fpu_active)
1404 cr0 |= X86_CR0_TS;
1405 /*
1406 * re-enable caching here because the QEMU bios
1407 * does not do it - this results in some delay at
1408 * reboot
1409 */
1410 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1411 svm->vmcb->save.cr0 = cr0;
1412 mark_dirty(svm->vmcb, VMCB_CR);
1413 update_cr0_intercept(svm);
1414 }
1415
1416 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1417 {
1418 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1419 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1420
1421 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1422 force_new_asid(vcpu);
1423
1424 vcpu->arch.cr4 = cr4;
1425 if (!npt_enabled)
1426 cr4 |= X86_CR4_PAE;
1427 cr4 |= host_cr4_mce;
1428 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1429 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1430 }
1431
1432 static void svm_set_segment(struct kvm_vcpu *vcpu,
1433 struct kvm_segment *var, int seg)
1434 {
1435 struct vcpu_svm *svm = to_svm(vcpu);
1436 struct vmcb_seg *s = svm_seg(vcpu, seg);
1437
1438 s->base = var->base;
1439 s->limit = var->limit;
1440 s->selector = var->selector;
1441 if (var->unusable)
1442 s->attrib = 0;
1443 else {
1444 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1445 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1446 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1447 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1448 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1449 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1450 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1451 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1452 }
1453 if (seg == VCPU_SREG_CS)
1454 svm->vmcb->save.cpl
1455 = (svm->vmcb->save.cs.attrib
1456 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1457
1458 mark_dirty(svm->vmcb, VMCB_SEG);
1459 }
1460
1461 static void update_db_intercept(struct kvm_vcpu *vcpu)
1462 {
1463 struct vcpu_svm *svm = to_svm(vcpu);
1464
1465 clr_exception_intercept(svm, DB_VECTOR);
1466 clr_exception_intercept(svm, BP_VECTOR);
1467
1468 if (svm->nmi_singlestep)
1469 set_exception_intercept(svm, DB_VECTOR);
1470
1471 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1472 if (vcpu->guest_debug &
1473 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1474 set_exception_intercept(svm, DB_VECTOR);
1475 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1476 set_exception_intercept(svm, BP_VECTOR);
1477 } else
1478 vcpu->guest_debug = 0;
1479 }
1480
1481 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1482 {
1483 struct vcpu_svm *svm = to_svm(vcpu);
1484
1485 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1486 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1487 else
1488 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1489
1490 mark_dirty(svm->vmcb, VMCB_DR);
1491
1492 update_db_intercept(vcpu);
1493 }
1494
1495 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1496 {
1497 if (sd->next_asid > sd->max_asid) {
1498 ++sd->asid_generation;
1499 sd->next_asid = 1;
1500 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1501 }
1502
1503 svm->asid_generation = sd->asid_generation;
1504 svm->vmcb->control.asid = sd->next_asid++;
1505
1506 mark_dirty(svm->vmcb, VMCB_ASID);
1507 }
1508
1509 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1510 {
1511 struct vcpu_svm *svm = to_svm(vcpu);
1512
1513 svm->vmcb->save.dr7 = value;
1514 mark_dirty(svm->vmcb, VMCB_DR);
1515 }
1516
1517 static int pf_interception(struct vcpu_svm *svm)
1518 {
1519 u64 fault_address = svm->vmcb->control.exit_info_2;
1520 u32 error_code;
1521 int r = 1;
1522
1523 switch (svm->apf_reason) {
1524 default:
1525 error_code = svm->vmcb->control.exit_info_1;
1526
1527 trace_kvm_page_fault(fault_address, error_code);
1528 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1529 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1530 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1531 break;
1532 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1533 svm->apf_reason = 0;
1534 local_irq_disable();
1535 kvm_async_pf_task_wait(fault_address);
1536 local_irq_enable();
1537 break;
1538 case KVM_PV_REASON_PAGE_READY:
1539 svm->apf_reason = 0;
1540 local_irq_disable();
1541 kvm_async_pf_task_wake(fault_address);
1542 local_irq_enable();
1543 break;
1544 }
1545 return r;
1546 }
1547
1548 static int db_interception(struct vcpu_svm *svm)
1549 {
1550 struct kvm_run *kvm_run = svm->vcpu.run;
1551
1552 if (!(svm->vcpu.guest_debug &
1553 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1554 !svm->nmi_singlestep) {
1555 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1556 return 1;
1557 }
1558
1559 if (svm->nmi_singlestep) {
1560 svm->nmi_singlestep = false;
1561 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1562 svm->vmcb->save.rflags &=
1563 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1564 update_db_intercept(&svm->vcpu);
1565 }
1566
1567 if (svm->vcpu.guest_debug &
1568 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1569 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1570 kvm_run->debug.arch.pc =
1571 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1572 kvm_run->debug.arch.exception = DB_VECTOR;
1573 return 0;
1574 }
1575
1576 return 1;
1577 }
1578
1579 static int bp_interception(struct vcpu_svm *svm)
1580 {
1581 struct kvm_run *kvm_run = svm->vcpu.run;
1582
1583 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1584 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1585 kvm_run->debug.arch.exception = BP_VECTOR;
1586 return 0;
1587 }
1588
1589 static int ud_interception(struct vcpu_svm *svm)
1590 {
1591 int er;
1592
1593 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1594 if (er != EMULATE_DONE)
1595 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1596 return 1;
1597 }
1598
1599 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1600 {
1601 struct vcpu_svm *svm = to_svm(vcpu);
1602
1603 clr_exception_intercept(svm, NM_VECTOR);
1604
1605 svm->vcpu.fpu_active = 1;
1606 update_cr0_intercept(svm);
1607 }
1608
1609 static int nm_interception(struct vcpu_svm *svm)
1610 {
1611 svm_fpu_activate(&svm->vcpu);
1612 return 1;
1613 }
1614
1615 static bool is_erratum_383(void)
1616 {
1617 int err, i;
1618 u64 value;
1619
1620 if (!erratum_383_found)
1621 return false;
1622
1623 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1624 if (err)
1625 return false;
1626
1627 /* Bit 62 may or may not be set for this mce */
1628 value &= ~(1ULL << 62);
1629
1630 if (value != 0xb600000000010015ULL)
1631 return false;
1632
1633 /* Clear MCi_STATUS registers */
1634 for (i = 0; i < 6; ++i)
1635 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1636
1637 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1638 if (!err) {
1639 u32 low, high;
1640
1641 value &= ~(1ULL << 2);
1642 low = lower_32_bits(value);
1643 high = upper_32_bits(value);
1644
1645 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1646 }
1647
1648 /* Flush tlb to evict multi-match entries */
1649 __flush_tlb_all();
1650
1651 return true;
1652 }
1653
1654 static void svm_handle_mce(struct vcpu_svm *svm)
1655 {
1656 if (is_erratum_383()) {
1657 /*
1658 * Erratum 383 triggered. Guest state is corrupt so kill the
1659 * guest.
1660 */
1661 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1662
1663 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1664
1665 return;
1666 }
1667
1668 /*
1669 * On an #MC intercept the MCE handler is not called automatically in
1670 * the host. So do it by hand here.
1671 */
1672 asm volatile (
1673 "int $0x12\n");
1674 /* not sure if we ever come back to this point */
1675
1676 return;
1677 }
1678
1679 static int mc_interception(struct vcpu_svm *svm)
1680 {
1681 return 1;
1682 }
1683
1684 static int shutdown_interception(struct vcpu_svm *svm)
1685 {
1686 struct kvm_run *kvm_run = svm->vcpu.run;
1687
1688 /*
1689 * VMCB is undefined after a SHUTDOWN intercept
1690 * so reinitialize it.
1691 */
1692 clear_page(svm->vmcb);
1693 init_vmcb(svm);
1694
1695 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1696 return 0;
1697 }
1698
1699 static int io_interception(struct vcpu_svm *svm)
1700 {
1701 struct kvm_vcpu *vcpu = &svm->vcpu;
1702 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1703 int size, in, string;
1704 unsigned port;
1705
1706 ++svm->vcpu.stat.io_exits;
1707 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1708 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1709 if (string || in)
1710 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1711
1712 port = io_info >> 16;
1713 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1714 svm->next_rip = svm->vmcb->control.exit_info_2;
1715 skip_emulated_instruction(&svm->vcpu);
1716
1717 return kvm_fast_pio_out(vcpu, size, port);
1718 }
1719
1720 static int nmi_interception(struct vcpu_svm *svm)
1721 {
1722 return 1;
1723 }
1724
1725 static int intr_interception(struct vcpu_svm *svm)
1726 {
1727 ++svm->vcpu.stat.irq_exits;
1728 return 1;
1729 }
1730
1731 static int nop_on_interception(struct vcpu_svm *svm)
1732 {
1733 return 1;
1734 }
1735
1736 static int halt_interception(struct vcpu_svm *svm)
1737 {
1738 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1739 skip_emulated_instruction(&svm->vcpu);
1740 return kvm_emulate_halt(&svm->vcpu);
1741 }
1742
1743 static int vmmcall_interception(struct vcpu_svm *svm)
1744 {
1745 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1746 skip_emulated_instruction(&svm->vcpu);
1747 kvm_emulate_hypercall(&svm->vcpu);
1748 return 1;
1749 }
1750
1751 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1752 {
1753 struct vcpu_svm *svm = to_svm(vcpu);
1754
1755 return svm->nested.nested_cr3;
1756 }
1757
1758 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1759 unsigned long root)
1760 {
1761 struct vcpu_svm *svm = to_svm(vcpu);
1762
1763 svm->vmcb->control.nested_cr3 = root;
1764 mark_dirty(svm->vmcb, VMCB_NPT);
1765 force_new_asid(vcpu);
1766 }
1767
1768 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1769 struct x86_exception *fault)
1770 {
1771 struct vcpu_svm *svm = to_svm(vcpu);
1772
1773 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1774 svm->vmcb->control.exit_code_hi = 0;
1775 svm->vmcb->control.exit_info_1 = fault->error_code;
1776 svm->vmcb->control.exit_info_2 = fault->address;
1777
1778 nested_svm_vmexit(svm);
1779 }
1780
1781 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1782 {
1783 int r;
1784
1785 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1786
1787 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1788 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1789 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1790 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1791 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1792
1793 return r;
1794 }
1795
1796 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1797 {
1798 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1799 }
1800
1801 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1802 {
1803 if (!(svm->vcpu.arch.efer & EFER_SVME)
1804 || !is_paging(&svm->vcpu)) {
1805 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1806 return 1;
1807 }
1808
1809 if (svm->vmcb->save.cpl) {
1810 kvm_inject_gp(&svm->vcpu, 0);
1811 return 1;
1812 }
1813
1814 return 0;
1815 }
1816
1817 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1818 bool has_error_code, u32 error_code)
1819 {
1820 int vmexit;
1821
1822 if (!is_guest_mode(&svm->vcpu))
1823 return 0;
1824
1825 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1826 svm->vmcb->control.exit_code_hi = 0;
1827 svm->vmcb->control.exit_info_1 = error_code;
1828 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1829
1830 vmexit = nested_svm_intercept(svm);
1831 if (vmexit == NESTED_EXIT_DONE)
1832 svm->nested.exit_required = true;
1833
1834 return vmexit;
1835 }
1836
1837 /* This function returns true if it is save to enable the irq window */
1838 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1839 {
1840 if (!is_guest_mode(&svm->vcpu))
1841 return true;
1842
1843 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1844 return true;
1845
1846 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1847 return false;
1848
1849 /*
1850 * if vmexit was already requested (by intercepted exception
1851 * for instance) do not overwrite it with "external interrupt"
1852 * vmexit.
1853 */
1854 if (svm->nested.exit_required)
1855 return false;
1856
1857 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1858 svm->vmcb->control.exit_info_1 = 0;
1859 svm->vmcb->control.exit_info_2 = 0;
1860
1861 if (svm->nested.intercept & 1ULL) {
1862 /*
1863 * The #vmexit can't be emulated here directly because this
1864 * code path runs with irqs and preemtion disabled. A
1865 * #vmexit emulation might sleep. Only signal request for
1866 * the #vmexit here.
1867 */
1868 svm->nested.exit_required = true;
1869 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1870 return false;
1871 }
1872
1873 return true;
1874 }
1875
1876 /* This function returns true if it is save to enable the nmi window */
1877 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1878 {
1879 if (!is_guest_mode(&svm->vcpu))
1880 return true;
1881
1882 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1883 return true;
1884
1885 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1886 svm->nested.exit_required = true;
1887
1888 return false;
1889 }
1890
1891 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1892 {
1893 struct page *page;
1894
1895 might_sleep();
1896
1897 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1898 if (is_error_page(page))
1899 goto error;
1900
1901 *_page = page;
1902
1903 return kmap(page);
1904
1905 error:
1906 kvm_release_page_clean(page);
1907 kvm_inject_gp(&svm->vcpu, 0);
1908
1909 return NULL;
1910 }
1911
1912 static void nested_svm_unmap(struct page *page)
1913 {
1914 kunmap(page);
1915 kvm_release_page_dirty(page);
1916 }
1917
1918 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1919 {
1920 unsigned port;
1921 u8 val, bit;
1922 u64 gpa;
1923
1924 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1925 return NESTED_EXIT_HOST;
1926
1927 port = svm->vmcb->control.exit_info_1 >> 16;
1928 gpa = svm->nested.vmcb_iopm + (port / 8);
1929 bit = port % 8;
1930 val = 0;
1931
1932 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1933 val &= (1 << bit);
1934
1935 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1936 }
1937
1938 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1939 {
1940 u32 offset, msr, value;
1941 int write, mask;
1942
1943 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1944 return NESTED_EXIT_HOST;
1945
1946 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1947 offset = svm_msrpm_offset(msr);
1948 write = svm->vmcb->control.exit_info_1 & 1;
1949 mask = 1 << ((2 * (msr & 0xf)) + write);
1950
1951 if (offset == MSR_INVALID)
1952 return NESTED_EXIT_DONE;
1953
1954 /* Offset is in 32 bit units but need in 8 bit units */
1955 offset *= 4;
1956
1957 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1958 return NESTED_EXIT_DONE;
1959
1960 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1961 }
1962
1963 static int nested_svm_exit_special(struct vcpu_svm *svm)
1964 {
1965 u32 exit_code = svm->vmcb->control.exit_code;
1966
1967 switch (exit_code) {
1968 case SVM_EXIT_INTR:
1969 case SVM_EXIT_NMI:
1970 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1971 return NESTED_EXIT_HOST;
1972 case SVM_EXIT_NPF:
1973 /* For now we are always handling NPFs when using them */
1974 if (npt_enabled)
1975 return NESTED_EXIT_HOST;
1976 break;
1977 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1978 /* When we're shadowing, trap PFs, but not async PF */
1979 if (!npt_enabled && svm->apf_reason == 0)
1980 return NESTED_EXIT_HOST;
1981 break;
1982 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1983 nm_interception(svm);
1984 break;
1985 default:
1986 break;
1987 }
1988
1989 return NESTED_EXIT_CONTINUE;
1990 }
1991
1992 /*
1993 * If this function returns true, this #vmexit was already handled
1994 */
1995 static int nested_svm_intercept(struct vcpu_svm *svm)
1996 {
1997 u32 exit_code = svm->vmcb->control.exit_code;
1998 int vmexit = NESTED_EXIT_HOST;
1999
2000 switch (exit_code) {
2001 case SVM_EXIT_MSR:
2002 vmexit = nested_svm_exit_handled_msr(svm);
2003 break;
2004 case SVM_EXIT_IOIO:
2005 vmexit = nested_svm_intercept_ioio(svm);
2006 break;
2007 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2008 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2009 if (svm->nested.intercept_cr & bit)
2010 vmexit = NESTED_EXIT_DONE;
2011 break;
2012 }
2013 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2014 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2015 if (svm->nested.intercept_dr & bit)
2016 vmexit = NESTED_EXIT_DONE;
2017 break;
2018 }
2019 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2020 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2021 if (svm->nested.intercept_exceptions & excp_bits)
2022 vmexit = NESTED_EXIT_DONE;
2023 /* async page fault always cause vmexit */
2024 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2025 svm->apf_reason != 0)
2026 vmexit = NESTED_EXIT_DONE;
2027 break;
2028 }
2029 case SVM_EXIT_ERR: {
2030 vmexit = NESTED_EXIT_DONE;
2031 break;
2032 }
2033 default: {
2034 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2035 if (svm->nested.intercept & exit_bits)
2036 vmexit = NESTED_EXIT_DONE;
2037 }
2038 }
2039
2040 return vmexit;
2041 }
2042
2043 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2044 {
2045 int vmexit;
2046
2047 vmexit = nested_svm_intercept(svm);
2048
2049 if (vmexit == NESTED_EXIT_DONE)
2050 nested_svm_vmexit(svm);
2051
2052 return vmexit;
2053 }
2054
2055 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2056 {
2057 struct vmcb_control_area *dst = &dst_vmcb->control;
2058 struct vmcb_control_area *from = &from_vmcb->control;
2059
2060 dst->intercept_cr = from->intercept_cr;
2061 dst->intercept_dr = from->intercept_dr;
2062 dst->intercept_exceptions = from->intercept_exceptions;
2063 dst->intercept = from->intercept;
2064 dst->iopm_base_pa = from->iopm_base_pa;
2065 dst->msrpm_base_pa = from->msrpm_base_pa;
2066 dst->tsc_offset = from->tsc_offset;
2067 dst->asid = from->asid;
2068 dst->tlb_ctl = from->tlb_ctl;
2069 dst->int_ctl = from->int_ctl;
2070 dst->int_vector = from->int_vector;
2071 dst->int_state = from->int_state;
2072 dst->exit_code = from->exit_code;
2073 dst->exit_code_hi = from->exit_code_hi;
2074 dst->exit_info_1 = from->exit_info_1;
2075 dst->exit_info_2 = from->exit_info_2;
2076 dst->exit_int_info = from->exit_int_info;
2077 dst->exit_int_info_err = from->exit_int_info_err;
2078 dst->nested_ctl = from->nested_ctl;
2079 dst->event_inj = from->event_inj;
2080 dst->event_inj_err = from->event_inj_err;
2081 dst->nested_cr3 = from->nested_cr3;
2082 dst->lbr_ctl = from->lbr_ctl;
2083 }
2084
2085 static int nested_svm_vmexit(struct vcpu_svm *svm)
2086 {
2087 struct vmcb *nested_vmcb;
2088 struct vmcb *hsave = svm->nested.hsave;
2089 struct vmcb *vmcb = svm->vmcb;
2090 struct page *page;
2091
2092 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2093 vmcb->control.exit_info_1,
2094 vmcb->control.exit_info_2,
2095 vmcb->control.exit_int_info,
2096 vmcb->control.exit_int_info_err);
2097
2098 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2099 if (!nested_vmcb)
2100 return 1;
2101
2102 /* Exit Guest-Mode */
2103 leave_guest_mode(&svm->vcpu);
2104 svm->nested.vmcb = 0;
2105
2106 /* Give the current vmcb to the guest */
2107 disable_gif(svm);
2108
2109 nested_vmcb->save.es = vmcb->save.es;
2110 nested_vmcb->save.cs = vmcb->save.cs;
2111 nested_vmcb->save.ss = vmcb->save.ss;
2112 nested_vmcb->save.ds = vmcb->save.ds;
2113 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2114 nested_vmcb->save.idtr = vmcb->save.idtr;
2115 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2116 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2117 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2118 nested_vmcb->save.cr2 = vmcb->save.cr2;
2119 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2120 nested_vmcb->save.rflags = vmcb->save.rflags;
2121 nested_vmcb->save.rip = vmcb->save.rip;
2122 nested_vmcb->save.rsp = vmcb->save.rsp;
2123 nested_vmcb->save.rax = vmcb->save.rax;
2124 nested_vmcb->save.dr7 = vmcb->save.dr7;
2125 nested_vmcb->save.dr6 = vmcb->save.dr6;
2126 nested_vmcb->save.cpl = vmcb->save.cpl;
2127
2128 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2129 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2130 nested_vmcb->control.int_state = vmcb->control.int_state;
2131 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2132 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2133 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2134 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2135 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2136 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2137 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2138
2139 /*
2140 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2141 * to make sure that we do not lose injected events. So check event_inj
2142 * here and copy it to exit_int_info if it is valid.
2143 * Exit_int_info and event_inj can't be both valid because the case
2144 * below only happens on a VMRUN instruction intercept which has
2145 * no valid exit_int_info set.
2146 */
2147 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2148 struct vmcb_control_area *nc = &nested_vmcb->control;
2149
2150 nc->exit_int_info = vmcb->control.event_inj;
2151 nc->exit_int_info_err = vmcb->control.event_inj_err;
2152 }
2153
2154 nested_vmcb->control.tlb_ctl = 0;
2155 nested_vmcb->control.event_inj = 0;
2156 nested_vmcb->control.event_inj_err = 0;
2157
2158 /* We always set V_INTR_MASKING and remember the old value in hflags */
2159 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2160 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2161
2162 /* Restore the original control entries */
2163 copy_vmcb_control_area(vmcb, hsave);
2164
2165 kvm_clear_exception_queue(&svm->vcpu);
2166 kvm_clear_interrupt_queue(&svm->vcpu);
2167
2168 svm->nested.nested_cr3 = 0;
2169
2170 /* Restore selected save entries */
2171 svm->vmcb->save.es = hsave->save.es;
2172 svm->vmcb->save.cs = hsave->save.cs;
2173 svm->vmcb->save.ss = hsave->save.ss;
2174 svm->vmcb->save.ds = hsave->save.ds;
2175 svm->vmcb->save.gdtr = hsave->save.gdtr;
2176 svm->vmcb->save.idtr = hsave->save.idtr;
2177 svm->vmcb->save.rflags = hsave->save.rflags;
2178 svm_set_efer(&svm->vcpu, hsave->save.efer);
2179 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2180 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2181 if (npt_enabled) {
2182 svm->vmcb->save.cr3 = hsave->save.cr3;
2183 svm->vcpu.arch.cr3 = hsave->save.cr3;
2184 } else {
2185 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2186 }
2187 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2188 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2189 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2190 svm->vmcb->save.dr7 = 0;
2191 svm->vmcb->save.cpl = 0;
2192 svm->vmcb->control.exit_int_info = 0;
2193
2194 mark_all_dirty(svm->vmcb);
2195
2196 nested_svm_unmap(page);
2197
2198 nested_svm_uninit_mmu_context(&svm->vcpu);
2199 kvm_mmu_reset_context(&svm->vcpu);
2200 kvm_mmu_load(&svm->vcpu);
2201
2202 return 0;
2203 }
2204
2205 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2206 {
2207 /*
2208 * This function merges the msr permission bitmaps of kvm and the
2209 * nested vmcb. It is omptimized in that it only merges the parts where
2210 * the kvm msr permission bitmap may contain zero bits
2211 */
2212 int i;
2213
2214 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2215 return true;
2216
2217 for (i = 0; i < MSRPM_OFFSETS; i++) {
2218 u32 value, p;
2219 u64 offset;
2220
2221 if (msrpm_offsets[i] == 0xffffffff)
2222 break;
2223
2224 p = msrpm_offsets[i];
2225 offset = svm->nested.vmcb_msrpm + (p * 4);
2226
2227 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2228 return false;
2229
2230 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2231 }
2232
2233 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2234
2235 return true;
2236 }
2237
2238 static bool nested_vmcb_checks(struct vmcb *vmcb)
2239 {
2240 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2241 return false;
2242
2243 if (vmcb->control.asid == 0)
2244 return false;
2245
2246 if (vmcb->control.nested_ctl && !npt_enabled)
2247 return false;
2248
2249 return true;
2250 }
2251
2252 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2253 {
2254 struct vmcb *nested_vmcb;
2255 struct vmcb *hsave = svm->nested.hsave;
2256 struct vmcb *vmcb = svm->vmcb;
2257 struct page *page;
2258 u64 vmcb_gpa;
2259
2260 vmcb_gpa = svm->vmcb->save.rax;
2261
2262 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2263 if (!nested_vmcb)
2264 return false;
2265
2266 if (!nested_vmcb_checks(nested_vmcb)) {
2267 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2268 nested_vmcb->control.exit_code_hi = 0;
2269 nested_vmcb->control.exit_info_1 = 0;
2270 nested_vmcb->control.exit_info_2 = 0;
2271
2272 nested_svm_unmap(page);
2273
2274 return false;
2275 }
2276
2277 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2278 nested_vmcb->save.rip,
2279 nested_vmcb->control.int_ctl,
2280 nested_vmcb->control.event_inj,
2281 nested_vmcb->control.nested_ctl);
2282
2283 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2284 nested_vmcb->control.intercept_cr >> 16,
2285 nested_vmcb->control.intercept_exceptions,
2286 nested_vmcb->control.intercept);
2287
2288 /* Clear internal status */
2289 kvm_clear_exception_queue(&svm->vcpu);
2290 kvm_clear_interrupt_queue(&svm->vcpu);
2291
2292 /*
2293 * Save the old vmcb, so we don't need to pick what we save, but can
2294 * restore everything when a VMEXIT occurs
2295 */
2296 hsave->save.es = vmcb->save.es;
2297 hsave->save.cs = vmcb->save.cs;
2298 hsave->save.ss = vmcb->save.ss;
2299 hsave->save.ds = vmcb->save.ds;
2300 hsave->save.gdtr = vmcb->save.gdtr;
2301 hsave->save.idtr = vmcb->save.idtr;
2302 hsave->save.efer = svm->vcpu.arch.efer;
2303 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2304 hsave->save.cr4 = svm->vcpu.arch.cr4;
2305 hsave->save.rflags = vmcb->save.rflags;
2306 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2307 hsave->save.rsp = vmcb->save.rsp;
2308 hsave->save.rax = vmcb->save.rax;
2309 if (npt_enabled)
2310 hsave->save.cr3 = vmcb->save.cr3;
2311 else
2312 hsave->save.cr3 = svm->vcpu.arch.cr3;
2313
2314 copy_vmcb_control_area(hsave, vmcb);
2315
2316 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2317 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2318 else
2319 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2320
2321 if (nested_vmcb->control.nested_ctl) {
2322 kvm_mmu_unload(&svm->vcpu);
2323 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2324 nested_svm_init_mmu_context(&svm->vcpu);
2325 }
2326
2327 /* Load the nested guest state */
2328 svm->vmcb->save.es = nested_vmcb->save.es;
2329 svm->vmcb->save.cs = nested_vmcb->save.cs;
2330 svm->vmcb->save.ss = nested_vmcb->save.ss;
2331 svm->vmcb->save.ds = nested_vmcb->save.ds;
2332 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2333 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2334 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2335 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2336 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2337 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2338 if (npt_enabled) {
2339 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2340 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2341 } else
2342 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2343
2344 /* Guest paging mode is active - reset mmu */
2345 kvm_mmu_reset_context(&svm->vcpu);
2346
2347 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2348 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2349 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2350 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2351
2352 /* In case we don't even reach vcpu_run, the fields are not updated */
2353 svm->vmcb->save.rax = nested_vmcb->save.rax;
2354 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2355 svm->vmcb->save.rip = nested_vmcb->save.rip;
2356 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2357 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2358 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2359
2360 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2361 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2362
2363 /* cache intercepts */
2364 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2365 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2366 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2367 svm->nested.intercept = nested_vmcb->control.intercept;
2368
2369 force_new_asid(&svm->vcpu);
2370 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2371 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2372 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2373 else
2374 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2375
2376 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2377 /* We only want the cr8 intercept bits of the guest */
2378 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2379 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2380 }
2381
2382 /* We don't want to see VMMCALLs from a nested guest */
2383 clr_intercept(svm, INTERCEPT_VMMCALL);
2384
2385 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2386 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2387 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2388 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2389 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2390 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2391
2392 nested_svm_unmap(page);
2393
2394 /* Enter Guest-Mode */
2395 enter_guest_mode(&svm->vcpu);
2396
2397 /*
2398 * Merge guest and host intercepts - must be called with vcpu in
2399 * guest-mode to take affect here
2400 */
2401 recalc_intercepts(svm);
2402
2403 svm->nested.vmcb = vmcb_gpa;
2404
2405 enable_gif(svm);
2406
2407 mark_all_dirty(svm->vmcb);
2408
2409 return true;
2410 }
2411
2412 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2413 {
2414 to_vmcb->save.fs = from_vmcb->save.fs;
2415 to_vmcb->save.gs = from_vmcb->save.gs;
2416 to_vmcb->save.tr = from_vmcb->save.tr;
2417 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2418 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2419 to_vmcb->save.star = from_vmcb->save.star;
2420 to_vmcb->save.lstar = from_vmcb->save.lstar;
2421 to_vmcb->save.cstar = from_vmcb->save.cstar;
2422 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2423 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2424 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2425 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2426 }
2427
2428 static int vmload_interception(struct vcpu_svm *svm)
2429 {
2430 struct vmcb *nested_vmcb;
2431 struct page *page;
2432
2433 if (nested_svm_check_permissions(svm))
2434 return 1;
2435
2436 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2437 skip_emulated_instruction(&svm->vcpu);
2438
2439 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2440 if (!nested_vmcb)
2441 return 1;
2442
2443 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2444 nested_svm_unmap(page);
2445
2446 return 1;
2447 }
2448
2449 static int vmsave_interception(struct vcpu_svm *svm)
2450 {
2451 struct vmcb *nested_vmcb;
2452 struct page *page;
2453
2454 if (nested_svm_check_permissions(svm))
2455 return 1;
2456
2457 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2458 skip_emulated_instruction(&svm->vcpu);
2459
2460 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2461 if (!nested_vmcb)
2462 return 1;
2463
2464 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2465 nested_svm_unmap(page);
2466
2467 return 1;
2468 }
2469
2470 static int vmrun_interception(struct vcpu_svm *svm)
2471 {
2472 if (nested_svm_check_permissions(svm))
2473 return 1;
2474
2475 /* Save rip after vmrun instruction */
2476 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2477
2478 if (!nested_svm_vmrun(svm))
2479 return 1;
2480
2481 if (!nested_svm_vmrun_msrpm(svm))
2482 goto failed;
2483
2484 return 1;
2485
2486 failed:
2487
2488 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2489 svm->vmcb->control.exit_code_hi = 0;
2490 svm->vmcb->control.exit_info_1 = 0;
2491 svm->vmcb->control.exit_info_2 = 0;
2492
2493 nested_svm_vmexit(svm);
2494
2495 return 1;
2496 }
2497
2498 static int stgi_interception(struct vcpu_svm *svm)
2499 {
2500 if (nested_svm_check_permissions(svm))
2501 return 1;
2502
2503 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2504 skip_emulated_instruction(&svm->vcpu);
2505 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2506
2507 enable_gif(svm);
2508
2509 return 1;
2510 }
2511
2512 static int clgi_interception(struct vcpu_svm *svm)
2513 {
2514 if (nested_svm_check_permissions(svm))
2515 return 1;
2516
2517 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2518 skip_emulated_instruction(&svm->vcpu);
2519
2520 disable_gif(svm);
2521
2522 /* After a CLGI no interrupts should come */
2523 svm_clear_vintr(svm);
2524 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2525
2526 mark_dirty(svm->vmcb, VMCB_INTR);
2527
2528 return 1;
2529 }
2530
2531 static int invlpga_interception(struct vcpu_svm *svm)
2532 {
2533 struct kvm_vcpu *vcpu = &svm->vcpu;
2534
2535 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2536 vcpu->arch.regs[VCPU_REGS_RAX]);
2537
2538 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2539 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2540
2541 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2542 skip_emulated_instruction(&svm->vcpu);
2543 return 1;
2544 }
2545
2546 static int skinit_interception(struct vcpu_svm *svm)
2547 {
2548 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2549
2550 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2551 return 1;
2552 }
2553
2554 static int invalid_op_interception(struct vcpu_svm *svm)
2555 {
2556 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2557 return 1;
2558 }
2559
2560 static int task_switch_interception(struct vcpu_svm *svm)
2561 {
2562 u16 tss_selector;
2563 int reason;
2564 int int_type = svm->vmcb->control.exit_int_info &
2565 SVM_EXITINTINFO_TYPE_MASK;
2566 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2567 uint32_t type =
2568 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2569 uint32_t idt_v =
2570 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2571 bool has_error_code = false;
2572 u32 error_code = 0;
2573
2574 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2575
2576 if (svm->vmcb->control.exit_info_2 &
2577 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2578 reason = TASK_SWITCH_IRET;
2579 else if (svm->vmcb->control.exit_info_2 &
2580 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2581 reason = TASK_SWITCH_JMP;
2582 else if (idt_v)
2583 reason = TASK_SWITCH_GATE;
2584 else
2585 reason = TASK_SWITCH_CALL;
2586
2587 if (reason == TASK_SWITCH_GATE) {
2588 switch (type) {
2589 case SVM_EXITINTINFO_TYPE_NMI:
2590 svm->vcpu.arch.nmi_injected = false;
2591 break;
2592 case SVM_EXITINTINFO_TYPE_EXEPT:
2593 if (svm->vmcb->control.exit_info_2 &
2594 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2595 has_error_code = true;
2596 error_code =
2597 (u32)svm->vmcb->control.exit_info_2;
2598 }
2599 kvm_clear_exception_queue(&svm->vcpu);
2600 break;
2601 case SVM_EXITINTINFO_TYPE_INTR:
2602 kvm_clear_interrupt_queue(&svm->vcpu);
2603 break;
2604 default:
2605 break;
2606 }
2607 }
2608
2609 if (reason != TASK_SWITCH_GATE ||
2610 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2611 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2612 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2613 skip_emulated_instruction(&svm->vcpu);
2614
2615 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2616 has_error_code, error_code) == EMULATE_FAIL) {
2617 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2618 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2619 svm->vcpu.run->internal.ndata = 0;
2620 return 0;
2621 }
2622 return 1;
2623 }
2624
2625 static int cpuid_interception(struct vcpu_svm *svm)
2626 {
2627 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2628 kvm_emulate_cpuid(&svm->vcpu);
2629 return 1;
2630 }
2631
2632 static int iret_interception(struct vcpu_svm *svm)
2633 {
2634 ++svm->vcpu.stat.nmi_window_exits;
2635 clr_intercept(svm, INTERCEPT_IRET);
2636 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2637 return 1;
2638 }
2639
2640 static int invlpg_interception(struct vcpu_svm *svm)
2641 {
2642 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2643 }
2644
2645 static int emulate_on_interception(struct vcpu_svm *svm)
2646 {
2647 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2648 }
2649
2650 static int cr0_write_interception(struct vcpu_svm *svm)
2651 {
2652 struct kvm_vcpu *vcpu = &svm->vcpu;
2653 int r;
2654
2655 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2656
2657 if (svm->nested.vmexit_rip) {
2658 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2659 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2660 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2661 svm->nested.vmexit_rip = 0;
2662 }
2663
2664 return r == EMULATE_DONE;
2665 }
2666
2667 static int cr8_write_interception(struct vcpu_svm *svm)
2668 {
2669 struct kvm_run *kvm_run = svm->vcpu.run;
2670
2671 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2672 /* instruction emulation calls kvm_set_cr8() */
2673 emulate_instruction(&svm->vcpu, 0, 0, 0);
2674 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2675 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2676 return 1;
2677 }
2678 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2679 return 1;
2680 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2681 return 0;
2682 }
2683
2684 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2685 {
2686 struct vcpu_svm *svm = to_svm(vcpu);
2687
2688 switch (ecx) {
2689 case MSR_IA32_TSC: {
2690 struct vmcb *vmcb = get_host_vmcb(svm);
2691
2692 *data = vmcb->control.tsc_offset + native_read_tsc();
2693 break;
2694 }
2695 case MSR_STAR:
2696 *data = svm->vmcb->save.star;
2697 break;
2698 #ifdef CONFIG_X86_64
2699 case MSR_LSTAR:
2700 *data = svm->vmcb->save.lstar;
2701 break;
2702 case MSR_CSTAR:
2703 *data = svm->vmcb->save.cstar;
2704 break;
2705 case MSR_KERNEL_GS_BASE:
2706 *data = svm->vmcb->save.kernel_gs_base;
2707 break;
2708 case MSR_SYSCALL_MASK:
2709 *data = svm->vmcb->save.sfmask;
2710 break;
2711 #endif
2712 case MSR_IA32_SYSENTER_CS:
2713 *data = svm->vmcb->save.sysenter_cs;
2714 break;
2715 case MSR_IA32_SYSENTER_EIP:
2716 *data = svm->sysenter_eip;
2717 break;
2718 case MSR_IA32_SYSENTER_ESP:
2719 *data = svm->sysenter_esp;
2720 break;
2721 /*
2722 * Nobody will change the following 5 values in the VMCB so we can
2723 * safely return them on rdmsr. They will always be 0 until LBRV is
2724 * implemented.
2725 */
2726 case MSR_IA32_DEBUGCTLMSR:
2727 *data = svm->vmcb->save.dbgctl;
2728 break;
2729 case MSR_IA32_LASTBRANCHFROMIP:
2730 *data = svm->vmcb->save.br_from;
2731 break;
2732 case MSR_IA32_LASTBRANCHTOIP:
2733 *data = svm->vmcb->save.br_to;
2734 break;
2735 case MSR_IA32_LASTINTFROMIP:
2736 *data = svm->vmcb->save.last_excp_from;
2737 break;
2738 case MSR_IA32_LASTINTTOIP:
2739 *data = svm->vmcb->save.last_excp_to;
2740 break;
2741 case MSR_VM_HSAVE_PA:
2742 *data = svm->nested.hsave_msr;
2743 break;
2744 case MSR_VM_CR:
2745 *data = svm->nested.vm_cr_msr;
2746 break;
2747 case MSR_IA32_UCODE_REV:
2748 *data = 0x01000065;
2749 break;
2750 default:
2751 return kvm_get_msr_common(vcpu, ecx, data);
2752 }
2753 return 0;
2754 }
2755
2756 static int rdmsr_interception(struct vcpu_svm *svm)
2757 {
2758 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2759 u64 data;
2760
2761 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2762 trace_kvm_msr_read_ex(ecx);
2763 kvm_inject_gp(&svm->vcpu, 0);
2764 } else {
2765 trace_kvm_msr_read(ecx, data);
2766
2767 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2768 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2769 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2770 skip_emulated_instruction(&svm->vcpu);
2771 }
2772 return 1;
2773 }
2774
2775 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2776 {
2777 struct vcpu_svm *svm = to_svm(vcpu);
2778 int svm_dis, chg_mask;
2779
2780 if (data & ~SVM_VM_CR_VALID_MASK)
2781 return 1;
2782
2783 chg_mask = SVM_VM_CR_VALID_MASK;
2784
2785 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2786 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2787
2788 svm->nested.vm_cr_msr &= ~chg_mask;
2789 svm->nested.vm_cr_msr |= (data & chg_mask);
2790
2791 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2792
2793 /* check for svm_disable while efer.svme is set */
2794 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2795 return 1;
2796
2797 return 0;
2798 }
2799
2800 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2801 {
2802 struct vcpu_svm *svm = to_svm(vcpu);
2803
2804 switch (ecx) {
2805 case MSR_IA32_TSC:
2806 kvm_write_tsc(vcpu, data);
2807 break;
2808 case MSR_STAR:
2809 svm->vmcb->save.star = data;
2810 break;
2811 #ifdef CONFIG_X86_64
2812 case MSR_LSTAR:
2813 svm->vmcb->save.lstar = data;
2814 break;
2815 case MSR_CSTAR:
2816 svm->vmcb->save.cstar = data;
2817 break;
2818 case MSR_KERNEL_GS_BASE:
2819 svm->vmcb->save.kernel_gs_base = data;
2820 break;
2821 case MSR_SYSCALL_MASK:
2822 svm->vmcb->save.sfmask = data;
2823 break;
2824 #endif
2825 case MSR_IA32_SYSENTER_CS:
2826 svm->vmcb->save.sysenter_cs = data;
2827 break;
2828 case MSR_IA32_SYSENTER_EIP:
2829 svm->sysenter_eip = data;
2830 svm->vmcb->save.sysenter_eip = data;
2831 break;
2832 case MSR_IA32_SYSENTER_ESP:
2833 svm->sysenter_esp = data;
2834 svm->vmcb->save.sysenter_esp = data;
2835 break;
2836 case MSR_IA32_DEBUGCTLMSR:
2837 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2838 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2839 __func__, data);
2840 break;
2841 }
2842 if (data & DEBUGCTL_RESERVED_BITS)
2843 return 1;
2844
2845 svm->vmcb->save.dbgctl = data;
2846 mark_dirty(svm->vmcb, VMCB_LBR);
2847 if (data & (1ULL<<0))
2848 svm_enable_lbrv(svm);
2849 else
2850 svm_disable_lbrv(svm);
2851 break;
2852 case MSR_VM_HSAVE_PA:
2853 svm->nested.hsave_msr = data;
2854 break;
2855 case MSR_VM_CR:
2856 return svm_set_vm_cr(vcpu, data);
2857 case MSR_VM_IGNNE:
2858 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2859 break;
2860 default:
2861 return kvm_set_msr_common(vcpu, ecx, data);
2862 }
2863 return 0;
2864 }
2865
2866 static int wrmsr_interception(struct vcpu_svm *svm)
2867 {
2868 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2869 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2870 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2871
2872
2873 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2874 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2875 trace_kvm_msr_write_ex(ecx, data);
2876 kvm_inject_gp(&svm->vcpu, 0);
2877 } else {
2878 trace_kvm_msr_write(ecx, data);
2879 skip_emulated_instruction(&svm->vcpu);
2880 }
2881 return 1;
2882 }
2883
2884 static int msr_interception(struct vcpu_svm *svm)
2885 {
2886 if (svm->vmcb->control.exit_info_1)
2887 return wrmsr_interception(svm);
2888 else
2889 return rdmsr_interception(svm);
2890 }
2891
2892 static int interrupt_window_interception(struct vcpu_svm *svm)
2893 {
2894 struct kvm_run *kvm_run = svm->vcpu.run;
2895
2896 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2897 svm_clear_vintr(svm);
2898 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2899 mark_dirty(svm->vmcb, VMCB_INTR);
2900 /*
2901 * If the user space waits to inject interrupts, exit as soon as
2902 * possible
2903 */
2904 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2905 kvm_run->request_interrupt_window &&
2906 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2907 ++svm->vcpu.stat.irq_window_exits;
2908 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2909 return 0;
2910 }
2911
2912 return 1;
2913 }
2914
2915 static int pause_interception(struct vcpu_svm *svm)
2916 {
2917 kvm_vcpu_on_spin(&(svm->vcpu));
2918 return 1;
2919 }
2920
2921 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2922 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2923 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2924 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2925 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2926 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2927 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2928 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2929 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2930 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2931 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2932 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2933 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2934 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2935 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2936 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2937 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2938 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2939 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2940 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2941 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2942 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2943 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2944 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2945 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2946 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2947 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2948 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2949 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2950 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2951 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2952 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2953 [SVM_EXIT_INTR] = intr_interception,
2954 [SVM_EXIT_NMI] = nmi_interception,
2955 [SVM_EXIT_SMI] = nop_on_interception,
2956 [SVM_EXIT_INIT] = nop_on_interception,
2957 [SVM_EXIT_VINTR] = interrupt_window_interception,
2958 [SVM_EXIT_CPUID] = cpuid_interception,
2959 [SVM_EXIT_IRET] = iret_interception,
2960 [SVM_EXIT_INVD] = emulate_on_interception,
2961 [SVM_EXIT_PAUSE] = pause_interception,
2962 [SVM_EXIT_HLT] = halt_interception,
2963 [SVM_EXIT_INVLPG] = invlpg_interception,
2964 [SVM_EXIT_INVLPGA] = invlpga_interception,
2965 [SVM_EXIT_IOIO] = io_interception,
2966 [SVM_EXIT_MSR] = msr_interception,
2967 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2968 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2969 [SVM_EXIT_VMRUN] = vmrun_interception,
2970 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2971 [SVM_EXIT_VMLOAD] = vmload_interception,
2972 [SVM_EXIT_VMSAVE] = vmsave_interception,
2973 [SVM_EXIT_STGI] = stgi_interception,
2974 [SVM_EXIT_CLGI] = clgi_interception,
2975 [SVM_EXIT_SKINIT] = skinit_interception,
2976 [SVM_EXIT_WBINVD] = emulate_on_interception,
2977 [SVM_EXIT_MONITOR] = invalid_op_interception,
2978 [SVM_EXIT_MWAIT] = invalid_op_interception,
2979 [SVM_EXIT_NPF] = pf_interception,
2980 };
2981
2982 void dump_vmcb(struct kvm_vcpu *vcpu)
2983 {
2984 struct vcpu_svm *svm = to_svm(vcpu);
2985 struct vmcb_control_area *control = &svm->vmcb->control;
2986 struct vmcb_save_area *save = &svm->vmcb->save;
2987
2988 pr_err("VMCB Control Area:\n");
2989 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2990 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2991 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2992 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2993 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2994 pr_err("intercepts: %016llx\n", control->intercept);
2995 pr_err("pause filter count: %d\n", control->pause_filter_count);
2996 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2997 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2998 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2999 pr_err("asid: %d\n", control->asid);
3000 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3001 pr_err("int_ctl: %08x\n", control->int_ctl);
3002 pr_err("int_vector: %08x\n", control->int_vector);
3003 pr_err("int_state: %08x\n", control->int_state);
3004 pr_err("exit_code: %08x\n", control->exit_code);
3005 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3006 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3007 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3008 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3009 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3010 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3011 pr_err("event_inj: %08x\n", control->event_inj);
3012 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3013 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3014 pr_err("next_rip: %016llx\n", control->next_rip);
3015 pr_err("VMCB State Save Area:\n");
3016 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3017 save->es.selector, save->es.attrib,
3018 save->es.limit, save->es.base);
3019 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3020 save->cs.selector, save->cs.attrib,
3021 save->cs.limit, save->cs.base);
3022 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3023 save->ss.selector, save->ss.attrib,
3024 save->ss.limit, save->ss.base);
3025 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3026 save->ds.selector, save->ds.attrib,
3027 save->ds.limit, save->ds.base);
3028 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3029 save->fs.selector, save->fs.attrib,
3030 save->fs.limit, save->fs.base);
3031 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3032 save->gs.selector, save->gs.attrib,
3033 save->gs.limit, save->gs.base);
3034 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3035 save->gdtr.selector, save->gdtr.attrib,
3036 save->gdtr.limit, save->gdtr.base);
3037 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3038 save->ldtr.selector, save->ldtr.attrib,
3039 save->ldtr.limit, save->ldtr.base);
3040 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3041 save->idtr.selector, save->idtr.attrib,
3042 save->idtr.limit, save->idtr.base);
3043 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3044 save->tr.selector, save->tr.attrib,
3045 save->tr.limit, save->tr.base);
3046 pr_err("cpl: %d efer: %016llx\n",
3047 save->cpl, save->efer);
3048 pr_err("cr0: %016llx cr2: %016llx\n",
3049 save->cr0, save->cr2);
3050 pr_err("cr3: %016llx cr4: %016llx\n",
3051 save->cr3, save->cr4);
3052 pr_err("dr6: %016llx dr7: %016llx\n",
3053 save->dr6, save->dr7);
3054 pr_err("rip: %016llx rflags: %016llx\n",
3055 save->rip, save->rflags);
3056 pr_err("rsp: %016llx rax: %016llx\n",
3057 save->rsp, save->rax);
3058 pr_err("star: %016llx lstar: %016llx\n",
3059 save->star, save->lstar);
3060 pr_err("cstar: %016llx sfmask: %016llx\n",
3061 save->cstar, save->sfmask);
3062 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3063 save->kernel_gs_base, save->sysenter_cs);
3064 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3065 save->sysenter_esp, save->sysenter_eip);
3066 pr_err("gpat: %016llx dbgctl: %016llx\n",
3067 save->g_pat, save->dbgctl);
3068 pr_err("br_from: %016llx br_to: %016llx\n",
3069 save->br_from, save->br_to);
3070 pr_err("excp_from: %016llx excp_to: %016llx\n",
3071 save->last_excp_from, save->last_excp_to);
3072
3073 }
3074
3075 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3076 {
3077 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3078
3079 *info1 = control->exit_info_1;
3080 *info2 = control->exit_info_2;
3081 }
3082
3083 static int handle_exit(struct kvm_vcpu *vcpu)
3084 {
3085 struct vcpu_svm *svm = to_svm(vcpu);
3086 struct kvm_run *kvm_run = vcpu->run;
3087 u32 exit_code = svm->vmcb->control.exit_code;
3088
3089 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3090
3091 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3092 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3093 if (npt_enabled)
3094 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3095
3096 if (unlikely(svm->nested.exit_required)) {
3097 nested_svm_vmexit(svm);
3098 svm->nested.exit_required = false;
3099
3100 return 1;
3101 }
3102
3103 if (is_guest_mode(vcpu)) {
3104 int vmexit;
3105
3106 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3107 svm->vmcb->control.exit_info_1,
3108 svm->vmcb->control.exit_info_2,
3109 svm->vmcb->control.exit_int_info,
3110 svm->vmcb->control.exit_int_info_err);
3111
3112 vmexit = nested_svm_exit_special(svm);
3113
3114 if (vmexit == NESTED_EXIT_CONTINUE)
3115 vmexit = nested_svm_exit_handled(svm);
3116
3117 if (vmexit == NESTED_EXIT_DONE)
3118 return 1;
3119 }
3120
3121 svm_complete_interrupts(svm);
3122
3123 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3124 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3125 kvm_run->fail_entry.hardware_entry_failure_reason
3126 = svm->vmcb->control.exit_code;
3127 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3128 dump_vmcb(vcpu);
3129 return 0;
3130 }
3131
3132 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3133 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3134 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3135 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3136 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3137 "exit_code 0x%x\n",
3138 __func__, svm->vmcb->control.exit_int_info,
3139 exit_code);
3140
3141 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3142 || !svm_exit_handlers[exit_code]) {
3143 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3144 kvm_run->hw.hardware_exit_reason = exit_code;
3145 return 0;
3146 }
3147
3148 return svm_exit_handlers[exit_code](svm);
3149 }
3150
3151 static void reload_tss(struct kvm_vcpu *vcpu)
3152 {
3153 int cpu = raw_smp_processor_id();
3154
3155 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3156 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3157 load_TR_desc();
3158 }
3159
3160 static void pre_svm_run(struct vcpu_svm *svm)
3161 {
3162 int cpu = raw_smp_processor_id();
3163
3164 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3165
3166 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3167 /* FIXME: handle wraparound of asid_generation */
3168 if (svm->asid_generation != sd->asid_generation)
3169 new_asid(svm, sd);
3170 }
3171
3172 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3173 {
3174 struct vcpu_svm *svm = to_svm(vcpu);
3175
3176 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3177 vcpu->arch.hflags |= HF_NMI_MASK;
3178 set_intercept(svm, INTERCEPT_IRET);
3179 ++vcpu->stat.nmi_injections;
3180 }
3181
3182 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3183 {
3184 struct vmcb_control_area *control;
3185
3186 control = &svm->vmcb->control;
3187 control->int_vector = irq;
3188 control->int_ctl &= ~V_INTR_PRIO_MASK;
3189 control->int_ctl |= V_IRQ_MASK |
3190 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3191 mark_dirty(svm->vmcb, VMCB_INTR);
3192 }
3193
3194 static void svm_set_irq(struct kvm_vcpu *vcpu)
3195 {
3196 struct vcpu_svm *svm = to_svm(vcpu);
3197
3198 BUG_ON(!(gif_set(svm)));
3199
3200 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3201 ++vcpu->stat.irq_injections;
3202
3203 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3204 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3205 }
3206
3207 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3208 {
3209 struct vcpu_svm *svm = to_svm(vcpu);
3210
3211 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3212 return;
3213
3214 if (irr == -1)
3215 return;
3216
3217 if (tpr >= irr)
3218 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3219 }
3220
3221 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3222 {
3223 struct vcpu_svm *svm = to_svm(vcpu);
3224 struct vmcb *vmcb = svm->vmcb;
3225 int ret;
3226 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3227 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3228 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3229
3230 return ret;
3231 }
3232
3233 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3234 {
3235 struct vcpu_svm *svm = to_svm(vcpu);
3236
3237 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3238 }
3239
3240 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3241 {
3242 struct vcpu_svm *svm = to_svm(vcpu);
3243
3244 if (masked) {
3245 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3246 set_intercept(svm, INTERCEPT_IRET);
3247 } else {
3248 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3249 clr_intercept(svm, INTERCEPT_IRET);
3250 }
3251 }
3252
3253 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3254 {
3255 struct vcpu_svm *svm = to_svm(vcpu);
3256 struct vmcb *vmcb = svm->vmcb;
3257 int ret;
3258
3259 if (!gif_set(svm) ||
3260 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3261 return 0;
3262
3263 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3264
3265 if (is_guest_mode(vcpu))
3266 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3267
3268 return ret;
3269 }
3270
3271 static void enable_irq_window(struct kvm_vcpu *vcpu)
3272 {
3273 struct vcpu_svm *svm = to_svm(vcpu);
3274
3275 /*
3276 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3277 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3278 * get that intercept, this function will be called again though and
3279 * we'll get the vintr intercept.
3280 */
3281 if (gif_set(svm) && nested_svm_intr(svm)) {
3282 svm_set_vintr(svm);
3283 svm_inject_irq(svm, 0x0);
3284 }
3285 }
3286
3287 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3288 {
3289 struct vcpu_svm *svm = to_svm(vcpu);
3290
3291 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3292 == HF_NMI_MASK)
3293 return; /* IRET will cause a vm exit */
3294
3295 /*
3296 * Something prevents NMI from been injected. Single step over possible
3297 * problem (IRET or exception injection or interrupt shadow)
3298 */
3299 svm->nmi_singlestep = true;
3300 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3301 update_db_intercept(vcpu);
3302 }
3303
3304 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3305 {
3306 return 0;
3307 }
3308
3309 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3310 {
3311 force_new_asid(vcpu);
3312 }
3313
3314 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3315 {
3316 }
3317
3318 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3319 {
3320 struct vcpu_svm *svm = to_svm(vcpu);
3321
3322 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3323 return;
3324
3325 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3326 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3327 kvm_set_cr8(vcpu, cr8);
3328 }
3329 }
3330
3331 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3332 {
3333 struct vcpu_svm *svm = to_svm(vcpu);
3334 u64 cr8;
3335
3336 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3337 return;
3338
3339 cr8 = kvm_get_cr8(vcpu);
3340 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3341 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3342 }
3343
3344 static void svm_complete_interrupts(struct vcpu_svm *svm)
3345 {
3346 u8 vector;
3347 int type;
3348 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3349 unsigned int3_injected = svm->int3_injected;
3350
3351 svm->int3_injected = 0;
3352
3353 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3354 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3355 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3356 }
3357
3358 svm->vcpu.arch.nmi_injected = false;
3359 kvm_clear_exception_queue(&svm->vcpu);
3360 kvm_clear_interrupt_queue(&svm->vcpu);
3361
3362 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3363 return;
3364
3365 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3366
3367 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3368 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3369
3370 switch (type) {
3371 case SVM_EXITINTINFO_TYPE_NMI:
3372 svm->vcpu.arch.nmi_injected = true;
3373 break;
3374 case SVM_EXITINTINFO_TYPE_EXEPT:
3375 /*
3376 * In case of software exceptions, do not reinject the vector,
3377 * but re-execute the instruction instead. Rewind RIP first
3378 * if we emulated INT3 before.
3379 */
3380 if (kvm_exception_is_soft(vector)) {
3381 if (vector == BP_VECTOR && int3_injected &&
3382 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3383 kvm_rip_write(&svm->vcpu,
3384 kvm_rip_read(&svm->vcpu) -
3385 int3_injected);
3386 break;
3387 }
3388 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3389 u32 err = svm->vmcb->control.exit_int_info_err;
3390 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3391
3392 } else
3393 kvm_requeue_exception(&svm->vcpu, vector);
3394 break;
3395 case SVM_EXITINTINFO_TYPE_INTR:
3396 kvm_queue_interrupt(&svm->vcpu, vector, false);
3397 break;
3398 default:
3399 break;
3400 }
3401 }
3402
3403 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3404 {
3405 struct vcpu_svm *svm = to_svm(vcpu);
3406 struct vmcb_control_area *control = &svm->vmcb->control;
3407
3408 control->exit_int_info = control->event_inj;
3409 control->exit_int_info_err = control->event_inj_err;
3410 control->event_inj = 0;
3411 svm_complete_interrupts(svm);
3412 }
3413
3414 #ifdef CONFIG_X86_64
3415 #define R "r"
3416 #else
3417 #define R "e"
3418 #endif
3419
3420 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3421 {
3422 struct vcpu_svm *svm = to_svm(vcpu);
3423
3424 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3425 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3426 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3427
3428 /*
3429 * A vmexit emulation is required before the vcpu can be executed
3430 * again.
3431 */
3432 if (unlikely(svm->nested.exit_required))
3433 return;
3434
3435 pre_svm_run(svm);
3436
3437 sync_lapic_to_cr8(vcpu);
3438
3439 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3440
3441 clgi();
3442
3443 local_irq_enable();
3444
3445 asm volatile (
3446 "push %%"R"bp; \n\t"
3447 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3448 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3449 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3450 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3451 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3452 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3453 #ifdef CONFIG_X86_64
3454 "mov %c[r8](%[svm]), %%r8 \n\t"
3455 "mov %c[r9](%[svm]), %%r9 \n\t"
3456 "mov %c[r10](%[svm]), %%r10 \n\t"
3457 "mov %c[r11](%[svm]), %%r11 \n\t"
3458 "mov %c[r12](%[svm]), %%r12 \n\t"
3459 "mov %c[r13](%[svm]), %%r13 \n\t"
3460 "mov %c[r14](%[svm]), %%r14 \n\t"
3461 "mov %c[r15](%[svm]), %%r15 \n\t"
3462 #endif
3463
3464 /* Enter guest mode */
3465 "push %%"R"ax \n\t"
3466 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3467 __ex(SVM_VMLOAD) "\n\t"
3468 __ex(SVM_VMRUN) "\n\t"
3469 __ex(SVM_VMSAVE) "\n\t"
3470 "pop %%"R"ax \n\t"
3471
3472 /* Save guest registers, load host registers */
3473 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3474 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3475 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3476 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3477 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3478 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3479 #ifdef CONFIG_X86_64
3480 "mov %%r8, %c[r8](%[svm]) \n\t"
3481 "mov %%r9, %c[r9](%[svm]) \n\t"
3482 "mov %%r10, %c[r10](%[svm]) \n\t"
3483 "mov %%r11, %c[r11](%[svm]) \n\t"
3484 "mov %%r12, %c[r12](%[svm]) \n\t"
3485 "mov %%r13, %c[r13](%[svm]) \n\t"
3486 "mov %%r14, %c[r14](%[svm]) \n\t"
3487 "mov %%r15, %c[r15](%[svm]) \n\t"
3488 #endif
3489 "pop %%"R"bp"
3490 :
3491 : [svm]"a"(svm),
3492 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3493 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3494 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3495 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3496 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3497 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3498 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3499 #ifdef CONFIG_X86_64
3500 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3501 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3502 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3503 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3504 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3505 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3506 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3507 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3508 #endif
3509 : "cc", "memory"
3510 , R"bx", R"cx", R"dx", R"si", R"di"
3511 #ifdef CONFIG_X86_64
3512 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3513 #endif
3514 );
3515
3516 #ifdef CONFIG_X86_64
3517 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3518 #else
3519 loadsegment(fs, svm->host.fs);
3520 #endif
3521
3522 reload_tss(vcpu);
3523
3524 local_irq_disable();
3525
3526 stgi();
3527
3528 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3529 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3530 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3531 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3532
3533 sync_cr8_to_lapic(vcpu);
3534
3535 svm->next_rip = 0;
3536
3537 /* if exit due to PF check for async PF */
3538 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3539 svm->apf_reason = kvm_read_and_reset_pf_reason();
3540
3541 if (npt_enabled) {
3542 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3543 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3544 }
3545
3546 /*
3547 * We need to handle MC intercepts here before the vcpu has a chance to
3548 * change the physical cpu
3549 */
3550 if (unlikely(svm->vmcb->control.exit_code ==
3551 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3552 svm_handle_mce(svm);
3553
3554 mark_all_clean(svm->vmcb);
3555 }
3556
3557 #undef R
3558
3559 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3560 {
3561 struct vcpu_svm *svm = to_svm(vcpu);
3562
3563 svm->vmcb->save.cr3 = root;
3564 mark_dirty(svm->vmcb, VMCB_CR);
3565 force_new_asid(vcpu);
3566 }
3567
3568 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3569 {
3570 struct vcpu_svm *svm = to_svm(vcpu);
3571
3572 svm->vmcb->control.nested_cr3 = root;
3573 mark_dirty(svm->vmcb, VMCB_NPT);
3574
3575 /* Also sync guest cr3 here in case we live migrate */
3576 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3577 mark_dirty(svm->vmcb, VMCB_CR);
3578
3579 force_new_asid(vcpu);
3580 }
3581
3582 static int is_disabled(void)
3583 {
3584 u64 vm_cr;
3585
3586 rdmsrl(MSR_VM_CR, vm_cr);
3587 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3588 return 1;
3589
3590 return 0;
3591 }
3592
3593 static void
3594 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3595 {
3596 /*
3597 * Patch in the VMMCALL instruction:
3598 */
3599 hypercall[0] = 0x0f;
3600 hypercall[1] = 0x01;
3601 hypercall[2] = 0xd9;
3602 }
3603
3604 static void svm_check_processor_compat(void *rtn)
3605 {
3606 *(int *)rtn = 0;
3607 }
3608
3609 static bool svm_cpu_has_accelerated_tpr(void)
3610 {
3611 return false;
3612 }
3613
3614 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3615 {
3616 return 0;
3617 }
3618
3619 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3620 {
3621 }
3622
3623 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3624 {
3625 switch (func) {
3626 case 0x00000001:
3627 /* Mask out xsave bit as long as it is not supported by SVM */
3628 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3629 break;
3630 case 0x80000001:
3631 if (nested)
3632 entry->ecx |= (1 << 2); /* Set SVM bit */
3633 break;
3634 case 0x8000000A:
3635 entry->eax = 1; /* SVM revision 1 */
3636 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3637 ASID emulation to nested SVM */
3638 entry->ecx = 0; /* Reserved */
3639 entry->edx = 0; /* Per default do not support any
3640 additional features */
3641
3642 /* Support next_rip if host supports it */
3643 if (boot_cpu_has(X86_FEATURE_NRIPS))
3644 entry->edx |= SVM_FEATURE_NRIP;
3645
3646 /* Support NPT for the guest if enabled */
3647 if (npt_enabled)
3648 entry->edx |= SVM_FEATURE_NPT;
3649
3650 break;
3651 }
3652 }
3653
3654 static const struct trace_print_flags svm_exit_reasons_str[] = {
3655 { SVM_EXIT_READ_CR0, "read_cr0" },
3656 { SVM_EXIT_READ_CR3, "read_cr3" },
3657 { SVM_EXIT_READ_CR4, "read_cr4" },
3658 { SVM_EXIT_READ_CR8, "read_cr8" },
3659 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3660 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3661 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3662 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3663 { SVM_EXIT_READ_DR0, "read_dr0" },
3664 { SVM_EXIT_READ_DR1, "read_dr1" },
3665 { SVM_EXIT_READ_DR2, "read_dr2" },
3666 { SVM_EXIT_READ_DR3, "read_dr3" },
3667 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3668 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3669 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3670 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3671 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3672 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3673 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3674 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3675 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3676 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3677 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3678 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3679 { SVM_EXIT_INTR, "interrupt" },
3680 { SVM_EXIT_NMI, "nmi" },
3681 { SVM_EXIT_SMI, "smi" },
3682 { SVM_EXIT_INIT, "init" },
3683 { SVM_EXIT_VINTR, "vintr" },
3684 { SVM_EXIT_CPUID, "cpuid" },
3685 { SVM_EXIT_INVD, "invd" },
3686 { SVM_EXIT_HLT, "hlt" },
3687 { SVM_EXIT_INVLPG, "invlpg" },
3688 { SVM_EXIT_INVLPGA, "invlpga" },
3689 { SVM_EXIT_IOIO, "io" },
3690 { SVM_EXIT_MSR, "msr" },
3691 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3692 { SVM_EXIT_SHUTDOWN, "shutdown" },
3693 { SVM_EXIT_VMRUN, "vmrun" },
3694 { SVM_EXIT_VMMCALL, "hypercall" },
3695 { SVM_EXIT_VMLOAD, "vmload" },
3696 { SVM_EXIT_VMSAVE, "vmsave" },
3697 { SVM_EXIT_STGI, "stgi" },
3698 { SVM_EXIT_CLGI, "clgi" },
3699 { SVM_EXIT_SKINIT, "skinit" },
3700 { SVM_EXIT_WBINVD, "wbinvd" },
3701 { SVM_EXIT_MONITOR, "monitor" },
3702 { SVM_EXIT_MWAIT, "mwait" },
3703 { SVM_EXIT_NPF, "npf" },
3704 { -1, NULL }
3705 };
3706
3707 static int svm_get_lpage_level(void)
3708 {
3709 return PT_PDPE_LEVEL;
3710 }
3711
3712 static bool svm_rdtscp_supported(void)
3713 {
3714 return false;
3715 }
3716
3717 static bool svm_has_wbinvd_exit(void)
3718 {
3719 return true;
3720 }
3721
3722 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3723 {
3724 struct vcpu_svm *svm = to_svm(vcpu);
3725
3726 set_exception_intercept(svm, NM_VECTOR);
3727 update_cr0_intercept(svm);
3728 }
3729
3730 static struct kvm_x86_ops svm_x86_ops = {
3731 .cpu_has_kvm_support = has_svm,
3732 .disabled_by_bios = is_disabled,
3733 .hardware_setup = svm_hardware_setup,
3734 .hardware_unsetup = svm_hardware_unsetup,
3735 .check_processor_compatibility = svm_check_processor_compat,
3736 .hardware_enable = svm_hardware_enable,
3737 .hardware_disable = svm_hardware_disable,
3738 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3739
3740 .vcpu_create = svm_create_vcpu,
3741 .vcpu_free = svm_free_vcpu,
3742 .vcpu_reset = svm_vcpu_reset,
3743
3744 .prepare_guest_switch = svm_prepare_guest_switch,
3745 .vcpu_load = svm_vcpu_load,
3746 .vcpu_put = svm_vcpu_put,
3747
3748 .set_guest_debug = svm_guest_debug,
3749 .get_msr = svm_get_msr,
3750 .set_msr = svm_set_msr,
3751 .get_segment_base = svm_get_segment_base,
3752 .get_segment = svm_get_segment,
3753 .set_segment = svm_set_segment,
3754 .get_cpl = svm_get_cpl,
3755 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3756 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3757 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3758 .set_cr0 = svm_set_cr0,
3759 .set_cr3 = svm_set_cr3,
3760 .set_cr4 = svm_set_cr4,
3761 .set_efer = svm_set_efer,
3762 .get_idt = svm_get_idt,
3763 .set_idt = svm_set_idt,
3764 .get_gdt = svm_get_gdt,
3765 .set_gdt = svm_set_gdt,
3766 .set_dr7 = svm_set_dr7,
3767 .cache_reg = svm_cache_reg,
3768 .get_rflags = svm_get_rflags,
3769 .set_rflags = svm_set_rflags,
3770 .fpu_activate = svm_fpu_activate,
3771 .fpu_deactivate = svm_fpu_deactivate,
3772
3773 .tlb_flush = svm_flush_tlb,
3774
3775 .run = svm_vcpu_run,
3776 .handle_exit = handle_exit,
3777 .skip_emulated_instruction = skip_emulated_instruction,
3778 .set_interrupt_shadow = svm_set_interrupt_shadow,
3779 .get_interrupt_shadow = svm_get_interrupt_shadow,
3780 .patch_hypercall = svm_patch_hypercall,
3781 .set_irq = svm_set_irq,
3782 .set_nmi = svm_inject_nmi,
3783 .queue_exception = svm_queue_exception,
3784 .cancel_injection = svm_cancel_injection,
3785 .interrupt_allowed = svm_interrupt_allowed,
3786 .nmi_allowed = svm_nmi_allowed,
3787 .get_nmi_mask = svm_get_nmi_mask,
3788 .set_nmi_mask = svm_set_nmi_mask,
3789 .enable_nmi_window = enable_nmi_window,
3790 .enable_irq_window = enable_irq_window,
3791 .update_cr8_intercept = update_cr8_intercept,
3792
3793 .set_tss_addr = svm_set_tss_addr,
3794 .get_tdp_level = get_npt_level,
3795 .get_mt_mask = svm_get_mt_mask,
3796
3797 .get_exit_info = svm_get_exit_info,
3798 .exit_reasons_str = svm_exit_reasons_str,
3799
3800 .get_lpage_level = svm_get_lpage_level,
3801
3802 .cpuid_update = svm_cpuid_update,
3803
3804 .rdtscp_supported = svm_rdtscp_supported,
3805
3806 .set_supported_cpuid = svm_set_supported_cpuid,
3807
3808 .has_wbinvd_exit = svm_has_wbinvd_exit,
3809
3810 .write_tsc_offset = svm_write_tsc_offset,
3811 .adjust_tsc_offset = svm_adjust_tsc_offset,
3812
3813 .set_tdp_cr3 = set_tdp_cr3,
3814 };
3815
3816 static int __init svm_init(void)
3817 {
3818 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3819 __alignof__(struct vcpu_svm), THIS_MODULE);
3820 }
3821
3822 static void __exit svm_exit(void)
3823 {
3824 kvm_exit();
3825 }
3826
3827 module_init(svm_init)
3828 module_exit(svm_exit)
Linux kernel - Deliverables
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