2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
115 #define KVM_VM_CR0_ALWAYS_ON \
116 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
117 #define KVM_CR4_GUEST_OWNED_BITS \
118 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
119 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
129 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
130 * ple_gap: upper bound on the amount of time between two successive
131 * executions of PAUSE in a loop. Also indicate if ple enabled.
132 * According to test, this time is usually smaller than 128 cycles.
133 * ple_window: upper bound on the amount of time a guest is allowed to execute
134 * in a PAUSE loop. Tests indicate that most spinlocks are held for
135 * less than 2^12 cycles
136 * Time is measured based on a counter that runs at the same rate as the TSC,
137 * refer SDM volume 3b section 21.6.13 & 22.1.3.
139 #define KVM_VMX_DEFAULT_PLE_GAP 128
140 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
144 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
146 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
147 module_param(ple_gap
, int, S_IRUGO
);
149 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
150 module_param(ple_window
, int, S_IRUGO
);
152 /* Default doubles per-vcpu window every exit. */
153 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
154 module_param(ple_window_grow
, int, S_IRUGO
);
156 /* Default resets per-vcpu window every exit to ple_window. */
157 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
158 module_param(ple_window_shrink
, int, S_IRUGO
);
160 /* Default is to compute the maximum so we can never overflow. */
161 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
162 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
163 module_param(ple_window_max
, int, S_IRUGO
);
165 extern const ulong vmx_return
;
167 #define NR_AUTOLOAD_MSRS 8
168 #define VMCS02_POOL_SIZE 1
177 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
178 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
179 * loaded on this CPU (so we can clear them if the CPU goes down).
185 struct list_head loaded_vmcss_on_cpu_link
;
188 struct shared_msr_entry
{
195 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
196 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
197 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
198 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
199 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
200 * More than one of these structures may exist, if L1 runs multiple L2 guests.
201 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
202 * underlying hardware which will be used to run L2.
203 * This structure is packed to ensure that its layout is identical across
204 * machines (necessary for live migration).
205 * If there are changes in this struct, VMCS12_REVISION must be changed.
207 typedef u64 natural_width
;
208 struct __packed vmcs12
{
209 /* According to the Intel spec, a VMCS region must start with the
210 * following two fields. Then follow implementation-specific data.
215 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
216 u32 padding
[7]; /* room for future expansion */
221 u64 vm_exit_msr_store_addr
;
222 u64 vm_exit_msr_load_addr
;
223 u64 vm_entry_msr_load_addr
;
225 u64 virtual_apic_page_addr
;
226 u64 apic_access_addr
;
227 u64 posted_intr_desc_addr
;
229 u64 eoi_exit_bitmap0
;
230 u64 eoi_exit_bitmap1
;
231 u64 eoi_exit_bitmap2
;
232 u64 eoi_exit_bitmap3
;
234 u64 guest_physical_address
;
235 u64 vmcs_link_pointer
;
236 u64 guest_ia32_debugctl
;
239 u64 guest_ia32_perf_global_ctrl
;
247 u64 host_ia32_perf_global_ctrl
;
248 u64 padding64
[8]; /* room for future expansion */
250 * To allow migration of L1 (complete with its L2 guests) between
251 * machines of different natural widths (32 or 64 bit), we cannot have
252 * unsigned long fields with no explict size. We use u64 (aliased
253 * natural_width) instead. Luckily, x86 is little-endian.
255 natural_width cr0_guest_host_mask
;
256 natural_width cr4_guest_host_mask
;
257 natural_width cr0_read_shadow
;
258 natural_width cr4_read_shadow
;
259 natural_width cr3_target_value0
;
260 natural_width cr3_target_value1
;
261 natural_width cr3_target_value2
;
262 natural_width cr3_target_value3
;
263 natural_width exit_qualification
;
264 natural_width guest_linear_address
;
265 natural_width guest_cr0
;
266 natural_width guest_cr3
;
267 natural_width guest_cr4
;
268 natural_width guest_es_base
;
269 natural_width guest_cs_base
;
270 natural_width guest_ss_base
;
271 natural_width guest_ds_base
;
272 natural_width guest_fs_base
;
273 natural_width guest_gs_base
;
274 natural_width guest_ldtr_base
;
275 natural_width guest_tr_base
;
276 natural_width guest_gdtr_base
;
277 natural_width guest_idtr_base
;
278 natural_width guest_dr7
;
279 natural_width guest_rsp
;
280 natural_width guest_rip
;
281 natural_width guest_rflags
;
282 natural_width guest_pending_dbg_exceptions
;
283 natural_width guest_sysenter_esp
;
284 natural_width guest_sysenter_eip
;
285 natural_width host_cr0
;
286 natural_width host_cr3
;
287 natural_width host_cr4
;
288 natural_width host_fs_base
;
289 natural_width host_gs_base
;
290 natural_width host_tr_base
;
291 natural_width host_gdtr_base
;
292 natural_width host_idtr_base
;
293 natural_width host_ia32_sysenter_esp
;
294 natural_width host_ia32_sysenter_eip
;
295 natural_width host_rsp
;
296 natural_width host_rip
;
297 natural_width paddingl
[8]; /* room for future expansion */
298 u32 pin_based_vm_exec_control
;
299 u32 cpu_based_vm_exec_control
;
300 u32 exception_bitmap
;
301 u32 page_fault_error_code_mask
;
302 u32 page_fault_error_code_match
;
303 u32 cr3_target_count
;
304 u32 vm_exit_controls
;
305 u32 vm_exit_msr_store_count
;
306 u32 vm_exit_msr_load_count
;
307 u32 vm_entry_controls
;
308 u32 vm_entry_msr_load_count
;
309 u32 vm_entry_intr_info_field
;
310 u32 vm_entry_exception_error_code
;
311 u32 vm_entry_instruction_len
;
313 u32 secondary_vm_exec_control
;
314 u32 vm_instruction_error
;
316 u32 vm_exit_intr_info
;
317 u32 vm_exit_intr_error_code
;
318 u32 idt_vectoring_info_field
;
319 u32 idt_vectoring_error_code
;
320 u32 vm_exit_instruction_len
;
321 u32 vmx_instruction_info
;
328 u32 guest_ldtr_limit
;
330 u32 guest_gdtr_limit
;
331 u32 guest_idtr_limit
;
332 u32 guest_es_ar_bytes
;
333 u32 guest_cs_ar_bytes
;
334 u32 guest_ss_ar_bytes
;
335 u32 guest_ds_ar_bytes
;
336 u32 guest_fs_ar_bytes
;
337 u32 guest_gs_ar_bytes
;
338 u32 guest_ldtr_ar_bytes
;
339 u32 guest_tr_ar_bytes
;
340 u32 guest_interruptibility_info
;
341 u32 guest_activity_state
;
342 u32 guest_sysenter_cs
;
343 u32 host_ia32_sysenter_cs
;
344 u32 vmx_preemption_timer_value
;
345 u32 padding32
[7]; /* room for future expansion */
346 u16 virtual_processor_id
;
348 u16 guest_es_selector
;
349 u16 guest_cs_selector
;
350 u16 guest_ss_selector
;
351 u16 guest_ds_selector
;
352 u16 guest_fs_selector
;
353 u16 guest_gs_selector
;
354 u16 guest_ldtr_selector
;
355 u16 guest_tr_selector
;
356 u16 guest_intr_status
;
357 u16 host_es_selector
;
358 u16 host_cs_selector
;
359 u16 host_ss_selector
;
360 u16 host_ds_selector
;
361 u16 host_fs_selector
;
362 u16 host_gs_selector
;
363 u16 host_tr_selector
;
367 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
368 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
369 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
371 #define VMCS12_REVISION 0x11e57ed0
374 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
375 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
376 * current implementation, 4K are reserved to avoid future complications.
378 #define VMCS12_SIZE 0x1000
380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
382 struct list_head list
;
384 struct loaded_vmcs vmcs02
;
388 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
389 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
392 /* Has the level1 guest done vmxon? */
396 /* The guest-physical address of the current VMCS L1 keeps for L2 */
398 /* The host-usable pointer to the above */
399 struct page
*current_vmcs12_page
;
400 struct vmcs12
*current_vmcs12
;
401 struct vmcs
*current_shadow_vmcs
;
403 * Indicates if the shadow vmcs must be updated with the
404 * data hold by vmcs12
406 bool sync_shadow_vmcs
;
408 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
409 struct list_head vmcs02_pool
;
411 u64 vmcs01_tsc_offset
;
412 /* L2 must run next, and mustn't decide to exit to L1. */
413 bool nested_run_pending
;
415 * Guest pages referred to in vmcs02 with host-physical pointers, so
416 * we must keep them pinned while L2 runs.
418 struct page
*apic_access_page
;
419 struct page
*virtual_apic_page
;
420 struct page
*pi_desc_page
;
421 struct pi_desc
*pi_desc
;
424 u64 msr_ia32_feature_control
;
426 struct hrtimer preemption_timer
;
427 bool preemption_timer_expired
;
429 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
435 u32 nested_vmx_procbased_ctls_low
;
436 u32 nested_vmx_procbased_ctls_high
;
437 u32 nested_vmx_true_procbased_ctls_low
;
438 u32 nested_vmx_secondary_ctls_low
;
439 u32 nested_vmx_secondary_ctls_high
;
440 u32 nested_vmx_pinbased_ctls_low
;
441 u32 nested_vmx_pinbased_ctls_high
;
442 u32 nested_vmx_exit_ctls_low
;
443 u32 nested_vmx_exit_ctls_high
;
444 u32 nested_vmx_true_exit_ctls_low
;
445 u32 nested_vmx_entry_ctls_low
;
446 u32 nested_vmx_entry_ctls_high
;
447 u32 nested_vmx_true_entry_ctls_low
;
448 u32 nested_vmx_misc_low
;
449 u32 nested_vmx_misc_high
;
450 u32 nested_vmx_ept_caps
;
451 u32 nested_vmx_vpid_caps
;
454 #define POSTED_INTR_ON 0
455 #define POSTED_INTR_SN 1
457 /* Posted-Interrupt Descriptor */
459 u32 pir
[8]; /* Posted interrupt requested */
462 /* bit 256 - Outstanding Notification */
464 /* bit 257 - Suppress Notification */
466 /* bit 271:258 - Reserved */
468 /* bit 279:272 - Notification Vector */
470 /* bit 287:280 - Reserved */
472 /* bit 319:288 - Notification Destination */
480 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
482 return test_and_set_bit(POSTED_INTR_ON
,
483 (unsigned long *)&pi_desc
->control
);
486 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
488 return test_and_clear_bit(POSTED_INTR_ON
,
489 (unsigned long *)&pi_desc
->control
);
492 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
494 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
497 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
499 return clear_bit(POSTED_INTR_SN
,
500 (unsigned long *)&pi_desc
->control
);
503 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
505 return set_bit(POSTED_INTR_SN
,
506 (unsigned long *)&pi_desc
->control
);
509 static inline int pi_test_on(struct pi_desc
*pi_desc
)
511 return test_bit(POSTED_INTR_ON
,
512 (unsigned long *)&pi_desc
->control
);
515 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
517 return test_bit(POSTED_INTR_SN
,
518 (unsigned long *)&pi_desc
->control
);
522 struct kvm_vcpu vcpu
;
523 unsigned long host_rsp
;
525 bool nmi_known_unmasked
;
527 u32 idt_vectoring_info
;
529 struct shared_msr_entry
*guest_msrs
;
532 unsigned long host_idt_base
;
534 u64 msr_host_kernel_gs_base
;
535 u64 msr_guest_kernel_gs_base
;
537 u32 vm_entry_controls_shadow
;
538 u32 vm_exit_controls_shadow
;
540 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541 * non-nested (L1) guest, it always points to vmcs01. For a nested
542 * guest (L2), it points to a different VMCS.
544 struct loaded_vmcs vmcs01
;
545 struct loaded_vmcs
*loaded_vmcs
;
546 bool __launched
; /* temporary, used in vmx_vcpu_run */
547 struct msr_autoload
{
549 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
550 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
554 u16 fs_sel
, gs_sel
, ldt_sel
;
558 int gs_ldt_reload_needed
;
559 int fs_reload_needed
;
560 u64 msr_host_bndcfgs
;
561 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
566 struct kvm_segment segs
[8];
569 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
570 struct kvm_save_segment
{
578 bool emulation_required
;
580 /* Support for vnmi-less CPUs */
581 int soft_vnmi_blocked
;
583 s64 vnmi_blocked_time
;
586 /* Posted interrupt descriptor */
587 struct pi_desc pi_desc
;
589 /* Support for a guest hypervisor (nested VMX) */
590 struct nested_vmx nested
;
592 /* Dynamic PLE window. */
594 bool ple_window_dirty
;
596 /* Support for PML */
597 #define PML_ENTITY_NUM 512
600 u64 current_tsc_ratio
;
602 bool guest_pkru_valid
;
607 enum segment_cache_field
{
616 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
618 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
621 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
623 return &(to_vmx(vcpu
)->pi_desc
);
626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
627 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
628 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
629 [number##_HIGH] = VMCS12_OFFSET(name)+4
632 static unsigned long shadow_read_only_fields
[] = {
634 * We do NOT shadow fields that are modified when L0
635 * traps and emulates any vmx instruction (e.g. VMPTRLD,
636 * VMXON...) executed by L1.
637 * For example, VM_INSTRUCTION_ERROR is read
638 * by L1 if a vmx instruction fails (part of the error path).
639 * Note the code assumes this logic. If for some reason
640 * we start shadowing these fields then we need to
641 * force a shadow sync when L0 emulates vmx instructions
642 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
643 * by nested_vmx_failValid)
647 VM_EXIT_INSTRUCTION_LEN
,
648 IDT_VECTORING_INFO_FIELD
,
649 IDT_VECTORING_ERROR_CODE
,
650 VM_EXIT_INTR_ERROR_CODE
,
652 GUEST_LINEAR_ADDRESS
,
653 GUEST_PHYSICAL_ADDRESS
655 static int max_shadow_read_only_fields
=
656 ARRAY_SIZE(shadow_read_only_fields
);
658 static unsigned long shadow_read_write_fields
[] = {
665 GUEST_INTERRUPTIBILITY_INFO
,
678 CPU_BASED_VM_EXEC_CONTROL
,
679 VM_ENTRY_EXCEPTION_ERROR_CODE
,
680 VM_ENTRY_INTR_INFO_FIELD
,
681 VM_ENTRY_INSTRUCTION_LEN
,
682 VM_ENTRY_EXCEPTION_ERROR_CODE
,
688 static int max_shadow_read_write_fields
=
689 ARRAY_SIZE(shadow_read_write_fields
);
691 static const unsigned short vmcs_field_to_offset_table
[] = {
692 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
693 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
694 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
695 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
696 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
697 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
698 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
699 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
700 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
701 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
702 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
703 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
704 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
705 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
706 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
707 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
708 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
709 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
710 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
711 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
712 FIELD64(MSR_BITMAP
, msr_bitmap
),
713 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
714 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
715 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
716 FIELD64(TSC_OFFSET
, tsc_offset
),
717 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
718 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
719 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
720 FIELD64(EPT_POINTER
, ept_pointer
),
721 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
722 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
723 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
724 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
725 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
726 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
727 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
728 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
729 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
730 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
731 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
732 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
733 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
734 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
735 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
736 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
737 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
738 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
739 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
740 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
741 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
742 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
743 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
744 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
745 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
746 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
747 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
748 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
749 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
750 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
751 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
752 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
753 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
754 FIELD(TPR_THRESHOLD
, tpr_threshold
),
755 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
756 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
757 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
758 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
759 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
760 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
761 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
762 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
763 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
764 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
765 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
766 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
767 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
768 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
769 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
770 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
771 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
772 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
773 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
774 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
775 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
776 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
777 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
778 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
779 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
780 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
781 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
782 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
783 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
784 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
785 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
786 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
787 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
788 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
789 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
790 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
791 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
792 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
793 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
794 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
795 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
796 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
797 FIELD(GUEST_CR0
, guest_cr0
),
798 FIELD(GUEST_CR3
, guest_cr3
),
799 FIELD(GUEST_CR4
, guest_cr4
),
800 FIELD(GUEST_ES_BASE
, guest_es_base
),
801 FIELD(GUEST_CS_BASE
, guest_cs_base
),
802 FIELD(GUEST_SS_BASE
, guest_ss_base
),
803 FIELD(GUEST_DS_BASE
, guest_ds_base
),
804 FIELD(GUEST_FS_BASE
, guest_fs_base
),
805 FIELD(GUEST_GS_BASE
, guest_gs_base
),
806 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
807 FIELD(GUEST_TR_BASE
, guest_tr_base
),
808 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
809 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
810 FIELD(GUEST_DR7
, guest_dr7
),
811 FIELD(GUEST_RSP
, guest_rsp
),
812 FIELD(GUEST_RIP
, guest_rip
),
813 FIELD(GUEST_RFLAGS
, guest_rflags
),
814 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
815 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
816 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
817 FIELD(HOST_CR0
, host_cr0
),
818 FIELD(HOST_CR3
, host_cr3
),
819 FIELD(HOST_CR4
, host_cr4
),
820 FIELD(HOST_FS_BASE
, host_fs_base
),
821 FIELD(HOST_GS_BASE
, host_gs_base
),
822 FIELD(HOST_TR_BASE
, host_tr_base
),
823 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
824 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
825 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
826 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
827 FIELD(HOST_RSP
, host_rsp
),
828 FIELD(HOST_RIP
, host_rip
),
831 static inline short vmcs_field_to_offset(unsigned long field
)
833 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
835 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
836 vmcs_field_to_offset_table
[field
] == 0)
839 return vmcs_field_to_offset_table
[field
];
842 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
844 return to_vmx(vcpu
)->nested
.current_vmcs12
;
847 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
849 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
850 if (is_error_page(page
))
856 static void nested_release_page(struct page
*page
)
858 kvm_release_page_dirty(page
);
861 static void nested_release_page_clean(struct page
*page
)
863 kvm_release_page_clean(page
);
866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
867 static u64
construct_eptp(unsigned long root_hpa
);
868 static void kvm_cpu_vmxon(u64 addr
);
869 static void kvm_cpu_vmxoff(void);
870 static bool vmx_xsaves_supported(void);
871 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
872 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
873 struct kvm_segment
*var
, int seg
);
874 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
875 struct kvm_segment
*var
, int seg
);
876 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
877 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
878 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
879 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
880 static int alloc_identity_pagetable(struct kvm
*kvm
);
882 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
883 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
885 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
886 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
888 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
889 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
892 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
893 * can find which vCPU should be waken up.
895 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
896 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
898 static unsigned long *vmx_io_bitmap_a
;
899 static unsigned long *vmx_io_bitmap_b
;
900 static unsigned long *vmx_msr_bitmap_legacy
;
901 static unsigned long *vmx_msr_bitmap_longmode
;
902 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
903 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
904 static unsigned long *vmx_msr_bitmap_nested
;
905 static unsigned long *vmx_vmread_bitmap
;
906 static unsigned long *vmx_vmwrite_bitmap
;
908 static bool cpu_has_load_ia32_efer
;
909 static bool cpu_has_load_perf_global_ctrl
;
911 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
912 static DEFINE_SPINLOCK(vmx_vpid_lock
);
914 static struct vmcs_config
{
918 u32 pin_based_exec_ctrl
;
919 u32 cpu_based_exec_ctrl
;
920 u32 cpu_based_2nd_exec_ctrl
;
925 static struct vmx_capability
{
930 #define VMX_SEGMENT_FIELD(seg) \
931 [VCPU_SREG_##seg] = { \
932 .selector = GUEST_##seg##_SELECTOR, \
933 .base = GUEST_##seg##_BASE, \
934 .limit = GUEST_##seg##_LIMIT, \
935 .ar_bytes = GUEST_##seg##_AR_BYTES, \
938 static const struct kvm_vmx_segment_field
{
943 } kvm_vmx_segment_fields
[] = {
944 VMX_SEGMENT_FIELD(CS
),
945 VMX_SEGMENT_FIELD(DS
),
946 VMX_SEGMENT_FIELD(ES
),
947 VMX_SEGMENT_FIELD(FS
),
948 VMX_SEGMENT_FIELD(GS
),
949 VMX_SEGMENT_FIELD(SS
),
950 VMX_SEGMENT_FIELD(TR
),
951 VMX_SEGMENT_FIELD(LDTR
),
954 static u64 host_efer
;
956 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
959 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
960 * away by decrementing the array size.
962 static const u32 vmx_msr_index
[] = {
964 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
966 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
969 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
971 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
972 INTR_INFO_VALID_MASK
)) ==
973 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
976 static inline bool is_debug(u32 intr_info
)
978 return is_exception_n(intr_info
, DB_VECTOR
);
981 static inline bool is_breakpoint(u32 intr_info
)
983 return is_exception_n(intr_info
, BP_VECTOR
);
986 static inline bool is_page_fault(u32 intr_info
)
988 return is_exception_n(intr_info
, PF_VECTOR
);
991 static inline bool is_no_device(u32 intr_info
)
993 return is_exception_n(intr_info
, NM_VECTOR
);
996 static inline bool is_invalid_opcode(u32 intr_info
)
998 return is_exception_n(intr_info
, UD_VECTOR
);
1001 static inline bool is_external_interrupt(u32 intr_info
)
1003 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1004 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1007 static inline bool is_machine_check(u32 intr_info
)
1009 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1010 INTR_INFO_VALID_MASK
)) ==
1011 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1016 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1021 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1026 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1031 return vmcs_config
.cpu_based_exec_ctrl
&
1032 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1037 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1038 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1043 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1044 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1049 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1050 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1055 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1056 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1059 static inline bool cpu_has_vmx_posted_intr(void)
1061 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1062 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1065 static inline bool cpu_has_vmx_apicv(void)
1067 return cpu_has_vmx_apic_register_virt() &&
1068 cpu_has_vmx_virtual_intr_delivery() &&
1069 cpu_has_vmx_posted_intr();
1072 static inline bool cpu_has_vmx_flexpriority(void)
1074 return cpu_has_vmx_tpr_shadow() &&
1075 cpu_has_vmx_virtualize_apic_accesses();
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1080 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1085 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1090 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1095 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1100 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1103 static inline bool cpu_has_vmx_invept_context(void)
1105 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1108 static inline bool cpu_has_vmx_invept_global(void)
1110 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1115 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1120 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1123 static inline bool cpu_has_vmx_ept(void)
1125 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1126 SECONDARY_EXEC_ENABLE_EPT
;
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1131 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1132 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1135 static inline bool cpu_has_vmx_ple(void)
1137 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1138 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1143 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1146 static inline bool cpu_has_vmx_vpid(void)
1148 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1149 SECONDARY_EXEC_ENABLE_VPID
;
1152 static inline bool cpu_has_vmx_rdtscp(void)
1154 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1155 SECONDARY_EXEC_RDTSCP
;
1158 static inline bool cpu_has_vmx_invpcid(void)
1160 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1161 SECONDARY_EXEC_ENABLE_INVPCID
;
1164 static inline bool cpu_has_virtual_nmis(void)
1166 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1171 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1172 SECONDARY_EXEC_WBINVD_EXITING
;
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1178 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1179 /* check if the cpu supports writing r/o exit information fields */
1180 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1183 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1184 SECONDARY_EXEC_SHADOW_VMCS
;
1187 static inline bool cpu_has_vmx_pml(void)
1189 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1194 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1195 SECONDARY_EXEC_TSC_SCALING
;
1198 static inline bool report_flexpriority(void)
1200 return flexpriority_enabled
;
1203 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1205 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1208 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1210 return (vmcs12
->cpu_based_vm_exec_control
&
1211 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1212 (vmcs12
->secondary_vm_exec_control
& bit
);
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1217 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1222 return vmcs12
->pin_based_vm_exec_control
&
1223 PIN_BASED_VMX_PREEMPTION_TIMER
;
1226 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1228 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1233 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1234 vmx_xsaves_supported();
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1239 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1242 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1244 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1249 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1252 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1254 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1259 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1262 static inline bool is_exception(u32 intr_info
)
1264 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1265 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1268 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1270 unsigned long exit_qualification
);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1272 struct vmcs12
*vmcs12
,
1273 u32 reason
, unsigned long qualification
);
1275 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1279 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1280 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1285 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1291 } operand
= { vpid
, 0, gva
};
1293 asm volatile (__ex(ASM_VMX_INVVPID
)
1294 /* CF==1 or ZF==1 --> rc = -1 */
1295 "; ja 1f ; ud2 ; 1:"
1296 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1299 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1303 } operand
= {eptp
, gpa
};
1305 asm volatile (__ex(ASM_VMX_INVEPT
)
1306 /* CF==1 or ZF==1 --> rc = -1 */
1307 "; ja 1f ; ud2 ; 1:\n"
1308 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1311 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1315 i
= __find_msr_index(vmx
, msr
);
1317 return &vmx
->guest_msrs
[i
];
1321 static void vmcs_clear(struct vmcs
*vmcs
)
1323 u64 phys_addr
= __pa(vmcs
);
1326 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1327 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1330 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1334 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1336 vmcs_clear(loaded_vmcs
->vmcs
);
1337 loaded_vmcs
->cpu
= -1;
1338 loaded_vmcs
->launched
= 0;
1341 static void vmcs_load(struct vmcs
*vmcs
)
1343 u64 phys_addr
= __pa(vmcs
);
1346 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1347 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1350 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1354 #ifdef CONFIG_KEXEC_CORE
1356 * This bitmap is used to indicate whether the vmclear
1357 * operation is enabled on all cpus. All disabled by
1360 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1362 static inline void crash_enable_local_vmclear(int cpu
)
1364 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1367 static inline void crash_disable_local_vmclear(int cpu
)
1369 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1372 static inline int crash_local_vmclear_enabled(int cpu
)
1374 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1377 static void crash_vmclear_local_loaded_vmcss(void)
1379 int cpu
= raw_smp_processor_id();
1380 struct loaded_vmcs
*v
;
1382 if (!crash_local_vmclear_enabled(cpu
))
1385 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1386 loaded_vmcss_on_cpu_link
)
1387 vmcs_clear(v
->vmcs
);
1390 static inline void crash_enable_local_vmclear(int cpu
) { }
1391 static inline void crash_disable_local_vmclear(int cpu
) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1394 static void __loaded_vmcs_clear(void *arg
)
1396 struct loaded_vmcs
*loaded_vmcs
= arg
;
1397 int cpu
= raw_smp_processor_id();
1399 if (loaded_vmcs
->cpu
!= cpu
)
1400 return; /* vcpu migration can race with cpu offline */
1401 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1402 per_cpu(current_vmcs
, cpu
) = NULL
;
1403 crash_disable_local_vmclear(cpu
);
1404 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1407 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408 * is before setting loaded_vmcs->vcpu to -1 which is done in
1409 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410 * then adds the vmcs into percpu list before it is deleted.
1414 loaded_vmcs_init(loaded_vmcs
);
1415 crash_enable_local_vmclear(cpu
);
1418 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1420 int cpu
= loaded_vmcs
->cpu
;
1423 smp_call_function_single(cpu
,
1424 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1427 static inline void vpid_sync_vcpu_single(int vpid
)
1432 if (cpu_has_vmx_invvpid_single())
1433 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1436 static inline void vpid_sync_vcpu_global(void)
1438 if (cpu_has_vmx_invvpid_global())
1439 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1442 static inline void vpid_sync_context(int vpid
)
1444 if (cpu_has_vmx_invvpid_single())
1445 vpid_sync_vcpu_single(vpid
);
1447 vpid_sync_vcpu_global();
1450 static inline void ept_sync_global(void)
1452 if (cpu_has_vmx_invept_global())
1453 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1456 static inline void ept_sync_context(u64 eptp
)
1459 if (cpu_has_vmx_invept_context())
1460 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1466 static __always_inline
void vmcs_check16(unsigned long field
)
1468 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1469 "16-bit accessor invalid for 64-bit field");
1470 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1471 "16-bit accessor invalid for 64-bit high field");
1472 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1473 "16-bit accessor invalid for 32-bit high field");
1474 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1475 "16-bit accessor invalid for natural width field");
1478 static __always_inline
void vmcs_check32(unsigned long field
)
1480 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1481 "32-bit accessor invalid for 16-bit field");
1482 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1483 "32-bit accessor invalid for natural width field");
1486 static __always_inline
void vmcs_check64(unsigned long field
)
1488 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1489 "64-bit accessor invalid for 16-bit field");
1490 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1491 "64-bit accessor invalid for 64-bit high field");
1492 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1493 "64-bit accessor invalid for 32-bit field");
1494 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1495 "64-bit accessor invalid for natural width field");
1498 static __always_inline
void vmcs_checkl(unsigned long field
)
1500 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1501 "Natural width accessor invalid for 16-bit field");
1502 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1503 "Natural width accessor invalid for 64-bit field");
1504 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1505 "Natural width accessor invalid for 64-bit high field");
1506 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1507 "Natural width accessor invalid for 32-bit field");
1510 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1512 unsigned long value
;
1514 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1515 : "=a"(value
) : "d"(field
) : "cc");
1519 static __always_inline u16
vmcs_read16(unsigned long field
)
1521 vmcs_check16(field
);
1522 return __vmcs_readl(field
);
1525 static __always_inline u32
vmcs_read32(unsigned long field
)
1527 vmcs_check32(field
);
1528 return __vmcs_readl(field
);
1531 static __always_inline u64
vmcs_read64(unsigned long field
)
1533 vmcs_check64(field
);
1534 #ifdef CONFIG_X86_64
1535 return __vmcs_readl(field
);
1537 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1541 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1544 return __vmcs_readl(field
);
1547 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1549 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1550 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1554 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1558 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1559 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1560 if (unlikely(error
))
1561 vmwrite_error(field
, value
);
1564 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1566 vmcs_check16(field
);
1567 __vmcs_writel(field
, value
);
1570 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1572 vmcs_check32(field
);
1573 __vmcs_writel(field
, value
);
1576 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1578 vmcs_check64(field
);
1579 __vmcs_writel(field
, value
);
1580 #ifndef CONFIG_X86_64
1582 __vmcs_writel(field
+1, value
>> 32);
1586 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1589 __vmcs_writel(field
, value
);
1592 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1595 "vmcs_clear_bits does not support 64-bit fields");
1596 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1599 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1602 "vmcs_set_bits does not support 64-bit fields");
1603 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1606 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1608 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1609 vmx
->vm_entry_controls_shadow
= val
;
1612 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1614 if (vmx
->vm_entry_controls_shadow
!= val
)
1615 vm_entry_controls_init(vmx
, val
);
1618 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1620 return vmx
->vm_entry_controls_shadow
;
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1626 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1631 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1634 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1636 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1637 vmx
->vm_exit_controls_shadow
= val
;
1640 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1642 if (vmx
->vm_exit_controls_shadow
!= val
)
1643 vm_exit_controls_init(vmx
, val
);
1646 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1648 return vmx
->vm_exit_controls_shadow
;
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1654 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1659 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1662 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1664 vmx
->segment_cache
.bitmask
= 0;
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1671 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1673 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1674 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1675 vmx
->segment_cache
.bitmask
= 0;
1677 ret
= vmx
->segment_cache
.bitmask
& mask
;
1678 vmx
->segment_cache
.bitmask
|= mask
;
1682 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1684 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1686 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1687 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1691 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1693 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1695 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1696 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1700 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1702 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1704 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1705 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1709 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1711 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1713 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1714 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1718 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1722 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1723 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1724 if ((vcpu
->guest_debug
&
1725 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1726 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1727 eb
|= 1u << BP_VECTOR
;
1728 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1731 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1732 if (vcpu
->fpu_active
)
1733 eb
&= ~(1u << NM_VECTOR
);
1735 /* When we are running a nested L2 guest and L1 specified for it a
1736 * certain exception bitmap, we must trap the same exceptions and pass
1737 * them to L1. When running L2, we will only handle the exceptions
1738 * specified above if L1 did not want them.
1740 if (is_guest_mode(vcpu
))
1741 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1743 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1747 unsigned long entry
, unsigned long exit
)
1749 vm_entry_controls_clearbit(vmx
, entry
);
1750 vm_exit_controls_clearbit(vmx
, exit
);
1753 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1756 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1760 if (cpu_has_load_ia32_efer
) {
1761 clear_atomic_switch_msr_special(vmx
,
1762 VM_ENTRY_LOAD_IA32_EFER
,
1763 VM_EXIT_LOAD_IA32_EFER
);
1767 case MSR_CORE_PERF_GLOBAL_CTRL
:
1768 if (cpu_has_load_perf_global_ctrl
) {
1769 clear_atomic_switch_msr_special(vmx
,
1770 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1771 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1777 for (i
= 0; i
< m
->nr
; ++i
)
1778 if (m
->guest
[i
].index
== msr
)
1784 m
->guest
[i
] = m
->guest
[m
->nr
];
1785 m
->host
[i
] = m
->host
[m
->nr
];
1786 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1787 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1791 unsigned long entry
, unsigned long exit
,
1792 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1793 u64 guest_val
, u64 host_val
)
1795 vmcs_write64(guest_val_vmcs
, guest_val
);
1796 vmcs_write64(host_val_vmcs
, host_val
);
1797 vm_entry_controls_setbit(vmx
, entry
);
1798 vm_exit_controls_setbit(vmx
, exit
);
1801 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1802 u64 guest_val
, u64 host_val
)
1805 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1809 if (cpu_has_load_ia32_efer
) {
1810 add_atomic_switch_msr_special(vmx
,
1811 VM_ENTRY_LOAD_IA32_EFER
,
1812 VM_EXIT_LOAD_IA32_EFER
,
1815 guest_val
, host_val
);
1819 case MSR_CORE_PERF_GLOBAL_CTRL
:
1820 if (cpu_has_load_perf_global_ctrl
) {
1821 add_atomic_switch_msr_special(vmx
,
1822 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1823 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1824 GUEST_IA32_PERF_GLOBAL_CTRL
,
1825 HOST_IA32_PERF_GLOBAL_CTRL
,
1826 guest_val
, host_val
);
1830 case MSR_IA32_PEBS_ENABLE
:
1831 /* PEBS needs a quiescent period after being disabled (to write
1832 * a record). Disabling PEBS through VMX MSR swapping doesn't
1833 * provide that period, so a CPU could write host's record into
1836 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1839 for (i
= 0; i
< m
->nr
; ++i
)
1840 if (m
->guest
[i
].index
== msr
)
1843 if (i
== NR_AUTOLOAD_MSRS
) {
1844 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1845 "Can't add msr %x\n", msr
);
1847 } else if (i
== m
->nr
) {
1849 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1850 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1853 m
->guest
[i
].index
= msr
;
1854 m
->guest
[i
].value
= guest_val
;
1855 m
->host
[i
].index
= msr
;
1856 m
->host
[i
].value
= host_val
;
1859 static void reload_tss(void)
1862 * VT restores TR but not its size. Useless.
1864 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1865 struct desc_struct
*descs
;
1867 descs
= (void *)gdt
->address
;
1868 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1872 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1874 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1875 u64 ignore_bits
= 0;
1879 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1880 * host CPUID is more efficient than testing guest CPUID
1881 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1883 if (boot_cpu_has(X86_FEATURE_SMEP
))
1884 guest_efer
|= EFER_NX
;
1885 else if (!(guest_efer
& EFER_NX
))
1886 ignore_bits
|= EFER_NX
;
1890 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1892 ignore_bits
|= EFER_SCE
;
1893 #ifdef CONFIG_X86_64
1894 ignore_bits
|= EFER_LMA
| EFER_LME
;
1895 /* SCE is meaningful only in long mode on Intel */
1896 if (guest_efer
& EFER_LMA
)
1897 ignore_bits
&= ~(u64
)EFER_SCE
;
1900 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1903 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904 * On CPUs that support "load IA32_EFER", always switch EFER
1905 * atomically, since it's faster than switching it manually.
1907 if (cpu_has_load_ia32_efer
||
1908 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1909 if (!(guest_efer
& EFER_LMA
))
1910 guest_efer
&= ~EFER_LME
;
1911 if (guest_efer
!= host_efer
)
1912 add_atomic_switch_msr(vmx
, MSR_EFER
,
1913 guest_efer
, host_efer
);
1916 guest_efer
&= ~ignore_bits
;
1917 guest_efer
|= host_efer
& ignore_bits
;
1919 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1920 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1926 static unsigned long segment_base(u16 selector
)
1928 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1929 struct desc_struct
*d
;
1930 unsigned long table_base
;
1933 if (!(selector
& ~3))
1936 table_base
= gdt
->address
;
1938 if (selector
& 4) { /* from ldt */
1939 u16 ldt_selector
= kvm_read_ldt();
1941 if (!(ldt_selector
& ~3))
1944 table_base
= segment_base(ldt_selector
);
1946 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1947 v
= get_desc_base(d
);
1948 #ifdef CONFIG_X86_64
1949 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1950 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1955 static inline unsigned long kvm_read_tr_base(void)
1958 asm("str %0" : "=g"(tr
));
1959 return segment_base(tr
);
1962 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1967 if (vmx
->host_state
.loaded
)
1970 vmx
->host_state
.loaded
= 1;
1972 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1973 * allow segment selectors with cpl > 0 or ti == 1.
1975 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1976 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1977 savesegment(fs
, vmx
->host_state
.fs_sel
);
1978 if (!(vmx
->host_state
.fs_sel
& 7)) {
1979 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1980 vmx
->host_state
.fs_reload_needed
= 0;
1982 vmcs_write16(HOST_FS_SELECTOR
, 0);
1983 vmx
->host_state
.fs_reload_needed
= 1;
1985 savesegment(gs
, vmx
->host_state
.gs_sel
);
1986 if (!(vmx
->host_state
.gs_sel
& 7))
1987 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1989 vmcs_write16(HOST_GS_SELECTOR
, 0);
1990 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1993 #ifdef CONFIG_X86_64
1994 savesegment(ds
, vmx
->host_state
.ds_sel
);
1995 savesegment(es
, vmx
->host_state
.es_sel
);
1998 #ifdef CONFIG_X86_64
1999 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2000 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2002 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2003 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2006 #ifdef CONFIG_X86_64
2007 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2008 if (is_long_mode(&vmx
->vcpu
))
2009 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2011 if (boot_cpu_has(X86_FEATURE_MPX
))
2012 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2013 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2014 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2015 vmx
->guest_msrs
[i
].data
,
2016 vmx
->guest_msrs
[i
].mask
);
2019 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2021 if (!vmx
->host_state
.loaded
)
2024 ++vmx
->vcpu
.stat
.host_state_reload
;
2025 vmx
->host_state
.loaded
= 0;
2026 #ifdef CONFIG_X86_64
2027 if (is_long_mode(&vmx
->vcpu
))
2028 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2030 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2031 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2032 #ifdef CONFIG_X86_64
2033 load_gs_index(vmx
->host_state
.gs_sel
);
2035 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2038 if (vmx
->host_state
.fs_reload_needed
)
2039 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2040 #ifdef CONFIG_X86_64
2041 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2042 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2043 loadsegment(es
, vmx
->host_state
.es_sel
);
2047 #ifdef CONFIG_X86_64
2048 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2050 if (vmx
->host_state
.msr_host_bndcfgs
)
2051 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2053 * If the FPU is not active (through the host task or
2054 * the guest vcpu), then restore the cr0.TS bit.
2056 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2058 load_gdt(this_cpu_ptr(&host_gdt
));
2061 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2064 __vmx_load_host_state(vmx
);
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2070 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2071 struct pi_desc old
, new;
2074 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2075 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2076 !kvm_vcpu_apicv_active(vcpu
))
2080 old
.control
= new.control
= pi_desc
->control
;
2083 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2084 * are two possible cases:
2085 * 1. After running 'pre_block', context switch
2086 * happened. For this case, 'sn' was set in
2087 * vmx_vcpu_put(), so we need to clear it here.
2088 * 2. After running 'pre_block', we were blocked,
2089 * and woken up by some other guy. For this case,
2090 * we don't need to do anything, 'pi_post_block'
2091 * will do everything for us. However, we cannot
2092 * check whether it is case #1 or case #2 here
2093 * (maybe, not needed), so we also clear sn here,
2094 * I think it is not a big deal.
2096 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2097 if (vcpu
->cpu
!= cpu
) {
2098 dest
= cpu_physical_id(cpu
);
2100 if (x2apic_enabled())
2103 new.ndst
= (dest
<< 8) & 0xFF00;
2106 /* set 'NV' to 'notification vector' */
2107 new.nv
= POSTED_INTR_VECTOR
;
2110 /* Allow posting non-urgent interrupts */
2112 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2113 new.control
) != old
.control
);
2117 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2118 * vcpu mutex is already taken.
2120 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2123 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2126 kvm_cpu_vmxon(phys_addr
);
2127 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2128 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2130 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2131 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2132 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2135 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2136 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2137 unsigned long sysenter_esp
;
2139 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2140 local_irq_disable();
2141 crash_disable_local_vmclear(cpu
);
2144 * Read loaded_vmcs->cpu should be before fetching
2145 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2146 * See the comments in __loaded_vmcs_clear().
2150 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2151 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2152 crash_enable_local_vmclear(cpu
);
2156 * Linux uses per-cpu TSS and GDT, so set these when switching
2159 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2160 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2162 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2163 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2165 vmx
->loaded_vmcs
->cpu
= cpu
;
2168 /* Setup TSC multiplier */
2169 if (kvm_has_tsc_control
&&
2170 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
) {
2171 vmx
->current_tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2172 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2175 vmx_vcpu_pi_load(vcpu
, cpu
);
2176 vmx
->host_pkru
= read_pkru();
2179 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2181 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2183 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2184 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2185 !kvm_vcpu_apicv_active(vcpu
))
2188 /* Set SN when the vCPU is preempted */
2189 if (vcpu
->preempted
)
2193 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2195 vmx_vcpu_pi_put(vcpu
);
2197 __vmx_load_host_state(to_vmx(vcpu
));
2198 if (!vmm_exclusive
) {
2199 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2205 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2209 if (vcpu
->fpu_active
)
2211 vcpu
->fpu_active
= 1;
2212 cr0
= vmcs_readl(GUEST_CR0
);
2213 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2214 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2215 vmcs_writel(GUEST_CR0
, cr0
);
2216 update_exception_bitmap(vcpu
);
2217 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2218 if (is_guest_mode(vcpu
))
2219 vcpu
->arch
.cr0_guest_owned_bits
&=
2220 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2221 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2224 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2227 * Return the cr0 value that a nested guest would read. This is a combination
2228 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2229 * its hypervisor (cr0_read_shadow).
2231 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2233 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2234 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2236 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2238 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2239 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2242 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2244 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2245 * set this *before* calling this function.
2247 vmx_decache_cr0_guest_bits(vcpu
);
2248 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2249 update_exception_bitmap(vcpu
);
2250 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2251 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2252 if (is_guest_mode(vcpu
)) {
2254 * L1's specified read shadow might not contain the TS bit,
2255 * so now that we turned on shadowing of this bit, we need to
2256 * set this bit of the shadow. Like in nested_vmx_run we need
2257 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2258 * up-to-date here because we just decached cr0.TS (and we'll
2259 * only update vmcs12->guest_cr0 on nested exit).
2261 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2262 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2263 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2264 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2266 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2269 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2271 unsigned long rflags
, save_rflags
;
2273 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2274 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2275 rflags
= vmcs_readl(GUEST_RFLAGS
);
2276 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2277 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2278 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2279 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2281 to_vmx(vcpu
)->rflags
= rflags
;
2283 return to_vmx(vcpu
)->rflags
;
2286 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2288 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2289 to_vmx(vcpu
)->rflags
= rflags
;
2290 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2291 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2292 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2294 vmcs_writel(GUEST_RFLAGS
, rflags
);
2297 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2299 return to_vmx(vcpu
)->guest_pkru
;
2302 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2304 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2307 if (interruptibility
& GUEST_INTR_STATE_STI
)
2308 ret
|= KVM_X86_SHADOW_INT_STI
;
2309 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2310 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2315 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2317 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2318 u32 interruptibility
= interruptibility_old
;
2320 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2322 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2323 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2324 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2325 interruptibility
|= GUEST_INTR_STATE_STI
;
2327 if ((interruptibility
!= interruptibility_old
))
2328 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2331 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2335 rip
= kvm_rip_read(vcpu
);
2336 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2337 kvm_rip_write(vcpu
, rip
);
2339 /* skipping an emulated instruction also counts */
2340 vmx_set_interrupt_shadow(vcpu
, 0);
2344 * KVM wants to inject page-faults which it got to the guest. This function
2345 * checks whether in a nested guest, we need to inject them to L1 or L2.
2347 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2349 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2351 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2354 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2355 vmcs_read32(VM_EXIT_INTR_INFO
),
2356 vmcs_readl(EXIT_QUALIFICATION
));
2360 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2361 bool has_error_code
, u32 error_code
,
2364 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2365 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2367 if (!reinject
&& is_guest_mode(vcpu
) &&
2368 nested_vmx_check_exception(vcpu
, nr
))
2371 if (has_error_code
) {
2372 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2373 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2376 if (vmx
->rmode
.vm86_active
) {
2378 if (kvm_exception_is_soft(nr
))
2379 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2380 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2381 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2385 if (kvm_exception_is_soft(nr
)) {
2386 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2387 vmx
->vcpu
.arch
.event_exit_inst_len
);
2388 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2390 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2392 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2395 static bool vmx_rdtscp_supported(void)
2397 return cpu_has_vmx_rdtscp();
2400 static bool vmx_invpcid_supported(void)
2402 return cpu_has_vmx_invpcid() && enable_ept
;
2406 * Swap MSR entry in host/guest MSR entry array.
2408 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2410 struct shared_msr_entry tmp
;
2412 tmp
= vmx
->guest_msrs
[to
];
2413 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2414 vmx
->guest_msrs
[from
] = tmp
;
2417 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2419 unsigned long *msr_bitmap
;
2421 if (is_guest_mode(vcpu
))
2422 msr_bitmap
= vmx_msr_bitmap_nested
;
2423 else if (cpu_has_secondary_exec_ctrls() &&
2424 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2425 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2426 if (is_long_mode(vcpu
))
2427 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2429 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2431 if (is_long_mode(vcpu
))
2432 msr_bitmap
= vmx_msr_bitmap_longmode
;
2434 msr_bitmap
= vmx_msr_bitmap_legacy
;
2437 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2441 * Set up the vmcs to automatically save and restore system
2442 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2443 * mode, as fiddling with msrs is very expensive.
2445 static void setup_msrs(struct vcpu_vmx
*vmx
)
2447 int save_nmsrs
, index
;
2450 #ifdef CONFIG_X86_64
2451 if (is_long_mode(&vmx
->vcpu
)) {
2452 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2454 move_msr_up(vmx
, index
, save_nmsrs
++);
2455 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2457 move_msr_up(vmx
, index
, save_nmsrs
++);
2458 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2460 move_msr_up(vmx
, index
, save_nmsrs
++);
2461 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2462 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2463 move_msr_up(vmx
, index
, save_nmsrs
++);
2465 * MSR_STAR is only needed on long mode guests, and only
2466 * if efer.sce is enabled.
2468 index
= __find_msr_index(vmx
, MSR_STAR
);
2469 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2470 move_msr_up(vmx
, index
, save_nmsrs
++);
2473 index
= __find_msr_index(vmx
, MSR_EFER
);
2474 if (index
>= 0 && update_transition_efer(vmx
, index
))
2475 move_msr_up(vmx
, index
, save_nmsrs
++);
2477 vmx
->save_nmsrs
= save_nmsrs
;
2479 if (cpu_has_vmx_msr_bitmap())
2480 vmx_set_msr_bitmap(&vmx
->vcpu
);
2484 * reads and returns guest's timestamp counter "register"
2485 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2486 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2488 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2490 u64 host_tsc
, tsc_offset
;
2493 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2494 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2498 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2499 * counter, even if a nested guest (L2) is currently running.
2501 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2505 tsc_offset
= is_guest_mode(vcpu
) ?
2506 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2507 vmcs_read64(TSC_OFFSET
);
2508 return host_tsc
+ tsc_offset
;
2511 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2513 return vmcs_read64(TSC_OFFSET
);
2517 * writes 'offset' into guest's timestamp counter offset register
2519 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2521 if (is_guest_mode(vcpu
)) {
2523 * We're here if L1 chose not to trap WRMSR to TSC. According
2524 * to the spec, this should set L1's TSC; The offset that L1
2525 * set for L2 remains unchanged, and still needs to be added
2526 * to the newly set TSC to get L2's TSC.
2528 struct vmcs12
*vmcs12
;
2529 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2530 /* recalculate vmcs02.TSC_OFFSET: */
2531 vmcs12
= get_vmcs12(vcpu
);
2532 vmcs_write64(TSC_OFFSET
, offset
+
2533 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2534 vmcs12
->tsc_offset
: 0));
2536 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2537 vmcs_read64(TSC_OFFSET
), offset
);
2538 vmcs_write64(TSC_OFFSET
, offset
);
2542 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2544 u64 offset
= vmcs_read64(TSC_OFFSET
);
2546 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2547 if (is_guest_mode(vcpu
)) {
2548 /* Even when running L2, the adjustment needs to apply to L1 */
2549 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2551 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2552 offset
+ adjustment
);
2555 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2557 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2558 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2562 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2563 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2564 * all guests if the "nested" module option is off, and can also be disabled
2565 * for a single guest by disabling its VMX cpuid bit.
2567 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2569 return nested
&& guest_cpuid_has_vmx(vcpu
);
2573 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2574 * returned for the various VMX controls MSRs when nested VMX is enabled.
2575 * The same values should also be used to verify that vmcs12 control fields are
2576 * valid during nested entry from L1 to L2.
2577 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2578 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2579 * bit in the high half is on if the corresponding bit in the control field
2580 * may be on. See also vmx_control_verify().
2582 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2585 * Note that as a general rule, the high half of the MSRs (bits in
2586 * the control fields which may be 1) should be initialized by the
2587 * intersection of the underlying hardware's MSR (i.e., features which
2588 * can be supported) and the list of features we want to expose -
2589 * because they are known to be properly supported in our code.
2590 * Also, usually, the low half of the MSRs (bits which must be 1) can
2591 * be set to 0, meaning that L1 may turn off any of these bits. The
2592 * reason is that if one of these bits is necessary, it will appear
2593 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2594 * fields of vmcs01 and vmcs02, will turn these bits off - and
2595 * nested_vmx_exit_handled() will not pass related exits to L1.
2596 * These rules have exceptions below.
2599 /* pin-based controls */
2600 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2601 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2602 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2603 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2604 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2605 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2606 PIN_BASED_EXT_INTR_MASK
|
2607 PIN_BASED_NMI_EXITING
|
2608 PIN_BASED_VIRTUAL_NMIS
;
2609 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2610 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2611 PIN_BASED_VMX_PREEMPTION_TIMER
;
2612 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2613 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2614 PIN_BASED_POSTED_INTR
;
2617 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2618 vmx
->nested
.nested_vmx_exit_ctls_low
,
2619 vmx
->nested
.nested_vmx_exit_ctls_high
);
2620 vmx
->nested
.nested_vmx_exit_ctls_low
=
2621 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2623 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2624 #ifdef CONFIG_X86_64
2625 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2627 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2628 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2629 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2630 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2631 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2633 if (kvm_mpx_supported())
2634 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2636 /* We support free control of debug control saving. */
2637 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2638 vmx
->nested
.nested_vmx_exit_ctls_low
&
2639 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2641 /* entry controls */
2642 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2643 vmx
->nested
.nested_vmx_entry_ctls_low
,
2644 vmx
->nested
.nested_vmx_entry_ctls_high
);
2645 vmx
->nested
.nested_vmx_entry_ctls_low
=
2646 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2647 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2648 #ifdef CONFIG_X86_64
2649 VM_ENTRY_IA32E_MODE
|
2651 VM_ENTRY_LOAD_IA32_PAT
;
2652 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2653 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2654 if (kvm_mpx_supported())
2655 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2657 /* We support free control of debug control loading. */
2658 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2659 vmx
->nested
.nested_vmx_entry_ctls_low
&
2660 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2662 /* cpu-based controls */
2663 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2664 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2665 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2666 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2667 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2668 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2669 CPU_BASED_VIRTUAL_INTR_PENDING
|
2670 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2671 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2672 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2673 CPU_BASED_CR3_STORE_EXITING
|
2674 #ifdef CONFIG_X86_64
2675 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2677 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2678 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2679 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2680 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2681 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2683 * We can allow some features even when not supported by the
2684 * hardware. For example, L1 can specify an MSR bitmap - and we
2685 * can use it to avoid exits to L1 - even when L0 runs L2
2686 * without MSR bitmaps.
2688 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2689 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2690 CPU_BASED_USE_MSR_BITMAPS
;
2692 /* We support free control of CR3 access interception. */
2693 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2694 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2695 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2697 /* secondary cpu-based controls */
2698 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2699 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2700 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2701 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2702 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2703 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2704 SECONDARY_EXEC_RDTSCP
|
2705 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2706 SECONDARY_EXEC_ENABLE_VPID
|
2707 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2708 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2709 SECONDARY_EXEC_WBINVD_EXITING
|
2710 SECONDARY_EXEC_XSAVES
|
2711 SECONDARY_EXEC_PCOMMIT
;
2714 /* nested EPT: emulate EPT also to L1 */
2715 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2716 SECONDARY_EXEC_ENABLE_EPT
;
2717 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2718 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2720 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2722 * For nested guests, we don't do anything specific
2723 * for single context invalidation. Hence, only advertise
2724 * support for global context invalidation.
2726 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2728 vmx
->nested
.nested_vmx_ept_caps
= 0;
2731 * Old versions of KVM use the single-context version without
2732 * checking for support, so declare that it is supported even
2733 * though it is treated as global context. The alternative is
2734 * not failing the single-context invvpid, and it is worse.
2737 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2738 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
|
2739 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2741 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2743 if (enable_unrestricted_guest
)
2744 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2745 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2747 /* miscellaneous data */
2748 rdmsr(MSR_IA32_VMX_MISC
,
2749 vmx
->nested
.nested_vmx_misc_low
,
2750 vmx
->nested
.nested_vmx_misc_high
);
2751 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2752 vmx
->nested
.nested_vmx_misc_low
|=
2753 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2754 VMX_MISC_ACTIVITY_HLT
;
2755 vmx
->nested
.nested_vmx_misc_high
= 0;
2758 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2761 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2763 return ((control
& high
) | low
) == control
;
2766 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2768 return low
| ((u64
)high
<< 32);
2771 /* Returns 0 on success, non-0 otherwise. */
2772 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2774 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2776 switch (msr_index
) {
2777 case MSR_IA32_VMX_BASIC
:
2779 * This MSR reports some information about VMX support. We
2780 * should return information about the VMX we emulate for the
2781 * guest, and the VMCS structure we give it - not about the
2782 * VMX support of the underlying hardware.
2784 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2785 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2786 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2788 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2789 case MSR_IA32_VMX_PINBASED_CTLS
:
2790 *pdata
= vmx_control_msr(
2791 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2792 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2794 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2795 *pdata
= vmx_control_msr(
2796 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2797 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2799 case MSR_IA32_VMX_PROCBASED_CTLS
:
2800 *pdata
= vmx_control_msr(
2801 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2802 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2804 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2805 *pdata
= vmx_control_msr(
2806 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2807 vmx
->nested
.nested_vmx_exit_ctls_high
);
2809 case MSR_IA32_VMX_EXIT_CTLS
:
2810 *pdata
= vmx_control_msr(
2811 vmx
->nested
.nested_vmx_exit_ctls_low
,
2812 vmx
->nested
.nested_vmx_exit_ctls_high
);
2814 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2815 *pdata
= vmx_control_msr(
2816 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2817 vmx
->nested
.nested_vmx_entry_ctls_high
);
2819 case MSR_IA32_VMX_ENTRY_CTLS
:
2820 *pdata
= vmx_control_msr(
2821 vmx
->nested
.nested_vmx_entry_ctls_low
,
2822 vmx
->nested
.nested_vmx_entry_ctls_high
);
2824 case MSR_IA32_VMX_MISC
:
2825 *pdata
= vmx_control_msr(
2826 vmx
->nested
.nested_vmx_misc_low
,
2827 vmx
->nested
.nested_vmx_misc_high
);
2830 * These MSRs specify bits which the guest must keep fixed (on or off)
2831 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2832 * We picked the standard core2 setting.
2834 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2835 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2836 case MSR_IA32_VMX_CR0_FIXED0
:
2837 *pdata
= VMXON_CR0_ALWAYSON
;
2839 case MSR_IA32_VMX_CR0_FIXED1
:
2842 case MSR_IA32_VMX_CR4_FIXED0
:
2843 *pdata
= VMXON_CR4_ALWAYSON
;
2845 case MSR_IA32_VMX_CR4_FIXED1
:
2848 case MSR_IA32_VMX_VMCS_ENUM
:
2849 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2851 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2852 *pdata
= vmx_control_msr(
2853 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2854 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2856 case MSR_IA32_VMX_EPT_VPID_CAP
:
2857 /* Currently, no nested vpid support */
2858 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2859 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2869 * Reads an msr value (of 'msr_index') into 'pdata'.
2870 * Returns 0 on success, non-0 otherwise.
2871 * Assumes vcpu_load() was already called.
2873 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2875 struct shared_msr_entry
*msr
;
2877 switch (msr_info
->index
) {
2878 #ifdef CONFIG_X86_64
2880 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2883 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2885 case MSR_KERNEL_GS_BASE
:
2886 vmx_load_host_state(to_vmx(vcpu
));
2887 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2891 return kvm_get_msr_common(vcpu
, msr_info
);
2893 msr_info
->data
= guest_read_tsc(vcpu
);
2895 case MSR_IA32_SYSENTER_CS
:
2896 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2898 case MSR_IA32_SYSENTER_EIP
:
2899 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2901 case MSR_IA32_SYSENTER_ESP
:
2902 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2904 case MSR_IA32_BNDCFGS
:
2905 if (!kvm_mpx_supported())
2907 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2909 case MSR_IA32_FEATURE_CONTROL
:
2910 if (!nested_vmx_allowed(vcpu
))
2912 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2914 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2915 if (!nested_vmx_allowed(vcpu
))
2917 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2919 if (!vmx_xsaves_supported())
2921 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2924 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2926 /* Otherwise falls through */
2928 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2930 msr_info
->data
= msr
->data
;
2933 return kvm_get_msr_common(vcpu
, msr_info
);
2939 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2942 * Writes msr value into into the appropriate "register".
2943 * Returns 0 on success, non-0 otherwise.
2944 * Assumes vcpu_load() was already called.
2946 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2948 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2949 struct shared_msr_entry
*msr
;
2951 u32 msr_index
= msr_info
->index
;
2952 u64 data
= msr_info
->data
;
2954 switch (msr_index
) {
2956 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2958 #ifdef CONFIG_X86_64
2960 vmx_segment_cache_clear(vmx
);
2961 vmcs_writel(GUEST_FS_BASE
, data
);
2964 vmx_segment_cache_clear(vmx
);
2965 vmcs_writel(GUEST_GS_BASE
, data
);
2967 case MSR_KERNEL_GS_BASE
:
2968 vmx_load_host_state(vmx
);
2969 vmx
->msr_guest_kernel_gs_base
= data
;
2972 case MSR_IA32_SYSENTER_CS
:
2973 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2975 case MSR_IA32_SYSENTER_EIP
:
2976 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2978 case MSR_IA32_SYSENTER_ESP
:
2979 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2981 case MSR_IA32_BNDCFGS
:
2982 if (!kvm_mpx_supported())
2984 vmcs_write64(GUEST_BNDCFGS
, data
);
2987 kvm_write_tsc(vcpu
, msr_info
);
2989 case MSR_IA32_CR_PAT
:
2990 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2991 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2993 vmcs_write64(GUEST_IA32_PAT
, data
);
2994 vcpu
->arch
.pat
= data
;
2997 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2999 case MSR_IA32_TSC_ADJUST
:
3000 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3002 case MSR_IA32_FEATURE_CONTROL
:
3003 if (!nested_vmx_allowed(vcpu
) ||
3004 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
3005 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3007 vmx
->nested
.msr_ia32_feature_control
= data
;
3008 if (msr_info
->host_initiated
&& data
== 0)
3009 vmx_leave_nested(vcpu
);
3011 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3012 return 1; /* they are read-only */
3014 if (!vmx_xsaves_supported())
3017 * The only supported bit as of Skylake is bit 8, but
3018 * it is not supported on KVM.
3022 vcpu
->arch
.ia32_xss
= data
;
3023 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3024 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3025 vcpu
->arch
.ia32_xss
, host_xss
);
3027 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3030 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3032 /* Check reserved bit, higher 32 bits should be zero */
3033 if ((data
>> 32) != 0)
3035 /* Otherwise falls through */
3037 msr
= find_msr_entry(vmx
, msr_index
);
3039 u64 old_msr_data
= msr
->data
;
3041 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3043 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3047 msr
->data
= old_msr_data
;
3051 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3057 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3059 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3062 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3065 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3067 case VCPU_EXREG_PDPTR
:
3069 ept_save_pdptrs(vcpu
);
3076 static __init
int cpu_has_kvm_support(void)
3078 return cpu_has_vmx();
3081 static __init
int vmx_disabled_by_bios(void)
3085 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3086 if (msr
& FEATURE_CONTROL_LOCKED
) {
3087 /* launched w/ TXT and VMX disabled */
3088 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3091 /* launched w/o TXT and VMX only enabled w/ TXT */
3092 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3093 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3094 && !tboot_enabled()) {
3095 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3096 "activate TXT before enabling KVM\n");
3099 /* launched w/o TXT and VMX disabled */
3100 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3101 && !tboot_enabled())
3108 static void kvm_cpu_vmxon(u64 addr
)
3110 intel_pt_handle_vmx(1);
3112 asm volatile (ASM_VMX_VMXON_RAX
3113 : : "a"(&addr
), "m"(addr
)
3117 static int hardware_enable(void)
3119 int cpu
= raw_smp_processor_id();
3120 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3123 if (cr4_read_shadow() & X86_CR4_VMXE
)
3126 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3127 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3128 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3131 * Now we can enable the vmclear operation in kdump
3132 * since the loaded_vmcss_on_cpu list on this cpu
3133 * has been initialized.
3135 * Though the cpu is not in VMX operation now, there
3136 * is no problem to enable the vmclear operation
3137 * for the loaded_vmcss_on_cpu list is empty!
3139 crash_enable_local_vmclear(cpu
);
3141 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3143 test_bits
= FEATURE_CONTROL_LOCKED
;
3144 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3145 if (tboot_enabled())
3146 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3148 if ((old
& test_bits
) != test_bits
) {
3149 /* enable and lock */
3150 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3152 cr4_set_bits(X86_CR4_VMXE
);
3154 if (vmm_exclusive
) {
3155 kvm_cpu_vmxon(phys_addr
);
3159 native_store_gdt(this_cpu_ptr(&host_gdt
));
3164 static void vmclear_local_loaded_vmcss(void)
3166 int cpu
= raw_smp_processor_id();
3167 struct loaded_vmcs
*v
, *n
;
3169 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3170 loaded_vmcss_on_cpu_link
)
3171 __loaded_vmcs_clear(v
);
3175 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3178 static void kvm_cpu_vmxoff(void)
3180 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3182 intel_pt_handle_vmx(0);
3185 static void hardware_disable(void)
3187 if (vmm_exclusive
) {
3188 vmclear_local_loaded_vmcss();
3191 cr4_clear_bits(X86_CR4_VMXE
);
3194 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3195 u32 msr
, u32
*result
)
3197 u32 vmx_msr_low
, vmx_msr_high
;
3198 u32 ctl
= ctl_min
| ctl_opt
;
3200 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3202 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3203 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3205 /* Ensure minimum (required) set of control bits are supported. */
3213 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3215 u32 vmx_msr_low
, vmx_msr_high
;
3217 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3218 return vmx_msr_high
& ctl
;
3221 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3223 u32 vmx_msr_low
, vmx_msr_high
;
3224 u32 min
, opt
, min2
, opt2
;
3225 u32 _pin_based_exec_control
= 0;
3226 u32 _cpu_based_exec_control
= 0;
3227 u32 _cpu_based_2nd_exec_control
= 0;
3228 u32 _vmexit_control
= 0;
3229 u32 _vmentry_control
= 0;
3231 min
= CPU_BASED_HLT_EXITING
|
3232 #ifdef CONFIG_X86_64
3233 CPU_BASED_CR8_LOAD_EXITING
|
3234 CPU_BASED_CR8_STORE_EXITING
|
3236 CPU_BASED_CR3_LOAD_EXITING
|
3237 CPU_BASED_CR3_STORE_EXITING
|
3238 CPU_BASED_USE_IO_BITMAPS
|
3239 CPU_BASED_MOV_DR_EXITING
|
3240 CPU_BASED_USE_TSC_OFFSETING
|
3241 CPU_BASED_MWAIT_EXITING
|
3242 CPU_BASED_MONITOR_EXITING
|
3243 CPU_BASED_INVLPG_EXITING
|
3244 CPU_BASED_RDPMC_EXITING
;
3246 opt
= CPU_BASED_TPR_SHADOW
|
3247 CPU_BASED_USE_MSR_BITMAPS
|
3248 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3249 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3250 &_cpu_based_exec_control
) < 0)
3252 #ifdef CONFIG_X86_64
3253 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3254 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3255 ~CPU_BASED_CR8_STORE_EXITING
;
3257 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3259 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3260 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3261 SECONDARY_EXEC_WBINVD_EXITING
|
3262 SECONDARY_EXEC_ENABLE_VPID
|
3263 SECONDARY_EXEC_ENABLE_EPT
|
3264 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3265 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3266 SECONDARY_EXEC_RDTSCP
|
3267 SECONDARY_EXEC_ENABLE_INVPCID
|
3268 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3269 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3270 SECONDARY_EXEC_SHADOW_VMCS
|
3271 SECONDARY_EXEC_XSAVES
|
3272 SECONDARY_EXEC_ENABLE_PML
|
3273 SECONDARY_EXEC_PCOMMIT
|
3274 SECONDARY_EXEC_TSC_SCALING
;
3275 if (adjust_vmx_controls(min2
, opt2
,
3276 MSR_IA32_VMX_PROCBASED_CTLS2
,
3277 &_cpu_based_2nd_exec_control
) < 0)
3280 #ifndef CONFIG_X86_64
3281 if (!(_cpu_based_2nd_exec_control
&
3282 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3283 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3286 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3287 _cpu_based_2nd_exec_control
&= ~(
3288 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3289 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3290 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3292 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3293 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3295 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3296 CPU_BASED_CR3_STORE_EXITING
|
3297 CPU_BASED_INVLPG_EXITING
);
3298 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3299 vmx_capability
.ept
, vmx_capability
.vpid
);
3302 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3303 #ifdef CONFIG_X86_64
3304 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3306 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3307 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3308 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3309 &_vmexit_control
) < 0)
3312 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3313 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3314 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3315 &_pin_based_exec_control
) < 0)
3318 if (!(_cpu_based_2nd_exec_control
&
3319 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3320 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3321 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3323 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3324 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3325 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3326 &_vmentry_control
) < 0)
3329 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3331 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3332 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3335 #ifdef CONFIG_X86_64
3336 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3337 if (vmx_msr_high
& (1u<<16))
3341 /* Require Write-Back (WB) memory type for VMCS accesses. */
3342 if (((vmx_msr_high
>> 18) & 15) != 6)
3345 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3346 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3347 vmcs_conf
->revision_id
= vmx_msr_low
;
3349 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3350 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3351 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3352 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3353 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3355 cpu_has_load_ia32_efer
=
3356 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3357 VM_ENTRY_LOAD_IA32_EFER
)
3358 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3359 VM_EXIT_LOAD_IA32_EFER
);
3361 cpu_has_load_perf_global_ctrl
=
3362 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3363 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3364 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3365 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3368 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3369 * but due to arrata below it can't be used. Workaround is to use
3370 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3372 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3377 * BC86,AAY89,BD102 (model 44)
3381 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3382 switch (boot_cpu_data
.x86_model
) {
3388 cpu_has_load_perf_global_ctrl
= false;
3389 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3390 "does not work properly. Using workaround\n");
3397 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3398 rdmsrl(MSR_IA32_XSS
, host_xss
);
3403 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3405 int node
= cpu_to_node(cpu
);
3409 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3412 vmcs
= page_address(pages
);
3413 memset(vmcs
, 0, vmcs_config
.size
);
3414 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3418 static struct vmcs
*alloc_vmcs(void)
3420 return alloc_vmcs_cpu(raw_smp_processor_id());
3423 static void free_vmcs(struct vmcs
*vmcs
)
3425 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3429 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3431 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3433 if (!loaded_vmcs
->vmcs
)
3435 loaded_vmcs_clear(loaded_vmcs
);
3436 free_vmcs(loaded_vmcs
->vmcs
);
3437 loaded_vmcs
->vmcs
= NULL
;
3440 static void free_kvm_area(void)
3444 for_each_possible_cpu(cpu
) {
3445 free_vmcs(per_cpu(vmxarea
, cpu
));
3446 per_cpu(vmxarea
, cpu
) = NULL
;
3450 static void init_vmcs_shadow_fields(void)
3454 /* No checks for read only fields yet */
3456 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3457 switch (shadow_read_write_fields
[i
]) {
3459 if (!kvm_mpx_supported())
3467 shadow_read_write_fields
[j
] =
3468 shadow_read_write_fields
[i
];
3471 max_shadow_read_write_fields
= j
;
3473 /* shadowed fields guest access without vmexit */
3474 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3475 clear_bit(shadow_read_write_fields
[i
],
3476 vmx_vmwrite_bitmap
);
3477 clear_bit(shadow_read_write_fields
[i
],
3480 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3481 clear_bit(shadow_read_only_fields
[i
],
3485 static __init
int alloc_kvm_area(void)
3489 for_each_possible_cpu(cpu
) {
3492 vmcs
= alloc_vmcs_cpu(cpu
);
3498 per_cpu(vmxarea
, cpu
) = vmcs
;
3503 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3505 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3508 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3509 struct kvm_segment
*save
)
3511 if (!emulate_invalid_guest_state
) {
3513 * CS and SS RPL should be equal during guest entry according
3514 * to VMX spec, but in reality it is not always so. Since vcpu
3515 * is in the middle of the transition from real mode to
3516 * protected mode it is safe to assume that RPL 0 is a good
3519 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3520 save
->selector
&= ~SEGMENT_RPL_MASK
;
3521 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3524 vmx_set_segment(vcpu
, save
, seg
);
3527 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3529 unsigned long flags
;
3530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3533 * Update real mode segment cache. It may be not up-to-date if sement
3534 * register was written while vcpu was in a guest mode.
3536 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3537 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3538 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3539 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3540 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3541 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3543 vmx
->rmode
.vm86_active
= 0;
3545 vmx_segment_cache_clear(vmx
);
3547 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3549 flags
= vmcs_readl(GUEST_RFLAGS
);
3550 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3551 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3552 vmcs_writel(GUEST_RFLAGS
, flags
);
3554 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3555 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3557 update_exception_bitmap(vcpu
);
3559 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3560 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3561 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3562 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3563 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3564 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3567 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3569 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3570 struct kvm_segment var
= *save
;
3573 if (seg
== VCPU_SREG_CS
)
3576 if (!emulate_invalid_guest_state
) {
3577 var
.selector
= var
.base
>> 4;
3578 var
.base
= var
.base
& 0xffff0;
3588 if (save
->base
& 0xf)
3589 printk_once(KERN_WARNING
"kvm: segment base is not "
3590 "paragraph aligned when entering "
3591 "protected mode (seg=%d)", seg
);
3594 vmcs_write16(sf
->selector
, var
.selector
);
3595 vmcs_write32(sf
->base
, var
.base
);
3596 vmcs_write32(sf
->limit
, var
.limit
);
3597 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3600 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3602 unsigned long flags
;
3603 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3605 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3606 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3607 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3608 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3609 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3610 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3611 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3613 vmx
->rmode
.vm86_active
= 1;
3616 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3617 * vcpu. Warn the user that an update is overdue.
3619 if (!vcpu
->kvm
->arch
.tss_addr
)
3620 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3621 "called before entering vcpu\n");
3623 vmx_segment_cache_clear(vmx
);
3625 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3626 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3627 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3629 flags
= vmcs_readl(GUEST_RFLAGS
);
3630 vmx
->rmode
.save_rflags
= flags
;
3632 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3634 vmcs_writel(GUEST_RFLAGS
, flags
);
3635 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3636 update_exception_bitmap(vcpu
);
3638 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3639 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3640 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3641 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3642 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3643 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3645 kvm_mmu_reset_context(vcpu
);
3648 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3651 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3657 * Force kernel_gs_base reloading before EFER changes, as control
3658 * of this msr depends on is_long_mode().
3660 vmx_load_host_state(to_vmx(vcpu
));
3661 vcpu
->arch
.efer
= efer
;
3662 if (efer
& EFER_LMA
) {
3663 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3666 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3668 msr
->data
= efer
& ~EFER_LME
;
3673 #ifdef CONFIG_X86_64
3675 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3679 vmx_segment_cache_clear(to_vmx(vcpu
));
3681 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3682 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3683 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3685 vmcs_write32(GUEST_TR_AR_BYTES
,
3686 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3687 | VMX_AR_TYPE_BUSY_64_TSS
);
3689 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3692 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3694 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3695 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3700 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3702 vpid_sync_context(vpid
);
3704 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3706 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3710 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3712 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3715 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3717 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3719 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3720 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3723 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3725 if (enable_ept
&& is_paging(vcpu
))
3726 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3727 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3730 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3732 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3734 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3735 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3738 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3740 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3742 if (!test_bit(VCPU_EXREG_PDPTR
,
3743 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3746 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3747 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3748 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3749 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3750 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3754 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3756 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3758 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3759 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3760 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3761 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3762 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3765 __set_bit(VCPU_EXREG_PDPTR
,
3766 (unsigned long *)&vcpu
->arch
.regs_avail
);
3767 __set_bit(VCPU_EXREG_PDPTR
,
3768 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3771 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3773 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3775 struct kvm_vcpu
*vcpu
)
3777 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3778 vmx_decache_cr3(vcpu
);
3779 if (!(cr0
& X86_CR0_PG
)) {
3780 /* From paging/starting to nonpaging */
3781 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3782 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3783 (CPU_BASED_CR3_LOAD_EXITING
|
3784 CPU_BASED_CR3_STORE_EXITING
));
3785 vcpu
->arch
.cr0
= cr0
;
3786 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3787 } else if (!is_paging(vcpu
)) {
3788 /* From nonpaging to paging */
3789 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3790 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3791 ~(CPU_BASED_CR3_LOAD_EXITING
|
3792 CPU_BASED_CR3_STORE_EXITING
));
3793 vcpu
->arch
.cr0
= cr0
;
3794 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3797 if (!(cr0
& X86_CR0_WP
))
3798 *hw_cr0
&= ~X86_CR0_WP
;
3801 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3803 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3804 unsigned long hw_cr0
;
3806 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3807 if (enable_unrestricted_guest
)
3808 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3810 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3812 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3815 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3819 #ifdef CONFIG_X86_64
3820 if (vcpu
->arch
.efer
& EFER_LME
) {
3821 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3823 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3829 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3831 if (!vcpu
->fpu_active
)
3832 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3834 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3835 vmcs_writel(GUEST_CR0
, hw_cr0
);
3836 vcpu
->arch
.cr0
= cr0
;
3838 /* depends on vcpu->arch.cr0 to be set to a new value */
3839 vmx
->emulation_required
= emulation_required(vcpu
);
3842 static u64
construct_eptp(unsigned long root_hpa
)
3846 /* TODO write the value reading from MSR */
3847 eptp
= VMX_EPT_DEFAULT_MT
|
3848 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3849 if (enable_ept_ad_bits
)
3850 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3851 eptp
|= (root_hpa
& PAGE_MASK
);
3856 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3858 unsigned long guest_cr3
;
3863 eptp
= construct_eptp(cr3
);
3864 vmcs_write64(EPT_POINTER
, eptp
);
3865 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3866 guest_cr3
= kvm_read_cr3(vcpu
);
3868 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3869 ept_load_pdptrs(vcpu
);
3872 vmx_flush_tlb(vcpu
);
3873 vmcs_writel(GUEST_CR3
, guest_cr3
);
3876 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3879 * Pass through host's Machine Check Enable value to hw_cr4, which
3880 * is in force while we are in guest mode. Do not let guests control
3881 * this bit, even if host CR4.MCE == 0.
3883 unsigned long hw_cr4
=
3884 (cr4_read_shadow() & X86_CR4_MCE
) |
3885 (cr4
& ~X86_CR4_MCE
) |
3886 (to_vmx(vcpu
)->rmode
.vm86_active
?
3887 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3889 if (cr4
& X86_CR4_VMXE
) {
3891 * To use VMXON (and later other VMX instructions), a guest
3892 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3893 * So basically the check on whether to allow nested VMX
3896 if (!nested_vmx_allowed(vcpu
))
3899 if (to_vmx(vcpu
)->nested
.vmxon
&&
3900 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3903 vcpu
->arch
.cr4
= cr4
;
3905 if (!is_paging(vcpu
)) {
3906 hw_cr4
&= ~X86_CR4_PAE
;
3907 hw_cr4
|= X86_CR4_PSE
;
3908 } else if (!(cr4
& X86_CR4_PAE
)) {
3909 hw_cr4
&= ~X86_CR4_PAE
;
3913 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
3915 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3916 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3917 * to be manually disabled when guest switches to non-paging
3920 * If !enable_unrestricted_guest, the CPU is always running
3921 * with CR0.PG=1 and CR4 needs to be modified.
3922 * If enable_unrestricted_guest, the CPU automatically
3923 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3925 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
3927 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3928 vmcs_writel(GUEST_CR4
, hw_cr4
);
3932 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3933 struct kvm_segment
*var
, int seg
)
3935 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3938 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3939 *var
= vmx
->rmode
.segs
[seg
];
3940 if (seg
== VCPU_SREG_TR
3941 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3943 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3944 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3947 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3948 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3949 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3950 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3951 var
->unusable
= (ar
>> 16) & 1;
3952 var
->type
= ar
& 15;
3953 var
->s
= (ar
>> 4) & 1;
3954 var
->dpl
= (ar
>> 5) & 3;
3956 * Some userspaces do not preserve unusable property. Since usable
3957 * segment has to be present according to VMX spec we can use present
3958 * property to amend userspace bug by making unusable segment always
3959 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3960 * segment as unusable.
3962 var
->present
= !var
->unusable
;
3963 var
->avl
= (ar
>> 12) & 1;
3964 var
->l
= (ar
>> 13) & 1;
3965 var
->db
= (ar
>> 14) & 1;
3966 var
->g
= (ar
>> 15) & 1;
3969 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3971 struct kvm_segment s
;
3973 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3974 vmx_get_segment(vcpu
, &s
, seg
);
3977 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3980 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3984 if (unlikely(vmx
->rmode
.vm86_active
))
3987 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3988 return VMX_AR_DPL(ar
);
3992 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3996 if (var
->unusable
|| !var
->present
)
3999 ar
= var
->type
& 15;
4000 ar
|= (var
->s
& 1) << 4;
4001 ar
|= (var
->dpl
& 3) << 5;
4002 ar
|= (var
->present
& 1) << 7;
4003 ar
|= (var
->avl
& 1) << 12;
4004 ar
|= (var
->l
& 1) << 13;
4005 ar
|= (var
->db
& 1) << 14;
4006 ar
|= (var
->g
& 1) << 15;
4012 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4013 struct kvm_segment
*var
, int seg
)
4015 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4016 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4018 vmx_segment_cache_clear(vmx
);
4020 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4021 vmx
->rmode
.segs
[seg
] = *var
;
4022 if (seg
== VCPU_SREG_TR
)
4023 vmcs_write16(sf
->selector
, var
->selector
);
4025 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4029 vmcs_writel(sf
->base
, var
->base
);
4030 vmcs_write32(sf
->limit
, var
->limit
);
4031 vmcs_write16(sf
->selector
, var
->selector
);
4034 * Fix the "Accessed" bit in AR field of segment registers for older
4036 * IA32 arch specifies that at the time of processor reset the
4037 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4038 * is setting it to 0 in the userland code. This causes invalid guest
4039 * state vmexit when "unrestricted guest" mode is turned on.
4040 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4041 * tree. Newer qemu binaries with that qemu fix would not need this
4044 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4045 var
->type
|= 0x1; /* Accessed */
4047 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4050 vmx
->emulation_required
= emulation_required(vcpu
);
4053 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4055 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4057 *db
= (ar
>> 14) & 1;
4058 *l
= (ar
>> 13) & 1;
4061 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4063 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4064 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4067 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4069 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4070 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4073 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4075 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4076 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4079 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4081 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4082 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4085 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4087 struct kvm_segment var
;
4090 vmx_get_segment(vcpu
, &var
, seg
);
4092 if (seg
== VCPU_SREG_CS
)
4094 ar
= vmx_segment_access_rights(&var
);
4096 if (var
.base
!= (var
.selector
<< 4))
4098 if (var
.limit
!= 0xffff)
4106 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4108 struct kvm_segment cs
;
4109 unsigned int cs_rpl
;
4111 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4112 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4116 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4120 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4121 if (cs
.dpl
> cs_rpl
)
4124 if (cs
.dpl
!= cs_rpl
)
4130 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4134 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4136 struct kvm_segment ss
;
4137 unsigned int ss_rpl
;
4139 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4140 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4144 if (ss
.type
!= 3 && ss
.type
!= 7)
4148 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4156 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4158 struct kvm_segment var
;
4161 vmx_get_segment(vcpu
, &var
, seg
);
4162 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4170 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4171 if (var
.dpl
< rpl
) /* DPL < RPL */
4175 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4181 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4183 struct kvm_segment tr
;
4185 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4189 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4191 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4199 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4201 struct kvm_segment ldtr
;
4203 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4207 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4217 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4219 struct kvm_segment cs
, ss
;
4221 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4222 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4224 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4225 (ss
.selector
& SEGMENT_RPL_MASK
));
4229 * Check if guest state is valid. Returns true if valid, false if
4231 * We assume that registers are always usable
4233 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4235 if (enable_unrestricted_guest
)
4238 /* real mode guest state checks */
4239 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4240 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4242 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4244 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4246 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4248 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4250 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4253 /* protected mode guest state checks */
4254 if (!cs_ss_rpl_check(vcpu
))
4256 if (!code_segment_valid(vcpu
))
4258 if (!stack_segment_valid(vcpu
))
4260 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4262 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4264 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4266 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4268 if (!tr_valid(vcpu
))
4270 if (!ldtr_valid(vcpu
))
4274 * - Add checks on RIP
4275 * - Add checks on RFLAGS
4281 static int init_rmode_tss(struct kvm
*kvm
)
4287 idx
= srcu_read_lock(&kvm
->srcu
);
4288 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4289 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4292 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4293 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4294 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4297 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4300 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4304 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4305 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4308 srcu_read_unlock(&kvm
->srcu
, idx
);
4312 static int init_rmode_identity_map(struct kvm
*kvm
)
4315 kvm_pfn_t identity_map_pfn
;
4321 /* Protect kvm->arch.ept_identity_pagetable_done. */
4322 mutex_lock(&kvm
->slots_lock
);
4324 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4327 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4329 r
= alloc_identity_pagetable(kvm
);
4333 idx
= srcu_read_lock(&kvm
->srcu
);
4334 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4337 /* Set up identity-mapping pagetable for EPT in real mode */
4338 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4339 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4340 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4341 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4342 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4346 kvm
->arch
.ept_identity_pagetable_done
= true;
4349 srcu_read_unlock(&kvm
->srcu
, idx
);
4352 mutex_unlock(&kvm
->slots_lock
);
4356 static void seg_setup(int seg
)
4358 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4361 vmcs_write16(sf
->selector
, 0);
4362 vmcs_writel(sf
->base
, 0);
4363 vmcs_write32(sf
->limit
, 0xffff);
4365 if (seg
== VCPU_SREG_CS
)
4366 ar
|= 0x08; /* code segment */
4368 vmcs_write32(sf
->ar_bytes
, ar
);
4371 static int alloc_apic_access_page(struct kvm
*kvm
)
4376 mutex_lock(&kvm
->slots_lock
);
4377 if (kvm
->arch
.apic_access_page_done
)
4379 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4380 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4384 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4385 if (is_error_page(page
)) {
4391 * Do not pin the page in memory, so that memory hot-unplug
4392 * is able to migrate it.
4395 kvm
->arch
.apic_access_page_done
= true;
4397 mutex_unlock(&kvm
->slots_lock
);
4401 static int alloc_identity_pagetable(struct kvm
*kvm
)
4403 /* Called with kvm->slots_lock held. */
4407 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4409 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4410 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4415 static int allocate_vpid(void)
4421 spin_lock(&vmx_vpid_lock
);
4422 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4423 if (vpid
< VMX_NR_VPIDS
)
4424 __set_bit(vpid
, vmx_vpid_bitmap
);
4427 spin_unlock(&vmx_vpid_lock
);
4431 static void free_vpid(int vpid
)
4433 if (!enable_vpid
|| vpid
== 0)
4435 spin_lock(&vmx_vpid_lock
);
4436 __clear_bit(vpid
, vmx_vpid_bitmap
);
4437 spin_unlock(&vmx_vpid_lock
);
4440 #define MSR_TYPE_R 1
4441 #define MSR_TYPE_W 2
4442 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4445 int f
= sizeof(unsigned long);
4447 if (!cpu_has_vmx_msr_bitmap())
4451 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4452 * have the write-low and read-high bitmap offsets the wrong way round.
4453 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4455 if (msr
<= 0x1fff) {
4456 if (type
& MSR_TYPE_R
)
4458 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4460 if (type
& MSR_TYPE_W
)
4462 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4464 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4466 if (type
& MSR_TYPE_R
)
4468 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4470 if (type
& MSR_TYPE_W
)
4472 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4477 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4480 int f
= sizeof(unsigned long);
4482 if (!cpu_has_vmx_msr_bitmap())
4486 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4487 * have the write-low and read-high bitmap offsets the wrong way round.
4488 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4490 if (msr
<= 0x1fff) {
4491 if (type
& MSR_TYPE_R
)
4493 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4495 if (type
& MSR_TYPE_W
)
4497 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4499 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4501 if (type
& MSR_TYPE_R
)
4503 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4505 if (type
& MSR_TYPE_W
)
4507 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4513 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4514 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4516 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4517 unsigned long *msr_bitmap_nested
,
4520 int f
= sizeof(unsigned long);
4522 if (!cpu_has_vmx_msr_bitmap()) {
4528 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4529 * have the write-low and read-high bitmap offsets the wrong way round.
4530 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4532 if (msr
<= 0x1fff) {
4533 if (type
& MSR_TYPE_R
&&
4534 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4536 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4538 if (type
& MSR_TYPE_W
&&
4539 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4541 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4543 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4545 if (type
& MSR_TYPE_R
&&
4546 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4548 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4550 if (type
& MSR_TYPE_W
&&
4551 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4553 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4558 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4561 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4562 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4563 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4564 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4567 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4569 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4571 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4575 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4577 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4579 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4583 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4585 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4587 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4591 static bool vmx_get_enable_apicv(void)
4593 return enable_apicv
;
4596 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4598 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4603 if (vmx
->nested
.pi_desc
&&
4604 vmx
->nested
.pi_pending
) {
4605 vmx
->nested
.pi_pending
= false;
4606 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4609 max_irr
= find_last_bit(
4610 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4615 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4620 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4621 kunmap(vmx
->nested
.virtual_apic_page
);
4623 status
= vmcs_read16(GUEST_INTR_STATUS
);
4624 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4626 status
|= (u8
)max_irr
;
4627 vmcs_write16(GUEST_INTR_STATUS
, status
);
4633 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4636 if (vcpu
->mode
== IN_GUEST_MODE
) {
4637 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4640 * Currently, we don't support urgent interrupt,
4641 * all interrupts are recognized as non-urgent
4642 * interrupt, so we cannot post interrupts when
4645 * If the vcpu is in guest mode, it means it is
4646 * running instead of being scheduled out and
4647 * waiting in the run queue, and that's the only
4648 * case when 'SN' is set currently, warning if
4651 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4653 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4654 POSTED_INTR_VECTOR
);
4661 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4664 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4666 if (is_guest_mode(vcpu
) &&
4667 vector
== vmx
->nested
.posted_intr_nv
) {
4668 /* the PIR and ON have been set by L1. */
4669 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4671 * If a posted intr is not recognized by hardware,
4672 * we will accomplish it in the next vmentry.
4674 vmx
->nested
.pi_pending
= true;
4675 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4681 * Send interrupt to vcpu via posted interrupt way.
4682 * 1. If target vcpu is running(non-root mode), send posted interrupt
4683 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4684 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4685 * interrupt from PIR in next vmentry.
4687 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4689 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4692 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4696 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4699 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4700 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4701 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4702 kvm_vcpu_kick(vcpu
);
4705 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4707 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4709 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4712 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4716 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4717 * will not change in the lifetime of the guest.
4718 * Note that host-state that does change is set elsewhere. E.g., host-state
4719 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4721 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4728 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4729 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4731 /* Save the most likely value for this task's CR4 in the VMCS. */
4732 cr4
= cr4_read_shadow();
4733 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4734 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4736 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4737 #ifdef CONFIG_X86_64
4739 * Load null selectors, so we can avoid reloading them in
4740 * __vmx_load_host_state(), in case userspace uses the null selectors
4741 * too (the expected case).
4743 vmcs_write16(HOST_DS_SELECTOR
, 0);
4744 vmcs_write16(HOST_ES_SELECTOR
, 0);
4746 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4747 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4749 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4750 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4752 native_store_idt(&dt
);
4753 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4754 vmx
->host_idt_base
= dt
.address
;
4756 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4758 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4759 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4760 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4761 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4763 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4764 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4765 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4769 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4771 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4773 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4774 if (is_guest_mode(&vmx
->vcpu
))
4775 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4776 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4777 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4780 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4782 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4784 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4785 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4786 return pin_based_exec_ctrl
;
4789 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4791 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4793 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4794 if (cpu_has_secondary_exec_ctrls()) {
4795 if (kvm_vcpu_apicv_active(vcpu
))
4796 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4797 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4798 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4800 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4801 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4802 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4805 if (cpu_has_vmx_msr_bitmap())
4806 vmx_set_msr_bitmap(vcpu
);
4809 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4811 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4813 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4814 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4816 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4817 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4818 #ifdef CONFIG_X86_64
4819 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4820 CPU_BASED_CR8_LOAD_EXITING
;
4824 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4825 CPU_BASED_CR3_LOAD_EXITING
|
4826 CPU_BASED_INVLPG_EXITING
;
4827 return exec_control
;
4830 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4832 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4833 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4834 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4836 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4838 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4839 enable_unrestricted_guest
= 0;
4840 /* Enable INVPCID for non-ept guests may cause performance regression. */
4841 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4843 if (!enable_unrestricted_guest
)
4844 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4846 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4847 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4848 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4849 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4850 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4851 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4853 We can NOT enable shadow_vmcs here because we don't have yet
4856 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4859 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4861 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4862 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4864 return exec_control
;
4867 static void ept_set_mmio_spte_mask(void)
4870 * EPT Misconfigurations can be generated if the value of bits 2:0
4871 * of an EPT paging-structure entry is 110b (write/execute).
4872 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4875 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4878 #define VMX_XSS_EXIT_BITMAP 0
4880 * Sets up the vmcs for emulated real mode.
4882 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4884 #ifdef CONFIG_X86_64
4890 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4891 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4893 if (enable_shadow_vmcs
) {
4894 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4895 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4897 if (cpu_has_vmx_msr_bitmap())
4898 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4900 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4903 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4905 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4907 if (cpu_has_secondary_exec_ctrls())
4908 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4909 vmx_secondary_exec_control(vmx
));
4911 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
4912 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4913 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4914 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4915 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4917 vmcs_write16(GUEST_INTR_STATUS
, 0);
4919 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4920 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4924 vmcs_write32(PLE_GAP
, ple_gap
);
4925 vmx
->ple_window
= ple_window
;
4926 vmx
->ple_window_dirty
= true;
4929 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4930 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4931 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4933 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4934 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4935 vmx_set_constant_host_state(vmx
);
4936 #ifdef CONFIG_X86_64
4937 rdmsrl(MSR_FS_BASE
, a
);
4938 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4939 rdmsrl(MSR_GS_BASE
, a
);
4940 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4942 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4943 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4946 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4947 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4948 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4949 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4950 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4952 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4953 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4955 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4956 u32 index
= vmx_msr_index
[i
];
4957 u32 data_low
, data_high
;
4960 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4962 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4964 vmx
->guest_msrs
[j
].index
= i
;
4965 vmx
->guest_msrs
[j
].data
= 0;
4966 vmx
->guest_msrs
[j
].mask
= -1ull;
4971 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4973 /* 22.2.1, 20.8.1 */
4974 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4976 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4977 set_cr4_guest_host_mask(vmx
);
4979 if (vmx_xsaves_supported())
4980 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4985 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4988 struct msr_data apic_base_msr
;
4991 vmx
->rmode
.vm86_active
= 0;
4993 vmx
->soft_vnmi_blocked
= 0;
4995 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4996 kvm_set_cr8(vcpu
, 0);
4999 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5000 MSR_IA32_APICBASE_ENABLE
;
5001 if (kvm_vcpu_is_reset_bsp(vcpu
))
5002 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5003 apic_base_msr
.host_initiated
= true;
5004 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5007 vmx_segment_cache_clear(vmx
);
5009 seg_setup(VCPU_SREG_CS
);
5010 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5011 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5013 seg_setup(VCPU_SREG_DS
);
5014 seg_setup(VCPU_SREG_ES
);
5015 seg_setup(VCPU_SREG_FS
);
5016 seg_setup(VCPU_SREG_GS
);
5017 seg_setup(VCPU_SREG_SS
);
5019 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5020 vmcs_writel(GUEST_TR_BASE
, 0);
5021 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5022 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5024 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5025 vmcs_writel(GUEST_LDTR_BASE
, 0);
5026 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5027 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5030 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5031 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5032 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5033 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5036 vmcs_writel(GUEST_RFLAGS
, 0x02);
5037 kvm_rip_write(vcpu
, 0xfff0);
5039 vmcs_writel(GUEST_GDTR_BASE
, 0);
5040 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5042 vmcs_writel(GUEST_IDTR_BASE
, 0);
5043 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5045 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5046 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5047 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5053 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5054 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5055 if (cpu_need_tpr_shadow(vcpu
))
5056 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5057 __pa(vcpu
->arch
.apic
->regs
));
5058 vmcs_write32(TPR_THRESHOLD
, 0);
5061 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5063 if (kvm_vcpu_apicv_active(vcpu
))
5064 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5067 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5069 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5070 vmx
->vcpu
.arch
.cr0
= cr0
;
5071 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5072 vmx_set_cr4(vcpu
, 0);
5073 vmx_set_efer(vcpu
, 0);
5074 vmx_fpu_activate(vcpu
);
5075 update_exception_bitmap(vcpu
);
5077 vpid_sync_context(vmx
->vpid
);
5081 * In nested virtualization, check if L1 asked to exit on external interrupts.
5082 * For most existing hypervisors, this will always return true.
5084 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5086 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5087 PIN_BASED_EXT_INTR_MASK
;
5091 * In nested virtualization, check if L1 has set
5092 * VM_EXIT_ACK_INTR_ON_EXIT
5094 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5096 return get_vmcs12(vcpu
)->vm_exit_controls
&
5097 VM_EXIT_ACK_INTR_ON_EXIT
;
5100 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5102 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5103 PIN_BASED_NMI_EXITING
;
5106 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5108 u32 cpu_based_vm_exec_control
;
5110 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5111 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5112 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5115 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5117 u32 cpu_based_vm_exec_control
;
5119 if (!cpu_has_virtual_nmis() ||
5120 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5121 enable_irq_window(vcpu
);
5125 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5126 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5127 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5130 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5132 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5134 int irq
= vcpu
->arch
.interrupt
.nr
;
5136 trace_kvm_inj_virq(irq
);
5138 ++vcpu
->stat
.irq_injections
;
5139 if (vmx
->rmode
.vm86_active
) {
5141 if (vcpu
->arch
.interrupt
.soft
)
5142 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5143 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5144 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5147 intr
= irq
| INTR_INFO_VALID_MASK
;
5148 if (vcpu
->arch
.interrupt
.soft
) {
5149 intr
|= INTR_TYPE_SOFT_INTR
;
5150 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5151 vmx
->vcpu
.arch
.event_exit_inst_len
);
5153 intr
|= INTR_TYPE_EXT_INTR
;
5154 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5157 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5159 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5161 if (is_guest_mode(vcpu
))
5164 if (!cpu_has_virtual_nmis()) {
5166 * Tracking the NMI-blocked state in software is built upon
5167 * finding the next open IRQ window. This, in turn, depends on
5168 * well-behaving guests: They have to keep IRQs disabled at
5169 * least as long as the NMI handler runs. Otherwise we may
5170 * cause NMI nesting, maybe breaking the guest. But as this is
5171 * highly unlikely, we can live with the residual risk.
5173 vmx
->soft_vnmi_blocked
= 1;
5174 vmx
->vnmi_blocked_time
= 0;
5177 ++vcpu
->stat
.nmi_injections
;
5178 vmx
->nmi_known_unmasked
= false;
5179 if (vmx
->rmode
.vm86_active
) {
5180 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5181 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5184 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5185 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5188 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5190 if (!cpu_has_virtual_nmis())
5191 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5192 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5194 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5197 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5199 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5201 if (!cpu_has_virtual_nmis()) {
5202 if (vmx
->soft_vnmi_blocked
!= masked
) {
5203 vmx
->soft_vnmi_blocked
= masked
;
5204 vmx
->vnmi_blocked_time
= 0;
5207 vmx
->nmi_known_unmasked
= !masked
;
5209 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5210 GUEST_INTR_STATE_NMI
);
5212 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5213 GUEST_INTR_STATE_NMI
);
5217 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5219 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5222 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5225 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5226 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5227 | GUEST_INTR_STATE_NMI
));
5230 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5232 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5233 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5234 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5235 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5238 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5242 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5246 kvm
->arch
.tss_addr
= addr
;
5247 return init_rmode_tss(kvm
);
5250 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5255 * Update instruction length as we may reinject the exception
5256 * from user space while in guest debugging mode.
5258 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5259 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5260 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5264 if (vcpu
->guest_debug
&
5265 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5282 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5283 int vec
, u32 err_code
)
5286 * Instruction with address size override prefix opcode 0x67
5287 * Cause the #SS fault with 0 error code in VM86 mode.
5289 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5290 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5291 if (vcpu
->arch
.halt_request
) {
5292 vcpu
->arch
.halt_request
= 0;
5293 return kvm_vcpu_halt(vcpu
);
5301 * Forward all other exceptions that are valid in real mode.
5302 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5303 * the required debugging infrastructure rework.
5305 kvm_queue_exception(vcpu
, vec
);
5310 * Trigger machine check on the host. We assume all the MSRs are already set up
5311 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5312 * We pass a fake environment to the machine check handler because we want
5313 * the guest to be always treated like user space, no matter what context
5314 * it used internally.
5316 static void kvm_machine_check(void)
5318 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5319 struct pt_regs regs
= {
5320 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5321 .flags
= X86_EFLAGS_IF
,
5324 do_machine_check(®s
, 0);
5328 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5330 /* already handled by vcpu_run */
5334 static int handle_exception(struct kvm_vcpu
*vcpu
)
5336 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5337 struct kvm_run
*kvm_run
= vcpu
->run
;
5338 u32 intr_info
, ex_no
, error_code
;
5339 unsigned long cr2
, rip
, dr6
;
5341 enum emulation_result er
;
5343 vect_info
= vmx
->idt_vectoring_info
;
5344 intr_info
= vmx
->exit_intr_info
;
5346 if (is_machine_check(intr_info
))
5347 return handle_machine_check(vcpu
);
5349 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5350 return 1; /* already handled by vmx_vcpu_run() */
5352 if (is_no_device(intr_info
)) {
5353 vmx_fpu_activate(vcpu
);
5357 if (is_invalid_opcode(intr_info
)) {
5358 if (is_guest_mode(vcpu
)) {
5359 kvm_queue_exception(vcpu
, UD_VECTOR
);
5362 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5363 if (er
!= EMULATE_DONE
)
5364 kvm_queue_exception(vcpu
, UD_VECTOR
);
5369 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5370 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5373 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5374 * MMIO, it is better to report an internal error.
5375 * See the comments in vmx_handle_exit.
5377 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5378 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5379 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5380 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5381 vcpu
->run
->internal
.ndata
= 3;
5382 vcpu
->run
->internal
.data
[0] = vect_info
;
5383 vcpu
->run
->internal
.data
[1] = intr_info
;
5384 vcpu
->run
->internal
.data
[2] = error_code
;
5388 if (is_page_fault(intr_info
)) {
5389 /* EPT won't cause page fault directly */
5391 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5392 trace_kvm_page_fault(cr2
, error_code
);
5394 if (kvm_event_needs_reinjection(vcpu
))
5395 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5396 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5399 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5401 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5402 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5406 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5409 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5410 if (!(vcpu
->guest_debug
&
5411 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5412 vcpu
->arch
.dr6
&= ~15;
5413 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5414 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5415 skip_emulated_instruction(vcpu
);
5417 kvm_queue_exception(vcpu
, DB_VECTOR
);
5420 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5421 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5425 * Update instruction length as we may reinject #BP from
5426 * user space while in guest debugging mode. Reading it for
5427 * #DB as well causes no harm, it is not used in that case.
5429 vmx
->vcpu
.arch
.event_exit_inst_len
=
5430 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5431 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5432 rip
= kvm_rip_read(vcpu
);
5433 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5434 kvm_run
->debug
.arch
.exception
= ex_no
;
5437 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5438 kvm_run
->ex
.exception
= ex_no
;
5439 kvm_run
->ex
.error_code
= error_code
;
5445 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5447 ++vcpu
->stat
.irq_exits
;
5451 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5453 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5457 static int handle_io(struct kvm_vcpu
*vcpu
)
5459 unsigned long exit_qualification
;
5460 int size
, in
, string
;
5463 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5464 string
= (exit_qualification
& 16) != 0;
5465 in
= (exit_qualification
& 8) != 0;
5467 ++vcpu
->stat
.io_exits
;
5470 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5472 port
= exit_qualification
>> 16;
5473 size
= (exit_qualification
& 7) + 1;
5474 skip_emulated_instruction(vcpu
);
5476 return kvm_fast_pio_out(vcpu
, size
, port
);
5480 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5483 * Patch in the VMCALL instruction:
5485 hypercall
[0] = 0x0f;
5486 hypercall
[1] = 0x01;
5487 hypercall
[2] = 0xc1;
5490 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5492 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5493 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5495 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5496 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5497 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5498 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5499 return (val
& always_on
) == always_on
;
5502 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5503 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5505 if (is_guest_mode(vcpu
)) {
5506 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5507 unsigned long orig_val
= val
;
5510 * We get here when L2 changed cr0 in a way that did not change
5511 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5512 * but did change L0 shadowed bits. So we first calculate the
5513 * effective cr0 value that L1 would like to write into the
5514 * hardware. It consists of the L2-owned bits from the new
5515 * value combined with the L1-owned bits from L1's guest_cr0.
5517 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5518 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5520 if (!nested_cr0_valid(vcpu
, val
))
5523 if (kvm_set_cr0(vcpu
, val
))
5525 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5528 if (to_vmx(vcpu
)->nested
.vmxon
&&
5529 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5531 return kvm_set_cr0(vcpu
, val
);
5535 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5537 if (is_guest_mode(vcpu
)) {
5538 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5539 unsigned long orig_val
= val
;
5541 /* analogously to handle_set_cr0 */
5542 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5543 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5544 if (kvm_set_cr4(vcpu
, val
))
5546 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5549 return kvm_set_cr4(vcpu
, val
);
5552 /* called to set cr0 as appropriate for clts instruction exit. */
5553 static void handle_clts(struct kvm_vcpu
*vcpu
)
5555 if (is_guest_mode(vcpu
)) {
5557 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5558 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5559 * just pretend it's off (also in arch.cr0 for fpu_activate).
5561 vmcs_writel(CR0_READ_SHADOW
,
5562 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5563 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5565 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5568 static int handle_cr(struct kvm_vcpu
*vcpu
)
5570 unsigned long exit_qualification
, val
;
5575 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5576 cr
= exit_qualification
& 15;
5577 reg
= (exit_qualification
>> 8) & 15;
5578 switch ((exit_qualification
>> 4) & 3) {
5579 case 0: /* mov to cr */
5580 val
= kvm_register_readl(vcpu
, reg
);
5581 trace_kvm_cr_write(cr
, val
);
5584 err
= handle_set_cr0(vcpu
, val
);
5585 kvm_complete_insn_gp(vcpu
, err
);
5588 err
= kvm_set_cr3(vcpu
, val
);
5589 kvm_complete_insn_gp(vcpu
, err
);
5592 err
= handle_set_cr4(vcpu
, val
);
5593 kvm_complete_insn_gp(vcpu
, err
);
5596 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5598 err
= kvm_set_cr8(vcpu
, cr8
);
5599 kvm_complete_insn_gp(vcpu
, err
);
5600 if (lapic_in_kernel(vcpu
))
5602 if (cr8_prev
<= cr8
)
5604 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5611 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5612 skip_emulated_instruction(vcpu
);
5613 vmx_fpu_activate(vcpu
);
5615 case 1: /*mov from cr*/
5618 val
= kvm_read_cr3(vcpu
);
5619 kvm_register_write(vcpu
, reg
, val
);
5620 trace_kvm_cr_read(cr
, val
);
5621 skip_emulated_instruction(vcpu
);
5624 val
= kvm_get_cr8(vcpu
);
5625 kvm_register_write(vcpu
, reg
, val
);
5626 trace_kvm_cr_read(cr
, val
);
5627 skip_emulated_instruction(vcpu
);
5632 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5633 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5634 kvm_lmsw(vcpu
, val
);
5636 skip_emulated_instruction(vcpu
);
5641 vcpu
->run
->exit_reason
= 0;
5642 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5643 (int)(exit_qualification
>> 4) & 3, cr
);
5647 static int handle_dr(struct kvm_vcpu
*vcpu
)
5649 unsigned long exit_qualification
;
5652 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5653 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5655 /* First, if DR does not exist, trigger UD */
5656 if (!kvm_require_dr(vcpu
, dr
))
5659 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5660 if (!kvm_require_cpl(vcpu
, 0))
5662 dr7
= vmcs_readl(GUEST_DR7
);
5665 * As the vm-exit takes precedence over the debug trap, we
5666 * need to emulate the latter, either for the host or the
5667 * guest debugging itself.
5669 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5670 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5671 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5672 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5673 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5674 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5677 vcpu
->arch
.dr6
&= ~15;
5678 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5679 kvm_queue_exception(vcpu
, DB_VECTOR
);
5684 if (vcpu
->guest_debug
== 0) {
5685 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5686 CPU_BASED_MOV_DR_EXITING
);
5689 * No more DR vmexits; force a reload of the debug registers
5690 * and reenter on this instruction. The next vmexit will
5691 * retrieve the full state of the debug registers.
5693 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5697 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5698 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5701 if (kvm_get_dr(vcpu
, dr
, &val
))
5703 kvm_register_write(vcpu
, reg
, val
);
5705 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5708 skip_emulated_instruction(vcpu
);
5712 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5714 return vcpu
->arch
.dr6
;
5717 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5721 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5723 get_debugreg(vcpu
->arch
.db
[0], 0);
5724 get_debugreg(vcpu
->arch
.db
[1], 1);
5725 get_debugreg(vcpu
->arch
.db
[2], 2);
5726 get_debugreg(vcpu
->arch
.db
[3], 3);
5727 get_debugreg(vcpu
->arch
.dr6
, 6);
5728 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5730 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5731 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5734 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5736 vmcs_writel(GUEST_DR7
, val
);
5739 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5741 kvm_emulate_cpuid(vcpu
);
5745 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5747 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5748 struct msr_data msr_info
;
5750 msr_info
.index
= ecx
;
5751 msr_info
.host_initiated
= false;
5752 if (vmx_get_msr(vcpu
, &msr_info
)) {
5753 trace_kvm_msr_read_ex(ecx
);
5754 kvm_inject_gp(vcpu
, 0);
5758 trace_kvm_msr_read(ecx
, msr_info
.data
);
5760 /* FIXME: handling of bits 32:63 of rax, rdx */
5761 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5762 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5763 skip_emulated_instruction(vcpu
);
5767 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5769 struct msr_data msr
;
5770 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5771 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5772 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5776 msr
.host_initiated
= false;
5777 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5778 trace_kvm_msr_write_ex(ecx
, data
);
5779 kvm_inject_gp(vcpu
, 0);
5783 trace_kvm_msr_write(ecx
, data
);
5784 skip_emulated_instruction(vcpu
);
5788 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5790 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5794 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5796 u32 cpu_based_vm_exec_control
;
5798 /* clear pending irq */
5799 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5800 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5801 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5803 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5805 ++vcpu
->stat
.irq_window_exits
;
5809 static int handle_halt(struct kvm_vcpu
*vcpu
)
5811 return kvm_emulate_halt(vcpu
);
5814 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5816 return kvm_emulate_hypercall(vcpu
);
5819 static int handle_invd(struct kvm_vcpu
*vcpu
)
5821 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5824 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5826 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5828 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5829 skip_emulated_instruction(vcpu
);
5833 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5837 err
= kvm_rdpmc(vcpu
);
5838 kvm_complete_insn_gp(vcpu
, err
);
5843 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5845 kvm_emulate_wbinvd(vcpu
);
5849 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5851 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5852 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5854 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5855 skip_emulated_instruction(vcpu
);
5859 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5861 skip_emulated_instruction(vcpu
);
5862 WARN(1, "this should never happen\n");
5866 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5868 skip_emulated_instruction(vcpu
);
5869 WARN(1, "this should never happen\n");
5873 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5875 if (likely(fasteoi
)) {
5876 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5877 int access_type
, offset
;
5879 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5880 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5882 * Sane guest uses MOV to write EOI, with written value
5883 * not cared. So make a short-circuit here by avoiding
5884 * heavy instruction emulation.
5886 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5887 (offset
== APIC_EOI
)) {
5888 kvm_lapic_set_eoi(vcpu
);
5889 skip_emulated_instruction(vcpu
);
5893 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5896 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5898 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5899 int vector
= exit_qualification
& 0xff;
5901 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5902 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5906 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5908 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5909 u32 offset
= exit_qualification
& 0xfff;
5911 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5912 kvm_apic_write_nodecode(vcpu
, offset
);
5916 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5918 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5919 unsigned long exit_qualification
;
5920 bool has_error_code
= false;
5923 int reason
, type
, idt_v
, idt_index
;
5925 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5926 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5927 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5929 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5931 reason
= (u32
)exit_qualification
>> 30;
5932 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5934 case INTR_TYPE_NMI_INTR
:
5935 vcpu
->arch
.nmi_injected
= false;
5936 vmx_set_nmi_mask(vcpu
, true);
5938 case INTR_TYPE_EXT_INTR
:
5939 case INTR_TYPE_SOFT_INTR
:
5940 kvm_clear_interrupt_queue(vcpu
);
5942 case INTR_TYPE_HARD_EXCEPTION
:
5943 if (vmx
->idt_vectoring_info
&
5944 VECTORING_INFO_DELIVER_CODE_MASK
) {
5945 has_error_code
= true;
5947 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5950 case INTR_TYPE_SOFT_EXCEPTION
:
5951 kvm_clear_exception_queue(vcpu
);
5957 tss_selector
= exit_qualification
;
5959 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5960 type
!= INTR_TYPE_EXT_INTR
&&
5961 type
!= INTR_TYPE_NMI_INTR
))
5962 skip_emulated_instruction(vcpu
);
5964 if (kvm_task_switch(vcpu
, tss_selector
,
5965 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5966 has_error_code
, error_code
) == EMULATE_FAIL
) {
5967 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5968 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5969 vcpu
->run
->internal
.ndata
= 0;
5974 * TODO: What about debug traps on tss switch?
5975 * Are we supposed to inject them and update dr6?
5981 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5983 unsigned long exit_qualification
;
5988 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5990 gla_validity
= (exit_qualification
>> 7) & 0x3;
5991 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5992 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5993 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5994 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5995 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5996 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5997 (long unsigned int)exit_qualification
);
5998 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5999 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6004 * EPT violation happened while executing iret from NMI,
6005 * "blocked by NMI" bit has to be set before next VM entry.
6006 * There are errata that may cause this bit to not be set:
6009 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6010 cpu_has_virtual_nmis() &&
6011 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6012 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6014 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6015 trace_kvm_page_fault(gpa
, exit_qualification
);
6017 /* It is a write fault? */
6018 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
6019 /* It is a fetch fault? */
6020 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6021 /* ept page table is present? */
6022 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
6024 vcpu
->arch
.exit_qualification
= exit_qualification
;
6026 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6029 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6034 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6035 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6036 skip_emulated_instruction(vcpu
);
6037 trace_kvm_fast_mmio(gpa
);
6041 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6042 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6043 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6046 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6047 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6049 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6052 /* It is the real ept misconfig */
6055 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6056 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6061 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6063 u32 cpu_based_vm_exec_control
;
6065 /* clear pending NMI */
6066 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6067 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6068 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6069 ++vcpu
->stat
.nmi_window_exits
;
6070 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6075 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6077 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6078 enum emulation_result err
= EMULATE_DONE
;
6081 bool intr_window_requested
;
6082 unsigned count
= 130;
6084 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6085 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6087 while (vmx
->emulation_required
&& count
-- != 0) {
6088 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6089 return handle_interrupt_window(&vmx
->vcpu
);
6091 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6094 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6096 if (err
== EMULATE_USER_EXIT
) {
6097 ++vcpu
->stat
.mmio_exits
;
6102 if (err
!= EMULATE_DONE
) {
6103 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6104 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6105 vcpu
->run
->internal
.ndata
= 0;
6109 if (vcpu
->arch
.halt_request
) {
6110 vcpu
->arch
.halt_request
= 0;
6111 ret
= kvm_vcpu_halt(vcpu
);
6115 if (signal_pending(current
))
6125 static int __grow_ple_window(int val
)
6127 if (ple_window_grow
< 1)
6130 val
= min(val
, ple_window_actual_max
);
6132 if (ple_window_grow
< ple_window
)
6133 val
*= ple_window_grow
;
6135 val
+= ple_window_grow
;
6140 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6145 if (modifier
< ple_window
)
6150 return max(val
, minimum
);
6153 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6156 int old
= vmx
->ple_window
;
6158 vmx
->ple_window
= __grow_ple_window(old
);
6160 if (vmx
->ple_window
!= old
)
6161 vmx
->ple_window_dirty
= true;
6163 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6166 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6168 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6169 int old
= vmx
->ple_window
;
6171 vmx
->ple_window
= __shrink_ple_window(old
,
6172 ple_window_shrink
, ple_window
);
6174 if (vmx
->ple_window
!= old
)
6175 vmx
->ple_window_dirty
= true;
6177 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6181 * ple_window_actual_max is computed to be one grow_ple_window() below
6182 * ple_window_max. (See __grow_ple_window for the reason.)
6183 * This prevents overflows, because ple_window_max is int.
6184 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6186 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6188 static void update_ple_window_actual_max(void)
6190 ple_window_actual_max
=
6191 __shrink_ple_window(max(ple_window_max
, ple_window
),
6192 ple_window_grow
, INT_MIN
);
6196 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6198 static void wakeup_handler(void)
6200 struct kvm_vcpu
*vcpu
;
6201 int cpu
= smp_processor_id();
6203 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6204 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6205 blocked_vcpu_list
) {
6206 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6208 if (pi_test_on(pi_desc
) == 1)
6209 kvm_vcpu_kick(vcpu
);
6211 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6214 static __init
int hardware_setup(void)
6216 int r
= -ENOMEM
, i
, msr
;
6218 rdmsrl_safe(MSR_EFER
, &host_efer
);
6220 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6221 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6223 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6224 if (!vmx_io_bitmap_a
)
6227 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6228 if (!vmx_io_bitmap_b
)
6231 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6232 if (!vmx_msr_bitmap_legacy
)
6235 vmx_msr_bitmap_legacy_x2apic
=
6236 (unsigned long *)__get_free_page(GFP_KERNEL
);
6237 if (!vmx_msr_bitmap_legacy_x2apic
)
6240 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6241 if (!vmx_msr_bitmap_longmode
)
6244 vmx_msr_bitmap_longmode_x2apic
=
6245 (unsigned long *)__get_free_page(GFP_KERNEL
);
6246 if (!vmx_msr_bitmap_longmode_x2apic
)
6250 vmx_msr_bitmap_nested
=
6251 (unsigned long *)__get_free_page(GFP_KERNEL
);
6252 if (!vmx_msr_bitmap_nested
)
6256 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6257 if (!vmx_vmread_bitmap
)
6260 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6261 if (!vmx_vmwrite_bitmap
)
6264 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6265 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6268 * Allow direct access to the PC debug port (it is often used for I/O
6269 * delays, but the vmexits simply slow things down).
6271 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6272 clear_bit(0x80, vmx_io_bitmap_a
);
6274 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6276 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6277 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6279 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6281 if (setup_vmcs_config(&vmcs_config
) < 0) {
6286 if (boot_cpu_has(X86_FEATURE_NX
))
6287 kvm_enable_efer_bits(EFER_NX
);
6289 if (!cpu_has_vmx_vpid())
6291 if (!cpu_has_vmx_shadow_vmcs())
6292 enable_shadow_vmcs
= 0;
6293 if (enable_shadow_vmcs
)
6294 init_vmcs_shadow_fields();
6296 if (!cpu_has_vmx_ept() ||
6297 !cpu_has_vmx_ept_4levels()) {
6299 enable_unrestricted_guest
= 0;
6300 enable_ept_ad_bits
= 0;
6303 if (!cpu_has_vmx_ept_ad_bits())
6304 enable_ept_ad_bits
= 0;
6306 if (!cpu_has_vmx_unrestricted_guest())
6307 enable_unrestricted_guest
= 0;
6309 if (!cpu_has_vmx_flexpriority())
6310 flexpriority_enabled
= 0;
6313 * set_apic_access_page_addr() is used to reload apic access
6314 * page upon invalidation. No need to do anything if not
6315 * using the APIC_ACCESS_ADDR VMCS field.
6317 if (!flexpriority_enabled
)
6318 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6320 if (!cpu_has_vmx_tpr_shadow())
6321 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6323 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6324 kvm_disable_largepages();
6326 if (!cpu_has_vmx_ple())
6329 if (!cpu_has_vmx_apicv())
6332 if (cpu_has_vmx_tsc_scaling()) {
6333 kvm_has_tsc_control
= true;
6334 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6335 kvm_tsc_scaling_ratio_frac_bits
= 48;
6338 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6339 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6340 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6341 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6342 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6343 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6344 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6346 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6347 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6348 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6349 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6351 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6353 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6354 vmx_disable_intercept_msr_read_x2apic(msr
);
6356 /* According SDM, in x2apic mode, the whole id reg is used. But in
6357 * KVM, it only use the highest eight bits. Need to intercept it */
6358 vmx_enable_intercept_msr_read_x2apic(0x802);
6360 vmx_enable_intercept_msr_read_x2apic(0x839);
6362 vmx_disable_intercept_msr_write_x2apic(0x808);
6364 vmx_disable_intercept_msr_write_x2apic(0x80b);
6366 vmx_disable_intercept_msr_write_x2apic(0x83f);
6369 kvm_mmu_set_mask_ptes(0ull,
6370 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6371 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6372 0ull, VMX_EPT_EXECUTABLE_MASK
);
6373 ept_set_mmio_spte_mask();
6378 update_ple_window_actual_max();
6381 * Only enable PML when hardware supports PML feature, and both EPT
6382 * and EPT A/D bit features are enabled -- PML depends on them to work.
6384 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6388 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6389 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6390 kvm_x86_ops
->flush_log_dirty
= NULL
;
6391 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6394 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6396 return alloc_kvm_area();
6399 free_page((unsigned long)vmx_vmwrite_bitmap
);
6401 free_page((unsigned long)vmx_vmread_bitmap
);
6404 free_page((unsigned long)vmx_msr_bitmap_nested
);
6406 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6408 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6410 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6412 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6414 free_page((unsigned long)vmx_io_bitmap_b
);
6416 free_page((unsigned long)vmx_io_bitmap_a
);
6421 static __exit
void hardware_unsetup(void)
6423 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6424 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6425 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6426 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6427 free_page((unsigned long)vmx_io_bitmap_b
);
6428 free_page((unsigned long)vmx_io_bitmap_a
);
6429 free_page((unsigned long)vmx_vmwrite_bitmap
);
6430 free_page((unsigned long)vmx_vmread_bitmap
);
6432 free_page((unsigned long)vmx_msr_bitmap_nested
);
6438 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6439 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6441 static int handle_pause(struct kvm_vcpu
*vcpu
)
6444 grow_ple_window(vcpu
);
6446 skip_emulated_instruction(vcpu
);
6447 kvm_vcpu_on_spin(vcpu
);
6452 static int handle_nop(struct kvm_vcpu
*vcpu
)
6454 skip_emulated_instruction(vcpu
);
6458 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6460 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6461 return handle_nop(vcpu
);
6464 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6469 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6471 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6472 return handle_nop(vcpu
);
6476 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6477 * We could reuse a single VMCS for all the L2 guests, but we also want the
6478 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6479 * allows keeping them loaded on the processor, and in the future will allow
6480 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6481 * every entry if they never change.
6482 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6483 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6485 * The following functions allocate and free a vmcs02 in this pool.
6488 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6489 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6491 struct vmcs02_list
*item
;
6492 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6493 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6494 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6495 return &item
->vmcs02
;
6498 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6499 /* Recycle the least recently used VMCS. */
6500 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6501 struct vmcs02_list
, list
);
6502 item
->vmptr
= vmx
->nested
.current_vmptr
;
6503 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6504 return &item
->vmcs02
;
6507 /* Create a new VMCS */
6508 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6511 item
->vmcs02
.vmcs
= alloc_vmcs();
6512 if (!item
->vmcs02
.vmcs
) {
6516 loaded_vmcs_init(&item
->vmcs02
);
6517 item
->vmptr
= vmx
->nested
.current_vmptr
;
6518 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6519 vmx
->nested
.vmcs02_num
++;
6520 return &item
->vmcs02
;
6523 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6524 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6526 struct vmcs02_list
*item
;
6527 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6528 if (item
->vmptr
== vmptr
) {
6529 free_loaded_vmcs(&item
->vmcs02
);
6530 list_del(&item
->list
);
6532 vmx
->nested
.vmcs02_num
--;
6538 * Free all VMCSs saved for this vcpu, except the one pointed by
6539 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6540 * must be &vmx->vmcs01.
6542 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6544 struct vmcs02_list
*item
, *n
;
6546 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6547 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6549 * Something will leak if the above WARN triggers. Better than
6552 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6555 free_loaded_vmcs(&item
->vmcs02
);
6556 list_del(&item
->list
);
6558 vmx
->nested
.vmcs02_num
--;
6563 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6564 * set the success or error code of an emulated VMX instruction, as specified
6565 * by Vol 2B, VMX Instruction Reference, "Conventions".
6567 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6569 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6570 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6571 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6574 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6576 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6577 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6578 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6582 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6583 u32 vm_instruction_error
)
6585 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6587 * failValid writes the error number to the current VMCS, which
6588 * can't be done there isn't a current VMCS.
6590 nested_vmx_failInvalid(vcpu
);
6593 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6594 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6595 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6597 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6599 * We don't need to force a shadow sync because
6600 * VM_INSTRUCTION_ERROR is not shadowed
6604 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6606 /* TODO: not to reset guest simply here. */
6607 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6608 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6611 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6613 struct vcpu_vmx
*vmx
=
6614 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6616 vmx
->nested
.preemption_timer_expired
= true;
6617 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6618 kvm_vcpu_kick(&vmx
->vcpu
);
6620 return HRTIMER_NORESTART
;
6624 * Decode the memory-address operand of a vmx instruction, as recorded on an
6625 * exit caused by such an instruction (run by a guest hypervisor).
6626 * On success, returns 0. When the operand is invalid, returns 1 and throws
6629 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6630 unsigned long exit_qualification
,
6631 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6635 struct kvm_segment s
;
6638 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6639 * Execution", on an exit, vmx_instruction_info holds most of the
6640 * addressing components of the operand. Only the displacement part
6641 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6642 * For how an actual address is calculated from all these components,
6643 * refer to Vol. 1, "Operand Addressing".
6645 int scaling
= vmx_instruction_info
& 3;
6646 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6647 bool is_reg
= vmx_instruction_info
& (1u << 10);
6648 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6649 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6650 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6651 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6652 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6655 kvm_queue_exception(vcpu
, UD_VECTOR
);
6659 /* Addr = segment_base + offset */
6660 /* offset = base + [index * scale] + displacement */
6661 off
= exit_qualification
; /* holds the displacement */
6663 off
+= kvm_register_read(vcpu
, base_reg
);
6665 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6666 vmx_get_segment(vcpu
, &s
, seg_reg
);
6667 *ret
= s
.base
+ off
;
6669 if (addr_size
== 1) /* 32 bit */
6672 /* Checks for #GP/#SS exceptions. */
6674 if (is_protmode(vcpu
)) {
6675 /* Protected mode: apply checks for segment validity in the
6677 * - segment type check (#GP(0) may be thrown)
6678 * - usability check (#GP(0)/#SS(0))
6679 * - limit check (#GP(0)/#SS(0))
6682 /* #GP(0) if the destination operand is located in a
6683 * read-only data segment or any code segment.
6685 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6687 /* #GP(0) if the source operand is located in an
6688 * execute-only code segment
6690 exn
= ((s
.type
& 0xa) == 8);
6693 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6696 if (is_long_mode(vcpu
)) {
6697 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6698 * non-canonical form. This is an only check for long mode.
6700 exn
= is_noncanonical_address(*ret
);
6701 } else if (is_protmode(vcpu
)) {
6702 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6704 exn
= (s
.unusable
!= 0);
6705 /* Protected mode: #GP(0)/#SS(0) if the memory
6706 * operand is outside the segment limit.
6708 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6711 kvm_queue_exception_e(vcpu
,
6712 seg_reg
== VCPU_SREG_SS
?
6713 SS_VECTOR
: GP_VECTOR
,
6722 * This function performs the various checks including
6723 * - if it's 4KB aligned
6724 * - No bits beyond the physical address width are set
6725 * - Returns 0 on success or else 1
6726 * (Intel SDM Section 30.3)
6728 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6733 struct x86_exception e
;
6735 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6736 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6738 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6739 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6742 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6743 sizeof(vmptr
), &e
)) {
6744 kvm_inject_page_fault(vcpu
, &e
);
6748 switch (exit_reason
) {
6749 case EXIT_REASON_VMON
:
6752 * The first 4 bytes of VMXON region contain the supported
6753 * VMCS revision identifier
6755 * Note - IA32_VMX_BASIC[48] will never be 1
6756 * for the nested case;
6757 * which replaces physical address width with 32
6760 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6761 nested_vmx_failInvalid(vcpu
);
6762 skip_emulated_instruction(vcpu
);
6766 page
= nested_get_page(vcpu
, vmptr
);
6768 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6769 nested_vmx_failInvalid(vcpu
);
6771 skip_emulated_instruction(vcpu
);
6775 vmx
->nested
.vmxon_ptr
= vmptr
;
6777 case EXIT_REASON_VMCLEAR
:
6778 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6779 nested_vmx_failValid(vcpu
,
6780 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6781 skip_emulated_instruction(vcpu
);
6785 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6786 nested_vmx_failValid(vcpu
,
6787 VMXERR_VMCLEAR_VMXON_POINTER
);
6788 skip_emulated_instruction(vcpu
);
6792 case EXIT_REASON_VMPTRLD
:
6793 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6794 nested_vmx_failValid(vcpu
,
6795 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6796 skip_emulated_instruction(vcpu
);
6800 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6801 nested_vmx_failValid(vcpu
,
6802 VMXERR_VMCLEAR_VMXON_POINTER
);
6803 skip_emulated_instruction(vcpu
);
6808 return 1; /* shouldn't happen */
6817 * Emulate the VMXON instruction.
6818 * Currently, we just remember that VMX is active, and do not save or even
6819 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6820 * do not currently need to store anything in that guest-allocated memory
6821 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6822 * argument is different from the VMXON pointer (which the spec says they do).
6824 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6826 struct kvm_segment cs
;
6827 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6828 struct vmcs
*shadow_vmcs
;
6829 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6830 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6832 /* The Intel VMX Instruction Reference lists a bunch of bits that
6833 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6834 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6835 * Otherwise, we should fail with #UD. We test these now:
6837 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6838 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6839 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6840 kvm_queue_exception(vcpu
, UD_VECTOR
);
6844 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6845 if (is_long_mode(vcpu
) && !cs
.l
) {
6846 kvm_queue_exception(vcpu
, UD_VECTOR
);
6850 if (vmx_get_cpl(vcpu
)) {
6851 kvm_inject_gp(vcpu
, 0);
6855 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6858 if (vmx
->nested
.vmxon
) {
6859 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6860 skip_emulated_instruction(vcpu
);
6864 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6865 != VMXON_NEEDED_FEATURES
) {
6866 kvm_inject_gp(vcpu
, 0);
6870 if (enable_shadow_vmcs
) {
6871 shadow_vmcs
= alloc_vmcs();
6874 /* mark vmcs as shadow */
6875 shadow_vmcs
->revision_id
|= (1u << 31);
6876 /* init shadow vmcs */
6877 vmcs_clear(shadow_vmcs
);
6878 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6881 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6882 vmx
->nested
.vmcs02_num
= 0;
6884 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6886 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6888 vmx
->nested
.vmxon
= true;
6890 skip_emulated_instruction(vcpu
);
6891 nested_vmx_succeed(vcpu
);
6896 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6897 * for running VMX instructions (except VMXON, whose prerequisites are
6898 * slightly different). It also specifies what exception to inject otherwise.
6900 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6902 struct kvm_segment cs
;
6903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6905 if (!vmx
->nested
.vmxon
) {
6906 kvm_queue_exception(vcpu
, UD_VECTOR
);
6910 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6911 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6912 (is_long_mode(vcpu
) && !cs
.l
)) {
6913 kvm_queue_exception(vcpu
, UD_VECTOR
);
6917 if (vmx_get_cpl(vcpu
)) {
6918 kvm_inject_gp(vcpu
, 0);
6925 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6927 if (vmx
->nested
.current_vmptr
== -1ull)
6930 /* current_vmptr and current_vmcs12 are always set/reset together */
6931 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6934 if (enable_shadow_vmcs
) {
6935 /* copy to memory all shadowed fields in case
6936 they were modified */
6937 copy_shadow_to_vmcs12(vmx
);
6938 vmx
->nested
.sync_shadow_vmcs
= false;
6939 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6940 SECONDARY_EXEC_SHADOW_VMCS
);
6941 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6943 vmx
->nested
.posted_intr_nv
= -1;
6944 kunmap(vmx
->nested
.current_vmcs12_page
);
6945 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6946 vmx
->nested
.current_vmptr
= -1ull;
6947 vmx
->nested
.current_vmcs12
= NULL
;
6951 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6952 * just stops using VMX.
6954 static void free_nested(struct vcpu_vmx
*vmx
)
6956 if (!vmx
->nested
.vmxon
)
6959 vmx
->nested
.vmxon
= false;
6960 free_vpid(vmx
->nested
.vpid02
);
6961 nested_release_vmcs12(vmx
);
6962 if (enable_shadow_vmcs
)
6963 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6964 /* Unpin physical memory we referred to in current vmcs02 */
6965 if (vmx
->nested
.apic_access_page
) {
6966 nested_release_page(vmx
->nested
.apic_access_page
);
6967 vmx
->nested
.apic_access_page
= NULL
;
6969 if (vmx
->nested
.virtual_apic_page
) {
6970 nested_release_page(vmx
->nested
.virtual_apic_page
);
6971 vmx
->nested
.virtual_apic_page
= NULL
;
6973 if (vmx
->nested
.pi_desc_page
) {
6974 kunmap(vmx
->nested
.pi_desc_page
);
6975 nested_release_page(vmx
->nested
.pi_desc_page
);
6976 vmx
->nested
.pi_desc_page
= NULL
;
6977 vmx
->nested
.pi_desc
= NULL
;
6980 nested_free_all_saved_vmcss(vmx
);
6983 /* Emulate the VMXOFF instruction */
6984 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6986 if (!nested_vmx_check_permission(vcpu
))
6988 free_nested(to_vmx(vcpu
));
6989 skip_emulated_instruction(vcpu
);
6990 nested_vmx_succeed(vcpu
);
6994 /* Emulate the VMCLEAR instruction */
6995 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6997 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6999 struct vmcs12
*vmcs12
;
7002 if (!nested_vmx_check_permission(vcpu
))
7005 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7008 if (vmptr
== vmx
->nested
.current_vmptr
)
7009 nested_release_vmcs12(vmx
);
7011 page
= nested_get_page(vcpu
, vmptr
);
7014 * For accurate processor emulation, VMCLEAR beyond available
7015 * physical memory should do nothing at all. However, it is
7016 * possible that a nested vmx bug, not a guest hypervisor bug,
7017 * resulted in this case, so let's shut down before doing any
7020 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7023 vmcs12
= kmap(page
);
7024 vmcs12
->launch_state
= 0;
7026 nested_release_page(page
);
7028 nested_free_vmcs02(vmx
, vmptr
);
7030 skip_emulated_instruction(vcpu
);
7031 nested_vmx_succeed(vcpu
);
7035 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7037 /* Emulate the VMLAUNCH instruction */
7038 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7040 return nested_vmx_run(vcpu
, true);
7043 /* Emulate the VMRESUME instruction */
7044 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7047 return nested_vmx_run(vcpu
, false);
7050 enum vmcs_field_type
{
7051 VMCS_FIELD_TYPE_U16
= 0,
7052 VMCS_FIELD_TYPE_U64
= 1,
7053 VMCS_FIELD_TYPE_U32
= 2,
7054 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7057 static inline int vmcs_field_type(unsigned long field
)
7059 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7060 return VMCS_FIELD_TYPE_U32
;
7061 return (field
>> 13) & 0x3 ;
7064 static inline int vmcs_field_readonly(unsigned long field
)
7066 return (((field
>> 10) & 0x3) == 1);
7070 * Read a vmcs12 field. Since these can have varying lengths and we return
7071 * one type, we chose the biggest type (u64) and zero-extend the return value
7072 * to that size. Note that the caller, handle_vmread, might need to use only
7073 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7074 * 64-bit fields are to be returned).
7076 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7077 unsigned long field
, u64
*ret
)
7079 short offset
= vmcs_field_to_offset(field
);
7085 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7087 switch (vmcs_field_type(field
)) {
7088 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7089 *ret
= *((natural_width
*)p
);
7091 case VMCS_FIELD_TYPE_U16
:
7094 case VMCS_FIELD_TYPE_U32
:
7097 case VMCS_FIELD_TYPE_U64
:
7107 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7108 unsigned long field
, u64 field_value
){
7109 short offset
= vmcs_field_to_offset(field
);
7110 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7114 switch (vmcs_field_type(field
)) {
7115 case VMCS_FIELD_TYPE_U16
:
7116 *(u16
*)p
= field_value
;
7118 case VMCS_FIELD_TYPE_U32
:
7119 *(u32
*)p
= field_value
;
7121 case VMCS_FIELD_TYPE_U64
:
7122 *(u64
*)p
= field_value
;
7124 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7125 *(natural_width
*)p
= field_value
;
7134 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7137 unsigned long field
;
7139 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7140 const unsigned long *fields
= shadow_read_write_fields
;
7141 const int num_fields
= max_shadow_read_write_fields
;
7145 vmcs_load(shadow_vmcs
);
7147 for (i
= 0; i
< num_fields
; i
++) {
7149 switch (vmcs_field_type(field
)) {
7150 case VMCS_FIELD_TYPE_U16
:
7151 field_value
= vmcs_read16(field
);
7153 case VMCS_FIELD_TYPE_U32
:
7154 field_value
= vmcs_read32(field
);
7156 case VMCS_FIELD_TYPE_U64
:
7157 field_value
= vmcs_read64(field
);
7159 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7160 field_value
= vmcs_readl(field
);
7166 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7169 vmcs_clear(shadow_vmcs
);
7170 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7175 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7177 const unsigned long *fields
[] = {
7178 shadow_read_write_fields
,
7179 shadow_read_only_fields
7181 const int max_fields
[] = {
7182 max_shadow_read_write_fields
,
7183 max_shadow_read_only_fields
7186 unsigned long field
;
7187 u64 field_value
= 0;
7188 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7190 vmcs_load(shadow_vmcs
);
7192 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7193 for (i
= 0; i
< max_fields
[q
]; i
++) {
7194 field
= fields
[q
][i
];
7195 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7197 switch (vmcs_field_type(field
)) {
7198 case VMCS_FIELD_TYPE_U16
:
7199 vmcs_write16(field
, (u16
)field_value
);
7201 case VMCS_FIELD_TYPE_U32
:
7202 vmcs_write32(field
, (u32
)field_value
);
7204 case VMCS_FIELD_TYPE_U64
:
7205 vmcs_write64(field
, (u64
)field_value
);
7207 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7208 vmcs_writel(field
, (long)field_value
);
7217 vmcs_clear(shadow_vmcs
);
7218 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7222 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7223 * used before) all generate the same failure when it is missing.
7225 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7227 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7228 if (vmx
->nested
.current_vmptr
== -1ull) {
7229 nested_vmx_failInvalid(vcpu
);
7230 skip_emulated_instruction(vcpu
);
7236 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7238 unsigned long field
;
7240 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7241 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7244 if (!nested_vmx_check_permission(vcpu
) ||
7245 !nested_vmx_check_vmcs12(vcpu
))
7248 /* Decode instruction info and find the field to read */
7249 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7250 /* Read the field, zero-extended to a u64 field_value */
7251 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7252 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7253 skip_emulated_instruction(vcpu
);
7257 * Now copy part of this value to register or memory, as requested.
7258 * Note that the number of bits actually copied is 32 or 64 depending
7259 * on the guest's mode (32 or 64 bit), not on the given field's length.
7261 if (vmx_instruction_info
& (1u << 10)) {
7262 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7265 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7266 vmx_instruction_info
, true, &gva
))
7268 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7269 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7270 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7273 nested_vmx_succeed(vcpu
);
7274 skip_emulated_instruction(vcpu
);
7279 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7281 unsigned long field
;
7283 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7284 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7285 /* The value to write might be 32 or 64 bits, depending on L1's long
7286 * mode, and eventually we need to write that into a field of several
7287 * possible lengths. The code below first zero-extends the value to 64
7288 * bit (field_value), and then copies only the appropriate number of
7289 * bits into the vmcs12 field.
7291 u64 field_value
= 0;
7292 struct x86_exception e
;
7294 if (!nested_vmx_check_permission(vcpu
) ||
7295 !nested_vmx_check_vmcs12(vcpu
))
7298 if (vmx_instruction_info
& (1u << 10))
7299 field_value
= kvm_register_readl(vcpu
,
7300 (((vmx_instruction_info
) >> 3) & 0xf));
7302 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7303 vmx_instruction_info
, false, &gva
))
7305 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7306 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7307 kvm_inject_page_fault(vcpu
, &e
);
7313 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7314 if (vmcs_field_readonly(field
)) {
7315 nested_vmx_failValid(vcpu
,
7316 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7317 skip_emulated_instruction(vcpu
);
7321 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7322 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7323 skip_emulated_instruction(vcpu
);
7327 nested_vmx_succeed(vcpu
);
7328 skip_emulated_instruction(vcpu
);
7332 /* Emulate the VMPTRLD instruction */
7333 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7335 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7338 if (!nested_vmx_check_permission(vcpu
))
7341 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7344 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7345 struct vmcs12
*new_vmcs12
;
7347 page
= nested_get_page(vcpu
, vmptr
);
7349 nested_vmx_failInvalid(vcpu
);
7350 skip_emulated_instruction(vcpu
);
7353 new_vmcs12
= kmap(page
);
7354 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7356 nested_release_page_clean(page
);
7357 nested_vmx_failValid(vcpu
,
7358 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7359 skip_emulated_instruction(vcpu
);
7363 nested_release_vmcs12(vmx
);
7364 vmx
->nested
.current_vmptr
= vmptr
;
7365 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7366 vmx
->nested
.current_vmcs12_page
= page
;
7367 if (enable_shadow_vmcs
) {
7368 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7369 SECONDARY_EXEC_SHADOW_VMCS
);
7370 vmcs_write64(VMCS_LINK_POINTER
,
7371 __pa(vmx
->nested
.current_shadow_vmcs
));
7372 vmx
->nested
.sync_shadow_vmcs
= true;
7376 nested_vmx_succeed(vcpu
);
7377 skip_emulated_instruction(vcpu
);
7381 /* Emulate the VMPTRST instruction */
7382 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7384 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7385 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7387 struct x86_exception e
;
7389 if (!nested_vmx_check_permission(vcpu
))
7392 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7393 vmx_instruction_info
, true, &vmcs_gva
))
7395 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7396 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7397 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7399 kvm_inject_page_fault(vcpu
, &e
);
7402 nested_vmx_succeed(vcpu
);
7403 skip_emulated_instruction(vcpu
);
7407 /* Emulate the INVEPT instruction */
7408 static int handle_invept(struct kvm_vcpu
*vcpu
)
7410 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7411 u32 vmx_instruction_info
, types
;
7414 struct x86_exception e
;
7419 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7420 SECONDARY_EXEC_ENABLE_EPT
) ||
7421 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7422 kvm_queue_exception(vcpu
, UD_VECTOR
);
7426 if (!nested_vmx_check_permission(vcpu
))
7429 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7430 kvm_queue_exception(vcpu
, UD_VECTOR
);
7434 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7435 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7437 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7439 if (!(types
& (1UL << type
))) {
7440 nested_vmx_failValid(vcpu
,
7441 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7442 skip_emulated_instruction(vcpu
);
7446 /* According to the Intel VMX instruction reference, the memory
7447 * operand is read even if it isn't needed (e.g., for type==global)
7449 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7450 vmx_instruction_info
, false, &gva
))
7452 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7453 sizeof(operand
), &e
)) {
7454 kvm_inject_page_fault(vcpu
, &e
);
7459 case VMX_EPT_EXTENT_GLOBAL
:
7460 kvm_mmu_sync_roots(vcpu
);
7461 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7462 nested_vmx_succeed(vcpu
);
7465 /* Trap single context invalidation invept calls */
7470 skip_emulated_instruction(vcpu
);
7474 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7477 u32 vmx_instruction_info
;
7478 unsigned long type
, types
;
7480 struct x86_exception e
;
7483 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7484 SECONDARY_EXEC_ENABLE_VPID
) ||
7485 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7486 kvm_queue_exception(vcpu
, UD_VECTOR
);
7490 if (!nested_vmx_check_permission(vcpu
))
7493 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7494 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7496 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7498 if (!(types
& (1UL << type
))) {
7499 nested_vmx_failValid(vcpu
,
7500 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7501 skip_emulated_instruction(vcpu
);
7505 /* according to the intel vmx instruction reference, the memory
7506 * operand is read even if it isn't needed (e.g., for type==global)
7508 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7509 vmx_instruction_info
, false, &gva
))
7511 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7513 kvm_inject_page_fault(vcpu
, &e
);
7518 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7520 * Old versions of KVM use the single-context version so we
7521 * have to support it; just treat it the same as all-context.
7523 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7524 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7525 nested_vmx_succeed(vcpu
);
7528 /* Trap individual address invalidation invvpid calls */
7533 skip_emulated_instruction(vcpu
);
7537 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7539 unsigned long exit_qualification
;
7541 trace_kvm_pml_full(vcpu
->vcpu_id
);
7543 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7546 * PML buffer FULL happened while executing iret from NMI,
7547 * "blocked by NMI" bit has to be set before next VM entry.
7549 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7550 cpu_has_virtual_nmis() &&
7551 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7552 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7553 GUEST_INTR_STATE_NMI
);
7556 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7557 * here.., and there's no userspace involvement needed for PML.
7562 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7564 /* we never catch pcommit instruct for L1 guest. */
7570 * The exit handlers return 1 if the exit was handled fully and guest execution
7571 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7572 * to be done to userspace and return 0.
7574 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7575 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7576 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7577 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7578 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7579 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7580 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7581 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7582 [EXIT_REASON_CPUID
] = handle_cpuid
,
7583 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7584 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7585 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7586 [EXIT_REASON_HLT
] = handle_halt
,
7587 [EXIT_REASON_INVD
] = handle_invd
,
7588 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7589 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7590 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7591 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7592 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7593 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7594 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7595 [EXIT_REASON_VMREAD
] = handle_vmread
,
7596 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7597 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7598 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7599 [EXIT_REASON_VMON
] = handle_vmon
,
7600 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7601 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7602 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7603 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7604 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7605 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7606 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7607 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7608 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7609 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7610 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7611 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7612 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7613 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7614 [EXIT_REASON_INVEPT
] = handle_invept
,
7615 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7616 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7617 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7618 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7619 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7622 static const int kvm_vmx_max_exit_handlers
=
7623 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7625 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7626 struct vmcs12
*vmcs12
)
7628 unsigned long exit_qualification
;
7629 gpa_t bitmap
, last_bitmap
;
7634 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7635 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7637 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7639 port
= exit_qualification
>> 16;
7640 size
= (exit_qualification
& 7) + 1;
7642 last_bitmap
= (gpa_t
)-1;
7647 bitmap
= vmcs12
->io_bitmap_a
;
7648 else if (port
< 0x10000)
7649 bitmap
= vmcs12
->io_bitmap_b
;
7652 bitmap
+= (port
& 0x7fff) / 8;
7654 if (last_bitmap
!= bitmap
)
7655 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7657 if (b
& (1 << (port
& 7)))
7662 last_bitmap
= bitmap
;
7669 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7670 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7671 * disinterest in the current event (read or write a specific MSR) by using an
7672 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7674 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7675 struct vmcs12
*vmcs12
, u32 exit_reason
)
7677 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7680 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7684 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7685 * for the four combinations of read/write and low/high MSR numbers.
7686 * First we need to figure out which of the four to use:
7688 bitmap
= vmcs12
->msr_bitmap
;
7689 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7691 if (msr_index
>= 0xc0000000) {
7692 msr_index
-= 0xc0000000;
7696 /* Then read the msr_index'th bit from this bitmap: */
7697 if (msr_index
< 1024*8) {
7699 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7701 return 1 & (b
>> (msr_index
& 7));
7703 return true; /* let L1 handle the wrong parameter */
7707 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7708 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7709 * intercept (via guest_host_mask etc.) the current event.
7711 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7712 struct vmcs12
*vmcs12
)
7714 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7715 int cr
= exit_qualification
& 15;
7716 int reg
= (exit_qualification
>> 8) & 15;
7717 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7719 switch ((exit_qualification
>> 4) & 3) {
7720 case 0: /* mov to cr */
7723 if (vmcs12
->cr0_guest_host_mask
&
7724 (val
^ vmcs12
->cr0_read_shadow
))
7728 if ((vmcs12
->cr3_target_count
>= 1 &&
7729 vmcs12
->cr3_target_value0
== val
) ||
7730 (vmcs12
->cr3_target_count
>= 2 &&
7731 vmcs12
->cr3_target_value1
== val
) ||
7732 (vmcs12
->cr3_target_count
>= 3 &&
7733 vmcs12
->cr3_target_value2
== val
) ||
7734 (vmcs12
->cr3_target_count
>= 4 &&
7735 vmcs12
->cr3_target_value3
== val
))
7737 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7741 if (vmcs12
->cr4_guest_host_mask
&
7742 (vmcs12
->cr4_read_shadow
^ val
))
7746 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7752 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7753 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7756 case 1: /* mov from cr */
7759 if (vmcs12
->cpu_based_vm_exec_control
&
7760 CPU_BASED_CR3_STORE_EXITING
)
7764 if (vmcs12
->cpu_based_vm_exec_control
&
7765 CPU_BASED_CR8_STORE_EXITING
)
7772 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7773 * cr0. Other attempted changes are ignored, with no exit.
7775 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7776 (val
^ vmcs12
->cr0_read_shadow
))
7778 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7779 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7788 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7789 * should handle it ourselves in L0 (and then continue L2). Only call this
7790 * when in is_guest_mode (L2).
7792 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7794 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7795 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7796 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7797 u32 exit_reason
= vmx
->exit_reason
;
7799 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7800 vmcs_readl(EXIT_QUALIFICATION
),
7801 vmx
->idt_vectoring_info
,
7803 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7806 if (vmx
->nested
.nested_run_pending
)
7809 if (unlikely(vmx
->fail
)) {
7810 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7811 vmcs_read32(VM_INSTRUCTION_ERROR
));
7815 switch (exit_reason
) {
7816 case EXIT_REASON_EXCEPTION_NMI
:
7817 if (!is_exception(intr_info
))
7819 else if (is_page_fault(intr_info
))
7821 else if (is_no_device(intr_info
) &&
7822 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7824 else if (is_debug(intr_info
) &&
7826 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7828 else if (is_breakpoint(intr_info
) &&
7829 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7831 return vmcs12
->exception_bitmap
&
7832 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7833 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7835 case EXIT_REASON_TRIPLE_FAULT
:
7837 case EXIT_REASON_PENDING_INTERRUPT
:
7838 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7839 case EXIT_REASON_NMI_WINDOW
:
7840 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7841 case EXIT_REASON_TASK_SWITCH
:
7843 case EXIT_REASON_CPUID
:
7844 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7847 case EXIT_REASON_HLT
:
7848 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7849 case EXIT_REASON_INVD
:
7851 case EXIT_REASON_INVLPG
:
7852 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7853 case EXIT_REASON_RDPMC
:
7854 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7855 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7856 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7857 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7858 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7859 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7860 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7861 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7862 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7864 * VMX instructions trap unconditionally. This allows L1 to
7865 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7868 case EXIT_REASON_CR_ACCESS
:
7869 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7870 case EXIT_REASON_DR_ACCESS
:
7871 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7872 case EXIT_REASON_IO_INSTRUCTION
:
7873 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7874 case EXIT_REASON_MSR_READ
:
7875 case EXIT_REASON_MSR_WRITE
:
7876 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7877 case EXIT_REASON_INVALID_STATE
:
7879 case EXIT_REASON_MWAIT_INSTRUCTION
:
7880 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7881 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7882 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7883 case EXIT_REASON_MONITOR_INSTRUCTION
:
7884 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7885 case EXIT_REASON_PAUSE_INSTRUCTION
:
7886 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7887 nested_cpu_has2(vmcs12
,
7888 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7889 case EXIT_REASON_MCE_DURING_VMENTRY
:
7891 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7892 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7893 case EXIT_REASON_APIC_ACCESS
:
7894 return nested_cpu_has2(vmcs12
,
7895 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7896 case EXIT_REASON_APIC_WRITE
:
7897 case EXIT_REASON_EOI_INDUCED
:
7898 /* apic_write and eoi_induced should exit unconditionally. */
7900 case EXIT_REASON_EPT_VIOLATION
:
7902 * L0 always deals with the EPT violation. If nested EPT is
7903 * used, and the nested mmu code discovers that the address is
7904 * missing in the guest EPT table (EPT12), the EPT violation
7905 * will be injected with nested_ept_inject_page_fault()
7908 case EXIT_REASON_EPT_MISCONFIG
:
7910 * L2 never uses directly L1's EPT, but rather L0's own EPT
7911 * table (shadow on EPT) or a merged EPT table that L0 built
7912 * (EPT on EPT). So any problems with the structure of the
7913 * table is L0's fault.
7916 case EXIT_REASON_WBINVD
:
7917 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7918 case EXIT_REASON_XSETBV
:
7920 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7922 * This should never happen, since it is not possible to
7923 * set XSS to a non-zero value---neither in L1 nor in L2.
7924 * If if it were, XSS would have to be checked against
7925 * the XSS exit bitmap in vmcs12.
7927 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7928 case EXIT_REASON_PCOMMIT
:
7929 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7935 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7937 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7938 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7941 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
7943 struct page
*pml_pg
;
7945 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7949 vmx
->pml_pg
= pml_pg
;
7951 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7952 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7957 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
7960 __free_page(vmx
->pml_pg
);
7965 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7967 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7971 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7973 /* Do nothing if PML buffer is empty */
7974 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7977 /* PML index always points to next available PML buffer entity */
7978 if (pml_idx
>= PML_ENTITY_NUM
)
7983 pml_buf
= page_address(vmx
->pml_pg
);
7984 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7987 gpa
= pml_buf
[pml_idx
];
7988 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7989 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7992 /* reset PML index */
7993 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7997 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7998 * Called before reporting dirty_bitmap to userspace.
8000 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8003 struct kvm_vcpu
*vcpu
;
8005 * We only need to kick vcpu out of guest mode here, as PML buffer
8006 * is flushed at beginning of all VMEXITs, and it's obvious that only
8007 * vcpus running in guest are possible to have unflushed GPAs in PML
8010 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8011 kvm_vcpu_kick(vcpu
);
8014 static void vmx_dump_sel(char *name
, uint32_t sel
)
8016 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8017 name
, vmcs_read32(sel
),
8018 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8019 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8020 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8023 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8025 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8026 name
, vmcs_read32(limit
),
8027 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8030 static void dump_vmcs(void)
8032 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8033 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8034 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8035 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8036 u32 secondary_exec_control
= 0;
8037 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8038 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8041 if (cpu_has_secondary_exec_ctrls())
8042 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8044 pr_err("*** Guest State ***\n");
8045 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8046 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8047 vmcs_readl(CR0_GUEST_HOST_MASK
));
8048 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8049 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8050 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8051 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8052 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8054 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8055 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8056 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8057 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8059 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8060 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8061 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8062 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8063 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8064 vmcs_readl(GUEST_SYSENTER_ESP
),
8065 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8066 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8067 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8068 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8069 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8070 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8071 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8072 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8073 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8074 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8075 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8076 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8077 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8078 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8079 efer
, vmcs_read64(GUEST_IA32_PAT
));
8080 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8081 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8082 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8083 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8084 pr_err("PerfGlobCtl = 0x%016llx\n",
8085 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8086 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8087 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8088 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8089 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8090 vmcs_read32(GUEST_ACTIVITY_STATE
));
8091 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8092 pr_err("InterruptStatus = %04x\n",
8093 vmcs_read16(GUEST_INTR_STATUS
));
8095 pr_err("*** Host State ***\n");
8096 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8097 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8098 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8099 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8100 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8101 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8102 vmcs_read16(HOST_TR_SELECTOR
));
8103 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8104 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8105 vmcs_readl(HOST_TR_BASE
));
8106 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8107 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8108 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8109 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8110 vmcs_readl(HOST_CR4
));
8111 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8112 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8113 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8114 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8115 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8116 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8117 vmcs_read64(HOST_IA32_EFER
),
8118 vmcs_read64(HOST_IA32_PAT
));
8119 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8120 pr_err("PerfGlobCtl = 0x%016llx\n",
8121 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8123 pr_err("*** Control State ***\n");
8124 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8125 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8126 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8127 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8128 vmcs_read32(EXCEPTION_BITMAP
),
8129 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8130 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8131 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8132 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8133 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8134 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8135 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8136 vmcs_read32(VM_EXIT_INTR_INFO
),
8137 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8138 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8139 pr_err(" reason=%08x qualification=%016lx\n",
8140 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8141 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8142 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8143 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8144 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8145 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8146 pr_err("TSC Multiplier = 0x%016llx\n",
8147 vmcs_read64(TSC_MULTIPLIER
));
8148 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8149 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8150 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8151 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8152 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8153 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8154 n
= vmcs_read32(CR3_TARGET_COUNT
);
8155 for (i
= 0; i
+ 1 < n
; i
+= 4)
8156 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8157 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8158 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8160 pr_err("CR3 target%u=%016lx\n",
8161 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8162 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8163 pr_err("PLE Gap=%08x Window=%08x\n",
8164 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8165 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8166 pr_err("Virtual processor ID = 0x%04x\n",
8167 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8171 * The guest has exited. See if we can fix it or if we need userspace
8174 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8177 u32 exit_reason
= vmx
->exit_reason
;
8178 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8180 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8183 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8184 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8185 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8186 * mode as if vcpus is in root mode, the PML buffer must has been
8190 vmx_flush_pml_buffer(vcpu
);
8192 /* If guest state is invalid, start emulating */
8193 if (vmx
->emulation_required
)
8194 return handle_invalid_guest_state(vcpu
);
8196 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8197 nested_vmx_vmexit(vcpu
, exit_reason
,
8198 vmcs_read32(VM_EXIT_INTR_INFO
),
8199 vmcs_readl(EXIT_QUALIFICATION
));
8203 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8205 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8206 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8211 if (unlikely(vmx
->fail
)) {
8212 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8213 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8214 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8220 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8221 * delivery event since it indicates guest is accessing MMIO.
8222 * The vm-exit can be triggered again after return to guest that
8223 * will cause infinite loop.
8225 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8226 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8227 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8228 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8229 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8230 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8231 vcpu
->run
->internal
.ndata
= 2;
8232 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8233 vcpu
->run
->internal
.data
[1] = exit_reason
;
8237 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8238 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8239 get_vmcs12(vcpu
))))) {
8240 if (vmx_interrupt_allowed(vcpu
)) {
8241 vmx
->soft_vnmi_blocked
= 0;
8242 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8243 vcpu
->arch
.nmi_pending
) {
8245 * This CPU don't support us in finding the end of an
8246 * NMI-blocked window if the guest runs with IRQs
8247 * disabled. So we pull the trigger after 1 s of
8248 * futile waiting, but inform the user about this.
8250 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8251 "state on VCPU %d after 1 s timeout\n",
8252 __func__
, vcpu
->vcpu_id
);
8253 vmx
->soft_vnmi_blocked
= 0;
8257 if (exit_reason
< kvm_vmx_max_exit_handlers
8258 && kvm_vmx_exit_handlers
[exit_reason
])
8259 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8261 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8262 kvm_queue_exception(vcpu
, UD_VECTOR
);
8267 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8269 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8271 if (is_guest_mode(vcpu
) &&
8272 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8275 if (irr
== -1 || tpr
< irr
) {
8276 vmcs_write32(TPR_THRESHOLD
, 0);
8280 vmcs_write32(TPR_THRESHOLD
, irr
);
8283 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8285 u32 sec_exec_control
;
8288 * There is not point to enable virtualize x2apic without enable
8291 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8292 !kvm_vcpu_apicv_active(vcpu
))
8295 if (!cpu_need_tpr_shadow(vcpu
))
8298 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8301 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8302 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8304 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8305 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8307 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8309 vmx_set_msr_bitmap(vcpu
);
8312 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8314 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8317 * Currently we do not handle the nested case where L2 has an
8318 * APIC access page of its own; that page is still pinned.
8319 * Hence, we skip the case where the VCPU is in guest mode _and_
8320 * L1 prepared an APIC access page for L2.
8322 * For the case where L1 and L2 share the same APIC access page
8323 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8324 * in the vmcs12), this function will only update either the vmcs01
8325 * or the vmcs02. If the former, the vmcs02 will be updated by
8326 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8327 * the next L2->L1 exit.
8329 if (!is_guest_mode(vcpu
) ||
8330 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8331 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8332 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8335 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8343 status
= vmcs_read16(GUEST_INTR_STATUS
);
8345 if (max_isr
!= old
) {
8347 status
|= max_isr
<< 8;
8348 vmcs_write16(GUEST_INTR_STATUS
, status
);
8352 static void vmx_set_rvi(int vector
)
8360 status
= vmcs_read16(GUEST_INTR_STATUS
);
8361 old
= (u8
)status
& 0xff;
8362 if ((u8
)vector
!= old
) {
8364 status
|= (u8
)vector
;
8365 vmcs_write16(GUEST_INTR_STATUS
, status
);
8369 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8371 if (!is_guest_mode(vcpu
)) {
8372 vmx_set_rvi(max_irr
);
8380 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8383 if (nested_exit_on_intr(vcpu
))
8387 * Else, fall back to pre-APICv interrupt injection since L2
8388 * is run without virtual interrupt delivery.
8390 if (!kvm_event_needs_reinjection(vcpu
) &&
8391 vmx_interrupt_allowed(vcpu
)) {
8392 kvm_queue_interrupt(vcpu
, max_irr
, false);
8393 vmx_inject_irq(vcpu
);
8397 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8399 if (!kvm_vcpu_apicv_active(vcpu
))
8402 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8403 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8404 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8405 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8408 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8412 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8413 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8416 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8417 exit_intr_info
= vmx
->exit_intr_info
;
8419 /* Handle machine checks before interrupts are enabled */
8420 if (is_machine_check(exit_intr_info
))
8421 kvm_machine_check();
8423 /* We need to handle NMIs before interrupts are enabled */
8424 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8425 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8426 kvm_before_handle_nmi(&vmx
->vcpu
);
8428 kvm_after_handle_nmi(&vmx
->vcpu
);
8432 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8434 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8435 register void *__sp
asm(_ASM_SP
);
8438 * If external interrupt exists, IF bit is set in rflags/eflags on the
8439 * interrupt stack frame, and interrupt will be enabled on a return
8440 * from interrupt handler.
8442 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8443 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8444 unsigned int vector
;
8445 unsigned long entry
;
8447 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8448 #ifdef CONFIG_X86_64
8452 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8453 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8454 entry
= gate_offset(*desc
);
8456 #ifdef CONFIG_X86_64
8457 "mov %%" _ASM_SP
", %[sp]\n\t"
8458 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8463 "orl $0x200, (%%" _ASM_SP
")\n\t"
8464 __ASM_SIZE(push
) " $%c[cs]\n\t"
8465 "call *%[entry]\n\t"
8467 #ifdef CONFIG_X86_64
8473 [ss
]"i"(__KERNEL_DS
),
8474 [cs
]"i"(__KERNEL_CS
)
8480 static bool vmx_has_high_real_mode_segbase(void)
8482 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8485 static bool vmx_mpx_supported(void)
8487 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8488 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8491 static bool vmx_xsaves_supported(void)
8493 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8494 SECONDARY_EXEC_XSAVES
;
8497 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8502 bool idtv_info_valid
;
8504 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8506 if (cpu_has_virtual_nmis()) {
8507 if (vmx
->nmi_known_unmasked
)
8510 * Can't use vmx->exit_intr_info since we're not sure what
8511 * the exit reason is.
8513 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8514 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8515 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8517 * SDM 3: 27.7.1.2 (September 2008)
8518 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8519 * a guest IRET fault.
8520 * SDM 3: 23.2.2 (September 2008)
8521 * Bit 12 is undefined in any of the following cases:
8522 * If the VM exit sets the valid bit in the IDT-vectoring
8523 * information field.
8524 * If the VM exit is due to a double fault.
8526 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8527 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8528 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8529 GUEST_INTR_STATE_NMI
);
8531 vmx
->nmi_known_unmasked
=
8532 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8533 & GUEST_INTR_STATE_NMI
);
8534 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8535 vmx
->vnmi_blocked_time
+=
8536 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8539 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8540 u32 idt_vectoring_info
,
8541 int instr_len_field
,
8542 int error_code_field
)
8546 bool idtv_info_valid
;
8548 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8550 vcpu
->arch
.nmi_injected
= false;
8551 kvm_clear_exception_queue(vcpu
);
8552 kvm_clear_interrupt_queue(vcpu
);
8554 if (!idtv_info_valid
)
8557 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8559 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8560 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8563 case INTR_TYPE_NMI_INTR
:
8564 vcpu
->arch
.nmi_injected
= true;
8566 * SDM 3: 27.7.1.2 (September 2008)
8567 * Clear bit "block by NMI" before VM entry if a NMI
8570 vmx_set_nmi_mask(vcpu
, false);
8572 case INTR_TYPE_SOFT_EXCEPTION
:
8573 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8575 case INTR_TYPE_HARD_EXCEPTION
:
8576 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8577 u32 err
= vmcs_read32(error_code_field
);
8578 kvm_requeue_exception_e(vcpu
, vector
, err
);
8580 kvm_requeue_exception(vcpu
, vector
);
8582 case INTR_TYPE_SOFT_INTR
:
8583 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8585 case INTR_TYPE_EXT_INTR
:
8586 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8593 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8595 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8596 VM_EXIT_INSTRUCTION_LEN
,
8597 IDT_VECTORING_ERROR_CODE
);
8600 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8602 __vmx_complete_interrupts(vcpu
,
8603 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8604 VM_ENTRY_INSTRUCTION_LEN
,
8605 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8607 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8610 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8613 struct perf_guest_switch_msr
*msrs
;
8615 msrs
= perf_guest_get_msrs(&nr_msrs
);
8620 for (i
= 0; i
< nr_msrs
; i
++)
8621 if (msrs
[i
].host
== msrs
[i
].guest
)
8622 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8624 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8628 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8631 unsigned long debugctlmsr
, cr4
;
8633 /* Record the guest's net vcpu time for enforced NMI injections. */
8634 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8635 vmx
->entry_time
= ktime_get();
8637 /* Don't enter VMX if guest state is invalid, let the exit handler
8638 start emulation until we arrive back to a valid state */
8639 if (vmx
->emulation_required
)
8642 if (vmx
->ple_window_dirty
) {
8643 vmx
->ple_window_dirty
= false;
8644 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8647 if (vmx
->nested
.sync_shadow_vmcs
) {
8648 copy_vmcs12_to_shadow(vmx
);
8649 vmx
->nested
.sync_shadow_vmcs
= false;
8652 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8653 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8654 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8655 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8657 cr4
= cr4_read_shadow();
8658 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8659 vmcs_writel(HOST_CR4
, cr4
);
8660 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8663 /* When single-stepping over STI and MOV SS, we must clear the
8664 * corresponding interruptibility bits in the guest state. Otherwise
8665 * vmentry fails as it then expects bit 14 (BS) in pending debug
8666 * exceptions being set, but that's not correct for the guest debugging
8668 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8669 vmx_set_interrupt_shadow(vcpu
, 0);
8671 if (vmx
->guest_pkru_valid
)
8672 __write_pkru(vmx
->guest_pkru
);
8674 atomic_switch_perf_msrs(vmx
);
8675 debugctlmsr
= get_debugctlmsr();
8677 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8679 /* Store host registers */
8680 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8681 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8682 "push %%" _ASM_CX
" \n\t"
8683 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8685 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8686 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8688 /* Reload cr2 if changed */
8689 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8690 "mov %%cr2, %%" _ASM_DX
" \n\t"
8691 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8693 "mov %%" _ASM_AX
", %%cr2 \n\t"
8695 /* Check if vmlaunch of vmresume is needed */
8696 "cmpl $0, %c[launched](%0) \n\t"
8697 /* Load guest registers. Don't clobber flags. */
8698 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8699 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8700 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8701 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8702 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8703 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8704 #ifdef CONFIG_X86_64
8705 "mov %c[r8](%0), %%r8 \n\t"
8706 "mov %c[r9](%0), %%r9 \n\t"
8707 "mov %c[r10](%0), %%r10 \n\t"
8708 "mov %c[r11](%0), %%r11 \n\t"
8709 "mov %c[r12](%0), %%r12 \n\t"
8710 "mov %c[r13](%0), %%r13 \n\t"
8711 "mov %c[r14](%0), %%r14 \n\t"
8712 "mov %c[r15](%0), %%r15 \n\t"
8714 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8716 /* Enter guest mode */
8718 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8720 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8722 /* Save guest registers, load host registers, keep flags */
8723 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8725 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8726 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8727 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8728 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8729 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8730 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8731 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8732 #ifdef CONFIG_X86_64
8733 "mov %%r8, %c[r8](%0) \n\t"
8734 "mov %%r9, %c[r9](%0) \n\t"
8735 "mov %%r10, %c[r10](%0) \n\t"
8736 "mov %%r11, %c[r11](%0) \n\t"
8737 "mov %%r12, %c[r12](%0) \n\t"
8738 "mov %%r13, %c[r13](%0) \n\t"
8739 "mov %%r14, %c[r14](%0) \n\t"
8740 "mov %%r15, %c[r15](%0) \n\t"
8742 "mov %%cr2, %%" _ASM_AX
" \n\t"
8743 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8745 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8746 "setbe %c[fail](%0) \n\t"
8747 ".pushsection .rodata \n\t"
8748 ".global vmx_return \n\t"
8749 "vmx_return: " _ASM_PTR
" 2b \n\t"
8751 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8752 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8753 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8754 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8755 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8756 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8757 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8758 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8759 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8760 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8761 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8762 #ifdef CONFIG_X86_64
8763 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8764 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8765 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8766 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8767 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8768 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8769 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8770 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8772 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8773 [wordsize
]"i"(sizeof(ulong
))
8775 #ifdef CONFIG_X86_64
8776 , "rax", "rbx", "rdi", "rsi"
8777 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8779 , "eax", "ebx", "edi", "esi"
8783 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8785 update_debugctlmsr(debugctlmsr
);
8787 #ifndef CONFIG_X86_64
8789 * The sysexit path does not restore ds/es, so we must set them to
8790 * a reasonable value ourselves.
8792 * We can't defer this to vmx_load_host_state() since that function
8793 * may be executed in interrupt context, which saves and restore segments
8794 * around it, nullifying its effect.
8796 loadsegment(ds
, __USER_DS
);
8797 loadsegment(es
, __USER_DS
);
8800 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8801 | (1 << VCPU_EXREG_RFLAGS
)
8802 | (1 << VCPU_EXREG_PDPTR
)
8803 | (1 << VCPU_EXREG_SEGMENTS
)
8804 | (1 << VCPU_EXREG_CR3
));
8805 vcpu
->arch
.regs_dirty
= 0;
8807 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8809 vmx
->loaded_vmcs
->launched
= 1;
8811 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8814 * eager fpu is enabled if PKEY is supported and CR4 is switched
8815 * back on host, so it is safe to read guest PKRU from current
8818 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8819 vmx
->guest_pkru
= __read_pkru();
8820 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
8821 vmx
->guest_pkru_valid
= true;
8822 __write_pkru(vmx
->host_pkru
);
8824 vmx
->guest_pkru_valid
= false;
8828 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8829 * we did not inject a still-pending event to L1 now because of
8830 * nested_run_pending, we need to re-enable this bit.
8832 if (vmx
->nested
.nested_run_pending
)
8833 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8835 vmx
->nested
.nested_run_pending
= 0;
8837 vmx_complete_atomic_exit(vmx
);
8838 vmx_recover_nmi_blocking(vmx
);
8839 vmx_complete_interrupts(vmx
);
8842 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8844 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8847 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8851 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8853 vmx_vcpu_load(vcpu
, cpu
);
8858 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8863 vmx_destroy_pml_buffer(vmx
);
8864 free_vpid(vmx
->vpid
);
8865 leave_guest_mode(vcpu
);
8866 vmx_load_vmcs01(vcpu
);
8868 free_loaded_vmcs(vmx
->loaded_vmcs
);
8869 kfree(vmx
->guest_msrs
);
8870 kvm_vcpu_uninit(vcpu
);
8871 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8874 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8877 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8881 return ERR_PTR(-ENOMEM
);
8883 vmx
->vpid
= allocate_vpid();
8885 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8889 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8890 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8894 if (!vmx
->guest_msrs
) {
8898 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8899 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8900 if (!vmx
->loaded_vmcs
->vmcs
)
8903 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8904 loaded_vmcs_init(vmx
->loaded_vmcs
);
8909 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8910 vmx
->vcpu
.cpu
= cpu
;
8911 err
= vmx_vcpu_setup(vmx
);
8912 vmx_vcpu_put(&vmx
->vcpu
);
8916 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8917 err
= alloc_apic_access_page(kvm
);
8923 if (!kvm
->arch
.ept_identity_map_addr
)
8924 kvm
->arch
.ept_identity_map_addr
=
8925 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8926 err
= init_rmode_identity_map(kvm
);
8932 nested_vmx_setup_ctls_msrs(vmx
);
8933 vmx
->nested
.vpid02
= allocate_vpid();
8936 vmx
->nested
.posted_intr_nv
= -1;
8937 vmx
->nested
.current_vmptr
= -1ull;
8938 vmx
->nested
.current_vmcs12
= NULL
;
8941 * If PML is turned on, failure on enabling PML just results in failure
8942 * of creating the vcpu, therefore we can simplify PML logic (by
8943 * avoiding dealing with cases, such as enabling PML partially on vcpus
8944 * for the guest, etc.
8947 err
= vmx_create_pml_buffer(vmx
);
8955 free_vpid(vmx
->nested
.vpid02
);
8956 free_loaded_vmcs(vmx
->loaded_vmcs
);
8958 kfree(vmx
->guest_msrs
);
8960 kvm_vcpu_uninit(&vmx
->vcpu
);
8962 free_vpid(vmx
->vpid
);
8963 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8964 return ERR_PTR(err
);
8967 static void __init
vmx_check_processor_compat(void *rtn
)
8969 struct vmcs_config vmcs_conf
;
8972 if (setup_vmcs_config(&vmcs_conf
) < 0)
8974 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8975 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8976 smp_processor_id());
8981 static int get_ept_level(void)
8983 return VMX_EPT_DEFAULT_GAW
+ 1;
8986 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8991 /* For VT-d and EPT combination
8992 * 1. MMIO: always map as UC
8994 * a. VT-d without snooping control feature: can't guarantee the
8995 * result, try to trust guest.
8996 * b. VT-d with snooping control feature: snooping control feature of
8997 * VT-d engine can guarantee the cache correctness. Just set it
8998 * to WB to keep consistent with host. So the same as item 3.
8999 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9000 * consistent with host MTRR
9003 cache
= MTRR_TYPE_UNCACHABLE
;
9007 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9008 ipat
= VMX_EPT_IPAT_BIT
;
9009 cache
= MTRR_TYPE_WRBACK
;
9013 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9014 ipat
= VMX_EPT_IPAT_BIT
;
9015 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9016 cache
= MTRR_TYPE_WRBACK
;
9018 cache
= MTRR_TYPE_UNCACHABLE
;
9022 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9025 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9028 static int vmx_get_lpage_level(void)
9030 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9031 return PT_DIRECTORY_LEVEL
;
9033 /* For shadow and EPT supported 1GB page */
9034 return PT_PDPE_LEVEL
;
9037 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9040 * These bits in the secondary execution controls field
9041 * are dynamic, the others are mostly based on the hypervisor
9042 * architecture and the guest's CPUID. Do not touch the
9046 SECONDARY_EXEC_SHADOW_VMCS
|
9047 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9048 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9050 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9052 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9053 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9056 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9058 struct kvm_cpuid_entry2
*best
;
9059 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9060 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9062 if (vmx_rdtscp_supported()) {
9063 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9064 if (!rdtscp_enabled
)
9065 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9069 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9070 SECONDARY_EXEC_RDTSCP
;
9072 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9073 ~SECONDARY_EXEC_RDTSCP
;
9077 /* Exposing INVPCID only when PCID is exposed */
9078 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9079 if (vmx_invpcid_supported() &&
9080 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9081 !guest_cpuid_has_pcid(vcpu
))) {
9082 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9085 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9088 if (cpu_has_secondary_exec_ctrls())
9089 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9091 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
9092 if (guest_cpuid_has_pcommit(vcpu
))
9093 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9094 SECONDARY_EXEC_PCOMMIT
;
9096 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9097 ~SECONDARY_EXEC_PCOMMIT
;
9101 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9103 if (func
== 1 && nested
)
9104 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9107 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9108 struct x86_exception
*fault
)
9110 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9113 if (fault
->error_code
& PFERR_RSVD_MASK
)
9114 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9116 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9117 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9118 vmcs12
->guest_physical_address
= fault
->address
;
9121 /* Callbacks for nested_ept_init_mmu_context: */
9123 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9125 /* return the page table to be shadowed - in our case, EPT12 */
9126 return get_vmcs12(vcpu
)->ept_pointer
;
9129 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9131 WARN_ON(mmu_is_nested(vcpu
));
9132 kvm_init_shadow_ept_mmu(vcpu
,
9133 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9134 VMX_EPT_EXECUTE_ONLY_BIT
);
9135 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9136 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9137 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9139 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9142 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9144 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9147 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9150 bool inequality
, bit
;
9152 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9154 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9155 vmcs12
->page_fault_error_code_match
;
9156 return inequality
^ bit
;
9159 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9160 struct x86_exception
*fault
)
9162 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9164 WARN_ON(!is_guest_mode(vcpu
));
9166 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9167 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9168 vmcs_read32(VM_EXIT_INTR_INFO
),
9169 vmcs_readl(EXIT_QUALIFICATION
));
9171 kvm_inject_page_fault(vcpu
, fault
);
9174 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9175 struct vmcs12
*vmcs12
)
9177 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9178 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9180 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9181 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9182 vmcs12
->apic_access_addr
>> maxphyaddr
)
9186 * Translate L1 physical address to host physical
9187 * address for vmcs02. Keep the page pinned, so this
9188 * physical address remains valid. We keep a reference
9189 * to it so we can release it later.
9191 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9192 nested_release_page(vmx
->nested
.apic_access_page
);
9193 vmx
->nested
.apic_access_page
=
9194 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9197 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9198 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9199 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9202 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9203 nested_release_page(vmx
->nested
.virtual_apic_page
);
9204 vmx
->nested
.virtual_apic_page
=
9205 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9208 * Failing the vm entry is _not_ what the processor does
9209 * but it's basically the only possibility we have.
9210 * We could still enter the guest if CR8 load exits are
9211 * enabled, CR8 store exits are enabled, and virtualize APIC
9212 * access is disabled; in this case the processor would never
9213 * use the TPR shadow and we could simply clear the bit from
9214 * the execution control. But such a configuration is useless,
9215 * so let's keep the code simple.
9217 if (!vmx
->nested
.virtual_apic_page
)
9221 if (nested_cpu_has_posted_intr(vmcs12
)) {
9222 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9223 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9226 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9227 kunmap(vmx
->nested
.pi_desc_page
);
9228 nested_release_page(vmx
->nested
.pi_desc_page
);
9230 vmx
->nested
.pi_desc_page
=
9231 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9232 if (!vmx
->nested
.pi_desc_page
)
9235 vmx
->nested
.pi_desc
=
9236 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9237 if (!vmx
->nested
.pi_desc
) {
9238 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9241 vmx
->nested
.pi_desc
=
9242 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9243 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9250 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9252 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9253 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9255 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9258 /* Make sure short timeouts reliably trigger an immediate vmexit.
9259 * hrtimer_start does not guarantee this. */
9260 if (preemption_timeout
<= 1) {
9261 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9265 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9266 preemption_timeout
*= 1000000;
9267 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9268 hrtimer_start(&vmx
->nested
.preemption_timer
,
9269 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9272 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9273 struct vmcs12
*vmcs12
)
9278 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9281 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9285 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9287 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9288 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9295 * Merge L0's and L1's MSR bitmap, return false to indicate that
9296 * we do not use the hardware.
9298 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9299 struct vmcs12
*vmcs12
)
9303 unsigned long *msr_bitmap
;
9305 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9308 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9313 msr_bitmap
= (unsigned long *)kmap(page
);
9315 nested_release_page_clean(page
);
9320 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9321 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9322 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9323 nested_vmx_disable_intercept_for_msr(
9325 vmx_msr_bitmap_nested
,
9327 /* TPR is allowed */
9328 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9329 vmx_msr_bitmap_nested
,
9330 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9331 MSR_TYPE_R
| MSR_TYPE_W
);
9332 if (nested_cpu_has_vid(vmcs12
)) {
9333 /* EOI and self-IPI are allowed */
9334 nested_vmx_disable_intercept_for_msr(
9336 vmx_msr_bitmap_nested
,
9337 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9339 nested_vmx_disable_intercept_for_msr(
9341 vmx_msr_bitmap_nested
,
9342 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9347 * Enable reading intercept of all the x2apic
9348 * MSRs. We should not rely on vmcs12 to do any
9349 * optimizations here, it may have been modified
9352 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9353 __vmx_enable_intercept_for_msr(
9354 vmx_msr_bitmap_nested
,
9358 __vmx_enable_intercept_for_msr(
9359 vmx_msr_bitmap_nested
,
9360 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9362 __vmx_enable_intercept_for_msr(
9363 vmx_msr_bitmap_nested
,
9364 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9366 __vmx_enable_intercept_for_msr(
9367 vmx_msr_bitmap_nested
,
9368 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9372 nested_release_page_clean(page
);
9377 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9378 struct vmcs12
*vmcs12
)
9380 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9381 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9382 !nested_cpu_has_vid(vmcs12
) &&
9383 !nested_cpu_has_posted_intr(vmcs12
))
9387 * If virtualize x2apic mode is enabled,
9388 * virtualize apic access must be disabled.
9390 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9391 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9395 * If virtual interrupt delivery is enabled,
9396 * we must exit on external interrupts.
9398 if (nested_cpu_has_vid(vmcs12
) &&
9399 !nested_exit_on_intr(vcpu
))
9403 * bits 15:8 should be zero in posted_intr_nv,
9404 * the descriptor address has been already checked
9405 * in nested_get_vmcs12_pages.
9407 if (nested_cpu_has_posted_intr(vmcs12
) &&
9408 (!nested_cpu_has_vid(vmcs12
) ||
9409 !nested_exit_intr_ack_set(vcpu
) ||
9410 vmcs12
->posted_intr_nv
& 0xff00))
9413 /* tpr shadow is needed by all apicv features. */
9414 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9420 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9421 unsigned long count_field
,
9422 unsigned long addr_field
)
9427 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9428 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9434 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9435 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9436 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9437 pr_warn_ratelimited(
9438 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9439 addr_field
, maxphyaddr
, count
, addr
);
9445 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9446 struct vmcs12
*vmcs12
)
9448 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9449 vmcs12
->vm_exit_msr_store_count
== 0 &&
9450 vmcs12
->vm_entry_msr_load_count
== 0)
9451 return 0; /* Fast path */
9452 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9453 VM_EXIT_MSR_LOAD_ADDR
) ||
9454 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9455 VM_EXIT_MSR_STORE_ADDR
) ||
9456 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9457 VM_ENTRY_MSR_LOAD_ADDR
))
9462 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9463 struct vmx_msr_entry
*e
)
9465 /* x2APIC MSR accesses are not allowed */
9466 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9468 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9469 e
->index
== MSR_IA32_UCODE_REV
)
9471 if (e
->reserved
!= 0)
9476 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9477 struct vmx_msr_entry
*e
)
9479 if (e
->index
== MSR_FS_BASE
||
9480 e
->index
== MSR_GS_BASE
||
9481 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9482 nested_vmx_msr_check_common(vcpu
, e
))
9487 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9488 struct vmx_msr_entry
*e
)
9490 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9491 nested_vmx_msr_check_common(vcpu
, e
))
9497 * Load guest's/host's msr at nested entry/exit.
9498 * return 0 for success, entry index for failure.
9500 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9503 struct vmx_msr_entry e
;
9504 struct msr_data msr
;
9506 msr
.host_initiated
= false;
9507 for (i
= 0; i
< count
; i
++) {
9508 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9510 pr_warn_ratelimited(
9511 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9512 __func__
, i
, gpa
+ i
* sizeof(e
));
9515 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9516 pr_warn_ratelimited(
9517 "%s check failed (%u, 0x%x, 0x%x)\n",
9518 __func__
, i
, e
.index
, e
.reserved
);
9521 msr
.index
= e
.index
;
9523 if (kvm_set_msr(vcpu
, &msr
)) {
9524 pr_warn_ratelimited(
9525 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9526 __func__
, i
, e
.index
, e
.value
);
9535 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9538 struct vmx_msr_entry e
;
9540 for (i
= 0; i
< count
; i
++) {
9541 struct msr_data msr_info
;
9542 if (kvm_vcpu_read_guest(vcpu
,
9543 gpa
+ i
* sizeof(e
),
9544 &e
, 2 * sizeof(u32
))) {
9545 pr_warn_ratelimited(
9546 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9547 __func__
, i
, gpa
+ i
* sizeof(e
));
9550 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9551 pr_warn_ratelimited(
9552 "%s check failed (%u, 0x%x, 0x%x)\n",
9553 __func__
, i
, e
.index
, e
.reserved
);
9556 msr_info
.host_initiated
= false;
9557 msr_info
.index
= e
.index
;
9558 if (kvm_get_msr(vcpu
, &msr_info
)) {
9559 pr_warn_ratelimited(
9560 "%s cannot read MSR (%u, 0x%x)\n",
9561 __func__
, i
, e
.index
);
9564 if (kvm_vcpu_write_guest(vcpu
,
9565 gpa
+ i
* sizeof(e
) +
9566 offsetof(struct vmx_msr_entry
, value
),
9567 &msr_info
.data
, sizeof(msr_info
.data
))) {
9568 pr_warn_ratelimited(
9569 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9570 __func__
, i
, e
.index
, msr_info
.data
);
9578 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9579 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9580 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9581 * guest in a way that will both be appropriate to L1's requests, and our
9582 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9583 * function also has additional necessary side-effects, like setting various
9584 * vcpu->arch fields.
9586 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9591 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9592 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9593 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9594 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9595 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9596 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9597 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9598 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9599 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9600 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9601 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9602 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9603 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9604 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9605 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9606 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9607 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9608 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9609 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9610 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9611 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9612 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9613 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9614 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9615 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9616 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9617 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9618 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9619 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9620 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9621 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9622 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9623 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9624 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9625 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9626 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9628 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9629 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9630 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9632 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9633 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9635 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9636 vmcs12
->vm_entry_intr_info_field
);
9637 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9638 vmcs12
->vm_entry_exception_error_code
);
9639 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9640 vmcs12
->vm_entry_instruction_len
);
9641 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9642 vmcs12
->guest_interruptibility_info
);
9643 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9644 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9645 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9646 vmcs12
->guest_pending_dbg_exceptions
);
9647 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9648 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9650 if (nested_cpu_has_xsaves(vmcs12
))
9651 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9652 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9654 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9655 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9656 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9658 if (nested_cpu_has_posted_intr(vmcs12
)) {
9660 * Note that we use L0's vector here and in
9661 * vmx_deliver_nested_posted_interrupt.
9663 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9664 vmx
->nested
.pi_pending
= false;
9665 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9666 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9667 page_to_phys(vmx
->nested
.pi_desc_page
) +
9668 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9671 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9673 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9675 vmx
->nested
.preemption_timer_expired
= false;
9676 if (nested_cpu_has_preemption_timer(vmcs12
))
9677 vmx_start_preemption_timer(vcpu
);
9680 * Whether page-faults are trapped is determined by a combination of
9681 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9682 * If enable_ept, L0 doesn't care about page faults and we should
9683 * set all of these to L1's desires. However, if !enable_ept, L0 does
9684 * care about (at least some) page faults, and because it is not easy
9685 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9686 * to exit on each and every L2 page fault. This is done by setting
9687 * MASK=MATCH=0 and (see below) EB.PF=1.
9688 * Note that below we don't need special code to set EB.PF beyond the
9689 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9690 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9691 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9693 * A problem with this approach (when !enable_ept) is that L1 may be
9694 * injected with more page faults than it asked for. This could have
9695 * caused problems, but in practice existing hypervisors don't care.
9696 * To fix this, we will need to emulate the PFEC checking (on the L1
9697 * page tables), using walk_addr(), when injecting PFs to L1.
9699 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9700 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9701 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9702 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9704 if (cpu_has_secondary_exec_ctrls()) {
9705 exec_control
= vmx_secondary_exec_control(vmx
);
9707 /* Take the following fields only from vmcs12 */
9708 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9709 SECONDARY_EXEC_RDTSCP
|
9710 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9711 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9712 SECONDARY_EXEC_PCOMMIT
);
9713 if (nested_cpu_has(vmcs12
,
9714 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9715 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9717 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9719 * If translation failed, no matter: This feature asks
9720 * to exit when accessing the given address, and if it
9721 * can never be accessed, this feature won't do
9724 if (!vmx
->nested
.apic_access_page
)
9726 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9728 vmcs_write64(APIC_ACCESS_ADDR
,
9729 page_to_phys(vmx
->nested
.apic_access_page
));
9730 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9731 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9733 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9734 kvm_vcpu_reload_apic_access_page(vcpu
);
9737 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9738 vmcs_write64(EOI_EXIT_BITMAP0
,
9739 vmcs12
->eoi_exit_bitmap0
);
9740 vmcs_write64(EOI_EXIT_BITMAP1
,
9741 vmcs12
->eoi_exit_bitmap1
);
9742 vmcs_write64(EOI_EXIT_BITMAP2
,
9743 vmcs12
->eoi_exit_bitmap2
);
9744 vmcs_write64(EOI_EXIT_BITMAP3
,
9745 vmcs12
->eoi_exit_bitmap3
);
9746 vmcs_write16(GUEST_INTR_STATUS
,
9747 vmcs12
->guest_intr_status
);
9750 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9755 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9756 * Some constant fields are set here by vmx_set_constant_host_state().
9757 * Other fields are different per CPU, and will be set later when
9758 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9760 vmx_set_constant_host_state(vmx
);
9763 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9764 * entry, but only if the current (host) sp changed from the value
9765 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9766 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9767 * here we just force the write to happen on entry.
9771 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9772 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9773 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9774 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9775 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9777 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9778 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9779 page_to_phys(vmx
->nested
.virtual_apic_page
));
9780 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9783 if (cpu_has_vmx_msr_bitmap() &&
9784 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9785 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9786 /* MSR_BITMAP will be set by following vmx_set_efer. */
9788 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9791 * Merging of IO bitmap not currently supported.
9792 * Rather, exit every time.
9794 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9795 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9797 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9799 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9800 * bitwise-or of what L1 wants to trap for L2, and what we want to
9801 * trap. Note that CR0.TS also needs updating - we do this later.
9803 update_exception_bitmap(vcpu
);
9804 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9805 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9807 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9808 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9809 * bits are further modified by vmx_set_efer() below.
9811 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9813 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9814 * emulated by vmx_set_efer(), below.
9816 vm_entry_controls_init(vmx
,
9817 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9818 ~VM_ENTRY_IA32E_MODE
) |
9819 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9821 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9822 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9823 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9824 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9825 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9828 set_cr4_guest_host_mask(vmx
);
9830 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9831 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9833 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9834 vmcs_write64(TSC_OFFSET
,
9835 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9837 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9841 * There is no direct mapping between vpid02 and vpid12, the
9842 * vpid02 is per-vCPU for L0 and reused while the value of
9843 * vpid12 is changed w/ one invvpid during nested vmentry.
9844 * The vpid12 is allocated by L1 for L2, so it will not
9845 * influence global bitmap(for vpid01 and vpid02 allocation)
9846 * even if spawn a lot of nested vCPUs.
9848 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9849 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9850 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9851 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9852 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9855 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9856 vmx_flush_tlb(vcpu
);
9861 if (nested_cpu_has_ept(vmcs12
)) {
9862 kvm_mmu_unload(vcpu
);
9863 nested_ept_init_mmu_context(vcpu
);
9866 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9867 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9868 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9869 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9871 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9872 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9873 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9876 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9877 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9878 * The CR0_READ_SHADOW is what L2 should have expected to read given
9879 * the specifications by L1; It's not enough to take
9880 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9881 * have more bits than L1 expected.
9883 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9884 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9886 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9887 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9889 /* shadow page tables on either EPT or shadow page tables */
9890 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9891 kvm_mmu_reset_context(vcpu
);
9894 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9897 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9900 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9901 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9902 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9903 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9906 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9907 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9911 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9912 * for running an L2 nested guest.
9914 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9916 struct vmcs12
*vmcs12
;
9917 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9919 struct loaded_vmcs
*vmcs02
;
9923 if (!nested_vmx_check_permission(vcpu
) ||
9924 !nested_vmx_check_vmcs12(vcpu
))
9927 skip_emulated_instruction(vcpu
);
9928 vmcs12
= get_vmcs12(vcpu
);
9930 if (enable_shadow_vmcs
)
9931 copy_shadow_to_vmcs12(vmx
);
9934 * The nested entry process starts with enforcing various prerequisites
9935 * on vmcs12 as required by the Intel SDM, and act appropriately when
9936 * they fail: As the SDM explains, some conditions should cause the
9937 * instruction to fail, while others will cause the instruction to seem
9938 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9939 * To speed up the normal (success) code path, we should avoid checking
9940 * for misconfigurations which will anyway be caught by the processor
9941 * when using the merged vmcs02.
9943 if (vmcs12
->launch_state
== launch
) {
9944 nested_vmx_failValid(vcpu
,
9945 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9946 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9950 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9951 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9952 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9956 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9957 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9961 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9962 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9966 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9967 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9971 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9972 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9976 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9977 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9978 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9979 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9980 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9981 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9982 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9983 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9984 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9985 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9986 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9987 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9988 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9989 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9990 vmx
->nested
.nested_vmx_entry_ctls_high
))
9992 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9996 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9997 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9998 nested_vmx_failValid(vcpu
,
9999 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
10003 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10004 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10005 nested_vmx_entry_failure(vcpu
, vmcs12
,
10006 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10009 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
10010 nested_vmx_entry_failure(vcpu
, vmcs12
,
10011 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
10016 * If the load IA32_EFER VM-entry control is 1, the following checks
10017 * are performed on the field for the IA32_EFER MSR:
10018 * - Bits reserved in the IA32_EFER MSR must be 0.
10019 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10020 * the IA-32e mode guest VM-exit control. It must also be identical
10021 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10024 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10025 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10026 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10027 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10028 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10029 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10030 nested_vmx_entry_failure(vcpu
, vmcs12
,
10031 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10037 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10038 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10039 * the values of the LMA and LME bits in the field must each be that of
10040 * the host address-space size VM-exit control.
10042 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10043 ia32e
= (vmcs12
->vm_exit_controls
&
10044 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10045 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10046 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10047 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10048 nested_vmx_entry_failure(vcpu
, vmcs12
,
10049 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10055 * We're finally done with prerequisite checking, and can start with
10056 * the nested entry.
10059 vmcs02
= nested_get_current_vmcs02(vmx
);
10063 enter_guest_mode(vcpu
);
10065 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
10067 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10068 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10071 vmx
->loaded_vmcs
= vmcs02
;
10072 vmx_vcpu_put(vcpu
);
10073 vmx_vcpu_load(vcpu
, cpu
);
10077 vmx_segment_cache_clear(vmx
);
10079 prepare_vmcs02(vcpu
, vmcs12
);
10081 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10082 vmcs12
->vm_entry_msr_load_addr
,
10083 vmcs12
->vm_entry_msr_load_count
);
10084 if (msr_entry_idx
) {
10085 leave_guest_mode(vcpu
);
10086 vmx_load_vmcs01(vcpu
);
10087 nested_vmx_entry_failure(vcpu
, vmcs12
,
10088 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10092 vmcs12
->launch_state
= 1;
10094 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10095 return kvm_vcpu_halt(vcpu
);
10097 vmx
->nested
.nested_run_pending
= 1;
10100 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10101 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10102 * returned as far as L1 is concerned. It will only return (and set
10103 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10109 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10110 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10111 * This function returns the new value we should put in vmcs12.guest_cr0.
10112 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10113 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10114 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10115 * didn't trap the bit, because if L1 did, so would L0).
10116 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10117 * been modified by L2, and L1 knows it. So just leave the old value of
10118 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10119 * isn't relevant, because if L0 traps this bit it can set it to anything.
10120 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10121 * changed these bits, and therefore they need to be updated, but L0
10122 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10123 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10125 static inline unsigned long
10126 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10129 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10130 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10131 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10132 vcpu
->arch
.cr0_guest_owned_bits
));
10135 static inline unsigned long
10136 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10139 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10140 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10141 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10142 vcpu
->arch
.cr4_guest_owned_bits
));
10145 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10146 struct vmcs12
*vmcs12
)
10151 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10152 nr
= vcpu
->arch
.exception
.nr
;
10153 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10155 if (kvm_exception_is_soft(nr
)) {
10156 vmcs12
->vm_exit_instruction_len
=
10157 vcpu
->arch
.event_exit_inst_len
;
10158 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10160 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10162 if (vcpu
->arch
.exception
.has_error_code
) {
10163 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10164 vmcs12
->idt_vectoring_error_code
=
10165 vcpu
->arch
.exception
.error_code
;
10168 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10169 } else if (vcpu
->arch
.nmi_injected
) {
10170 vmcs12
->idt_vectoring_info_field
=
10171 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10172 } else if (vcpu
->arch
.interrupt
.pending
) {
10173 nr
= vcpu
->arch
.interrupt
.nr
;
10174 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10176 if (vcpu
->arch
.interrupt
.soft
) {
10177 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10178 vmcs12
->vm_entry_instruction_len
=
10179 vcpu
->arch
.event_exit_inst_len
;
10181 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10183 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10187 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10189 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10191 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10192 vmx
->nested
.preemption_timer_expired
) {
10193 if (vmx
->nested
.nested_run_pending
)
10195 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10199 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10200 if (vmx
->nested
.nested_run_pending
||
10201 vcpu
->arch
.interrupt
.pending
)
10203 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10204 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10205 INTR_INFO_VALID_MASK
, 0);
10207 * The NMI-triggered VM exit counts as injection:
10208 * clear this one and block further NMIs.
10210 vcpu
->arch
.nmi_pending
= 0;
10211 vmx_set_nmi_mask(vcpu
, true);
10215 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10216 nested_exit_on_intr(vcpu
)) {
10217 if (vmx
->nested
.nested_run_pending
)
10219 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10223 return vmx_complete_nested_posted_interrupt(vcpu
);
10226 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10228 ktime_t remaining
=
10229 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10232 if (ktime_to_ns(remaining
) <= 0)
10235 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10236 do_div(value
, 1000000);
10237 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10241 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10242 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10243 * and this function updates it to reflect the changes to the guest state while
10244 * L2 was running (and perhaps made some exits which were handled directly by L0
10245 * without going back to L1), and to reflect the exit reason.
10246 * Note that we do not have to copy here all VMCS fields, just those that
10247 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10248 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10249 * which already writes to vmcs12 directly.
10251 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10252 u32 exit_reason
, u32 exit_intr_info
,
10253 unsigned long exit_qualification
)
10255 /* update guest state fields: */
10256 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10257 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10259 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10260 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10261 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10263 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10264 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10265 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10266 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10267 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10268 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10269 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10270 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10271 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10272 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10273 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10274 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10275 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10276 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10277 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10278 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10279 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10280 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10281 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10282 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10283 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10284 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10285 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10286 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10287 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10288 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10289 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10290 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10291 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10292 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10293 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10294 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10295 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10296 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10297 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10298 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10300 vmcs12
->guest_interruptibility_info
=
10301 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10302 vmcs12
->guest_pending_dbg_exceptions
=
10303 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10304 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10305 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10307 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10309 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10310 if (vmcs12
->vm_exit_controls
&
10311 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10312 vmcs12
->vmx_preemption_timer_value
=
10313 vmx_get_preemption_timer_value(vcpu
);
10314 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10318 * In some cases (usually, nested EPT), L2 is allowed to change its
10319 * own CR3 without exiting. If it has changed it, we must keep it.
10320 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10321 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10323 * Additionally, restore L2's PDPTR to vmcs12.
10326 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10327 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10328 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10329 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10330 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10333 if (nested_cpu_has_vid(vmcs12
))
10334 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10336 vmcs12
->vm_entry_controls
=
10337 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10338 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10340 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10341 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10342 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10345 /* TODO: These cannot have changed unless we have MSR bitmaps and
10346 * the relevant bit asks not to trap the change */
10347 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10348 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10349 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10350 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10351 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10352 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10353 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10354 if (kvm_mpx_supported())
10355 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10356 if (nested_cpu_has_xsaves(vmcs12
))
10357 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10359 /* update exit information fields: */
10361 vmcs12
->vm_exit_reason
= exit_reason
;
10362 vmcs12
->exit_qualification
= exit_qualification
;
10364 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10365 if ((vmcs12
->vm_exit_intr_info
&
10366 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10367 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10368 vmcs12
->vm_exit_intr_error_code
=
10369 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10370 vmcs12
->idt_vectoring_info_field
= 0;
10371 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10372 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10374 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10375 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10376 * instead of reading the real value. */
10377 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10380 * Transfer the event that L0 or L1 may wanted to inject into
10381 * L2 to IDT_VECTORING_INFO_FIELD.
10383 vmcs12_save_pending_event(vcpu
, vmcs12
);
10387 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10388 * preserved above and would only end up incorrectly in L1.
10390 vcpu
->arch
.nmi_injected
= false;
10391 kvm_clear_exception_queue(vcpu
);
10392 kvm_clear_interrupt_queue(vcpu
);
10396 * A part of what we need to when the nested L2 guest exits and we want to
10397 * run its L1 parent, is to reset L1's guest state to the host state specified
10399 * This function is to be called not only on normal nested exit, but also on
10400 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10401 * Failures During or After Loading Guest State").
10402 * This function should be called when the active VMCS is L1's (vmcs01).
10404 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10405 struct vmcs12
*vmcs12
)
10407 struct kvm_segment seg
;
10409 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10410 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10411 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10412 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10414 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10415 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10417 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10418 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10419 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10421 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10422 * actually changed, because it depends on the current state of
10423 * fpu_active (which may have changed).
10424 * Note that vmx_set_cr0 refers to efer set above.
10426 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10428 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10429 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10430 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10432 update_exception_bitmap(vcpu
);
10433 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10434 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10437 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10438 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10440 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10441 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10443 nested_ept_uninit_mmu_context(vcpu
);
10445 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10446 kvm_mmu_reset_context(vcpu
);
10449 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10453 * Trivially support vpid by letting L2s share their parent
10454 * L1's vpid. TODO: move to a more elaborate solution, giving
10455 * each L2 its own vpid and exposing the vpid feature to L1.
10457 vmx_flush_tlb(vcpu
);
10461 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10462 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10463 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10464 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10465 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10467 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10468 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10469 vmcs_write64(GUEST_BNDCFGS
, 0);
10471 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10472 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10473 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10475 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10476 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10477 vmcs12
->host_ia32_perf_global_ctrl
);
10479 /* Set L1 segment info according to Intel SDM
10480 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10481 seg
= (struct kvm_segment
) {
10483 .limit
= 0xFFFFFFFF,
10484 .selector
= vmcs12
->host_cs_selector
,
10490 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10494 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10495 seg
= (struct kvm_segment
) {
10497 .limit
= 0xFFFFFFFF,
10504 seg
.selector
= vmcs12
->host_ds_selector
;
10505 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10506 seg
.selector
= vmcs12
->host_es_selector
;
10507 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10508 seg
.selector
= vmcs12
->host_ss_selector
;
10509 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10510 seg
.selector
= vmcs12
->host_fs_selector
;
10511 seg
.base
= vmcs12
->host_fs_base
;
10512 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10513 seg
.selector
= vmcs12
->host_gs_selector
;
10514 seg
.base
= vmcs12
->host_gs_base
;
10515 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10516 seg
= (struct kvm_segment
) {
10517 .base
= vmcs12
->host_tr_base
,
10519 .selector
= vmcs12
->host_tr_selector
,
10523 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10525 kvm_set_dr(vcpu
, 7, 0x400);
10526 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10528 if (cpu_has_vmx_msr_bitmap())
10529 vmx_set_msr_bitmap(vcpu
);
10531 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10532 vmcs12
->vm_exit_msr_load_count
))
10533 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10537 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10538 * and modify vmcs12 to make it see what it would expect to see there if
10539 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10541 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10542 u32 exit_intr_info
,
10543 unsigned long exit_qualification
)
10545 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10546 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10548 /* trying to cancel vmlaunch/vmresume is a bug */
10549 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10551 leave_guest_mode(vcpu
);
10552 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10553 exit_qualification
);
10555 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10556 vmcs12
->vm_exit_msr_store_count
))
10557 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10559 vmx_load_vmcs01(vcpu
);
10561 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10562 && nested_exit_intr_ack_set(vcpu
)) {
10563 int irq
= kvm_cpu_get_interrupt(vcpu
);
10565 vmcs12
->vm_exit_intr_info
= irq
|
10566 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10569 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10570 vmcs12
->exit_qualification
,
10571 vmcs12
->idt_vectoring_info_field
,
10572 vmcs12
->vm_exit_intr_info
,
10573 vmcs12
->vm_exit_intr_error_code
,
10576 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10577 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10578 vmx_segment_cache_clear(vmx
);
10580 /* if no vmcs02 cache requested, remove the one we used */
10581 if (VMCS02_POOL_SIZE
== 0)
10582 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10584 load_vmcs12_host_state(vcpu
, vmcs12
);
10586 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10587 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10589 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10592 /* Unpin physical memory we referred to in vmcs02 */
10593 if (vmx
->nested
.apic_access_page
) {
10594 nested_release_page(vmx
->nested
.apic_access_page
);
10595 vmx
->nested
.apic_access_page
= NULL
;
10597 if (vmx
->nested
.virtual_apic_page
) {
10598 nested_release_page(vmx
->nested
.virtual_apic_page
);
10599 vmx
->nested
.virtual_apic_page
= NULL
;
10601 if (vmx
->nested
.pi_desc_page
) {
10602 kunmap(vmx
->nested
.pi_desc_page
);
10603 nested_release_page(vmx
->nested
.pi_desc_page
);
10604 vmx
->nested
.pi_desc_page
= NULL
;
10605 vmx
->nested
.pi_desc
= NULL
;
10609 * We are now running in L2, mmu_notifier will force to reload the
10610 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10612 kvm_vcpu_reload_apic_access_page(vcpu
);
10615 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10616 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10617 * success or failure flag accordingly.
10619 if (unlikely(vmx
->fail
)) {
10621 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10623 nested_vmx_succeed(vcpu
);
10624 if (enable_shadow_vmcs
)
10625 vmx
->nested
.sync_shadow_vmcs
= true;
10627 /* in case we halted in L2 */
10628 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10632 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10634 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10636 if (is_guest_mode(vcpu
))
10637 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10638 free_nested(to_vmx(vcpu
));
10642 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10643 * 23.7 "VM-entry failures during or after loading guest state" (this also
10644 * lists the acceptable exit-reason and exit-qualification parameters).
10645 * It should only be called before L2 actually succeeded to run, and when
10646 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10648 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10649 struct vmcs12
*vmcs12
,
10650 u32 reason
, unsigned long qualification
)
10652 load_vmcs12_host_state(vcpu
, vmcs12
);
10653 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10654 vmcs12
->exit_qualification
= qualification
;
10655 nested_vmx_succeed(vcpu
);
10656 if (enable_shadow_vmcs
)
10657 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10660 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10661 struct x86_instruction_info
*info
,
10662 enum x86_intercept_stage stage
)
10664 return X86EMUL_CONTINUE
;
10667 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10670 shrink_ple_window(vcpu
);
10673 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10674 struct kvm_memory_slot
*slot
)
10676 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10677 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10680 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10681 struct kvm_memory_slot
*slot
)
10683 kvm_mmu_slot_set_dirty(kvm
, slot
);
10686 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10688 kvm_flush_pml_buffers(kvm
);
10691 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10692 struct kvm_memory_slot
*memslot
,
10693 gfn_t offset
, unsigned long mask
)
10695 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10699 * This routine does the following things for vCPU which is going
10700 * to be blocked if VT-d PI is enabled.
10701 * - Store the vCPU to the wakeup list, so when interrupts happen
10702 * we can find the right vCPU to wake up.
10703 * - Change the Posted-interrupt descriptor as below:
10704 * 'NDST' <-- vcpu->pre_pcpu
10705 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10706 * - If 'ON' is set during this process, which means at least one
10707 * interrupt is posted for this vCPU, we cannot block it, in
10708 * this case, return 1, otherwise, return 0.
10711 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10713 unsigned long flags
;
10715 struct pi_desc old
, new;
10716 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10718 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10719 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10720 !kvm_vcpu_apicv_active(vcpu
))
10723 vcpu
->pre_pcpu
= vcpu
->cpu
;
10724 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10725 vcpu
->pre_pcpu
), flags
);
10726 list_add_tail(&vcpu
->blocked_vcpu_list
,
10727 &per_cpu(blocked_vcpu_on_cpu
,
10729 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10730 vcpu
->pre_pcpu
), flags
);
10733 old
.control
= new.control
= pi_desc
->control
;
10736 * We should not block the vCPU if
10737 * an interrupt is posted for it.
10739 if (pi_test_on(pi_desc
) == 1) {
10740 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10741 vcpu
->pre_pcpu
), flags
);
10742 list_del(&vcpu
->blocked_vcpu_list
);
10743 spin_unlock_irqrestore(
10744 &per_cpu(blocked_vcpu_on_cpu_lock
,
10745 vcpu
->pre_pcpu
), flags
);
10746 vcpu
->pre_pcpu
= -1;
10751 WARN((pi_desc
->sn
== 1),
10752 "Warning: SN field of posted-interrupts "
10753 "is set before blocking\n");
10756 * Since vCPU can be preempted during this process,
10757 * vcpu->cpu could be different with pre_pcpu, we
10758 * need to set pre_pcpu as the destination of wakeup
10759 * notification event, then we can find the right vCPU
10760 * to wakeup in wakeup handler if interrupts happen
10761 * when the vCPU is in blocked state.
10763 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10765 if (x2apic_enabled())
10768 new.ndst
= (dest
<< 8) & 0xFF00;
10770 /* set 'NV' to 'wakeup vector' */
10771 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10772 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10773 new.control
) != old
.control
);
10778 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10780 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10781 struct pi_desc old
, new;
10783 unsigned long flags
;
10785 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10786 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10787 !kvm_vcpu_apicv_active(vcpu
))
10791 old
.control
= new.control
= pi_desc
->control
;
10793 dest
= cpu_physical_id(vcpu
->cpu
);
10795 if (x2apic_enabled())
10798 new.ndst
= (dest
<< 8) & 0xFF00;
10800 /* Allow posting non-urgent interrupts */
10803 /* set 'NV' to 'notification vector' */
10804 new.nv
= POSTED_INTR_VECTOR
;
10805 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10806 new.control
) != old
.control
);
10808 if(vcpu
->pre_pcpu
!= -1) {
10810 &per_cpu(blocked_vcpu_on_cpu_lock
,
10811 vcpu
->pre_pcpu
), flags
);
10812 list_del(&vcpu
->blocked_vcpu_list
);
10813 spin_unlock_irqrestore(
10814 &per_cpu(blocked_vcpu_on_cpu_lock
,
10815 vcpu
->pre_pcpu
), flags
);
10816 vcpu
->pre_pcpu
= -1;
10821 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10824 * @host_irq: host irq of the interrupt
10825 * @guest_irq: gsi of the interrupt
10826 * @set: set or unset PI
10827 * returns 0 on success, < 0 on failure
10829 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10830 uint32_t guest_irq
, bool set
)
10832 struct kvm_kernel_irq_routing_entry
*e
;
10833 struct kvm_irq_routing_table
*irq_rt
;
10834 struct kvm_lapic_irq irq
;
10835 struct kvm_vcpu
*vcpu
;
10836 struct vcpu_data vcpu_info
;
10837 int idx
, ret
= -EINVAL
;
10839 if (!kvm_arch_has_assigned_device(kvm
) ||
10840 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10841 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
10844 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10845 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10846 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10848 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10849 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10852 * VT-d PI cannot support posting multicast/broadcast
10853 * interrupts to a vCPU, we still use interrupt remapping
10854 * for these kind of interrupts.
10856 * For lowest-priority interrupts, we only support
10857 * those with single CPU as the destination, e.g. user
10858 * configures the interrupts via /proc/irq or uses
10859 * irqbalance to make the interrupts single-CPU.
10861 * We will support full lowest-priority interrupt later.
10864 kvm_set_msi_irq(e
, &irq
);
10865 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
10867 * Make sure the IRTE is in remapped mode if
10868 * we don't handle it in posted mode.
10870 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10873 "failed to back to remapped mode, irq: %u\n",
10881 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10882 vcpu_info
.vector
= irq
.vector
;
10884 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
10885 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10888 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10890 /* suppress notification event before unposting */
10891 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10892 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10893 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10897 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10905 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10909 static struct kvm_x86_ops vmx_x86_ops
= {
10910 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10911 .disabled_by_bios
= vmx_disabled_by_bios
,
10912 .hardware_setup
= hardware_setup
,
10913 .hardware_unsetup
= hardware_unsetup
,
10914 .check_processor_compatibility
= vmx_check_processor_compat
,
10915 .hardware_enable
= hardware_enable
,
10916 .hardware_disable
= hardware_disable
,
10917 .cpu_has_accelerated_tpr
= report_flexpriority
,
10918 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10920 .vcpu_create
= vmx_create_vcpu
,
10921 .vcpu_free
= vmx_free_vcpu
,
10922 .vcpu_reset
= vmx_vcpu_reset
,
10924 .prepare_guest_switch
= vmx_save_host_state
,
10925 .vcpu_load
= vmx_vcpu_load
,
10926 .vcpu_put
= vmx_vcpu_put
,
10928 .update_bp_intercept
= update_exception_bitmap
,
10929 .get_msr
= vmx_get_msr
,
10930 .set_msr
= vmx_set_msr
,
10931 .get_segment_base
= vmx_get_segment_base
,
10932 .get_segment
= vmx_get_segment
,
10933 .set_segment
= vmx_set_segment
,
10934 .get_cpl
= vmx_get_cpl
,
10935 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10936 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10937 .decache_cr3
= vmx_decache_cr3
,
10938 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10939 .set_cr0
= vmx_set_cr0
,
10940 .set_cr3
= vmx_set_cr3
,
10941 .set_cr4
= vmx_set_cr4
,
10942 .set_efer
= vmx_set_efer
,
10943 .get_idt
= vmx_get_idt
,
10944 .set_idt
= vmx_set_idt
,
10945 .get_gdt
= vmx_get_gdt
,
10946 .set_gdt
= vmx_set_gdt
,
10947 .get_dr6
= vmx_get_dr6
,
10948 .set_dr6
= vmx_set_dr6
,
10949 .set_dr7
= vmx_set_dr7
,
10950 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10951 .cache_reg
= vmx_cache_reg
,
10952 .get_rflags
= vmx_get_rflags
,
10953 .set_rflags
= vmx_set_rflags
,
10955 .get_pkru
= vmx_get_pkru
,
10957 .fpu_activate
= vmx_fpu_activate
,
10958 .fpu_deactivate
= vmx_fpu_deactivate
,
10960 .tlb_flush
= vmx_flush_tlb
,
10962 .run
= vmx_vcpu_run
,
10963 .handle_exit
= vmx_handle_exit
,
10964 .skip_emulated_instruction
= skip_emulated_instruction
,
10965 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10966 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10967 .patch_hypercall
= vmx_patch_hypercall
,
10968 .set_irq
= vmx_inject_irq
,
10969 .set_nmi
= vmx_inject_nmi
,
10970 .queue_exception
= vmx_queue_exception
,
10971 .cancel_injection
= vmx_cancel_injection
,
10972 .interrupt_allowed
= vmx_interrupt_allowed
,
10973 .nmi_allowed
= vmx_nmi_allowed
,
10974 .get_nmi_mask
= vmx_get_nmi_mask
,
10975 .set_nmi_mask
= vmx_set_nmi_mask
,
10976 .enable_nmi_window
= enable_nmi_window
,
10977 .enable_irq_window
= enable_irq_window
,
10978 .update_cr8_intercept
= update_cr8_intercept
,
10979 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10980 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10981 .get_enable_apicv
= vmx_get_enable_apicv
,
10982 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
10983 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10984 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10985 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10986 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10987 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10989 .set_tss_addr
= vmx_set_tss_addr
,
10990 .get_tdp_level
= get_ept_level
,
10991 .get_mt_mask
= vmx_get_mt_mask
,
10993 .get_exit_info
= vmx_get_exit_info
,
10995 .get_lpage_level
= vmx_get_lpage_level
,
10997 .cpuid_update
= vmx_cpuid_update
,
10999 .rdtscp_supported
= vmx_rdtscp_supported
,
11000 .invpcid_supported
= vmx_invpcid_supported
,
11002 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11004 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11006 .read_tsc_offset
= vmx_read_tsc_offset
,
11007 .write_tsc_offset
= vmx_write_tsc_offset
,
11008 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
11009 .read_l1_tsc
= vmx_read_l1_tsc
,
11011 .set_tdp_cr3
= vmx_set_cr3
,
11013 .check_intercept
= vmx_check_intercept
,
11014 .handle_external_intr
= vmx_handle_external_intr
,
11015 .mpx_supported
= vmx_mpx_supported
,
11016 .xsaves_supported
= vmx_xsaves_supported
,
11018 .check_nested_events
= vmx_check_nested_events
,
11020 .sched_in
= vmx_sched_in
,
11022 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11023 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11024 .flush_log_dirty
= vmx_flush_log_dirty
,
11025 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11027 .pre_block
= vmx_pre_block
,
11028 .post_block
= vmx_post_block
,
11030 .pmu_ops
= &intel_pmu_ops
,
11032 .update_pi_irte
= vmx_update_pi_irte
,
11035 static int __init
vmx_init(void)
11037 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11038 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11042 #ifdef CONFIG_KEXEC_CORE
11043 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11044 crash_vmclear_local_loaded_vmcss
);
11050 static void __exit
vmx_exit(void)
11052 #ifdef CONFIG_KEXEC_CORE
11053 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11060 module_init(vmx_init
)
11061 module_exit(vmx_exit
)