2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
35 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 static int __read_mostly bypass_guest_pf
= 1;
46 module_param(bypass_guest_pf
, bool, S_IRUGO
);
48 static int __read_mostly enable_vpid
= 1;
49 module_param_named(vpid
, enable_vpid
, bool, 0444);
51 static int __read_mostly flexpriority_enabled
= 1;
52 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
54 static int __read_mostly enable_ept
= 1;
55 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
57 static int __read_mostly enable_unrestricted_guest
= 1;
58 module_param_named(unrestricted_guest
,
59 enable_unrestricted_guest
, bool, S_IRUGO
);
61 static int __read_mostly emulate_invalid_guest_state
= 0;
62 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66 #define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70 #define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
72 #define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
90 #define KVM_VMX_DEFAULT_PLE_GAP 41
91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
93 module_param(ple_gap
, int, S_IRUGO
);
95 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
96 module_param(ple_window
, int, S_IRUGO
);
104 struct shared_msr_entry
{
111 struct kvm_vcpu vcpu
;
112 struct list_head local_vcpus_link
;
113 unsigned long host_rsp
;
116 u32 idt_vectoring_info
;
117 struct shared_msr_entry
*guest_msrs
;
121 u64 msr_host_kernel_gs_base
;
122 u64 msr_guest_kernel_gs_base
;
127 u16 fs_sel
, gs_sel
, ldt_sel
;
128 int gs_ldt_reload_needed
;
129 int fs_reload_needed
;
134 struct kvm_save_segment
{
139 } tr
, es
, ds
, fs
, gs
;
147 bool emulation_required
;
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked
;
152 s64 vnmi_blocked_time
;
158 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
160 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
163 static int init_rmode(struct kvm
*kvm
);
164 static u64
construct_eptp(unsigned long root_hpa
);
166 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
167 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
168 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
170 static unsigned long *vmx_io_bitmap_a
;
171 static unsigned long *vmx_io_bitmap_b
;
172 static unsigned long *vmx_msr_bitmap_legacy
;
173 static unsigned long *vmx_msr_bitmap_longmode
;
175 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
176 static DEFINE_SPINLOCK(vmx_vpid_lock
);
178 static struct vmcs_config
{
182 u32 pin_based_exec_ctrl
;
183 u32 cpu_based_exec_ctrl
;
184 u32 cpu_based_2nd_exec_ctrl
;
189 static struct vmx_capability
{
194 #define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
202 static struct kvm_vmx_segment_field
{
207 } kvm_vmx_segment_fields
[] = {
208 VMX_SEGMENT_FIELD(CS
),
209 VMX_SEGMENT_FIELD(DS
),
210 VMX_SEGMENT_FIELD(ES
),
211 VMX_SEGMENT_FIELD(FS
),
212 VMX_SEGMENT_FIELD(GS
),
213 VMX_SEGMENT_FIELD(SS
),
214 VMX_SEGMENT_FIELD(TR
),
215 VMX_SEGMENT_FIELD(LDTR
),
218 static u64 host_efer
;
220 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
226 static const u32 vmx_msr_index
[] = {
228 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
230 MSR_EFER
, MSR_TSC_AUX
, MSR_K6_STAR
,
232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
234 static inline int is_page_fault(u32 intr_info
)
236 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
237 INTR_INFO_VALID_MASK
)) ==
238 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
241 static inline int is_no_device(u32 intr_info
)
243 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
244 INTR_INFO_VALID_MASK
)) ==
245 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
248 static inline int is_invalid_opcode(u32 intr_info
)
250 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
251 INTR_INFO_VALID_MASK
)) ==
252 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
255 static inline int is_external_interrupt(u32 intr_info
)
257 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
258 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
261 static inline int is_machine_check(u32 intr_info
)
263 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
264 INTR_INFO_VALID_MASK
)) ==
265 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
268 static inline int cpu_has_vmx_msr_bitmap(void)
270 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
273 static inline int cpu_has_vmx_tpr_shadow(void)
275 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
278 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
283 static inline int cpu_has_secondary_exec_ctrls(void)
285 return vmcs_config
.cpu_based_exec_ctrl
&
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
295 static inline bool cpu_has_vmx_flexpriority(void)
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
301 static inline bool cpu_has_vmx_ept_execute_only(void)
303 return !!(vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
);
306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
308 return !!(vmx_capability
.ept
& VMX_EPTP_UC_BIT
);
311 static inline bool cpu_has_vmx_eptp_writeback(void)
313 return !!(vmx_capability
.ept
& VMX_EPTP_WB_BIT
);
316 static inline bool cpu_has_vmx_ept_2m_page(void)
318 return !!(vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
);
321 static inline int cpu_has_vmx_invept_individual_addr(void)
323 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
);
326 static inline int cpu_has_vmx_invept_context(void)
328 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
);
331 static inline int cpu_has_vmx_invept_global(void)
333 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
);
336 static inline int cpu_has_vmx_ept(void)
338 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
339 SECONDARY_EXEC_ENABLE_EPT
;
342 static inline int cpu_has_vmx_unrestricted_guest(void)
344 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
345 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
348 static inline int cpu_has_vmx_ple(void)
350 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
351 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
354 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
356 return flexpriority_enabled
&&
357 (cpu_has_vmx_virtualize_apic_accesses()) &&
358 (irqchip_in_kernel(kvm
));
361 static inline int cpu_has_vmx_vpid(void)
363 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
364 SECONDARY_EXEC_ENABLE_VPID
;
367 static inline int cpu_has_vmx_rdtscp(void)
369 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
370 SECONDARY_EXEC_RDTSCP
;
373 static inline int cpu_has_virtual_nmis(void)
375 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
378 static inline bool report_flexpriority(void)
380 return flexpriority_enabled
;
383 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
387 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
388 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
393 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
399 } operand
= { vpid
, 0, gva
};
401 asm volatile (__ex(ASM_VMX_INVVPID
)
402 /* CF==1 or ZF==1 --> rc = -1 */
404 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
407 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
411 } operand
= {eptp
, gpa
};
413 asm volatile (__ex(ASM_VMX_INVEPT
)
414 /* CF==1 or ZF==1 --> rc = -1 */
415 "; ja 1f ; ud2 ; 1:\n"
416 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
419 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
423 i
= __find_msr_index(vmx
, msr
);
425 return &vmx
->guest_msrs
[i
];
429 static void vmcs_clear(struct vmcs
*vmcs
)
431 u64 phys_addr
= __pa(vmcs
);
434 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
435 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
438 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
442 static void __vcpu_clear(void *arg
)
444 struct vcpu_vmx
*vmx
= arg
;
445 int cpu
= raw_smp_processor_id();
447 if (vmx
->vcpu
.cpu
== cpu
)
448 vmcs_clear(vmx
->vmcs
);
449 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
450 per_cpu(current_vmcs
, cpu
) = NULL
;
451 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
452 list_del(&vmx
->local_vcpus_link
);
457 static void vcpu_clear(struct vcpu_vmx
*vmx
)
459 if (vmx
->vcpu
.cpu
== -1)
461 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
464 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
469 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
472 static inline void ept_sync_global(void)
474 if (cpu_has_vmx_invept_global())
475 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
478 static inline void ept_sync_context(u64 eptp
)
481 if (cpu_has_vmx_invept_context())
482 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
488 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
491 if (cpu_has_vmx_invept_individual_addr())
492 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
495 ept_sync_context(eptp
);
499 static unsigned long vmcs_readl(unsigned long field
)
503 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
504 : "=a"(value
) : "d"(field
) : "cc");
508 static u16
vmcs_read16(unsigned long field
)
510 return vmcs_readl(field
);
513 static u32
vmcs_read32(unsigned long field
)
515 return vmcs_readl(field
);
518 static u64
vmcs_read64(unsigned long field
)
521 return vmcs_readl(field
);
523 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
527 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
529 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
530 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
534 static void vmcs_writel(unsigned long field
, unsigned long value
)
538 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
539 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
541 vmwrite_error(field
, value
);
544 static void vmcs_write16(unsigned long field
, u16 value
)
546 vmcs_writel(field
, value
);
549 static void vmcs_write32(unsigned long field
, u32 value
)
551 vmcs_writel(field
, value
);
554 static void vmcs_write64(unsigned long field
, u64 value
)
556 vmcs_writel(field
, value
);
557 #ifndef CONFIG_X86_64
559 vmcs_writel(field
+1, value
>> 32);
563 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
565 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
568 static void vmcs_set_bits(unsigned long field
, u32 mask
)
570 vmcs_writel(field
, vmcs_readl(field
) | mask
);
573 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
577 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
);
578 if (!vcpu
->fpu_active
)
579 eb
|= 1u << NM_VECTOR
;
581 * Unconditionally intercept #DB so we can maintain dr6 without
582 * reading it every exit.
584 eb
|= 1u << DB_VECTOR
;
585 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
586 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
587 eb
|= 1u << BP_VECTOR
;
589 if (to_vmx(vcpu
)->rmode
.vm86_active
)
592 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
593 vmcs_write32(EXCEPTION_BITMAP
, eb
);
596 static void reload_tss(void)
599 * VT restores TR but not its size. Useless.
601 struct descriptor_table gdt
;
602 struct desc_struct
*descs
;
605 descs
= (void *)gdt
.base
;
606 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
610 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
615 guest_efer
= vmx
->vcpu
.arch
.shadow_efer
;
618 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
621 ignore_bits
= EFER_NX
| EFER_SCE
;
623 ignore_bits
|= EFER_LMA
| EFER_LME
;
624 /* SCE is meaningful only in long mode on Intel */
625 if (guest_efer
& EFER_LMA
)
626 ignore_bits
&= ~(u64
)EFER_SCE
;
628 guest_efer
&= ~ignore_bits
;
629 guest_efer
|= host_efer
& ignore_bits
;
630 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
631 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
635 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
637 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
640 if (vmx
->host_state
.loaded
)
643 vmx
->host_state
.loaded
= 1;
645 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
646 * allow segment selectors with cpl > 0 or ti == 1.
648 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
649 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
650 vmx
->host_state
.fs_sel
= kvm_read_fs();
651 if (!(vmx
->host_state
.fs_sel
& 7)) {
652 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
653 vmx
->host_state
.fs_reload_needed
= 0;
655 vmcs_write16(HOST_FS_SELECTOR
, 0);
656 vmx
->host_state
.fs_reload_needed
= 1;
658 vmx
->host_state
.gs_sel
= kvm_read_gs();
659 if (!(vmx
->host_state
.gs_sel
& 7))
660 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
662 vmcs_write16(HOST_GS_SELECTOR
, 0);
663 vmx
->host_state
.gs_ldt_reload_needed
= 1;
667 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
668 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
670 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
671 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
675 if (is_long_mode(&vmx
->vcpu
)) {
676 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
677 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
680 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
681 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
682 vmx
->guest_msrs
[i
].data
,
683 vmx
->guest_msrs
[i
].mask
);
686 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
690 if (!vmx
->host_state
.loaded
)
693 ++vmx
->vcpu
.stat
.host_state_reload
;
694 vmx
->host_state
.loaded
= 0;
695 if (vmx
->host_state
.fs_reload_needed
)
696 kvm_load_fs(vmx
->host_state
.fs_sel
);
697 if (vmx
->host_state
.gs_ldt_reload_needed
) {
698 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
700 * If we have to reload gs, we must take care to
701 * preserve our gs base.
703 local_irq_save(flags
);
704 kvm_load_gs(vmx
->host_state
.gs_sel
);
706 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
708 local_irq_restore(flags
);
712 if (is_long_mode(&vmx
->vcpu
)) {
713 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
714 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
719 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
722 __vmx_load_host_state(vmx
);
727 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
728 * vcpu mutex is already taken.
730 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
732 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
733 u64 phys_addr
= __pa(vmx
->vmcs
);
734 u64 tsc_this
, delta
, new_offset
;
736 if (vcpu
->cpu
!= cpu
) {
738 kvm_migrate_timers(vcpu
);
739 set_bit(KVM_REQ_TLB_FLUSH
, &vcpu
->requests
);
741 list_add(&vmx
->local_vcpus_link
,
742 &per_cpu(vcpus_on_cpu
, cpu
));
746 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
749 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
750 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
751 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
754 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
755 vmx
->vmcs
, phys_addr
);
758 if (vcpu
->cpu
!= cpu
) {
759 struct descriptor_table dt
;
760 unsigned long sysenter_esp
;
764 * Linux uses per-cpu TSS and GDT, so set these when switching
767 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
769 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
771 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
772 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
775 * Make sure the time stamp counter is monotonous.
778 if (tsc_this
< vcpu
->arch
.host_tsc
) {
779 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
780 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
781 vmcs_write64(TSC_OFFSET
, new_offset
);
786 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
788 __vmx_load_host_state(to_vmx(vcpu
));
791 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
793 if (vcpu
->fpu_active
)
795 vcpu
->fpu_active
= 1;
796 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
797 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
798 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
799 update_exception_bitmap(vcpu
);
802 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
804 if (!vcpu
->fpu_active
)
806 vcpu
->fpu_active
= 0;
807 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
808 update_exception_bitmap(vcpu
);
811 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
813 unsigned long rflags
;
815 rflags
= vmcs_readl(GUEST_RFLAGS
);
816 if (to_vmx(vcpu
)->rmode
.vm86_active
)
817 rflags
&= ~(unsigned long)(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
821 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
823 if (to_vmx(vcpu
)->rmode
.vm86_active
)
824 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
825 vmcs_writel(GUEST_RFLAGS
, rflags
);
828 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
830 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
833 if (interruptibility
& GUEST_INTR_STATE_STI
)
834 ret
|= X86_SHADOW_INT_STI
;
835 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
836 ret
|= X86_SHADOW_INT_MOV_SS
;
841 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
843 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
844 u32 interruptibility
= interruptibility_old
;
846 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
848 if (mask
& X86_SHADOW_INT_MOV_SS
)
849 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
850 if (mask
& X86_SHADOW_INT_STI
)
851 interruptibility
|= GUEST_INTR_STATE_STI
;
853 if ((interruptibility
!= interruptibility_old
))
854 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
857 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
861 rip
= kvm_rip_read(vcpu
);
862 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
863 kvm_rip_write(vcpu
, rip
);
865 /* skipping an emulated instruction also counts */
866 vmx_set_interrupt_shadow(vcpu
, 0);
869 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
870 bool has_error_code
, u32 error_code
)
872 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
873 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
875 if (has_error_code
) {
876 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
877 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
880 if (vmx
->rmode
.vm86_active
) {
881 vmx
->rmode
.irq
.pending
= true;
882 vmx
->rmode
.irq
.vector
= nr
;
883 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
884 if (kvm_exception_is_soft(nr
))
885 vmx
->rmode
.irq
.rip
+=
886 vmx
->vcpu
.arch
.event_exit_inst_len
;
887 intr_info
|= INTR_TYPE_SOFT_INTR
;
888 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
889 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
890 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
894 if (kvm_exception_is_soft(nr
)) {
895 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
896 vmx
->vcpu
.arch
.event_exit_inst_len
);
897 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
899 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
901 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
904 static bool vmx_rdtscp_supported(void)
906 return cpu_has_vmx_rdtscp();
910 * Swap MSR entry in host/guest MSR entry array.
912 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
914 struct shared_msr_entry tmp
;
916 tmp
= vmx
->guest_msrs
[to
];
917 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
918 vmx
->guest_msrs
[from
] = tmp
;
922 * Set up the vmcs to automatically save and restore system
923 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
924 * mode, as fiddling with msrs is very expensive.
926 static void setup_msrs(struct vcpu_vmx
*vmx
)
928 int save_nmsrs
, index
;
929 unsigned long *msr_bitmap
;
931 vmx_load_host_state(vmx
);
934 if (is_long_mode(&vmx
->vcpu
)) {
935 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
937 move_msr_up(vmx
, index
, save_nmsrs
++);
938 index
= __find_msr_index(vmx
, MSR_LSTAR
);
940 move_msr_up(vmx
, index
, save_nmsrs
++);
941 index
= __find_msr_index(vmx
, MSR_CSTAR
);
943 move_msr_up(vmx
, index
, save_nmsrs
++);
944 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
945 if (index
>= 0 && vmx
->rdtscp_enabled
)
946 move_msr_up(vmx
, index
, save_nmsrs
++);
948 * MSR_K6_STAR is only needed on long mode guests, and only
949 * if efer.sce is enabled.
951 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
952 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
953 move_msr_up(vmx
, index
, save_nmsrs
++);
956 index
= __find_msr_index(vmx
, MSR_EFER
);
957 if (index
>= 0 && update_transition_efer(vmx
, index
))
958 move_msr_up(vmx
, index
, save_nmsrs
++);
960 vmx
->save_nmsrs
= save_nmsrs
;
962 if (cpu_has_vmx_msr_bitmap()) {
963 if (is_long_mode(&vmx
->vcpu
))
964 msr_bitmap
= vmx_msr_bitmap_longmode
;
966 msr_bitmap
= vmx_msr_bitmap_legacy
;
968 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
973 * reads and returns guest's timestamp counter "register"
974 * guest_tsc = host_tsc + tsc_offset -- 21.3
976 static u64
guest_read_tsc(void)
978 u64 host_tsc
, tsc_offset
;
981 tsc_offset
= vmcs_read64(TSC_OFFSET
);
982 return host_tsc
+ tsc_offset
;
986 * writes 'guest_tsc' into guest's timestamp counter "register"
987 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
989 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
991 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
995 * Reads an msr value (of 'msr_index') into 'pdata'.
996 * Returns 0 on success, non-0 otherwise.
997 * Assumes vcpu_load() was already called.
999 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1002 struct shared_msr_entry
*msr
;
1005 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1009 switch (msr_index
) {
1010 #ifdef CONFIG_X86_64
1012 data
= vmcs_readl(GUEST_FS_BASE
);
1015 data
= vmcs_readl(GUEST_GS_BASE
);
1017 case MSR_KERNEL_GS_BASE
:
1018 vmx_load_host_state(to_vmx(vcpu
));
1019 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1023 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1025 data
= guest_read_tsc();
1027 case MSR_IA32_SYSENTER_CS
:
1028 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1030 case MSR_IA32_SYSENTER_EIP
:
1031 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1033 case MSR_IA32_SYSENTER_ESP
:
1034 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1037 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1039 /* Otherwise falls through */
1041 vmx_load_host_state(to_vmx(vcpu
));
1042 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1044 vmx_load_host_state(to_vmx(vcpu
));
1048 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1056 * Writes msr value into into the appropriate "register".
1057 * Returns 0 on success, non-0 otherwise.
1058 * Assumes vcpu_load() was already called.
1060 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1062 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1063 struct shared_msr_entry
*msr
;
1067 switch (msr_index
) {
1069 vmx_load_host_state(vmx
);
1070 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1072 #ifdef CONFIG_X86_64
1074 vmcs_writel(GUEST_FS_BASE
, data
);
1077 vmcs_writel(GUEST_GS_BASE
, data
);
1079 case MSR_KERNEL_GS_BASE
:
1080 vmx_load_host_state(vmx
);
1081 vmx
->msr_guest_kernel_gs_base
= data
;
1084 case MSR_IA32_SYSENTER_CS
:
1085 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1087 case MSR_IA32_SYSENTER_EIP
:
1088 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1090 case MSR_IA32_SYSENTER_ESP
:
1091 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1095 guest_write_tsc(data
, host_tsc
);
1097 case MSR_IA32_CR_PAT
:
1098 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1099 vmcs_write64(GUEST_IA32_PAT
, data
);
1100 vcpu
->arch
.pat
= data
;
1103 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1106 if (!vmx
->rdtscp_enabled
)
1108 /* Check reserved bit, higher 32 bits should be zero */
1109 if ((data
>> 32) != 0)
1111 /* Otherwise falls through */
1113 msr
= find_msr_entry(vmx
, msr_index
);
1115 vmx_load_host_state(vmx
);
1119 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1125 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1127 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1130 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1133 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1135 case VCPU_EXREG_PDPTR
:
1137 ept_save_pdptrs(vcpu
);
1144 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1146 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1147 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1149 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1151 update_exception_bitmap(vcpu
);
1154 static __init
int cpu_has_kvm_support(void)
1156 return cpu_has_vmx();
1159 static __init
int vmx_disabled_by_bios(void)
1163 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1164 return (msr
& (FEATURE_CONTROL_LOCKED
|
1165 FEATURE_CONTROL_VMXON_ENABLED
))
1166 == FEATURE_CONTROL_LOCKED
;
1167 /* locked but not enabled */
1170 static int hardware_enable(void *garbage
)
1172 int cpu
= raw_smp_processor_id();
1173 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1176 if (read_cr4() & X86_CR4_VMXE
)
1179 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1180 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1181 if ((old
& (FEATURE_CONTROL_LOCKED
|
1182 FEATURE_CONTROL_VMXON_ENABLED
))
1183 != (FEATURE_CONTROL_LOCKED
|
1184 FEATURE_CONTROL_VMXON_ENABLED
))
1185 /* enable and lock */
1186 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
1187 FEATURE_CONTROL_LOCKED
|
1188 FEATURE_CONTROL_VMXON_ENABLED
);
1189 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1190 asm volatile (ASM_VMX_VMXON_RAX
1191 : : "a"(&phys_addr
), "m"(phys_addr
)
1199 static void vmclear_local_vcpus(void)
1201 int cpu
= raw_smp_processor_id();
1202 struct vcpu_vmx
*vmx
, *n
;
1204 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1210 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1213 static void kvm_cpu_vmxoff(void)
1215 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1216 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1219 static void hardware_disable(void *garbage
)
1221 vmclear_local_vcpus();
1225 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1226 u32 msr
, u32
*result
)
1228 u32 vmx_msr_low
, vmx_msr_high
;
1229 u32 ctl
= ctl_min
| ctl_opt
;
1231 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1233 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1234 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1236 /* Ensure minimum (required) set of control bits are supported. */
1244 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1246 u32 vmx_msr_low
, vmx_msr_high
;
1247 u32 min
, opt
, min2
, opt2
;
1248 u32 _pin_based_exec_control
= 0;
1249 u32 _cpu_based_exec_control
= 0;
1250 u32 _cpu_based_2nd_exec_control
= 0;
1251 u32 _vmexit_control
= 0;
1252 u32 _vmentry_control
= 0;
1254 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1255 opt
= PIN_BASED_VIRTUAL_NMIS
;
1256 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1257 &_pin_based_exec_control
) < 0)
1260 min
= CPU_BASED_HLT_EXITING
|
1261 #ifdef CONFIG_X86_64
1262 CPU_BASED_CR8_LOAD_EXITING
|
1263 CPU_BASED_CR8_STORE_EXITING
|
1265 CPU_BASED_CR3_LOAD_EXITING
|
1266 CPU_BASED_CR3_STORE_EXITING
|
1267 CPU_BASED_USE_IO_BITMAPS
|
1268 CPU_BASED_MOV_DR_EXITING
|
1269 CPU_BASED_USE_TSC_OFFSETING
|
1270 CPU_BASED_MWAIT_EXITING
|
1271 CPU_BASED_MONITOR_EXITING
|
1272 CPU_BASED_INVLPG_EXITING
;
1273 opt
= CPU_BASED_TPR_SHADOW
|
1274 CPU_BASED_USE_MSR_BITMAPS
|
1275 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1276 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1277 &_cpu_based_exec_control
) < 0)
1279 #ifdef CONFIG_X86_64
1280 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1281 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1282 ~CPU_BASED_CR8_STORE_EXITING
;
1284 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1286 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1287 SECONDARY_EXEC_WBINVD_EXITING
|
1288 SECONDARY_EXEC_ENABLE_VPID
|
1289 SECONDARY_EXEC_ENABLE_EPT
|
1290 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1291 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1292 SECONDARY_EXEC_RDTSCP
;
1293 if (adjust_vmx_controls(min2
, opt2
,
1294 MSR_IA32_VMX_PROCBASED_CTLS2
,
1295 &_cpu_based_2nd_exec_control
) < 0)
1298 #ifndef CONFIG_X86_64
1299 if (!(_cpu_based_2nd_exec_control
&
1300 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1301 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1303 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1304 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1306 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1307 CPU_BASED_CR3_STORE_EXITING
|
1308 CPU_BASED_INVLPG_EXITING
);
1309 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1310 vmx_capability
.ept
, vmx_capability
.vpid
);
1314 #ifdef CONFIG_X86_64
1315 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1317 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1318 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1319 &_vmexit_control
) < 0)
1323 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1324 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1325 &_vmentry_control
) < 0)
1328 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1330 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1331 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1334 #ifdef CONFIG_X86_64
1335 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1336 if (vmx_msr_high
& (1u<<16))
1340 /* Require Write-Back (WB) memory type for VMCS accesses. */
1341 if (((vmx_msr_high
>> 18) & 15) != 6)
1344 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1345 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1346 vmcs_conf
->revision_id
= vmx_msr_low
;
1348 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1349 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1350 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1351 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1352 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1357 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1359 int node
= cpu_to_node(cpu
);
1363 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1366 vmcs
= page_address(pages
);
1367 memset(vmcs
, 0, vmcs_config
.size
);
1368 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1372 static struct vmcs
*alloc_vmcs(void)
1374 return alloc_vmcs_cpu(raw_smp_processor_id());
1377 static void free_vmcs(struct vmcs
*vmcs
)
1379 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1382 static void free_kvm_area(void)
1386 for_each_possible_cpu(cpu
) {
1387 free_vmcs(per_cpu(vmxarea
, cpu
));
1388 per_cpu(vmxarea
, cpu
) = NULL
;
1392 static __init
int alloc_kvm_area(void)
1396 for_each_possible_cpu(cpu
) {
1399 vmcs
= alloc_vmcs_cpu(cpu
);
1405 per_cpu(vmxarea
, cpu
) = vmcs
;
1410 static __init
int hardware_setup(void)
1412 if (setup_vmcs_config(&vmcs_config
) < 0)
1415 if (boot_cpu_has(X86_FEATURE_NX
))
1416 kvm_enable_efer_bits(EFER_NX
);
1418 if (!cpu_has_vmx_vpid())
1421 if (!cpu_has_vmx_ept()) {
1423 enable_unrestricted_guest
= 0;
1426 if (!cpu_has_vmx_unrestricted_guest())
1427 enable_unrestricted_guest
= 0;
1429 if (!cpu_has_vmx_flexpriority())
1430 flexpriority_enabled
= 0;
1432 if (!cpu_has_vmx_tpr_shadow())
1433 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1435 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1436 kvm_disable_largepages();
1438 if (!cpu_has_vmx_ple())
1441 return alloc_kvm_area();
1444 static __exit
void hardware_unsetup(void)
1449 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1451 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1453 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1454 vmcs_write16(sf
->selector
, save
->selector
);
1455 vmcs_writel(sf
->base
, save
->base
);
1456 vmcs_write32(sf
->limit
, save
->limit
);
1457 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1459 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1461 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1465 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1467 unsigned long flags
;
1468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1470 vmx
->emulation_required
= 1;
1471 vmx
->rmode
.vm86_active
= 0;
1473 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1474 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1475 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1477 flags
= vmcs_readl(GUEST_RFLAGS
);
1478 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1479 flags
|= (vmx
->rmode
.save_iopl
<< IOPL_SHIFT
);
1480 vmcs_writel(GUEST_RFLAGS
, flags
);
1482 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1483 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1485 update_exception_bitmap(vcpu
);
1487 if (emulate_invalid_guest_state
)
1490 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1491 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1492 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1493 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1495 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1496 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1498 vmcs_write16(GUEST_CS_SELECTOR
,
1499 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1500 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1503 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1505 if (!kvm
->arch
.tss_addr
) {
1506 struct kvm_memslots
*slots
;
1509 slots
= rcu_dereference(kvm
->memslots
);
1510 base_gfn
= kvm
->memslots
->memslots
[0].base_gfn
+
1511 kvm
->memslots
->memslots
[0].npages
- 3;
1512 return base_gfn
<< PAGE_SHIFT
;
1514 return kvm
->arch
.tss_addr
;
1517 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1519 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1521 save
->selector
= vmcs_read16(sf
->selector
);
1522 save
->base
= vmcs_readl(sf
->base
);
1523 save
->limit
= vmcs_read32(sf
->limit
);
1524 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1525 vmcs_write16(sf
->selector
, save
->base
>> 4);
1526 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1527 vmcs_write32(sf
->limit
, 0xffff);
1528 vmcs_write32(sf
->ar_bytes
, 0xf3);
1531 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1533 unsigned long flags
;
1534 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1536 if (enable_unrestricted_guest
)
1539 vmx
->emulation_required
= 1;
1540 vmx
->rmode
.vm86_active
= 1;
1542 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1543 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1545 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1546 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1548 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1549 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1551 flags
= vmcs_readl(GUEST_RFLAGS
);
1552 vmx
->rmode
.save_iopl
1553 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1555 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1557 vmcs_writel(GUEST_RFLAGS
, flags
);
1558 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1559 update_exception_bitmap(vcpu
);
1561 if (emulate_invalid_guest_state
)
1562 goto continue_rmode
;
1564 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1565 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1566 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1568 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1569 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1570 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1571 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1572 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1574 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1575 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1576 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1577 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1580 kvm_mmu_reset_context(vcpu
);
1581 init_rmode(vcpu
->kvm
);
1584 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1586 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1587 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1593 * Force kernel_gs_base reloading before EFER changes, as control
1594 * of this msr depends on is_long_mode().
1596 vmx_load_host_state(to_vmx(vcpu
));
1597 vcpu
->arch
.shadow_efer
= efer
;
1600 if (efer
& EFER_LMA
) {
1601 vmcs_write32(VM_ENTRY_CONTROLS
,
1602 vmcs_read32(VM_ENTRY_CONTROLS
) |
1603 VM_ENTRY_IA32E_MODE
);
1606 vmcs_write32(VM_ENTRY_CONTROLS
,
1607 vmcs_read32(VM_ENTRY_CONTROLS
) &
1608 ~VM_ENTRY_IA32E_MODE
);
1610 msr
->data
= efer
& ~EFER_LME
;
1615 #ifdef CONFIG_X86_64
1617 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1621 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1622 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1623 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1625 vmcs_write32(GUEST_TR_AR_BYTES
,
1626 (guest_tr_ar
& ~AR_TYPE_MASK
)
1627 | AR_TYPE_BUSY_64_TSS
);
1629 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1630 vmx_set_efer(vcpu
, vcpu
->arch
.shadow_efer
);
1633 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1635 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1637 vmcs_write32(VM_ENTRY_CONTROLS
,
1638 vmcs_read32(VM_ENTRY_CONTROLS
)
1639 & ~VM_ENTRY_IA32E_MODE
);
1644 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1646 vpid_sync_vcpu_all(to_vmx(vcpu
));
1648 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1651 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1653 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1655 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1656 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1659 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1661 if (!test_bit(VCPU_EXREG_PDPTR
,
1662 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1665 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1666 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1667 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1668 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1669 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1673 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1675 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1676 vcpu
->arch
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1677 vcpu
->arch
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1678 vcpu
->arch
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1679 vcpu
->arch
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1682 __set_bit(VCPU_EXREG_PDPTR
,
1683 (unsigned long *)&vcpu
->arch
.regs_avail
);
1684 __set_bit(VCPU_EXREG_PDPTR
,
1685 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1688 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1690 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1692 struct kvm_vcpu
*vcpu
)
1694 if (!(cr0
& X86_CR0_PG
)) {
1695 /* From paging/starting to nonpaging */
1696 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1697 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1698 (CPU_BASED_CR3_LOAD_EXITING
|
1699 CPU_BASED_CR3_STORE_EXITING
));
1700 vcpu
->arch
.cr0
= cr0
;
1701 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1702 } else if (!is_paging(vcpu
)) {
1703 /* From nonpaging to paging */
1704 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1705 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1706 ~(CPU_BASED_CR3_LOAD_EXITING
|
1707 CPU_BASED_CR3_STORE_EXITING
));
1708 vcpu
->arch
.cr0
= cr0
;
1709 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1712 if (!(cr0
& X86_CR0_WP
))
1713 *hw_cr0
&= ~X86_CR0_WP
;
1716 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1718 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1719 unsigned long hw_cr0
;
1721 if (enable_unrestricted_guest
)
1722 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1723 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1725 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1727 vmx_fpu_deactivate(vcpu
);
1729 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1732 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1735 #ifdef CONFIG_X86_64
1736 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1737 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1739 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1745 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1747 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1748 vmcs_writel(GUEST_CR0
, hw_cr0
);
1749 vcpu
->arch
.cr0
= cr0
;
1751 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1752 vmx_fpu_activate(vcpu
);
1755 static u64
construct_eptp(unsigned long root_hpa
)
1759 /* TODO write the value reading from MSR */
1760 eptp
= VMX_EPT_DEFAULT_MT
|
1761 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1762 eptp
|= (root_hpa
& PAGE_MASK
);
1767 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1769 unsigned long guest_cr3
;
1774 eptp
= construct_eptp(cr3
);
1775 vmcs_write64(EPT_POINTER
, eptp
);
1776 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1777 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1778 ept_load_pdptrs(vcpu
);
1781 vmx_flush_tlb(vcpu
);
1782 vmcs_writel(GUEST_CR3
, guest_cr3
);
1783 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1784 vmx_fpu_deactivate(vcpu
);
1787 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1789 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1790 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1792 vcpu
->arch
.cr4
= cr4
;
1794 if (!is_paging(vcpu
)) {
1795 hw_cr4
&= ~X86_CR4_PAE
;
1796 hw_cr4
|= X86_CR4_PSE
;
1797 } else if (!(cr4
& X86_CR4_PAE
)) {
1798 hw_cr4
&= ~X86_CR4_PAE
;
1802 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1803 vmcs_writel(GUEST_CR4
, hw_cr4
);
1806 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1808 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1810 return vmcs_readl(sf
->base
);
1813 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1814 struct kvm_segment
*var
, int seg
)
1816 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1819 var
->base
= vmcs_readl(sf
->base
);
1820 var
->limit
= vmcs_read32(sf
->limit
);
1821 var
->selector
= vmcs_read16(sf
->selector
);
1822 ar
= vmcs_read32(sf
->ar_bytes
);
1823 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1825 var
->type
= ar
& 15;
1826 var
->s
= (ar
>> 4) & 1;
1827 var
->dpl
= (ar
>> 5) & 3;
1828 var
->present
= (ar
>> 7) & 1;
1829 var
->avl
= (ar
>> 12) & 1;
1830 var
->l
= (ar
>> 13) & 1;
1831 var
->db
= (ar
>> 14) & 1;
1832 var
->g
= (ar
>> 15) & 1;
1833 var
->unusable
= (ar
>> 16) & 1;
1836 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1838 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) /* if real mode */
1841 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1844 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
1847 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1854 ar
= var
->type
& 15;
1855 ar
|= (var
->s
& 1) << 4;
1856 ar
|= (var
->dpl
& 3) << 5;
1857 ar
|= (var
->present
& 1) << 7;
1858 ar
|= (var
->avl
& 1) << 12;
1859 ar
|= (var
->l
& 1) << 13;
1860 ar
|= (var
->db
& 1) << 14;
1861 ar
|= (var
->g
& 1) << 15;
1863 if (ar
== 0) /* a 0 value means unusable */
1864 ar
= AR_UNUSABLE_MASK
;
1869 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1870 struct kvm_segment
*var
, int seg
)
1872 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1873 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1876 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
1877 vmx
->rmode
.tr
.selector
= var
->selector
;
1878 vmx
->rmode
.tr
.base
= var
->base
;
1879 vmx
->rmode
.tr
.limit
= var
->limit
;
1880 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1883 vmcs_writel(sf
->base
, var
->base
);
1884 vmcs_write32(sf
->limit
, var
->limit
);
1885 vmcs_write16(sf
->selector
, var
->selector
);
1886 if (vmx
->rmode
.vm86_active
&& var
->s
) {
1888 * Hack real-mode segments into vm86 compatibility.
1890 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1891 vmcs_writel(sf
->base
, 0xf0000);
1894 ar
= vmx_segment_access_rights(var
);
1897 * Fix the "Accessed" bit in AR field of segment registers for older
1899 * IA32 arch specifies that at the time of processor reset the
1900 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1901 * is setting it to 0 in the usedland code. This causes invalid guest
1902 * state vmexit when "unrestricted guest" mode is turned on.
1903 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1904 * tree. Newer qemu binaries with that qemu fix would not need this
1907 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
1908 ar
|= 0x1; /* Accessed */
1910 vmcs_write32(sf
->ar_bytes
, ar
);
1913 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1915 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1917 *db
= (ar
>> 14) & 1;
1918 *l
= (ar
>> 13) & 1;
1921 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1923 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1924 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1927 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1929 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1930 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1933 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1935 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1936 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1939 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1941 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1942 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1945 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1947 struct kvm_segment var
;
1950 vmx_get_segment(vcpu
, &var
, seg
);
1951 ar
= vmx_segment_access_rights(&var
);
1953 if (var
.base
!= (var
.selector
<< 4))
1955 if (var
.limit
!= 0xffff)
1963 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
1965 struct kvm_segment cs
;
1966 unsigned int cs_rpl
;
1968 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1969 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
1973 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
1977 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
1978 if (cs
.dpl
> cs_rpl
)
1981 if (cs
.dpl
!= cs_rpl
)
1987 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1991 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
1993 struct kvm_segment ss
;
1994 unsigned int ss_rpl
;
1996 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1997 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2001 if (ss
.type
!= 3 && ss
.type
!= 7)
2005 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2013 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2015 struct kvm_segment var
;
2018 vmx_get_segment(vcpu
, &var
, seg
);
2019 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2027 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2028 if (var
.dpl
< rpl
) /* DPL < RPL */
2032 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2038 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2040 struct kvm_segment tr
;
2042 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2046 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2048 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2056 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2058 struct kvm_segment ldtr
;
2060 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2064 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2074 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2076 struct kvm_segment cs
, ss
;
2078 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2079 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2081 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2082 (ss
.selector
& SELECTOR_RPL_MASK
));
2086 * Check if guest state is valid. Returns true if valid, false if
2088 * We assume that registers are always usable
2090 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2092 /* real mode guest state checks */
2093 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) {
2094 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2096 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2098 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2100 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2102 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2104 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2107 /* protected mode guest state checks */
2108 if (!cs_ss_rpl_check(vcpu
))
2110 if (!code_segment_valid(vcpu
))
2112 if (!stack_segment_valid(vcpu
))
2114 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2116 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2118 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2120 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2122 if (!tr_valid(vcpu
))
2124 if (!ldtr_valid(vcpu
))
2128 * - Add checks on RIP
2129 * - Add checks on RFLAGS
2135 static int init_rmode_tss(struct kvm
*kvm
)
2137 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2142 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2145 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2146 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2147 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2150 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2153 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2157 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2158 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2168 static int init_rmode_identity_map(struct kvm
*kvm
)
2171 pfn_t identity_map_pfn
;
2176 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2177 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2178 "haven't been allocated!\n");
2181 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2184 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2185 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2188 /* Set up identity-mapping pagetable for EPT in real mode */
2189 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2190 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2191 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2192 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2193 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2197 kvm
->arch
.ept_identity_pagetable_done
= true;
2203 static void seg_setup(int seg
)
2205 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2208 vmcs_write16(sf
->selector
, 0);
2209 vmcs_writel(sf
->base
, 0);
2210 vmcs_write32(sf
->limit
, 0xffff);
2211 if (enable_unrestricted_guest
) {
2213 if (seg
== VCPU_SREG_CS
)
2214 ar
|= 0x08; /* code segment */
2218 vmcs_write32(sf
->ar_bytes
, ar
);
2221 static int alloc_apic_access_page(struct kvm
*kvm
)
2223 struct kvm_userspace_memory_region kvm_userspace_mem
;
2226 mutex_lock(&kvm
->slots_lock
);
2227 if (kvm
->arch
.apic_access_page
)
2229 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2230 kvm_userspace_mem
.flags
= 0;
2231 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2232 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2233 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2237 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2239 mutex_unlock(&kvm
->slots_lock
);
2243 static int alloc_identity_pagetable(struct kvm
*kvm
)
2245 struct kvm_userspace_memory_region kvm_userspace_mem
;
2248 mutex_lock(&kvm
->slots_lock
);
2249 if (kvm
->arch
.ept_identity_pagetable
)
2251 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2252 kvm_userspace_mem
.flags
= 0;
2253 kvm_userspace_mem
.guest_phys_addr
=
2254 kvm
->arch
.ept_identity_map_addr
;
2255 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2256 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2260 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2261 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2263 mutex_unlock(&kvm
->slots_lock
);
2267 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2274 spin_lock(&vmx_vpid_lock
);
2275 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2276 if (vpid
< VMX_NR_VPIDS
) {
2278 __set_bit(vpid
, vmx_vpid_bitmap
);
2280 spin_unlock(&vmx_vpid_lock
);
2283 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2285 int f
= sizeof(unsigned long);
2287 if (!cpu_has_vmx_msr_bitmap())
2291 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2292 * have the write-low and read-high bitmap offsets the wrong way round.
2293 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2295 if (msr
<= 0x1fff) {
2296 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2297 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2298 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2300 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2301 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2305 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2308 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2309 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2313 * Sets up the vmcs for emulated real mode.
2315 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2317 u32 host_sysenter_cs
, msr_low
, msr_high
;
2319 u64 host_pat
, tsc_this
, tsc_base
;
2321 struct descriptor_table dt
;
2323 unsigned long kvm_vmx_return
;
2327 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2328 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2330 if (cpu_has_vmx_msr_bitmap())
2331 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2333 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2336 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2337 vmcs_config
.pin_based_exec_ctrl
);
2339 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2340 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2341 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2342 #ifdef CONFIG_X86_64
2343 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2344 CPU_BASED_CR8_LOAD_EXITING
;
2348 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2349 CPU_BASED_CR3_LOAD_EXITING
|
2350 CPU_BASED_INVLPG_EXITING
;
2351 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2353 if (cpu_has_secondary_exec_ctrls()) {
2354 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2355 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2357 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2359 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2361 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2362 enable_unrestricted_guest
= 0;
2364 if (!enable_unrestricted_guest
)
2365 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2367 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2372 vmcs_write32(PLE_GAP
, ple_gap
);
2373 vmcs_write32(PLE_WINDOW
, ple_window
);
2376 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2377 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2378 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2380 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2381 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2382 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2384 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2385 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2386 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2387 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2388 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2389 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2390 #ifdef CONFIG_X86_64
2391 rdmsrl(MSR_FS_BASE
, a
);
2392 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2393 rdmsrl(MSR_GS_BASE
, a
);
2394 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2396 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2397 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2400 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2403 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
2405 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2406 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2407 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2408 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2409 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2411 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2412 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2413 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2414 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2415 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2416 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2418 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2419 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2420 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2421 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2423 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2424 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2425 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2426 /* Write the default value follow host pat */
2427 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2428 /* Keep arch.pat sync with GUEST_IA32_PAT */
2429 vmx
->vcpu
.arch
.pat
= host_pat
;
2432 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2433 u32 index
= vmx_msr_index
[i
];
2434 u32 data_low
, data_high
;
2437 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2439 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2441 vmx
->guest_msrs
[j
].index
= i
;
2442 vmx
->guest_msrs
[j
].data
= 0;
2443 vmx
->guest_msrs
[j
].mask
= -1ull;
2447 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2449 /* 22.2.1, 20.8.1 */
2450 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2452 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2453 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2455 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2456 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2458 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2460 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2461 tsc_base
= tsc_this
;
2463 guest_write_tsc(0, tsc_base
);
2468 static int init_rmode(struct kvm
*kvm
)
2470 if (!init_rmode_tss(kvm
))
2472 if (!init_rmode_identity_map(kvm
))
2477 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2479 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2483 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2484 idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2485 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2490 vmx
->rmode
.vm86_active
= 0;
2492 vmx
->soft_vnmi_blocked
= 0;
2494 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2495 kvm_set_cr8(&vmx
->vcpu
, 0);
2496 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2497 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2498 msr
|= MSR_IA32_APICBASE_BSP
;
2499 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2501 fx_init(&vmx
->vcpu
);
2503 seg_setup(VCPU_SREG_CS
);
2505 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2506 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2508 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2509 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2510 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2512 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2513 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2516 seg_setup(VCPU_SREG_DS
);
2517 seg_setup(VCPU_SREG_ES
);
2518 seg_setup(VCPU_SREG_FS
);
2519 seg_setup(VCPU_SREG_GS
);
2520 seg_setup(VCPU_SREG_SS
);
2522 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2523 vmcs_writel(GUEST_TR_BASE
, 0);
2524 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2525 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2527 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2528 vmcs_writel(GUEST_LDTR_BASE
, 0);
2529 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2530 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2532 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2533 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2534 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2536 vmcs_writel(GUEST_RFLAGS
, 0x02);
2537 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2538 kvm_rip_write(vcpu
, 0xfff0);
2540 kvm_rip_write(vcpu
, 0);
2541 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2543 vmcs_writel(GUEST_DR7
, 0x400);
2545 vmcs_writel(GUEST_GDTR_BASE
, 0);
2546 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2548 vmcs_writel(GUEST_IDTR_BASE
, 0);
2549 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2551 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2552 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2553 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2555 /* Special registers */
2556 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2562 if (cpu_has_vmx_tpr_shadow()) {
2563 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2564 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2565 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2566 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2567 vmcs_write32(TPR_THRESHOLD
, 0);
2570 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2571 vmcs_write64(APIC_ACCESS_ADDR
,
2572 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2575 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2577 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2578 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
2579 vmx_set_cr4(&vmx
->vcpu
, 0);
2580 vmx_set_efer(&vmx
->vcpu
, 0);
2581 vmx_fpu_activate(&vmx
->vcpu
);
2582 update_exception_bitmap(&vmx
->vcpu
);
2584 vpid_sync_vcpu_all(vmx
);
2588 /* HACK: Don't enable emulation on guest boot/reset */
2589 vmx
->emulation_required
= 0;
2592 srcu_read_unlock(&vcpu
->kvm
->srcu
, idx
);
2596 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2598 u32 cpu_based_vm_exec_control
;
2600 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2601 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2605 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2607 u32 cpu_based_vm_exec_control
;
2609 if (!cpu_has_virtual_nmis()) {
2610 enable_irq_window(vcpu
);
2614 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2615 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2616 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2619 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2621 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2623 int irq
= vcpu
->arch
.interrupt
.nr
;
2625 trace_kvm_inj_virq(irq
);
2627 ++vcpu
->stat
.irq_injections
;
2628 if (vmx
->rmode
.vm86_active
) {
2629 vmx
->rmode
.irq
.pending
= true;
2630 vmx
->rmode
.irq
.vector
= irq
;
2631 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2632 if (vcpu
->arch
.interrupt
.soft
)
2633 vmx
->rmode
.irq
.rip
+=
2634 vmx
->vcpu
.arch
.event_exit_inst_len
;
2635 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2636 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2638 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2641 intr
= irq
| INTR_INFO_VALID_MASK
;
2642 if (vcpu
->arch
.interrupt
.soft
) {
2643 intr
|= INTR_TYPE_SOFT_INTR
;
2644 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2645 vmx
->vcpu
.arch
.event_exit_inst_len
);
2647 intr
|= INTR_TYPE_EXT_INTR
;
2648 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2651 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2653 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2655 if (!cpu_has_virtual_nmis()) {
2657 * Tracking the NMI-blocked state in software is built upon
2658 * finding the next open IRQ window. This, in turn, depends on
2659 * well-behaving guests: They have to keep IRQs disabled at
2660 * least as long as the NMI handler runs. Otherwise we may
2661 * cause NMI nesting, maybe breaking the guest. But as this is
2662 * highly unlikely, we can live with the residual risk.
2664 vmx
->soft_vnmi_blocked
= 1;
2665 vmx
->vnmi_blocked_time
= 0;
2668 ++vcpu
->stat
.nmi_injections
;
2669 if (vmx
->rmode
.vm86_active
) {
2670 vmx
->rmode
.irq
.pending
= true;
2671 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2672 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2673 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2674 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2675 INTR_INFO_VALID_MASK
);
2676 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2677 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2680 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2681 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2684 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2686 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2689 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2690 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
|
2691 GUEST_INTR_STATE_NMI
));
2694 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2696 if (!cpu_has_virtual_nmis())
2697 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2699 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2700 GUEST_INTR_STATE_NMI
);
2703 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2707 if (!cpu_has_virtual_nmis()) {
2708 if (vmx
->soft_vnmi_blocked
!= masked
) {
2709 vmx
->soft_vnmi_blocked
= masked
;
2710 vmx
->vnmi_blocked_time
= 0;
2714 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2715 GUEST_INTR_STATE_NMI
);
2717 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2718 GUEST_INTR_STATE_NMI
);
2722 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2724 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2725 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2726 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2729 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2732 struct kvm_userspace_memory_region tss_mem
= {
2733 .slot
= TSS_PRIVATE_MEMSLOT
,
2734 .guest_phys_addr
= addr
,
2735 .memory_size
= PAGE_SIZE
* 3,
2739 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2742 kvm
->arch
.tss_addr
= addr
;
2746 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2747 int vec
, u32 err_code
)
2750 * Instruction with address size override prefix opcode 0x67
2751 * Cause the #SS fault with 0 error code in VM86 mode.
2753 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2754 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
)
2757 * Forward all other exceptions that are valid in real mode.
2758 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2759 * the required debugging infrastructure rework.
2763 if (vcpu
->guest_debug
&
2764 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2766 kvm_queue_exception(vcpu
, vec
);
2769 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2780 kvm_queue_exception(vcpu
, vec
);
2787 * Trigger machine check on the host. We assume all the MSRs are already set up
2788 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2789 * We pass a fake environment to the machine check handler because we want
2790 * the guest to be always treated like user space, no matter what context
2791 * it used internally.
2793 static void kvm_machine_check(void)
2795 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2796 struct pt_regs regs
= {
2797 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
2798 .flags
= X86_EFLAGS_IF
,
2801 do_machine_check(®s
, 0);
2805 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
2807 /* already handled by vcpu_run */
2811 static int handle_exception(struct kvm_vcpu
*vcpu
)
2813 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2814 struct kvm_run
*kvm_run
= vcpu
->run
;
2815 u32 intr_info
, ex_no
, error_code
;
2816 unsigned long cr2
, rip
, dr6
;
2818 enum emulation_result er
;
2820 vect_info
= vmx
->idt_vectoring_info
;
2821 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2823 if (is_machine_check(intr_info
))
2824 return handle_machine_check(vcpu
);
2826 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2827 !is_page_fault(intr_info
)) {
2828 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2829 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
2830 vcpu
->run
->internal
.ndata
= 2;
2831 vcpu
->run
->internal
.data
[0] = vect_info
;
2832 vcpu
->run
->internal
.data
[1] = intr_info
;
2836 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2837 return 1; /* already handled by vmx_vcpu_run() */
2839 if (is_no_device(intr_info
)) {
2840 vmx_fpu_activate(vcpu
);
2844 if (is_invalid_opcode(intr_info
)) {
2845 er
= emulate_instruction(vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
2846 if (er
!= EMULATE_DONE
)
2847 kvm_queue_exception(vcpu
, UD_VECTOR
);
2852 rip
= kvm_rip_read(vcpu
);
2853 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2854 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2855 if (is_page_fault(intr_info
)) {
2856 /* EPT won't cause page fault directly */
2859 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2860 trace_kvm_page_fault(cr2
, error_code
);
2862 if (kvm_event_needs_reinjection(vcpu
))
2863 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
2864 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2867 if (vmx
->rmode
.vm86_active
&&
2868 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2870 if (vcpu
->arch
.halt_request
) {
2871 vcpu
->arch
.halt_request
= 0;
2872 return kvm_emulate_halt(vcpu
);
2877 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
2880 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
2881 if (!(vcpu
->guest_debug
&
2882 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
2883 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
2884 kvm_queue_exception(vcpu
, DB_VECTOR
);
2887 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
2888 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
2891 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2892 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
2893 kvm_run
->debug
.arch
.exception
= ex_no
;
2896 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2897 kvm_run
->ex
.exception
= ex_no
;
2898 kvm_run
->ex
.error_code
= error_code
;
2904 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
2906 ++vcpu
->stat
.irq_exits
;
2910 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
2912 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2916 static int handle_io(struct kvm_vcpu
*vcpu
)
2918 unsigned long exit_qualification
;
2919 int size
, in
, string
;
2922 ++vcpu
->stat
.io_exits
;
2923 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2924 string
= (exit_qualification
& 16) != 0;
2927 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DO_MMIO
)
2932 size
= (exit_qualification
& 7) + 1;
2933 in
= (exit_qualification
& 8) != 0;
2934 port
= exit_qualification
>> 16;
2936 skip_emulated_instruction(vcpu
);
2937 return kvm_emulate_pio(vcpu
, in
, size
, port
);
2941 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2944 * Patch in the VMCALL instruction:
2946 hypercall
[0] = 0x0f;
2947 hypercall
[1] = 0x01;
2948 hypercall
[2] = 0xc1;
2951 static int handle_cr(struct kvm_vcpu
*vcpu
)
2953 unsigned long exit_qualification
, val
;
2957 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2958 cr
= exit_qualification
& 15;
2959 reg
= (exit_qualification
>> 8) & 15;
2960 switch ((exit_qualification
>> 4) & 3) {
2961 case 0: /* mov to cr */
2962 val
= kvm_register_read(vcpu
, reg
);
2963 trace_kvm_cr_write(cr
, val
);
2966 kvm_set_cr0(vcpu
, val
);
2967 skip_emulated_instruction(vcpu
);
2970 kvm_set_cr3(vcpu
, val
);
2971 skip_emulated_instruction(vcpu
);
2974 kvm_set_cr4(vcpu
, val
);
2975 skip_emulated_instruction(vcpu
);
2978 u8 cr8_prev
= kvm_get_cr8(vcpu
);
2979 u8 cr8
= kvm_register_read(vcpu
, reg
);
2980 kvm_set_cr8(vcpu
, cr8
);
2981 skip_emulated_instruction(vcpu
);
2982 if (irqchip_in_kernel(vcpu
->kvm
))
2984 if (cr8_prev
<= cr8
)
2986 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
2992 vmx_fpu_deactivate(vcpu
);
2993 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2994 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2995 vmx_fpu_activate(vcpu
);
2996 skip_emulated_instruction(vcpu
);
2998 case 1: /*mov from cr*/
3001 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3002 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3003 skip_emulated_instruction(vcpu
);
3006 val
= kvm_get_cr8(vcpu
);
3007 kvm_register_write(vcpu
, reg
, val
);
3008 trace_kvm_cr_read(cr
, val
);
3009 skip_emulated_instruction(vcpu
);
3014 kvm_lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
3016 skip_emulated_instruction(vcpu
);
3021 vcpu
->run
->exit_reason
= 0;
3022 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3023 (int)(exit_qualification
>> 4) & 3, cr
);
3027 static int handle_dr(struct kvm_vcpu
*vcpu
)
3029 unsigned long exit_qualification
;
3033 if (!kvm_require_cpl(vcpu
, 0))
3035 dr
= vmcs_readl(GUEST_DR7
);
3038 * As the vm-exit takes precedence over the debug trap, we
3039 * need to emulate the latter, either for the host or the
3040 * guest debugging itself.
3042 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3043 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3044 vcpu
->run
->debug
.arch
.dr7
= dr
;
3045 vcpu
->run
->debug
.arch
.pc
=
3046 vmcs_readl(GUEST_CS_BASE
) +
3047 vmcs_readl(GUEST_RIP
);
3048 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3049 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3052 vcpu
->arch
.dr7
&= ~DR7_GD
;
3053 vcpu
->arch
.dr6
|= DR6_BD
;
3054 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3055 kvm_queue_exception(vcpu
, DB_VECTOR
);
3060 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3061 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3062 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3063 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3066 val
= vcpu
->arch
.db
[dr
];
3069 val
= vcpu
->arch
.dr6
;
3072 val
= vcpu
->arch
.dr7
;
3077 kvm_register_write(vcpu
, reg
, val
);
3079 val
= vcpu
->arch
.regs
[reg
];
3082 vcpu
->arch
.db
[dr
] = val
;
3083 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
3084 vcpu
->arch
.eff_db
[dr
] = val
;
3087 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
))
3088 kvm_queue_exception(vcpu
, UD_VECTOR
);
3091 if (val
& 0xffffffff00000000ULL
) {
3092 kvm_queue_exception(vcpu
, GP_VECTOR
);
3095 vcpu
->arch
.dr6
= (val
& DR6_VOLATILE
) | DR6_FIXED_1
;
3098 if (val
& 0xffffffff00000000ULL
) {
3099 kvm_queue_exception(vcpu
, GP_VECTOR
);
3102 vcpu
->arch
.dr7
= (val
& DR7_VOLATILE
) | DR7_FIXED_1
;
3103 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
3104 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3105 vcpu
->arch
.switch_db_regs
=
3106 (val
& DR7_BP_EN_MASK
);
3111 skip_emulated_instruction(vcpu
);
3115 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3117 kvm_emulate_cpuid(vcpu
);
3121 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3123 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3126 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3127 kvm_inject_gp(vcpu
, 0);
3131 trace_kvm_msr_read(ecx
, data
);
3133 /* FIXME: handling of bits 32:63 of rax, rdx */
3134 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3135 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3136 skip_emulated_instruction(vcpu
);
3140 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3142 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3143 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3144 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3146 trace_kvm_msr_write(ecx
, data
);
3148 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3149 kvm_inject_gp(vcpu
, 0);
3153 skip_emulated_instruction(vcpu
);
3157 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3162 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3164 u32 cpu_based_vm_exec_control
;
3166 /* clear pending irq */
3167 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3168 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3171 ++vcpu
->stat
.irq_window_exits
;
3174 * If the user space waits to inject interrupts, exit as soon as
3177 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3178 vcpu
->run
->request_interrupt_window
&&
3179 !kvm_cpu_has_interrupt(vcpu
)) {
3180 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3186 static int handle_halt(struct kvm_vcpu
*vcpu
)
3188 skip_emulated_instruction(vcpu
);
3189 return kvm_emulate_halt(vcpu
);
3192 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3194 skip_emulated_instruction(vcpu
);
3195 kvm_emulate_hypercall(vcpu
);
3199 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3201 kvm_queue_exception(vcpu
, UD_VECTOR
);
3205 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3207 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3209 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3210 skip_emulated_instruction(vcpu
);
3214 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3216 skip_emulated_instruction(vcpu
);
3217 /* TODO: Add support for VT-d/pass-through device */
3221 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3223 unsigned long exit_qualification
;
3224 enum emulation_result er
;
3225 unsigned long offset
;
3227 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3228 offset
= exit_qualification
& 0xffful
;
3230 er
= emulate_instruction(vcpu
, 0, 0, 0);
3232 if (er
!= EMULATE_DONE
) {
3234 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3241 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3243 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3244 unsigned long exit_qualification
;
3246 int reason
, type
, idt_v
;
3248 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3249 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3251 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3253 reason
= (u32
)exit_qualification
>> 30;
3254 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3256 case INTR_TYPE_NMI_INTR
:
3257 vcpu
->arch
.nmi_injected
= false;
3258 if (cpu_has_virtual_nmis())
3259 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3260 GUEST_INTR_STATE_NMI
);
3262 case INTR_TYPE_EXT_INTR
:
3263 case INTR_TYPE_SOFT_INTR
:
3264 kvm_clear_interrupt_queue(vcpu
);
3266 case INTR_TYPE_HARD_EXCEPTION
:
3267 case INTR_TYPE_SOFT_EXCEPTION
:
3268 kvm_clear_exception_queue(vcpu
);
3274 tss_selector
= exit_qualification
;
3276 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3277 type
!= INTR_TYPE_EXT_INTR
&&
3278 type
!= INTR_TYPE_NMI_INTR
))
3279 skip_emulated_instruction(vcpu
);
3281 if (!kvm_task_switch(vcpu
, tss_selector
, reason
))
3284 /* clear all local breakpoint enable flags */
3285 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3288 * TODO: What about debug traps on tss switch?
3289 * Are we supposed to inject them and update dr6?
3295 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3297 unsigned long exit_qualification
;
3301 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3303 if (exit_qualification
& (1 << 6)) {
3304 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3308 gla_validity
= (exit_qualification
>> 7) & 0x3;
3309 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3310 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3311 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3312 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3313 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3314 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3315 (long unsigned int)exit_qualification
);
3316 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3317 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3321 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3322 trace_kvm_page_fault(gpa
, exit_qualification
);
3323 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3326 static u64
ept_rsvd_mask(u64 spte
, int level
)
3331 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3332 mask
|= (1ULL << i
);
3335 /* bits 7:3 reserved */
3337 else if (level
== 2) {
3338 if (spte
& (1ULL << 7))
3339 /* 2MB ref, bits 20:12 reserved */
3342 /* bits 6:3 reserved */
3349 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3352 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3354 /* 010b (write-only) */
3355 WARN_ON((spte
& 0x7) == 0x2);
3357 /* 110b (write/execute) */
3358 WARN_ON((spte
& 0x7) == 0x6);
3360 /* 100b (execute-only) and value not supported by logical processor */
3361 if (!cpu_has_vmx_ept_execute_only())
3362 WARN_ON((spte
& 0x7) == 0x4);
3366 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3368 if (rsvd_bits
!= 0) {
3369 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3370 __func__
, rsvd_bits
);
3374 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3375 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3377 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3378 ept_mem_type
== 7) {
3379 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3380 __func__
, ept_mem_type
);
3387 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3393 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3395 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3396 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3398 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3400 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3401 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3403 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3404 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3409 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3411 u32 cpu_based_vm_exec_control
;
3413 /* clear pending NMI */
3414 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3415 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3416 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3417 ++vcpu
->stat
.nmi_window_exits
;
3422 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3424 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3425 enum emulation_result err
= EMULATE_DONE
;
3428 while (!guest_state_valid(vcpu
)) {
3429 err
= emulate_instruction(vcpu
, 0, 0, 0);
3431 if (err
== EMULATE_DO_MMIO
) {
3436 if (err
!= EMULATE_DONE
) {
3437 kvm_report_emulation_failure(vcpu
, "emulation failure");
3438 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3439 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3440 vcpu
->run
->internal
.ndata
= 0;
3445 if (signal_pending(current
))
3451 vmx
->emulation_required
= 0;
3457 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3458 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3460 static int handle_pause(struct kvm_vcpu
*vcpu
)
3462 skip_emulated_instruction(vcpu
);
3463 kvm_vcpu_on_spin(vcpu
);
3468 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3470 kvm_queue_exception(vcpu
, UD_VECTOR
);
3475 * The exit handlers return 1 if the exit was handled fully and guest execution
3476 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3477 * to be done to userspace and return 0.
3479 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3480 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3481 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3482 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3483 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3484 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3485 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3486 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3487 [EXIT_REASON_CPUID
] = handle_cpuid
,
3488 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3489 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3490 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3491 [EXIT_REASON_HLT
] = handle_halt
,
3492 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3493 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3494 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3495 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3496 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3497 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3498 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3499 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3500 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3501 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3502 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3503 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3504 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3505 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3506 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3507 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3508 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3509 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3510 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3511 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3512 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3515 static const int kvm_vmx_max_exit_handlers
=
3516 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3519 * The guest has exited. See if we can fix it or if we need userspace
3522 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3524 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3525 u32 exit_reason
= vmx
->exit_reason
;
3526 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3528 trace_kvm_exit(exit_reason
, kvm_rip_read(vcpu
));
3530 /* If guest state is invalid, start emulating */
3531 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3532 return handle_invalid_guest_state(vcpu
);
3534 /* Access CR3 don't cause VMExit in paging mode, so we need
3535 * to sync with guest real CR3. */
3536 if (enable_ept
&& is_paging(vcpu
))
3537 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3539 if (unlikely(vmx
->fail
)) {
3540 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3541 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3542 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3546 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3547 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3548 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3549 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3550 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3551 "(0x%x) and exit reason is 0x%x\n",
3552 __func__
, vectoring_info
, exit_reason
);
3554 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3555 if (vmx_interrupt_allowed(vcpu
)) {
3556 vmx
->soft_vnmi_blocked
= 0;
3557 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3558 vcpu
->arch
.nmi_pending
) {
3560 * This CPU don't support us in finding the end of an
3561 * NMI-blocked window if the guest runs with IRQs
3562 * disabled. So we pull the trigger after 1 s of
3563 * futile waiting, but inform the user about this.
3565 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3566 "state on VCPU %d after 1 s timeout\n",
3567 __func__
, vcpu
->vcpu_id
);
3568 vmx
->soft_vnmi_blocked
= 0;
3572 if (exit_reason
< kvm_vmx_max_exit_handlers
3573 && kvm_vmx_exit_handlers
[exit_reason
])
3574 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3576 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3577 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3582 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3584 if (irr
== -1 || tpr
< irr
) {
3585 vmcs_write32(TPR_THRESHOLD
, 0);
3589 vmcs_write32(TPR_THRESHOLD
, irr
);
3592 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3595 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3599 bool idtv_info_valid
;
3601 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3603 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3605 /* Handle machine checks before interrupts are enabled */
3606 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3607 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3608 && is_machine_check(exit_intr_info
)))
3609 kvm_machine_check();
3611 /* We need to handle NMIs before interrupts are enabled */
3612 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3613 (exit_intr_info
& INTR_INFO_VALID_MASK
))
3616 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3618 if (cpu_has_virtual_nmis()) {
3619 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3620 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3622 * SDM 3: 27.7.1.2 (September 2008)
3623 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3624 * a guest IRET fault.
3625 * SDM 3: 23.2.2 (September 2008)
3626 * Bit 12 is undefined in any of the following cases:
3627 * If the VM exit sets the valid bit in the IDT-vectoring
3628 * information field.
3629 * If the VM exit is due to a double fault.
3631 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3632 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3633 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3634 GUEST_INTR_STATE_NMI
);
3635 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3636 vmx
->vnmi_blocked_time
+=
3637 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3639 vmx
->vcpu
.arch
.nmi_injected
= false;
3640 kvm_clear_exception_queue(&vmx
->vcpu
);
3641 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3643 if (!idtv_info_valid
)
3646 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3647 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3650 case INTR_TYPE_NMI_INTR
:
3651 vmx
->vcpu
.arch
.nmi_injected
= true;
3653 * SDM 3: 27.7.1.2 (September 2008)
3654 * Clear bit "block by NMI" before VM entry if a NMI
3657 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3658 GUEST_INTR_STATE_NMI
);
3660 case INTR_TYPE_SOFT_EXCEPTION
:
3661 vmx
->vcpu
.arch
.event_exit_inst_len
=
3662 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3664 case INTR_TYPE_HARD_EXCEPTION
:
3665 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3666 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3667 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3669 kvm_queue_exception(&vmx
->vcpu
, vector
);
3671 case INTR_TYPE_SOFT_INTR
:
3672 vmx
->vcpu
.arch
.event_exit_inst_len
=
3673 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3675 case INTR_TYPE_EXT_INTR
:
3676 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3677 type
== INTR_TYPE_SOFT_INTR
);
3685 * Failure to inject an interrupt should give us the information
3686 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3687 * when fetching the interrupt redirection bitmap in the real-mode
3688 * tss, this doesn't happen. So we do it ourselves.
3690 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3692 vmx
->rmode
.irq
.pending
= 0;
3693 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3695 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3696 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3697 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3698 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3701 vmx
->idt_vectoring_info
=
3702 VECTORING_INFO_VALID_MASK
3703 | INTR_TYPE_EXT_INTR
3704 | vmx
->rmode
.irq
.vector
;
3707 #ifdef CONFIG_X86_64
3715 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3719 /* Record the guest's net vcpu time for enforced NMI injections. */
3720 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3721 vmx
->entry_time
= ktime_get();
3723 /* Don't enter VMX if guest state is invalid, let the exit handler
3724 start emulation until we arrive back to a valid state */
3725 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3728 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3729 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3730 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3731 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3733 /* When single-stepping over STI and MOV SS, we must clear the
3734 * corresponding interruptibility bits in the guest state. Otherwise
3735 * vmentry fails as it then expects bit 14 (BS) in pending debug
3736 * exceptions being set, but that's not correct for the guest debugging
3738 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3739 vmx_set_interrupt_shadow(vcpu
, 0);
3742 * Loading guest fpu may have cleared host cr0.ts
3744 vmcs_writel(HOST_CR0
, read_cr0());
3746 if (vcpu
->arch
.switch_db_regs
)
3747 set_debugreg(vcpu
->arch
.dr6
, 6);
3750 /* Store host registers */
3751 "push %%"R
"dx; push %%"R
"bp;"
3753 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3755 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3756 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3758 /* Reload cr2 if changed */
3759 "mov %c[cr2](%0), %%"R
"ax \n\t"
3760 "mov %%cr2, %%"R
"dx \n\t"
3761 "cmp %%"R
"ax, %%"R
"dx \n\t"
3763 "mov %%"R
"ax, %%cr2 \n\t"
3765 /* Check if vmlaunch of vmresume is needed */
3766 "cmpl $0, %c[launched](%0) \n\t"
3767 /* Load guest registers. Don't clobber flags. */
3768 "mov %c[rax](%0), %%"R
"ax \n\t"
3769 "mov %c[rbx](%0), %%"R
"bx \n\t"
3770 "mov %c[rdx](%0), %%"R
"dx \n\t"
3771 "mov %c[rsi](%0), %%"R
"si \n\t"
3772 "mov %c[rdi](%0), %%"R
"di \n\t"
3773 "mov %c[rbp](%0), %%"R
"bp \n\t"
3774 #ifdef CONFIG_X86_64
3775 "mov %c[r8](%0), %%r8 \n\t"
3776 "mov %c[r9](%0), %%r9 \n\t"
3777 "mov %c[r10](%0), %%r10 \n\t"
3778 "mov %c[r11](%0), %%r11 \n\t"
3779 "mov %c[r12](%0), %%r12 \n\t"
3780 "mov %c[r13](%0), %%r13 \n\t"
3781 "mov %c[r14](%0), %%r14 \n\t"
3782 "mov %c[r15](%0), %%r15 \n\t"
3784 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3786 /* Enter guest mode */
3787 "jne .Llaunched \n\t"
3788 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3789 "jmp .Lkvm_vmx_return \n\t"
3790 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3791 ".Lkvm_vmx_return: "
3792 /* Save guest registers, load host registers, keep flags */
3793 "xchg %0, (%%"R
"sp) \n\t"
3794 "mov %%"R
"ax, %c[rax](%0) \n\t"
3795 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3796 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3797 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3798 "mov %%"R
"si, %c[rsi](%0) \n\t"
3799 "mov %%"R
"di, %c[rdi](%0) \n\t"
3800 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3801 #ifdef CONFIG_X86_64
3802 "mov %%r8, %c[r8](%0) \n\t"
3803 "mov %%r9, %c[r9](%0) \n\t"
3804 "mov %%r10, %c[r10](%0) \n\t"
3805 "mov %%r11, %c[r11](%0) \n\t"
3806 "mov %%r12, %c[r12](%0) \n\t"
3807 "mov %%r13, %c[r13](%0) \n\t"
3808 "mov %%r14, %c[r14](%0) \n\t"
3809 "mov %%r15, %c[r15](%0) \n\t"
3811 "mov %%cr2, %%"R
"ax \n\t"
3812 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3814 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3815 "setbe %c[fail](%0) \n\t"
3816 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3817 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3818 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3819 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3820 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3821 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3822 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3823 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3824 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3825 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3826 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3827 #ifdef CONFIG_X86_64
3828 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3829 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3830 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3831 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3832 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3833 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3834 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3835 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3837 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3839 , R
"bx", R
"di", R
"si"
3840 #ifdef CONFIG_X86_64
3841 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3845 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
3846 | (1 << VCPU_EXREG_PDPTR
));
3847 vcpu
->arch
.regs_dirty
= 0;
3849 if (vcpu
->arch
.switch_db_regs
)
3850 get_debugreg(vcpu
->arch
.dr6
, 6);
3852 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3853 if (vmx
->rmode
.irq
.pending
)
3854 fixup_rmode_irq(vmx
);
3856 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3859 vmx_complete_interrupts(vmx
);
3865 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3867 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3871 free_vmcs(vmx
->vmcs
);
3876 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3878 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3880 spin_lock(&vmx_vpid_lock
);
3882 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3883 spin_unlock(&vmx_vpid_lock
);
3884 vmx_free_vmcs(vcpu
);
3885 kfree(vmx
->guest_msrs
);
3886 kvm_vcpu_uninit(vcpu
);
3887 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3890 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
3893 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
3897 return ERR_PTR(-ENOMEM
);
3901 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
3905 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3906 if (!vmx
->guest_msrs
) {
3911 vmx
->vmcs
= alloc_vmcs();
3915 vmcs_clear(vmx
->vmcs
);
3918 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
3919 err
= vmx_vcpu_setup(vmx
);
3920 vmx_vcpu_put(&vmx
->vcpu
);
3924 if (vm_need_virtualize_apic_accesses(kvm
))
3925 if (alloc_apic_access_page(kvm
) != 0)
3929 if (!kvm
->arch
.ept_identity_map_addr
)
3930 kvm
->arch
.ept_identity_map_addr
=
3931 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
3932 if (alloc_identity_pagetable(kvm
) != 0)
3939 free_vmcs(vmx
->vmcs
);
3941 kfree(vmx
->guest_msrs
);
3943 kvm_vcpu_uninit(&vmx
->vcpu
);
3945 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3946 return ERR_PTR(err
);
3949 static void __init
vmx_check_processor_compat(void *rtn
)
3951 struct vmcs_config vmcs_conf
;
3954 if (setup_vmcs_config(&vmcs_conf
) < 0)
3956 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
3957 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
3958 smp_processor_id());
3963 static int get_ept_level(void)
3965 return VMX_EPT_DEFAULT_GAW
+ 1;
3968 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3972 /* For VT-d and EPT combination
3973 * 1. MMIO: always map as UC
3975 * a. VT-d without snooping control feature: can't guarantee the
3976 * result, try to trust guest.
3977 * b. VT-d with snooping control feature: snooping control feature of
3978 * VT-d engine can guarantee the cache correctness. Just set it
3979 * to WB to keep consistent with host. So the same as item 3.
3980 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3981 * consistent with host MTRR
3984 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
3985 else if (vcpu
->kvm
->arch
.iommu_domain
&&
3986 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
3987 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
3988 VMX_EPT_MT_EPTE_SHIFT
;
3990 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
3996 #define _ER(x) { EXIT_REASON_##x, #x }
3998 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4000 _ER(EXTERNAL_INTERRUPT
),
4002 _ER(PENDING_INTERRUPT
),
4022 _ER(IO_INSTRUCTION
),
4025 _ER(MWAIT_INSTRUCTION
),
4026 _ER(MONITOR_INSTRUCTION
),
4027 _ER(PAUSE_INSTRUCTION
),
4028 _ER(MCE_DURING_VMENTRY
),
4029 _ER(TPR_BELOW_THRESHOLD
),
4039 static int vmx_get_lpage_level(void)
4041 return PT_DIRECTORY_LEVEL
;
4044 static inline u32
bit(int bitno
)
4046 return 1 << (bitno
& 31);
4049 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4051 struct kvm_cpuid_entry2
*best
;
4052 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4055 vmx
->rdtscp_enabled
= false;
4056 if (vmx_rdtscp_supported()) {
4057 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4058 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4059 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4060 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4061 vmx
->rdtscp_enabled
= true;
4063 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4064 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4071 static struct kvm_x86_ops vmx_x86_ops
= {
4072 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4073 .disabled_by_bios
= vmx_disabled_by_bios
,
4074 .hardware_setup
= hardware_setup
,
4075 .hardware_unsetup
= hardware_unsetup
,
4076 .check_processor_compatibility
= vmx_check_processor_compat
,
4077 .hardware_enable
= hardware_enable
,
4078 .hardware_disable
= hardware_disable
,
4079 .cpu_has_accelerated_tpr
= report_flexpriority
,
4081 .vcpu_create
= vmx_create_vcpu
,
4082 .vcpu_free
= vmx_free_vcpu
,
4083 .vcpu_reset
= vmx_vcpu_reset
,
4085 .prepare_guest_switch
= vmx_save_host_state
,
4086 .vcpu_load
= vmx_vcpu_load
,
4087 .vcpu_put
= vmx_vcpu_put
,
4089 .set_guest_debug
= set_guest_debug
,
4090 .get_msr
= vmx_get_msr
,
4091 .set_msr
= vmx_set_msr
,
4092 .get_segment_base
= vmx_get_segment_base
,
4093 .get_segment
= vmx_get_segment
,
4094 .set_segment
= vmx_set_segment
,
4095 .get_cpl
= vmx_get_cpl
,
4096 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4097 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4098 .set_cr0
= vmx_set_cr0
,
4099 .set_cr3
= vmx_set_cr3
,
4100 .set_cr4
= vmx_set_cr4
,
4101 .set_efer
= vmx_set_efer
,
4102 .get_idt
= vmx_get_idt
,
4103 .set_idt
= vmx_set_idt
,
4104 .get_gdt
= vmx_get_gdt
,
4105 .set_gdt
= vmx_set_gdt
,
4106 .cache_reg
= vmx_cache_reg
,
4107 .get_rflags
= vmx_get_rflags
,
4108 .set_rflags
= vmx_set_rflags
,
4110 .tlb_flush
= vmx_flush_tlb
,
4112 .run
= vmx_vcpu_run
,
4113 .handle_exit
= vmx_handle_exit
,
4114 .skip_emulated_instruction
= skip_emulated_instruction
,
4115 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4116 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4117 .patch_hypercall
= vmx_patch_hypercall
,
4118 .set_irq
= vmx_inject_irq
,
4119 .set_nmi
= vmx_inject_nmi
,
4120 .queue_exception
= vmx_queue_exception
,
4121 .interrupt_allowed
= vmx_interrupt_allowed
,
4122 .nmi_allowed
= vmx_nmi_allowed
,
4123 .get_nmi_mask
= vmx_get_nmi_mask
,
4124 .set_nmi_mask
= vmx_set_nmi_mask
,
4125 .enable_nmi_window
= enable_nmi_window
,
4126 .enable_irq_window
= enable_irq_window
,
4127 .update_cr8_intercept
= update_cr8_intercept
,
4129 .set_tss_addr
= vmx_set_tss_addr
,
4130 .get_tdp_level
= get_ept_level
,
4131 .get_mt_mask
= vmx_get_mt_mask
,
4133 .exit_reasons_str
= vmx_exit_reasons_str
,
4134 .get_lpage_level
= vmx_get_lpage_level
,
4136 .cpuid_update
= vmx_cpuid_update
,
4138 .rdtscp_supported
= vmx_rdtscp_supported
,
4141 static int __init
vmx_init(void)
4145 rdmsrl_safe(MSR_EFER
, &host_efer
);
4147 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4148 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4150 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4151 if (!vmx_io_bitmap_a
)
4154 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4155 if (!vmx_io_bitmap_b
) {
4160 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4161 if (!vmx_msr_bitmap_legacy
) {
4166 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4167 if (!vmx_msr_bitmap_longmode
) {
4173 * Allow direct access to the PC debug port (it is often used for I/O
4174 * delays, but the vmexits simply slow things down).
4176 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4177 clear_bit(0x80, vmx_io_bitmap_a
);
4179 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4181 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4182 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4184 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4186 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
4190 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4191 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4192 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4193 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4194 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4195 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4198 bypass_guest_pf
= 0;
4199 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
4200 VMX_EPT_WRITABLE_MASK
);
4201 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4202 VMX_EPT_EXECUTABLE_MASK
);
4207 if (bypass_guest_pf
)
4208 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4213 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4215 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4217 free_page((unsigned long)vmx_io_bitmap_b
);
4219 free_page((unsigned long)vmx_io_bitmap_a
);
4223 static void __exit
vmx_exit(void)
4225 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4226 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4227 free_page((unsigned long)vmx_io_bitmap_b
);
4228 free_page((unsigned long)vmx_io_bitmap_a
);
4233 module_init(vmx_init
)
4234 module_exit(vmx_exit
)