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KVM: x86: Fix guest debug across vcpu INIT reset
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45
46 #include "trace.h"
47
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
51
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
54
55 static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58 };
59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
61 static bool __read_mostly enable_vpid = 1;
62 module_param_named(vpid, enable_vpid, bool, 0444);
63
64 static bool __read_mostly flexpriority_enabled = 1;
65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
66
67 static bool __read_mostly enable_ept = 1;
68 module_param_named(ept, enable_ept, bool, S_IRUGO);
69
70 static bool __read_mostly enable_unrestricted_guest = 1;
71 module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
74 static bool __read_mostly enable_ept_ad_bits = 1;
75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
77 static bool __read_mostly emulate_invalid_guest_state = true;
78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
79
80 static bool __read_mostly vmm_exclusive = 1;
81 module_param(vmm_exclusive, bool, S_IRUGO);
82
83 static bool __read_mostly fasteoi = 1;
84 module_param(fasteoi, bool, S_IRUGO);
85
86 /*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
91 static bool __read_mostly nested = 0;
92 module_param(nested, bool, S_IRUGO);
93
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
111 /*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125 module_param(ple_gap, int, S_IRUGO);
126
127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128 module_param(ple_window, int, S_IRUGO);
129
130 extern const ulong vmx_return;
131
132 #define NR_AUTOLOAD_MSRS 8
133 #define VMCS02_POOL_SIZE 1
134
135 struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139 };
140
141 /*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146 struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151 };
152
153 struct shared_msr_entry {
154 unsigned index;
155 u64 data;
156 u64 mask;
157 };
158
159 /*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
172 typedef u64 natural_width;
173 struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
179
180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
319 };
320
321 /*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326 #define VMCS12_REVISION 0x11e57ed0
327
328 /*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333 #define VMCS12_SIZE 0x1000
334
335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
336 struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340 };
341
342 /*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346 struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
359 u64 vmcs01_tsc_offset;
360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
367 };
368
369 struct vcpu_vmx {
370 struct kvm_vcpu vcpu;
371 unsigned long host_rsp;
372 u8 fail;
373 u8 cpl;
374 bool nmi_known_unmasked;
375 u32 exit_intr_info;
376 u32 idt_vectoring_info;
377 ulong rflags;
378 struct shared_msr_entry *guest_msrs;
379 int nmsrs;
380 int save_nmsrs;
381 #ifdef CONFIG_X86_64
382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
384 #endif
385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
401 #ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403 #endif
404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
406 } host_state;
407 struct {
408 int vm86_active;
409 ulong save_rflags;
410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
419 } seg[8];
420 } segment_cache;
421 int vpid;
422 bool emulation_required;
423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
428 u32 exit_reason;
429
430 bool rdtscp_enabled;
431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
434 };
435
436 enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443 };
444
445 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446 {
447 return container_of(vcpu, struct vcpu_vmx, vcpu);
448 }
449
450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
455 static const unsigned short vmcs_field_to_offset_table[] = {
456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583 };
584 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586 static inline short vmcs_field_to_offset(unsigned long field)
587 {
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591 }
592
593 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594 {
595 return to_vmx(vcpu)->nested.current_vmcs12;
596 }
597
598 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599 {
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
601 if (is_error_page(page))
602 return NULL;
603
604 return page;
605 }
606
607 static void nested_release_page(struct page *page)
608 {
609 kvm_release_page_dirty(page);
610 }
611
612 static void nested_release_page_clean(struct page *page)
613 {
614 kvm_release_page_clean(page);
615 }
616
617 static u64 construct_eptp(unsigned long root_hpa);
618 static void kvm_cpu_vmxon(u64 addr);
619 static void kvm_cpu_vmxoff(void);
620 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
621 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
622 static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624 static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
626
627 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
629 /*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
634 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
635
636 static unsigned long *vmx_io_bitmap_a;
637 static unsigned long *vmx_io_bitmap_b;
638 static unsigned long *vmx_msr_bitmap_legacy;
639 static unsigned long *vmx_msr_bitmap_longmode;
640
641 static bool cpu_has_load_ia32_efer;
642 static bool cpu_has_load_perf_global_ctrl;
643
644 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645 static DEFINE_SPINLOCK(vmx_vpid_lock);
646
647 static struct vmcs_config {
648 int size;
649 int order;
650 u32 revision_id;
651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
653 u32 cpu_based_2nd_exec_ctrl;
654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656 } vmcs_config;
657
658 static struct vmx_capability {
659 u32 ept;
660 u32 vpid;
661 } vmx_capability;
662
663 #define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
671 static const struct kvm_vmx_segment_field {
672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676 } kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685 };
686
687 static u64 host_efer;
688
689 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
691 /*
692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
693 * away by decrementing the array size.
694 */
695 static const u32 vmx_msr_index[] = {
696 #ifdef CONFIG_X86_64
697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
698 #endif
699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
700 };
701 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
702
703 static inline bool is_page_fault(u32 intr_info)
704 {
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
708 }
709
710 static inline bool is_no_device(u32 intr_info)
711 {
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
715 }
716
717 static inline bool is_invalid_opcode(u32 intr_info)
718 {
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
722 }
723
724 static inline bool is_external_interrupt(u32 intr_info)
725 {
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728 }
729
730 static inline bool is_machine_check(u32 intr_info)
731 {
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735 }
736
737 static inline bool cpu_has_vmx_msr_bitmap(void)
738 {
739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
740 }
741
742 static inline bool cpu_has_vmx_tpr_shadow(void)
743 {
744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
745 }
746
747 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
748 {
749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
750 }
751
752 static inline bool cpu_has_secondary_exec_ctrls(void)
753 {
754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
756 }
757
758 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
759 {
760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762 }
763
764 static inline bool cpu_has_vmx_flexpriority(void)
765 {
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
768 }
769
770 static inline bool cpu_has_vmx_ept_execute_only(void)
771 {
772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
773 }
774
775 static inline bool cpu_has_vmx_eptp_uncacheable(void)
776 {
777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
778 }
779
780 static inline bool cpu_has_vmx_eptp_writeback(void)
781 {
782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
783 }
784
785 static inline bool cpu_has_vmx_ept_2m_page(void)
786 {
787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
788 }
789
790 static inline bool cpu_has_vmx_ept_1g_page(void)
791 {
792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
793 }
794
795 static inline bool cpu_has_vmx_ept_4levels(void)
796 {
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798 }
799
800 static inline bool cpu_has_vmx_ept_ad_bits(void)
801 {
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803 }
804
805 static inline bool cpu_has_vmx_invept_individual_addr(void)
806 {
807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
808 }
809
810 static inline bool cpu_has_vmx_invept_context(void)
811 {
812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
813 }
814
815 static inline bool cpu_has_vmx_invept_global(void)
816 {
817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
818 }
819
820 static inline bool cpu_has_vmx_invvpid_single(void)
821 {
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823 }
824
825 static inline bool cpu_has_vmx_invvpid_global(void)
826 {
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828 }
829
830 static inline bool cpu_has_vmx_ept(void)
831 {
832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
834 }
835
836 static inline bool cpu_has_vmx_unrestricted_guest(void)
837 {
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840 }
841
842 static inline bool cpu_has_vmx_ple(void)
843 {
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846 }
847
848 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
849 {
850 return flexpriority_enabled && irqchip_in_kernel(kvm);
851 }
852
853 static inline bool cpu_has_vmx_vpid(void)
854 {
855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
857 }
858
859 static inline bool cpu_has_vmx_rdtscp(void)
860 {
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863 }
864
865 static inline bool cpu_has_vmx_invpcid(void)
866 {
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869 }
870
871 static inline bool cpu_has_virtual_nmis(void)
872 {
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874 }
875
876 static inline bool cpu_has_vmx_wbinvd_exit(void)
877 {
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880 }
881
882 static inline bool report_flexpriority(void)
883 {
884 return flexpriority_enabled;
885 }
886
887 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888 {
889 return vmcs12->cpu_based_vm_exec_control & bit;
890 }
891
892 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893 {
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897 }
898
899 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901 {
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903 }
904
905 static inline bool is_exception(u32 intr_info)
906 {
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909 }
910
911 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
912 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
916 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
917 {
918 int i;
919
920 for (i = 0; i < vmx->nmsrs; ++i)
921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
922 return i;
923 return -1;
924 }
925
926 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927 {
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
934 asm volatile (__ex(ASM_VMX_INVVPID)
935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938 }
939
940 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941 {
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
946 asm volatile (__ex(ASM_VMX_INVEPT)
947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950 }
951
952 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
953 {
954 int i;
955
956 i = __find_msr_index(vmx, msr);
957 if (i >= 0)
958 return &vmx->guest_msrs[i];
959 return NULL;
960 }
961
962 static void vmcs_clear(struct vmcs *vmcs)
963 {
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973 }
974
975 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976 {
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980 }
981
982 static void vmcs_load(struct vmcs *vmcs)
983 {
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
989 : "cc", "memory");
990 if (error)
991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
992 vmcs, phys_addr);
993 }
994
995 static void __loaded_vmcs_clear(void *arg)
996 {
997 struct loaded_vmcs *loaded_vmcs = arg;
998 int cpu = raw_smp_processor_id();
999
1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1003 per_cpu(current_vmcs, cpu) = NULL;
1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1005 loaded_vmcs_init(loaded_vmcs);
1006 }
1007
1008 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1009 {
1010 if (loaded_vmcs->cpu != -1)
1011 smp_call_function_single(
1012 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1013 }
1014
1015 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1016 {
1017 if (vmx->vpid == 0)
1018 return;
1019
1020 if (cpu_has_vmx_invvpid_single())
1021 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1022 }
1023
1024 static inline void vpid_sync_vcpu_global(void)
1025 {
1026 if (cpu_has_vmx_invvpid_global())
1027 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1028 }
1029
1030 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1031 {
1032 if (cpu_has_vmx_invvpid_single())
1033 vpid_sync_vcpu_single(vmx);
1034 else
1035 vpid_sync_vcpu_global();
1036 }
1037
1038 static inline void ept_sync_global(void)
1039 {
1040 if (cpu_has_vmx_invept_global())
1041 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1042 }
1043
1044 static inline void ept_sync_context(u64 eptp)
1045 {
1046 if (enable_ept) {
1047 if (cpu_has_vmx_invept_context())
1048 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1049 else
1050 ept_sync_global();
1051 }
1052 }
1053
1054 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1055 {
1056 if (enable_ept) {
1057 if (cpu_has_vmx_invept_individual_addr())
1058 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1059 eptp, gpa);
1060 else
1061 ept_sync_context(eptp);
1062 }
1063 }
1064
1065 static __always_inline unsigned long vmcs_readl(unsigned long field)
1066 {
1067 unsigned long value;
1068
1069 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1070 : "=a"(value) : "d"(field) : "cc");
1071 return value;
1072 }
1073
1074 static __always_inline u16 vmcs_read16(unsigned long field)
1075 {
1076 return vmcs_readl(field);
1077 }
1078
1079 static __always_inline u32 vmcs_read32(unsigned long field)
1080 {
1081 return vmcs_readl(field);
1082 }
1083
1084 static __always_inline u64 vmcs_read64(unsigned long field)
1085 {
1086 #ifdef CONFIG_X86_64
1087 return vmcs_readl(field);
1088 #else
1089 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1090 #endif
1091 }
1092
1093 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1094 {
1095 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1096 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1097 dump_stack();
1098 }
1099
1100 static void vmcs_writel(unsigned long field, unsigned long value)
1101 {
1102 u8 error;
1103
1104 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1105 : "=q"(error) : "a"(value), "d"(field) : "cc");
1106 if (unlikely(error))
1107 vmwrite_error(field, value);
1108 }
1109
1110 static void vmcs_write16(unsigned long field, u16 value)
1111 {
1112 vmcs_writel(field, value);
1113 }
1114
1115 static void vmcs_write32(unsigned long field, u32 value)
1116 {
1117 vmcs_writel(field, value);
1118 }
1119
1120 static void vmcs_write64(unsigned long field, u64 value)
1121 {
1122 vmcs_writel(field, value);
1123 #ifndef CONFIG_X86_64
1124 asm volatile ("");
1125 vmcs_writel(field+1, value >> 32);
1126 #endif
1127 }
1128
1129 static void vmcs_clear_bits(unsigned long field, u32 mask)
1130 {
1131 vmcs_writel(field, vmcs_readl(field) & ~mask);
1132 }
1133
1134 static void vmcs_set_bits(unsigned long field, u32 mask)
1135 {
1136 vmcs_writel(field, vmcs_readl(field) | mask);
1137 }
1138
1139 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1140 {
1141 vmx->segment_cache.bitmask = 0;
1142 }
1143
1144 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1145 unsigned field)
1146 {
1147 bool ret;
1148 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1149
1150 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1151 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1152 vmx->segment_cache.bitmask = 0;
1153 }
1154 ret = vmx->segment_cache.bitmask & mask;
1155 vmx->segment_cache.bitmask |= mask;
1156 return ret;
1157 }
1158
1159 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161 u16 *p = &vmx->segment_cache.seg[seg].selector;
1162
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1164 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1165 return *p;
1166 }
1167
1168 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1169 {
1170 ulong *p = &vmx->segment_cache.seg[seg].base;
1171
1172 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1173 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1174 return *p;
1175 }
1176
1177 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1178 {
1179 u32 *p = &vmx->segment_cache.seg[seg].limit;
1180
1181 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1182 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1183 return *p;
1184 }
1185
1186 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1187 {
1188 u32 *p = &vmx->segment_cache.seg[seg].ar;
1189
1190 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1191 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1192 return *p;
1193 }
1194
1195 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1196 {
1197 u32 eb;
1198
1199 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1200 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1201 if ((vcpu->guest_debug &
1202 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1203 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1204 eb |= 1u << BP_VECTOR;
1205 if (to_vmx(vcpu)->rmode.vm86_active)
1206 eb = ~0;
1207 if (enable_ept)
1208 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1209 if (vcpu->fpu_active)
1210 eb &= ~(1u << NM_VECTOR);
1211
1212 /* When we are running a nested L2 guest and L1 specified for it a
1213 * certain exception bitmap, we must trap the same exceptions and pass
1214 * them to L1. When running L2, we will only handle the exceptions
1215 * specified above if L1 did not want them.
1216 */
1217 if (is_guest_mode(vcpu))
1218 eb |= get_vmcs12(vcpu)->exception_bitmap;
1219
1220 vmcs_write32(EXCEPTION_BITMAP, eb);
1221 }
1222
1223 static void clear_atomic_switch_msr_special(unsigned long entry,
1224 unsigned long exit)
1225 {
1226 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1227 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1228 }
1229
1230 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1231 {
1232 unsigned i;
1233 struct msr_autoload *m = &vmx->msr_autoload;
1234
1235 switch (msr) {
1236 case MSR_EFER:
1237 if (cpu_has_load_ia32_efer) {
1238 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1239 VM_EXIT_LOAD_IA32_EFER);
1240 return;
1241 }
1242 break;
1243 case MSR_CORE_PERF_GLOBAL_CTRL:
1244 if (cpu_has_load_perf_global_ctrl) {
1245 clear_atomic_switch_msr_special(
1246 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1247 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1248 return;
1249 }
1250 break;
1251 }
1252
1253 for (i = 0; i < m->nr; ++i)
1254 if (m->guest[i].index == msr)
1255 break;
1256
1257 if (i == m->nr)
1258 return;
1259 --m->nr;
1260 m->guest[i] = m->guest[m->nr];
1261 m->host[i] = m->host[m->nr];
1262 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1263 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1264 }
1265
1266 static void add_atomic_switch_msr_special(unsigned long entry,
1267 unsigned long exit, unsigned long guest_val_vmcs,
1268 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1269 {
1270 vmcs_write64(guest_val_vmcs, guest_val);
1271 vmcs_write64(host_val_vmcs, host_val);
1272 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1273 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1274 }
1275
1276 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1277 u64 guest_val, u64 host_val)
1278 {
1279 unsigned i;
1280 struct msr_autoload *m = &vmx->msr_autoload;
1281
1282 switch (msr) {
1283 case MSR_EFER:
1284 if (cpu_has_load_ia32_efer) {
1285 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1286 VM_EXIT_LOAD_IA32_EFER,
1287 GUEST_IA32_EFER,
1288 HOST_IA32_EFER,
1289 guest_val, host_val);
1290 return;
1291 }
1292 break;
1293 case MSR_CORE_PERF_GLOBAL_CTRL:
1294 if (cpu_has_load_perf_global_ctrl) {
1295 add_atomic_switch_msr_special(
1296 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1297 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1298 GUEST_IA32_PERF_GLOBAL_CTRL,
1299 HOST_IA32_PERF_GLOBAL_CTRL,
1300 guest_val, host_val);
1301 return;
1302 }
1303 break;
1304 }
1305
1306 for (i = 0; i < m->nr; ++i)
1307 if (m->guest[i].index == msr)
1308 break;
1309
1310 if (i == NR_AUTOLOAD_MSRS) {
1311 printk_once(KERN_WARNING"Not enough mst switch entries. "
1312 "Can't add msr %x\n", msr);
1313 return;
1314 } else if (i == m->nr) {
1315 ++m->nr;
1316 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1317 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1318 }
1319
1320 m->guest[i].index = msr;
1321 m->guest[i].value = guest_val;
1322 m->host[i].index = msr;
1323 m->host[i].value = host_val;
1324 }
1325
1326 static void reload_tss(void)
1327 {
1328 /*
1329 * VT restores TR but not its size. Useless.
1330 */
1331 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1332 struct desc_struct *descs;
1333
1334 descs = (void *)gdt->address;
1335 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1336 load_TR_desc();
1337 }
1338
1339 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1340 {
1341 u64 guest_efer;
1342 u64 ignore_bits;
1343
1344 guest_efer = vmx->vcpu.arch.efer;
1345
1346 /*
1347 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1348 * outside long mode
1349 */
1350 ignore_bits = EFER_NX | EFER_SCE;
1351 #ifdef CONFIG_X86_64
1352 ignore_bits |= EFER_LMA | EFER_LME;
1353 /* SCE is meaningful only in long mode on Intel */
1354 if (guest_efer & EFER_LMA)
1355 ignore_bits &= ~(u64)EFER_SCE;
1356 #endif
1357 guest_efer &= ~ignore_bits;
1358 guest_efer |= host_efer & ignore_bits;
1359 vmx->guest_msrs[efer_offset].data = guest_efer;
1360 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1361
1362 clear_atomic_switch_msr(vmx, MSR_EFER);
1363 /* On ept, can't emulate nx, and must switch nx atomically */
1364 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1365 guest_efer = vmx->vcpu.arch.efer;
1366 if (!(guest_efer & EFER_LMA))
1367 guest_efer &= ~EFER_LME;
1368 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1369 return false;
1370 }
1371
1372 return true;
1373 }
1374
1375 static unsigned long segment_base(u16 selector)
1376 {
1377 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1378 struct desc_struct *d;
1379 unsigned long table_base;
1380 unsigned long v;
1381
1382 if (!(selector & ~3))
1383 return 0;
1384
1385 table_base = gdt->address;
1386
1387 if (selector & 4) { /* from ldt */
1388 u16 ldt_selector = kvm_read_ldt();
1389
1390 if (!(ldt_selector & ~3))
1391 return 0;
1392
1393 table_base = segment_base(ldt_selector);
1394 }
1395 d = (struct desc_struct *)(table_base + (selector & ~7));
1396 v = get_desc_base(d);
1397 #ifdef CONFIG_X86_64
1398 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1399 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1400 #endif
1401 return v;
1402 }
1403
1404 static inline unsigned long kvm_read_tr_base(void)
1405 {
1406 u16 tr;
1407 asm("str %0" : "=g"(tr));
1408 return segment_base(tr);
1409 }
1410
1411 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1412 {
1413 struct vcpu_vmx *vmx = to_vmx(vcpu);
1414 int i;
1415
1416 if (vmx->host_state.loaded)
1417 return;
1418
1419 vmx->host_state.loaded = 1;
1420 /*
1421 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1422 * allow segment selectors with cpl > 0 or ti == 1.
1423 */
1424 vmx->host_state.ldt_sel = kvm_read_ldt();
1425 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1426 savesegment(fs, vmx->host_state.fs_sel);
1427 if (!(vmx->host_state.fs_sel & 7)) {
1428 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1429 vmx->host_state.fs_reload_needed = 0;
1430 } else {
1431 vmcs_write16(HOST_FS_SELECTOR, 0);
1432 vmx->host_state.fs_reload_needed = 1;
1433 }
1434 savesegment(gs, vmx->host_state.gs_sel);
1435 if (!(vmx->host_state.gs_sel & 7))
1436 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1437 else {
1438 vmcs_write16(HOST_GS_SELECTOR, 0);
1439 vmx->host_state.gs_ldt_reload_needed = 1;
1440 }
1441
1442 #ifdef CONFIG_X86_64
1443 savesegment(ds, vmx->host_state.ds_sel);
1444 savesegment(es, vmx->host_state.es_sel);
1445 #endif
1446
1447 #ifdef CONFIG_X86_64
1448 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1449 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1450 #else
1451 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1452 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1453 #endif
1454
1455 #ifdef CONFIG_X86_64
1456 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1457 if (is_long_mode(&vmx->vcpu))
1458 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1459 #endif
1460 for (i = 0; i < vmx->save_nmsrs; ++i)
1461 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1462 vmx->guest_msrs[i].data,
1463 vmx->guest_msrs[i].mask);
1464 }
1465
1466 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1467 {
1468 if (!vmx->host_state.loaded)
1469 return;
1470
1471 ++vmx->vcpu.stat.host_state_reload;
1472 vmx->host_state.loaded = 0;
1473 #ifdef CONFIG_X86_64
1474 if (is_long_mode(&vmx->vcpu))
1475 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1476 #endif
1477 if (vmx->host_state.gs_ldt_reload_needed) {
1478 kvm_load_ldt(vmx->host_state.ldt_sel);
1479 #ifdef CONFIG_X86_64
1480 load_gs_index(vmx->host_state.gs_sel);
1481 #else
1482 loadsegment(gs, vmx->host_state.gs_sel);
1483 #endif
1484 }
1485 if (vmx->host_state.fs_reload_needed)
1486 loadsegment(fs, vmx->host_state.fs_sel);
1487 #ifdef CONFIG_X86_64
1488 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1489 loadsegment(ds, vmx->host_state.ds_sel);
1490 loadsegment(es, vmx->host_state.es_sel);
1491 }
1492 #endif
1493 reload_tss();
1494 #ifdef CONFIG_X86_64
1495 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1496 #endif
1497 if (user_has_fpu())
1498 clts();
1499 load_gdt(&__get_cpu_var(host_gdt));
1500 }
1501
1502 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503 {
1504 preempt_disable();
1505 __vmx_load_host_state(vmx);
1506 preempt_enable();
1507 }
1508
1509 /*
1510 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511 * vcpu mutex is already taken.
1512 */
1513 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1514 {
1515 struct vcpu_vmx *vmx = to_vmx(vcpu);
1516 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1517
1518 if (!vmm_exclusive)
1519 kvm_cpu_vmxon(phys_addr);
1520 else if (vmx->loaded_vmcs->cpu != cpu)
1521 loaded_vmcs_clear(vmx->loaded_vmcs);
1522
1523 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525 vmcs_load(vmx->loaded_vmcs->vmcs);
1526 }
1527
1528 if (vmx->loaded_vmcs->cpu != cpu) {
1529 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1530 unsigned long sysenter_esp;
1531
1532 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1533 local_irq_disable();
1534 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535 &per_cpu(loaded_vmcss_on_cpu, cpu));
1536 local_irq_enable();
1537
1538 /*
1539 * Linux uses per-cpu TSS and GDT, so set these when switching
1540 * processors.
1541 */
1542 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1543 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1544
1545 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1547 vmx->loaded_vmcs->cpu = cpu;
1548 }
1549 }
1550
1551 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552 {
1553 __vmx_load_host_state(to_vmx(vcpu));
1554 if (!vmm_exclusive) {
1555 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556 vcpu->cpu = -1;
1557 kvm_cpu_vmxoff();
1558 }
1559 }
1560
1561 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562 {
1563 ulong cr0;
1564
1565 if (vcpu->fpu_active)
1566 return;
1567 vcpu->fpu_active = 1;
1568 cr0 = vmcs_readl(GUEST_CR0);
1569 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571 vmcs_writel(GUEST_CR0, cr0);
1572 update_exception_bitmap(vcpu);
1573 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1574 if (is_guest_mode(vcpu))
1575 vcpu->arch.cr0_guest_owned_bits &=
1576 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1577 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1578 }
1579
1580 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
1582 /*
1583 * Return the cr0 value that a nested guest would read. This is a combination
1584 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585 * its hypervisor (cr0_read_shadow).
1586 */
1587 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588 {
1589 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591 }
1592 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593 {
1594 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596 }
1597
1598 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599 {
1600 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601 * set this *before* calling this function.
1602 */
1603 vmx_decache_cr0_guest_bits(vcpu);
1604 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1605 update_exception_bitmap(vcpu);
1606 vcpu->arch.cr0_guest_owned_bits = 0;
1607 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1608 if (is_guest_mode(vcpu)) {
1609 /*
1610 * L1's specified read shadow might not contain the TS bit,
1611 * so now that we turned on shadowing of this bit, we need to
1612 * set this bit of the shadow. Like in nested_vmx_run we need
1613 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614 * up-to-date here because we just decached cr0.TS (and we'll
1615 * only update vmcs12->guest_cr0 on nested exit).
1616 */
1617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619 (vcpu->arch.cr0 & X86_CR0_TS);
1620 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621 } else
1622 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1623 }
1624
1625 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626 {
1627 unsigned long rflags, save_rflags;
1628
1629 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631 rflags = vmcs_readl(GUEST_RFLAGS);
1632 if (to_vmx(vcpu)->rmode.vm86_active) {
1633 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636 }
1637 to_vmx(vcpu)->rflags = rflags;
1638 }
1639 return to_vmx(vcpu)->rflags;
1640 }
1641
1642 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643 {
1644 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1645 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1646 to_vmx(vcpu)->rflags = rflags;
1647 if (to_vmx(vcpu)->rmode.vm86_active) {
1648 to_vmx(vcpu)->rmode.save_rflags = rflags;
1649 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1650 }
1651 vmcs_writel(GUEST_RFLAGS, rflags);
1652 }
1653
1654 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655 {
1656 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657 int ret = 0;
1658
1659 if (interruptibility & GUEST_INTR_STATE_STI)
1660 ret |= KVM_X86_SHADOW_INT_STI;
1661 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1662 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1663
1664 return ret & mask;
1665 }
1666
1667 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668 {
1669 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670 u32 interruptibility = interruptibility_old;
1671
1672 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
1674 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1675 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1676 else if (mask & KVM_X86_SHADOW_INT_STI)
1677 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679 if ((interruptibility != interruptibility_old))
1680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681 }
1682
1683 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684 {
1685 unsigned long rip;
1686
1687 rip = kvm_rip_read(vcpu);
1688 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1689 kvm_rip_write(vcpu, rip);
1690
1691 /* skipping an emulated instruction also counts */
1692 vmx_set_interrupt_shadow(vcpu, 0);
1693 }
1694
1695 /*
1696 * KVM wants to inject page-faults which it got to the guest. This function
1697 * checks whether in a nested guest, we need to inject them to L1 or L2.
1698 * This function assumes it is called with the exit reason in vmcs02 being
1699 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700 * is running).
1701 */
1702 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703 {
1704 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1707 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1708 return 0;
1709
1710 nested_vmx_vmexit(vcpu);
1711 return 1;
1712 }
1713
1714 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1715 bool has_error_code, u32 error_code,
1716 bool reinject)
1717 {
1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
1719 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1720
1721 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722 nested_pf_handled(vcpu))
1723 return;
1724
1725 if (has_error_code) {
1726 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1727 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728 }
1729
1730 if (vmx->rmode.vm86_active) {
1731 int inc_eip = 0;
1732 if (kvm_exception_is_soft(nr))
1733 inc_eip = vcpu->arch.event_exit_inst_len;
1734 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1735 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1736 return;
1737 }
1738
1739 if (kvm_exception_is_soft(nr)) {
1740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741 vmx->vcpu.arch.event_exit_inst_len);
1742 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743 } else
1744 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1747 }
1748
1749 static bool vmx_rdtscp_supported(void)
1750 {
1751 return cpu_has_vmx_rdtscp();
1752 }
1753
1754 static bool vmx_invpcid_supported(void)
1755 {
1756 return cpu_has_vmx_invpcid() && enable_ept;
1757 }
1758
1759 /*
1760 * Swap MSR entry in host/guest MSR entry array.
1761 */
1762 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1763 {
1764 struct shared_msr_entry tmp;
1765
1766 tmp = vmx->guest_msrs[to];
1767 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1768 vmx->guest_msrs[from] = tmp;
1769 }
1770
1771 /*
1772 * Set up the vmcs to automatically save and restore system
1773 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1774 * mode, as fiddling with msrs is very expensive.
1775 */
1776 static void setup_msrs(struct vcpu_vmx *vmx)
1777 {
1778 int save_nmsrs, index;
1779 unsigned long *msr_bitmap;
1780
1781 save_nmsrs = 0;
1782 #ifdef CONFIG_X86_64
1783 if (is_long_mode(&vmx->vcpu)) {
1784 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1785 if (index >= 0)
1786 move_msr_up(vmx, index, save_nmsrs++);
1787 index = __find_msr_index(vmx, MSR_LSTAR);
1788 if (index >= 0)
1789 move_msr_up(vmx, index, save_nmsrs++);
1790 index = __find_msr_index(vmx, MSR_CSTAR);
1791 if (index >= 0)
1792 move_msr_up(vmx, index, save_nmsrs++);
1793 index = __find_msr_index(vmx, MSR_TSC_AUX);
1794 if (index >= 0 && vmx->rdtscp_enabled)
1795 move_msr_up(vmx, index, save_nmsrs++);
1796 /*
1797 * MSR_STAR is only needed on long mode guests, and only
1798 * if efer.sce is enabled.
1799 */
1800 index = __find_msr_index(vmx, MSR_STAR);
1801 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1802 move_msr_up(vmx, index, save_nmsrs++);
1803 }
1804 #endif
1805 index = __find_msr_index(vmx, MSR_EFER);
1806 if (index >= 0 && update_transition_efer(vmx, index))
1807 move_msr_up(vmx, index, save_nmsrs++);
1808
1809 vmx->save_nmsrs = save_nmsrs;
1810
1811 if (cpu_has_vmx_msr_bitmap()) {
1812 if (is_long_mode(&vmx->vcpu))
1813 msr_bitmap = vmx_msr_bitmap_longmode;
1814 else
1815 msr_bitmap = vmx_msr_bitmap_legacy;
1816
1817 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1818 }
1819 }
1820
1821 /*
1822 * reads and returns guest's timestamp counter "register"
1823 * guest_tsc = host_tsc + tsc_offset -- 21.3
1824 */
1825 static u64 guest_read_tsc(void)
1826 {
1827 u64 host_tsc, tsc_offset;
1828
1829 rdtscll(host_tsc);
1830 tsc_offset = vmcs_read64(TSC_OFFSET);
1831 return host_tsc + tsc_offset;
1832 }
1833
1834 /*
1835 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1836 * counter, even if a nested guest (L2) is currently running.
1837 */
1838 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1839 {
1840 u64 host_tsc, tsc_offset;
1841
1842 rdtscll(host_tsc);
1843 tsc_offset = is_guest_mode(vcpu) ?
1844 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1845 vmcs_read64(TSC_OFFSET);
1846 return host_tsc + tsc_offset;
1847 }
1848
1849 /*
1850 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1851 * software catchup for faster rates on slower CPUs.
1852 */
1853 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1854 {
1855 if (!scale)
1856 return;
1857
1858 if (user_tsc_khz > tsc_khz) {
1859 vcpu->arch.tsc_catchup = 1;
1860 vcpu->arch.tsc_always_catchup = 1;
1861 } else
1862 WARN(1, "user requested TSC rate below hardware speed\n");
1863 }
1864
1865 /*
1866 * writes 'offset' into guest's timestamp counter offset register
1867 */
1868 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1869 {
1870 if (is_guest_mode(vcpu)) {
1871 /*
1872 * We're here if L1 chose not to trap WRMSR to TSC. According
1873 * to the spec, this should set L1's TSC; The offset that L1
1874 * set for L2 remains unchanged, and still needs to be added
1875 * to the newly set TSC to get L2's TSC.
1876 */
1877 struct vmcs12 *vmcs12;
1878 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1879 /* recalculate vmcs02.TSC_OFFSET: */
1880 vmcs12 = get_vmcs12(vcpu);
1881 vmcs_write64(TSC_OFFSET, offset +
1882 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1883 vmcs12->tsc_offset : 0));
1884 } else {
1885 vmcs_write64(TSC_OFFSET, offset);
1886 }
1887 }
1888
1889 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1890 {
1891 u64 offset = vmcs_read64(TSC_OFFSET);
1892 vmcs_write64(TSC_OFFSET, offset + adjustment);
1893 if (is_guest_mode(vcpu)) {
1894 /* Even when running L2, the adjustment needs to apply to L1 */
1895 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1896 }
1897 }
1898
1899 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1900 {
1901 return target_tsc - native_read_tsc();
1902 }
1903
1904 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1905 {
1906 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1907 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1908 }
1909
1910 /*
1911 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1912 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1913 * all guests if the "nested" module option is off, and can also be disabled
1914 * for a single guest by disabling its VMX cpuid bit.
1915 */
1916 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1917 {
1918 return nested && guest_cpuid_has_vmx(vcpu);
1919 }
1920
1921 /*
1922 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1923 * returned for the various VMX controls MSRs when nested VMX is enabled.
1924 * The same values should also be used to verify that vmcs12 control fields are
1925 * valid during nested entry from L1 to L2.
1926 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1927 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1928 * bit in the high half is on if the corresponding bit in the control field
1929 * may be on. See also vmx_control_verify().
1930 * TODO: allow these variables to be modified (downgraded) by module options
1931 * or other means.
1932 */
1933 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1934 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1935 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1936 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1937 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1938 static __init void nested_vmx_setup_ctls_msrs(void)
1939 {
1940 /*
1941 * Note that as a general rule, the high half of the MSRs (bits in
1942 * the control fields which may be 1) should be initialized by the
1943 * intersection of the underlying hardware's MSR (i.e., features which
1944 * can be supported) and the list of features we want to expose -
1945 * because they are known to be properly supported in our code.
1946 * Also, usually, the low half of the MSRs (bits which must be 1) can
1947 * be set to 0, meaning that L1 may turn off any of these bits. The
1948 * reason is that if one of these bits is necessary, it will appear
1949 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1950 * fields of vmcs01 and vmcs02, will turn these bits off - and
1951 * nested_vmx_exit_handled() will not pass related exits to L1.
1952 * These rules have exceptions below.
1953 */
1954
1955 /* pin-based controls */
1956 /*
1957 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1958 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1959 */
1960 nested_vmx_pinbased_ctls_low = 0x16 ;
1961 nested_vmx_pinbased_ctls_high = 0x16 |
1962 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1963 PIN_BASED_VIRTUAL_NMIS;
1964
1965 /* exit controls */
1966 nested_vmx_exit_ctls_low = 0;
1967 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1968 #ifdef CONFIG_X86_64
1969 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1970 #else
1971 nested_vmx_exit_ctls_high = 0;
1972 #endif
1973
1974 /* entry controls */
1975 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1976 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1977 nested_vmx_entry_ctls_low = 0;
1978 nested_vmx_entry_ctls_high &=
1979 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1980
1981 /* cpu-based controls */
1982 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1983 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1984 nested_vmx_procbased_ctls_low = 0;
1985 nested_vmx_procbased_ctls_high &=
1986 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1987 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1988 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1989 CPU_BASED_CR3_STORE_EXITING |
1990 #ifdef CONFIG_X86_64
1991 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1992 #endif
1993 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1994 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1995 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
1996 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1997 /*
1998 * We can allow some features even when not supported by the
1999 * hardware. For example, L1 can specify an MSR bitmap - and we
2000 * can use it to avoid exits to L1 - even when L0 runs L2
2001 * without MSR bitmaps.
2002 */
2003 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2004
2005 /* secondary cpu-based controls */
2006 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2007 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2008 nested_vmx_secondary_ctls_low = 0;
2009 nested_vmx_secondary_ctls_high &=
2010 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2011 }
2012
2013 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2014 {
2015 /*
2016 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2017 */
2018 return ((control & high) | low) == control;
2019 }
2020
2021 static inline u64 vmx_control_msr(u32 low, u32 high)
2022 {
2023 return low | ((u64)high << 32);
2024 }
2025
2026 /*
2027 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2028 * also let it use VMX-specific MSRs.
2029 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2030 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2031 * like all other MSRs).
2032 */
2033 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2034 {
2035 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2036 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2037 /*
2038 * According to the spec, processors which do not support VMX
2039 * should throw a #GP(0) when VMX capability MSRs are read.
2040 */
2041 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2042 return 1;
2043 }
2044
2045 switch (msr_index) {
2046 case MSR_IA32_FEATURE_CONTROL:
2047 *pdata = 0;
2048 break;
2049 case MSR_IA32_VMX_BASIC:
2050 /*
2051 * This MSR reports some information about VMX support. We
2052 * should return information about the VMX we emulate for the
2053 * guest, and the VMCS structure we give it - not about the
2054 * VMX support of the underlying hardware.
2055 */
2056 *pdata = VMCS12_REVISION |
2057 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2058 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2059 break;
2060 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2061 case MSR_IA32_VMX_PINBASED_CTLS:
2062 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2063 nested_vmx_pinbased_ctls_high);
2064 break;
2065 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2066 case MSR_IA32_VMX_PROCBASED_CTLS:
2067 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2068 nested_vmx_procbased_ctls_high);
2069 break;
2070 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2071 case MSR_IA32_VMX_EXIT_CTLS:
2072 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2073 nested_vmx_exit_ctls_high);
2074 break;
2075 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2076 case MSR_IA32_VMX_ENTRY_CTLS:
2077 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2078 nested_vmx_entry_ctls_high);
2079 break;
2080 case MSR_IA32_VMX_MISC:
2081 *pdata = 0;
2082 break;
2083 /*
2084 * These MSRs specify bits which the guest must keep fixed (on or off)
2085 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2086 * We picked the standard core2 setting.
2087 */
2088 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2089 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2090 case MSR_IA32_VMX_CR0_FIXED0:
2091 *pdata = VMXON_CR0_ALWAYSON;
2092 break;
2093 case MSR_IA32_VMX_CR0_FIXED1:
2094 *pdata = -1ULL;
2095 break;
2096 case MSR_IA32_VMX_CR4_FIXED0:
2097 *pdata = VMXON_CR4_ALWAYSON;
2098 break;
2099 case MSR_IA32_VMX_CR4_FIXED1:
2100 *pdata = -1ULL;
2101 break;
2102 case MSR_IA32_VMX_VMCS_ENUM:
2103 *pdata = 0x1f;
2104 break;
2105 case MSR_IA32_VMX_PROCBASED_CTLS2:
2106 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2107 nested_vmx_secondary_ctls_high);
2108 break;
2109 case MSR_IA32_VMX_EPT_VPID_CAP:
2110 /* Currently, no nested ept or nested vpid */
2111 *pdata = 0;
2112 break;
2113 default:
2114 return 0;
2115 }
2116
2117 return 1;
2118 }
2119
2120 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2121 {
2122 if (!nested_vmx_allowed(vcpu))
2123 return 0;
2124
2125 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2126 /* TODO: the right thing. */
2127 return 1;
2128 /*
2129 * No need to treat VMX capability MSRs specially: If we don't handle
2130 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2131 */
2132 return 0;
2133 }
2134
2135 /*
2136 * Reads an msr value (of 'msr_index') into 'pdata'.
2137 * Returns 0 on success, non-0 otherwise.
2138 * Assumes vcpu_load() was already called.
2139 */
2140 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2141 {
2142 u64 data;
2143 struct shared_msr_entry *msr;
2144
2145 if (!pdata) {
2146 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2147 return -EINVAL;
2148 }
2149
2150 switch (msr_index) {
2151 #ifdef CONFIG_X86_64
2152 case MSR_FS_BASE:
2153 data = vmcs_readl(GUEST_FS_BASE);
2154 break;
2155 case MSR_GS_BASE:
2156 data = vmcs_readl(GUEST_GS_BASE);
2157 break;
2158 case MSR_KERNEL_GS_BASE:
2159 vmx_load_host_state(to_vmx(vcpu));
2160 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2161 break;
2162 #endif
2163 case MSR_EFER:
2164 return kvm_get_msr_common(vcpu, msr_index, pdata);
2165 case MSR_IA32_TSC:
2166 data = guest_read_tsc();
2167 break;
2168 case MSR_IA32_SYSENTER_CS:
2169 data = vmcs_read32(GUEST_SYSENTER_CS);
2170 break;
2171 case MSR_IA32_SYSENTER_EIP:
2172 data = vmcs_readl(GUEST_SYSENTER_EIP);
2173 break;
2174 case MSR_IA32_SYSENTER_ESP:
2175 data = vmcs_readl(GUEST_SYSENTER_ESP);
2176 break;
2177 case MSR_TSC_AUX:
2178 if (!to_vmx(vcpu)->rdtscp_enabled)
2179 return 1;
2180 /* Otherwise falls through */
2181 default:
2182 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2183 return 0;
2184 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2185 if (msr) {
2186 data = msr->data;
2187 break;
2188 }
2189 return kvm_get_msr_common(vcpu, msr_index, pdata);
2190 }
2191
2192 *pdata = data;
2193 return 0;
2194 }
2195
2196 /*
2197 * Writes msr value into into the appropriate "register".
2198 * Returns 0 on success, non-0 otherwise.
2199 * Assumes vcpu_load() was already called.
2200 */
2201 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2202 {
2203 struct vcpu_vmx *vmx = to_vmx(vcpu);
2204 struct shared_msr_entry *msr;
2205 int ret = 0;
2206
2207 switch (msr_index) {
2208 case MSR_EFER:
2209 ret = kvm_set_msr_common(vcpu, msr_index, data);
2210 break;
2211 #ifdef CONFIG_X86_64
2212 case MSR_FS_BASE:
2213 vmx_segment_cache_clear(vmx);
2214 vmcs_writel(GUEST_FS_BASE, data);
2215 break;
2216 case MSR_GS_BASE:
2217 vmx_segment_cache_clear(vmx);
2218 vmcs_writel(GUEST_GS_BASE, data);
2219 break;
2220 case MSR_KERNEL_GS_BASE:
2221 vmx_load_host_state(vmx);
2222 vmx->msr_guest_kernel_gs_base = data;
2223 break;
2224 #endif
2225 case MSR_IA32_SYSENTER_CS:
2226 vmcs_write32(GUEST_SYSENTER_CS, data);
2227 break;
2228 case MSR_IA32_SYSENTER_EIP:
2229 vmcs_writel(GUEST_SYSENTER_EIP, data);
2230 break;
2231 case MSR_IA32_SYSENTER_ESP:
2232 vmcs_writel(GUEST_SYSENTER_ESP, data);
2233 break;
2234 case MSR_IA32_TSC:
2235 kvm_write_tsc(vcpu, data);
2236 break;
2237 case MSR_IA32_CR_PAT:
2238 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2239 vmcs_write64(GUEST_IA32_PAT, data);
2240 vcpu->arch.pat = data;
2241 break;
2242 }
2243 ret = kvm_set_msr_common(vcpu, msr_index, data);
2244 break;
2245 case MSR_TSC_AUX:
2246 if (!vmx->rdtscp_enabled)
2247 return 1;
2248 /* Check reserved bit, higher 32 bits should be zero */
2249 if ((data >> 32) != 0)
2250 return 1;
2251 /* Otherwise falls through */
2252 default:
2253 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2254 break;
2255 msr = find_msr_entry(vmx, msr_index);
2256 if (msr) {
2257 msr->data = data;
2258 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2259 preempt_disable();
2260 kvm_set_shared_msr(msr->index, msr->data,
2261 msr->mask);
2262 preempt_enable();
2263 }
2264 break;
2265 }
2266 ret = kvm_set_msr_common(vcpu, msr_index, data);
2267 }
2268
2269 return ret;
2270 }
2271
2272 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2273 {
2274 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2275 switch (reg) {
2276 case VCPU_REGS_RSP:
2277 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2278 break;
2279 case VCPU_REGS_RIP:
2280 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2281 break;
2282 case VCPU_EXREG_PDPTR:
2283 if (enable_ept)
2284 ept_save_pdptrs(vcpu);
2285 break;
2286 default:
2287 break;
2288 }
2289 }
2290
2291 static __init int cpu_has_kvm_support(void)
2292 {
2293 return cpu_has_vmx();
2294 }
2295
2296 static __init int vmx_disabled_by_bios(void)
2297 {
2298 u64 msr;
2299
2300 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2301 if (msr & FEATURE_CONTROL_LOCKED) {
2302 /* launched w/ TXT and VMX disabled */
2303 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2304 && tboot_enabled())
2305 return 1;
2306 /* launched w/o TXT and VMX only enabled w/ TXT */
2307 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2308 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309 && !tboot_enabled()) {
2310 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2311 "activate TXT before enabling KVM\n");
2312 return 1;
2313 }
2314 /* launched w/o TXT and VMX disabled */
2315 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2316 && !tboot_enabled())
2317 return 1;
2318 }
2319
2320 return 0;
2321 }
2322
2323 static void kvm_cpu_vmxon(u64 addr)
2324 {
2325 asm volatile (ASM_VMX_VMXON_RAX
2326 : : "a"(&addr), "m"(addr)
2327 : "memory", "cc");
2328 }
2329
2330 static int hardware_enable(void *garbage)
2331 {
2332 int cpu = raw_smp_processor_id();
2333 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2334 u64 old, test_bits;
2335
2336 if (read_cr4() & X86_CR4_VMXE)
2337 return -EBUSY;
2338
2339 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2340 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2341
2342 test_bits = FEATURE_CONTROL_LOCKED;
2343 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2344 if (tboot_enabled())
2345 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2346
2347 if ((old & test_bits) != test_bits) {
2348 /* enable and lock */
2349 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2350 }
2351 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2352
2353 if (vmm_exclusive) {
2354 kvm_cpu_vmxon(phys_addr);
2355 ept_sync_global();
2356 }
2357
2358 store_gdt(&__get_cpu_var(host_gdt));
2359
2360 return 0;
2361 }
2362
2363 static void vmclear_local_loaded_vmcss(void)
2364 {
2365 int cpu = raw_smp_processor_id();
2366 struct loaded_vmcs *v, *n;
2367
2368 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2369 loaded_vmcss_on_cpu_link)
2370 __loaded_vmcs_clear(v);
2371 }
2372
2373
2374 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2375 * tricks.
2376 */
2377 static void kvm_cpu_vmxoff(void)
2378 {
2379 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2380 }
2381
2382 static void hardware_disable(void *garbage)
2383 {
2384 if (vmm_exclusive) {
2385 vmclear_local_loaded_vmcss();
2386 kvm_cpu_vmxoff();
2387 }
2388 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2389 }
2390
2391 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2392 u32 msr, u32 *result)
2393 {
2394 u32 vmx_msr_low, vmx_msr_high;
2395 u32 ctl = ctl_min | ctl_opt;
2396
2397 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2398
2399 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2400 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2401
2402 /* Ensure minimum (required) set of control bits are supported. */
2403 if (ctl_min & ~ctl)
2404 return -EIO;
2405
2406 *result = ctl;
2407 return 0;
2408 }
2409
2410 static __init bool allow_1_setting(u32 msr, u32 ctl)
2411 {
2412 u32 vmx_msr_low, vmx_msr_high;
2413
2414 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2415 return vmx_msr_high & ctl;
2416 }
2417
2418 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2419 {
2420 u32 vmx_msr_low, vmx_msr_high;
2421 u32 min, opt, min2, opt2;
2422 u32 _pin_based_exec_control = 0;
2423 u32 _cpu_based_exec_control = 0;
2424 u32 _cpu_based_2nd_exec_control = 0;
2425 u32 _vmexit_control = 0;
2426 u32 _vmentry_control = 0;
2427
2428 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2429 opt = PIN_BASED_VIRTUAL_NMIS;
2430 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2431 &_pin_based_exec_control) < 0)
2432 return -EIO;
2433
2434 min = CPU_BASED_HLT_EXITING |
2435 #ifdef CONFIG_X86_64
2436 CPU_BASED_CR8_LOAD_EXITING |
2437 CPU_BASED_CR8_STORE_EXITING |
2438 #endif
2439 CPU_BASED_CR3_LOAD_EXITING |
2440 CPU_BASED_CR3_STORE_EXITING |
2441 CPU_BASED_USE_IO_BITMAPS |
2442 CPU_BASED_MOV_DR_EXITING |
2443 CPU_BASED_USE_TSC_OFFSETING |
2444 CPU_BASED_MWAIT_EXITING |
2445 CPU_BASED_MONITOR_EXITING |
2446 CPU_BASED_INVLPG_EXITING |
2447 CPU_BASED_RDPMC_EXITING;
2448
2449 opt = CPU_BASED_TPR_SHADOW |
2450 CPU_BASED_USE_MSR_BITMAPS |
2451 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2452 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2453 &_cpu_based_exec_control) < 0)
2454 return -EIO;
2455 #ifdef CONFIG_X86_64
2456 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2457 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2458 ~CPU_BASED_CR8_STORE_EXITING;
2459 #endif
2460 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2461 min2 = 0;
2462 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2463 SECONDARY_EXEC_WBINVD_EXITING |
2464 SECONDARY_EXEC_ENABLE_VPID |
2465 SECONDARY_EXEC_ENABLE_EPT |
2466 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2467 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2468 SECONDARY_EXEC_RDTSCP |
2469 SECONDARY_EXEC_ENABLE_INVPCID;
2470 if (adjust_vmx_controls(min2, opt2,
2471 MSR_IA32_VMX_PROCBASED_CTLS2,
2472 &_cpu_based_2nd_exec_control) < 0)
2473 return -EIO;
2474 }
2475 #ifndef CONFIG_X86_64
2476 if (!(_cpu_based_2nd_exec_control &
2477 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2478 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2479 #endif
2480 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2481 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2482 enabled */
2483 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2484 CPU_BASED_CR3_STORE_EXITING |
2485 CPU_BASED_INVLPG_EXITING);
2486 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2487 vmx_capability.ept, vmx_capability.vpid);
2488 }
2489
2490 min = 0;
2491 #ifdef CONFIG_X86_64
2492 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2493 #endif
2494 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2495 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2496 &_vmexit_control) < 0)
2497 return -EIO;
2498
2499 min = 0;
2500 opt = VM_ENTRY_LOAD_IA32_PAT;
2501 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2502 &_vmentry_control) < 0)
2503 return -EIO;
2504
2505 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2506
2507 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2508 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2509 return -EIO;
2510
2511 #ifdef CONFIG_X86_64
2512 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2513 if (vmx_msr_high & (1u<<16))
2514 return -EIO;
2515 #endif
2516
2517 /* Require Write-Back (WB) memory type for VMCS accesses. */
2518 if (((vmx_msr_high >> 18) & 15) != 6)
2519 return -EIO;
2520
2521 vmcs_conf->size = vmx_msr_high & 0x1fff;
2522 vmcs_conf->order = get_order(vmcs_config.size);
2523 vmcs_conf->revision_id = vmx_msr_low;
2524
2525 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2526 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2527 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2528 vmcs_conf->vmexit_ctrl = _vmexit_control;
2529 vmcs_conf->vmentry_ctrl = _vmentry_control;
2530
2531 cpu_has_load_ia32_efer =
2532 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2533 VM_ENTRY_LOAD_IA32_EFER)
2534 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2535 VM_EXIT_LOAD_IA32_EFER);
2536
2537 cpu_has_load_perf_global_ctrl =
2538 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2539 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2540 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2541 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2542
2543 /*
2544 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2545 * but due to arrata below it can't be used. Workaround is to use
2546 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2547 *
2548 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2549 *
2550 * AAK155 (model 26)
2551 * AAP115 (model 30)
2552 * AAT100 (model 37)
2553 * BC86,AAY89,BD102 (model 44)
2554 * BA97 (model 46)
2555 *
2556 */
2557 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2558 switch (boot_cpu_data.x86_model) {
2559 case 26:
2560 case 30:
2561 case 37:
2562 case 44:
2563 case 46:
2564 cpu_has_load_perf_global_ctrl = false;
2565 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2566 "does not work properly. Using workaround\n");
2567 break;
2568 default:
2569 break;
2570 }
2571 }
2572
2573 return 0;
2574 }
2575
2576 static struct vmcs *alloc_vmcs_cpu(int cpu)
2577 {
2578 int node = cpu_to_node(cpu);
2579 struct page *pages;
2580 struct vmcs *vmcs;
2581
2582 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2583 if (!pages)
2584 return NULL;
2585 vmcs = page_address(pages);
2586 memset(vmcs, 0, vmcs_config.size);
2587 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2588 return vmcs;
2589 }
2590
2591 static struct vmcs *alloc_vmcs(void)
2592 {
2593 return alloc_vmcs_cpu(raw_smp_processor_id());
2594 }
2595
2596 static void free_vmcs(struct vmcs *vmcs)
2597 {
2598 free_pages((unsigned long)vmcs, vmcs_config.order);
2599 }
2600
2601 /*
2602 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2603 */
2604 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2605 {
2606 if (!loaded_vmcs->vmcs)
2607 return;
2608 loaded_vmcs_clear(loaded_vmcs);
2609 free_vmcs(loaded_vmcs->vmcs);
2610 loaded_vmcs->vmcs = NULL;
2611 }
2612
2613 static void free_kvm_area(void)
2614 {
2615 int cpu;
2616
2617 for_each_possible_cpu(cpu) {
2618 free_vmcs(per_cpu(vmxarea, cpu));
2619 per_cpu(vmxarea, cpu) = NULL;
2620 }
2621 }
2622
2623 static __init int alloc_kvm_area(void)
2624 {
2625 int cpu;
2626
2627 for_each_possible_cpu(cpu) {
2628 struct vmcs *vmcs;
2629
2630 vmcs = alloc_vmcs_cpu(cpu);
2631 if (!vmcs) {
2632 free_kvm_area();
2633 return -ENOMEM;
2634 }
2635
2636 per_cpu(vmxarea, cpu) = vmcs;
2637 }
2638 return 0;
2639 }
2640
2641 static __init int hardware_setup(void)
2642 {
2643 if (setup_vmcs_config(&vmcs_config) < 0)
2644 return -EIO;
2645
2646 if (boot_cpu_has(X86_FEATURE_NX))
2647 kvm_enable_efer_bits(EFER_NX);
2648
2649 if (!cpu_has_vmx_vpid())
2650 enable_vpid = 0;
2651
2652 if (!cpu_has_vmx_ept() ||
2653 !cpu_has_vmx_ept_4levels()) {
2654 enable_ept = 0;
2655 enable_unrestricted_guest = 0;
2656 enable_ept_ad_bits = 0;
2657 }
2658
2659 if (!cpu_has_vmx_ept_ad_bits())
2660 enable_ept_ad_bits = 0;
2661
2662 if (!cpu_has_vmx_unrestricted_guest())
2663 enable_unrestricted_guest = 0;
2664
2665 if (!cpu_has_vmx_flexpriority())
2666 flexpriority_enabled = 0;
2667
2668 if (!cpu_has_vmx_tpr_shadow())
2669 kvm_x86_ops->update_cr8_intercept = NULL;
2670
2671 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2672 kvm_disable_largepages();
2673
2674 if (!cpu_has_vmx_ple())
2675 ple_gap = 0;
2676
2677 if (nested)
2678 nested_vmx_setup_ctls_msrs();
2679
2680 return alloc_kvm_area();
2681 }
2682
2683 static __exit void hardware_unsetup(void)
2684 {
2685 free_kvm_area();
2686 }
2687
2688 static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
2689 {
2690 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2691 struct kvm_segment tmp = *save;
2692
2693 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2694 tmp.base = vmcs_readl(sf->base);
2695 tmp.selector = vmcs_read16(sf->selector);
2696 tmp.s = 1;
2697 }
2698 vmx_set_segment(vcpu, &tmp, seg);
2699 }
2700
2701 static void enter_pmode(struct kvm_vcpu *vcpu)
2702 {
2703 unsigned long flags;
2704 struct vcpu_vmx *vmx = to_vmx(vcpu);
2705
2706 vmx->emulation_required = 1;
2707 vmx->rmode.vm86_active = 0;
2708
2709 vmx_segment_cache_clear(vmx);
2710
2711 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2712
2713 flags = vmcs_readl(GUEST_RFLAGS);
2714 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2715 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2716 vmcs_writel(GUEST_RFLAGS, flags);
2717
2718 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2719 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2720
2721 update_exception_bitmap(vcpu);
2722
2723 if (emulate_invalid_guest_state)
2724 return;
2725
2726 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2727 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2728 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2729 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2730
2731 vmx_segment_cache_clear(vmx);
2732
2733 vmcs_write16(GUEST_SS_SELECTOR, 0);
2734 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2735
2736 vmcs_write16(GUEST_CS_SELECTOR,
2737 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2738 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2739 }
2740
2741 static gva_t rmode_tss_base(struct kvm *kvm)
2742 {
2743 if (!kvm->arch.tss_addr) {
2744 struct kvm_memslots *slots;
2745 struct kvm_memory_slot *slot;
2746 gfn_t base_gfn;
2747
2748 slots = kvm_memslots(kvm);
2749 slot = id_to_memslot(slots, 0);
2750 base_gfn = slot->base_gfn + slot->npages - 3;
2751
2752 return base_gfn << PAGE_SHIFT;
2753 }
2754 return kvm->arch.tss_addr;
2755 }
2756
2757 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2758 {
2759 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2760
2761 vmcs_write16(sf->selector, save->base >> 4);
2762 vmcs_write32(sf->base, save->base & 0xffff0);
2763 vmcs_write32(sf->limit, 0xffff);
2764 vmcs_write32(sf->ar_bytes, 0xf3);
2765 if (save->base & 0xf)
2766 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2767 " aligned when entering protected mode (seg=%d)",
2768 seg);
2769 }
2770
2771 static void enter_rmode(struct kvm_vcpu *vcpu)
2772 {
2773 unsigned long flags;
2774 struct vcpu_vmx *vmx = to_vmx(vcpu);
2775 struct kvm_segment var;
2776
2777 if (enable_unrestricted_guest)
2778 return;
2779
2780 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2781 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2782 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2783 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2784 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2785
2786 vmx->emulation_required = 1;
2787 vmx->rmode.vm86_active = 1;
2788
2789
2790 /*
2791 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2792 * vcpu. Call it here with phys address pointing 16M below 4G.
2793 */
2794 if (!vcpu->kvm->arch.tss_addr) {
2795 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2796 "called before entering vcpu\n");
2797 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2798 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2799 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2800 }
2801
2802 vmx_segment_cache_clear(vmx);
2803
2804 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2805 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2806 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2807
2808 flags = vmcs_readl(GUEST_RFLAGS);
2809 vmx->rmode.save_rflags = flags;
2810
2811 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2812
2813 vmcs_writel(GUEST_RFLAGS, flags);
2814 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2815 update_exception_bitmap(vcpu);
2816
2817 if (emulate_invalid_guest_state)
2818 goto continue_rmode;
2819
2820 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2821 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2822
2823 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2824 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2825
2826 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2827 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2828
2829 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2830 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2831
2832 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2833 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2834
2835 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2836 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2837
2838 continue_rmode:
2839 kvm_mmu_reset_context(vcpu);
2840 }
2841
2842 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2843 {
2844 struct vcpu_vmx *vmx = to_vmx(vcpu);
2845 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2846
2847 if (!msr)
2848 return;
2849
2850 /*
2851 * Force kernel_gs_base reloading before EFER changes, as control
2852 * of this msr depends on is_long_mode().
2853 */
2854 vmx_load_host_state(to_vmx(vcpu));
2855 vcpu->arch.efer = efer;
2856 if (efer & EFER_LMA) {
2857 vmcs_write32(VM_ENTRY_CONTROLS,
2858 vmcs_read32(VM_ENTRY_CONTROLS) |
2859 VM_ENTRY_IA32E_MODE);
2860 msr->data = efer;
2861 } else {
2862 vmcs_write32(VM_ENTRY_CONTROLS,
2863 vmcs_read32(VM_ENTRY_CONTROLS) &
2864 ~VM_ENTRY_IA32E_MODE);
2865
2866 msr->data = efer & ~EFER_LME;
2867 }
2868 setup_msrs(vmx);
2869 }
2870
2871 #ifdef CONFIG_X86_64
2872
2873 static void enter_lmode(struct kvm_vcpu *vcpu)
2874 {
2875 u32 guest_tr_ar;
2876
2877 vmx_segment_cache_clear(to_vmx(vcpu));
2878
2879 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2880 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2881 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2882 __func__);
2883 vmcs_write32(GUEST_TR_AR_BYTES,
2884 (guest_tr_ar & ~AR_TYPE_MASK)
2885 | AR_TYPE_BUSY_64_TSS);
2886 }
2887 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2888 }
2889
2890 static void exit_lmode(struct kvm_vcpu *vcpu)
2891 {
2892 vmcs_write32(VM_ENTRY_CONTROLS,
2893 vmcs_read32(VM_ENTRY_CONTROLS)
2894 & ~VM_ENTRY_IA32E_MODE);
2895 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2896 }
2897
2898 #endif
2899
2900 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2901 {
2902 vpid_sync_context(to_vmx(vcpu));
2903 if (enable_ept) {
2904 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2905 return;
2906 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2907 }
2908 }
2909
2910 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2911 {
2912 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2913
2914 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2915 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2916 }
2917
2918 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2919 {
2920 if (enable_ept && is_paging(vcpu))
2921 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2922 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2923 }
2924
2925 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2926 {
2927 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2928
2929 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2930 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2931 }
2932
2933 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2934 {
2935 if (!test_bit(VCPU_EXREG_PDPTR,
2936 (unsigned long *)&vcpu->arch.regs_dirty))
2937 return;
2938
2939 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2940 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2941 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2942 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2943 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2944 }
2945 }
2946
2947 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2948 {
2949 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2950 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2951 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2952 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2953 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2954 }
2955
2956 __set_bit(VCPU_EXREG_PDPTR,
2957 (unsigned long *)&vcpu->arch.regs_avail);
2958 __set_bit(VCPU_EXREG_PDPTR,
2959 (unsigned long *)&vcpu->arch.regs_dirty);
2960 }
2961
2962 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2963
2964 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2965 unsigned long cr0,
2966 struct kvm_vcpu *vcpu)
2967 {
2968 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2969 vmx_decache_cr3(vcpu);
2970 if (!(cr0 & X86_CR0_PG)) {
2971 /* From paging/starting to nonpaging */
2972 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2973 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2974 (CPU_BASED_CR3_LOAD_EXITING |
2975 CPU_BASED_CR3_STORE_EXITING));
2976 vcpu->arch.cr0 = cr0;
2977 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2978 } else if (!is_paging(vcpu)) {
2979 /* From nonpaging to paging */
2980 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2981 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2982 ~(CPU_BASED_CR3_LOAD_EXITING |
2983 CPU_BASED_CR3_STORE_EXITING));
2984 vcpu->arch.cr0 = cr0;
2985 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2986 }
2987
2988 if (!(cr0 & X86_CR0_WP))
2989 *hw_cr0 &= ~X86_CR0_WP;
2990 }
2991
2992 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2993 {
2994 struct vcpu_vmx *vmx = to_vmx(vcpu);
2995 unsigned long hw_cr0;
2996
2997 if (enable_unrestricted_guest)
2998 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2999 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3000 else
3001 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3002
3003 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3004 enter_pmode(vcpu);
3005
3006 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3007 enter_rmode(vcpu);
3008
3009 #ifdef CONFIG_X86_64
3010 if (vcpu->arch.efer & EFER_LME) {
3011 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3012 enter_lmode(vcpu);
3013 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3014 exit_lmode(vcpu);
3015 }
3016 #endif
3017
3018 if (enable_ept)
3019 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3020
3021 if (!vcpu->fpu_active)
3022 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3023
3024 vmcs_writel(CR0_READ_SHADOW, cr0);
3025 vmcs_writel(GUEST_CR0, hw_cr0);
3026 vcpu->arch.cr0 = cr0;
3027 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3028 }
3029
3030 static u64 construct_eptp(unsigned long root_hpa)
3031 {
3032 u64 eptp;
3033
3034 /* TODO write the value reading from MSR */
3035 eptp = VMX_EPT_DEFAULT_MT |
3036 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3037 if (enable_ept_ad_bits)
3038 eptp |= VMX_EPT_AD_ENABLE_BIT;
3039 eptp |= (root_hpa & PAGE_MASK);
3040
3041 return eptp;
3042 }
3043
3044 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3045 {
3046 unsigned long guest_cr3;
3047 u64 eptp;
3048
3049 guest_cr3 = cr3;
3050 if (enable_ept) {
3051 eptp = construct_eptp(cr3);
3052 vmcs_write64(EPT_POINTER, eptp);
3053 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3054 vcpu->kvm->arch.ept_identity_map_addr;
3055 ept_load_pdptrs(vcpu);
3056 }
3057
3058 vmx_flush_tlb(vcpu);
3059 vmcs_writel(GUEST_CR3, guest_cr3);
3060 }
3061
3062 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3063 {
3064 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3065 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3066
3067 if (cr4 & X86_CR4_VMXE) {
3068 /*
3069 * To use VMXON (and later other VMX instructions), a guest
3070 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3071 * So basically the check on whether to allow nested VMX
3072 * is here.
3073 */
3074 if (!nested_vmx_allowed(vcpu))
3075 return 1;
3076 } else if (to_vmx(vcpu)->nested.vmxon)
3077 return 1;
3078
3079 vcpu->arch.cr4 = cr4;
3080 if (enable_ept) {
3081 if (!is_paging(vcpu)) {
3082 hw_cr4 &= ~X86_CR4_PAE;
3083 hw_cr4 |= X86_CR4_PSE;
3084 } else if (!(cr4 & X86_CR4_PAE)) {
3085 hw_cr4 &= ~X86_CR4_PAE;
3086 }
3087 }
3088
3089 vmcs_writel(CR4_READ_SHADOW, cr4);
3090 vmcs_writel(GUEST_CR4, hw_cr4);
3091 return 0;
3092 }
3093
3094 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3095 struct kvm_segment *var, int seg)
3096 {
3097 struct vcpu_vmx *vmx = to_vmx(vcpu);
3098 u32 ar;
3099
3100 if (vmx->rmode.vm86_active
3101 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3102 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3103 || seg == VCPU_SREG_GS)) {
3104 *var = vmx->rmode.segs[seg];
3105 if (seg == VCPU_SREG_TR
3106 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3107 return;
3108 var->base = vmx_read_guest_seg_base(vmx, seg);
3109 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3110 return;
3111 }
3112 var->base = vmx_read_guest_seg_base(vmx, seg);
3113 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3114 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3115 ar = vmx_read_guest_seg_ar(vmx, seg);
3116 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3117 ar = 0;
3118 var->type = ar & 15;
3119 var->s = (ar >> 4) & 1;
3120 var->dpl = (ar >> 5) & 3;
3121 var->present = (ar >> 7) & 1;
3122 var->avl = (ar >> 12) & 1;
3123 var->l = (ar >> 13) & 1;
3124 var->db = (ar >> 14) & 1;
3125 var->g = (ar >> 15) & 1;
3126 var->unusable = (ar >> 16) & 1;
3127 }
3128
3129 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3130 {
3131 struct kvm_segment s;
3132
3133 if (to_vmx(vcpu)->rmode.vm86_active) {
3134 vmx_get_segment(vcpu, &s, seg);
3135 return s.base;
3136 }
3137 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3138 }
3139
3140 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3141 {
3142 if (!is_protmode(vcpu))
3143 return 0;
3144
3145 if (!is_long_mode(vcpu)
3146 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3147 return 3;
3148
3149 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3150 }
3151
3152 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3153 {
3154 struct vcpu_vmx *vmx = to_vmx(vcpu);
3155
3156 /*
3157 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3158 * fail; use the cache instead.
3159 */
3160 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3161 return vmx->cpl;
3162 }
3163
3164 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3165 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3166 vmx->cpl = __vmx_get_cpl(vcpu);
3167 }
3168
3169 return vmx->cpl;
3170 }
3171
3172
3173 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3174 {
3175 u32 ar;
3176
3177 if (var->unusable || !var->present)
3178 ar = 1 << 16;
3179 else {
3180 ar = var->type & 15;
3181 ar |= (var->s & 1) << 4;
3182 ar |= (var->dpl & 3) << 5;
3183 ar |= (var->present & 1) << 7;
3184 ar |= (var->avl & 1) << 12;
3185 ar |= (var->l & 1) << 13;
3186 ar |= (var->db & 1) << 14;
3187 ar |= (var->g & 1) << 15;
3188 }
3189
3190 return ar;
3191 }
3192
3193 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3194 struct kvm_segment *var, int seg)
3195 {
3196 struct vcpu_vmx *vmx = to_vmx(vcpu);
3197 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3198 u32 ar;
3199
3200 vmx_segment_cache_clear(vmx);
3201
3202 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3203 vmcs_write16(sf->selector, var->selector);
3204 vmx->rmode.segs[VCPU_SREG_TR] = *var;
3205 return;
3206 }
3207 vmcs_writel(sf->base, var->base);
3208 vmcs_write32(sf->limit, var->limit);
3209 vmcs_write16(sf->selector, var->selector);
3210 if (vmx->rmode.vm86_active && var->s) {
3211 vmx->rmode.segs[seg] = *var;
3212 /*
3213 * Hack real-mode segments into vm86 compatibility.
3214 */
3215 if (var->base == 0xffff0000 && var->selector == 0xf000)
3216 vmcs_writel(sf->base, 0xf0000);
3217 ar = 0xf3;
3218 } else
3219 ar = vmx_segment_access_rights(var);
3220
3221 /*
3222 * Fix the "Accessed" bit in AR field of segment registers for older
3223 * qemu binaries.
3224 * IA32 arch specifies that at the time of processor reset the
3225 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3226 * is setting it to 0 in the userland code. This causes invalid guest
3227 * state vmexit when "unrestricted guest" mode is turned on.
3228 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3229 * tree. Newer qemu binaries with that qemu fix would not need this
3230 * kvm hack.
3231 */
3232 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3233 ar |= 0x1; /* Accessed */
3234
3235 vmcs_write32(sf->ar_bytes, ar);
3236 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3237
3238 /*
3239 * Fix segments for real mode guest in hosts that don't have
3240 * "unrestricted_mode" or it was disabled.
3241 * This is done to allow migration of the guests from hosts with
3242 * unrestricted guest like Westmere to older host that don't have
3243 * unrestricted guest like Nehelem.
3244 */
3245 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3246 switch (seg) {
3247 case VCPU_SREG_CS:
3248 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3249 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3250 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3251 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3252 vmcs_write16(GUEST_CS_SELECTOR,
3253 vmcs_readl(GUEST_CS_BASE) >> 4);
3254 break;
3255 case VCPU_SREG_ES:
3256 case VCPU_SREG_DS:
3257 case VCPU_SREG_GS:
3258 case VCPU_SREG_FS:
3259 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3260 break;
3261 case VCPU_SREG_SS:
3262 vmcs_write16(GUEST_SS_SELECTOR,
3263 vmcs_readl(GUEST_SS_BASE) >> 4);
3264 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3265 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3266 break;
3267 }
3268 }
3269 }
3270
3271 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3272 {
3273 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3274
3275 *db = (ar >> 14) & 1;
3276 *l = (ar >> 13) & 1;
3277 }
3278
3279 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3280 {
3281 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3282 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3283 }
3284
3285 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3286 {
3287 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3288 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3289 }
3290
3291 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3292 {
3293 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3294 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3295 }
3296
3297 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3298 {
3299 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3300 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3301 }
3302
3303 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3304 {
3305 struct kvm_segment var;
3306 u32 ar;
3307
3308 vmx_get_segment(vcpu, &var, seg);
3309 ar = vmx_segment_access_rights(&var);
3310
3311 if (var.base != (var.selector << 4))
3312 return false;
3313 if (var.limit < 0xffff)
3314 return false;
3315 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
3316 return false;
3317
3318 return true;
3319 }
3320
3321 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3322 {
3323 struct kvm_segment cs;
3324 unsigned int cs_rpl;
3325
3326 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3327 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3328
3329 if (cs.unusable)
3330 return false;
3331 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3332 return false;
3333 if (!cs.s)
3334 return false;
3335 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3336 if (cs.dpl > cs_rpl)
3337 return false;
3338 } else {
3339 if (cs.dpl != cs_rpl)
3340 return false;
3341 }
3342 if (!cs.present)
3343 return false;
3344
3345 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3346 return true;
3347 }
3348
3349 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3350 {
3351 struct kvm_segment ss;
3352 unsigned int ss_rpl;
3353
3354 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3355 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3356
3357 if (ss.unusable)
3358 return true;
3359 if (ss.type != 3 && ss.type != 7)
3360 return false;
3361 if (!ss.s)
3362 return false;
3363 if (ss.dpl != ss_rpl) /* DPL != RPL */
3364 return false;
3365 if (!ss.present)
3366 return false;
3367
3368 return true;
3369 }
3370
3371 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3372 {
3373 struct kvm_segment var;
3374 unsigned int rpl;
3375
3376 vmx_get_segment(vcpu, &var, seg);
3377 rpl = var.selector & SELECTOR_RPL_MASK;
3378
3379 if (var.unusable)
3380 return true;
3381 if (!var.s)
3382 return false;
3383 if (!var.present)
3384 return false;
3385 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3386 if (var.dpl < rpl) /* DPL < RPL */
3387 return false;
3388 }
3389
3390 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3391 * rights flags
3392 */
3393 return true;
3394 }
3395
3396 static bool tr_valid(struct kvm_vcpu *vcpu)
3397 {
3398 struct kvm_segment tr;
3399
3400 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3401
3402 if (tr.unusable)
3403 return false;
3404 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3405 return false;
3406 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3407 return false;
3408 if (!tr.present)
3409 return false;
3410
3411 return true;
3412 }
3413
3414 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3415 {
3416 struct kvm_segment ldtr;
3417
3418 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3419
3420 if (ldtr.unusable)
3421 return true;
3422 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3423 return false;
3424 if (ldtr.type != 2)
3425 return false;
3426 if (!ldtr.present)
3427 return false;
3428
3429 return true;
3430 }
3431
3432 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3433 {
3434 struct kvm_segment cs, ss;
3435
3436 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3437 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3438
3439 return ((cs.selector & SELECTOR_RPL_MASK) ==
3440 (ss.selector & SELECTOR_RPL_MASK));
3441 }
3442
3443 /*
3444 * Check if guest state is valid. Returns true if valid, false if
3445 * not.
3446 * We assume that registers are always usable
3447 */
3448 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3449 {
3450 /* real mode guest state checks */
3451 if (!is_protmode(vcpu)) {
3452 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3453 return false;
3454 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3455 return false;
3456 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3457 return false;
3458 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3459 return false;
3460 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3461 return false;
3462 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3463 return false;
3464 } else {
3465 /* protected mode guest state checks */
3466 if (!cs_ss_rpl_check(vcpu))
3467 return false;
3468 if (!code_segment_valid(vcpu))
3469 return false;
3470 if (!stack_segment_valid(vcpu))
3471 return false;
3472 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3473 return false;
3474 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3475 return false;
3476 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3477 return false;
3478 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3479 return false;
3480 if (!tr_valid(vcpu))
3481 return false;
3482 if (!ldtr_valid(vcpu))
3483 return false;
3484 }
3485 /* TODO:
3486 * - Add checks on RIP
3487 * - Add checks on RFLAGS
3488 */
3489
3490 return true;
3491 }
3492
3493 static int init_rmode_tss(struct kvm *kvm)
3494 {
3495 gfn_t fn;
3496 u16 data = 0;
3497 int r, idx, ret = 0;
3498
3499 idx = srcu_read_lock(&kvm->srcu);
3500 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3501 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3502 if (r < 0)
3503 goto out;
3504 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3505 r = kvm_write_guest_page(kvm, fn++, &data,
3506 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3507 if (r < 0)
3508 goto out;
3509 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3510 if (r < 0)
3511 goto out;
3512 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3513 if (r < 0)
3514 goto out;
3515 data = ~0;
3516 r = kvm_write_guest_page(kvm, fn, &data,
3517 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3518 sizeof(u8));
3519 if (r < 0)
3520 goto out;
3521
3522 ret = 1;
3523 out:
3524 srcu_read_unlock(&kvm->srcu, idx);
3525 return ret;
3526 }
3527
3528 static int init_rmode_identity_map(struct kvm *kvm)
3529 {
3530 int i, idx, r, ret;
3531 pfn_t identity_map_pfn;
3532 u32 tmp;
3533
3534 if (!enable_ept)
3535 return 1;
3536 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3537 printk(KERN_ERR "EPT: identity-mapping pagetable "
3538 "haven't been allocated!\n");
3539 return 0;
3540 }
3541 if (likely(kvm->arch.ept_identity_pagetable_done))
3542 return 1;
3543 ret = 0;
3544 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3545 idx = srcu_read_lock(&kvm->srcu);
3546 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3547 if (r < 0)
3548 goto out;
3549 /* Set up identity-mapping pagetable for EPT in real mode */
3550 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3551 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3552 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3553 r = kvm_write_guest_page(kvm, identity_map_pfn,
3554 &tmp, i * sizeof(tmp), sizeof(tmp));
3555 if (r < 0)
3556 goto out;
3557 }
3558 kvm->arch.ept_identity_pagetable_done = true;
3559 ret = 1;
3560 out:
3561 srcu_read_unlock(&kvm->srcu, idx);
3562 return ret;
3563 }
3564
3565 static void seg_setup(int seg)
3566 {
3567 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3568 unsigned int ar;
3569
3570 vmcs_write16(sf->selector, 0);
3571 vmcs_writel(sf->base, 0);
3572 vmcs_write32(sf->limit, 0xffff);
3573 if (enable_unrestricted_guest) {
3574 ar = 0x93;
3575 if (seg == VCPU_SREG_CS)
3576 ar |= 0x08; /* code segment */
3577 } else
3578 ar = 0xf3;
3579
3580 vmcs_write32(sf->ar_bytes, ar);
3581 }
3582
3583 static int alloc_apic_access_page(struct kvm *kvm)
3584 {
3585 struct kvm_userspace_memory_region kvm_userspace_mem;
3586 int r = 0;
3587
3588 mutex_lock(&kvm->slots_lock);
3589 if (kvm->arch.apic_access_page)
3590 goto out;
3591 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3592 kvm_userspace_mem.flags = 0;
3593 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3594 kvm_userspace_mem.memory_size = PAGE_SIZE;
3595 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3596 if (r)
3597 goto out;
3598
3599 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3600 out:
3601 mutex_unlock(&kvm->slots_lock);
3602 return r;
3603 }
3604
3605 static int alloc_identity_pagetable(struct kvm *kvm)
3606 {
3607 struct kvm_userspace_memory_region kvm_userspace_mem;
3608 int r = 0;
3609
3610 mutex_lock(&kvm->slots_lock);
3611 if (kvm->arch.ept_identity_pagetable)
3612 goto out;
3613 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3614 kvm_userspace_mem.flags = 0;
3615 kvm_userspace_mem.guest_phys_addr =
3616 kvm->arch.ept_identity_map_addr;
3617 kvm_userspace_mem.memory_size = PAGE_SIZE;
3618 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3619 if (r)
3620 goto out;
3621
3622 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3623 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3624 out:
3625 mutex_unlock(&kvm->slots_lock);
3626 return r;
3627 }
3628
3629 static void allocate_vpid(struct vcpu_vmx *vmx)
3630 {
3631 int vpid;
3632
3633 vmx->vpid = 0;
3634 if (!enable_vpid)
3635 return;
3636 spin_lock(&vmx_vpid_lock);
3637 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3638 if (vpid < VMX_NR_VPIDS) {
3639 vmx->vpid = vpid;
3640 __set_bit(vpid, vmx_vpid_bitmap);
3641 }
3642 spin_unlock(&vmx_vpid_lock);
3643 }
3644
3645 static void free_vpid(struct vcpu_vmx *vmx)
3646 {
3647 if (!enable_vpid)
3648 return;
3649 spin_lock(&vmx_vpid_lock);
3650 if (vmx->vpid != 0)
3651 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3652 spin_unlock(&vmx_vpid_lock);
3653 }
3654
3655 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3656 {
3657 int f = sizeof(unsigned long);
3658
3659 if (!cpu_has_vmx_msr_bitmap())
3660 return;
3661
3662 /*
3663 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3664 * have the write-low and read-high bitmap offsets the wrong way round.
3665 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3666 */
3667 if (msr <= 0x1fff) {
3668 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3669 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3670 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3671 msr &= 0x1fff;
3672 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3673 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3674 }
3675 }
3676
3677 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3678 {
3679 if (!longmode_only)
3680 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3681 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3682 }
3683
3684 /*
3685 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3686 * will not change in the lifetime of the guest.
3687 * Note that host-state that does change is set elsewhere. E.g., host-state
3688 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3689 */
3690 static void vmx_set_constant_host_state(void)
3691 {
3692 u32 low32, high32;
3693 unsigned long tmpl;
3694 struct desc_ptr dt;
3695
3696 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3697 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3698 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3699
3700 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3701 #ifdef CONFIG_X86_64
3702 /*
3703 * Load null selectors, so we can avoid reloading them in
3704 * __vmx_load_host_state(), in case userspace uses the null selectors
3705 * too (the expected case).
3706 */
3707 vmcs_write16(HOST_DS_SELECTOR, 0);
3708 vmcs_write16(HOST_ES_SELECTOR, 0);
3709 #else
3710 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3711 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3712 #endif
3713 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3714 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3715
3716 native_store_idt(&dt);
3717 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3718
3719 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3720
3721 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3722 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3723 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3724 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3725
3726 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3727 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3728 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3729 }
3730 }
3731
3732 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3733 {
3734 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3735 if (enable_ept)
3736 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3737 if (is_guest_mode(&vmx->vcpu))
3738 vmx->vcpu.arch.cr4_guest_owned_bits &=
3739 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3740 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3741 }
3742
3743 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3744 {
3745 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3746 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3747 exec_control &= ~CPU_BASED_TPR_SHADOW;
3748 #ifdef CONFIG_X86_64
3749 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3750 CPU_BASED_CR8_LOAD_EXITING;
3751 #endif
3752 }
3753 if (!enable_ept)
3754 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3755 CPU_BASED_CR3_LOAD_EXITING |
3756 CPU_BASED_INVLPG_EXITING;
3757 return exec_control;
3758 }
3759
3760 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3761 {
3762 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3763 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3764 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3765 if (vmx->vpid == 0)
3766 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3767 if (!enable_ept) {
3768 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3769 enable_unrestricted_guest = 0;
3770 /* Enable INVPCID for non-ept guests may cause performance regression. */
3771 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3772 }
3773 if (!enable_unrestricted_guest)
3774 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3775 if (!ple_gap)
3776 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3777 return exec_control;
3778 }
3779
3780 static void ept_set_mmio_spte_mask(void)
3781 {
3782 /*
3783 * EPT Misconfigurations can be generated if the value of bits 2:0
3784 * of an EPT paging-structure entry is 110b (write/execute).
3785 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3786 * spte.
3787 */
3788 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3789 }
3790
3791 /*
3792 * Sets up the vmcs for emulated real mode.
3793 */
3794 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3795 {
3796 #ifdef CONFIG_X86_64
3797 unsigned long a;
3798 #endif
3799 int i;
3800
3801 /* I/O */
3802 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3803 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3804
3805 if (cpu_has_vmx_msr_bitmap())
3806 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3807
3808 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3809
3810 /* Control */
3811 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3812 vmcs_config.pin_based_exec_ctrl);
3813
3814 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3815
3816 if (cpu_has_secondary_exec_ctrls()) {
3817 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3818 vmx_secondary_exec_control(vmx));
3819 }
3820
3821 if (ple_gap) {
3822 vmcs_write32(PLE_GAP, ple_gap);
3823 vmcs_write32(PLE_WINDOW, ple_window);
3824 }
3825
3826 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3827 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3828 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3829
3830 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3831 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3832 vmx_set_constant_host_state();
3833 #ifdef CONFIG_X86_64
3834 rdmsrl(MSR_FS_BASE, a);
3835 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3836 rdmsrl(MSR_GS_BASE, a);
3837 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3838 #else
3839 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3840 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3841 #endif
3842
3843 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3844 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3845 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3846 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3847 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3848
3849 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3850 u32 msr_low, msr_high;
3851 u64 host_pat;
3852 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3853 host_pat = msr_low | ((u64) msr_high << 32);
3854 /* Write the default value follow host pat */
3855 vmcs_write64(GUEST_IA32_PAT, host_pat);
3856 /* Keep arch.pat sync with GUEST_IA32_PAT */
3857 vmx->vcpu.arch.pat = host_pat;
3858 }
3859
3860 for (i = 0; i < NR_VMX_MSR; ++i) {
3861 u32 index = vmx_msr_index[i];
3862 u32 data_low, data_high;
3863 int j = vmx->nmsrs;
3864
3865 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3866 continue;
3867 if (wrmsr_safe(index, data_low, data_high) < 0)
3868 continue;
3869 vmx->guest_msrs[j].index = i;
3870 vmx->guest_msrs[j].data = 0;
3871 vmx->guest_msrs[j].mask = -1ull;
3872 ++vmx->nmsrs;
3873 }
3874
3875 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3876
3877 /* 22.2.1, 20.8.1 */
3878 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3879
3880 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3881 set_cr4_guest_host_mask(vmx);
3882
3883 kvm_write_tsc(&vmx->vcpu, 0);
3884
3885 return 0;
3886 }
3887
3888 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3889 {
3890 struct vcpu_vmx *vmx = to_vmx(vcpu);
3891 u64 msr;
3892 int ret;
3893
3894 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3895
3896 vmx->rmode.vm86_active = 0;
3897
3898 vmx->soft_vnmi_blocked = 0;
3899
3900 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3901 kvm_set_cr8(&vmx->vcpu, 0);
3902 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3903 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3904 msr |= MSR_IA32_APICBASE_BSP;
3905 kvm_set_apic_base(&vmx->vcpu, msr);
3906
3907 ret = fx_init(&vmx->vcpu);
3908 if (ret != 0)
3909 goto out;
3910
3911 vmx_segment_cache_clear(vmx);
3912
3913 seg_setup(VCPU_SREG_CS);
3914 /*
3915 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3916 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3917 */
3918 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3919 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3920 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3921 } else {
3922 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3923 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3924 }
3925
3926 seg_setup(VCPU_SREG_DS);
3927 seg_setup(VCPU_SREG_ES);
3928 seg_setup(VCPU_SREG_FS);
3929 seg_setup(VCPU_SREG_GS);
3930 seg_setup(VCPU_SREG_SS);
3931
3932 vmcs_write16(GUEST_TR_SELECTOR, 0);
3933 vmcs_writel(GUEST_TR_BASE, 0);
3934 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3935 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3936
3937 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3938 vmcs_writel(GUEST_LDTR_BASE, 0);
3939 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3940 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3941
3942 vmcs_write32(GUEST_SYSENTER_CS, 0);
3943 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3944 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3945
3946 vmcs_writel(GUEST_RFLAGS, 0x02);
3947 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3948 kvm_rip_write(vcpu, 0xfff0);
3949 else
3950 kvm_rip_write(vcpu, 0);
3951 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3952
3953 vmcs_writel(GUEST_GDTR_BASE, 0);
3954 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3955
3956 vmcs_writel(GUEST_IDTR_BASE, 0);
3957 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3958
3959 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3960 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3961 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3962
3963 /* Special registers */
3964 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3965
3966 setup_msrs(vmx);
3967
3968 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3969
3970 if (cpu_has_vmx_tpr_shadow()) {
3971 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3972 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3973 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3974 __pa(vmx->vcpu.arch.apic->regs));
3975 vmcs_write32(TPR_THRESHOLD, 0);
3976 }
3977
3978 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3979 vmcs_write64(APIC_ACCESS_ADDR,
3980 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3981
3982 if (vmx->vpid != 0)
3983 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3984
3985 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3986 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3987 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3988 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3989 vmx_set_cr4(&vmx->vcpu, 0);
3990 vmx_set_efer(&vmx->vcpu, 0);
3991 vmx_fpu_activate(&vmx->vcpu);
3992 update_exception_bitmap(&vmx->vcpu);
3993
3994 vpid_sync_context(vmx);
3995
3996 ret = 0;
3997
3998 /* HACK: Don't enable emulation on guest boot/reset */
3999 vmx->emulation_required = 0;
4000
4001 out:
4002 return ret;
4003 }
4004
4005 /*
4006 * In nested virtualization, check if L1 asked to exit on external interrupts.
4007 * For most existing hypervisors, this will always return true.
4008 */
4009 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4010 {
4011 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4012 PIN_BASED_EXT_INTR_MASK;
4013 }
4014
4015 static void enable_irq_window(struct kvm_vcpu *vcpu)
4016 {
4017 u32 cpu_based_vm_exec_control;
4018 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4019 /*
4020 * We get here if vmx_interrupt_allowed() said we can't
4021 * inject to L1 now because L2 must run. Ask L2 to exit
4022 * right after entry, so we can inject to L1 more promptly.
4023 */
4024 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4025 return;
4026 }
4027
4028 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4029 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4030 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4031 }
4032
4033 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4034 {
4035 u32 cpu_based_vm_exec_control;
4036
4037 if (!cpu_has_virtual_nmis()) {
4038 enable_irq_window(vcpu);
4039 return;
4040 }
4041
4042 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4043 enable_irq_window(vcpu);
4044 return;
4045 }
4046 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4047 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4048 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4049 }
4050
4051 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4052 {
4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4054 uint32_t intr;
4055 int irq = vcpu->arch.interrupt.nr;
4056
4057 trace_kvm_inj_virq(irq);
4058
4059 ++vcpu->stat.irq_injections;
4060 if (vmx->rmode.vm86_active) {
4061 int inc_eip = 0;
4062 if (vcpu->arch.interrupt.soft)
4063 inc_eip = vcpu->arch.event_exit_inst_len;
4064 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4065 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4066 return;
4067 }
4068 intr = irq | INTR_INFO_VALID_MASK;
4069 if (vcpu->arch.interrupt.soft) {
4070 intr |= INTR_TYPE_SOFT_INTR;
4071 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4072 vmx->vcpu.arch.event_exit_inst_len);
4073 } else
4074 intr |= INTR_TYPE_EXT_INTR;
4075 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4076 }
4077
4078 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4079 {
4080 struct vcpu_vmx *vmx = to_vmx(vcpu);
4081
4082 if (is_guest_mode(vcpu))
4083 return;
4084
4085 if (!cpu_has_virtual_nmis()) {
4086 /*
4087 * Tracking the NMI-blocked state in software is built upon
4088 * finding the next open IRQ window. This, in turn, depends on
4089 * well-behaving guests: They have to keep IRQs disabled at
4090 * least as long as the NMI handler runs. Otherwise we may
4091 * cause NMI nesting, maybe breaking the guest. But as this is
4092 * highly unlikely, we can live with the residual risk.
4093 */
4094 vmx->soft_vnmi_blocked = 1;
4095 vmx->vnmi_blocked_time = 0;
4096 }
4097
4098 ++vcpu->stat.nmi_injections;
4099 vmx->nmi_known_unmasked = false;
4100 if (vmx->rmode.vm86_active) {
4101 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4102 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4103 return;
4104 }
4105 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4106 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4107 }
4108
4109 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4110 {
4111 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4112 return 0;
4113
4114 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4115 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4116 | GUEST_INTR_STATE_NMI));
4117 }
4118
4119 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4120 {
4121 if (!cpu_has_virtual_nmis())
4122 return to_vmx(vcpu)->soft_vnmi_blocked;
4123 if (to_vmx(vcpu)->nmi_known_unmasked)
4124 return false;
4125 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4126 }
4127
4128 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4129 {
4130 struct vcpu_vmx *vmx = to_vmx(vcpu);
4131
4132 if (!cpu_has_virtual_nmis()) {
4133 if (vmx->soft_vnmi_blocked != masked) {
4134 vmx->soft_vnmi_blocked = masked;
4135 vmx->vnmi_blocked_time = 0;
4136 }
4137 } else {
4138 vmx->nmi_known_unmasked = !masked;
4139 if (masked)
4140 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4141 GUEST_INTR_STATE_NMI);
4142 else
4143 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4144 GUEST_INTR_STATE_NMI);
4145 }
4146 }
4147
4148 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4149 {
4150 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4151 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4152 if (to_vmx(vcpu)->nested.nested_run_pending ||
4153 (vmcs12->idt_vectoring_info_field &
4154 VECTORING_INFO_VALID_MASK))
4155 return 0;
4156 nested_vmx_vmexit(vcpu);
4157 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4158 vmcs12->vm_exit_intr_info = 0;
4159 /* fall through to normal code, but now in L1, not L2 */
4160 }
4161
4162 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4163 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4164 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4165 }
4166
4167 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4168 {
4169 int ret;
4170 struct kvm_userspace_memory_region tss_mem = {
4171 .slot = TSS_PRIVATE_MEMSLOT,
4172 .guest_phys_addr = addr,
4173 .memory_size = PAGE_SIZE * 3,
4174 .flags = 0,
4175 };
4176
4177 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4178 if (ret)
4179 return ret;
4180 kvm->arch.tss_addr = addr;
4181 if (!init_rmode_tss(kvm))
4182 return -ENOMEM;
4183
4184 return 0;
4185 }
4186
4187 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4188 int vec, u32 err_code)
4189 {
4190 /*
4191 * Instruction with address size override prefix opcode 0x67
4192 * Cause the #SS fault with 0 error code in VM86 mode.
4193 */
4194 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4195 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4196 return 1;
4197 /*
4198 * Forward all other exceptions that are valid in real mode.
4199 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4200 * the required debugging infrastructure rework.
4201 */
4202 switch (vec) {
4203 case DB_VECTOR:
4204 if (vcpu->guest_debug &
4205 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4206 return 0;
4207 kvm_queue_exception(vcpu, vec);
4208 return 1;
4209 case BP_VECTOR:
4210 /*
4211 * Update instruction length as we may reinject the exception
4212 * from user space while in guest debugging mode.
4213 */
4214 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4215 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4216 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4217 return 0;
4218 /* fall through */
4219 case DE_VECTOR:
4220 case OF_VECTOR:
4221 case BR_VECTOR:
4222 case UD_VECTOR:
4223 case DF_VECTOR:
4224 case SS_VECTOR:
4225 case GP_VECTOR:
4226 case MF_VECTOR:
4227 kvm_queue_exception(vcpu, vec);
4228 return 1;
4229 }
4230 return 0;
4231 }
4232
4233 /*
4234 * Trigger machine check on the host. We assume all the MSRs are already set up
4235 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4236 * We pass a fake environment to the machine check handler because we want
4237 * the guest to be always treated like user space, no matter what context
4238 * it used internally.
4239 */
4240 static void kvm_machine_check(void)
4241 {
4242 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4243 struct pt_regs regs = {
4244 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4245 .flags = X86_EFLAGS_IF,
4246 };
4247
4248 do_machine_check(&regs, 0);
4249 #endif
4250 }
4251
4252 static int handle_machine_check(struct kvm_vcpu *vcpu)
4253 {
4254 /* already handled by vcpu_run */
4255 return 1;
4256 }
4257
4258 static int handle_exception(struct kvm_vcpu *vcpu)
4259 {
4260 struct vcpu_vmx *vmx = to_vmx(vcpu);
4261 struct kvm_run *kvm_run = vcpu->run;
4262 u32 intr_info, ex_no, error_code;
4263 unsigned long cr2, rip, dr6;
4264 u32 vect_info;
4265 enum emulation_result er;
4266
4267 vect_info = vmx->idt_vectoring_info;
4268 intr_info = vmx->exit_intr_info;
4269
4270 if (is_machine_check(intr_info))
4271 return handle_machine_check(vcpu);
4272
4273 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4274 !is_page_fault(intr_info)) {
4275 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4276 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4277 vcpu->run->internal.ndata = 2;
4278 vcpu->run->internal.data[0] = vect_info;
4279 vcpu->run->internal.data[1] = intr_info;
4280 return 0;
4281 }
4282
4283 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4284 return 1; /* already handled by vmx_vcpu_run() */
4285
4286 if (is_no_device(intr_info)) {
4287 vmx_fpu_activate(vcpu);
4288 return 1;
4289 }
4290
4291 if (is_invalid_opcode(intr_info)) {
4292 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4293 if (er != EMULATE_DONE)
4294 kvm_queue_exception(vcpu, UD_VECTOR);
4295 return 1;
4296 }
4297
4298 error_code = 0;
4299 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4300 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4301 if (is_page_fault(intr_info)) {
4302 /* EPT won't cause page fault directly */
4303 BUG_ON(enable_ept);
4304 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4305 trace_kvm_page_fault(cr2, error_code);
4306
4307 if (kvm_event_needs_reinjection(vcpu))
4308 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4309 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4310 }
4311
4312 if (vmx->rmode.vm86_active &&
4313 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4314 error_code)) {
4315 if (vcpu->arch.halt_request) {
4316 vcpu->arch.halt_request = 0;
4317 return kvm_emulate_halt(vcpu);
4318 }
4319 return 1;
4320 }
4321
4322 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4323 switch (ex_no) {
4324 case DB_VECTOR:
4325 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4326 if (!(vcpu->guest_debug &
4327 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4328 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4329 kvm_queue_exception(vcpu, DB_VECTOR);
4330 return 1;
4331 }
4332 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4333 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4334 /* fall through */
4335 case BP_VECTOR:
4336 /*
4337 * Update instruction length as we may reinject #BP from
4338 * user space while in guest debugging mode. Reading it for
4339 * #DB as well causes no harm, it is not used in that case.
4340 */
4341 vmx->vcpu.arch.event_exit_inst_len =
4342 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4343 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4344 rip = kvm_rip_read(vcpu);
4345 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4346 kvm_run->debug.arch.exception = ex_no;
4347 break;
4348 default:
4349 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4350 kvm_run->ex.exception = ex_no;
4351 kvm_run->ex.error_code = error_code;
4352 break;
4353 }
4354 return 0;
4355 }
4356
4357 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4358 {
4359 ++vcpu->stat.irq_exits;
4360 return 1;
4361 }
4362
4363 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4364 {
4365 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4366 return 0;
4367 }
4368
4369 static int handle_io(struct kvm_vcpu *vcpu)
4370 {
4371 unsigned long exit_qualification;
4372 int size, in, string;
4373 unsigned port;
4374
4375 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4376 string = (exit_qualification & 16) != 0;
4377 in = (exit_qualification & 8) != 0;
4378
4379 ++vcpu->stat.io_exits;
4380
4381 if (string || in)
4382 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4383
4384 port = exit_qualification >> 16;
4385 size = (exit_qualification & 7) + 1;
4386 skip_emulated_instruction(vcpu);
4387
4388 return kvm_fast_pio_out(vcpu, size, port);
4389 }
4390
4391 static void
4392 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4393 {
4394 /*
4395 * Patch in the VMCALL instruction:
4396 */
4397 hypercall[0] = 0x0f;
4398 hypercall[1] = 0x01;
4399 hypercall[2] = 0xc1;
4400 }
4401
4402 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4403 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4404 {
4405 if (to_vmx(vcpu)->nested.vmxon &&
4406 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4407 return 1;
4408
4409 if (is_guest_mode(vcpu)) {
4410 /*
4411 * We get here when L2 changed cr0 in a way that did not change
4412 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4413 * but did change L0 shadowed bits. This can currently happen
4414 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4415 * loading) while pretending to allow the guest to change it.
4416 */
4417 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4418 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4419 return 1;
4420 vmcs_writel(CR0_READ_SHADOW, val);
4421 return 0;
4422 } else
4423 return kvm_set_cr0(vcpu, val);
4424 }
4425
4426 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4427 {
4428 if (is_guest_mode(vcpu)) {
4429 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4430 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4431 return 1;
4432 vmcs_writel(CR4_READ_SHADOW, val);
4433 return 0;
4434 } else
4435 return kvm_set_cr4(vcpu, val);
4436 }
4437
4438 /* called to set cr0 as approriate for clts instruction exit. */
4439 static void handle_clts(struct kvm_vcpu *vcpu)
4440 {
4441 if (is_guest_mode(vcpu)) {
4442 /*
4443 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4444 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4445 * just pretend it's off (also in arch.cr0 for fpu_activate).
4446 */
4447 vmcs_writel(CR0_READ_SHADOW,
4448 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4449 vcpu->arch.cr0 &= ~X86_CR0_TS;
4450 } else
4451 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4452 }
4453
4454 static int handle_cr(struct kvm_vcpu *vcpu)
4455 {
4456 unsigned long exit_qualification, val;
4457 int cr;
4458 int reg;
4459 int err;
4460
4461 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4462 cr = exit_qualification & 15;
4463 reg = (exit_qualification >> 8) & 15;
4464 switch ((exit_qualification >> 4) & 3) {
4465 case 0: /* mov to cr */
4466 val = kvm_register_read(vcpu, reg);
4467 trace_kvm_cr_write(cr, val);
4468 switch (cr) {
4469 case 0:
4470 err = handle_set_cr0(vcpu, val);
4471 kvm_complete_insn_gp(vcpu, err);
4472 return 1;
4473 case 3:
4474 err = kvm_set_cr3(vcpu, val);
4475 kvm_complete_insn_gp(vcpu, err);
4476 return 1;
4477 case 4:
4478 err = handle_set_cr4(vcpu, val);
4479 kvm_complete_insn_gp(vcpu, err);
4480 return 1;
4481 case 8: {
4482 u8 cr8_prev = kvm_get_cr8(vcpu);
4483 u8 cr8 = kvm_register_read(vcpu, reg);
4484 err = kvm_set_cr8(vcpu, cr8);
4485 kvm_complete_insn_gp(vcpu, err);
4486 if (irqchip_in_kernel(vcpu->kvm))
4487 return 1;
4488 if (cr8_prev <= cr8)
4489 return 1;
4490 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4491 return 0;
4492 }
4493 };
4494 break;
4495 case 2: /* clts */
4496 handle_clts(vcpu);
4497 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4498 skip_emulated_instruction(vcpu);
4499 vmx_fpu_activate(vcpu);
4500 return 1;
4501 case 1: /*mov from cr*/
4502 switch (cr) {
4503 case 3:
4504 val = kvm_read_cr3(vcpu);
4505 kvm_register_write(vcpu, reg, val);
4506 trace_kvm_cr_read(cr, val);
4507 skip_emulated_instruction(vcpu);
4508 return 1;
4509 case 8:
4510 val = kvm_get_cr8(vcpu);
4511 kvm_register_write(vcpu, reg, val);
4512 trace_kvm_cr_read(cr, val);
4513 skip_emulated_instruction(vcpu);
4514 return 1;
4515 }
4516 break;
4517 case 3: /* lmsw */
4518 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4519 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4520 kvm_lmsw(vcpu, val);
4521
4522 skip_emulated_instruction(vcpu);
4523 return 1;
4524 default:
4525 break;
4526 }
4527 vcpu->run->exit_reason = 0;
4528 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4529 (int)(exit_qualification >> 4) & 3, cr);
4530 return 0;
4531 }
4532
4533 static int handle_dr(struct kvm_vcpu *vcpu)
4534 {
4535 unsigned long exit_qualification;
4536 int dr, reg;
4537
4538 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4539 if (!kvm_require_cpl(vcpu, 0))
4540 return 1;
4541 dr = vmcs_readl(GUEST_DR7);
4542 if (dr & DR7_GD) {
4543 /*
4544 * As the vm-exit takes precedence over the debug trap, we
4545 * need to emulate the latter, either for the host or the
4546 * guest debugging itself.
4547 */
4548 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4549 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4550 vcpu->run->debug.arch.dr7 = dr;
4551 vcpu->run->debug.arch.pc =
4552 vmcs_readl(GUEST_CS_BASE) +
4553 vmcs_readl(GUEST_RIP);
4554 vcpu->run->debug.arch.exception = DB_VECTOR;
4555 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4556 return 0;
4557 } else {
4558 vcpu->arch.dr7 &= ~DR7_GD;
4559 vcpu->arch.dr6 |= DR6_BD;
4560 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4561 kvm_queue_exception(vcpu, DB_VECTOR);
4562 return 1;
4563 }
4564 }
4565
4566 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4567 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4568 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4569 if (exit_qualification & TYPE_MOV_FROM_DR) {
4570 unsigned long val;
4571 if (!kvm_get_dr(vcpu, dr, &val))
4572 kvm_register_write(vcpu, reg, val);
4573 } else
4574 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4575 skip_emulated_instruction(vcpu);
4576 return 1;
4577 }
4578
4579 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4580 {
4581 vmcs_writel(GUEST_DR7, val);
4582 }
4583
4584 static int handle_cpuid(struct kvm_vcpu *vcpu)
4585 {
4586 kvm_emulate_cpuid(vcpu);
4587 return 1;
4588 }
4589
4590 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4591 {
4592 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4593 u64 data;
4594
4595 if (vmx_get_msr(vcpu, ecx, &data)) {
4596 trace_kvm_msr_read_ex(ecx);
4597 kvm_inject_gp(vcpu, 0);
4598 return 1;
4599 }
4600
4601 trace_kvm_msr_read(ecx, data);
4602
4603 /* FIXME: handling of bits 32:63 of rax, rdx */
4604 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4605 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4606 skip_emulated_instruction(vcpu);
4607 return 1;
4608 }
4609
4610 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4611 {
4612 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4613 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4614 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4615
4616 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4617 trace_kvm_msr_write_ex(ecx, data);
4618 kvm_inject_gp(vcpu, 0);
4619 return 1;
4620 }
4621
4622 trace_kvm_msr_write(ecx, data);
4623 skip_emulated_instruction(vcpu);
4624 return 1;
4625 }
4626
4627 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4628 {
4629 kvm_make_request(KVM_REQ_EVENT, vcpu);
4630 return 1;
4631 }
4632
4633 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4634 {
4635 u32 cpu_based_vm_exec_control;
4636
4637 /* clear pending irq */
4638 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4639 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4640 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4641
4642 kvm_make_request(KVM_REQ_EVENT, vcpu);
4643
4644 ++vcpu->stat.irq_window_exits;
4645
4646 /*
4647 * If the user space waits to inject interrupts, exit as soon as
4648 * possible
4649 */
4650 if (!irqchip_in_kernel(vcpu->kvm) &&
4651 vcpu->run->request_interrupt_window &&
4652 !kvm_cpu_has_interrupt(vcpu)) {
4653 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4654 return 0;
4655 }
4656 return 1;
4657 }
4658
4659 static int handle_halt(struct kvm_vcpu *vcpu)
4660 {
4661 skip_emulated_instruction(vcpu);
4662 return kvm_emulate_halt(vcpu);
4663 }
4664
4665 static int handle_vmcall(struct kvm_vcpu *vcpu)
4666 {
4667 skip_emulated_instruction(vcpu);
4668 kvm_emulate_hypercall(vcpu);
4669 return 1;
4670 }
4671
4672 static int handle_invd(struct kvm_vcpu *vcpu)
4673 {
4674 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4675 }
4676
4677 static int handle_invlpg(struct kvm_vcpu *vcpu)
4678 {
4679 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4680
4681 kvm_mmu_invlpg(vcpu, exit_qualification);
4682 skip_emulated_instruction(vcpu);
4683 return 1;
4684 }
4685
4686 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4687 {
4688 int err;
4689
4690 err = kvm_rdpmc(vcpu);
4691 kvm_complete_insn_gp(vcpu, err);
4692
4693 return 1;
4694 }
4695
4696 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4697 {
4698 skip_emulated_instruction(vcpu);
4699 kvm_emulate_wbinvd(vcpu);
4700 return 1;
4701 }
4702
4703 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4704 {
4705 u64 new_bv = kvm_read_edx_eax(vcpu);
4706 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4707
4708 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4709 skip_emulated_instruction(vcpu);
4710 return 1;
4711 }
4712
4713 static int handle_apic_access(struct kvm_vcpu *vcpu)
4714 {
4715 if (likely(fasteoi)) {
4716 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4717 int access_type, offset;
4718
4719 access_type = exit_qualification & APIC_ACCESS_TYPE;
4720 offset = exit_qualification & APIC_ACCESS_OFFSET;
4721 /*
4722 * Sane guest uses MOV to write EOI, with written value
4723 * not cared. So make a short-circuit here by avoiding
4724 * heavy instruction emulation.
4725 */
4726 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4727 (offset == APIC_EOI)) {
4728 kvm_lapic_set_eoi(vcpu);
4729 skip_emulated_instruction(vcpu);
4730 return 1;
4731 }
4732 }
4733 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4734 }
4735
4736 static int handle_task_switch(struct kvm_vcpu *vcpu)
4737 {
4738 struct vcpu_vmx *vmx = to_vmx(vcpu);
4739 unsigned long exit_qualification;
4740 bool has_error_code = false;
4741 u32 error_code = 0;
4742 u16 tss_selector;
4743 int reason, type, idt_v, idt_index;
4744
4745 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4746 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4747 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4748
4749 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4750
4751 reason = (u32)exit_qualification >> 30;
4752 if (reason == TASK_SWITCH_GATE && idt_v) {
4753 switch (type) {
4754 case INTR_TYPE_NMI_INTR:
4755 vcpu->arch.nmi_injected = false;
4756 vmx_set_nmi_mask(vcpu, true);
4757 break;
4758 case INTR_TYPE_EXT_INTR:
4759 case INTR_TYPE_SOFT_INTR:
4760 kvm_clear_interrupt_queue(vcpu);
4761 break;
4762 case INTR_TYPE_HARD_EXCEPTION:
4763 if (vmx->idt_vectoring_info &
4764 VECTORING_INFO_DELIVER_CODE_MASK) {
4765 has_error_code = true;
4766 error_code =
4767 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4768 }
4769 /* fall through */
4770 case INTR_TYPE_SOFT_EXCEPTION:
4771 kvm_clear_exception_queue(vcpu);
4772 break;
4773 default:
4774 break;
4775 }
4776 }
4777 tss_selector = exit_qualification;
4778
4779 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4780 type != INTR_TYPE_EXT_INTR &&
4781 type != INTR_TYPE_NMI_INTR))
4782 skip_emulated_instruction(vcpu);
4783
4784 if (kvm_task_switch(vcpu, tss_selector,
4785 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4786 has_error_code, error_code) == EMULATE_FAIL) {
4787 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4788 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4789 vcpu->run->internal.ndata = 0;
4790 return 0;
4791 }
4792
4793 /* clear all local breakpoint enable flags */
4794 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4795
4796 /*
4797 * TODO: What about debug traps on tss switch?
4798 * Are we supposed to inject them and update dr6?
4799 */
4800
4801 return 1;
4802 }
4803
4804 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4805 {
4806 unsigned long exit_qualification;
4807 gpa_t gpa;
4808 u32 error_code;
4809 int gla_validity;
4810
4811 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4812
4813 if (exit_qualification & (1 << 6)) {
4814 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4815 return -EINVAL;
4816 }
4817
4818 gla_validity = (exit_qualification >> 7) & 0x3;
4819 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4820 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4821 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4822 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4823 vmcs_readl(GUEST_LINEAR_ADDRESS));
4824 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4825 (long unsigned int)exit_qualification);
4826 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4827 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4828 return 0;
4829 }
4830
4831 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4832 trace_kvm_page_fault(gpa, exit_qualification);
4833
4834 /* It is a write fault? */
4835 error_code = exit_qualification & (1U << 1);
4836 /* ept page table is present? */
4837 error_code |= (exit_qualification >> 3) & 0x1;
4838
4839 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4840 }
4841
4842 static u64 ept_rsvd_mask(u64 spte, int level)
4843 {
4844 int i;
4845 u64 mask = 0;
4846
4847 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4848 mask |= (1ULL << i);
4849
4850 if (level > 2)
4851 /* bits 7:3 reserved */
4852 mask |= 0xf8;
4853 else if (level == 2) {
4854 if (spte & (1ULL << 7))
4855 /* 2MB ref, bits 20:12 reserved */
4856 mask |= 0x1ff000;
4857 else
4858 /* bits 6:3 reserved */
4859 mask |= 0x78;
4860 }
4861
4862 return mask;
4863 }
4864
4865 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4866 int level)
4867 {
4868 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4869
4870 /* 010b (write-only) */
4871 WARN_ON((spte & 0x7) == 0x2);
4872
4873 /* 110b (write/execute) */
4874 WARN_ON((spte & 0x7) == 0x6);
4875
4876 /* 100b (execute-only) and value not supported by logical processor */
4877 if (!cpu_has_vmx_ept_execute_only())
4878 WARN_ON((spte & 0x7) == 0x4);
4879
4880 /* not 000b */
4881 if ((spte & 0x7)) {
4882 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4883
4884 if (rsvd_bits != 0) {
4885 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4886 __func__, rsvd_bits);
4887 WARN_ON(1);
4888 }
4889
4890 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4891 u64 ept_mem_type = (spte & 0x38) >> 3;
4892
4893 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4894 ept_mem_type == 7) {
4895 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4896 __func__, ept_mem_type);
4897 WARN_ON(1);
4898 }
4899 }
4900 }
4901 }
4902
4903 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4904 {
4905 u64 sptes[4];
4906 int nr_sptes, i, ret;
4907 gpa_t gpa;
4908
4909 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4910
4911 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4912 if (likely(ret == 1))
4913 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4914 EMULATE_DONE;
4915 if (unlikely(!ret))
4916 return 1;
4917
4918 /* It is the real ept misconfig */
4919 printk(KERN_ERR "EPT: Misconfiguration.\n");
4920 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4921
4922 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4923
4924 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4925 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4926
4927 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4928 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4929
4930 return 0;
4931 }
4932
4933 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4934 {
4935 u32 cpu_based_vm_exec_control;
4936
4937 /* clear pending NMI */
4938 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4939 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4940 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4941 ++vcpu->stat.nmi_window_exits;
4942 kvm_make_request(KVM_REQ_EVENT, vcpu);
4943
4944 return 1;
4945 }
4946
4947 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4948 {
4949 struct vcpu_vmx *vmx = to_vmx(vcpu);
4950 enum emulation_result err = EMULATE_DONE;
4951 int ret = 1;
4952 u32 cpu_exec_ctrl;
4953 bool intr_window_requested;
4954 unsigned count = 130;
4955
4956 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4957 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4958
4959 while (!guest_state_valid(vcpu) && count-- != 0) {
4960 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
4961 return handle_interrupt_window(&vmx->vcpu);
4962
4963 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4964 return 1;
4965
4966 err = emulate_instruction(vcpu, 0);
4967
4968 if (err == EMULATE_DO_MMIO) {
4969 ret = 0;
4970 goto out;
4971 }
4972
4973 if (err != EMULATE_DONE) {
4974 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4975 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4976 vcpu->run->internal.ndata = 0;
4977 return 0;
4978 }
4979
4980 if (signal_pending(current))
4981 goto out;
4982 if (need_resched())
4983 schedule();
4984 }
4985
4986 vmx->emulation_required = !guest_state_valid(vcpu);
4987 out:
4988 return ret;
4989 }
4990
4991 /*
4992 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4993 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4994 */
4995 static int handle_pause(struct kvm_vcpu *vcpu)
4996 {
4997 skip_emulated_instruction(vcpu);
4998 kvm_vcpu_on_spin(vcpu);
4999
5000 return 1;
5001 }
5002
5003 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5004 {
5005 kvm_queue_exception(vcpu, UD_VECTOR);
5006 return 1;
5007 }
5008
5009 /*
5010 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5011 * We could reuse a single VMCS for all the L2 guests, but we also want the
5012 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5013 * allows keeping them loaded on the processor, and in the future will allow
5014 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5015 * every entry if they never change.
5016 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5017 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5018 *
5019 * The following functions allocate and free a vmcs02 in this pool.
5020 */
5021
5022 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5023 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5024 {
5025 struct vmcs02_list *item;
5026 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5027 if (item->vmptr == vmx->nested.current_vmptr) {
5028 list_move(&item->list, &vmx->nested.vmcs02_pool);
5029 return &item->vmcs02;
5030 }
5031
5032 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5033 /* Recycle the least recently used VMCS. */
5034 item = list_entry(vmx->nested.vmcs02_pool.prev,
5035 struct vmcs02_list, list);
5036 item->vmptr = vmx->nested.current_vmptr;
5037 list_move(&item->list, &vmx->nested.vmcs02_pool);
5038 return &item->vmcs02;
5039 }
5040
5041 /* Create a new VMCS */
5042 item = (struct vmcs02_list *)
5043 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5044 if (!item)
5045 return NULL;
5046 item->vmcs02.vmcs = alloc_vmcs();
5047 if (!item->vmcs02.vmcs) {
5048 kfree(item);
5049 return NULL;
5050 }
5051 loaded_vmcs_init(&item->vmcs02);
5052 item->vmptr = vmx->nested.current_vmptr;
5053 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5054 vmx->nested.vmcs02_num++;
5055 return &item->vmcs02;
5056 }
5057
5058 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5059 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5060 {
5061 struct vmcs02_list *item;
5062 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5063 if (item->vmptr == vmptr) {
5064 free_loaded_vmcs(&item->vmcs02);
5065 list_del(&item->list);
5066 kfree(item);
5067 vmx->nested.vmcs02_num--;
5068 return;
5069 }
5070 }
5071
5072 /*
5073 * Free all VMCSs saved for this vcpu, except the one pointed by
5074 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5075 * currently used, if running L2), and vmcs01 when running L2.
5076 */
5077 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5078 {
5079 struct vmcs02_list *item, *n;
5080 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5081 if (vmx->loaded_vmcs != &item->vmcs02)
5082 free_loaded_vmcs(&item->vmcs02);
5083 list_del(&item->list);
5084 kfree(item);
5085 }
5086 vmx->nested.vmcs02_num = 0;
5087
5088 if (vmx->loaded_vmcs != &vmx->vmcs01)
5089 free_loaded_vmcs(&vmx->vmcs01);
5090 }
5091
5092 /*
5093 * Emulate the VMXON instruction.
5094 * Currently, we just remember that VMX is active, and do not save or even
5095 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5096 * do not currently need to store anything in that guest-allocated memory
5097 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5098 * argument is different from the VMXON pointer (which the spec says they do).
5099 */
5100 static int handle_vmon(struct kvm_vcpu *vcpu)
5101 {
5102 struct kvm_segment cs;
5103 struct vcpu_vmx *vmx = to_vmx(vcpu);
5104
5105 /* The Intel VMX Instruction Reference lists a bunch of bits that
5106 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5107 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5108 * Otherwise, we should fail with #UD. We test these now:
5109 */
5110 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5111 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5112 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5113 kvm_queue_exception(vcpu, UD_VECTOR);
5114 return 1;
5115 }
5116
5117 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5118 if (is_long_mode(vcpu) && !cs.l) {
5119 kvm_queue_exception(vcpu, UD_VECTOR);
5120 return 1;
5121 }
5122
5123 if (vmx_get_cpl(vcpu)) {
5124 kvm_inject_gp(vcpu, 0);
5125 return 1;
5126 }
5127
5128 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5129 vmx->nested.vmcs02_num = 0;
5130
5131 vmx->nested.vmxon = true;
5132
5133 skip_emulated_instruction(vcpu);
5134 return 1;
5135 }
5136
5137 /*
5138 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5139 * for running VMX instructions (except VMXON, whose prerequisites are
5140 * slightly different). It also specifies what exception to inject otherwise.
5141 */
5142 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5143 {
5144 struct kvm_segment cs;
5145 struct vcpu_vmx *vmx = to_vmx(vcpu);
5146
5147 if (!vmx->nested.vmxon) {
5148 kvm_queue_exception(vcpu, UD_VECTOR);
5149 return 0;
5150 }
5151
5152 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5153 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5154 (is_long_mode(vcpu) && !cs.l)) {
5155 kvm_queue_exception(vcpu, UD_VECTOR);
5156 return 0;
5157 }
5158
5159 if (vmx_get_cpl(vcpu)) {
5160 kvm_inject_gp(vcpu, 0);
5161 return 0;
5162 }
5163
5164 return 1;
5165 }
5166
5167 /*
5168 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5169 * just stops using VMX.
5170 */
5171 static void free_nested(struct vcpu_vmx *vmx)
5172 {
5173 if (!vmx->nested.vmxon)
5174 return;
5175 vmx->nested.vmxon = false;
5176 if (vmx->nested.current_vmptr != -1ull) {
5177 kunmap(vmx->nested.current_vmcs12_page);
5178 nested_release_page(vmx->nested.current_vmcs12_page);
5179 vmx->nested.current_vmptr = -1ull;
5180 vmx->nested.current_vmcs12 = NULL;
5181 }
5182 /* Unpin physical memory we referred to in current vmcs02 */
5183 if (vmx->nested.apic_access_page) {
5184 nested_release_page(vmx->nested.apic_access_page);
5185 vmx->nested.apic_access_page = 0;
5186 }
5187
5188 nested_free_all_saved_vmcss(vmx);
5189 }
5190
5191 /* Emulate the VMXOFF instruction */
5192 static int handle_vmoff(struct kvm_vcpu *vcpu)
5193 {
5194 if (!nested_vmx_check_permission(vcpu))
5195 return 1;
5196 free_nested(to_vmx(vcpu));
5197 skip_emulated_instruction(vcpu);
5198 return 1;
5199 }
5200
5201 /*
5202 * Decode the memory-address operand of a vmx instruction, as recorded on an
5203 * exit caused by such an instruction (run by a guest hypervisor).
5204 * On success, returns 0. When the operand is invalid, returns 1 and throws
5205 * #UD or #GP.
5206 */
5207 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5208 unsigned long exit_qualification,
5209 u32 vmx_instruction_info, gva_t *ret)
5210 {
5211 /*
5212 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5213 * Execution", on an exit, vmx_instruction_info holds most of the
5214 * addressing components of the operand. Only the displacement part
5215 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5216 * For how an actual address is calculated from all these components,
5217 * refer to Vol. 1, "Operand Addressing".
5218 */
5219 int scaling = vmx_instruction_info & 3;
5220 int addr_size = (vmx_instruction_info >> 7) & 7;
5221 bool is_reg = vmx_instruction_info & (1u << 10);
5222 int seg_reg = (vmx_instruction_info >> 15) & 7;
5223 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5224 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5225 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5226 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5227
5228 if (is_reg) {
5229 kvm_queue_exception(vcpu, UD_VECTOR);
5230 return 1;
5231 }
5232
5233 /* Addr = segment_base + offset */
5234 /* offset = base + [index * scale] + displacement */
5235 *ret = vmx_get_segment_base(vcpu, seg_reg);
5236 if (base_is_valid)
5237 *ret += kvm_register_read(vcpu, base_reg);
5238 if (index_is_valid)
5239 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5240 *ret += exit_qualification; /* holds the displacement */
5241
5242 if (addr_size == 1) /* 32 bit */
5243 *ret &= 0xffffffff;
5244
5245 /*
5246 * TODO: throw #GP (and return 1) in various cases that the VM*
5247 * instructions require it - e.g., offset beyond segment limit,
5248 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5249 * address, and so on. Currently these are not checked.
5250 */
5251 return 0;
5252 }
5253
5254 /*
5255 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5256 * set the success or error code of an emulated VMX instruction, as specified
5257 * by Vol 2B, VMX Instruction Reference, "Conventions".
5258 */
5259 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5260 {
5261 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5262 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5263 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5264 }
5265
5266 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5267 {
5268 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5269 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5270 X86_EFLAGS_SF | X86_EFLAGS_OF))
5271 | X86_EFLAGS_CF);
5272 }
5273
5274 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5275 u32 vm_instruction_error)
5276 {
5277 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5278 /*
5279 * failValid writes the error number to the current VMCS, which
5280 * can't be done there isn't a current VMCS.
5281 */
5282 nested_vmx_failInvalid(vcpu);
5283 return;
5284 }
5285 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5286 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5287 X86_EFLAGS_SF | X86_EFLAGS_OF))
5288 | X86_EFLAGS_ZF);
5289 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5290 }
5291
5292 /* Emulate the VMCLEAR instruction */
5293 static int handle_vmclear(struct kvm_vcpu *vcpu)
5294 {
5295 struct vcpu_vmx *vmx = to_vmx(vcpu);
5296 gva_t gva;
5297 gpa_t vmptr;
5298 struct vmcs12 *vmcs12;
5299 struct page *page;
5300 struct x86_exception e;
5301
5302 if (!nested_vmx_check_permission(vcpu))
5303 return 1;
5304
5305 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5306 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5307 return 1;
5308
5309 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5310 sizeof(vmptr), &e)) {
5311 kvm_inject_page_fault(vcpu, &e);
5312 return 1;
5313 }
5314
5315 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5316 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5317 skip_emulated_instruction(vcpu);
5318 return 1;
5319 }
5320
5321 if (vmptr == vmx->nested.current_vmptr) {
5322 kunmap(vmx->nested.current_vmcs12_page);
5323 nested_release_page(vmx->nested.current_vmcs12_page);
5324 vmx->nested.current_vmptr = -1ull;
5325 vmx->nested.current_vmcs12 = NULL;
5326 }
5327
5328 page = nested_get_page(vcpu, vmptr);
5329 if (page == NULL) {
5330 /*
5331 * For accurate processor emulation, VMCLEAR beyond available
5332 * physical memory should do nothing at all. However, it is
5333 * possible that a nested vmx bug, not a guest hypervisor bug,
5334 * resulted in this case, so let's shut down before doing any
5335 * more damage:
5336 */
5337 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5338 return 1;
5339 }
5340 vmcs12 = kmap(page);
5341 vmcs12->launch_state = 0;
5342 kunmap(page);
5343 nested_release_page(page);
5344
5345 nested_free_vmcs02(vmx, vmptr);
5346
5347 skip_emulated_instruction(vcpu);
5348 nested_vmx_succeed(vcpu);
5349 return 1;
5350 }
5351
5352 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5353
5354 /* Emulate the VMLAUNCH instruction */
5355 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5356 {
5357 return nested_vmx_run(vcpu, true);
5358 }
5359
5360 /* Emulate the VMRESUME instruction */
5361 static int handle_vmresume(struct kvm_vcpu *vcpu)
5362 {
5363
5364 return nested_vmx_run(vcpu, false);
5365 }
5366
5367 enum vmcs_field_type {
5368 VMCS_FIELD_TYPE_U16 = 0,
5369 VMCS_FIELD_TYPE_U64 = 1,
5370 VMCS_FIELD_TYPE_U32 = 2,
5371 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5372 };
5373
5374 static inline int vmcs_field_type(unsigned long field)
5375 {
5376 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5377 return VMCS_FIELD_TYPE_U32;
5378 return (field >> 13) & 0x3 ;
5379 }
5380
5381 static inline int vmcs_field_readonly(unsigned long field)
5382 {
5383 return (((field >> 10) & 0x3) == 1);
5384 }
5385
5386 /*
5387 * Read a vmcs12 field. Since these can have varying lengths and we return
5388 * one type, we chose the biggest type (u64) and zero-extend the return value
5389 * to that size. Note that the caller, handle_vmread, might need to use only
5390 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5391 * 64-bit fields are to be returned).
5392 */
5393 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5394 unsigned long field, u64 *ret)
5395 {
5396 short offset = vmcs_field_to_offset(field);
5397 char *p;
5398
5399 if (offset < 0)
5400 return 0;
5401
5402 p = ((char *)(get_vmcs12(vcpu))) + offset;
5403
5404 switch (vmcs_field_type(field)) {
5405 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5406 *ret = *((natural_width *)p);
5407 return 1;
5408 case VMCS_FIELD_TYPE_U16:
5409 *ret = *((u16 *)p);
5410 return 1;
5411 case VMCS_FIELD_TYPE_U32:
5412 *ret = *((u32 *)p);
5413 return 1;
5414 case VMCS_FIELD_TYPE_U64:
5415 *ret = *((u64 *)p);
5416 return 1;
5417 default:
5418 return 0; /* can never happen. */
5419 }
5420 }
5421
5422 /*
5423 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5424 * used before) all generate the same failure when it is missing.
5425 */
5426 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5427 {
5428 struct vcpu_vmx *vmx = to_vmx(vcpu);
5429 if (vmx->nested.current_vmptr == -1ull) {
5430 nested_vmx_failInvalid(vcpu);
5431 skip_emulated_instruction(vcpu);
5432 return 0;
5433 }
5434 return 1;
5435 }
5436
5437 static int handle_vmread(struct kvm_vcpu *vcpu)
5438 {
5439 unsigned long field;
5440 u64 field_value;
5441 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5442 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5443 gva_t gva = 0;
5444
5445 if (!nested_vmx_check_permission(vcpu) ||
5446 !nested_vmx_check_vmcs12(vcpu))
5447 return 1;
5448
5449 /* Decode instruction info and find the field to read */
5450 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5451 /* Read the field, zero-extended to a u64 field_value */
5452 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5453 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5454 skip_emulated_instruction(vcpu);
5455 return 1;
5456 }
5457 /*
5458 * Now copy part of this value to register or memory, as requested.
5459 * Note that the number of bits actually copied is 32 or 64 depending
5460 * on the guest's mode (32 or 64 bit), not on the given field's length.
5461 */
5462 if (vmx_instruction_info & (1u << 10)) {
5463 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5464 field_value);
5465 } else {
5466 if (get_vmx_mem_address(vcpu, exit_qualification,
5467 vmx_instruction_info, &gva))
5468 return 1;
5469 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5470 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5471 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5472 }
5473
5474 nested_vmx_succeed(vcpu);
5475 skip_emulated_instruction(vcpu);
5476 return 1;
5477 }
5478
5479
5480 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5481 {
5482 unsigned long field;
5483 gva_t gva;
5484 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5485 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5486 char *p;
5487 short offset;
5488 /* The value to write might be 32 or 64 bits, depending on L1's long
5489 * mode, and eventually we need to write that into a field of several
5490 * possible lengths. The code below first zero-extends the value to 64
5491 * bit (field_value), and then copies only the approriate number of
5492 * bits into the vmcs12 field.
5493 */
5494 u64 field_value = 0;
5495 struct x86_exception e;
5496
5497 if (!nested_vmx_check_permission(vcpu) ||
5498 !nested_vmx_check_vmcs12(vcpu))
5499 return 1;
5500
5501 if (vmx_instruction_info & (1u << 10))
5502 field_value = kvm_register_read(vcpu,
5503 (((vmx_instruction_info) >> 3) & 0xf));
5504 else {
5505 if (get_vmx_mem_address(vcpu, exit_qualification,
5506 vmx_instruction_info, &gva))
5507 return 1;
5508 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5509 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5510 kvm_inject_page_fault(vcpu, &e);
5511 return 1;
5512 }
5513 }
5514
5515
5516 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5517 if (vmcs_field_readonly(field)) {
5518 nested_vmx_failValid(vcpu,
5519 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5520 skip_emulated_instruction(vcpu);
5521 return 1;
5522 }
5523
5524 offset = vmcs_field_to_offset(field);
5525 if (offset < 0) {
5526 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5527 skip_emulated_instruction(vcpu);
5528 return 1;
5529 }
5530 p = ((char *) get_vmcs12(vcpu)) + offset;
5531
5532 switch (vmcs_field_type(field)) {
5533 case VMCS_FIELD_TYPE_U16:
5534 *(u16 *)p = field_value;
5535 break;
5536 case VMCS_FIELD_TYPE_U32:
5537 *(u32 *)p = field_value;
5538 break;
5539 case VMCS_FIELD_TYPE_U64:
5540 *(u64 *)p = field_value;
5541 break;
5542 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5543 *(natural_width *)p = field_value;
5544 break;
5545 default:
5546 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5547 skip_emulated_instruction(vcpu);
5548 return 1;
5549 }
5550
5551 nested_vmx_succeed(vcpu);
5552 skip_emulated_instruction(vcpu);
5553 return 1;
5554 }
5555
5556 /* Emulate the VMPTRLD instruction */
5557 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5558 {
5559 struct vcpu_vmx *vmx = to_vmx(vcpu);
5560 gva_t gva;
5561 gpa_t vmptr;
5562 struct x86_exception e;
5563
5564 if (!nested_vmx_check_permission(vcpu))
5565 return 1;
5566
5567 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5568 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5569 return 1;
5570
5571 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5572 sizeof(vmptr), &e)) {
5573 kvm_inject_page_fault(vcpu, &e);
5574 return 1;
5575 }
5576
5577 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5578 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5579 skip_emulated_instruction(vcpu);
5580 return 1;
5581 }
5582
5583 if (vmx->nested.current_vmptr != vmptr) {
5584 struct vmcs12 *new_vmcs12;
5585 struct page *page;
5586 page = nested_get_page(vcpu, vmptr);
5587 if (page == NULL) {
5588 nested_vmx_failInvalid(vcpu);
5589 skip_emulated_instruction(vcpu);
5590 return 1;
5591 }
5592 new_vmcs12 = kmap(page);
5593 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5594 kunmap(page);
5595 nested_release_page_clean(page);
5596 nested_vmx_failValid(vcpu,
5597 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5598 skip_emulated_instruction(vcpu);
5599 return 1;
5600 }
5601 if (vmx->nested.current_vmptr != -1ull) {
5602 kunmap(vmx->nested.current_vmcs12_page);
5603 nested_release_page(vmx->nested.current_vmcs12_page);
5604 }
5605
5606 vmx->nested.current_vmptr = vmptr;
5607 vmx->nested.current_vmcs12 = new_vmcs12;
5608 vmx->nested.current_vmcs12_page = page;
5609 }
5610
5611 nested_vmx_succeed(vcpu);
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
5615
5616 /* Emulate the VMPTRST instruction */
5617 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5618 {
5619 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5620 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5621 gva_t vmcs_gva;
5622 struct x86_exception e;
5623
5624 if (!nested_vmx_check_permission(vcpu))
5625 return 1;
5626
5627 if (get_vmx_mem_address(vcpu, exit_qualification,
5628 vmx_instruction_info, &vmcs_gva))
5629 return 1;
5630 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5631 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5632 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5633 sizeof(u64), &e)) {
5634 kvm_inject_page_fault(vcpu, &e);
5635 return 1;
5636 }
5637 nested_vmx_succeed(vcpu);
5638 skip_emulated_instruction(vcpu);
5639 return 1;
5640 }
5641
5642 /*
5643 * The exit handlers return 1 if the exit was handled fully and guest execution
5644 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5645 * to be done to userspace and return 0.
5646 */
5647 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5648 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5649 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5650 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5651 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5652 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5653 [EXIT_REASON_CR_ACCESS] = handle_cr,
5654 [EXIT_REASON_DR_ACCESS] = handle_dr,
5655 [EXIT_REASON_CPUID] = handle_cpuid,
5656 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5657 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5658 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5659 [EXIT_REASON_HLT] = handle_halt,
5660 [EXIT_REASON_INVD] = handle_invd,
5661 [EXIT_REASON_INVLPG] = handle_invlpg,
5662 [EXIT_REASON_RDPMC] = handle_rdpmc,
5663 [EXIT_REASON_VMCALL] = handle_vmcall,
5664 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5665 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5666 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5667 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5668 [EXIT_REASON_VMREAD] = handle_vmread,
5669 [EXIT_REASON_VMRESUME] = handle_vmresume,
5670 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5671 [EXIT_REASON_VMOFF] = handle_vmoff,
5672 [EXIT_REASON_VMON] = handle_vmon,
5673 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5674 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5675 [EXIT_REASON_WBINVD] = handle_wbinvd,
5676 [EXIT_REASON_XSETBV] = handle_xsetbv,
5677 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5678 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5679 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5680 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5681 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5682 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5683 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5684 };
5685
5686 static const int kvm_vmx_max_exit_handlers =
5687 ARRAY_SIZE(kvm_vmx_exit_handlers);
5688
5689 /*
5690 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5691 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5692 * disinterest in the current event (read or write a specific MSR) by using an
5693 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5694 */
5695 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5696 struct vmcs12 *vmcs12, u32 exit_reason)
5697 {
5698 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5699 gpa_t bitmap;
5700
5701 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5702 return 1;
5703
5704 /*
5705 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5706 * for the four combinations of read/write and low/high MSR numbers.
5707 * First we need to figure out which of the four to use:
5708 */
5709 bitmap = vmcs12->msr_bitmap;
5710 if (exit_reason == EXIT_REASON_MSR_WRITE)
5711 bitmap += 2048;
5712 if (msr_index >= 0xc0000000) {
5713 msr_index -= 0xc0000000;
5714 bitmap += 1024;
5715 }
5716
5717 /* Then read the msr_index'th bit from this bitmap: */
5718 if (msr_index < 1024*8) {
5719 unsigned char b;
5720 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5721 return 1 & (b >> (msr_index & 7));
5722 } else
5723 return 1; /* let L1 handle the wrong parameter */
5724 }
5725
5726 /*
5727 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5728 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5729 * intercept (via guest_host_mask etc.) the current event.
5730 */
5731 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5732 struct vmcs12 *vmcs12)
5733 {
5734 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5735 int cr = exit_qualification & 15;
5736 int reg = (exit_qualification >> 8) & 15;
5737 unsigned long val = kvm_register_read(vcpu, reg);
5738
5739 switch ((exit_qualification >> 4) & 3) {
5740 case 0: /* mov to cr */
5741 switch (cr) {
5742 case 0:
5743 if (vmcs12->cr0_guest_host_mask &
5744 (val ^ vmcs12->cr0_read_shadow))
5745 return 1;
5746 break;
5747 case 3:
5748 if ((vmcs12->cr3_target_count >= 1 &&
5749 vmcs12->cr3_target_value0 == val) ||
5750 (vmcs12->cr3_target_count >= 2 &&
5751 vmcs12->cr3_target_value1 == val) ||
5752 (vmcs12->cr3_target_count >= 3 &&
5753 vmcs12->cr3_target_value2 == val) ||
5754 (vmcs12->cr3_target_count >= 4 &&
5755 vmcs12->cr3_target_value3 == val))
5756 return 0;
5757 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5758 return 1;
5759 break;
5760 case 4:
5761 if (vmcs12->cr4_guest_host_mask &
5762 (vmcs12->cr4_read_shadow ^ val))
5763 return 1;
5764 break;
5765 case 8:
5766 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5767 return 1;
5768 break;
5769 }
5770 break;
5771 case 2: /* clts */
5772 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5773 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5774 return 1;
5775 break;
5776 case 1: /* mov from cr */
5777 switch (cr) {
5778 case 3:
5779 if (vmcs12->cpu_based_vm_exec_control &
5780 CPU_BASED_CR3_STORE_EXITING)
5781 return 1;
5782 break;
5783 case 8:
5784 if (vmcs12->cpu_based_vm_exec_control &
5785 CPU_BASED_CR8_STORE_EXITING)
5786 return 1;
5787 break;
5788 }
5789 break;
5790 case 3: /* lmsw */
5791 /*
5792 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5793 * cr0. Other attempted changes are ignored, with no exit.
5794 */
5795 if (vmcs12->cr0_guest_host_mask & 0xe &
5796 (val ^ vmcs12->cr0_read_shadow))
5797 return 1;
5798 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5799 !(vmcs12->cr0_read_shadow & 0x1) &&
5800 (val & 0x1))
5801 return 1;
5802 break;
5803 }
5804 return 0;
5805 }
5806
5807 /*
5808 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5809 * should handle it ourselves in L0 (and then continue L2). Only call this
5810 * when in is_guest_mode (L2).
5811 */
5812 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5813 {
5814 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5815 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5816 struct vcpu_vmx *vmx = to_vmx(vcpu);
5817 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5818
5819 if (vmx->nested.nested_run_pending)
5820 return 0;
5821
5822 if (unlikely(vmx->fail)) {
5823 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5824 vmcs_read32(VM_INSTRUCTION_ERROR));
5825 return 1;
5826 }
5827
5828 switch (exit_reason) {
5829 case EXIT_REASON_EXCEPTION_NMI:
5830 if (!is_exception(intr_info))
5831 return 0;
5832 else if (is_page_fault(intr_info))
5833 return enable_ept;
5834 return vmcs12->exception_bitmap &
5835 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5836 case EXIT_REASON_EXTERNAL_INTERRUPT:
5837 return 0;
5838 case EXIT_REASON_TRIPLE_FAULT:
5839 return 1;
5840 case EXIT_REASON_PENDING_INTERRUPT:
5841 case EXIT_REASON_NMI_WINDOW:
5842 /*
5843 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5844 * (aka Interrupt Window Exiting) only when L1 turned it on,
5845 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5846 * Same for NMI Window Exiting.
5847 */
5848 return 1;
5849 case EXIT_REASON_TASK_SWITCH:
5850 return 1;
5851 case EXIT_REASON_CPUID:
5852 return 1;
5853 case EXIT_REASON_HLT:
5854 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5855 case EXIT_REASON_INVD:
5856 return 1;
5857 case EXIT_REASON_INVLPG:
5858 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5859 case EXIT_REASON_RDPMC:
5860 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5861 case EXIT_REASON_RDTSC:
5862 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5863 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5864 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5865 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5866 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5867 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5868 /*
5869 * VMX instructions trap unconditionally. This allows L1 to
5870 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5871 */
5872 return 1;
5873 case EXIT_REASON_CR_ACCESS:
5874 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5875 case EXIT_REASON_DR_ACCESS:
5876 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5877 case EXIT_REASON_IO_INSTRUCTION:
5878 /* TODO: support IO bitmaps */
5879 return 1;
5880 case EXIT_REASON_MSR_READ:
5881 case EXIT_REASON_MSR_WRITE:
5882 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5883 case EXIT_REASON_INVALID_STATE:
5884 return 1;
5885 case EXIT_REASON_MWAIT_INSTRUCTION:
5886 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5887 case EXIT_REASON_MONITOR_INSTRUCTION:
5888 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5889 case EXIT_REASON_PAUSE_INSTRUCTION:
5890 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5891 nested_cpu_has2(vmcs12,
5892 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5893 case EXIT_REASON_MCE_DURING_VMENTRY:
5894 return 0;
5895 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5896 return 1;
5897 case EXIT_REASON_APIC_ACCESS:
5898 return nested_cpu_has2(vmcs12,
5899 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5900 case EXIT_REASON_EPT_VIOLATION:
5901 case EXIT_REASON_EPT_MISCONFIG:
5902 return 0;
5903 case EXIT_REASON_WBINVD:
5904 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5905 case EXIT_REASON_XSETBV:
5906 return 1;
5907 default:
5908 return 1;
5909 }
5910 }
5911
5912 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5913 {
5914 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5915 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5916 }
5917
5918 /*
5919 * The guest has exited. See if we can fix it or if we need userspace
5920 * assistance.
5921 */
5922 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5923 {
5924 struct vcpu_vmx *vmx = to_vmx(vcpu);
5925 u32 exit_reason = vmx->exit_reason;
5926 u32 vectoring_info = vmx->idt_vectoring_info;
5927
5928 /* If guest state is invalid, start emulating */
5929 if (vmx->emulation_required && emulate_invalid_guest_state)
5930 return handle_invalid_guest_state(vcpu);
5931
5932 /*
5933 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5934 * we did not inject a still-pending event to L1 now because of
5935 * nested_run_pending, we need to re-enable this bit.
5936 */
5937 if (vmx->nested.nested_run_pending)
5938 kvm_make_request(KVM_REQ_EVENT, vcpu);
5939
5940 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5941 exit_reason == EXIT_REASON_VMRESUME))
5942 vmx->nested.nested_run_pending = 1;
5943 else
5944 vmx->nested.nested_run_pending = 0;
5945
5946 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5947 nested_vmx_vmexit(vcpu);
5948 return 1;
5949 }
5950
5951 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5952 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5953 vcpu->run->fail_entry.hardware_entry_failure_reason
5954 = exit_reason;
5955 return 0;
5956 }
5957
5958 if (unlikely(vmx->fail)) {
5959 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5960 vcpu->run->fail_entry.hardware_entry_failure_reason
5961 = vmcs_read32(VM_INSTRUCTION_ERROR);
5962 return 0;
5963 }
5964
5965 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5966 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5967 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5968 exit_reason != EXIT_REASON_TASK_SWITCH))
5969 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5970 "(0x%x) and exit reason is 0x%x\n",
5971 __func__, vectoring_info, exit_reason);
5972
5973 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5974 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5975 get_vmcs12(vcpu), vcpu)))) {
5976 if (vmx_interrupt_allowed(vcpu)) {
5977 vmx->soft_vnmi_blocked = 0;
5978 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5979 vcpu->arch.nmi_pending) {
5980 /*
5981 * This CPU don't support us in finding the end of an
5982 * NMI-blocked window if the guest runs with IRQs
5983 * disabled. So we pull the trigger after 1 s of
5984 * futile waiting, but inform the user about this.
5985 */
5986 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5987 "state on VCPU %d after 1 s timeout\n",
5988 __func__, vcpu->vcpu_id);
5989 vmx->soft_vnmi_blocked = 0;
5990 }
5991 }
5992
5993 if (exit_reason < kvm_vmx_max_exit_handlers
5994 && kvm_vmx_exit_handlers[exit_reason])
5995 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5996 else {
5997 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5998 vcpu->run->hw.hardware_exit_reason = exit_reason;
5999 }
6000 return 0;
6001 }
6002
6003 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6004 {
6005 if (irr == -1 || tpr < irr) {
6006 vmcs_write32(TPR_THRESHOLD, 0);
6007 return;
6008 }
6009
6010 vmcs_write32(TPR_THRESHOLD, irr);
6011 }
6012
6013 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6014 {
6015 u32 exit_intr_info;
6016
6017 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6018 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6019 return;
6020
6021 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6022 exit_intr_info = vmx->exit_intr_info;
6023
6024 /* Handle machine checks before interrupts are enabled */
6025 if (is_machine_check(exit_intr_info))
6026 kvm_machine_check();
6027
6028 /* We need to handle NMIs before interrupts are enabled */
6029 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6030 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6031 kvm_before_handle_nmi(&vmx->vcpu);
6032 asm("int $2");
6033 kvm_after_handle_nmi(&vmx->vcpu);
6034 }
6035 }
6036
6037 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6038 {
6039 u32 exit_intr_info;
6040 bool unblock_nmi;
6041 u8 vector;
6042 bool idtv_info_valid;
6043
6044 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6045
6046 if (cpu_has_virtual_nmis()) {
6047 if (vmx->nmi_known_unmasked)
6048 return;
6049 /*
6050 * Can't use vmx->exit_intr_info since we're not sure what
6051 * the exit reason is.
6052 */
6053 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6054 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6055 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6056 /*
6057 * SDM 3: 27.7.1.2 (September 2008)
6058 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6059 * a guest IRET fault.
6060 * SDM 3: 23.2.2 (September 2008)
6061 * Bit 12 is undefined in any of the following cases:
6062 * If the VM exit sets the valid bit in the IDT-vectoring
6063 * information field.
6064 * If the VM exit is due to a double fault.
6065 */
6066 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6067 vector != DF_VECTOR && !idtv_info_valid)
6068 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6069 GUEST_INTR_STATE_NMI);
6070 else
6071 vmx->nmi_known_unmasked =
6072 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6073 & GUEST_INTR_STATE_NMI);
6074 } else if (unlikely(vmx->soft_vnmi_blocked))
6075 vmx->vnmi_blocked_time +=
6076 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6077 }
6078
6079 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6080 u32 idt_vectoring_info,
6081 int instr_len_field,
6082 int error_code_field)
6083 {
6084 u8 vector;
6085 int type;
6086 bool idtv_info_valid;
6087
6088 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6089
6090 vmx->vcpu.arch.nmi_injected = false;
6091 kvm_clear_exception_queue(&vmx->vcpu);
6092 kvm_clear_interrupt_queue(&vmx->vcpu);
6093
6094 if (!idtv_info_valid)
6095 return;
6096
6097 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6098
6099 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6100 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6101
6102 switch (type) {
6103 case INTR_TYPE_NMI_INTR:
6104 vmx->vcpu.arch.nmi_injected = true;
6105 /*
6106 * SDM 3: 27.7.1.2 (September 2008)
6107 * Clear bit "block by NMI" before VM entry if a NMI
6108 * delivery faulted.
6109 */
6110 vmx_set_nmi_mask(&vmx->vcpu, false);
6111 break;
6112 case INTR_TYPE_SOFT_EXCEPTION:
6113 vmx->vcpu.arch.event_exit_inst_len =
6114 vmcs_read32(instr_len_field);
6115 /* fall through */
6116 case INTR_TYPE_HARD_EXCEPTION:
6117 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6118 u32 err = vmcs_read32(error_code_field);
6119 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6120 } else
6121 kvm_queue_exception(&vmx->vcpu, vector);
6122 break;
6123 case INTR_TYPE_SOFT_INTR:
6124 vmx->vcpu.arch.event_exit_inst_len =
6125 vmcs_read32(instr_len_field);
6126 /* fall through */
6127 case INTR_TYPE_EXT_INTR:
6128 kvm_queue_interrupt(&vmx->vcpu, vector,
6129 type == INTR_TYPE_SOFT_INTR);
6130 break;
6131 default:
6132 break;
6133 }
6134 }
6135
6136 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6137 {
6138 if (is_guest_mode(&vmx->vcpu))
6139 return;
6140 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6141 VM_EXIT_INSTRUCTION_LEN,
6142 IDT_VECTORING_ERROR_CODE);
6143 }
6144
6145 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6146 {
6147 if (is_guest_mode(vcpu))
6148 return;
6149 __vmx_complete_interrupts(to_vmx(vcpu),
6150 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6151 VM_ENTRY_INSTRUCTION_LEN,
6152 VM_ENTRY_EXCEPTION_ERROR_CODE);
6153
6154 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6155 }
6156
6157 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6158 {
6159 int i, nr_msrs;
6160 struct perf_guest_switch_msr *msrs;
6161
6162 msrs = perf_guest_get_msrs(&nr_msrs);
6163
6164 if (!msrs)
6165 return;
6166
6167 for (i = 0; i < nr_msrs; i++)
6168 if (msrs[i].host == msrs[i].guest)
6169 clear_atomic_switch_msr(vmx, msrs[i].msr);
6170 else
6171 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6172 msrs[i].host);
6173 }
6174
6175 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6176 {
6177 struct vcpu_vmx *vmx = to_vmx(vcpu);
6178 unsigned long debugctlmsr;
6179
6180 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6181 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6182 if (vmcs12->idt_vectoring_info_field &
6183 VECTORING_INFO_VALID_MASK) {
6184 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6185 vmcs12->idt_vectoring_info_field);
6186 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6187 vmcs12->vm_exit_instruction_len);
6188 if (vmcs12->idt_vectoring_info_field &
6189 VECTORING_INFO_DELIVER_CODE_MASK)
6190 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6191 vmcs12->idt_vectoring_error_code);
6192 }
6193 }
6194
6195 /* Record the guest's net vcpu time for enforced NMI injections. */
6196 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6197 vmx->entry_time = ktime_get();
6198
6199 /* Don't enter VMX if guest state is invalid, let the exit handler
6200 start emulation until we arrive back to a valid state */
6201 if (vmx->emulation_required && emulate_invalid_guest_state)
6202 return;
6203
6204 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6205 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6206 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6207 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6208
6209 /* When single-stepping over STI and MOV SS, we must clear the
6210 * corresponding interruptibility bits in the guest state. Otherwise
6211 * vmentry fails as it then expects bit 14 (BS) in pending debug
6212 * exceptions being set, but that's not correct for the guest debugging
6213 * case. */
6214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6215 vmx_set_interrupt_shadow(vcpu, 0);
6216
6217 atomic_switch_perf_msrs(vmx);
6218 debugctlmsr = get_debugctlmsr();
6219
6220 vmx->__launched = vmx->loaded_vmcs->launched;
6221 asm(
6222 /* Store host registers */
6223 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6224 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6225 "push %%" _ASM_CX " \n\t"
6226 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6227 "je 1f \n\t"
6228 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6229 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6230 "1: \n\t"
6231 /* Reload cr2 if changed */
6232 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6233 "mov %%cr2, %%" _ASM_DX " \n\t"
6234 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6235 "je 2f \n\t"
6236 "mov %%" _ASM_AX", %%cr2 \n\t"
6237 "2: \n\t"
6238 /* Check if vmlaunch of vmresume is needed */
6239 "cmpl $0, %c[launched](%0) \n\t"
6240 /* Load guest registers. Don't clobber flags. */
6241 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6242 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6243 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6244 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6245 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6246 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6247 #ifdef CONFIG_X86_64
6248 "mov %c[r8](%0), %%r8 \n\t"
6249 "mov %c[r9](%0), %%r9 \n\t"
6250 "mov %c[r10](%0), %%r10 \n\t"
6251 "mov %c[r11](%0), %%r11 \n\t"
6252 "mov %c[r12](%0), %%r12 \n\t"
6253 "mov %c[r13](%0), %%r13 \n\t"
6254 "mov %c[r14](%0), %%r14 \n\t"
6255 "mov %c[r15](%0), %%r15 \n\t"
6256 #endif
6257 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6258
6259 /* Enter guest mode */
6260 "jne 1f \n\t"
6261 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6262 "jmp 2f \n\t"
6263 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6264 "2: "
6265 /* Save guest registers, load host registers, keep flags */
6266 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6267 "pop %0 \n\t"
6268 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6269 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6270 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6271 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6272 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6273 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6274 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6275 #ifdef CONFIG_X86_64
6276 "mov %%r8, %c[r8](%0) \n\t"
6277 "mov %%r9, %c[r9](%0) \n\t"
6278 "mov %%r10, %c[r10](%0) \n\t"
6279 "mov %%r11, %c[r11](%0) \n\t"
6280 "mov %%r12, %c[r12](%0) \n\t"
6281 "mov %%r13, %c[r13](%0) \n\t"
6282 "mov %%r14, %c[r14](%0) \n\t"
6283 "mov %%r15, %c[r15](%0) \n\t"
6284 #endif
6285 "mov %%cr2, %%" _ASM_AX " \n\t"
6286 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6287
6288 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6289 "setbe %c[fail](%0) \n\t"
6290 ".pushsection .rodata \n\t"
6291 ".global vmx_return \n\t"
6292 "vmx_return: " _ASM_PTR " 2b \n\t"
6293 ".popsection"
6294 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6295 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6296 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6297 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6298 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6299 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6300 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6301 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6302 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6303 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6304 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6305 #ifdef CONFIG_X86_64
6306 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6307 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6308 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6309 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6310 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6311 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6312 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6313 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6314 #endif
6315 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6316 [wordsize]"i"(sizeof(ulong))
6317 : "cc", "memory"
6318 #ifdef CONFIG_X86_64
6319 , "rax", "rbx", "rdi", "rsi"
6320 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6321 #else
6322 , "eax", "ebx", "edi", "esi"
6323 #endif
6324 );
6325
6326 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6327 if (debugctlmsr)
6328 update_debugctlmsr(debugctlmsr);
6329
6330 #ifndef CONFIG_X86_64
6331 /*
6332 * The sysexit path does not restore ds/es, so we must set them to
6333 * a reasonable value ourselves.
6334 *
6335 * We can't defer this to vmx_load_host_state() since that function
6336 * may be executed in interrupt context, which saves and restore segments
6337 * around it, nullifying its effect.
6338 */
6339 loadsegment(ds, __USER_DS);
6340 loadsegment(es, __USER_DS);
6341 #endif
6342
6343 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6344 | (1 << VCPU_EXREG_RFLAGS)
6345 | (1 << VCPU_EXREG_CPL)
6346 | (1 << VCPU_EXREG_PDPTR)
6347 | (1 << VCPU_EXREG_SEGMENTS)
6348 | (1 << VCPU_EXREG_CR3));
6349 vcpu->arch.regs_dirty = 0;
6350
6351 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6352
6353 if (is_guest_mode(vcpu)) {
6354 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6355 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6356 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6357 vmcs12->idt_vectoring_error_code =
6358 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6359 vmcs12->vm_exit_instruction_len =
6360 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6361 }
6362 }
6363
6364 vmx->loaded_vmcs->launched = 1;
6365
6366 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6367 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6368
6369 vmx_complete_atomic_exit(vmx);
6370 vmx_recover_nmi_blocking(vmx);
6371 vmx_complete_interrupts(vmx);
6372 }
6373
6374 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6375 {
6376 struct vcpu_vmx *vmx = to_vmx(vcpu);
6377
6378 free_vpid(vmx);
6379 free_nested(vmx);
6380 free_loaded_vmcs(vmx->loaded_vmcs);
6381 kfree(vmx->guest_msrs);
6382 kvm_vcpu_uninit(vcpu);
6383 kmem_cache_free(kvm_vcpu_cache, vmx);
6384 }
6385
6386 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6387 {
6388 int err;
6389 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6390 int cpu;
6391
6392 if (!vmx)
6393 return ERR_PTR(-ENOMEM);
6394
6395 allocate_vpid(vmx);
6396
6397 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6398 if (err)
6399 goto free_vcpu;
6400
6401 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6402 err = -ENOMEM;
6403 if (!vmx->guest_msrs) {
6404 goto uninit_vcpu;
6405 }
6406
6407 vmx->loaded_vmcs = &vmx->vmcs01;
6408 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6409 if (!vmx->loaded_vmcs->vmcs)
6410 goto free_msrs;
6411 if (!vmm_exclusive)
6412 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6413 loaded_vmcs_init(vmx->loaded_vmcs);
6414 if (!vmm_exclusive)
6415 kvm_cpu_vmxoff();
6416
6417 cpu = get_cpu();
6418 vmx_vcpu_load(&vmx->vcpu, cpu);
6419 vmx->vcpu.cpu = cpu;
6420 err = vmx_vcpu_setup(vmx);
6421 vmx_vcpu_put(&vmx->vcpu);
6422 put_cpu();
6423 if (err)
6424 goto free_vmcs;
6425 if (vm_need_virtualize_apic_accesses(kvm))
6426 err = alloc_apic_access_page(kvm);
6427 if (err)
6428 goto free_vmcs;
6429
6430 if (enable_ept) {
6431 if (!kvm->arch.ept_identity_map_addr)
6432 kvm->arch.ept_identity_map_addr =
6433 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6434 err = -ENOMEM;
6435 if (alloc_identity_pagetable(kvm) != 0)
6436 goto free_vmcs;
6437 if (!init_rmode_identity_map(kvm))
6438 goto free_vmcs;
6439 }
6440
6441 vmx->nested.current_vmptr = -1ull;
6442 vmx->nested.current_vmcs12 = NULL;
6443
6444 return &vmx->vcpu;
6445
6446 free_vmcs:
6447 free_loaded_vmcs(vmx->loaded_vmcs);
6448 free_msrs:
6449 kfree(vmx->guest_msrs);
6450 uninit_vcpu:
6451 kvm_vcpu_uninit(&vmx->vcpu);
6452 free_vcpu:
6453 free_vpid(vmx);
6454 kmem_cache_free(kvm_vcpu_cache, vmx);
6455 return ERR_PTR(err);
6456 }
6457
6458 static void __init vmx_check_processor_compat(void *rtn)
6459 {
6460 struct vmcs_config vmcs_conf;
6461
6462 *(int *)rtn = 0;
6463 if (setup_vmcs_config(&vmcs_conf) < 0)
6464 *(int *)rtn = -EIO;
6465 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6466 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6467 smp_processor_id());
6468 *(int *)rtn = -EIO;
6469 }
6470 }
6471
6472 static int get_ept_level(void)
6473 {
6474 return VMX_EPT_DEFAULT_GAW + 1;
6475 }
6476
6477 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6478 {
6479 u64 ret;
6480
6481 /* For VT-d and EPT combination
6482 * 1. MMIO: always map as UC
6483 * 2. EPT with VT-d:
6484 * a. VT-d without snooping control feature: can't guarantee the
6485 * result, try to trust guest.
6486 * b. VT-d with snooping control feature: snooping control feature of
6487 * VT-d engine can guarantee the cache correctness. Just set it
6488 * to WB to keep consistent with host. So the same as item 3.
6489 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6490 * consistent with host MTRR
6491 */
6492 if (is_mmio)
6493 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6494 else if (vcpu->kvm->arch.iommu_domain &&
6495 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6496 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6497 VMX_EPT_MT_EPTE_SHIFT;
6498 else
6499 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6500 | VMX_EPT_IPAT_BIT;
6501
6502 return ret;
6503 }
6504
6505 static int vmx_get_lpage_level(void)
6506 {
6507 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6508 return PT_DIRECTORY_LEVEL;
6509 else
6510 /* For shadow and EPT supported 1GB page */
6511 return PT_PDPE_LEVEL;
6512 }
6513
6514 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6515 {
6516 struct kvm_cpuid_entry2 *best;
6517 struct vcpu_vmx *vmx = to_vmx(vcpu);
6518 u32 exec_control;
6519
6520 vmx->rdtscp_enabled = false;
6521 if (vmx_rdtscp_supported()) {
6522 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6523 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6524 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6525 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6526 vmx->rdtscp_enabled = true;
6527 else {
6528 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6529 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6530 exec_control);
6531 }
6532 }
6533 }
6534
6535 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6536 /* Exposing INVPCID only when PCID is exposed */
6537 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6538 if (vmx_invpcid_supported() &&
6539 best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6540 guest_cpuid_has_pcid(vcpu)) {
6541 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6542 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6543 exec_control);
6544 } else {
6545 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6546 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6547 exec_control);
6548 if (best)
6549 best->ecx &= ~bit(X86_FEATURE_INVPCID);
6550 }
6551 }
6552
6553 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6554 {
6555 if (func == 1 && nested)
6556 entry->ecx |= bit(X86_FEATURE_VMX);
6557 }
6558
6559 /*
6560 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6561 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6562 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6563 * guest in a way that will both be appropriate to L1's requests, and our
6564 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6565 * function also has additional necessary side-effects, like setting various
6566 * vcpu->arch fields.
6567 */
6568 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6569 {
6570 struct vcpu_vmx *vmx = to_vmx(vcpu);
6571 u32 exec_control;
6572
6573 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6574 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6575 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6576 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6577 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6578 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6579 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6580 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6581 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6582 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6583 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6584 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6585 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6586 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6587 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6588 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6589 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6590 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6591 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6592 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6593 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6594 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6595 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6596 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6597 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6598 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6599 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6600 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6601 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6602 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6603 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6604 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6605 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6606 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6607 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6608 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6609
6610 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6611 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6612 vmcs12->vm_entry_intr_info_field);
6613 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6614 vmcs12->vm_entry_exception_error_code);
6615 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6616 vmcs12->vm_entry_instruction_len);
6617 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6618 vmcs12->guest_interruptibility_info);
6619 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6620 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6621 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6622 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6623 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6624 vmcs12->guest_pending_dbg_exceptions);
6625 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6626 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6627
6628 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6629
6630 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6631 (vmcs_config.pin_based_exec_ctrl |
6632 vmcs12->pin_based_vm_exec_control));
6633
6634 /*
6635 * Whether page-faults are trapped is determined by a combination of
6636 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6637 * If enable_ept, L0 doesn't care about page faults and we should
6638 * set all of these to L1's desires. However, if !enable_ept, L0 does
6639 * care about (at least some) page faults, and because it is not easy
6640 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6641 * to exit on each and every L2 page fault. This is done by setting
6642 * MASK=MATCH=0 and (see below) EB.PF=1.
6643 * Note that below we don't need special code to set EB.PF beyond the
6644 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6645 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6646 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6647 *
6648 * A problem with this approach (when !enable_ept) is that L1 may be
6649 * injected with more page faults than it asked for. This could have
6650 * caused problems, but in practice existing hypervisors don't care.
6651 * To fix this, we will need to emulate the PFEC checking (on the L1
6652 * page tables), using walk_addr(), when injecting PFs to L1.
6653 */
6654 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6655 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6656 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6657 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6658
6659 if (cpu_has_secondary_exec_ctrls()) {
6660 u32 exec_control = vmx_secondary_exec_control(vmx);
6661 if (!vmx->rdtscp_enabled)
6662 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6663 /* Take the following fields only from vmcs12 */
6664 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6665 if (nested_cpu_has(vmcs12,
6666 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6667 exec_control |= vmcs12->secondary_vm_exec_control;
6668
6669 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6670 /*
6671 * Translate L1 physical address to host physical
6672 * address for vmcs02. Keep the page pinned, so this
6673 * physical address remains valid. We keep a reference
6674 * to it so we can release it later.
6675 */
6676 if (vmx->nested.apic_access_page) /* shouldn't happen */
6677 nested_release_page(vmx->nested.apic_access_page);
6678 vmx->nested.apic_access_page =
6679 nested_get_page(vcpu, vmcs12->apic_access_addr);
6680 /*
6681 * If translation failed, no matter: This feature asks
6682 * to exit when accessing the given address, and if it
6683 * can never be accessed, this feature won't do
6684 * anything anyway.
6685 */
6686 if (!vmx->nested.apic_access_page)
6687 exec_control &=
6688 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6689 else
6690 vmcs_write64(APIC_ACCESS_ADDR,
6691 page_to_phys(vmx->nested.apic_access_page));
6692 }
6693
6694 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6695 }
6696
6697
6698 /*
6699 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6700 * Some constant fields are set here by vmx_set_constant_host_state().
6701 * Other fields are different per CPU, and will be set later when
6702 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6703 */
6704 vmx_set_constant_host_state();
6705
6706 /*
6707 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6708 * entry, but only if the current (host) sp changed from the value
6709 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6710 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6711 * here we just force the write to happen on entry.
6712 */
6713 vmx->host_rsp = 0;
6714
6715 exec_control = vmx_exec_control(vmx); /* L0's desires */
6716 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6717 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6718 exec_control &= ~CPU_BASED_TPR_SHADOW;
6719 exec_control |= vmcs12->cpu_based_vm_exec_control;
6720 /*
6721 * Merging of IO and MSR bitmaps not currently supported.
6722 * Rather, exit every time.
6723 */
6724 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6725 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6726 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6727
6728 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6729
6730 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6731 * bitwise-or of what L1 wants to trap for L2, and what we want to
6732 * trap. Note that CR0.TS also needs updating - we do this later.
6733 */
6734 update_exception_bitmap(vcpu);
6735 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6736 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6737
6738 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6739 vmcs_write32(VM_EXIT_CONTROLS,
6740 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6741 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6742 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6743
6744 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6745 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6746 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6747 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6748
6749
6750 set_cr4_guest_host_mask(vmx);
6751
6752 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6753 vmcs_write64(TSC_OFFSET,
6754 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6755 else
6756 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6757
6758 if (enable_vpid) {
6759 /*
6760 * Trivially support vpid by letting L2s share their parent
6761 * L1's vpid. TODO: move to a more elaborate solution, giving
6762 * each L2 its own vpid and exposing the vpid feature to L1.
6763 */
6764 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6765 vmx_flush_tlb(vcpu);
6766 }
6767
6768 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6769 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6770 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6771 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6772 else
6773 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6774 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6775 vmx_set_efer(vcpu, vcpu->arch.efer);
6776
6777 /*
6778 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6779 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6780 * The CR0_READ_SHADOW is what L2 should have expected to read given
6781 * the specifications by L1; It's not enough to take
6782 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6783 * have more bits than L1 expected.
6784 */
6785 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6786 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6787
6788 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6789 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6790
6791 /* shadow page tables on either EPT or shadow page tables */
6792 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6793 kvm_mmu_reset_context(vcpu);
6794
6795 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6796 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6797 }
6798
6799 /*
6800 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6801 * for running an L2 nested guest.
6802 */
6803 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6804 {
6805 struct vmcs12 *vmcs12;
6806 struct vcpu_vmx *vmx = to_vmx(vcpu);
6807 int cpu;
6808 struct loaded_vmcs *vmcs02;
6809
6810 if (!nested_vmx_check_permission(vcpu) ||
6811 !nested_vmx_check_vmcs12(vcpu))
6812 return 1;
6813
6814 skip_emulated_instruction(vcpu);
6815 vmcs12 = get_vmcs12(vcpu);
6816
6817 /*
6818 * The nested entry process starts with enforcing various prerequisites
6819 * on vmcs12 as required by the Intel SDM, and act appropriately when
6820 * they fail: As the SDM explains, some conditions should cause the
6821 * instruction to fail, while others will cause the instruction to seem
6822 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6823 * To speed up the normal (success) code path, we should avoid checking
6824 * for misconfigurations which will anyway be caught by the processor
6825 * when using the merged vmcs02.
6826 */
6827 if (vmcs12->launch_state == launch) {
6828 nested_vmx_failValid(vcpu,
6829 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6830 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6831 return 1;
6832 }
6833
6834 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6835 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6836 /*TODO: Also verify bits beyond physical address width are 0*/
6837 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6838 return 1;
6839 }
6840
6841 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6842 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6843 /*TODO: Also verify bits beyond physical address width are 0*/
6844 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6845 return 1;
6846 }
6847
6848 if (vmcs12->vm_entry_msr_load_count > 0 ||
6849 vmcs12->vm_exit_msr_load_count > 0 ||
6850 vmcs12->vm_exit_msr_store_count > 0) {
6851 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6852 __func__);
6853 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6854 return 1;
6855 }
6856
6857 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6858 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6859 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6860 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6861 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6862 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6863 !vmx_control_verify(vmcs12->vm_exit_controls,
6864 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6865 !vmx_control_verify(vmcs12->vm_entry_controls,
6866 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6867 {
6868 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6869 return 1;
6870 }
6871
6872 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6873 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6874 nested_vmx_failValid(vcpu,
6875 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6876 return 1;
6877 }
6878
6879 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6880 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6881 nested_vmx_entry_failure(vcpu, vmcs12,
6882 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6883 return 1;
6884 }
6885 if (vmcs12->vmcs_link_pointer != -1ull) {
6886 nested_vmx_entry_failure(vcpu, vmcs12,
6887 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6888 return 1;
6889 }
6890
6891 /*
6892 * We're finally done with prerequisite checking, and can start with
6893 * the nested entry.
6894 */
6895
6896 vmcs02 = nested_get_current_vmcs02(vmx);
6897 if (!vmcs02)
6898 return -ENOMEM;
6899
6900 enter_guest_mode(vcpu);
6901
6902 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6903
6904 cpu = get_cpu();
6905 vmx->loaded_vmcs = vmcs02;
6906 vmx_vcpu_put(vcpu);
6907 vmx_vcpu_load(vcpu, cpu);
6908 vcpu->cpu = cpu;
6909 put_cpu();
6910
6911 vmcs12->launch_state = 1;
6912
6913 prepare_vmcs02(vcpu, vmcs12);
6914
6915 /*
6916 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6917 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6918 * returned as far as L1 is concerned. It will only return (and set
6919 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6920 */
6921 return 1;
6922 }
6923
6924 /*
6925 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6926 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6927 * This function returns the new value we should put in vmcs12.guest_cr0.
6928 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6929 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6930 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6931 * didn't trap the bit, because if L1 did, so would L0).
6932 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6933 * been modified by L2, and L1 knows it. So just leave the old value of
6934 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6935 * isn't relevant, because if L0 traps this bit it can set it to anything.
6936 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6937 * changed these bits, and therefore they need to be updated, but L0
6938 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6939 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6940 */
6941 static inline unsigned long
6942 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6943 {
6944 return
6945 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6946 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6947 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6948 vcpu->arch.cr0_guest_owned_bits));
6949 }
6950
6951 static inline unsigned long
6952 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6953 {
6954 return
6955 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6956 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6957 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6958 vcpu->arch.cr4_guest_owned_bits));
6959 }
6960
6961 /*
6962 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6963 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6964 * and this function updates it to reflect the changes to the guest state while
6965 * L2 was running (and perhaps made some exits which were handled directly by L0
6966 * without going back to L1), and to reflect the exit reason.
6967 * Note that we do not have to copy here all VMCS fields, just those that
6968 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6969 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6970 * which already writes to vmcs12 directly.
6971 */
6972 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6973 {
6974 /* update guest state fields: */
6975 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6976 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6977
6978 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6979 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6980 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6981 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6982
6983 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6984 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6985 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6986 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6987 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6988 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6989 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6990 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6991 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6992 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6993 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6994 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6995 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6996 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6997 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6998 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6999 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7000 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7001 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7002 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7003 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7004 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7005 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7006 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7007 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7008 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7009 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7010 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7011 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7012 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7013 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7014 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7015 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7016 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7017 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7018 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7019
7020 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7021 vmcs12->guest_interruptibility_info =
7022 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7023 vmcs12->guest_pending_dbg_exceptions =
7024 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7025
7026 /* TODO: These cannot have changed unless we have MSR bitmaps and
7027 * the relevant bit asks not to trap the change */
7028 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7029 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7030 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7031 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7032 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7033 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7034
7035 /* update exit information fields: */
7036
7037 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7038 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7039
7040 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7041 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7042 vmcs12->idt_vectoring_info_field =
7043 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7044 vmcs12->idt_vectoring_error_code =
7045 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7046 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7047 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7048
7049 /* clear vm-entry fields which are to be cleared on exit */
7050 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7051 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7052 }
7053
7054 /*
7055 * A part of what we need to when the nested L2 guest exits and we want to
7056 * run its L1 parent, is to reset L1's guest state to the host state specified
7057 * in vmcs12.
7058 * This function is to be called not only on normal nested exit, but also on
7059 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7060 * Failures During or After Loading Guest State").
7061 * This function should be called when the active VMCS is L1's (vmcs01).
7062 */
7063 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7064 {
7065 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7066 vcpu->arch.efer = vmcs12->host_ia32_efer;
7067 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7068 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7069 else
7070 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7071 vmx_set_efer(vcpu, vcpu->arch.efer);
7072
7073 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7074 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7075 /*
7076 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7077 * actually changed, because it depends on the current state of
7078 * fpu_active (which may have changed).
7079 * Note that vmx_set_cr0 refers to efer set above.
7080 */
7081 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7082 /*
7083 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7084 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7085 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7086 */
7087 update_exception_bitmap(vcpu);
7088 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7089 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7090
7091 /*
7092 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7093 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7094 */
7095 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7096 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7097
7098 /* shadow page tables on either EPT or shadow page tables */
7099 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7100 kvm_mmu_reset_context(vcpu);
7101
7102 if (enable_vpid) {
7103 /*
7104 * Trivially support vpid by letting L2s share their parent
7105 * L1's vpid. TODO: move to a more elaborate solution, giving
7106 * each L2 its own vpid and exposing the vpid feature to L1.
7107 */
7108 vmx_flush_tlb(vcpu);
7109 }
7110
7111
7112 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7113 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7114 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7115 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7116 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7117 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7118 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7119 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7120 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7121 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7122 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7123 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7124 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7125 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7126 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7127
7128 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7129 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7130 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7131 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7132 vmcs12->host_ia32_perf_global_ctrl);
7133 }
7134
7135 /*
7136 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7137 * and modify vmcs12 to make it see what it would expect to see there if
7138 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7139 */
7140 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7141 {
7142 struct vcpu_vmx *vmx = to_vmx(vcpu);
7143 int cpu;
7144 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7145
7146 leave_guest_mode(vcpu);
7147 prepare_vmcs12(vcpu, vmcs12);
7148
7149 cpu = get_cpu();
7150 vmx->loaded_vmcs = &vmx->vmcs01;
7151 vmx_vcpu_put(vcpu);
7152 vmx_vcpu_load(vcpu, cpu);
7153 vcpu->cpu = cpu;
7154 put_cpu();
7155
7156 /* if no vmcs02 cache requested, remove the one we used */
7157 if (VMCS02_POOL_SIZE == 0)
7158 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7159
7160 load_vmcs12_host_state(vcpu, vmcs12);
7161
7162 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7163 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7164
7165 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7166 vmx->host_rsp = 0;
7167
7168 /* Unpin physical memory we referred to in vmcs02 */
7169 if (vmx->nested.apic_access_page) {
7170 nested_release_page(vmx->nested.apic_access_page);
7171 vmx->nested.apic_access_page = 0;
7172 }
7173
7174 /*
7175 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7176 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7177 * success or failure flag accordingly.
7178 */
7179 if (unlikely(vmx->fail)) {
7180 vmx->fail = 0;
7181 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7182 } else
7183 nested_vmx_succeed(vcpu);
7184 }
7185
7186 /*
7187 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7188 * 23.7 "VM-entry failures during or after loading guest state" (this also
7189 * lists the acceptable exit-reason and exit-qualification parameters).
7190 * It should only be called before L2 actually succeeded to run, and when
7191 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7192 */
7193 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7194 struct vmcs12 *vmcs12,
7195 u32 reason, unsigned long qualification)
7196 {
7197 load_vmcs12_host_state(vcpu, vmcs12);
7198 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7199 vmcs12->exit_qualification = qualification;
7200 nested_vmx_succeed(vcpu);
7201 }
7202
7203 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7204 struct x86_instruction_info *info,
7205 enum x86_intercept_stage stage)
7206 {
7207 return X86EMUL_CONTINUE;
7208 }
7209
7210 static struct kvm_x86_ops vmx_x86_ops = {
7211 .cpu_has_kvm_support = cpu_has_kvm_support,
7212 .disabled_by_bios = vmx_disabled_by_bios,
7213 .hardware_setup = hardware_setup,
7214 .hardware_unsetup = hardware_unsetup,
7215 .check_processor_compatibility = vmx_check_processor_compat,
7216 .hardware_enable = hardware_enable,
7217 .hardware_disable = hardware_disable,
7218 .cpu_has_accelerated_tpr = report_flexpriority,
7219
7220 .vcpu_create = vmx_create_vcpu,
7221 .vcpu_free = vmx_free_vcpu,
7222 .vcpu_reset = vmx_vcpu_reset,
7223
7224 .prepare_guest_switch = vmx_save_host_state,
7225 .vcpu_load = vmx_vcpu_load,
7226 .vcpu_put = vmx_vcpu_put,
7227
7228 .update_db_bp_intercept = update_exception_bitmap,
7229 .get_msr = vmx_get_msr,
7230 .set_msr = vmx_set_msr,
7231 .get_segment_base = vmx_get_segment_base,
7232 .get_segment = vmx_get_segment,
7233 .set_segment = vmx_set_segment,
7234 .get_cpl = vmx_get_cpl,
7235 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7236 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7237 .decache_cr3 = vmx_decache_cr3,
7238 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7239 .set_cr0 = vmx_set_cr0,
7240 .set_cr3 = vmx_set_cr3,
7241 .set_cr4 = vmx_set_cr4,
7242 .set_efer = vmx_set_efer,
7243 .get_idt = vmx_get_idt,
7244 .set_idt = vmx_set_idt,
7245 .get_gdt = vmx_get_gdt,
7246 .set_gdt = vmx_set_gdt,
7247 .set_dr7 = vmx_set_dr7,
7248 .cache_reg = vmx_cache_reg,
7249 .get_rflags = vmx_get_rflags,
7250 .set_rflags = vmx_set_rflags,
7251 .fpu_activate = vmx_fpu_activate,
7252 .fpu_deactivate = vmx_fpu_deactivate,
7253
7254 .tlb_flush = vmx_flush_tlb,
7255
7256 .run = vmx_vcpu_run,
7257 .handle_exit = vmx_handle_exit,
7258 .skip_emulated_instruction = skip_emulated_instruction,
7259 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7260 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7261 .patch_hypercall = vmx_patch_hypercall,
7262 .set_irq = vmx_inject_irq,
7263 .set_nmi = vmx_inject_nmi,
7264 .queue_exception = vmx_queue_exception,
7265 .cancel_injection = vmx_cancel_injection,
7266 .interrupt_allowed = vmx_interrupt_allowed,
7267 .nmi_allowed = vmx_nmi_allowed,
7268 .get_nmi_mask = vmx_get_nmi_mask,
7269 .set_nmi_mask = vmx_set_nmi_mask,
7270 .enable_nmi_window = enable_nmi_window,
7271 .enable_irq_window = enable_irq_window,
7272 .update_cr8_intercept = update_cr8_intercept,
7273
7274 .set_tss_addr = vmx_set_tss_addr,
7275 .get_tdp_level = get_ept_level,
7276 .get_mt_mask = vmx_get_mt_mask,
7277
7278 .get_exit_info = vmx_get_exit_info,
7279
7280 .get_lpage_level = vmx_get_lpage_level,
7281
7282 .cpuid_update = vmx_cpuid_update,
7283
7284 .rdtscp_supported = vmx_rdtscp_supported,
7285 .invpcid_supported = vmx_invpcid_supported,
7286
7287 .set_supported_cpuid = vmx_set_supported_cpuid,
7288
7289 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7290
7291 .set_tsc_khz = vmx_set_tsc_khz,
7292 .write_tsc_offset = vmx_write_tsc_offset,
7293 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7294 .compute_tsc_offset = vmx_compute_tsc_offset,
7295 .read_l1_tsc = vmx_read_l1_tsc,
7296
7297 .set_tdp_cr3 = vmx_set_cr3,
7298
7299 .check_intercept = vmx_check_intercept,
7300 };
7301
7302 static int __init vmx_init(void)
7303 {
7304 int r, i;
7305
7306 rdmsrl_safe(MSR_EFER, &host_efer);
7307
7308 for (i = 0; i < NR_VMX_MSR; ++i)
7309 kvm_define_shared_msr(i, vmx_msr_index[i]);
7310
7311 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7312 if (!vmx_io_bitmap_a)
7313 return -ENOMEM;
7314
7315 r = -ENOMEM;
7316
7317 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7318 if (!vmx_io_bitmap_b)
7319 goto out;
7320
7321 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7322 if (!vmx_msr_bitmap_legacy)
7323 goto out1;
7324
7325
7326 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7327 if (!vmx_msr_bitmap_longmode)
7328 goto out2;
7329
7330
7331 /*
7332 * Allow direct access to the PC debug port (it is often used for I/O
7333 * delays, but the vmexits simply slow things down).
7334 */
7335 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7336 clear_bit(0x80, vmx_io_bitmap_a);
7337
7338 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7339
7340 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7341 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7342
7343 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7344
7345 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7346 __alignof__(struct vcpu_vmx), THIS_MODULE);
7347 if (r)
7348 goto out3;
7349
7350 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7351 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7352 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7353 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7354 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7355 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7356
7357 if (enable_ept) {
7358 kvm_mmu_set_mask_ptes(0ull,
7359 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7360 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7361 0ull, VMX_EPT_EXECUTABLE_MASK);
7362 ept_set_mmio_spte_mask();
7363 kvm_enable_tdp();
7364 } else
7365 kvm_disable_tdp();
7366
7367 return 0;
7368
7369 out3:
7370 free_page((unsigned long)vmx_msr_bitmap_longmode);
7371 out2:
7372 free_page((unsigned long)vmx_msr_bitmap_legacy);
7373 out1:
7374 free_page((unsigned long)vmx_io_bitmap_b);
7375 out:
7376 free_page((unsigned long)vmx_io_bitmap_a);
7377 return r;
7378 }
7379
7380 static void __exit vmx_exit(void)
7381 {
7382 free_page((unsigned long)vmx_msr_bitmap_legacy);
7383 free_page((unsigned long)vmx_msr_bitmap_longmode);
7384 free_page((unsigned long)vmx_io_bitmap_b);
7385 free_page((unsigned long)vmx_io_bitmap_a);
7386
7387 kvm_exit();
7388 }
7389
7390 module_init(vmx_init)
7391 module_exit(vmx_exit)
Linux kernel - Deliverables
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