2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
135 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
136 module_param(ple_gap
, int, S_IRUGO
);
138 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
139 module_param(ple_window
, int, S_IRUGO
);
141 /* Default doubles per-vcpu window every exit. */
142 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
143 module_param(ple_window_grow
, int, S_IRUGO
);
145 /* Default resets per-vcpu window every exit to ple_window. */
146 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
147 module_param(ple_window_shrink
, int, S_IRUGO
);
149 /* Default is to compute the maximum so we can never overflow. */
150 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
151 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
152 module_param(ple_window_max
, int, S_IRUGO
);
154 extern const ulong vmx_return
;
156 #define NR_AUTOLOAD_MSRS 8
157 #define VMCS02_POOL_SIZE 1
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
174 struct list_head loaded_vmcss_on_cpu_link
;
177 struct shared_msr_entry
{
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
196 typedef u64 natural_width
;
197 struct __packed vmcs12
{
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
204 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding
[7]; /* room for future expansion */
210 u64 vm_exit_msr_store_addr
;
211 u64 vm_exit_msr_load_addr
;
212 u64 vm_entry_msr_load_addr
;
214 u64 virtual_apic_page_addr
;
215 u64 apic_access_addr
;
217 u64 guest_physical_address
;
218 u64 vmcs_link_pointer
;
219 u64 guest_ia32_debugctl
;
222 u64 guest_ia32_perf_global_ctrl
;
230 u64 host_ia32_perf_global_ctrl
;
231 u64 padding64
[8]; /* room for future expansion */
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
238 natural_width cr0_guest_host_mask
;
239 natural_width cr4_guest_host_mask
;
240 natural_width cr0_read_shadow
;
241 natural_width cr4_read_shadow
;
242 natural_width cr3_target_value0
;
243 natural_width cr3_target_value1
;
244 natural_width cr3_target_value2
;
245 natural_width cr3_target_value3
;
246 natural_width exit_qualification
;
247 natural_width guest_linear_address
;
248 natural_width guest_cr0
;
249 natural_width guest_cr3
;
250 natural_width guest_cr4
;
251 natural_width guest_es_base
;
252 natural_width guest_cs_base
;
253 natural_width guest_ss_base
;
254 natural_width guest_ds_base
;
255 natural_width guest_fs_base
;
256 natural_width guest_gs_base
;
257 natural_width guest_ldtr_base
;
258 natural_width guest_tr_base
;
259 natural_width guest_gdtr_base
;
260 natural_width guest_idtr_base
;
261 natural_width guest_dr7
;
262 natural_width guest_rsp
;
263 natural_width guest_rip
;
264 natural_width guest_rflags
;
265 natural_width guest_pending_dbg_exceptions
;
266 natural_width guest_sysenter_esp
;
267 natural_width guest_sysenter_eip
;
268 natural_width host_cr0
;
269 natural_width host_cr3
;
270 natural_width host_cr4
;
271 natural_width host_fs_base
;
272 natural_width host_gs_base
;
273 natural_width host_tr_base
;
274 natural_width host_gdtr_base
;
275 natural_width host_idtr_base
;
276 natural_width host_ia32_sysenter_esp
;
277 natural_width host_ia32_sysenter_eip
;
278 natural_width host_rsp
;
279 natural_width host_rip
;
280 natural_width paddingl
[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control
;
282 u32 cpu_based_vm_exec_control
;
283 u32 exception_bitmap
;
284 u32 page_fault_error_code_mask
;
285 u32 page_fault_error_code_match
;
286 u32 cr3_target_count
;
287 u32 vm_exit_controls
;
288 u32 vm_exit_msr_store_count
;
289 u32 vm_exit_msr_load_count
;
290 u32 vm_entry_controls
;
291 u32 vm_entry_msr_load_count
;
292 u32 vm_entry_intr_info_field
;
293 u32 vm_entry_exception_error_code
;
294 u32 vm_entry_instruction_len
;
296 u32 secondary_vm_exec_control
;
297 u32 vm_instruction_error
;
299 u32 vm_exit_intr_info
;
300 u32 vm_exit_intr_error_code
;
301 u32 idt_vectoring_info_field
;
302 u32 idt_vectoring_error_code
;
303 u32 vm_exit_instruction_len
;
304 u32 vmx_instruction_info
;
311 u32 guest_ldtr_limit
;
313 u32 guest_gdtr_limit
;
314 u32 guest_idtr_limit
;
315 u32 guest_es_ar_bytes
;
316 u32 guest_cs_ar_bytes
;
317 u32 guest_ss_ar_bytes
;
318 u32 guest_ds_ar_bytes
;
319 u32 guest_fs_ar_bytes
;
320 u32 guest_gs_ar_bytes
;
321 u32 guest_ldtr_ar_bytes
;
322 u32 guest_tr_ar_bytes
;
323 u32 guest_interruptibility_info
;
324 u32 guest_activity_state
;
325 u32 guest_sysenter_cs
;
326 u32 host_ia32_sysenter_cs
;
327 u32 vmx_preemption_timer_value
;
328 u32 padding32
[7]; /* room for future expansion */
329 u16 virtual_processor_id
;
330 u16 guest_es_selector
;
331 u16 guest_cs_selector
;
332 u16 guest_ss_selector
;
333 u16 guest_ds_selector
;
334 u16 guest_fs_selector
;
335 u16 guest_gs_selector
;
336 u16 guest_ldtr_selector
;
337 u16 guest_tr_selector
;
338 u16 host_es_selector
;
339 u16 host_cs_selector
;
340 u16 host_ss_selector
;
341 u16 host_ds_selector
;
342 u16 host_fs_selector
;
343 u16 host_gs_selector
;
344 u16 host_tr_selector
;
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
352 #define VMCS12_REVISION 0x11e57ed0
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
359 #define VMCS12_SIZE 0x1000
361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
363 struct list_head list
;
365 struct loaded_vmcs vmcs02
;
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
373 /* Has the level1 guest done vmxon? */
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
379 /* The host-usable pointer to the above */
380 struct page
*current_vmcs12_page
;
381 struct vmcs12
*current_vmcs12
;
382 struct vmcs
*current_shadow_vmcs
;
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
387 bool sync_shadow_vmcs
;
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool
;
392 u64 vmcs01_tsc_offset
;
393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending
;
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
399 struct page
*apic_access_page
;
400 u64 msr_ia32_feature_control
;
402 struct hrtimer preemption_timer
;
403 bool preemption_timer_expired
;
405 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
409 #define POSTED_INTR_ON 0
410 /* Posted-Interrupt Descriptor */
412 u32 pir
[8]; /* Posted interrupt requested */
413 u32 control
; /* bit 0 of control is outstanding notification bit */
417 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
419 return test_and_set_bit(POSTED_INTR_ON
,
420 (unsigned long *)&pi_desc
->control
);
423 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
425 return test_and_clear_bit(POSTED_INTR_ON
,
426 (unsigned long *)&pi_desc
->control
);
429 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
431 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
435 struct kvm_vcpu vcpu
;
436 unsigned long host_rsp
;
438 bool nmi_known_unmasked
;
440 u32 idt_vectoring_info
;
442 struct shared_msr_entry
*guest_msrs
;
445 unsigned long host_idt_base
;
447 u64 msr_host_kernel_gs_base
;
448 u64 msr_guest_kernel_gs_base
;
450 u32 vm_entry_controls_shadow
;
451 u32 vm_exit_controls_shadow
;
453 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
454 * non-nested (L1) guest, it always points to vmcs01. For a nested
455 * guest (L2), it points to a different VMCS.
457 struct loaded_vmcs vmcs01
;
458 struct loaded_vmcs
*loaded_vmcs
;
459 bool __launched
; /* temporary, used in vmx_vcpu_run */
460 struct msr_autoload
{
462 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
463 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
467 u16 fs_sel
, gs_sel
, ldt_sel
;
471 int gs_ldt_reload_needed
;
472 int fs_reload_needed
;
473 u64 msr_host_bndcfgs
;
478 struct kvm_segment segs
[8];
481 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
482 struct kvm_save_segment
{
490 bool emulation_required
;
492 /* Support for vnmi-less CPUs */
493 int soft_vnmi_blocked
;
495 s64 vnmi_blocked_time
;
500 /* Posted interrupt descriptor */
501 struct pi_desc pi_desc
;
503 /* Support for a guest hypervisor (nested VMX) */
504 struct nested_vmx nested
;
506 /* Dynamic PLE window. */
508 bool ple_window_dirty
;
511 enum segment_cache_field
{
520 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
522 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
525 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
526 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
527 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
528 [number##_HIGH] = VMCS12_OFFSET(name)+4
531 static unsigned long shadow_read_only_fields
[] = {
533 * We do NOT shadow fields that are modified when L0
534 * traps and emulates any vmx instruction (e.g. VMPTRLD,
535 * VMXON...) executed by L1.
536 * For example, VM_INSTRUCTION_ERROR is read
537 * by L1 if a vmx instruction fails (part of the error path).
538 * Note the code assumes this logic. If for some reason
539 * we start shadowing these fields then we need to
540 * force a shadow sync when L0 emulates vmx instructions
541 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
542 * by nested_vmx_failValid)
546 VM_EXIT_INSTRUCTION_LEN
,
547 IDT_VECTORING_INFO_FIELD
,
548 IDT_VECTORING_ERROR_CODE
,
549 VM_EXIT_INTR_ERROR_CODE
,
551 GUEST_LINEAR_ADDRESS
,
552 GUEST_PHYSICAL_ADDRESS
554 static int max_shadow_read_only_fields
=
555 ARRAY_SIZE(shadow_read_only_fields
);
557 static unsigned long shadow_read_write_fields
[] = {
563 GUEST_INTERRUPTIBILITY_INFO
,
576 CPU_BASED_VM_EXEC_CONTROL
,
577 VM_ENTRY_EXCEPTION_ERROR_CODE
,
578 VM_ENTRY_INTR_INFO_FIELD
,
579 VM_ENTRY_INSTRUCTION_LEN
,
580 VM_ENTRY_EXCEPTION_ERROR_CODE
,
586 static int max_shadow_read_write_fields
=
587 ARRAY_SIZE(shadow_read_write_fields
);
589 static const unsigned short vmcs_field_to_offset_table
[] = {
590 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
591 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
592 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
593 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
594 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
595 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
596 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
597 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
598 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
599 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
600 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
601 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
602 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
603 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
604 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
605 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
606 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
607 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
608 FIELD64(MSR_BITMAP
, msr_bitmap
),
609 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
610 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
611 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
612 FIELD64(TSC_OFFSET
, tsc_offset
),
613 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
614 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
615 FIELD64(EPT_POINTER
, ept_pointer
),
616 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
617 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
618 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
619 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
620 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
621 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
622 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
623 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
624 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
625 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
626 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
627 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
628 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
629 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
630 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
631 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
632 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
633 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
634 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
635 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
636 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
637 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
638 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
639 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
640 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
641 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
642 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
643 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
644 FIELD(TPR_THRESHOLD
, tpr_threshold
),
645 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
646 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
647 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
648 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
649 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
650 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
651 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
652 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
653 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
654 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
655 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
656 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
657 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
658 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
659 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
660 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
661 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
662 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
663 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
664 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
665 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
666 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
667 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
668 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
669 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
670 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
671 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
672 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
673 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
674 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
675 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
676 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
677 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
678 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
679 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
680 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
681 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
682 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
683 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
684 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
685 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
686 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
687 FIELD(GUEST_CR0
, guest_cr0
),
688 FIELD(GUEST_CR3
, guest_cr3
),
689 FIELD(GUEST_CR4
, guest_cr4
),
690 FIELD(GUEST_ES_BASE
, guest_es_base
),
691 FIELD(GUEST_CS_BASE
, guest_cs_base
),
692 FIELD(GUEST_SS_BASE
, guest_ss_base
),
693 FIELD(GUEST_DS_BASE
, guest_ds_base
),
694 FIELD(GUEST_FS_BASE
, guest_fs_base
),
695 FIELD(GUEST_GS_BASE
, guest_gs_base
),
696 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
697 FIELD(GUEST_TR_BASE
, guest_tr_base
),
698 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
699 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
700 FIELD(GUEST_DR7
, guest_dr7
),
701 FIELD(GUEST_RSP
, guest_rsp
),
702 FIELD(GUEST_RIP
, guest_rip
),
703 FIELD(GUEST_RFLAGS
, guest_rflags
),
704 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
705 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
706 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
707 FIELD(HOST_CR0
, host_cr0
),
708 FIELD(HOST_CR3
, host_cr3
),
709 FIELD(HOST_CR4
, host_cr4
),
710 FIELD(HOST_FS_BASE
, host_fs_base
),
711 FIELD(HOST_GS_BASE
, host_gs_base
),
712 FIELD(HOST_TR_BASE
, host_tr_base
),
713 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
714 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
715 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
716 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
717 FIELD(HOST_RSP
, host_rsp
),
718 FIELD(HOST_RIP
, host_rip
),
720 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
722 static inline short vmcs_field_to_offset(unsigned long field
)
724 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
726 return vmcs_field_to_offset_table
[field
];
729 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
731 return to_vmx(vcpu
)->nested
.current_vmcs12
;
734 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
736 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
737 if (is_error_page(page
))
743 static void nested_release_page(struct page
*page
)
745 kvm_release_page_dirty(page
);
748 static void nested_release_page_clean(struct page
*page
)
750 kvm_release_page_clean(page
);
753 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
754 static u64
construct_eptp(unsigned long root_hpa
);
755 static void kvm_cpu_vmxon(u64 addr
);
756 static void kvm_cpu_vmxoff(void);
757 static bool vmx_mpx_supported(void);
758 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
759 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
760 struct kvm_segment
*var
, int seg
);
761 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
762 struct kvm_segment
*var
, int seg
);
763 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
764 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
765 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
766 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
767 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
769 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
770 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
772 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
773 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
775 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
776 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
778 static unsigned long *vmx_io_bitmap_a
;
779 static unsigned long *vmx_io_bitmap_b
;
780 static unsigned long *vmx_msr_bitmap_legacy
;
781 static unsigned long *vmx_msr_bitmap_longmode
;
782 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
783 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
784 static unsigned long *vmx_vmread_bitmap
;
785 static unsigned long *vmx_vmwrite_bitmap
;
787 static bool cpu_has_load_ia32_efer
;
788 static bool cpu_has_load_perf_global_ctrl
;
790 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
791 static DEFINE_SPINLOCK(vmx_vpid_lock
);
793 static struct vmcs_config
{
797 u32 pin_based_exec_ctrl
;
798 u32 cpu_based_exec_ctrl
;
799 u32 cpu_based_2nd_exec_ctrl
;
804 static struct vmx_capability
{
809 #define VMX_SEGMENT_FIELD(seg) \
810 [VCPU_SREG_##seg] = { \
811 .selector = GUEST_##seg##_SELECTOR, \
812 .base = GUEST_##seg##_BASE, \
813 .limit = GUEST_##seg##_LIMIT, \
814 .ar_bytes = GUEST_##seg##_AR_BYTES, \
817 static const struct kvm_vmx_segment_field
{
822 } kvm_vmx_segment_fields
[] = {
823 VMX_SEGMENT_FIELD(CS
),
824 VMX_SEGMENT_FIELD(DS
),
825 VMX_SEGMENT_FIELD(ES
),
826 VMX_SEGMENT_FIELD(FS
),
827 VMX_SEGMENT_FIELD(GS
),
828 VMX_SEGMENT_FIELD(SS
),
829 VMX_SEGMENT_FIELD(TR
),
830 VMX_SEGMENT_FIELD(LDTR
),
833 static u64 host_efer
;
835 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
838 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
839 * away by decrementing the array size.
841 static const u32 vmx_msr_index
[] = {
843 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
845 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
848 static inline bool is_page_fault(u32 intr_info
)
850 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
851 INTR_INFO_VALID_MASK
)) ==
852 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
855 static inline bool is_no_device(u32 intr_info
)
857 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
858 INTR_INFO_VALID_MASK
)) ==
859 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
862 static inline bool is_invalid_opcode(u32 intr_info
)
864 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
865 INTR_INFO_VALID_MASK
)) ==
866 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
869 static inline bool is_external_interrupt(u32 intr_info
)
871 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
872 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
875 static inline bool is_machine_check(u32 intr_info
)
877 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
878 INTR_INFO_VALID_MASK
)) ==
879 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
882 static inline bool cpu_has_vmx_msr_bitmap(void)
884 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
887 static inline bool cpu_has_vmx_tpr_shadow(void)
889 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
892 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
894 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
897 static inline bool cpu_has_secondary_exec_ctrls(void)
899 return vmcs_config
.cpu_based_exec_ctrl
&
900 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
903 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
905 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
906 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
909 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
911 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
912 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
915 static inline bool cpu_has_vmx_apic_register_virt(void)
917 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
918 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
921 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
923 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
924 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
927 static inline bool cpu_has_vmx_posted_intr(void)
929 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
932 static inline bool cpu_has_vmx_apicv(void)
934 return cpu_has_vmx_apic_register_virt() &&
935 cpu_has_vmx_virtual_intr_delivery() &&
936 cpu_has_vmx_posted_intr();
939 static inline bool cpu_has_vmx_flexpriority(void)
941 return cpu_has_vmx_tpr_shadow() &&
942 cpu_has_vmx_virtualize_apic_accesses();
945 static inline bool cpu_has_vmx_ept_execute_only(void)
947 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
950 static inline bool cpu_has_vmx_eptp_uncacheable(void)
952 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
955 static inline bool cpu_has_vmx_eptp_writeback(void)
957 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
960 static inline bool cpu_has_vmx_ept_2m_page(void)
962 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
965 static inline bool cpu_has_vmx_ept_1g_page(void)
967 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
970 static inline bool cpu_has_vmx_ept_4levels(void)
972 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
975 static inline bool cpu_has_vmx_ept_ad_bits(void)
977 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
980 static inline bool cpu_has_vmx_invept_context(void)
982 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
985 static inline bool cpu_has_vmx_invept_global(void)
987 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
990 static inline bool cpu_has_vmx_invvpid_single(void)
992 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
995 static inline bool cpu_has_vmx_invvpid_global(void)
997 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1000 static inline bool cpu_has_vmx_ept(void)
1002 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1003 SECONDARY_EXEC_ENABLE_EPT
;
1006 static inline bool cpu_has_vmx_unrestricted_guest(void)
1008 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1009 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1012 static inline bool cpu_has_vmx_ple(void)
1014 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1015 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1018 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1020 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1023 static inline bool cpu_has_vmx_vpid(void)
1025 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1026 SECONDARY_EXEC_ENABLE_VPID
;
1029 static inline bool cpu_has_vmx_rdtscp(void)
1031 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1032 SECONDARY_EXEC_RDTSCP
;
1035 static inline bool cpu_has_vmx_invpcid(void)
1037 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1038 SECONDARY_EXEC_ENABLE_INVPCID
;
1041 static inline bool cpu_has_virtual_nmis(void)
1043 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1046 static inline bool cpu_has_vmx_wbinvd_exit(void)
1048 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1049 SECONDARY_EXEC_WBINVD_EXITING
;
1052 static inline bool cpu_has_vmx_shadow_vmcs(void)
1055 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1056 /* check if the cpu supports writing r/o exit information fields */
1057 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1060 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1061 SECONDARY_EXEC_SHADOW_VMCS
;
1064 static inline bool report_flexpriority(void)
1066 return flexpriority_enabled
;
1069 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1071 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1074 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1076 return (vmcs12
->cpu_based_vm_exec_control
&
1077 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1078 (vmcs12
->secondary_vm_exec_control
& bit
);
1081 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1083 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1086 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1088 return vmcs12
->pin_based_vm_exec_control
&
1089 PIN_BASED_VMX_PREEMPTION_TIMER
;
1092 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1094 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1097 static inline bool is_exception(u32 intr_info
)
1099 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1100 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1103 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1105 unsigned long exit_qualification
);
1106 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1107 struct vmcs12
*vmcs12
,
1108 u32 reason
, unsigned long qualification
);
1110 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1114 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1115 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1120 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1126 } operand
= { vpid
, 0, gva
};
1128 asm volatile (__ex(ASM_VMX_INVVPID
)
1129 /* CF==1 or ZF==1 --> rc = -1 */
1130 "; ja 1f ; ud2 ; 1:"
1131 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1134 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1138 } operand
= {eptp
, gpa
};
1140 asm volatile (__ex(ASM_VMX_INVEPT
)
1141 /* CF==1 or ZF==1 --> rc = -1 */
1142 "; ja 1f ; ud2 ; 1:\n"
1143 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1146 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1150 i
= __find_msr_index(vmx
, msr
);
1152 return &vmx
->guest_msrs
[i
];
1156 static void vmcs_clear(struct vmcs
*vmcs
)
1158 u64 phys_addr
= __pa(vmcs
);
1161 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1162 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1165 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1169 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1171 vmcs_clear(loaded_vmcs
->vmcs
);
1172 loaded_vmcs
->cpu
= -1;
1173 loaded_vmcs
->launched
= 0;
1176 static void vmcs_load(struct vmcs
*vmcs
)
1178 u64 phys_addr
= __pa(vmcs
);
1181 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1182 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1185 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1191 * This bitmap is used to indicate whether the vmclear
1192 * operation is enabled on all cpus. All disabled by
1195 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1197 static inline void crash_enable_local_vmclear(int cpu
)
1199 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1202 static inline void crash_disable_local_vmclear(int cpu
)
1204 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1207 static inline int crash_local_vmclear_enabled(int cpu
)
1209 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1212 static void crash_vmclear_local_loaded_vmcss(void)
1214 int cpu
= raw_smp_processor_id();
1215 struct loaded_vmcs
*v
;
1217 if (!crash_local_vmclear_enabled(cpu
))
1220 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1221 loaded_vmcss_on_cpu_link
)
1222 vmcs_clear(v
->vmcs
);
1225 static inline void crash_enable_local_vmclear(int cpu
) { }
1226 static inline void crash_disable_local_vmclear(int cpu
) { }
1227 #endif /* CONFIG_KEXEC */
1229 static void __loaded_vmcs_clear(void *arg
)
1231 struct loaded_vmcs
*loaded_vmcs
= arg
;
1232 int cpu
= raw_smp_processor_id();
1234 if (loaded_vmcs
->cpu
!= cpu
)
1235 return; /* vcpu migration can race with cpu offline */
1236 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1237 per_cpu(current_vmcs
, cpu
) = NULL
;
1238 crash_disable_local_vmclear(cpu
);
1239 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1242 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1243 * is before setting loaded_vmcs->vcpu to -1 which is done in
1244 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1245 * then adds the vmcs into percpu list before it is deleted.
1249 loaded_vmcs_init(loaded_vmcs
);
1250 crash_enable_local_vmclear(cpu
);
1253 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1255 int cpu
= loaded_vmcs
->cpu
;
1258 smp_call_function_single(cpu
,
1259 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1262 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1267 if (cpu_has_vmx_invvpid_single())
1268 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1271 static inline void vpid_sync_vcpu_global(void)
1273 if (cpu_has_vmx_invvpid_global())
1274 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1277 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1279 if (cpu_has_vmx_invvpid_single())
1280 vpid_sync_vcpu_single(vmx
);
1282 vpid_sync_vcpu_global();
1285 static inline void ept_sync_global(void)
1287 if (cpu_has_vmx_invept_global())
1288 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1291 static inline void ept_sync_context(u64 eptp
)
1294 if (cpu_has_vmx_invept_context())
1295 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1301 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1303 unsigned long value
;
1305 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1306 : "=a"(value
) : "d"(field
) : "cc");
1310 static __always_inline u16
vmcs_read16(unsigned long field
)
1312 return vmcs_readl(field
);
1315 static __always_inline u32
vmcs_read32(unsigned long field
)
1317 return vmcs_readl(field
);
1320 static __always_inline u64
vmcs_read64(unsigned long field
)
1322 #ifdef CONFIG_X86_64
1323 return vmcs_readl(field
);
1325 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1329 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1331 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1332 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1336 static void vmcs_writel(unsigned long field
, unsigned long value
)
1340 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1341 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1342 if (unlikely(error
))
1343 vmwrite_error(field
, value
);
1346 static void vmcs_write16(unsigned long field
, u16 value
)
1348 vmcs_writel(field
, value
);
1351 static void vmcs_write32(unsigned long field
, u32 value
)
1353 vmcs_writel(field
, value
);
1356 static void vmcs_write64(unsigned long field
, u64 value
)
1358 vmcs_writel(field
, value
);
1359 #ifndef CONFIG_X86_64
1361 vmcs_writel(field
+1, value
>> 32);
1365 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1367 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1370 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1372 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1375 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1377 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1378 vmx
->vm_entry_controls_shadow
= val
;
1381 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1383 if (vmx
->vm_entry_controls_shadow
!= val
)
1384 vm_entry_controls_init(vmx
, val
);
1387 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1389 return vmx
->vm_entry_controls_shadow
;
1393 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1395 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1398 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1400 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1403 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1405 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1406 vmx
->vm_exit_controls_shadow
= val
;
1409 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1411 if (vmx
->vm_exit_controls_shadow
!= val
)
1412 vm_exit_controls_init(vmx
, val
);
1415 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1417 return vmx
->vm_exit_controls_shadow
;
1421 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1423 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1426 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1428 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1431 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1433 vmx
->segment_cache
.bitmask
= 0;
1436 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1440 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1442 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1443 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1444 vmx
->segment_cache
.bitmask
= 0;
1446 ret
= vmx
->segment_cache
.bitmask
& mask
;
1447 vmx
->segment_cache
.bitmask
|= mask
;
1451 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1453 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1455 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1456 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1460 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1462 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1464 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1465 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1469 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1471 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1473 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1474 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1478 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1480 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1482 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1483 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1487 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1491 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1492 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1493 if ((vcpu
->guest_debug
&
1494 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1495 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1496 eb
|= 1u << BP_VECTOR
;
1497 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1500 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1501 if (vcpu
->fpu_active
)
1502 eb
&= ~(1u << NM_VECTOR
);
1504 /* When we are running a nested L2 guest and L1 specified for it a
1505 * certain exception bitmap, we must trap the same exceptions and pass
1506 * them to L1. When running L2, we will only handle the exceptions
1507 * specified above if L1 did not want them.
1509 if (is_guest_mode(vcpu
))
1510 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1512 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1515 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1516 unsigned long entry
, unsigned long exit
)
1518 vm_entry_controls_clearbit(vmx
, entry
);
1519 vm_exit_controls_clearbit(vmx
, exit
);
1522 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1525 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1529 if (cpu_has_load_ia32_efer
) {
1530 clear_atomic_switch_msr_special(vmx
,
1531 VM_ENTRY_LOAD_IA32_EFER
,
1532 VM_EXIT_LOAD_IA32_EFER
);
1536 case MSR_CORE_PERF_GLOBAL_CTRL
:
1537 if (cpu_has_load_perf_global_ctrl
) {
1538 clear_atomic_switch_msr_special(vmx
,
1539 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1540 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1546 for (i
= 0; i
< m
->nr
; ++i
)
1547 if (m
->guest
[i
].index
== msr
)
1553 m
->guest
[i
] = m
->guest
[m
->nr
];
1554 m
->host
[i
] = m
->host
[m
->nr
];
1555 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1556 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1559 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1560 unsigned long entry
, unsigned long exit
,
1561 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1562 u64 guest_val
, u64 host_val
)
1564 vmcs_write64(guest_val_vmcs
, guest_val
);
1565 vmcs_write64(host_val_vmcs
, host_val
);
1566 vm_entry_controls_setbit(vmx
, entry
);
1567 vm_exit_controls_setbit(vmx
, exit
);
1570 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1571 u64 guest_val
, u64 host_val
)
1574 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1578 if (cpu_has_load_ia32_efer
) {
1579 add_atomic_switch_msr_special(vmx
,
1580 VM_ENTRY_LOAD_IA32_EFER
,
1581 VM_EXIT_LOAD_IA32_EFER
,
1584 guest_val
, host_val
);
1588 case MSR_CORE_PERF_GLOBAL_CTRL
:
1589 if (cpu_has_load_perf_global_ctrl
) {
1590 add_atomic_switch_msr_special(vmx
,
1591 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1592 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1593 GUEST_IA32_PERF_GLOBAL_CTRL
,
1594 HOST_IA32_PERF_GLOBAL_CTRL
,
1595 guest_val
, host_val
);
1601 for (i
= 0; i
< m
->nr
; ++i
)
1602 if (m
->guest
[i
].index
== msr
)
1605 if (i
== NR_AUTOLOAD_MSRS
) {
1606 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1607 "Can't add msr %x\n", msr
);
1609 } else if (i
== m
->nr
) {
1611 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1612 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1615 m
->guest
[i
].index
= msr
;
1616 m
->guest
[i
].value
= guest_val
;
1617 m
->host
[i
].index
= msr
;
1618 m
->host
[i
].value
= host_val
;
1621 static void reload_tss(void)
1624 * VT restores TR but not its size. Useless.
1626 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1627 struct desc_struct
*descs
;
1629 descs
= (void *)gdt
->address
;
1630 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1634 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1639 guest_efer
= vmx
->vcpu
.arch
.efer
;
1642 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1645 ignore_bits
= EFER_NX
| EFER_SCE
;
1646 #ifdef CONFIG_X86_64
1647 ignore_bits
|= EFER_LMA
| EFER_LME
;
1648 /* SCE is meaningful only in long mode on Intel */
1649 if (guest_efer
& EFER_LMA
)
1650 ignore_bits
&= ~(u64
)EFER_SCE
;
1652 guest_efer
&= ~ignore_bits
;
1653 guest_efer
|= host_efer
& ignore_bits
;
1654 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1655 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1657 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1658 /* On ept, can't emulate nx, and must switch nx atomically */
1659 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1660 guest_efer
= vmx
->vcpu
.arch
.efer
;
1661 if (!(guest_efer
& EFER_LMA
))
1662 guest_efer
&= ~EFER_LME
;
1663 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1670 static unsigned long segment_base(u16 selector
)
1672 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1673 struct desc_struct
*d
;
1674 unsigned long table_base
;
1677 if (!(selector
& ~3))
1680 table_base
= gdt
->address
;
1682 if (selector
& 4) { /* from ldt */
1683 u16 ldt_selector
= kvm_read_ldt();
1685 if (!(ldt_selector
& ~3))
1688 table_base
= segment_base(ldt_selector
);
1690 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1691 v
= get_desc_base(d
);
1692 #ifdef CONFIG_X86_64
1693 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1694 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1699 static inline unsigned long kvm_read_tr_base(void)
1702 asm("str %0" : "=g"(tr
));
1703 return segment_base(tr
);
1706 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1708 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1711 if (vmx
->host_state
.loaded
)
1714 vmx
->host_state
.loaded
= 1;
1716 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1717 * allow segment selectors with cpl > 0 or ti == 1.
1719 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1720 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1721 savesegment(fs
, vmx
->host_state
.fs_sel
);
1722 if (!(vmx
->host_state
.fs_sel
& 7)) {
1723 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1724 vmx
->host_state
.fs_reload_needed
= 0;
1726 vmcs_write16(HOST_FS_SELECTOR
, 0);
1727 vmx
->host_state
.fs_reload_needed
= 1;
1729 savesegment(gs
, vmx
->host_state
.gs_sel
);
1730 if (!(vmx
->host_state
.gs_sel
& 7))
1731 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1733 vmcs_write16(HOST_GS_SELECTOR
, 0);
1734 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1737 #ifdef CONFIG_X86_64
1738 savesegment(ds
, vmx
->host_state
.ds_sel
);
1739 savesegment(es
, vmx
->host_state
.es_sel
);
1742 #ifdef CONFIG_X86_64
1743 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1744 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1746 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1747 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1750 #ifdef CONFIG_X86_64
1751 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1752 if (is_long_mode(&vmx
->vcpu
))
1753 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1755 if (boot_cpu_has(X86_FEATURE_MPX
))
1756 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1757 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1758 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1759 vmx
->guest_msrs
[i
].data
,
1760 vmx
->guest_msrs
[i
].mask
);
1763 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1765 if (!vmx
->host_state
.loaded
)
1768 ++vmx
->vcpu
.stat
.host_state_reload
;
1769 vmx
->host_state
.loaded
= 0;
1770 #ifdef CONFIG_X86_64
1771 if (is_long_mode(&vmx
->vcpu
))
1772 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1774 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1775 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1776 #ifdef CONFIG_X86_64
1777 load_gs_index(vmx
->host_state
.gs_sel
);
1779 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1782 if (vmx
->host_state
.fs_reload_needed
)
1783 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1784 #ifdef CONFIG_X86_64
1785 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1786 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1787 loadsegment(es
, vmx
->host_state
.es_sel
);
1791 #ifdef CONFIG_X86_64
1792 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1794 if (vmx
->host_state
.msr_host_bndcfgs
)
1795 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1797 * If the FPU is not active (through the host task or
1798 * the guest vcpu), then restore the cr0.TS bit.
1800 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1802 load_gdt(&__get_cpu_var(host_gdt
));
1805 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1808 __vmx_load_host_state(vmx
);
1813 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1814 * vcpu mutex is already taken.
1816 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1818 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1819 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1822 kvm_cpu_vmxon(phys_addr
);
1823 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1824 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1826 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1827 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1828 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1831 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1832 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1833 unsigned long sysenter_esp
;
1835 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1836 local_irq_disable();
1837 crash_disable_local_vmclear(cpu
);
1840 * Read loaded_vmcs->cpu should be before fetching
1841 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1842 * See the comments in __loaded_vmcs_clear().
1846 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1847 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1848 crash_enable_local_vmclear(cpu
);
1852 * Linux uses per-cpu TSS and GDT, so set these when switching
1855 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1856 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1858 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1859 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1860 vmx
->loaded_vmcs
->cpu
= cpu
;
1864 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1866 __vmx_load_host_state(to_vmx(vcpu
));
1867 if (!vmm_exclusive
) {
1868 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1874 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1878 if (vcpu
->fpu_active
)
1880 vcpu
->fpu_active
= 1;
1881 cr0
= vmcs_readl(GUEST_CR0
);
1882 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1883 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1884 vmcs_writel(GUEST_CR0
, cr0
);
1885 update_exception_bitmap(vcpu
);
1886 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1887 if (is_guest_mode(vcpu
))
1888 vcpu
->arch
.cr0_guest_owned_bits
&=
1889 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1890 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1893 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1896 * Return the cr0 value that a nested guest would read. This is a combination
1897 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1898 * its hypervisor (cr0_read_shadow).
1900 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1902 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1903 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1905 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1907 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1908 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1911 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1913 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1914 * set this *before* calling this function.
1916 vmx_decache_cr0_guest_bits(vcpu
);
1917 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1918 update_exception_bitmap(vcpu
);
1919 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1920 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1921 if (is_guest_mode(vcpu
)) {
1923 * L1's specified read shadow might not contain the TS bit,
1924 * so now that we turned on shadowing of this bit, we need to
1925 * set this bit of the shadow. Like in nested_vmx_run we need
1926 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1927 * up-to-date here because we just decached cr0.TS (and we'll
1928 * only update vmcs12->guest_cr0 on nested exit).
1930 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1931 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1932 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1933 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1935 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1938 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1940 unsigned long rflags
, save_rflags
;
1942 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1943 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1944 rflags
= vmcs_readl(GUEST_RFLAGS
);
1945 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1946 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1947 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1948 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1950 to_vmx(vcpu
)->rflags
= rflags
;
1952 return to_vmx(vcpu
)->rflags
;
1955 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1957 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1958 to_vmx(vcpu
)->rflags
= rflags
;
1959 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1960 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1961 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1963 vmcs_writel(GUEST_RFLAGS
, rflags
);
1966 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1968 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1971 if (interruptibility
& GUEST_INTR_STATE_STI
)
1972 ret
|= KVM_X86_SHADOW_INT_STI
;
1973 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1974 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1979 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1981 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1982 u32 interruptibility
= interruptibility_old
;
1984 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1986 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1987 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1988 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1989 interruptibility
|= GUEST_INTR_STATE_STI
;
1991 if ((interruptibility
!= interruptibility_old
))
1992 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1995 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1999 rip
= kvm_rip_read(vcpu
);
2000 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2001 kvm_rip_write(vcpu
, rip
);
2003 /* skipping an emulated instruction also counts */
2004 vmx_set_interrupt_shadow(vcpu
, 0);
2008 * KVM wants to inject page-faults which it got to the guest. This function
2009 * checks whether in a nested guest, we need to inject them to L1 or L2.
2011 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2013 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2015 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2018 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2019 vmcs_read32(VM_EXIT_INTR_INFO
),
2020 vmcs_readl(EXIT_QUALIFICATION
));
2024 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2025 bool has_error_code
, u32 error_code
,
2028 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2029 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2031 if (!reinject
&& is_guest_mode(vcpu
) &&
2032 nested_vmx_check_exception(vcpu
, nr
))
2035 if (has_error_code
) {
2036 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2037 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2040 if (vmx
->rmode
.vm86_active
) {
2042 if (kvm_exception_is_soft(nr
))
2043 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2044 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2045 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2049 if (kvm_exception_is_soft(nr
)) {
2050 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2051 vmx
->vcpu
.arch
.event_exit_inst_len
);
2052 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2054 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2056 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2059 static bool vmx_rdtscp_supported(void)
2061 return cpu_has_vmx_rdtscp();
2064 static bool vmx_invpcid_supported(void)
2066 return cpu_has_vmx_invpcid() && enable_ept
;
2070 * Swap MSR entry in host/guest MSR entry array.
2072 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2074 struct shared_msr_entry tmp
;
2076 tmp
= vmx
->guest_msrs
[to
];
2077 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2078 vmx
->guest_msrs
[from
] = tmp
;
2081 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2083 unsigned long *msr_bitmap
;
2085 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2086 if (is_long_mode(vcpu
))
2087 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2089 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2091 if (is_long_mode(vcpu
))
2092 msr_bitmap
= vmx_msr_bitmap_longmode
;
2094 msr_bitmap
= vmx_msr_bitmap_legacy
;
2097 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2101 * Set up the vmcs to automatically save and restore system
2102 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2103 * mode, as fiddling with msrs is very expensive.
2105 static void setup_msrs(struct vcpu_vmx
*vmx
)
2107 int save_nmsrs
, index
;
2110 #ifdef CONFIG_X86_64
2111 if (is_long_mode(&vmx
->vcpu
)) {
2112 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2114 move_msr_up(vmx
, index
, save_nmsrs
++);
2115 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2117 move_msr_up(vmx
, index
, save_nmsrs
++);
2118 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2120 move_msr_up(vmx
, index
, save_nmsrs
++);
2121 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2122 if (index
>= 0 && vmx
->rdtscp_enabled
)
2123 move_msr_up(vmx
, index
, save_nmsrs
++);
2125 * MSR_STAR is only needed on long mode guests, and only
2126 * if efer.sce is enabled.
2128 index
= __find_msr_index(vmx
, MSR_STAR
);
2129 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2130 move_msr_up(vmx
, index
, save_nmsrs
++);
2133 index
= __find_msr_index(vmx
, MSR_EFER
);
2134 if (index
>= 0 && update_transition_efer(vmx
, index
))
2135 move_msr_up(vmx
, index
, save_nmsrs
++);
2137 vmx
->save_nmsrs
= save_nmsrs
;
2139 if (cpu_has_vmx_msr_bitmap())
2140 vmx_set_msr_bitmap(&vmx
->vcpu
);
2144 * reads and returns guest's timestamp counter "register"
2145 * guest_tsc = host_tsc + tsc_offset -- 21.3
2147 static u64
guest_read_tsc(void)
2149 u64 host_tsc
, tsc_offset
;
2152 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2153 return host_tsc
+ tsc_offset
;
2157 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2158 * counter, even if a nested guest (L2) is currently running.
2160 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2164 tsc_offset
= is_guest_mode(vcpu
) ?
2165 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2166 vmcs_read64(TSC_OFFSET
);
2167 return host_tsc
+ tsc_offset
;
2171 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2172 * software catchup for faster rates on slower CPUs.
2174 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2179 if (user_tsc_khz
> tsc_khz
) {
2180 vcpu
->arch
.tsc_catchup
= 1;
2181 vcpu
->arch
.tsc_always_catchup
= 1;
2183 WARN(1, "user requested TSC rate below hardware speed\n");
2186 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2188 return vmcs_read64(TSC_OFFSET
);
2192 * writes 'offset' into guest's timestamp counter offset register
2194 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2196 if (is_guest_mode(vcpu
)) {
2198 * We're here if L1 chose not to trap WRMSR to TSC. According
2199 * to the spec, this should set L1's TSC; The offset that L1
2200 * set for L2 remains unchanged, and still needs to be added
2201 * to the newly set TSC to get L2's TSC.
2203 struct vmcs12
*vmcs12
;
2204 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2205 /* recalculate vmcs02.TSC_OFFSET: */
2206 vmcs12
= get_vmcs12(vcpu
);
2207 vmcs_write64(TSC_OFFSET
, offset
+
2208 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2209 vmcs12
->tsc_offset
: 0));
2211 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2212 vmcs_read64(TSC_OFFSET
), offset
);
2213 vmcs_write64(TSC_OFFSET
, offset
);
2217 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2219 u64 offset
= vmcs_read64(TSC_OFFSET
);
2221 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2222 if (is_guest_mode(vcpu
)) {
2223 /* Even when running L2, the adjustment needs to apply to L1 */
2224 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2226 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2227 offset
+ adjustment
);
2230 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2232 return target_tsc
- native_read_tsc();
2235 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2237 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2238 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2242 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2243 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2244 * all guests if the "nested" module option is off, and can also be disabled
2245 * for a single guest by disabling its VMX cpuid bit.
2247 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2249 return nested
&& guest_cpuid_has_vmx(vcpu
);
2253 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2254 * returned for the various VMX controls MSRs when nested VMX is enabled.
2255 * The same values should also be used to verify that vmcs12 control fields are
2256 * valid during nested entry from L1 to L2.
2257 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2258 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2259 * bit in the high half is on if the corresponding bit in the control field
2260 * may be on. See also vmx_control_verify().
2261 * TODO: allow these variables to be modified (downgraded) by module options
2264 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2265 static u32 nested_vmx_true_procbased_ctls_low
;
2266 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2267 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2268 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2269 static u32 nested_vmx_true_exit_ctls_low
;
2270 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2271 static u32 nested_vmx_true_entry_ctls_low
;
2272 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2273 static u32 nested_vmx_ept_caps
;
2274 static __init
void nested_vmx_setup_ctls_msrs(void)
2277 * Note that as a general rule, the high half of the MSRs (bits in
2278 * the control fields which may be 1) should be initialized by the
2279 * intersection of the underlying hardware's MSR (i.e., features which
2280 * can be supported) and the list of features we want to expose -
2281 * because they are known to be properly supported in our code.
2282 * Also, usually, the low half of the MSRs (bits which must be 1) can
2283 * be set to 0, meaning that L1 may turn off any of these bits. The
2284 * reason is that if one of these bits is necessary, it will appear
2285 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2286 * fields of vmcs01 and vmcs02, will turn these bits off - and
2287 * nested_vmx_exit_handled() will not pass related exits to L1.
2288 * These rules have exceptions below.
2291 /* pin-based controls */
2292 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2293 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2294 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2295 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2296 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2297 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2298 PIN_BASED_VMX_PREEMPTION_TIMER
;
2301 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2302 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2303 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2305 nested_vmx_exit_ctls_high
&=
2306 #ifdef CONFIG_X86_64
2307 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2309 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2310 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2311 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2312 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2314 if (vmx_mpx_supported())
2315 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2317 /* We support free control of debug control saving. */
2318 nested_vmx_true_exit_ctls_low
= nested_vmx_exit_ctls_low
&
2319 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2321 /* entry controls */
2322 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2323 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2324 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2325 nested_vmx_entry_ctls_high
&=
2326 #ifdef CONFIG_X86_64
2327 VM_ENTRY_IA32E_MODE
|
2329 VM_ENTRY_LOAD_IA32_PAT
;
2330 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2331 VM_ENTRY_LOAD_IA32_EFER
);
2332 if (vmx_mpx_supported())
2333 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2335 /* We support free control of debug control loading. */
2336 nested_vmx_true_entry_ctls_low
= nested_vmx_entry_ctls_low
&
2337 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2339 /* cpu-based controls */
2340 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2341 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2342 nested_vmx_procbased_ctls_low
= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2343 nested_vmx_procbased_ctls_high
&=
2344 CPU_BASED_VIRTUAL_INTR_PENDING
|
2345 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2346 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2347 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2348 CPU_BASED_CR3_STORE_EXITING
|
2349 #ifdef CONFIG_X86_64
2350 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2352 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2353 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2354 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2355 CPU_BASED_PAUSE_EXITING
|
2356 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2358 * We can allow some features even when not supported by the
2359 * hardware. For example, L1 can specify an MSR bitmap - and we
2360 * can use it to avoid exits to L1 - even when L0 runs L2
2361 * without MSR bitmaps.
2363 nested_vmx_procbased_ctls_high
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2364 CPU_BASED_USE_MSR_BITMAPS
;
2366 /* We support free control of CR3 access interception. */
2367 nested_vmx_true_procbased_ctls_low
= nested_vmx_procbased_ctls_low
&
2368 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2370 /* secondary cpu-based controls */
2371 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2372 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2373 nested_vmx_secondary_ctls_low
= 0;
2374 nested_vmx_secondary_ctls_high
&=
2375 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2376 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2377 SECONDARY_EXEC_WBINVD_EXITING
;
2380 /* nested EPT: emulate EPT also to L1 */
2381 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2382 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2383 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2385 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2387 * For nested guests, we don't do anything specific
2388 * for single context invalidation. Hence, only advertise
2389 * support for global context invalidation.
2391 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2393 nested_vmx_ept_caps
= 0;
2395 /* miscellaneous data */
2396 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2397 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2398 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2399 VMX_MISC_ACTIVITY_HLT
;
2400 nested_vmx_misc_high
= 0;
2403 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2406 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2408 return ((control
& high
) | low
) == control
;
2411 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2413 return low
| ((u64
)high
<< 32);
2416 /* Returns 0 on success, non-0 otherwise. */
2417 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2419 switch (msr_index
) {
2420 case MSR_IA32_VMX_BASIC
:
2422 * This MSR reports some information about VMX support. We
2423 * should return information about the VMX we emulate for the
2424 * guest, and the VMCS structure we give it - not about the
2425 * VMX support of the underlying hardware.
2427 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2428 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2429 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2431 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2432 case MSR_IA32_VMX_PINBASED_CTLS
:
2433 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2434 nested_vmx_pinbased_ctls_high
);
2436 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2437 *pdata
= vmx_control_msr(nested_vmx_true_procbased_ctls_low
,
2438 nested_vmx_procbased_ctls_high
);
2440 case MSR_IA32_VMX_PROCBASED_CTLS
:
2441 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2442 nested_vmx_procbased_ctls_high
);
2444 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2445 *pdata
= vmx_control_msr(nested_vmx_true_exit_ctls_low
,
2446 nested_vmx_exit_ctls_high
);
2448 case MSR_IA32_VMX_EXIT_CTLS
:
2449 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2450 nested_vmx_exit_ctls_high
);
2452 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2453 *pdata
= vmx_control_msr(nested_vmx_true_entry_ctls_low
,
2454 nested_vmx_entry_ctls_high
);
2456 case MSR_IA32_VMX_ENTRY_CTLS
:
2457 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2458 nested_vmx_entry_ctls_high
);
2460 case MSR_IA32_VMX_MISC
:
2461 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2462 nested_vmx_misc_high
);
2465 * These MSRs specify bits which the guest must keep fixed (on or off)
2466 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2467 * We picked the standard core2 setting.
2469 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2470 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2471 case MSR_IA32_VMX_CR0_FIXED0
:
2472 *pdata
= VMXON_CR0_ALWAYSON
;
2474 case MSR_IA32_VMX_CR0_FIXED1
:
2477 case MSR_IA32_VMX_CR4_FIXED0
:
2478 *pdata
= VMXON_CR4_ALWAYSON
;
2480 case MSR_IA32_VMX_CR4_FIXED1
:
2483 case MSR_IA32_VMX_VMCS_ENUM
:
2484 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2486 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2487 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2488 nested_vmx_secondary_ctls_high
);
2490 case MSR_IA32_VMX_EPT_VPID_CAP
:
2491 /* Currently, no nested vpid support */
2492 *pdata
= nested_vmx_ept_caps
;
2502 * Reads an msr value (of 'msr_index') into 'pdata'.
2503 * Returns 0 on success, non-0 otherwise.
2504 * Assumes vcpu_load() was already called.
2506 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2509 struct shared_msr_entry
*msr
;
2512 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2516 switch (msr_index
) {
2517 #ifdef CONFIG_X86_64
2519 data
= vmcs_readl(GUEST_FS_BASE
);
2522 data
= vmcs_readl(GUEST_GS_BASE
);
2524 case MSR_KERNEL_GS_BASE
:
2525 vmx_load_host_state(to_vmx(vcpu
));
2526 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2530 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2532 data
= guest_read_tsc();
2534 case MSR_IA32_SYSENTER_CS
:
2535 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2537 case MSR_IA32_SYSENTER_EIP
:
2538 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2540 case MSR_IA32_SYSENTER_ESP
:
2541 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2543 case MSR_IA32_BNDCFGS
:
2544 if (!vmx_mpx_supported())
2546 data
= vmcs_read64(GUEST_BNDCFGS
);
2548 case MSR_IA32_FEATURE_CONTROL
:
2549 if (!nested_vmx_allowed(vcpu
))
2551 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2553 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2554 if (!nested_vmx_allowed(vcpu
))
2556 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2558 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2560 /* Otherwise falls through */
2562 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2567 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2574 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2577 * Writes msr value into into the appropriate "register".
2578 * Returns 0 on success, non-0 otherwise.
2579 * Assumes vcpu_load() was already called.
2581 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2583 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2584 struct shared_msr_entry
*msr
;
2586 u32 msr_index
= msr_info
->index
;
2587 u64 data
= msr_info
->data
;
2589 switch (msr_index
) {
2591 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2593 #ifdef CONFIG_X86_64
2595 vmx_segment_cache_clear(vmx
);
2596 vmcs_writel(GUEST_FS_BASE
, data
);
2599 vmx_segment_cache_clear(vmx
);
2600 vmcs_writel(GUEST_GS_BASE
, data
);
2602 case MSR_KERNEL_GS_BASE
:
2603 vmx_load_host_state(vmx
);
2604 vmx
->msr_guest_kernel_gs_base
= data
;
2607 case MSR_IA32_SYSENTER_CS
:
2608 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2610 case MSR_IA32_SYSENTER_EIP
:
2611 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2613 case MSR_IA32_SYSENTER_ESP
:
2614 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2616 case MSR_IA32_BNDCFGS
:
2617 if (!vmx_mpx_supported())
2619 vmcs_write64(GUEST_BNDCFGS
, data
);
2622 kvm_write_tsc(vcpu
, msr_info
);
2624 case MSR_IA32_CR_PAT
:
2625 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2626 vmcs_write64(GUEST_IA32_PAT
, data
);
2627 vcpu
->arch
.pat
= data
;
2630 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2632 case MSR_IA32_TSC_ADJUST
:
2633 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2635 case MSR_IA32_FEATURE_CONTROL
:
2636 if (!nested_vmx_allowed(vcpu
) ||
2637 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2638 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2640 vmx
->nested
.msr_ia32_feature_control
= data
;
2641 if (msr_info
->host_initiated
&& data
== 0)
2642 vmx_leave_nested(vcpu
);
2644 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2645 return 1; /* they are read-only */
2647 if (!vmx
->rdtscp_enabled
)
2649 /* Check reserved bit, higher 32 bits should be zero */
2650 if ((data
>> 32) != 0)
2652 /* Otherwise falls through */
2654 msr
= find_msr_entry(vmx
, msr_index
);
2657 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2659 kvm_set_shared_msr(msr
->index
, msr
->data
,
2665 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2671 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2673 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2676 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2679 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2681 case VCPU_EXREG_PDPTR
:
2683 ept_save_pdptrs(vcpu
);
2690 static __init
int cpu_has_kvm_support(void)
2692 return cpu_has_vmx();
2695 static __init
int vmx_disabled_by_bios(void)
2699 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2700 if (msr
& FEATURE_CONTROL_LOCKED
) {
2701 /* launched w/ TXT and VMX disabled */
2702 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2705 /* launched w/o TXT and VMX only enabled w/ TXT */
2706 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2707 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2708 && !tboot_enabled()) {
2709 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2710 "activate TXT before enabling KVM\n");
2713 /* launched w/o TXT and VMX disabled */
2714 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2715 && !tboot_enabled())
2722 static void kvm_cpu_vmxon(u64 addr
)
2724 asm volatile (ASM_VMX_VMXON_RAX
2725 : : "a"(&addr
), "m"(addr
)
2729 static int hardware_enable(void *garbage
)
2731 int cpu
= raw_smp_processor_id();
2732 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2735 if (read_cr4() & X86_CR4_VMXE
)
2738 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2741 * Now we can enable the vmclear operation in kdump
2742 * since the loaded_vmcss_on_cpu list on this cpu
2743 * has been initialized.
2745 * Though the cpu is not in VMX operation now, there
2746 * is no problem to enable the vmclear operation
2747 * for the loaded_vmcss_on_cpu list is empty!
2749 crash_enable_local_vmclear(cpu
);
2751 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2753 test_bits
= FEATURE_CONTROL_LOCKED
;
2754 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2755 if (tboot_enabled())
2756 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2758 if ((old
& test_bits
) != test_bits
) {
2759 /* enable and lock */
2760 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2762 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2764 if (vmm_exclusive
) {
2765 kvm_cpu_vmxon(phys_addr
);
2769 native_store_gdt(&__get_cpu_var(host_gdt
));
2774 static void vmclear_local_loaded_vmcss(void)
2776 int cpu
= raw_smp_processor_id();
2777 struct loaded_vmcs
*v
, *n
;
2779 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2780 loaded_vmcss_on_cpu_link
)
2781 __loaded_vmcs_clear(v
);
2785 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2788 static void kvm_cpu_vmxoff(void)
2790 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2793 static void hardware_disable(void *garbage
)
2795 if (vmm_exclusive
) {
2796 vmclear_local_loaded_vmcss();
2799 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2802 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2803 u32 msr
, u32
*result
)
2805 u32 vmx_msr_low
, vmx_msr_high
;
2806 u32 ctl
= ctl_min
| ctl_opt
;
2808 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2810 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2811 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2813 /* Ensure minimum (required) set of control bits are supported. */
2821 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2823 u32 vmx_msr_low
, vmx_msr_high
;
2825 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2826 return vmx_msr_high
& ctl
;
2829 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2831 u32 vmx_msr_low
, vmx_msr_high
;
2832 u32 min
, opt
, min2
, opt2
;
2833 u32 _pin_based_exec_control
= 0;
2834 u32 _cpu_based_exec_control
= 0;
2835 u32 _cpu_based_2nd_exec_control
= 0;
2836 u32 _vmexit_control
= 0;
2837 u32 _vmentry_control
= 0;
2839 min
= CPU_BASED_HLT_EXITING
|
2840 #ifdef CONFIG_X86_64
2841 CPU_BASED_CR8_LOAD_EXITING
|
2842 CPU_BASED_CR8_STORE_EXITING
|
2844 CPU_BASED_CR3_LOAD_EXITING
|
2845 CPU_BASED_CR3_STORE_EXITING
|
2846 CPU_BASED_USE_IO_BITMAPS
|
2847 CPU_BASED_MOV_DR_EXITING
|
2848 CPU_BASED_USE_TSC_OFFSETING
|
2849 CPU_BASED_MWAIT_EXITING
|
2850 CPU_BASED_MONITOR_EXITING
|
2851 CPU_BASED_INVLPG_EXITING
|
2852 CPU_BASED_RDPMC_EXITING
;
2854 opt
= CPU_BASED_TPR_SHADOW
|
2855 CPU_BASED_USE_MSR_BITMAPS
|
2856 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2857 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2858 &_cpu_based_exec_control
) < 0)
2860 #ifdef CONFIG_X86_64
2861 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2862 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2863 ~CPU_BASED_CR8_STORE_EXITING
;
2865 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2867 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2868 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2869 SECONDARY_EXEC_WBINVD_EXITING
|
2870 SECONDARY_EXEC_ENABLE_VPID
|
2871 SECONDARY_EXEC_ENABLE_EPT
|
2872 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2873 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2874 SECONDARY_EXEC_RDTSCP
|
2875 SECONDARY_EXEC_ENABLE_INVPCID
|
2876 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2877 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2878 SECONDARY_EXEC_SHADOW_VMCS
;
2879 if (adjust_vmx_controls(min2
, opt2
,
2880 MSR_IA32_VMX_PROCBASED_CTLS2
,
2881 &_cpu_based_2nd_exec_control
) < 0)
2884 #ifndef CONFIG_X86_64
2885 if (!(_cpu_based_2nd_exec_control
&
2886 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2887 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2890 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2891 _cpu_based_2nd_exec_control
&= ~(
2892 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2893 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2894 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2896 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2897 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2899 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2900 CPU_BASED_CR3_STORE_EXITING
|
2901 CPU_BASED_INVLPG_EXITING
);
2902 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2903 vmx_capability
.ept
, vmx_capability
.vpid
);
2906 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2907 #ifdef CONFIG_X86_64
2908 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2910 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2911 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2912 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2913 &_vmexit_control
) < 0)
2916 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2917 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2918 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2919 &_pin_based_exec_control
) < 0)
2922 if (!(_cpu_based_2nd_exec_control
&
2923 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2924 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2925 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2927 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2928 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2929 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2930 &_vmentry_control
) < 0)
2933 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2935 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2936 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2939 #ifdef CONFIG_X86_64
2940 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2941 if (vmx_msr_high
& (1u<<16))
2945 /* Require Write-Back (WB) memory type for VMCS accesses. */
2946 if (((vmx_msr_high
>> 18) & 15) != 6)
2949 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2950 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2951 vmcs_conf
->revision_id
= vmx_msr_low
;
2953 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2954 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2955 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2956 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2957 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2959 cpu_has_load_ia32_efer
=
2960 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2961 VM_ENTRY_LOAD_IA32_EFER
)
2962 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2963 VM_EXIT_LOAD_IA32_EFER
);
2965 cpu_has_load_perf_global_ctrl
=
2966 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2967 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2968 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2969 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2972 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2973 * but due to arrata below it can't be used. Workaround is to use
2974 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2976 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2981 * BC86,AAY89,BD102 (model 44)
2985 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2986 switch (boot_cpu_data
.x86_model
) {
2992 cpu_has_load_perf_global_ctrl
= false;
2993 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2994 "does not work properly. Using workaround\n");
3004 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3006 int node
= cpu_to_node(cpu
);
3010 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3013 vmcs
= page_address(pages
);
3014 memset(vmcs
, 0, vmcs_config
.size
);
3015 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3019 static struct vmcs
*alloc_vmcs(void)
3021 return alloc_vmcs_cpu(raw_smp_processor_id());
3024 static void free_vmcs(struct vmcs
*vmcs
)
3026 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3030 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3032 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3034 if (!loaded_vmcs
->vmcs
)
3036 loaded_vmcs_clear(loaded_vmcs
);
3037 free_vmcs(loaded_vmcs
->vmcs
);
3038 loaded_vmcs
->vmcs
= NULL
;
3041 static void free_kvm_area(void)
3045 for_each_possible_cpu(cpu
) {
3046 free_vmcs(per_cpu(vmxarea
, cpu
));
3047 per_cpu(vmxarea
, cpu
) = NULL
;
3051 static void init_vmcs_shadow_fields(void)
3055 /* No checks for read only fields yet */
3057 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3058 switch (shadow_read_write_fields
[i
]) {
3060 if (!vmx_mpx_supported())
3068 shadow_read_write_fields
[j
] =
3069 shadow_read_write_fields
[i
];
3072 max_shadow_read_write_fields
= j
;
3074 /* shadowed fields guest access without vmexit */
3075 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3076 clear_bit(shadow_read_write_fields
[i
],
3077 vmx_vmwrite_bitmap
);
3078 clear_bit(shadow_read_write_fields
[i
],
3081 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3082 clear_bit(shadow_read_only_fields
[i
],
3086 static __init
int alloc_kvm_area(void)
3090 for_each_possible_cpu(cpu
) {
3093 vmcs
= alloc_vmcs_cpu(cpu
);
3099 per_cpu(vmxarea
, cpu
) = vmcs
;
3104 static __init
int hardware_setup(void)
3106 if (setup_vmcs_config(&vmcs_config
) < 0)
3109 if (boot_cpu_has(X86_FEATURE_NX
))
3110 kvm_enable_efer_bits(EFER_NX
);
3112 if (!cpu_has_vmx_vpid())
3114 if (!cpu_has_vmx_shadow_vmcs())
3115 enable_shadow_vmcs
= 0;
3116 if (enable_shadow_vmcs
)
3117 init_vmcs_shadow_fields();
3119 if (!cpu_has_vmx_ept() ||
3120 !cpu_has_vmx_ept_4levels()) {
3122 enable_unrestricted_guest
= 0;
3123 enable_ept_ad_bits
= 0;
3126 if (!cpu_has_vmx_ept_ad_bits())
3127 enable_ept_ad_bits
= 0;
3129 if (!cpu_has_vmx_unrestricted_guest())
3130 enable_unrestricted_guest
= 0;
3132 if (!cpu_has_vmx_flexpriority())
3133 flexpriority_enabled
= 0;
3135 if (!cpu_has_vmx_tpr_shadow())
3136 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3138 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3139 kvm_disable_largepages();
3141 if (!cpu_has_vmx_ple())
3144 if (!cpu_has_vmx_apicv())
3148 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3150 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3151 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3152 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3156 nested_vmx_setup_ctls_msrs();
3158 return alloc_kvm_area();
3161 static __exit
void hardware_unsetup(void)
3166 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3168 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3171 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3172 struct kvm_segment
*save
)
3174 if (!emulate_invalid_guest_state
) {
3176 * CS and SS RPL should be equal during guest entry according
3177 * to VMX spec, but in reality it is not always so. Since vcpu
3178 * is in the middle of the transition from real mode to
3179 * protected mode it is safe to assume that RPL 0 is a good
3182 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3183 save
->selector
&= ~SELECTOR_RPL_MASK
;
3184 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3187 vmx_set_segment(vcpu
, save
, seg
);
3190 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3192 unsigned long flags
;
3193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3196 * Update real mode segment cache. It may be not up-to-date if sement
3197 * register was written while vcpu was in a guest mode.
3199 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3200 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3201 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3202 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3203 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3204 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3206 vmx
->rmode
.vm86_active
= 0;
3208 vmx_segment_cache_clear(vmx
);
3210 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3212 flags
= vmcs_readl(GUEST_RFLAGS
);
3213 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3214 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3215 vmcs_writel(GUEST_RFLAGS
, flags
);
3217 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3218 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3220 update_exception_bitmap(vcpu
);
3222 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3223 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3224 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3225 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3226 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3227 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3230 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3232 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3233 struct kvm_segment var
= *save
;
3236 if (seg
== VCPU_SREG_CS
)
3239 if (!emulate_invalid_guest_state
) {
3240 var
.selector
= var
.base
>> 4;
3241 var
.base
= var
.base
& 0xffff0;
3251 if (save
->base
& 0xf)
3252 printk_once(KERN_WARNING
"kvm: segment base is not "
3253 "paragraph aligned when entering "
3254 "protected mode (seg=%d)", seg
);
3257 vmcs_write16(sf
->selector
, var
.selector
);
3258 vmcs_write32(sf
->base
, var
.base
);
3259 vmcs_write32(sf
->limit
, var
.limit
);
3260 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3263 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3265 unsigned long flags
;
3266 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3268 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3269 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3270 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3271 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3272 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3273 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3274 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3276 vmx
->rmode
.vm86_active
= 1;
3279 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3280 * vcpu. Warn the user that an update is overdue.
3282 if (!vcpu
->kvm
->arch
.tss_addr
)
3283 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3284 "called before entering vcpu\n");
3286 vmx_segment_cache_clear(vmx
);
3288 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3289 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3290 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3292 flags
= vmcs_readl(GUEST_RFLAGS
);
3293 vmx
->rmode
.save_rflags
= flags
;
3295 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3297 vmcs_writel(GUEST_RFLAGS
, flags
);
3298 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3299 update_exception_bitmap(vcpu
);
3301 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3302 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3303 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3304 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3305 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3306 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3308 kvm_mmu_reset_context(vcpu
);
3311 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3314 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3320 * Force kernel_gs_base reloading before EFER changes, as control
3321 * of this msr depends on is_long_mode().
3323 vmx_load_host_state(to_vmx(vcpu
));
3324 vcpu
->arch
.efer
= efer
;
3325 if (efer
& EFER_LMA
) {
3326 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3329 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3331 msr
->data
= efer
& ~EFER_LME
;
3336 #ifdef CONFIG_X86_64
3338 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3342 vmx_segment_cache_clear(to_vmx(vcpu
));
3344 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3345 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3346 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3348 vmcs_write32(GUEST_TR_AR_BYTES
,
3349 (guest_tr_ar
& ~AR_TYPE_MASK
)
3350 | AR_TYPE_BUSY_64_TSS
);
3352 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3355 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3357 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3358 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3363 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3365 vpid_sync_context(to_vmx(vcpu
));
3367 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3369 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3373 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3375 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3377 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3378 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3381 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3383 if (enable_ept
&& is_paging(vcpu
))
3384 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3385 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3388 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3390 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3392 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3393 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3396 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3398 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3400 if (!test_bit(VCPU_EXREG_PDPTR
,
3401 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3404 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3405 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3406 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3407 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3408 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3412 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3414 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3416 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3417 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3418 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3419 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3420 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3423 __set_bit(VCPU_EXREG_PDPTR
,
3424 (unsigned long *)&vcpu
->arch
.regs_avail
);
3425 __set_bit(VCPU_EXREG_PDPTR
,
3426 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3429 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3431 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3433 struct kvm_vcpu
*vcpu
)
3435 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3436 vmx_decache_cr3(vcpu
);
3437 if (!(cr0
& X86_CR0_PG
)) {
3438 /* From paging/starting to nonpaging */
3439 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3440 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3441 (CPU_BASED_CR3_LOAD_EXITING
|
3442 CPU_BASED_CR3_STORE_EXITING
));
3443 vcpu
->arch
.cr0
= cr0
;
3444 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3445 } else if (!is_paging(vcpu
)) {
3446 /* From nonpaging to paging */
3447 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3448 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3449 ~(CPU_BASED_CR3_LOAD_EXITING
|
3450 CPU_BASED_CR3_STORE_EXITING
));
3451 vcpu
->arch
.cr0
= cr0
;
3452 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3455 if (!(cr0
& X86_CR0_WP
))
3456 *hw_cr0
&= ~X86_CR0_WP
;
3459 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3461 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3462 unsigned long hw_cr0
;
3464 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3465 if (enable_unrestricted_guest
)
3466 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3468 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3470 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3473 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3477 #ifdef CONFIG_X86_64
3478 if (vcpu
->arch
.efer
& EFER_LME
) {
3479 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3481 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3487 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3489 if (!vcpu
->fpu_active
)
3490 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3492 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3493 vmcs_writel(GUEST_CR0
, hw_cr0
);
3494 vcpu
->arch
.cr0
= cr0
;
3496 /* depends on vcpu->arch.cr0 to be set to a new value */
3497 vmx
->emulation_required
= emulation_required(vcpu
);
3500 static u64
construct_eptp(unsigned long root_hpa
)
3504 /* TODO write the value reading from MSR */
3505 eptp
= VMX_EPT_DEFAULT_MT
|
3506 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3507 if (enable_ept_ad_bits
)
3508 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3509 eptp
|= (root_hpa
& PAGE_MASK
);
3514 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3516 unsigned long guest_cr3
;
3521 eptp
= construct_eptp(cr3
);
3522 vmcs_write64(EPT_POINTER
, eptp
);
3523 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3524 guest_cr3
= kvm_read_cr3(vcpu
);
3526 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3527 ept_load_pdptrs(vcpu
);
3530 vmx_flush_tlb(vcpu
);
3531 vmcs_writel(GUEST_CR3
, guest_cr3
);
3534 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3536 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3537 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3539 if (cr4
& X86_CR4_VMXE
) {
3541 * To use VMXON (and later other VMX instructions), a guest
3542 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3543 * So basically the check on whether to allow nested VMX
3546 if (!nested_vmx_allowed(vcpu
))
3549 if (to_vmx(vcpu
)->nested
.vmxon
&&
3550 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3553 vcpu
->arch
.cr4
= cr4
;
3555 if (!is_paging(vcpu
)) {
3556 hw_cr4
&= ~X86_CR4_PAE
;
3557 hw_cr4
|= X86_CR4_PSE
;
3559 * SMEP/SMAP is disabled if CPU is in non-paging mode
3560 * in hardware. However KVM always uses paging mode to
3561 * emulate guest non-paging mode with TDP.
3562 * To emulate this behavior, SMEP/SMAP needs to be
3563 * manually disabled when guest switches to non-paging
3566 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3567 } else if (!(cr4
& X86_CR4_PAE
)) {
3568 hw_cr4
&= ~X86_CR4_PAE
;
3572 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3573 vmcs_writel(GUEST_CR4
, hw_cr4
);
3577 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3578 struct kvm_segment
*var
, int seg
)
3580 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3583 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3584 *var
= vmx
->rmode
.segs
[seg
];
3585 if (seg
== VCPU_SREG_TR
3586 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3588 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3589 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3592 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3593 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3594 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3595 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3596 var
->unusable
= (ar
>> 16) & 1;
3597 var
->type
= ar
& 15;
3598 var
->s
= (ar
>> 4) & 1;
3599 var
->dpl
= (ar
>> 5) & 3;
3601 * Some userspaces do not preserve unusable property. Since usable
3602 * segment has to be present according to VMX spec we can use present
3603 * property to amend userspace bug by making unusable segment always
3604 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3605 * segment as unusable.
3607 var
->present
= !var
->unusable
;
3608 var
->avl
= (ar
>> 12) & 1;
3609 var
->l
= (ar
>> 13) & 1;
3610 var
->db
= (ar
>> 14) & 1;
3611 var
->g
= (ar
>> 15) & 1;
3614 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3616 struct kvm_segment s
;
3618 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3619 vmx_get_segment(vcpu
, &s
, seg
);
3622 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3625 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3627 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3629 if (unlikely(vmx
->rmode
.vm86_active
))
3632 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3637 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3641 if (var
->unusable
|| !var
->present
)
3644 ar
= var
->type
& 15;
3645 ar
|= (var
->s
& 1) << 4;
3646 ar
|= (var
->dpl
& 3) << 5;
3647 ar
|= (var
->present
& 1) << 7;
3648 ar
|= (var
->avl
& 1) << 12;
3649 ar
|= (var
->l
& 1) << 13;
3650 ar
|= (var
->db
& 1) << 14;
3651 ar
|= (var
->g
& 1) << 15;
3657 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3658 struct kvm_segment
*var
, int seg
)
3660 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3661 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3663 vmx_segment_cache_clear(vmx
);
3665 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3666 vmx
->rmode
.segs
[seg
] = *var
;
3667 if (seg
== VCPU_SREG_TR
)
3668 vmcs_write16(sf
->selector
, var
->selector
);
3670 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3674 vmcs_writel(sf
->base
, var
->base
);
3675 vmcs_write32(sf
->limit
, var
->limit
);
3676 vmcs_write16(sf
->selector
, var
->selector
);
3679 * Fix the "Accessed" bit in AR field of segment registers for older
3681 * IA32 arch specifies that at the time of processor reset the
3682 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3683 * is setting it to 0 in the userland code. This causes invalid guest
3684 * state vmexit when "unrestricted guest" mode is turned on.
3685 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3686 * tree. Newer qemu binaries with that qemu fix would not need this
3689 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3690 var
->type
|= 0x1; /* Accessed */
3692 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3695 vmx
->emulation_required
= emulation_required(vcpu
);
3698 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3700 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3702 *db
= (ar
>> 14) & 1;
3703 *l
= (ar
>> 13) & 1;
3706 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3708 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3709 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3712 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3714 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3715 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3718 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3720 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3721 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3724 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3726 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3727 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3730 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3732 struct kvm_segment var
;
3735 vmx_get_segment(vcpu
, &var
, seg
);
3737 if (seg
== VCPU_SREG_CS
)
3739 ar
= vmx_segment_access_rights(&var
);
3741 if (var
.base
!= (var
.selector
<< 4))
3743 if (var
.limit
!= 0xffff)
3751 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3753 struct kvm_segment cs
;
3754 unsigned int cs_rpl
;
3756 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3757 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3761 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3765 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3766 if (cs
.dpl
> cs_rpl
)
3769 if (cs
.dpl
!= cs_rpl
)
3775 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3779 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3781 struct kvm_segment ss
;
3782 unsigned int ss_rpl
;
3784 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3785 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3789 if (ss
.type
!= 3 && ss
.type
!= 7)
3793 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3801 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3803 struct kvm_segment var
;
3806 vmx_get_segment(vcpu
, &var
, seg
);
3807 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3815 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3816 if (var
.dpl
< rpl
) /* DPL < RPL */
3820 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3826 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3828 struct kvm_segment tr
;
3830 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3834 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3836 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3844 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3846 struct kvm_segment ldtr
;
3848 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3852 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3862 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3864 struct kvm_segment cs
, ss
;
3866 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3867 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3869 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3870 (ss
.selector
& SELECTOR_RPL_MASK
));
3874 * Check if guest state is valid. Returns true if valid, false if
3876 * We assume that registers are always usable
3878 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3880 if (enable_unrestricted_guest
)
3883 /* real mode guest state checks */
3884 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3885 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3887 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3889 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3891 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3893 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3895 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3898 /* protected mode guest state checks */
3899 if (!cs_ss_rpl_check(vcpu
))
3901 if (!code_segment_valid(vcpu
))
3903 if (!stack_segment_valid(vcpu
))
3905 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3907 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3909 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3911 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3913 if (!tr_valid(vcpu
))
3915 if (!ldtr_valid(vcpu
))
3919 * - Add checks on RIP
3920 * - Add checks on RFLAGS
3926 static int init_rmode_tss(struct kvm
*kvm
)
3930 int r
, idx
, ret
= 0;
3932 idx
= srcu_read_lock(&kvm
->srcu
);
3933 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3934 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3937 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3938 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3939 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3942 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3945 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3949 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3950 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3957 srcu_read_unlock(&kvm
->srcu
, idx
);
3961 static int init_rmode_identity_map(struct kvm
*kvm
)
3964 pfn_t identity_map_pfn
;
3969 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3970 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3971 "haven't been allocated!\n");
3974 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3977 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3978 idx
= srcu_read_lock(&kvm
->srcu
);
3979 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3982 /* Set up identity-mapping pagetable for EPT in real mode */
3983 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3984 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3985 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3986 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3987 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3991 kvm
->arch
.ept_identity_pagetable_done
= true;
3994 srcu_read_unlock(&kvm
->srcu
, idx
);
3998 static void seg_setup(int seg
)
4000 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4003 vmcs_write16(sf
->selector
, 0);
4004 vmcs_writel(sf
->base
, 0);
4005 vmcs_write32(sf
->limit
, 0xffff);
4007 if (seg
== VCPU_SREG_CS
)
4008 ar
|= 0x08; /* code segment */
4010 vmcs_write32(sf
->ar_bytes
, ar
);
4013 static int alloc_apic_access_page(struct kvm
*kvm
)
4016 struct kvm_userspace_memory_region kvm_userspace_mem
;
4019 mutex_lock(&kvm
->slots_lock
);
4020 if (kvm
->arch
.apic_access_page
)
4022 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4023 kvm_userspace_mem
.flags
= 0;
4024 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
4025 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4026 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4030 page
= gfn_to_page(kvm
, 0xfee00);
4031 if (is_error_page(page
)) {
4036 kvm
->arch
.apic_access_page
= page
;
4038 mutex_unlock(&kvm
->slots_lock
);
4042 static int alloc_identity_pagetable(struct kvm
*kvm
)
4045 struct kvm_userspace_memory_region kvm_userspace_mem
;
4048 mutex_lock(&kvm
->slots_lock
);
4049 if (kvm
->arch
.ept_identity_pagetable
)
4051 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4052 kvm_userspace_mem
.flags
= 0;
4053 kvm_userspace_mem
.guest_phys_addr
=
4054 kvm
->arch
.ept_identity_map_addr
;
4055 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4056 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4060 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
4061 if (is_error_page(page
)) {
4066 kvm
->arch
.ept_identity_pagetable
= page
;
4068 mutex_unlock(&kvm
->slots_lock
);
4072 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4079 spin_lock(&vmx_vpid_lock
);
4080 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4081 if (vpid
< VMX_NR_VPIDS
) {
4083 __set_bit(vpid
, vmx_vpid_bitmap
);
4085 spin_unlock(&vmx_vpid_lock
);
4088 static void free_vpid(struct vcpu_vmx
*vmx
)
4092 spin_lock(&vmx_vpid_lock
);
4094 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4095 spin_unlock(&vmx_vpid_lock
);
4098 #define MSR_TYPE_R 1
4099 #define MSR_TYPE_W 2
4100 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4103 int f
= sizeof(unsigned long);
4105 if (!cpu_has_vmx_msr_bitmap())
4109 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4110 * have the write-low and read-high bitmap offsets the wrong way round.
4111 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4113 if (msr
<= 0x1fff) {
4114 if (type
& MSR_TYPE_R
)
4116 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4118 if (type
& MSR_TYPE_W
)
4120 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4122 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4124 if (type
& MSR_TYPE_R
)
4126 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4128 if (type
& MSR_TYPE_W
)
4130 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4135 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4138 int f
= sizeof(unsigned long);
4140 if (!cpu_has_vmx_msr_bitmap())
4144 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4145 * have the write-low and read-high bitmap offsets the wrong way round.
4146 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4148 if (msr
<= 0x1fff) {
4149 if (type
& MSR_TYPE_R
)
4151 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4153 if (type
& MSR_TYPE_W
)
4155 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4157 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4159 if (type
& MSR_TYPE_R
)
4161 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4163 if (type
& MSR_TYPE_W
)
4165 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4170 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4173 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4174 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4175 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4176 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4179 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4181 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4183 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4187 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4189 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4191 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4195 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4197 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4199 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4203 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4205 return enable_apicv
&& irqchip_in_kernel(kvm
);
4209 * Send interrupt to vcpu via posted interrupt way.
4210 * 1. If target vcpu is running(non-root mode), send posted interrupt
4211 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4212 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4213 * interrupt from PIR in next vmentry.
4215 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4217 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4220 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4223 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4224 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4226 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4227 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4228 POSTED_INTR_VECTOR
);
4231 kvm_vcpu_kick(vcpu
);
4234 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4238 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4241 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4244 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4250 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4251 * will not change in the lifetime of the guest.
4252 * Note that host-state that does change is set elsewhere. E.g., host-state
4253 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4255 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4261 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4262 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4263 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4265 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4266 #ifdef CONFIG_X86_64
4268 * Load null selectors, so we can avoid reloading them in
4269 * __vmx_load_host_state(), in case userspace uses the null selectors
4270 * too (the expected case).
4272 vmcs_write16(HOST_DS_SELECTOR
, 0);
4273 vmcs_write16(HOST_ES_SELECTOR
, 0);
4275 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4276 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4278 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4279 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4281 native_store_idt(&dt
);
4282 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4283 vmx
->host_idt_base
= dt
.address
;
4285 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4287 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4288 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4289 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4290 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4292 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4293 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4294 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4298 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4300 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4302 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4303 if (is_guest_mode(&vmx
->vcpu
))
4304 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4305 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4306 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4309 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4311 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4313 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4314 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4315 return pin_based_exec_ctrl
;
4318 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4320 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4322 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4323 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4325 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4326 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4327 #ifdef CONFIG_X86_64
4328 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4329 CPU_BASED_CR8_LOAD_EXITING
;
4333 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4334 CPU_BASED_CR3_LOAD_EXITING
|
4335 CPU_BASED_INVLPG_EXITING
;
4336 return exec_control
;
4339 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4341 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4342 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4343 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4345 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4347 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4348 enable_unrestricted_guest
= 0;
4349 /* Enable INVPCID for non-ept guests may cause performance regression. */
4350 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4352 if (!enable_unrestricted_guest
)
4353 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4355 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4356 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4357 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4358 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4359 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4360 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4362 We can NOT enable shadow_vmcs here because we don't have yet
4365 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4366 return exec_control
;
4369 static void ept_set_mmio_spte_mask(void)
4372 * EPT Misconfigurations can be generated if the value of bits 2:0
4373 * of an EPT paging-structure entry is 110b (write/execute).
4374 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4377 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4381 * Sets up the vmcs for emulated real mode.
4383 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4385 #ifdef CONFIG_X86_64
4391 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4392 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4394 if (enable_shadow_vmcs
) {
4395 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4396 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4398 if (cpu_has_vmx_msr_bitmap())
4399 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4401 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4404 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4406 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4408 if (cpu_has_secondary_exec_ctrls()) {
4409 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4410 vmx_secondary_exec_control(vmx
));
4413 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4414 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4415 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4416 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4417 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4419 vmcs_write16(GUEST_INTR_STATUS
, 0);
4421 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4422 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4426 vmcs_write32(PLE_GAP
, ple_gap
);
4427 vmx
->ple_window
= ple_window
;
4428 vmx
->ple_window_dirty
= true;
4431 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4432 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4433 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4435 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4436 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4437 vmx_set_constant_host_state(vmx
);
4438 #ifdef CONFIG_X86_64
4439 rdmsrl(MSR_FS_BASE
, a
);
4440 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4441 rdmsrl(MSR_GS_BASE
, a
);
4442 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4444 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4445 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4448 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4449 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4450 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4451 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4452 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4454 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4455 u32 msr_low
, msr_high
;
4457 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4458 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4459 /* Write the default value follow host pat */
4460 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4461 /* Keep arch.pat sync with GUEST_IA32_PAT */
4462 vmx
->vcpu
.arch
.pat
= host_pat
;
4465 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4466 u32 index
= vmx_msr_index
[i
];
4467 u32 data_low
, data_high
;
4470 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4472 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4474 vmx
->guest_msrs
[j
].index
= i
;
4475 vmx
->guest_msrs
[j
].data
= 0;
4476 vmx
->guest_msrs
[j
].mask
= -1ull;
4481 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4483 /* 22.2.1, 20.8.1 */
4484 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4486 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4487 set_cr4_guest_host_mask(vmx
);
4492 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4494 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4495 struct msr_data apic_base_msr
;
4497 vmx
->rmode
.vm86_active
= 0;
4499 vmx
->soft_vnmi_blocked
= 0;
4501 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4502 kvm_set_cr8(&vmx
->vcpu
, 0);
4503 apic_base_msr
.data
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4504 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4505 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4506 apic_base_msr
.host_initiated
= true;
4507 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4509 vmx_segment_cache_clear(vmx
);
4511 seg_setup(VCPU_SREG_CS
);
4512 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4513 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4515 seg_setup(VCPU_SREG_DS
);
4516 seg_setup(VCPU_SREG_ES
);
4517 seg_setup(VCPU_SREG_FS
);
4518 seg_setup(VCPU_SREG_GS
);
4519 seg_setup(VCPU_SREG_SS
);
4521 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4522 vmcs_writel(GUEST_TR_BASE
, 0);
4523 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4524 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4526 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4527 vmcs_writel(GUEST_LDTR_BASE
, 0);
4528 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4529 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4531 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4532 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4533 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4535 vmcs_writel(GUEST_RFLAGS
, 0x02);
4536 kvm_rip_write(vcpu
, 0xfff0);
4538 vmcs_writel(GUEST_GDTR_BASE
, 0);
4539 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4541 vmcs_writel(GUEST_IDTR_BASE
, 0);
4542 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4544 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4545 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4546 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4548 /* Special registers */
4549 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4555 if (cpu_has_vmx_tpr_shadow()) {
4556 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4557 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4558 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4559 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4560 vmcs_write32(TPR_THRESHOLD
, 0);
4563 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4564 vmcs_write64(APIC_ACCESS_ADDR
,
4565 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4567 if (vmx_vm_has_apicv(vcpu
->kvm
))
4568 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4571 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4573 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4574 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4575 vmx_set_cr4(&vmx
->vcpu
, 0);
4576 vmx_set_efer(&vmx
->vcpu
, 0);
4577 vmx_fpu_activate(&vmx
->vcpu
);
4578 update_exception_bitmap(&vmx
->vcpu
);
4580 vpid_sync_context(vmx
);
4584 * In nested virtualization, check if L1 asked to exit on external interrupts.
4585 * For most existing hypervisors, this will always return true.
4587 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4589 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4590 PIN_BASED_EXT_INTR_MASK
;
4594 * In nested virtualization, check if L1 has set
4595 * VM_EXIT_ACK_INTR_ON_EXIT
4597 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4599 return get_vmcs12(vcpu
)->vm_exit_controls
&
4600 VM_EXIT_ACK_INTR_ON_EXIT
;
4603 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4605 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4606 PIN_BASED_NMI_EXITING
;
4609 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4611 u32 cpu_based_vm_exec_control
;
4613 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4614 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4618 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4620 u32 cpu_based_vm_exec_control
;
4622 if (!cpu_has_virtual_nmis() ||
4623 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4624 enable_irq_window(vcpu
);
4628 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4629 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4630 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4633 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4635 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4637 int irq
= vcpu
->arch
.interrupt
.nr
;
4639 trace_kvm_inj_virq(irq
);
4641 ++vcpu
->stat
.irq_injections
;
4642 if (vmx
->rmode
.vm86_active
) {
4644 if (vcpu
->arch
.interrupt
.soft
)
4645 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4646 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4647 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4650 intr
= irq
| INTR_INFO_VALID_MASK
;
4651 if (vcpu
->arch
.interrupt
.soft
) {
4652 intr
|= INTR_TYPE_SOFT_INTR
;
4653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4654 vmx
->vcpu
.arch
.event_exit_inst_len
);
4656 intr
|= INTR_TYPE_EXT_INTR
;
4657 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4660 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4664 if (is_guest_mode(vcpu
))
4667 if (!cpu_has_virtual_nmis()) {
4669 * Tracking the NMI-blocked state in software is built upon
4670 * finding the next open IRQ window. This, in turn, depends on
4671 * well-behaving guests: They have to keep IRQs disabled at
4672 * least as long as the NMI handler runs. Otherwise we may
4673 * cause NMI nesting, maybe breaking the guest. But as this is
4674 * highly unlikely, we can live with the residual risk.
4676 vmx
->soft_vnmi_blocked
= 1;
4677 vmx
->vnmi_blocked_time
= 0;
4680 ++vcpu
->stat
.nmi_injections
;
4681 vmx
->nmi_known_unmasked
= false;
4682 if (vmx
->rmode
.vm86_active
) {
4683 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4684 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4687 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4688 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4691 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4693 if (!cpu_has_virtual_nmis())
4694 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4695 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4697 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4700 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4702 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4704 if (!cpu_has_virtual_nmis()) {
4705 if (vmx
->soft_vnmi_blocked
!= masked
) {
4706 vmx
->soft_vnmi_blocked
= masked
;
4707 vmx
->vnmi_blocked_time
= 0;
4710 vmx
->nmi_known_unmasked
= !masked
;
4712 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4713 GUEST_INTR_STATE_NMI
);
4715 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4716 GUEST_INTR_STATE_NMI
);
4720 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4722 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4725 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4728 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4729 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4730 | GUEST_INTR_STATE_NMI
));
4733 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4735 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4736 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4737 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4738 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4741 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4744 struct kvm_userspace_memory_region tss_mem
= {
4745 .slot
= TSS_PRIVATE_MEMSLOT
,
4746 .guest_phys_addr
= addr
,
4747 .memory_size
= PAGE_SIZE
* 3,
4751 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4754 kvm
->arch
.tss_addr
= addr
;
4755 if (!init_rmode_tss(kvm
))
4761 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4766 * Update instruction length as we may reinject the exception
4767 * from user space while in guest debugging mode.
4769 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4770 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4771 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4775 if (vcpu
->guest_debug
&
4776 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4793 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4794 int vec
, u32 err_code
)
4797 * Instruction with address size override prefix opcode 0x67
4798 * Cause the #SS fault with 0 error code in VM86 mode.
4800 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4801 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4802 if (vcpu
->arch
.halt_request
) {
4803 vcpu
->arch
.halt_request
= 0;
4804 return kvm_emulate_halt(vcpu
);
4812 * Forward all other exceptions that are valid in real mode.
4813 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4814 * the required debugging infrastructure rework.
4816 kvm_queue_exception(vcpu
, vec
);
4821 * Trigger machine check on the host. We assume all the MSRs are already set up
4822 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4823 * We pass a fake environment to the machine check handler because we want
4824 * the guest to be always treated like user space, no matter what context
4825 * it used internally.
4827 static void kvm_machine_check(void)
4829 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4830 struct pt_regs regs
= {
4831 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4832 .flags
= X86_EFLAGS_IF
,
4835 do_machine_check(®s
, 0);
4839 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4841 /* already handled by vcpu_run */
4845 static int handle_exception(struct kvm_vcpu
*vcpu
)
4847 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4848 struct kvm_run
*kvm_run
= vcpu
->run
;
4849 u32 intr_info
, ex_no
, error_code
;
4850 unsigned long cr2
, rip
, dr6
;
4852 enum emulation_result er
;
4854 vect_info
= vmx
->idt_vectoring_info
;
4855 intr_info
= vmx
->exit_intr_info
;
4857 if (is_machine_check(intr_info
))
4858 return handle_machine_check(vcpu
);
4860 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4861 return 1; /* already handled by vmx_vcpu_run() */
4863 if (is_no_device(intr_info
)) {
4864 vmx_fpu_activate(vcpu
);
4868 if (is_invalid_opcode(intr_info
)) {
4869 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4870 if (er
!= EMULATE_DONE
)
4871 kvm_queue_exception(vcpu
, UD_VECTOR
);
4876 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4877 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4880 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4881 * MMIO, it is better to report an internal error.
4882 * See the comments in vmx_handle_exit.
4884 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4885 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4886 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4887 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4888 vcpu
->run
->internal
.ndata
= 2;
4889 vcpu
->run
->internal
.data
[0] = vect_info
;
4890 vcpu
->run
->internal
.data
[1] = intr_info
;
4894 if (is_page_fault(intr_info
)) {
4895 /* EPT won't cause page fault directly */
4897 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4898 trace_kvm_page_fault(cr2
, error_code
);
4900 if (kvm_event_needs_reinjection(vcpu
))
4901 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4902 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4905 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4907 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4908 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4912 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4913 if (!(vcpu
->guest_debug
&
4914 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4915 vcpu
->arch
.dr6
&= ~15;
4916 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
4917 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
4918 skip_emulated_instruction(vcpu
);
4920 kvm_queue_exception(vcpu
, DB_VECTOR
);
4923 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4924 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4928 * Update instruction length as we may reinject #BP from
4929 * user space while in guest debugging mode. Reading it for
4930 * #DB as well causes no harm, it is not used in that case.
4932 vmx
->vcpu
.arch
.event_exit_inst_len
=
4933 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4934 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4935 rip
= kvm_rip_read(vcpu
);
4936 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4937 kvm_run
->debug
.arch
.exception
= ex_no
;
4940 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4941 kvm_run
->ex
.exception
= ex_no
;
4942 kvm_run
->ex
.error_code
= error_code
;
4948 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4950 ++vcpu
->stat
.irq_exits
;
4954 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4956 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4960 static int handle_io(struct kvm_vcpu
*vcpu
)
4962 unsigned long exit_qualification
;
4963 int size
, in
, string
;
4966 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4967 string
= (exit_qualification
& 16) != 0;
4968 in
= (exit_qualification
& 8) != 0;
4970 ++vcpu
->stat
.io_exits
;
4973 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4975 port
= exit_qualification
>> 16;
4976 size
= (exit_qualification
& 7) + 1;
4977 skip_emulated_instruction(vcpu
);
4979 return kvm_fast_pio_out(vcpu
, size
, port
);
4983 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4986 * Patch in the VMCALL instruction:
4988 hypercall
[0] = 0x0f;
4989 hypercall
[1] = 0x01;
4990 hypercall
[2] = 0xc1;
4993 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4995 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4997 if (nested_vmx_secondary_ctls_high
&
4998 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4999 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5000 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5001 return (val
& always_on
) == always_on
;
5004 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5005 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5007 if (is_guest_mode(vcpu
)) {
5008 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5009 unsigned long orig_val
= val
;
5012 * We get here when L2 changed cr0 in a way that did not change
5013 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5014 * but did change L0 shadowed bits. So we first calculate the
5015 * effective cr0 value that L1 would like to write into the
5016 * hardware. It consists of the L2-owned bits from the new
5017 * value combined with the L1-owned bits from L1's guest_cr0.
5019 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5020 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5022 if (!nested_cr0_valid(vmcs12
, val
))
5025 if (kvm_set_cr0(vcpu
, val
))
5027 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5030 if (to_vmx(vcpu
)->nested
.vmxon
&&
5031 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5033 return kvm_set_cr0(vcpu
, val
);
5037 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5039 if (is_guest_mode(vcpu
)) {
5040 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5041 unsigned long orig_val
= val
;
5043 /* analogously to handle_set_cr0 */
5044 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5045 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5046 if (kvm_set_cr4(vcpu
, val
))
5048 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5051 return kvm_set_cr4(vcpu
, val
);
5054 /* called to set cr0 as approriate for clts instruction exit. */
5055 static void handle_clts(struct kvm_vcpu
*vcpu
)
5057 if (is_guest_mode(vcpu
)) {
5059 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5060 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5061 * just pretend it's off (also in arch.cr0 for fpu_activate).
5063 vmcs_writel(CR0_READ_SHADOW
,
5064 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5065 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5067 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5070 static int handle_cr(struct kvm_vcpu
*vcpu
)
5072 unsigned long exit_qualification
, val
;
5077 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5078 cr
= exit_qualification
& 15;
5079 reg
= (exit_qualification
>> 8) & 15;
5080 switch ((exit_qualification
>> 4) & 3) {
5081 case 0: /* mov to cr */
5082 val
= kvm_register_readl(vcpu
, reg
);
5083 trace_kvm_cr_write(cr
, val
);
5086 err
= handle_set_cr0(vcpu
, val
);
5087 kvm_complete_insn_gp(vcpu
, err
);
5090 err
= kvm_set_cr3(vcpu
, val
);
5091 kvm_complete_insn_gp(vcpu
, err
);
5094 err
= handle_set_cr4(vcpu
, val
);
5095 kvm_complete_insn_gp(vcpu
, err
);
5098 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5100 err
= kvm_set_cr8(vcpu
, cr8
);
5101 kvm_complete_insn_gp(vcpu
, err
);
5102 if (irqchip_in_kernel(vcpu
->kvm
))
5104 if (cr8_prev
<= cr8
)
5106 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5113 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5114 skip_emulated_instruction(vcpu
);
5115 vmx_fpu_activate(vcpu
);
5117 case 1: /*mov from cr*/
5120 val
= kvm_read_cr3(vcpu
);
5121 kvm_register_write(vcpu
, reg
, val
);
5122 trace_kvm_cr_read(cr
, val
);
5123 skip_emulated_instruction(vcpu
);
5126 val
= kvm_get_cr8(vcpu
);
5127 kvm_register_write(vcpu
, reg
, val
);
5128 trace_kvm_cr_read(cr
, val
);
5129 skip_emulated_instruction(vcpu
);
5134 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5135 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5136 kvm_lmsw(vcpu
, val
);
5138 skip_emulated_instruction(vcpu
);
5143 vcpu
->run
->exit_reason
= 0;
5144 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5145 (int)(exit_qualification
>> 4) & 3, cr
);
5149 static int handle_dr(struct kvm_vcpu
*vcpu
)
5151 unsigned long exit_qualification
;
5154 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5155 if (!kvm_require_cpl(vcpu
, 0))
5157 dr
= vmcs_readl(GUEST_DR7
);
5160 * As the vm-exit takes precedence over the debug trap, we
5161 * need to emulate the latter, either for the host or the
5162 * guest debugging itself.
5164 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5165 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5166 vcpu
->run
->debug
.arch
.dr7
= dr
;
5167 vcpu
->run
->debug
.arch
.pc
=
5168 vmcs_readl(GUEST_CS_BASE
) +
5169 vmcs_readl(GUEST_RIP
);
5170 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5171 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5174 vcpu
->arch
.dr7
&= ~DR7_GD
;
5175 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5176 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5177 kvm_queue_exception(vcpu
, DB_VECTOR
);
5182 if (vcpu
->guest_debug
== 0) {
5183 u32 cpu_based_vm_exec_control
;
5185 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5186 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5190 * No more DR vmexits; force a reload of the debug registers
5191 * and reenter on this instruction. The next vmexit will
5192 * retrieve the full state of the debug registers.
5194 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5198 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5199 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5200 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5201 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5204 if (kvm_get_dr(vcpu
, dr
, &val
))
5206 kvm_register_write(vcpu
, reg
, val
);
5208 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5211 skip_emulated_instruction(vcpu
);
5215 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5217 return vcpu
->arch
.dr6
;
5220 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5224 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5226 u32 cpu_based_vm_exec_control
;
5228 get_debugreg(vcpu
->arch
.db
[0], 0);
5229 get_debugreg(vcpu
->arch
.db
[1], 1);
5230 get_debugreg(vcpu
->arch
.db
[2], 2);
5231 get_debugreg(vcpu
->arch
.db
[3], 3);
5232 get_debugreg(vcpu
->arch
.dr6
, 6);
5233 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5235 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5237 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5238 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5239 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5242 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5244 vmcs_writel(GUEST_DR7
, val
);
5247 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5249 kvm_emulate_cpuid(vcpu
);
5253 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5255 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5258 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5259 trace_kvm_msr_read_ex(ecx
);
5260 kvm_inject_gp(vcpu
, 0);
5264 trace_kvm_msr_read(ecx
, data
);
5266 /* FIXME: handling of bits 32:63 of rax, rdx */
5267 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5268 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5269 skip_emulated_instruction(vcpu
);
5273 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5275 struct msr_data msr
;
5276 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5277 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5278 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5282 msr
.host_initiated
= false;
5283 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5284 trace_kvm_msr_write_ex(ecx
, data
);
5285 kvm_inject_gp(vcpu
, 0);
5289 trace_kvm_msr_write(ecx
, data
);
5290 skip_emulated_instruction(vcpu
);
5294 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5296 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5300 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5302 u32 cpu_based_vm_exec_control
;
5304 /* clear pending irq */
5305 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5306 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5309 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5311 ++vcpu
->stat
.irq_window_exits
;
5314 * If the user space waits to inject interrupts, exit as soon as
5317 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5318 vcpu
->run
->request_interrupt_window
&&
5319 !kvm_cpu_has_interrupt(vcpu
)) {
5320 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5326 static int handle_halt(struct kvm_vcpu
*vcpu
)
5328 skip_emulated_instruction(vcpu
);
5329 return kvm_emulate_halt(vcpu
);
5332 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5334 skip_emulated_instruction(vcpu
);
5335 kvm_emulate_hypercall(vcpu
);
5339 static int handle_invd(struct kvm_vcpu
*vcpu
)
5341 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5344 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5346 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5348 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5349 skip_emulated_instruction(vcpu
);
5353 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5357 err
= kvm_rdpmc(vcpu
);
5358 kvm_complete_insn_gp(vcpu
, err
);
5363 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5365 skip_emulated_instruction(vcpu
);
5366 kvm_emulate_wbinvd(vcpu
);
5370 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5372 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5373 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5375 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5376 skip_emulated_instruction(vcpu
);
5380 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5382 if (likely(fasteoi
)) {
5383 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5384 int access_type
, offset
;
5386 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5387 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5389 * Sane guest uses MOV to write EOI, with written value
5390 * not cared. So make a short-circuit here by avoiding
5391 * heavy instruction emulation.
5393 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5394 (offset
== APIC_EOI
)) {
5395 kvm_lapic_set_eoi(vcpu
);
5396 skip_emulated_instruction(vcpu
);
5400 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5403 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5405 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5406 int vector
= exit_qualification
& 0xff;
5408 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5409 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5413 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5415 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5416 u32 offset
= exit_qualification
& 0xfff;
5418 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5419 kvm_apic_write_nodecode(vcpu
, offset
);
5423 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5426 unsigned long exit_qualification
;
5427 bool has_error_code
= false;
5430 int reason
, type
, idt_v
, idt_index
;
5432 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5433 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5434 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5436 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5438 reason
= (u32
)exit_qualification
>> 30;
5439 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5441 case INTR_TYPE_NMI_INTR
:
5442 vcpu
->arch
.nmi_injected
= false;
5443 vmx_set_nmi_mask(vcpu
, true);
5445 case INTR_TYPE_EXT_INTR
:
5446 case INTR_TYPE_SOFT_INTR
:
5447 kvm_clear_interrupt_queue(vcpu
);
5449 case INTR_TYPE_HARD_EXCEPTION
:
5450 if (vmx
->idt_vectoring_info
&
5451 VECTORING_INFO_DELIVER_CODE_MASK
) {
5452 has_error_code
= true;
5454 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5457 case INTR_TYPE_SOFT_EXCEPTION
:
5458 kvm_clear_exception_queue(vcpu
);
5464 tss_selector
= exit_qualification
;
5466 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5467 type
!= INTR_TYPE_EXT_INTR
&&
5468 type
!= INTR_TYPE_NMI_INTR
))
5469 skip_emulated_instruction(vcpu
);
5471 if (kvm_task_switch(vcpu
, tss_selector
,
5472 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5473 has_error_code
, error_code
) == EMULATE_FAIL
) {
5474 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5475 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5476 vcpu
->run
->internal
.ndata
= 0;
5480 /* clear all local breakpoint enable flags */
5481 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x55);
5484 * TODO: What about debug traps on tss switch?
5485 * Are we supposed to inject them and update dr6?
5491 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5493 unsigned long exit_qualification
;
5498 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5500 gla_validity
= (exit_qualification
>> 7) & 0x3;
5501 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5502 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5503 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5505 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5506 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5507 (long unsigned int)exit_qualification
);
5508 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5509 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5514 * EPT violation happened while executing iret from NMI,
5515 * "blocked by NMI" bit has to be set before next VM entry.
5516 * There are errata that may cause this bit to not be set:
5519 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5520 cpu_has_virtual_nmis() &&
5521 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5522 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5524 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5525 trace_kvm_page_fault(gpa
, exit_qualification
);
5527 /* It is a write fault? */
5528 error_code
= exit_qualification
& (1U << 1);
5529 /* It is a fetch fault? */
5530 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5531 /* ept page table is present? */
5532 error_code
|= (exit_qualification
>> 3) & 0x1;
5534 vcpu
->arch
.exit_qualification
= exit_qualification
;
5536 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5539 static u64
ept_rsvd_mask(u64 spte
, int level
)
5544 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5545 mask
|= (1ULL << i
);
5548 /* bits 7:3 reserved */
5550 else if (spte
& (1ULL << 7))
5552 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5553 * level == 1 if the hypervisor is using the ignored bit 7.
5555 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5557 /* bits 6:3 reserved */
5563 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5566 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5568 /* 010b (write-only) */
5569 WARN_ON((spte
& 0x7) == 0x2);
5571 /* 110b (write/execute) */
5572 WARN_ON((spte
& 0x7) == 0x6);
5574 /* 100b (execute-only) and value not supported by logical processor */
5575 if (!cpu_has_vmx_ept_execute_only())
5576 WARN_ON((spte
& 0x7) == 0x4);
5580 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5582 if (rsvd_bits
!= 0) {
5583 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5584 __func__
, rsvd_bits
);
5588 /* bits 5:3 are _not_ reserved for large page or leaf page */
5589 if ((rsvd_bits
& 0x38) == 0) {
5590 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5592 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5593 ept_mem_type
== 7) {
5594 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5595 __func__
, ept_mem_type
);
5602 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5605 int nr_sptes
, i
, ret
;
5608 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5609 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5610 skip_emulated_instruction(vcpu
);
5614 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5615 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5616 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5619 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5620 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5622 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5625 /* It is the real ept misconfig */
5626 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5627 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5629 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5631 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5632 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5634 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5635 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5640 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5642 u32 cpu_based_vm_exec_control
;
5644 /* clear pending NMI */
5645 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5646 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5648 ++vcpu
->stat
.nmi_window_exits
;
5649 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5654 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5656 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5657 enum emulation_result err
= EMULATE_DONE
;
5660 bool intr_window_requested
;
5661 unsigned count
= 130;
5663 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5664 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5666 while (vmx
->emulation_required
&& count
-- != 0) {
5667 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5668 return handle_interrupt_window(&vmx
->vcpu
);
5670 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5673 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5675 if (err
== EMULATE_USER_EXIT
) {
5676 ++vcpu
->stat
.mmio_exits
;
5681 if (err
!= EMULATE_DONE
) {
5682 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5683 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5684 vcpu
->run
->internal
.ndata
= 0;
5688 if (vcpu
->arch
.halt_request
) {
5689 vcpu
->arch
.halt_request
= 0;
5690 ret
= kvm_emulate_halt(vcpu
);
5694 if (signal_pending(current
))
5704 static int __grow_ple_window(int val
)
5706 if (ple_window_grow
< 1)
5709 val
= min(val
, ple_window_actual_max
);
5711 if (ple_window_grow
< ple_window
)
5712 val
*= ple_window_grow
;
5714 val
+= ple_window_grow
;
5719 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5724 if (modifier
< ple_window
)
5729 return max(val
, minimum
);
5732 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5734 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5735 int old
= vmx
->ple_window
;
5737 vmx
->ple_window
= __grow_ple_window(old
);
5739 if (vmx
->ple_window
!= old
)
5740 vmx
->ple_window_dirty
= true;
5742 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5745 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5747 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5748 int old
= vmx
->ple_window
;
5750 vmx
->ple_window
= __shrink_ple_window(old
,
5751 ple_window_shrink
, ple_window
);
5753 if (vmx
->ple_window
!= old
)
5754 vmx
->ple_window_dirty
= true;
5756 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5760 * ple_window_actual_max is computed to be one grow_ple_window() below
5761 * ple_window_max. (See __grow_ple_window for the reason.)
5762 * This prevents overflows, because ple_window_max is int.
5763 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5765 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5767 static void update_ple_window_actual_max(void)
5769 ple_window_actual_max
=
5770 __shrink_ple_window(max(ple_window_max
, ple_window
),
5771 ple_window_grow
, INT_MIN
);
5775 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5776 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5778 static int handle_pause(struct kvm_vcpu
*vcpu
)
5781 grow_ple_window(vcpu
);
5783 skip_emulated_instruction(vcpu
);
5784 kvm_vcpu_on_spin(vcpu
);
5789 static int handle_nop(struct kvm_vcpu
*vcpu
)
5791 skip_emulated_instruction(vcpu
);
5795 static int handle_mwait(struct kvm_vcpu
*vcpu
)
5797 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
5798 return handle_nop(vcpu
);
5801 static int handle_monitor(struct kvm_vcpu
*vcpu
)
5803 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
5804 return handle_nop(vcpu
);
5808 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5809 * We could reuse a single VMCS for all the L2 guests, but we also want the
5810 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5811 * allows keeping them loaded on the processor, and in the future will allow
5812 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5813 * every entry if they never change.
5814 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5815 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5817 * The following functions allocate and free a vmcs02 in this pool.
5820 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5821 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5823 struct vmcs02_list
*item
;
5824 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5825 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5826 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5827 return &item
->vmcs02
;
5830 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5831 /* Recycle the least recently used VMCS. */
5832 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5833 struct vmcs02_list
, list
);
5834 item
->vmptr
= vmx
->nested
.current_vmptr
;
5835 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5836 return &item
->vmcs02
;
5839 /* Create a new VMCS */
5840 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5843 item
->vmcs02
.vmcs
= alloc_vmcs();
5844 if (!item
->vmcs02
.vmcs
) {
5848 loaded_vmcs_init(&item
->vmcs02
);
5849 item
->vmptr
= vmx
->nested
.current_vmptr
;
5850 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5851 vmx
->nested
.vmcs02_num
++;
5852 return &item
->vmcs02
;
5855 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5856 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5858 struct vmcs02_list
*item
;
5859 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5860 if (item
->vmptr
== vmptr
) {
5861 free_loaded_vmcs(&item
->vmcs02
);
5862 list_del(&item
->list
);
5864 vmx
->nested
.vmcs02_num
--;
5870 * Free all VMCSs saved for this vcpu, except the one pointed by
5871 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5872 * must be &vmx->vmcs01.
5874 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5876 struct vmcs02_list
*item
, *n
;
5878 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
5879 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5881 * Something will leak if the above WARN triggers. Better than
5884 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
5887 free_loaded_vmcs(&item
->vmcs02
);
5888 list_del(&item
->list
);
5890 vmx
->nested
.vmcs02_num
--;
5895 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5896 * set the success or error code of an emulated VMX instruction, as specified
5897 * by Vol 2B, VMX Instruction Reference, "Conventions".
5899 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5901 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5902 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5903 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5906 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5908 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5909 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5910 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5914 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5915 u32 vm_instruction_error
)
5917 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5919 * failValid writes the error number to the current VMCS, which
5920 * can't be done there isn't a current VMCS.
5922 nested_vmx_failInvalid(vcpu
);
5925 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5926 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5927 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5929 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5931 * We don't need to force a shadow sync because
5932 * VM_INSTRUCTION_ERROR is not shadowed
5936 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
5938 struct vcpu_vmx
*vmx
=
5939 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
5941 vmx
->nested
.preemption_timer_expired
= true;
5942 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5943 kvm_vcpu_kick(&vmx
->vcpu
);
5945 return HRTIMER_NORESTART
;
5949 * Decode the memory-address operand of a vmx instruction, as recorded on an
5950 * exit caused by such an instruction (run by a guest hypervisor).
5951 * On success, returns 0. When the operand is invalid, returns 1 and throws
5954 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5955 unsigned long exit_qualification
,
5956 u32 vmx_instruction_info
, gva_t
*ret
)
5959 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5960 * Execution", on an exit, vmx_instruction_info holds most of the
5961 * addressing components of the operand. Only the displacement part
5962 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5963 * For how an actual address is calculated from all these components,
5964 * refer to Vol. 1, "Operand Addressing".
5966 int scaling
= vmx_instruction_info
& 3;
5967 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5968 bool is_reg
= vmx_instruction_info
& (1u << 10);
5969 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5970 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5971 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5972 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5973 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5976 kvm_queue_exception(vcpu
, UD_VECTOR
);
5980 /* Addr = segment_base + offset */
5981 /* offset = base + [index * scale] + displacement */
5982 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5984 *ret
+= kvm_register_read(vcpu
, base_reg
);
5986 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5987 *ret
+= exit_qualification
; /* holds the displacement */
5989 if (addr_size
== 1) /* 32 bit */
5993 * TODO: throw #GP (and return 1) in various cases that the VM*
5994 * instructions require it - e.g., offset beyond segment limit,
5995 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5996 * address, and so on. Currently these are not checked.
6002 * This function performs the various checks including
6003 * - if it's 4KB aligned
6004 * - No bits beyond the physical address width are set
6005 * - Returns 0 on success or else 1
6006 * (Intel SDM Section 30.3)
6008 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6013 struct x86_exception e
;
6015 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6016 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6018 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6019 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6022 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6023 sizeof(vmptr
), &e
)) {
6024 kvm_inject_page_fault(vcpu
, &e
);
6028 switch (exit_reason
) {
6029 case EXIT_REASON_VMON
:
6032 * The first 4 bytes of VMXON region contain the supported
6033 * VMCS revision identifier
6035 * Note - IA32_VMX_BASIC[48] will never be 1
6036 * for the nested case;
6037 * which replaces physical address width with 32
6040 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6041 nested_vmx_failInvalid(vcpu
);
6042 skip_emulated_instruction(vcpu
);
6046 page
= nested_get_page(vcpu
, vmptr
);
6048 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6049 nested_vmx_failInvalid(vcpu
);
6051 skip_emulated_instruction(vcpu
);
6055 vmx
->nested
.vmxon_ptr
= vmptr
;
6057 case EXIT_REASON_VMCLEAR
:
6058 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6059 nested_vmx_failValid(vcpu
,
6060 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6061 skip_emulated_instruction(vcpu
);
6065 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6066 nested_vmx_failValid(vcpu
,
6067 VMXERR_VMCLEAR_VMXON_POINTER
);
6068 skip_emulated_instruction(vcpu
);
6072 case EXIT_REASON_VMPTRLD
:
6073 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6074 nested_vmx_failValid(vcpu
,
6075 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6076 skip_emulated_instruction(vcpu
);
6080 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6081 nested_vmx_failValid(vcpu
,
6082 VMXERR_VMCLEAR_VMXON_POINTER
);
6083 skip_emulated_instruction(vcpu
);
6088 return 1; /* shouldn't happen */
6097 * Emulate the VMXON instruction.
6098 * Currently, we just remember that VMX is active, and do not save or even
6099 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6100 * do not currently need to store anything in that guest-allocated memory
6101 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6102 * argument is different from the VMXON pointer (which the spec says they do).
6104 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6106 struct kvm_segment cs
;
6107 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6108 struct vmcs
*shadow_vmcs
;
6109 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6110 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6112 /* The Intel VMX Instruction Reference lists a bunch of bits that
6113 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6114 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6115 * Otherwise, we should fail with #UD. We test these now:
6117 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6118 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6119 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6120 kvm_queue_exception(vcpu
, UD_VECTOR
);
6124 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6125 if (is_long_mode(vcpu
) && !cs
.l
) {
6126 kvm_queue_exception(vcpu
, UD_VECTOR
);
6130 if (vmx_get_cpl(vcpu
)) {
6131 kvm_inject_gp(vcpu
, 0);
6135 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6138 if (vmx
->nested
.vmxon
) {
6139 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6140 skip_emulated_instruction(vcpu
);
6144 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6145 != VMXON_NEEDED_FEATURES
) {
6146 kvm_inject_gp(vcpu
, 0);
6150 if (enable_shadow_vmcs
) {
6151 shadow_vmcs
= alloc_vmcs();
6154 /* mark vmcs as shadow */
6155 shadow_vmcs
->revision_id
|= (1u << 31);
6156 /* init shadow vmcs */
6157 vmcs_clear(shadow_vmcs
);
6158 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6161 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6162 vmx
->nested
.vmcs02_num
= 0;
6164 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6166 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6168 vmx
->nested
.vmxon
= true;
6170 skip_emulated_instruction(vcpu
);
6171 nested_vmx_succeed(vcpu
);
6176 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6177 * for running VMX instructions (except VMXON, whose prerequisites are
6178 * slightly different). It also specifies what exception to inject otherwise.
6180 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6182 struct kvm_segment cs
;
6183 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6185 if (!vmx
->nested
.vmxon
) {
6186 kvm_queue_exception(vcpu
, UD_VECTOR
);
6190 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6191 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6192 (is_long_mode(vcpu
) && !cs
.l
)) {
6193 kvm_queue_exception(vcpu
, UD_VECTOR
);
6197 if (vmx_get_cpl(vcpu
)) {
6198 kvm_inject_gp(vcpu
, 0);
6205 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6208 if (vmx
->nested
.current_vmptr
== -1ull)
6211 /* current_vmptr and current_vmcs12 are always set/reset together */
6212 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6215 if (enable_shadow_vmcs
) {
6216 /* copy to memory all shadowed fields in case
6217 they were modified */
6218 copy_shadow_to_vmcs12(vmx
);
6219 vmx
->nested
.sync_shadow_vmcs
= false;
6220 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6221 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6222 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6223 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6225 kunmap(vmx
->nested
.current_vmcs12_page
);
6226 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6227 vmx
->nested
.current_vmptr
= -1ull;
6228 vmx
->nested
.current_vmcs12
= NULL
;
6232 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6233 * just stops using VMX.
6235 static void free_nested(struct vcpu_vmx
*vmx
)
6237 if (!vmx
->nested
.vmxon
)
6240 vmx
->nested
.vmxon
= false;
6241 nested_release_vmcs12(vmx
);
6242 if (enable_shadow_vmcs
)
6243 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6244 /* Unpin physical memory we referred to in current vmcs02 */
6245 if (vmx
->nested
.apic_access_page
) {
6246 nested_release_page(vmx
->nested
.apic_access_page
);
6247 vmx
->nested
.apic_access_page
= 0;
6250 nested_free_all_saved_vmcss(vmx
);
6253 /* Emulate the VMXOFF instruction */
6254 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6256 if (!nested_vmx_check_permission(vcpu
))
6258 free_nested(to_vmx(vcpu
));
6259 skip_emulated_instruction(vcpu
);
6260 nested_vmx_succeed(vcpu
);
6264 /* Emulate the VMCLEAR instruction */
6265 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6267 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6269 struct vmcs12
*vmcs12
;
6272 if (!nested_vmx_check_permission(vcpu
))
6275 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6278 if (vmptr
== vmx
->nested
.current_vmptr
)
6279 nested_release_vmcs12(vmx
);
6281 page
= nested_get_page(vcpu
, vmptr
);
6284 * For accurate processor emulation, VMCLEAR beyond available
6285 * physical memory should do nothing at all. However, it is
6286 * possible that a nested vmx bug, not a guest hypervisor bug,
6287 * resulted in this case, so let's shut down before doing any
6290 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6293 vmcs12
= kmap(page
);
6294 vmcs12
->launch_state
= 0;
6296 nested_release_page(page
);
6298 nested_free_vmcs02(vmx
, vmptr
);
6300 skip_emulated_instruction(vcpu
);
6301 nested_vmx_succeed(vcpu
);
6305 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6307 /* Emulate the VMLAUNCH instruction */
6308 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6310 return nested_vmx_run(vcpu
, true);
6313 /* Emulate the VMRESUME instruction */
6314 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6317 return nested_vmx_run(vcpu
, false);
6320 enum vmcs_field_type
{
6321 VMCS_FIELD_TYPE_U16
= 0,
6322 VMCS_FIELD_TYPE_U64
= 1,
6323 VMCS_FIELD_TYPE_U32
= 2,
6324 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6327 static inline int vmcs_field_type(unsigned long field
)
6329 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6330 return VMCS_FIELD_TYPE_U32
;
6331 return (field
>> 13) & 0x3 ;
6334 static inline int vmcs_field_readonly(unsigned long field
)
6336 return (((field
>> 10) & 0x3) == 1);
6340 * Read a vmcs12 field. Since these can have varying lengths and we return
6341 * one type, we chose the biggest type (u64) and zero-extend the return value
6342 * to that size. Note that the caller, handle_vmread, might need to use only
6343 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6344 * 64-bit fields are to be returned).
6346 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6347 unsigned long field
, u64
*ret
)
6349 short offset
= vmcs_field_to_offset(field
);
6355 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6357 switch (vmcs_field_type(field
)) {
6358 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6359 *ret
= *((natural_width
*)p
);
6361 case VMCS_FIELD_TYPE_U16
:
6364 case VMCS_FIELD_TYPE_U32
:
6367 case VMCS_FIELD_TYPE_U64
:
6371 return 0; /* can never happen. */
6376 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6377 unsigned long field
, u64 field_value
){
6378 short offset
= vmcs_field_to_offset(field
);
6379 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6383 switch (vmcs_field_type(field
)) {
6384 case VMCS_FIELD_TYPE_U16
:
6385 *(u16
*)p
= field_value
;
6387 case VMCS_FIELD_TYPE_U32
:
6388 *(u32
*)p
= field_value
;
6390 case VMCS_FIELD_TYPE_U64
:
6391 *(u64
*)p
= field_value
;
6393 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6394 *(natural_width
*)p
= field_value
;
6397 return false; /* can never happen. */
6402 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6405 unsigned long field
;
6407 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6408 const unsigned long *fields
= shadow_read_write_fields
;
6409 const int num_fields
= max_shadow_read_write_fields
;
6411 vmcs_load(shadow_vmcs
);
6413 for (i
= 0; i
< num_fields
; i
++) {
6415 switch (vmcs_field_type(field
)) {
6416 case VMCS_FIELD_TYPE_U16
:
6417 field_value
= vmcs_read16(field
);
6419 case VMCS_FIELD_TYPE_U32
:
6420 field_value
= vmcs_read32(field
);
6422 case VMCS_FIELD_TYPE_U64
:
6423 field_value
= vmcs_read64(field
);
6425 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6426 field_value
= vmcs_readl(field
);
6429 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6432 vmcs_clear(shadow_vmcs
);
6433 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6436 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6438 const unsigned long *fields
[] = {
6439 shadow_read_write_fields
,
6440 shadow_read_only_fields
6442 const int max_fields
[] = {
6443 max_shadow_read_write_fields
,
6444 max_shadow_read_only_fields
6447 unsigned long field
;
6448 u64 field_value
= 0;
6449 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6451 vmcs_load(shadow_vmcs
);
6453 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6454 for (i
= 0; i
< max_fields
[q
]; i
++) {
6455 field
= fields
[q
][i
];
6456 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6458 switch (vmcs_field_type(field
)) {
6459 case VMCS_FIELD_TYPE_U16
:
6460 vmcs_write16(field
, (u16
)field_value
);
6462 case VMCS_FIELD_TYPE_U32
:
6463 vmcs_write32(field
, (u32
)field_value
);
6465 case VMCS_FIELD_TYPE_U64
:
6466 vmcs_write64(field
, (u64
)field_value
);
6468 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6469 vmcs_writel(field
, (long)field_value
);
6475 vmcs_clear(shadow_vmcs
);
6476 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6480 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6481 * used before) all generate the same failure when it is missing.
6483 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6485 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6486 if (vmx
->nested
.current_vmptr
== -1ull) {
6487 nested_vmx_failInvalid(vcpu
);
6488 skip_emulated_instruction(vcpu
);
6494 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6496 unsigned long field
;
6498 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6499 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6502 if (!nested_vmx_check_permission(vcpu
) ||
6503 !nested_vmx_check_vmcs12(vcpu
))
6506 /* Decode instruction info and find the field to read */
6507 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6508 /* Read the field, zero-extended to a u64 field_value */
6509 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6510 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6511 skip_emulated_instruction(vcpu
);
6515 * Now copy part of this value to register or memory, as requested.
6516 * Note that the number of bits actually copied is 32 or 64 depending
6517 * on the guest's mode (32 or 64 bit), not on the given field's length.
6519 if (vmx_instruction_info
& (1u << 10)) {
6520 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6523 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6524 vmx_instruction_info
, &gva
))
6526 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6527 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6528 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6531 nested_vmx_succeed(vcpu
);
6532 skip_emulated_instruction(vcpu
);
6537 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6539 unsigned long field
;
6541 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6542 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6543 /* The value to write might be 32 or 64 bits, depending on L1's long
6544 * mode, and eventually we need to write that into a field of several
6545 * possible lengths. The code below first zero-extends the value to 64
6546 * bit (field_value), and then copies only the approriate number of
6547 * bits into the vmcs12 field.
6549 u64 field_value
= 0;
6550 struct x86_exception e
;
6552 if (!nested_vmx_check_permission(vcpu
) ||
6553 !nested_vmx_check_vmcs12(vcpu
))
6556 if (vmx_instruction_info
& (1u << 10))
6557 field_value
= kvm_register_readl(vcpu
,
6558 (((vmx_instruction_info
) >> 3) & 0xf));
6560 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6561 vmx_instruction_info
, &gva
))
6563 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6564 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
6565 kvm_inject_page_fault(vcpu
, &e
);
6571 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6572 if (vmcs_field_readonly(field
)) {
6573 nested_vmx_failValid(vcpu
,
6574 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6575 skip_emulated_instruction(vcpu
);
6579 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6580 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6581 skip_emulated_instruction(vcpu
);
6585 nested_vmx_succeed(vcpu
);
6586 skip_emulated_instruction(vcpu
);
6590 /* Emulate the VMPTRLD instruction */
6591 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6593 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6597 if (!nested_vmx_check_permission(vcpu
))
6600 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6603 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6604 struct vmcs12
*new_vmcs12
;
6606 page
= nested_get_page(vcpu
, vmptr
);
6608 nested_vmx_failInvalid(vcpu
);
6609 skip_emulated_instruction(vcpu
);
6612 new_vmcs12
= kmap(page
);
6613 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6615 nested_release_page_clean(page
);
6616 nested_vmx_failValid(vcpu
,
6617 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6618 skip_emulated_instruction(vcpu
);
6622 nested_release_vmcs12(vmx
);
6623 vmx
->nested
.current_vmptr
= vmptr
;
6624 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6625 vmx
->nested
.current_vmcs12_page
= page
;
6626 if (enable_shadow_vmcs
) {
6627 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6628 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6629 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6630 vmcs_write64(VMCS_LINK_POINTER
,
6631 __pa(vmx
->nested
.current_shadow_vmcs
));
6632 vmx
->nested
.sync_shadow_vmcs
= true;
6636 nested_vmx_succeed(vcpu
);
6637 skip_emulated_instruction(vcpu
);
6641 /* Emulate the VMPTRST instruction */
6642 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6644 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6645 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6647 struct x86_exception e
;
6649 if (!nested_vmx_check_permission(vcpu
))
6652 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6653 vmx_instruction_info
, &vmcs_gva
))
6655 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6656 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6657 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6659 kvm_inject_page_fault(vcpu
, &e
);
6662 nested_vmx_succeed(vcpu
);
6663 skip_emulated_instruction(vcpu
);
6667 /* Emulate the INVEPT instruction */
6668 static int handle_invept(struct kvm_vcpu
*vcpu
)
6670 u32 vmx_instruction_info
, types
;
6673 struct x86_exception e
;
6678 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6679 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6680 kvm_queue_exception(vcpu
, UD_VECTOR
);
6684 if (!nested_vmx_check_permission(vcpu
))
6687 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6688 kvm_queue_exception(vcpu
, UD_VECTOR
);
6692 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6693 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6695 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6697 if (!(types
& (1UL << type
))) {
6698 nested_vmx_failValid(vcpu
,
6699 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6703 /* According to the Intel VMX instruction reference, the memory
6704 * operand is read even if it isn't needed (e.g., for type==global)
6706 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6707 vmx_instruction_info
, &gva
))
6709 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6710 sizeof(operand
), &e
)) {
6711 kvm_inject_page_fault(vcpu
, &e
);
6716 case VMX_EPT_EXTENT_GLOBAL
:
6717 kvm_mmu_sync_roots(vcpu
);
6718 kvm_mmu_flush_tlb(vcpu
);
6719 nested_vmx_succeed(vcpu
);
6722 /* Trap single context invalidation invept calls */
6727 skip_emulated_instruction(vcpu
);
6732 * The exit handlers return 1 if the exit was handled fully and guest execution
6733 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6734 * to be done to userspace and return 0.
6736 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6737 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6738 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6739 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6740 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6741 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6742 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6743 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6744 [EXIT_REASON_CPUID
] = handle_cpuid
,
6745 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6746 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6747 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6748 [EXIT_REASON_HLT
] = handle_halt
,
6749 [EXIT_REASON_INVD
] = handle_invd
,
6750 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6751 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6752 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6753 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6754 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6755 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6756 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6757 [EXIT_REASON_VMREAD
] = handle_vmread
,
6758 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6759 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6760 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6761 [EXIT_REASON_VMON
] = handle_vmon
,
6762 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6763 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6764 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6765 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6766 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6767 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6768 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6769 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6770 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6771 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6772 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6773 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
6774 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
6775 [EXIT_REASON_INVEPT
] = handle_invept
,
6778 static const int kvm_vmx_max_exit_handlers
=
6779 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6781 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6782 struct vmcs12
*vmcs12
)
6784 unsigned long exit_qualification
;
6785 gpa_t bitmap
, last_bitmap
;
6790 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6791 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6793 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6795 port
= exit_qualification
>> 16;
6796 size
= (exit_qualification
& 7) + 1;
6798 last_bitmap
= (gpa_t
)-1;
6803 bitmap
= vmcs12
->io_bitmap_a
;
6804 else if (port
< 0x10000)
6805 bitmap
= vmcs12
->io_bitmap_b
;
6808 bitmap
+= (port
& 0x7fff) / 8;
6810 if (last_bitmap
!= bitmap
)
6811 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6813 if (b
& (1 << (port
& 7)))
6818 last_bitmap
= bitmap
;
6825 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6826 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6827 * disinterest in the current event (read or write a specific MSR) by using an
6828 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6830 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6831 struct vmcs12
*vmcs12
, u32 exit_reason
)
6833 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6836 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6840 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6841 * for the four combinations of read/write and low/high MSR numbers.
6842 * First we need to figure out which of the four to use:
6844 bitmap
= vmcs12
->msr_bitmap
;
6845 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6847 if (msr_index
>= 0xc0000000) {
6848 msr_index
-= 0xc0000000;
6852 /* Then read the msr_index'th bit from this bitmap: */
6853 if (msr_index
< 1024*8) {
6855 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6857 return 1 & (b
>> (msr_index
& 7));
6859 return 1; /* let L1 handle the wrong parameter */
6863 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6864 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6865 * intercept (via guest_host_mask etc.) the current event.
6867 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6868 struct vmcs12
*vmcs12
)
6870 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6871 int cr
= exit_qualification
& 15;
6872 int reg
= (exit_qualification
>> 8) & 15;
6873 unsigned long val
= kvm_register_readl(vcpu
, reg
);
6875 switch ((exit_qualification
>> 4) & 3) {
6876 case 0: /* mov to cr */
6879 if (vmcs12
->cr0_guest_host_mask
&
6880 (val
^ vmcs12
->cr0_read_shadow
))
6884 if ((vmcs12
->cr3_target_count
>= 1 &&
6885 vmcs12
->cr3_target_value0
== val
) ||
6886 (vmcs12
->cr3_target_count
>= 2 &&
6887 vmcs12
->cr3_target_value1
== val
) ||
6888 (vmcs12
->cr3_target_count
>= 3 &&
6889 vmcs12
->cr3_target_value2
== val
) ||
6890 (vmcs12
->cr3_target_count
>= 4 &&
6891 vmcs12
->cr3_target_value3
== val
))
6893 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6897 if (vmcs12
->cr4_guest_host_mask
&
6898 (vmcs12
->cr4_read_shadow
^ val
))
6902 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6908 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6909 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6912 case 1: /* mov from cr */
6915 if (vmcs12
->cpu_based_vm_exec_control
&
6916 CPU_BASED_CR3_STORE_EXITING
)
6920 if (vmcs12
->cpu_based_vm_exec_control
&
6921 CPU_BASED_CR8_STORE_EXITING
)
6928 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6929 * cr0. Other attempted changes are ignored, with no exit.
6931 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6932 (val
^ vmcs12
->cr0_read_shadow
))
6934 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6935 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6944 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6945 * should handle it ourselves in L0 (and then continue L2). Only call this
6946 * when in is_guest_mode (L2).
6948 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6950 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6951 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6952 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6953 u32 exit_reason
= vmx
->exit_reason
;
6955 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6956 vmcs_readl(EXIT_QUALIFICATION
),
6957 vmx
->idt_vectoring_info
,
6959 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6962 if (vmx
->nested
.nested_run_pending
)
6965 if (unlikely(vmx
->fail
)) {
6966 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6967 vmcs_read32(VM_INSTRUCTION_ERROR
));
6971 switch (exit_reason
) {
6972 case EXIT_REASON_EXCEPTION_NMI
:
6973 if (!is_exception(intr_info
))
6975 else if (is_page_fault(intr_info
))
6977 else if (is_no_device(intr_info
) &&
6978 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
6980 return vmcs12
->exception_bitmap
&
6981 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6982 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6984 case EXIT_REASON_TRIPLE_FAULT
:
6986 case EXIT_REASON_PENDING_INTERRUPT
:
6987 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6988 case EXIT_REASON_NMI_WINDOW
:
6989 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6990 case EXIT_REASON_TASK_SWITCH
:
6992 case EXIT_REASON_CPUID
:
6994 case EXIT_REASON_HLT
:
6995 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6996 case EXIT_REASON_INVD
:
6998 case EXIT_REASON_INVLPG
:
6999 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7000 case EXIT_REASON_RDPMC
:
7001 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7002 case EXIT_REASON_RDTSC
:
7003 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7004 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7005 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7006 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7007 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7008 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7009 case EXIT_REASON_INVEPT
:
7011 * VMX instructions trap unconditionally. This allows L1 to
7012 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7015 case EXIT_REASON_CR_ACCESS
:
7016 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7017 case EXIT_REASON_DR_ACCESS
:
7018 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7019 case EXIT_REASON_IO_INSTRUCTION
:
7020 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7021 case EXIT_REASON_MSR_READ
:
7022 case EXIT_REASON_MSR_WRITE
:
7023 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7024 case EXIT_REASON_INVALID_STATE
:
7026 case EXIT_REASON_MWAIT_INSTRUCTION
:
7027 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7028 case EXIT_REASON_MONITOR_INSTRUCTION
:
7029 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7030 case EXIT_REASON_PAUSE_INSTRUCTION
:
7031 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7032 nested_cpu_has2(vmcs12
,
7033 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7034 case EXIT_REASON_MCE_DURING_VMENTRY
:
7036 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7038 case EXIT_REASON_APIC_ACCESS
:
7039 return nested_cpu_has2(vmcs12
,
7040 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7041 case EXIT_REASON_EPT_VIOLATION
:
7043 * L0 always deals with the EPT violation. If nested EPT is
7044 * used, and the nested mmu code discovers that the address is
7045 * missing in the guest EPT table (EPT12), the EPT violation
7046 * will be injected with nested_ept_inject_page_fault()
7049 case EXIT_REASON_EPT_MISCONFIG
:
7051 * L2 never uses directly L1's EPT, but rather L0's own EPT
7052 * table (shadow on EPT) or a merged EPT table that L0 built
7053 * (EPT on EPT). So any problems with the structure of the
7054 * table is L0's fault.
7057 case EXIT_REASON_WBINVD
:
7058 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7059 case EXIT_REASON_XSETBV
:
7066 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7068 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7069 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7073 * The guest has exited. See if we can fix it or if we need userspace
7076 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7078 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7079 u32 exit_reason
= vmx
->exit_reason
;
7080 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7082 /* If guest state is invalid, start emulating */
7083 if (vmx
->emulation_required
)
7084 return handle_invalid_guest_state(vcpu
);
7086 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7087 nested_vmx_vmexit(vcpu
, exit_reason
,
7088 vmcs_read32(VM_EXIT_INTR_INFO
),
7089 vmcs_readl(EXIT_QUALIFICATION
));
7093 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7094 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7095 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7100 if (unlikely(vmx
->fail
)) {
7101 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7102 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7103 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7109 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7110 * delivery event since it indicates guest is accessing MMIO.
7111 * The vm-exit can be triggered again after return to guest that
7112 * will cause infinite loop.
7114 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7115 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7116 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7117 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7118 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7119 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7120 vcpu
->run
->internal
.ndata
= 2;
7121 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7122 vcpu
->run
->internal
.data
[1] = exit_reason
;
7126 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7127 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7128 get_vmcs12(vcpu
))))) {
7129 if (vmx_interrupt_allowed(vcpu
)) {
7130 vmx
->soft_vnmi_blocked
= 0;
7131 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7132 vcpu
->arch
.nmi_pending
) {
7134 * This CPU don't support us in finding the end of an
7135 * NMI-blocked window if the guest runs with IRQs
7136 * disabled. So we pull the trigger after 1 s of
7137 * futile waiting, but inform the user about this.
7139 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7140 "state on VCPU %d after 1 s timeout\n",
7141 __func__
, vcpu
->vcpu_id
);
7142 vmx
->soft_vnmi_blocked
= 0;
7146 if (exit_reason
< kvm_vmx_max_exit_handlers
7147 && kvm_vmx_exit_handlers
[exit_reason
])
7148 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7150 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
7151 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
7156 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7158 if (irr
== -1 || tpr
< irr
) {
7159 vmcs_write32(TPR_THRESHOLD
, 0);
7163 vmcs_write32(TPR_THRESHOLD
, irr
);
7166 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7168 u32 sec_exec_control
;
7171 * There is not point to enable virtualize x2apic without enable
7174 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7175 !vmx_vm_has_apicv(vcpu
->kvm
))
7178 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7181 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7184 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7185 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7187 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7188 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7190 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7192 vmx_set_msr_bitmap(vcpu
);
7195 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7200 if (!vmx_vm_has_apicv(kvm
))
7206 status
= vmcs_read16(GUEST_INTR_STATUS
);
7211 vmcs_write16(GUEST_INTR_STATUS
, status
);
7215 static void vmx_set_rvi(int vector
)
7220 status
= vmcs_read16(GUEST_INTR_STATUS
);
7221 old
= (u8
)status
& 0xff;
7222 if ((u8
)vector
!= old
) {
7224 status
|= (u8
)vector
;
7225 vmcs_write16(GUEST_INTR_STATUS
, status
);
7229 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7235 * If a vmexit is needed, vmx_check_nested_events handles it.
7237 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
7240 if (!is_guest_mode(vcpu
)) {
7241 vmx_set_rvi(max_irr
);
7246 * Fall back to pre-APICv interrupt injection since L2
7247 * is run without virtual interrupt delivery.
7249 if (!kvm_event_needs_reinjection(vcpu
) &&
7250 vmx_interrupt_allowed(vcpu
)) {
7251 kvm_queue_interrupt(vcpu
, max_irr
, false);
7252 vmx_inject_irq(vcpu
);
7256 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7258 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7261 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7262 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7263 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7264 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7267 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7271 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7272 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7275 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7276 exit_intr_info
= vmx
->exit_intr_info
;
7278 /* Handle machine checks before interrupts are enabled */
7279 if (is_machine_check(exit_intr_info
))
7280 kvm_machine_check();
7282 /* We need to handle NMIs before interrupts are enabled */
7283 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7284 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7285 kvm_before_handle_nmi(&vmx
->vcpu
);
7287 kvm_after_handle_nmi(&vmx
->vcpu
);
7291 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7293 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7296 * If external interrupt exists, IF bit is set in rflags/eflags on the
7297 * interrupt stack frame, and interrupt will be enabled on a return
7298 * from interrupt handler.
7300 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7301 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7302 unsigned int vector
;
7303 unsigned long entry
;
7305 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7306 #ifdef CONFIG_X86_64
7310 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7311 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7312 entry
= gate_offset(*desc
);
7314 #ifdef CONFIG_X86_64
7315 "mov %%" _ASM_SP
", %[sp]\n\t"
7316 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7321 "orl $0x200, (%%" _ASM_SP
")\n\t"
7322 __ASM_SIZE(push
) " $%c[cs]\n\t"
7323 "call *%[entry]\n\t"
7325 #ifdef CONFIG_X86_64
7330 [ss
]"i"(__KERNEL_DS
),
7331 [cs
]"i"(__KERNEL_CS
)
7337 static bool vmx_mpx_supported(void)
7339 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7340 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7343 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7348 bool idtv_info_valid
;
7350 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7352 if (cpu_has_virtual_nmis()) {
7353 if (vmx
->nmi_known_unmasked
)
7356 * Can't use vmx->exit_intr_info since we're not sure what
7357 * the exit reason is.
7359 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7360 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7361 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7363 * SDM 3: 27.7.1.2 (September 2008)
7364 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7365 * a guest IRET fault.
7366 * SDM 3: 23.2.2 (September 2008)
7367 * Bit 12 is undefined in any of the following cases:
7368 * If the VM exit sets the valid bit in the IDT-vectoring
7369 * information field.
7370 * If the VM exit is due to a double fault.
7372 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7373 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7374 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7375 GUEST_INTR_STATE_NMI
);
7377 vmx
->nmi_known_unmasked
=
7378 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7379 & GUEST_INTR_STATE_NMI
);
7380 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7381 vmx
->vnmi_blocked_time
+=
7382 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7385 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7386 u32 idt_vectoring_info
,
7387 int instr_len_field
,
7388 int error_code_field
)
7392 bool idtv_info_valid
;
7394 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7396 vcpu
->arch
.nmi_injected
= false;
7397 kvm_clear_exception_queue(vcpu
);
7398 kvm_clear_interrupt_queue(vcpu
);
7400 if (!idtv_info_valid
)
7403 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7405 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7406 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7409 case INTR_TYPE_NMI_INTR
:
7410 vcpu
->arch
.nmi_injected
= true;
7412 * SDM 3: 27.7.1.2 (September 2008)
7413 * Clear bit "block by NMI" before VM entry if a NMI
7416 vmx_set_nmi_mask(vcpu
, false);
7418 case INTR_TYPE_SOFT_EXCEPTION
:
7419 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7421 case INTR_TYPE_HARD_EXCEPTION
:
7422 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7423 u32 err
= vmcs_read32(error_code_field
);
7424 kvm_requeue_exception_e(vcpu
, vector
, err
);
7426 kvm_requeue_exception(vcpu
, vector
);
7428 case INTR_TYPE_SOFT_INTR
:
7429 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7431 case INTR_TYPE_EXT_INTR
:
7432 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7439 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7441 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7442 VM_EXIT_INSTRUCTION_LEN
,
7443 IDT_VECTORING_ERROR_CODE
);
7446 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7448 __vmx_complete_interrupts(vcpu
,
7449 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7450 VM_ENTRY_INSTRUCTION_LEN
,
7451 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7456 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7459 struct perf_guest_switch_msr
*msrs
;
7461 msrs
= perf_guest_get_msrs(&nr_msrs
);
7466 for (i
= 0; i
< nr_msrs
; i
++)
7467 if (msrs
[i
].host
== msrs
[i
].guest
)
7468 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7470 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7474 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7477 unsigned long debugctlmsr
;
7479 /* Record the guest's net vcpu time for enforced NMI injections. */
7480 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7481 vmx
->entry_time
= ktime_get();
7483 /* Don't enter VMX if guest state is invalid, let the exit handler
7484 start emulation until we arrive back to a valid state */
7485 if (vmx
->emulation_required
)
7488 if (vmx
->ple_window_dirty
) {
7489 vmx
->ple_window_dirty
= false;
7490 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
7493 if (vmx
->nested
.sync_shadow_vmcs
) {
7494 copy_vmcs12_to_shadow(vmx
);
7495 vmx
->nested
.sync_shadow_vmcs
= false;
7498 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7499 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7500 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7501 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7503 /* When single-stepping over STI and MOV SS, we must clear the
7504 * corresponding interruptibility bits in the guest state. Otherwise
7505 * vmentry fails as it then expects bit 14 (BS) in pending debug
7506 * exceptions being set, but that's not correct for the guest debugging
7508 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7509 vmx_set_interrupt_shadow(vcpu
, 0);
7511 atomic_switch_perf_msrs(vmx
);
7512 debugctlmsr
= get_debugctlmsr();
7514 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7516 /* Store host registers */
7517 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7518 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7519 "push %%" _ASM_CX
" \n\t"
7520 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7522 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7523 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7525 /* Reload cr2 if changed */
7526 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7527 "mov %%cr2, %%" _ASM_DX
" \n\t"
7528 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7530 "mov %%" _ASM_AX
", %%cr2 \n\t"
7532 /* Check if vmlaunch of vmresume is needed */
7533 "cmpl $0, %c[launched](%0) \n\t"
7534 /* Load guest registers. Don't clobber flags. */
7535 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7536 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7537 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7538 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7539 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7540 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7541 #ifdef CONFIG_X86_64
7542 "mov %c[r8](%0), %%r8 \n\t"
7543 "mov %c[r9](%0), %%r9 \n\t"
7544 "mov %c[r10](%0), %%r10 \n\t"
7545 "mov %c[r11](%0), %%r11 \n\t"
7546 "mov %c[r12](%0), %%r12 \n\t"
7547 "mov %c[r13](%0), %%r13 \n\t"
7548 "mov %c[r14](%0), %%r14 \n\t"
7549 "mov %c[r15](%0), %%r15 \n\t"
7551 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7553 /* Enter guest mode */
7555 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7557 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7559 /* Save guest registers, load host registers, keep flags */
7560 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7562 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7563 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7564 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7565 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7566 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7567 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7568 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7569 #ifdef CONFIG_X86_64
7570 "mov %%r8, %c[r8](%0) \n\t"
7571 "mov %%r9, %c[r9](%0) \n\t"
7572 "mov %%r10, %c[r10](%0) \n\t"
7573 "mov %%r11, %c[r11](%0) \n\t"
7574 "mov %%r12, %c[r12](%0) \n\t"
7575 "mov %%r13, %c[r13](%0) \n\t"
7576 "mov %%r14, %c[r14](%0) \n\t"
7577 "mov %%r15, %c[r15](%0) \n\t"
7579 "mov %%cr2, %%" _ASM_AX
" \n\t"
7580 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7582 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7583 "setbe %c[fail](%0) \n\t"
7584 ".pushsection .rodata \n\t"
7585 ".global vmx_return \n\t"
7586 "vmx_return: " _ASM_PTR
" 2b \n\t"
7588 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7589 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7590 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7591 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7592 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7593 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7594 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7595 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7596 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7597 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7598 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7599 #ifdef CONFIG_X86_64
7600 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7601 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7602 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7603 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7604 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7605 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7606 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7607 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7609 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7610 [wordsize
]"i"(sizeof(ulong
))
7612 #ifdef CONFIG_X86_64
7613 , "rax", "rbx", "rdi", "rsi"
7614 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7616 , "eax", "ebx", "edi", "esi"
7620 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7622 update_debugctlmsr(debugctlmsr
);
7624 #ifndef CONFIG_X86_64
7626 * The sysexit path does not restore ds/es, so we must set them to
7627 * a reasonable value ourselves.
7629 * We can't defer this to vmx_load_host_state() since that function
7630 * may be executed in interrupt context, which saves and restore segments
7631 * around it, nullifying its effect.
7633 loadsegment(ds
, __USER_DS
);
7634 loadsegment(es
, __USER_DS
);
7637 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7638 | (1 << VCPU_EXREG_RFLAGS
)
7639 | (1 << VCPU_EXREG_PDPTR
)
7640 | (1 << VCPU_EXREG_SEGMENTS
)
7641 | (1 << VCPU_EXREG_CR3
));
7642 vcpu
->arch
.regs_dirty
= 0;
7644 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7646 vmx
->loaded_vmcs
->launched
= 1;
7648 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7649 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7652 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7653 * we did not inject a still-pending event to L1 now because of
7654 * nested_run_pending, we need to re-enable this bit.
7656 if (vmx
->nested
.nested_run_pending
)
7657 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7659 vmx
->nested
.nested_run_pending
= 0;
7661 vmx_complete_atomic_exit(vmx
);
7662 vmx_recover_nmi_blocking(vmx
);
7663 vmx_complete_interrupts(vmx
);
7666 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
7668 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7671 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
7675 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7677 vmx_vcpu_load(vcpu
, cpu
);
7682 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7687 leave_guest_mode(vcpu
);
7688 vmx_load_vmcs01(vcpu
);
7690 free_loaded_vmcs(vmx
->loaded_vmcs
);
7691 kfree(vmx
->guest_msrs
);
7692 kvm_vcpu_uninit(vcpu
);
7693 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7696 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7699 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7703 return ERR_PTR(-ENOMEM
);
7707 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7711 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7712 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
7716 if (!vmx
->guest_msrs
) {
7720 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7721 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7722 if (!vmx
->loaded_vmcs
->vmcs
)
7725 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7726 loaded_vmcs_init(vmx
->loaded_vmcs
);
7731 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7732 vmx
->vcpu
.cpu
= cpu
;
7733 err
= vmx_vcpu_setup(vmx
);
7734 vmx_vcpu_put(&vmx
->vcpu
);
7738 if (vm_need_virtualize_apic_accesses(kvm
)) {
7739 err
= alloc_apic_access_page(kvm
);
7745 if (!kvm
->arch
.ept_identity_map_addr
)
7746 kvm
->arch
.ept_identity_map_addr
=
7747 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7749 if (alloc_identity_pagetable(kvm
) != 0)
7751 if (!init_rmode_identity_map(kvm
))
7755 vmx
->nested
.current_vmptr
= -1ull;
7756 vmx
->nested
.current_vmcs12
= NULL
;
7761 free_loaded_vmcs(vmx
->loaded_vmcs
);
7763 kfree(vmx
->guest_msrs
);
7765 kvm_vcpu_uninit(&vmx
->vcpu
);
7768 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7769 return ERR_PTR(err
);
7772 static void __init
vmx_check_processor_compat(void *rtn
)
7774 struct vmcs_config vmcs_conf
;
7777 if (setup_vmcs_config(&vmcs_conf
) < 0)
7779 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7780 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7781 smp_processor_id());
7786 static int get_ept_level(void)
7788 return VMX_EPT_DEFAULT_GAW
+ 1;
7791 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7795 /* For VT-d and EPT combination
7796 * 1. MMIO: always map as UC
7798 * a. VT-d without snooping control feature: can't guarantee the
7799 * result, try to trust guest.
7800 * b. VT-d with snooping control feature: snooping control feature of
7801 * VT-d engine can guarantee the cache correctness. Just set it
7802 * to WB to keep consistent with host. So the same as item 3.
7803 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7804 * consistent with host MTRR
7807 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7808 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7809 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7810 VMX_EPT_MT_EPTE_SHIFT
;
7812 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7818 static int vmx_get_lpage_level(void)
7820 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7821 return PT_DIRECTORY_LEVEL
;
7823 /* For shadow and EPT supported 1GB page */
7824 return PT_PDPE_LEVEL
;
7827 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7829 struct kvm_cpuid_entry2
*best
;
7830 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7833 vmx
->rdtscp_enabled
= false;
7834 if (vmx_rdtscp_supported()) {
7835 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7836 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7837 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7838 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7839 vmx
->rdtscp_enabled
= true;
7841 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7842 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7848 /* Exposing INVPCID only when PCID is exposed */
7849 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7850 if (vmx_invpcid_supported() &&
7851 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7852 guest_cpuid_has_pcid(vcpu
)) {
7853 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7854 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7855 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7858 if (cpu_has_secondary_exec_ctrls()) {
7859 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7860 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7861 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7865 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7869 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7871 if (func
== 1 && nested
)
7872 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7875 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7876 struct x86_exception
*fault
)
7878 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7881 if (fault
->error_code
& PFERR_RSVD_MASK
)
7882 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7884 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7885 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7886 vmcs12
->guest_physical_address
= fault
->address
;
7889 /* Callbacks for nested_ept_init_mmu_context: */
7891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7893 /* return the page table to be shadowed - in our case, EPT12 */
7894 return get_vmcs12(vcpu
)->ept_pointer
;
7897 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7899 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7900 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7902 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7903 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7904 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7906 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7909 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7911 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7914 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7915 struct x86_exception
*fault
)
7917 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7919 WARN_ON(!is_guest_mode(vcpu
));
7921 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7922 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7923 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7924 vmcs_read32(VM_EXIT_INTR_INFO
),
7925 vmcs_readl(EXIT_QUALIFICATION
));
7927 kvm_inject_page_fault(vcpu
, fault
);
7930 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
7931 struct vmcs12
*vmcs12
)
7933 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7935 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
7936 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
))
7937 /*TODO: Also verify bits beyond physical address width are 0*/
7941 * Translate L1 physical address to host physical
7942 * address for vmcs02. Keep the page pinned, so this
7943 * physical address remains valid. We keep a reference
7944 * to it so we can release it later.
7946 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7947 nested_release_page(vmx
->nested
.apic_access_page
);
7948 vmx
->nested
.apic_access_page
=
7949 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7954 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
7956 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
7957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7959 if (vcpu
->arch
.virtual_tsc_khz
== 0)
7962 /* Make sure short timeouts reliably trigger an immediate vmexit.
7963 * hrtimer_start does not guarantee this. */
7964 if (preemption_timeout
<= 1) {
7965 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
7969 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
7970 preemption_timeout
*= 1000000;
7971 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
7972 hrtimer_start(&vmx
->nested
.preemption_timer
,
7973 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
7977 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7978 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7979 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7980 * guest in a way that will both be appropriate to L1's requests, and our
7981 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7982 * function also has additional necessary side-effects, like setting various
7983 * vcpu->arch fields.
7985 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7990 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7991 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7992 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7993 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7994 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7995 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7996 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7997 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7998 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7999 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
8000 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
8001 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
8002 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
8003 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
8004 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
8005 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
8006 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
8007 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
8008 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
8009 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
8010 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
8011 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
8012 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
8013 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
8014 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
8015 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
8016 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
8017 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
8018 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
8019 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
8020 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
8021 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
8022 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
8023 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
8024 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
8025 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
8027 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
8028 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
8029 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
8031 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
8032 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
8034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
8035 vmcs12
->vm_entry_intr_info_field
);
8036 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
8037 vmcs12
->vm_entry_exception_error_code
);
8038 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
8039 vmcs12
->vm_entry_instruction_len
);
8040 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
8041 vmcs12
->guest_interruptibility_info
);
8042 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
8043 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
8044 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
8045 vmcs12
->guest_pending_dbg_exceptions
);
8046 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
8047 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
8049 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
8051 exec_control
= vmcs12
->pin_based_vm_exec_control
;
8052 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
8053 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
8054 PIN_BASED_POSTED_INTR
);
8055 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
8057 vmx
->nested
.preemption_timer_expired
= false;
8058 if (nested_cpu_has_preemption_timer(vmcs12
))
8059 vmx_start_preemption_timer(vcpu
);
8062 * Whether page-faults are trapped is determined by a combination of
8063 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8064 * If enable_ept, L0 doesn't care about page faults and we should
8065 * set all of these to L1's desires. However, if !enable_ept, L0 does
8066 * care about (at least some) page faults, and because it is not easy
8067 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8068 * to exit on each and every L2 page fault. This is done by setting
8069 * MASK=MATCH=0 and (see below) EB.PF=1.
8070 * Note that below we don't need special code to set EB.PF beyond the
8071 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8072 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8073 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8075 * A problem with this approach (when !enable_ept) is that L1 may be
8076 * injected with more page faults than it asked for. This could have
8077 * caused problems, but in practice existing hypervisors don't care.
8078 * To fix this, we will need to emulate the PFEC checking (on the L1
8079 * page tables), using walk_addr(), when injecting PFs to L1.
8081 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
8082 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
8083 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
8084 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
8086 if (cpu_has_secondary_exec_ctrls()) {
8087 exec_control
= vmx_secondary_exec_control(vmx
);
8088 if (!vmx
->rdtscp_enabled
)
8089 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8090 /* Take the following fields only from vmcs12 */
8091 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
8092 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
8093 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
8094 if (nested_cpu_has(vmcs12
,
8095 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
8096 exec_control
|= vmcs12
->secondary_vm_exec_control
;
8098 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
8100 * If translation failed, no matter: This feature asks
8101 * to exit when accessing the given address, and if it
8102 * can never be accessed, this feature won't do
8105 if (!vmx
->nested
.apic_access_page
)
8107 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8109 vmcs_write64(APIC_ACCESS_ADDR
,
8110 page_to_phys(vmx
->nested
.apic_access_page
));
8111 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
8113 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8114 vmcs_write64(APIC_ACCESS_ADDR
,
8115 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
8118 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
8123 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8124 * Some constant fields are set here by vmx_set_constant_host_state().
8125 * Other fields are different per CPU, and will be set later when
8126 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8128 vmx_set_constant_host_state(vmx
);
8131 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8132 * entry, but only if the current (host) sp changed from the value
8133 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8134 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8135 * here we just force the write to happen on entry.
8139 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
8140 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
8141 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
8142 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
8143 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
8145 * Merging of IO and MSR bitmaps not currently supported.
8146 * Rather, exit every time.
8148 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
8149 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
8150 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
8152 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
8154 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8155 * bitwise-or of what L1 wants to trap for L2, and what we want to
8156 * trap. Note that CR0.TS also needs updating - we do this later.
8158 update_exception_bitmap(vcpu
);
8159 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
8160 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8162 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8163 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8164 * bits are further modified by vmx_set_efer() below.
8166 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
8168 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8169 * emulated by vmx_set_efer(), below.
8171 vm_entry_controls_init(vmx
,
8172 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
8173 ~VM_ENTRY_IA32E_MODE
) |
8174 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
8176 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
8177 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
8178 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
8179 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
8180 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
8183 set_cr4_guest_host_mask(vmx
);
8185 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
8186 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
8188 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
8189 vmcs_write64(TSC_OFFSET
,
8190 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
8192 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8196 * Trivially support vpid by letting L2s share their parent
8197 * L1's vpid. TODO: move to a more elaborate solution, giving
8198 * each L2 its own vpid and exposing the vpid feature to L1.
8200 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
8201 vmx_flush_tlb(vcpu
);
8204 if (nested_cpu_has_ept(vmcs12
)) {
8205 kvm_mmu_unload(vcpu
);
8206 nested_ept_init_mmu_context(vcpu
);
8209 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
8210 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
8211 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
8212 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8214 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8215 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8216 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8219 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8220 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8221 * The CR0_READ_SHADOW is what L2 should have expected to read given
8222 * the specifications by L1; It's not enough to take
8223 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8224 * have more bits than L1 expected.
8226 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
8227 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
8229 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
8230 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
8232 /* shadow page tables on either EPT or shadow page tables */
8233 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
8234 kvm_mmu_reset_context(vcpu
);
8237 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
8240 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8243 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
8244 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
8245 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
8246 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
8249 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
8250 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
8254 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8255 * for running an L2 nested guest.
8257 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
8259 struct vmcs12
*vmcs12
;
8260 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8262 struct loaded_vmcs
*vmcs02
;
8265 if (!nested_vmx_check_permission(vcpu
) ||
8266 !nested_vmx_check_vmcs12(vcpu
))
8269 skip_emulated_instruction(vcpu
);
8270 vmcs12
= get_vmcs12(vcpu
);
8272 if (enable_shadow_vmcs
)
8273 copy_shadow_to_vmcs12(vmx
);
8276 * The nested entry process starts with enforcing various prerequisites
8277 * on vmcs12 as required by the Intel SDM, and act appropriately when
8278 * they fail: As the SDM explains, some conditions should cause the
8279 * instruction to fail, while others will cause the instruction to seem
8280 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8281 * To speed up the normal (success) code path, we should avoid checking
8282 * for misconfigurations which will anyway be caught by the processor
8283 * when using the merged vmcs02.
8285 if (vmcs12
->launch_state
== launch
) {
8286 nested_vmx_failValid(vcpu
,
8287 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8288 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
8292 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
8293 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
8294 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8298 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
8299 !PAGE_ALIGNED(vmcs12
->msr_bitmap
)) {
8300 /*TODO: Also verify bits beyond physical address width are 0*/
8301 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8305 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
8306 /*TODO: Also verify bits beyond physical address width are 0*/
8307 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8311 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8312 vmcs12
->vm_exit_msr_load_count
> 0 ||
8313 vmcs12
->vm_exit_msr_store_count
> 0) {
8314 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8316 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8320 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8321 nested_vmx_true_procbased_ctls_low
,
8322 nested_vmx_procbased_ctls_high
) ||
8323 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8324 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8325 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8326 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8327 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8328 nested_vmx_true_exit_ctls_low
,
8329 nested_vmx_exit_ctls_high
) ||
8330 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8331 nested_vmx_true_entry_ctls_low
,
8332 nested_vmx_entry_ctls_high
))
8334 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8338 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8339 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8340 nested_vmx_failValid(vcpu
,
8341 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8345 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8346 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8347 nested_vmx_entry_failure(vcpu
, vmcs12
,
8348 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8351 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8352 nested_vmx_entry_failure(vcpu
, vmcs12
,
8353 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8358 * If the load IA32_EFER VM-entry control is 1, the following checks
8359 * are performed on the field for the IA32_EFER MSR:
8360 * - Bits reserved in the IA32_EFER MSR must be 0.
8361 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8362 * the IA-32e mode guest VM-exit control. It must also be identical
8363 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8366 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8367 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8368 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8369 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8370 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8371 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8372 nested_vmx_entry_failure(vcpu
, vmcs12
,
8373 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8379 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8380 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8381 * the values of the LMA and LME bits in the field must each be that of
8382 * the host address-space size VM-exit control.
8384 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8385 ia32e
= (vmcs12
->vm_exit_controls
&
8386 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8387 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8388 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8389 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8390 nested_vmx_entry_failure(vcpu
, vmcs12
,
8391 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8397 * We're finally done with prerequisite checking, and can start with
8401 vmcs02
= nested_get_current_vmcs02(vmx
);
8405 enter_guest_mode(vcpu
);
8407 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8409 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
8410 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8413 vmx
->loaded_vmcs
= vmcs02
;
8415 vmx_vcpu_load(vcpu
, cpu
);
8419 vmx_segment_cache_clear(vmx
);
8421 vmcs12
->launch_state
= 1;
8423 prepare_vmcs02(vcpu
, vmcs12
);
8425 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8426 return kvm_emulate_halt(vcpu
);
8428 vmx
->nested
.nested_run_pending
= 1;
8431 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8432 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8433 * returned as far as L1 is concerned. It will only return (and set
8434 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8440 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8441 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8442 * This function returns the new value we should put in vmcs12.guest_cr0.
8443 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8444 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8445 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8446 * didn't trap the bit, because if L1 did, so would L0).
8447 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8448 * been modified by L2, and L1 knows it. So just leave the old value of
8449 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8450 * isn't relevant, because if L0 traps this bit it can set it to anything.
8451 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8452 * changed these bits, and therefore they need to be updated, but L0
8453 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8454 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8456 static inline unsigned long
8457 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8460 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8461 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8462 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8463 vcpu
->arch
.cr0_guest_owned_bits
));
8466 static inline unsigned long
8467 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8470 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8471 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8472 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8473 vcpu
->arch
.cr4_guest_owned_bits
));
8476 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8477 struct vmcs12
*vmcs12
)
8482 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8483 nr
= vcpu
->arch
.exception
.nr
;
8484 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8486 if (kvm_exception_is_soft(nr
)) {
8487 vmcs12
->vm_exit_instruction_len
=
8488 vcpu
->arch
.event_exit_inst_len
;
8489 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8491 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8493 if (vcpu
->arch
.exception
.has_error_code
) {
8494 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8495 vmcs12
->idt_vectoring_error_code
=
8496 vcpu
->arch
.exception
.error_code
;
8499 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8500 } else if (vcpu
->arch
.nmi_injected
) {
8501 vmcs12
->idt_vectoring_info_field
=
8502 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8503 } else if (vcpu
->arch
.interrupt
.pending
) {
8504 nr
= vcpu
->arch
.interrupt
.nr
;
8505 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8507 if (vcpu
->arch
.interrupt
.soft
) {
8508 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8509 vmcs12
->vm_entry_instruction_len
=
8510 vcpu
->arch
.event_exit_inst_len
;
8512 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8514 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8518 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8520 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8522 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8523 vmx
->nested
.preemption_timer_expired
) {
8524 if (vmx
->nested
.nested_run_pending
)
8526 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8530 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8531 if (vmx
->nested
.nested_run_pending
||
8532 vcpu
->arch
.interrupt
.pending
)
8534 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8535 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8536 INTR_INFO_VALID_MASK
, 0);
8538 * The NMI-triggered VM exit counts as injection:
8539 * clear this one and block further NMIs.
8541 vcpu
->arch
.nmi_pending
= 0;
8542 vmx_set_nmi_mask(vcpu
, true);
8546 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8547 nested_exit_on_intr(vcpu
)) {
8548 if (vmx
->nested
.nested_run_pending
)
8550 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8556 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8559 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8562 if (ktime_to_ns(remaining
) <= 0)
8565 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8566 do_div(value
, 1000000);
8567 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8571 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8572 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8573 * and this function updates it to reflect the changes to the guest state while
8574 * L2 was running (and perhaps made some exits which were handled directly by L0
8575 * without going back to L1), and to reflect the exit reason.
8576 * Note that we do not have to copy here all VMCS fields, just those that
8577 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8578 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8579 * which already writes to vmcs12 directly.
8581 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8582 u32 exit_reason
, u32 exit_intr_info
,
8583 unsigned long exit_qualification
)
8585 /* update guest state fields: */
8586 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8587 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8589 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8590 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8591 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8593 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8594 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8595 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8596 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8597 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8598 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8599 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8600 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8601 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8602 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8603 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8604 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8605 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8606 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8607 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8608 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8609 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8610 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8611 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8612 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8613 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8614 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8615 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8616 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8617 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8618 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8619 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8620 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8621 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8622 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8623 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8624 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8625 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8626 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8627 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8628 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8630 vmcs12
->guest_interruptibility_info
=
8631 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8632 vmcs12
->guest_pending_dbg_exceptions
=
8633 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8634 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8635 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8637 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8639 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8640 if (vmcs12
->vm_exit_controls
&
8641 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8642 vmcs12
->vmx_preemption_timer_value
=
8643 vmx_get_preemption_timer_value(vcpu
);
8644 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8648 * In some cases (usually, nested EPT), L2 is allowed to change its
8649 * own CR3 without exiting. If it has changed it, we must keep it.
8650 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8651 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8653 * Additionally, restore L2's PDPTR to vmcs12.
8656 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8657 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8658 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8659 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8660 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8663 vmcs12
->vm_entry_controls
=
8664 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8665 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8667 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
8668 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8669 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8672 /* TODO: These cannot have changed unless we have MSR bitmaps and
8673 * the relevant bit asks not to trap the change */
8674 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8675 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8676 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8677 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8678 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8679 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8680 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8681 if (vmx_mpx_supported())
8682 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8684 /* update exit information fields: */
8686 vmcs12
->vm_exit_reason
= exit_reason
;
8687 vmcs12
->exit_qualification
= exit_qualification
;
8689 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8690 if ((vmcs12
->vm_exit_intr_info
&
8691 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8692 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8693 vmcs12
->vm_exit_intr_error_code
=
8694 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8695 vmcs12
->idt_vectoring_info_field
= 0;
8696 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8697 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8699 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8700 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8701 * instead of reading the real value. */
8702 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8705 * Transfer the event that L0 or L1 may wanted to inject into
8706 * L2 to IDT_VECTORING_INFO_FIELD.
8708 vmcs12_save_pending_event(vcpu
, vmcs12
);
8712 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8713 * preserved above and would only end up incorrectly in L1.
8715 vcpu
->arch
.nmi_injected
= false;
8716 kvm_clear_exception_queue(vcpu
);
8717 kvm_clear_interrupt_queue(vcpu
);
8721 * A part of what we need to when the nested L2 guest exits and we want to
8722 * run its L1 parent, is to reset L1's guest state to the host state specified
8724 * This function is to be called not only on normal nested exit, but also on
8725 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8726 * Failures During or After Loading Guest State").
8727 * This function should be called when the active VMCS is L1's (vmcs01).
8729 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8730 struct vmcs12
*vmcs12
)
8732 struct kvm_segment seg
;
8734 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8735 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8736 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8737 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8739 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8740 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8742 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8743 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8744 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8746 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8747 * actually changed, because it depends on the current state of
8748 * fpu_active (which may have changed).
8749 * Note that vmx_set_cr0 refers to efer set above.
8751 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8753 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8754 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8755 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8757 update_exception_bitmap(vcpu
);
8758 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8759 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8762 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8763 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8765 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8766 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8768 nested_ept_uninit_mmu_context(vcpu
);
8770 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8771 kvm_mmu_reset_context(vcpu
);
8774 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8778 * Trivially support vpid by letting L2s share their parent
8779 * L1's vpid. TODO: move to a more elaborate solution, giving
8780 * each L2 its own vpid and exposing the vpid feature to L1.
8782 vmx_flush_tlb(vcpu
);
8786 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8787 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8788 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8789 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8790 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8792 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8793 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
8794 vmcs_write64(GUEST_BNDCFGS
, 0);
8796 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8797 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8798 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8800 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8801 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8802 vmcs12
->host_ia32_perf_global_ctrl
);
8804 /* Set L1 segment info according to Intel SDM
8805 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8806 seg
= (struct kvm_segment
) {
8808 .limit
= 0xFFFFFFFF,
8809 .selector
= vmcs12
->host_cs_selector
,
8815 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8819 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8820 seg
= (struct kvm_segment
) {
8822 .limit
= 0xFFFFFFFF,
8829 seg
.selector
= vmcs12
->host_ds_selector
;
8830 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8831 seg
.selector
= vmcs12
->host_es_selector
;
8832 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8833 seg
.selector
= vmcs12
->host_ss_selector
;
8834 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8835 seg
.selector
= vmcs12
->host_fs_selector
;
8836 seg
.base
= vmcs12
->host_fs_base
;
8837 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8838 seg
.selector
= vmcs12
->host_gs_selector
;
8839 seg
.base
= vmcs12
->host_gs_base
;
8840 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8841 seg
= (struct kvm_segment
) {
8842 .base
= vmcs12
->host_tr_base
,
8844 .selector
= vmcs12
->host_tr_selector
,
8848 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8850 kvm_set_dr(vcpu
, 7, 0x400);
8851 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8855 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8856 * and modify vmcs12 to make it see what it would expect to see there if
8857 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8859 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8861 unsigned long exit_qualification
)
8863 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8864 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8866 /* trying to cancel vmlaunch/vmresume is a bug */
8867 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8869 leave_guest_mode(vcpu
);
8870 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8871 exit_qualification
);
8873 vmx_load_vmcs01(vcpu
);
8875 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
8876 && nested_exit_intr_ack_set(vcpu
)) {
8877 int irq
= kvm_cpu_get_interrupt(vcpu
);
8879 vmcs12
->vm_exit_intr_info
= irq
|
8880 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
8883 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8884 vmcs12
->exit_qualification
,
8885 vmcs12
->idt_vectoring_info_field
,
8886 vmcs12
->vm_exit_intr_info
,
8887 vmcs12
->vm_exit_intr_error_code
,
8890 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8891 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8892 vmx_segment_cache_clear(vmx
);
8894 /* if no vmcs02 cache requested, remove the one we used */
8895 if (VMCS02_POOL_SIZE
== 0)
8896 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8898 load_vmcs12_host_state(vcpu
, vmcs12
);
8900 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8901 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8903 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8906 /* Unpin physical memory we referred to in vmcs02 */
8907 if (vmx
->nested
.apic_access_page
) {
8908 nested_release_page(vmx
->nested
.apic_access_page
);
8909 vmx
->nested
.apic_access_page
= 0;
8913 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8914 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8915 * success or failure flag accordingly.
8917 if (unlikely(vmx
->fail
)) {
8919 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8921 nested_vmx_succeed(vcpu
);
8922 if (enable_shadow_vmcs
)
8923 vmx
->nested
.sync_shadow_vmcs
= true;
8925 /* in case we halted in L2 */
8926 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
8930 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8932 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8934 if (is_guest_mode(vcpu
))
8935 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8936 free_nested(to_vmx(vcpu
));
8940 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8941 * 23.7 "VM-entry failures during or after loading guest state" (this also
8942 * lists the acceptable exit-reason and exit-qualification parameters).
8943 * It should only be called before L2 actually succeeded to run, and when
8944 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8946 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8947 struct vmcs12
*vmcs12
,
8948 u32 reason
, unsigned long qualification
)
8950 load_vmcs12_host_state(vcpu
, vmcs12
);
8951 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8952 vmcs12
->exit_qualification
= qualification
;
8953 nested_vmx_succeed(vcpu
);
8954 if (enable_shadow_vmcs
)
8955 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8958 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8959 struct x86_instruction_info
*info
,
8960 enum x86_intercept_stage stage
)
8962 return X86EMUL_CONTINUE
;
8965 void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
8968 shrink_ple_window(vcpu
);
8971 static struct kvm_x86_ops vmx_x86_ops
= {
8972 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8973 .disabled_by_bios
= vmx_disabled_by_bios
,
8974 .hardware_setup
= hardware_setup
,
8975 .hardware_unsetup
= hardware_unsetup
,
8976 .check_processor_compatibility
= vmx_check_processor_compat
,
8977 .hardware_enable
= hardware_enable
,
8978 .hardware_disable
= hardware_disable
,
8979 .cpu_has_accelerated_tpr
= report_flexpriority
,
8981 .vcpu_create
= vmx_create_vcpu
,
8982 .vcpu_free
= vmx_free_vcpu
,
8983 .vcpu_reset
= vmx_vcpu_reset
,
8985 .prepare_guest_switch
= vmx_save_host_state
,
8986 .vcpu_load
= vmx_vcpu_load
,
8987 .vcpu_put
= vmx_vcpu_put
,
8989 .update_db_bp_intercept
= update_exception_bitmap
,
8990 .get_msr
= vmx_get_msr
,
8991 .set_msr
= vmx_set_msr
,
8992 .get_segment_base
= vmx_get_segment_base
,
8993 .get_segment
= vmx_get_segment
,
8994 .set_segment
= vmx_set_segment
,
8995 .get_cpl
= vmx_get_cpl
,
8996 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8997 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8998 .decache_cr3
= vmx_decache_cr3
,
8999 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
9000 .set_cr0
= vmx_set_cr0
,
9001 .set_cr3
= vmx_set_cr3
,
9002 .set_cr4
= vmx_set_cr4
,
9003 .set_efer
= vmx_set_efer
,
9004 .get_idt
= vmx_get_idt
,
9005 .set_idt
= vmx_set_idt
,
9006 .get_gdt
= vmx_get_gdt
,
9007 .set_gdt
= vmx_set_gdt
,
9008 .get_dr6
= vmx_get_dr6
,
9009 .set_dr6
= vmx_set_dr6
,
9010 .set_dr7
= vmx_set_dr7
,
9011 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
9012 .cache_reg
= vmx_cache_reg
,
9013 .get_rflags
= vmx_get_rflags
,
9014 .set_rflags
= vmx_set_rflags
,
9015 .fpu_deactivate
= vmx_fpu_deactivate
,
9017 .tlb_flush
= vmx_flush_tlb
,
9019 .run
= vmx_vcpu_run
,
9020 .handle_exit
= vmx_handle_exit
,
9021 .skip_emulated_instruction
= skip_emulated_instruction
,
9022 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
9023 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
9024 .patch_hypercall
= vmx_patch_hypercall
,
9025 .set_irq
= vmx_inject_irq
,
9026 .set_nmi
= vmx_inject_nmi
,
9027 .queue_exception
= vmx_queue_exception
,
9028 .cancel_injection
= vmx_cancel_injection
,
9029 .interrupt_allowed
= vmx_interrupt_allowed
,
9030 .nmi_allowed
= vmx_nmi_allowed
,
9031 .get_nmi_mask
= vmx_get_nmi_mask
,
9032 .set_nmi_mask
= vmx_set_nmi_mask
,
9033 .enable_nmi_window
= enable_nmi_window
,
9034 .enable_irq_window
= enable_irq_window
,
9035 .update_cr8_intercept
= update_cr8_intercept
,
9036 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
9037 .vm_has_apicv
= vmx_vm_has_apicv
,
9038 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
9039 .hwapic_irr_update
= vmx_hwapic_irr_update
,
9040 .hwapic_isr_update
= vmx_hwapic_isr_update
,
9041 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
9042 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
9044 .set_tss_addr
= vmx_set_tss_addr
,
9045 .get_tdp_level
= get_ept_level
,
9046 .get_mt_mask
= vmx_get_mt_mask
,
9048 .get_exit_info
= vmx_get_exit_info
,
9050 .get_lpage_level
= vmx_get_lpage_level
,
9052 .cpuid_update
= vmx_cpuid_update
,
9054 .rdtscp_supported
= vmx_rdtscp_supported
,
9055 .invpcid_supported
= vmx_invpcid_supported
,
9057 .set_supported_cpuid
= vmx_set_supported_cpuid
,
9059 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
9061 .set_tsc_khz
= vmx_set_tsc_khz
,
9062 .read_tsc_offset
= vmx_read_tsc_offset
,
9063 .write_tsc_offset
= vmx_write_tsc_offset
,
9064 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
9065 .compute_tsc_offset
= vmx_compute_tsc_offset
,
9066 .read_l1_tsc
= vmx_read_l1_tsc
,
9068 .set_tdp_cr3
= vmx_set_cr3
,
9070 .check_intercept
= vmx_check_intercept
,
9071 .handle_external_intr
= vmx_handle_external_intr
,
9072 .mpx_supported
= vmx_mpx_supported
,
9074 .check_nested_events
= vmx_check_nested_events
,
9076 .sched_in
= vmx_sched_in
,
9079 static int __init
vmx_init(void)
9083 rdmsrl_safe(MSR_EFER
, &host_efer
);
9085 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
9086 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
9088 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9089 if (!vmx_io_bitmap_a
)
9094 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9095 if (!vmx_io_bitmap_b
)
9098 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9099 if (!vmx_msr_bitmap_legacy
)
9102 vmx_msr_bitmap_legacy_x2apic
=
9103 (unsigned long *)__get_free_page(GFP_KERNEL
);
9104 if (!vmx_msr_bitmap_legacy_x2apic
)
9107 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9108 if (!vmx_msr_bitmap_longmode
)
9111 vmx_msr_bitmap_longmode_x2apic
=
9112 (unsigned long *)__get_free_page(GFP_KERNEL
);
9113 if (!vmx_msr_bitmap_longmode_x2apic
)
9115 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9116 if (!vmx_vmread_bitmap
)
9119 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9120 if (!vmx_vmwrite_bitmap
)
9123 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
9124 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
9127 * Allow direct access to the PC debug port (it is often used for I/O
9128 * delays, but the vmexits simply slow things down).
9130 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
9131 clear_bit(0x80, vmx_io_bitmap_a
);
9133 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
9135 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
9136 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
9138 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
9140 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
9141 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
9146 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
9147 crash_vmclear_local_loaded_vmcss
);
9150 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
9151 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
9152 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
9153 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
9154 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
9155 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
9156 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
9158 memcpy(vmx_msr_bitmap_legacy_x2apic
,
9159 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
9160 memcpy(vmx_msr_bitmap_longmode_x2apic
,
9161 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
9164 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9165 vmx_disable_intercept_msr_read_x2apic(msr
);
9167 /* According SDM, in x2apic mode, the whole id reg is used.
9168 * But in KVM, it only use the highest eight bits. Need to
9170 vmx_enable_intercept_msr_read_x2apic(0x802);
9172 vmx_enable_intercept_msr_read_x2apic(0x839);
9174 vmx_disable_intercept_msr_write_x2apic(0x808);
9176 vmx_disable_intercept_msr_write_x2apic(0x80b);
9178 vmx_disable_intercept_msr_write_x2apic(0x83f);
9182 kvm_mmu_set_mask_ptes(0ull,
9183 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
9184 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
9185 0ull, VMX_EPT_EXECUTABLE_MASK
);
9186 ept_set_mmio_spte_mask();
9191 update_ple_window_actual_max();
9196 free_page((unsigned long)vmx_vmwrite_bitmap
);
9198 free_page((unsigned long)vmx_vmread_bitmap
);
9200 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9202 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9204 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9206 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9208 free_page((unsigned long)vmx_io_bitmap_b
);
9210 free_page((unsigned long)vmx_io_bitmap_a
);
9214 static void __exit
vmx_exit(void)
9216 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9217 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9218 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9219 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9220 free_page((unsigned long)vmx_io_bitmap_b
);
9221 free_page((unsigned long)vmx_io_bitmap_a
);
9222 free_page((unsigned long)vmx_vmwrite_bitmap
);
9223 free_page((unsigned long)vmx_vmread_bitmap
);
9226 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
9233 module_init(vmx_init
)
9234 module_exit(vmx_exit
)