2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30 #include <linux/tboot.h>
31 #include "kvm_cache_regs.h"
37 #include <asm/virtext.h>
42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44 MODULE_AUTHOR("Qumranet");
45 MODULE_LICENSE("GPL");
47 static int __read_mostly bypass_guest_pf
= 1;
48 module_param(bypass_guest_pf
, bool, S_IRUGO
);
50 static int __read_mostly enable_vpid
= 1;
51 module_param_named(vpid
, enable_vpid
, bool, 0444);
53 static int __read_mostly flexpriority_enabled
= 1;
54 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
56 static int __read_mostly enable_ept
= 1;
57 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
59 static int __read_mostly enable_unrestricted_guest
= 1;
60 module_param_named(unrestricted_guest
,
61 enable_unrestricted_guest
, bool, S_IRUGO
);
63 static int __read_mostly emulate_invalid_guest_state
= 0;
64 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
66 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
67 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
68 #define KVM_GUEST_CR0_MASK \
69 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
70 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE)
72 #define KVM_VM_CR0_ALWAYS_ON \
73 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74 #define KVM_CR4_GUEST_OWNED_BITS \
75 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
78 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
79 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
81 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
84 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
85 * ple_gap: upper bound on the amount of time between two successive
86 * executions of PAUSE in a loop. Also indicate if ple enabled.
87 * According to test, this time is usually small than 41 cycles.
88 * ple_window: upper bound on the amount of time a guest is allowed to execute
89 * in a PAUSE loop. Tests indicate that most spinlocks are held for
90 * less than 2^12 cycles
91 * Time is measured based on a counter that runs at the same rate as the TSC,
92 * refer SDM volume 3b section 21.6.13 & 22.1.3.
94 #define KVM_VMX_DEFAULT_PLE_GAP 41
95 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
96 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
97 module_param(ple_gap
, int, S_IRUGO
);
99 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
100 module_param(ple_window
, int, S_IRUGO
);
102 #define NR_AUTOLOAD_MSRS 1
110 struct shared_msr_entry
{
117 struct kvm_vcpu vcpu
;
118 struct list_head local_vcpus_link
;
119 unsigned long host_rsp
;
122 u32 idt_vectoring_info
;
123 struct shared_msr_entry
*guest_msrs
;
127 u64 msr_host_kernel_gs_base
;
128 u64 msr_guest_kernel_gs_base
;
131 struct msr_autoload
{
133 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
134 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
138 u16 fs_sel
, gs_sel
, ldt_sel
;
139 int gs_ldt_reload_needed
;
140 int fs_reload_needed
;
145 struct kvm_save_segment
{
150 } tr
, es
, ds
, fs
, gs
;
158 bool emulation_required
;
160 /* Support for vnmi-less CPUs */
161 int soft_vnmi_blocked
;
163 s64 vnmi_blocked_time
;
169 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
171 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
174 static int init_rmode(struct kvm
*kvm
);
175 static u64
construct_eptp(unsigned long root_hpa
);
177 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
178 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
179 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
181 static unsigned long *vmx_io_bitmap_a
;
182 static unsigned long *vmx_io_bitmap_b
;
183 static unsigned long *vmx_msr_bitmap_legacy
;
184 static unsigned long *vmx_msr_bitmap_longmode
;
186 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
187 static DEFINE_SPINLOCK(vmx_vpid_lock
);
189 static struct vmcs_config
{
193 u32 pin_based_exec_ctrl
;
194 u32 cpu_based_exec_ctrl
;
195 u32 cpu_based_2nd_exec_ctrl
;
200 static struct vmx_capability
{
205 #define VMX_SEGMENT_FIELD(seg) \
206 [VCPU_SREG_##seg] = { \
207 .selector = GUEST_##seg##_SELECTOR, \
208 .base = GUEST_##seg##_BASE, \
209 .limit = GUEST_##seg##_LIMIT, \
210 .ar_bytes = GUEST_##seg##_AR_BYTES, \
213 static struct kvm_vmx_segment_field
{
218 } kvm_vmx_segment_fields
[] = {
219 VMX_SEGMENT_FIELD(CS
),
220 VMX_SEGMENT_FIELD(DS
),
221 VMX_SEGMENT_FIELD(ES
),
222 VMX_SEGMENT_FIELD(FS
),
223 VMX_SEGMENT_FIELD(GS
),
224 VMX_SEGMENT_FIELD(SS
),
225 VMX_SEGMENT_FIELD(TR
),
226 VMX_SEGMENT_FIELD(LDTR
),
229 static u64 host_efer
;
231 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
234 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
235 * away by decrementing the array size.
237 static const u32 vmx_msr_index
[] = {
239 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
241 MSR_EFER
, MSR_TSC_AUX
, MSR_K6_STAR
,
243 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
245 static inline bool is_page_fault(u32 intr_info
)
247 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
248 INTR_INFO_VALID_MASK
)) ==
249 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
252 static inline bool is_no_device(u32 intr_info
)
254 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
255 INTR_INFO_VALID_MASK
)) ==
256 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
259 static inline bool is_invalid_opcode(u32 intr_info
)
261 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
262 INTR_INFO_VALID_MASK
)) ==
263 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
266 static inline bool is_external_interrupt(u32 intr_info
)
268 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
269 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
272 static inline bool is_machine_check(u32 intr_info
)
274 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
275 INTR_INFO_VALID_MASK
)) ==
276 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
279 static inline bool cpu_has_vmx_msr_bitmap(void)
281 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
284 static inline bool cpu_has_vmx_tpr_shadow(void)
286 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
289 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
291 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
294 static inline bool cpu_has_secondary_exec_ctrls(void)
296 return vmcs_config
.cpu_based_exec_ctrl
&
297 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
300 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
302 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
303 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
306 static inline bool cpu_has_vmx_flexpriority(void)
308 return cpu_has_vmx_tpr_shadow() &&
309 cpu_has_vmx_virtualize_apic_accesses();
312 static inline bool cpu_has_vmx_ept_execute_only(void)
314 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
317 static inline bool cpu_has_vmx_eptp_uncacheable(void)
319 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
322 static inline bool cpu_has_vmx_eptp_writeback(void)
324 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
327 static inline bool cpu_has_vmx_ept_2m_page(void)
329 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
332 static inline bool cpu_has_vmx_ept_1g_page(void)
334 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
337 static inline bool cpu_has_vmx_invept_individual_addr(void)
339 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
342 static inline bool cpu_has_vmx_invept_context(void)
344 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
347 static inline bool cpu_has_vmx_invept_global(void)
349 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
352 static inline bool cpu_has_vmx_ept(void)
354 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
355 SECONDARY_EXEC_ENABLE_EPT
;
358 static inline bool cpu_has_vmx_unrestricted_guest(void)
360 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
361 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
364 static inline bool cpu_has_vmx_ple(void)
366 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
367 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
370 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
372 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
375 static inline bool cpu_has_vmx_vpid(void)
377 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
378 SECONDARY_EXEC_ENABLE_VPID
;
381 static inline bool cpu_has_vmx_rdtscp(void)
383 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
384 SECONDARY_EXEC_RDTSCP
;
387 static inline bool cpu_has_virtual_nmis(void)
389 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
392 static inline bool report_flexpriority(void)
394 return flexpriority_enabled
;
397 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
401 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
402 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
407 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
413 } operand
= { vpid
, 0, gva
};
415 asm volatile (__ex(ASM_VMX_INVVPID
)
416 /* CF==1 or ZF==1 --> rc = -1 */
418 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
421 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
425 } operand
= {eptp
, gpa
};
427 asm volatile (__ex(ASM_VMX_INVEPT
)
428 /* CF==1 or ZF==1 --> rc = -1 */
429 "; ja 1f ; ud2 ; 1:\n"
430 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
433 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
437 i
= __find_msr_index(vmx
, msr
);
439 return &vmx
->guest_msrs
[i
];
443 static void vmcs_clear(struct vmcs
*vmcs
)
445 u64 phys_addr
= __pa(vmcs
);
448 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
449 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
452 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
456 static void __vcpu_clear(void *arg
)
458 struct vcpu_vmx
*vmx
= arg
;
459 int cpu
= raw_smp_processor_id();
461 if (vmx
->vcpu
.cpu
== cpu
)
462 vmcs_clear(vmx
->vmcs
);
463 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
464 per_cpu(current_vmcs
, cpu
) = NULL
;
465 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
466 list_del(&vmx
->local_vcpus_link
);
471 static void vcpu_clear(struct vcpu_vmx
*vmx
)
473 if (vmx
->vcpu
.cpu
== -1)
475 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
478 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
483 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
486 static inline void ept_sync_global(void)
488 if (cpu_has_vmx_invept_global())
489 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
492 static inline void ept_sync_context(u64 eptp
)
495 if (cpu_has_vmx_invept_context())
496 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
502 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
505 if (cpu_has_vmx_invept_individual_addr())
506 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
509 ept_sync_context(eptp
);
513 static unsigned long vmcs_readl(unsigned long field
)
517 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
518 : "=a"(value
) : "d"(field
) : "cc");
522 static u16
vmcs_read16(unsigned long field
)
524 return vmcs_readl(field
);
527 static u32
vmcs_read32(unsigned long field
)
529 return vmcs_readl(field
);
532 static u64
vmcs_read64(unsigned long field
)
535 return vmcs_readl(field
);
537 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
541 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
543 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
544 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
548 static void vmcs_writel(unsigned long field
, unsigned long value
)
552 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
553 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
555 vmwrite_error(field
, value
);
558 static void vmcs_write16(unsigned long field
, u16 value
)
560 vmcs_writel(field
, value
);
563 static void vmcs_write32(unsigned long field
, u32 value
)
565 vmcs_writel(field
, value
);
568 static void vmcs_write64(unsigned long field
, u64 value
)
570 vmcs_writel(field
, value
);
571 #ifndef CONFIG_X86_64
573 vmcs_writel(field
+1, value
>> 32);
577 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
579 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
582 static void vmcs_set_bits(unsigned long field
, u32 mask
)
584 vmcs_writel(field
, vmcs_readl(field
) | mask
);
587 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
591 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
592 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
593 if ((vcpu
->guest_debug
&
594 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
595 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
596 eb
|= 1u << BP_VECTOR
;
597 if (to_vmx(vcpu
)->rmode
.vm86_active
)
600 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
601 if (vcpu
->fpu_active
)
602 eb
&= ~(1u << NM_VECTOR
);
603 vmcs_write32(EXCEPTION_BITMAP
, eb
);
606 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
609 struct msr_autoload
*m
= &vmx
->msr_autoload
;
611 for (i
= 0; i
< m
->nr
; ++i
)
612 if (m
->guest
[i
].index
== msr
)
618 m
->guest
[i
] = m
->guest
[m
->nr
];
619 m
->host
[i
] = m
->host
[m
->nr
];
620 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
621 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
624 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
625 u64 guest_val
, u64 host_val
)
628 struct msr_autoload
*m
= &vmx
->msr_autoload
;
630 for (i
= 0; i
< m
->nr
; ++i
)
631 if (m
->guest
[i
].index
== msr
)
636 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
637 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
640 m
->guest
[i
].index
= msr
;
641 m
->guest
[i
].value
= guest_val
;
642 m
->host
[i
].index
= msr
;
643 m
->host
[i
].value
= host_val
;
646 static void reload_tss(void)
649 * VT restores TR but not its size. Useless.
652 struct desc_struct
*descs
;
654 native_store_gdt(&gdt
);
655 descs
= (void *)gdt
.address
;
656 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
660 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
665 guest_efer
= vmx
->vcpu
.arch
.efer
;
668 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
671 ignore_bits
= EFER_NX
| EFER_SCE
;
673 ignore_bits
|= EFER_LMA
| EFER_LME
;
674 /* SCE is meaningful only in long mode on Intel */
675 if (guest_efer
& EFER_LMA
)
676 ignore_bits
&= ~(u64
)EFER_SCE
;
678 guest_efer
&= ~ignore_bits
;
679 guest_efer
|= host_efer
& ignore_bits
;
680 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
681 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
683 clear_atomic_switch_msr(vmx
, MSR_EFER
);
684 /* On ept, can't emulate nx, and must switch nx atomically */
685 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
686 guest_efer
= vmx
->vcpu
.arch
.efer
;
687 if (!(guest_efer
& EFER_LMA
))
688 guest_efer
&= ~EFER_LME
;
689 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
696 static unsigned long segment_base(u16 selector
)
699 struct desc_struct
*d
;
700 unsigned long table_base
;
703 if (!(selector
& ~3))
706 native_store_gdt(&gdt
);
707 table_base
= gdt
.address
;
709 if (selector
& 4) { /* from ldt */
710 u16 ldt_selector
= kvm_read_ldt();
712 if (!(ldt_selector
& ~3))
715 table_base
= segment_base(ldt_selector
);
717 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
718 v
= get_desc_base(d
);
720 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
721 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
726 static inline unsigned long kvm_read_tr_base(void)
729 asm("str %0" : "=g"(tr
));
730 return segment_base(tr
);
733 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
735 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
738 if (vmx
->host_state
.loaded
)
741 vmx
->host_state
.loaded
= 1;
743 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
744 * allow segment selectors with cpl > 0 or ti == 1.
746 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
747 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
748 vmx
->host_state
.fs_sel
= kvm_read_fs();
749 if (!(vmx
->host_state
.fs_sel
& 7)) {
750 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
751 vmx
->host_state
.fs_reload_needed
= 0;
753 vmcs_write16(HOST_FS_SELECTOR
, 0);
754 vmx
->host_state
.fs_reload_needed
= 1;
756 vmx
->host_state
.gs_sel
= kvm_read_gs();
757 if (!(vmx
->host_state
.gs_sel
& 7))
758 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
760 vmcs_write16(HOST_GS_SELECTOR
, 0);
761 vmx
->host_state
.gs_ldt_reload_needed
= 1;
765 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
766 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
768 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
769 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
773 if (is_long_mode(&vmx
->vcpu
)) {
774 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
775 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
778 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
779 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
780 vmx
->guest_msrs
[i
].data
,
781 vmx
->guest_msrs
[i
].mask
);
784 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
788 if (!vmx
->host_state
.loaded
)
791 ++vmx
->vcpu
.stat
.host_state_reload
;
792 vmx
->host_state
.loaded
= 0;
793 if (vmx
->host_state
.fs_reload_needed
)
794 kvm_load_fs(vmx
->host_state
.fs_sel
);
795 if (vmx
->host_state
.gs_ldt_reload_needed
) {
796 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
798 * If we have to reload gs, we must take care to
799 * preserve our gs base.
801 local_irq_save(flags
);
802 kvm_load_gs(vmx
->host_state
.gs_sel
);
804 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
806 local_irq_restore(flags
);
810 if (is_long_mode(&vmx
->vcpu
)) {
811 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
812 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
817 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
820 __vmx_load_host_state(vmx
);
825 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
826 * vcpu mutex is already taken.
828 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
830 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
831 u64 phys_addr
= __pa(vmx
->vmcs
);
832 u64 tsc_this
, delta
, new_offset
;
834 if (vcpu
->cpu
!= cpu
) {
836 kvm_migrate_timers(vcpu
);
837 set_bit(KVM_REQ_TLB_FLUSH
, &vcpu
->requests
);
839 list_add(&vmx
->local_vcpus_link
,
840 &per_cpu(vcpus_on_cpu
, cpu
));
844 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
847 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
848 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
849 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
852 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
853 vmx
->vmcs
, phys_addr
);
856 if (vcpu
->cpu
!= cpu
) {
858 unsigned long sysenter_esp
;
862 * Linux uses per-cpu TSS and GDT, so set these when switching
865 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
866 native_store_gdt(&dt
);
867 vmcs_writel(HOST_GDTR_BASE
, dt
.address
); /* 22.2.4 */
869 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
870 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
873 * Make sure the time stamp counter is monotonous.
876 if (tsc_this
< vcpu
->arch
.host_tsc
) {
877 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
878 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
879 vmcs_write64(TSC_OFFSET
, new_offset
);
884 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
886 __vmx_load_host_state(to_vmx(vcpu
));
889 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
893 if (vcpu
->fpu_active
)
895 vcpu
->fpu_active
= 1;
896 cr0
= vmcs_readl(GUEST_CR0
);
897 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
898 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
899 vmcs_writel(GUEST_CR0
, cr0
);
900 update_exception_bitmap(vcpu
);
901 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
902 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
905 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
907 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
909 vmx_decache_cr0_guest_bits(vcpu
);
910 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
911 update_exception_bitmap(vcpu
);
912 vcpu
->arch
.cr0_guest_owned_bits
= 0;
913 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
914 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
917 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
919 unsigned long rflags
, save_rflags
;
921 rflags
= vmcs_readl(GUEST_RFLAGS
);
922 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
923 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
924 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
925 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
930 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
932 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
933 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
934 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
936 vmcs_writel(GUEST_RFLAGS
, rflags
);
939 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
941 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
944 if (interruptibility
& GUEST_INTR_STATE_STI
)
945 ret
|= KVM_X86_SHADOW_INT_STI
;
946 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
947 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
952 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
954 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
955 u32 interruptibility
= interruptibility_old
;
957 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
959 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
960 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
961 else if (mask
& KVM_X86_SHADOW_INT_STI
)
962 interruptibility
|= GUEST_INTR_STATE_STI
;
964 if ((interruptibility
!= interruptibility_old
))
965 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
968 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
972 rip
= kvm_rip_read(vcpu
);
973 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
974 kvm_rip_write(vcpu
, rip
);
976 /* skipping an emulated instruction also counts */
977 vmx_set_interrupt_shadow(vcpu
, 0);
980 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
981 bool has_error_code
, u32 error_code
,
984 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
985 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
987 if (has_error_code
) {
988 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
989 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
992 if (vmx
->rmode
.vm86_active
) {
993 vmx
->rmode
.irq
.pending
= true;
994 vmx
->rmode
.irq
.vector
= nr
;
995 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
996 if (kvm_exception_is_soft(nr
))
997 vmx
->rmode
.irq
.rip
+=
998 vmx
->vcpu
.arch
.event_exit_inst_len
;
999 intr_info
|= INTR_TYPE_SOFT_INTR
;
1000 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1001 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
1002 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
1006 if (kvm_exception_is_soft(nr
)) {
1007 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1008 vmx
->vcpu
.arch
.event_exit_inst_len
);
1009 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1011 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1013 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1016 static bool vmx_rdtscp_supported(void)
1018 return cpu_has_vmx_rdtscp();
1022 * Swap MSR entry in host/guest MSR entry array.
1024 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1026 struct shared_msr_entry tmp
;
1028 tmp
= vmx
->guest_msrs
[to
];
1029 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1030 vmx
->guest_msrs
[from
] = tmp
;
1034 * Set up the vmcs to automatically save and restore system
1035 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1036 * mode, as fiddling with msrs is very expensive.
1038 static void setup_msrs(struct vcpu_vmx
*vmx
)
1040 int save_nmsrs
, index
;
1041 unsigned long *msr_bitmap
;
1043 vmx_load_host_state(vmx
);
1045 #ifdef CONFIG_X86_64
1046 if (is_long_mode(&vmx
->vcpu
)) {
1047 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1049 move_msr_up(vmx
, index
, save_nmsrs
++);
1050 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1052 move_msr_up(vmx
, index
, save_nmsrs
++);
1053 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1055 move_msr_up(vmx
, index
, save_nmsrs
++);
1056 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1057 if (index
>= 0 && vmx
->rdtscp_enabled
)
1058 move_msr_up(vmx
, index
, save_nmsrs
++);
1060 * MSR_K6_STAR is only needed on long mode guests, and only
1061 * if efer.sce is enabled.
1063 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
1064 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1065 move_msr_up(vmx
, index
, save_nmsrs
++);
1068 index
= __find_msr_index(vmx
, MSR_EFER
);
1069 if (index
>= 0 && update_transition_efer(vmx
, index
))
1070 move_msr_up(vmx
, index
, save_nmsrs
++);
1072 vmx
->save_nmsrs
= save_nmsrs
;
1074 if (cpu_has_vmx_msr_bitmap()) {
1075 if (is_long_mode(&vmx
->vcpu
))
1076 msr_bitmap
= vmx_msr_bitmap_longmode
;
1078 msr_bitmap
= vmx_msr_bitmap_legacy
;
1080 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1085 * reads and returns guest's timestamp counter "register"
1086 * guest_tsc = host_tsc + tsc_offset -- 21.3
1088 static u64
guest_read_tsc(void)
1090 u64 host_tsc
, tsc_offset
;
1093 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1094 return host_tsc
+ tsc_offset
;
1098 * writes 'guest_tsc' into guest's timestamp counter "register"
1099 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1101 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
1103 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
1107 * Reads an msr value (of 'msr_index') into 'pdata'.
1108 * Returns 0 on success, non-0 otherwise.
1109 * Assumes vcpu_load() was already called.
1111 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1114 struct shared_msr_entry
*msr
;
1117 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1121 switch (msr_index
) {
1122 #ifdef CONFIG_X86_64
1124 data
= vmcs_readl(GUEST_FS_BASE
);
1127 data
= vmcs_readl(GUEST_GS_BASE
);
1129 case MSR_KERNEL_GS_BASE
:
1130 vmx_load_host_state(to_vmx(vcpu
));
1131 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1135 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1137 data
= guest_read_tsc();
1139 case MSR_IA32_SYSENTER_CS
:
1140 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1142 case MSR_IA32_SYSENTER_EIP
:
1143 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1145 case MSR_IA32_SYSENTER_ESP
:
1146 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1149 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1151 /* Otherwise falls through */
1153 vmx_load_host_state(to_vmx(vcpu
));
1154 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1156 vmx_load_host_state(to_vmx(vcpu
));
1160 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1168 * Writes msr value into into the appropriate "register".
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1172 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1174 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1175 struct shared_msr_entry
*msr
;
1179 switch (msr_index
) {
1181 vmx_load_host_state(vmx
);
1182 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1184 #ifdef CONFIG_X86_64
1186 vmcs_writel(GUEST_FS_BASE
, data
);
1189 vmcs_writel(GUEST_GS_BASE
, data
);
1191 case MSR_KERNEL_GS_BASE
:
1192 vmx_load_host_state(vmx
);
1193 vmx
->msr_guest_kernel_gs_base
= data
;
1196 case MSR_IA32_SYSENTER_CS
:
1197 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1199 case MSR_IA32_SYSENTER_EIP
:
1200 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1202 case MSR_IA32_SYSENTER_ESP
:
1203 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1207 guest_write_tsc(data
, host_tsc
);
1209 case MSR_IA32_CR_PAT
:
1210 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1211 vmcs_write64(GUEST_IA32_PAT
, data
);
1212 vcpu
->arch
.pat
= data
;
1215 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1218 if (!vmx
->rdtscp_enabled
)
1220 /* Check reserved bit, higher 32 bits should be zero */
1221 if ((data
>> 32) != 0)
1223 /* Otherwise falls through */
1225 msr
= find_msr_entry(vmx
, msr_index
);
1227 vmx_load_host_state(vmx
);
1231 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1237 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1239 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1242 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1245 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1247 case VCPU_EXREG_PDPTR
:
1249 ept_save_pdptrs(vcpu
);
1256 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1258 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1259 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1261 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1263 update_exception_bitmap(vcpu
);
1266 static __init
int cpu_has_kvm_support(void)
1268 return cpu_has_vmx();
1271 static __init
int vmx_disabled_by_bios(void)
1275 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1276 if (msr
& FEATURE_CONTROL_LOCKED
) {
1277 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1280 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1281 && !tboot_enabled())
1286 /* locked but not enabled */
1289 static int hardware_enable(void *garbage
)
1291 int cpu
= raw_smp_processor_id();
1292 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1295 if (read_cr4() & X86_CR4_VMXE
)
1298 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1299 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1301 test_bits
= FEATURE_CONTROL_LOCKED
;
1302 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1303 if (tboot_enabled())
1304 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
1306 if ((old
& test_bits
) != test_bits
) {
1307 /* enable and lock */
1308 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
1310 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1311 asm volatile (ASM_VMX_VMXON_RAX
1312 : : "a"(&phys_addr
), "m"(phys_addr
)
1320 static void vmclear_local_vcpus(void)
1322 int cpu
= raw_smp_processor_id();
1323 struct vcpu_vmx
*vmx
, *n
;
1325 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1331 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1334 static void kvm_cpu_vmxoff(void)
1336 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1337 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1340 static void hardware_disable(void *garbage
)
1342 vmclear_local_vcpus();
1346 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1347 u32 msr
, u32
*result
)
1349 u32 vmx_msr_low
, vmx_msr_high
;
1350 u32 ctl
= ctl_min
| ctl_opt
;
1352 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1354 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1355 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1357 /* Ensure minimum (required) set of control bits are supported. */
1365 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1367 u32 vmx_msr_low
, vmx_msr_high
;
1368 u32 min
, opt
, min2
, opt2
;
1369 u32 _pin_based_exec_control
= 0;
1370 u32 _cpu_based_exec_control
= 0;
1371 u32 _cpu_based_2nd_exec_control
= 0;
1372 u32 _vmexit_control
= 0;
1373 u32 _vmentry_control
= 0;
1375 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1376 opt
= PIN_BASED_VIRTUAL_NMIS
;
1377 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1378 &_pin_based_exec_control
) < 0)
1381 min
= CPU_BASED_HLT_EXITING
|
1382 #ifdef CONFIG_X86_64
1383 CPU_BASED_CR8_LOAD_EXITING
|
1384 CPU_BASED_CR8_STORE_EXITING
|
1386 CPU_BASED_CR3_LOAD_EXITING
|
1387 CPU_BASED_CR3_STORE_EXITING
|
1388 CPU_BASED_USE_IO_BITMAPS
|
1389 CPU_BASED_MOV_DR_EXITING
|
1390 CPU_BASED_USE_TSC_OFFSETING
|
1391 CPU_BASED_MWAIT_EXITING
|
1392 CPU_BASED_MONITOR_EXITING
|
1393 CPU_BASED_INVLPG_EXITING
;
1394 opt
= CPU_BASED_TPR_SHADOW
|
1395 CPU_BASED_USE_MSR_BITMAPS
|
1396 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1397 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1398 &_cpu_based_exec_control
) < 0)
1400 #ifdef CONFIG_X86_64
1401 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1402 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1403 ~CPU_BASED_CR8_STORE_EXITING
;
1405 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1407 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1408 SECONDARY_EXEC_WBINVD_EXITING
|
1409 SECONDARY_EXEC_ENABLE_VPID
|
1410 SECONDARY_EXEC_ENABLE_EPT
|
1411 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1412 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1413 SECONDARY_EXEC_RDTSCP
;
1414 if (adjust_vmx_controls(min2
, opt2
,
1415 MSR_IA32_VMX_PROCBASED_CTLS2
,
1416 &_cpu_based_2nd_exec_control
) < 0)
1419 #ifndef CONFIG_X86_64
1420 if (!(_cpu_based_2nd_exec_control
&
1421 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1422 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1424 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1425 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1427 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1428 CPU_BASED_CR3_STORE_EXITING
|
1429 CPU_BASED_INVLPG_EXITING
);
1430 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1431 vmx_capability
.ept
, vmx_capability
.vpid
);
1435 #ifdef CONFIG_X86_64
1436 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1438 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1439 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1440 &_vmexit_control
) < 0)
1444 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1445 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1446 &_vmentry_control
) < 0)
1449 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1451 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1452 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1455 #ifdef CONFIG_X86_64
1456 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1457 if (vmx_msr_high
& (1u<<16))
1461 /* Require Write-Back (WB) memory type for VMCS accesses. */
1462 if (((vmx_msr_high
>> 18) & 15) != 6)
1465 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1466 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1467 vmcs_conf
->revision_id
= vmx_msr_low
;
1469 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1470 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1471 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1472 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1473 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1478 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1480 int node
= cpu_to_node(cpu
);
1484 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1487 vmcs
= page_address(pages
);
1488 memset(vmcs
, 0, vmcs_config
.size
);
1489 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1493 static struct vmcs
*alloc_vmcs(void)
1495 return alloc_vmcs_cpu(raw_smp_processor_id());
1498 static void free_vmcs(struct vmcs
*vmcs
)
1500 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1503 static void free_kvm_area(void)
1507 for_each_possible_cpu(cpu
) {
1508 free_vmcs(per_cpu(vmxarea
, cpu
));
1509 per_cpu(vmxarea
, cpu
) = NULL
;
1513 static __init
int alloc_kvm_area(void)
1517 for_each_possible_cpu(cpu
) {
1520 vmcs
= alloc_vmcs_cpu(cpu
);
1526 per_cpu(vmxarea
, cpu
) = vmcs
;
1531 static __init
int hardware_setup(void)
1533 if (setup_vmcs_config(&vmcs_config
) < 0)
1536 if (boot_cpu_has(X86_FEATURE_NX
))
1537 kvm_enable_efer_bits(EFER_NX
);
1539 if (!cpu_has_vmx_vpid())
1542 if (!cpu_has_vmx_ept()) {
1544 enable_unrestricted_guest
= 0;
1547 if (!cpu_has_vmx_unrestricted_guest())
1548 enable_unrestricted_guest
= 0;
1550 if (!cpu_has_vmx_flexpriority())
1551 flexpriority_enabled
= 0;
1553 if (!cpu_has_vmx_tpr_shadow())
1554 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1556 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1557 kvm_disable_largepages();
1559 if (!cpu_has_vmx_ple())
1562 return alloc_kvm_area();
1565 static __exit
void hardware_unsetup(void)
1570 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1572 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1574 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1575 vmcs_write16(sf
->selector
, save
->selector
);
1576 vmcs_writel(sf
->base
, save
->base
);
1577 vmcs_write32(sf
->limit
, save
->limit
);
1578 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1580 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1582 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1586 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1588 unsigned long flags
;
1589 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1591 vmx
->emulation_required
= 1;
1592 vmx
->rmode
.vm86_active
= 0;
1594 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1595 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1596 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1598 flags
= vmcs_readl(GUEST_RFLAGS
);
1599 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1600 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1601 vmcs_writel(GUEST_RFLAGS
, flags
);
1603 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1604 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1606 update_exception_bitmap(vcpu
);
1608 if (emulate_invalid_guest_state
)
1611 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1612 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1613 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1614 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1616 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1617 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1619 vmcs_write16(GUEST_CS_SELECTOR
,
1620 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1621 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1624 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1626 if (!kvm
->arch
.tss_addr
) {
1627 struct kvm_memslots
*slots
;
1630 slots
= kvm_memslots(kvm
);
1631 base_gfn
= kvm
->memslots
->memslots
[0].base_gfn
+
1632 kvm
->memslots
->memslots
[0].npages
- 3;
1633 return base_gfn
<< PAGE_SHIFT
;
1635 return kvm
->arch
.tss_addr
;
1638 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1640 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1642 save
->selector
= vmcs_read16(sf
->selector
);
1643 save
->base
= vmcs_readl(sf
->base
);
1644 save
->limit
= vmcs_read32(sf
->limit
);
1645 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1646 vmcs_write16(sf
->selector
, save
->base
>> 4);
1647 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1648 vmcs_write32(sf
->limit
, 0xffff);
1649 vmcs_write32(sf
->ar_bytes
, 0xf3);
1652 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1654 unsigned long flags
;
1655 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1657 if (enable_unrestricted_guest
)
1660 vmx
->emulation_required
= 1;
1661 vmx
->rmode
.vm86_active
= 1;
1663 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1664 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1666 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1667 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1669 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1670 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1672 flags
= vmcs_readl(GUEST_RFLAGS
);
1673 vmx
->rmode
.save_rflags
= flags
;
1675 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1677 vmcs_writel(GUEST_RFLAGS
, flags
);
1678 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1679 update_exception_bitmap(vcpu
);
1681 if (emulate_invalid_guest_state
)
1682 goto continue_rmode
;
1684 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1685 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1686 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1688 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1689 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1690 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1691 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1692 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1694 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1695 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1696 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1697 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1700 kvm_mmu_reset_context(vcpu
);
1701 init_rmode(vcpu
->kvm
);
1704 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1707 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1713 * Force kernel_gs_base reloading before EFER changes, as control
1714 * of this msr depends on is_long_mode().
1716 vmx_load_host_state(to_vmx(vcpu
));
1717 vcpu
->arch
.efer
= efer
;
1718 if (efer
& EFER_LMA
) {
1719 vmcs_write32(VM_ENTRY_CONTROLS
,
1720 vmcs_read32(VM_ENTRY_CONTROLS
) |
1721 VM_ENTRY_IA32E_MODE
);
1724 vmcs_write32(VM_ENTRY_CONTROLS
,
1725 vmcs_read32(VM_ENTRY_CONTROLS
) &
1726 ~VM_ENTRY_IA32E_MODE
);
1728 msr
->data
= efer
& ~EFER_LME
;
1733 #ifdef CONFIG_X86_64
1735 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1739 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1740 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1741 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1743 vmcs_write32(GUEST_TR_AR_BYTES
,
1744 (guest_tr_ar
& ~AR_TYPE_MASK
)
1745 | AR_TYPE_BUSY_64_TSS
);
1747 vcpu
->arch
.efer
|= EFER_LMA
;
1748 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
1751 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1753 vcpu
->arch
.efer
&= ~EFER_LMA
;
1755 vmcs_write32(VM_ENTRY_CONTROLS
,
1756 vmcs_read32(VM_ENTRY_CONTROLS
)
1757 & ~VM_ENTRY_IA32E_MODE
);
1758 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
1763 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1765 vpid_sync_vcpu_all(to_vmx(vcpu
));
1767 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1770 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1772 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
1774 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
1775 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
1778 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1780 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1782 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1783 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1786 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1788 if (!test_bit(VCPU_EXREG_PDPTR
,
1789 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1792 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1793 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1794 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1795 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1796 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1800 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1802 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1803 vcpu
->arch
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1804 vcpu
->arch
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1805 vcpu
->arch
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1806 vcpu
->arch
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1809 __set_bit(VCPU_EXREG_PDPTR
,
1810 (unsigned long *)&vcpu
->arch
.regs_avail
);
1811 __set_bit(VCPU_EXREG_PDPTR
,
1812 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1815 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1817 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1819 struct kvm_vcpu
*vcpu
)
1821 if (!(cr0
& X86_CR0_PG
)) {
1822 /* From paging/starting to nonpaging */
1823 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1824 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1825 (CPU_BASED_CR3_LOAD_EXITING
|
1826 CPU_BASED_CR3_STORE_EXITING
));
1827 vcpu
->arch
.cr0
= cr0
;
1828 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1829 } else if (!is_paging(vcpu
)) {
1830 /* From nonpaging to paging */
1831 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1832 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1833 ~(CPU_BASED_CR3_LOAD_EXITING
|
1834 CPU_BASED_CR3_STORE_EXITING
));
1835 vcpu
->arch
.cr0
= cr0
;
1836 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1839 if (!(cr0
& X86_CR0_WP
))
1840 *hw_cr0
&= ~X86_CR0_WP
;
1843 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1846 unsigned long hw_cr0
;
1848 if (enable_unrestricted_guest
)
1849 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1850 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1852 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1854 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1857 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1860 #ifdef CONFIG_X86_64
1861 if (vcpu
->arch
.efer
& EFER_LME
) {
1862 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1864 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1870 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1872 if (!vcpu
->fpu_active
)
1873 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
1875 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1876 vmcs_writel(GUEST_CR0
, hw_cr0
);
1877 vcpu
->arch
.cr0
= cr0
;
1880 static u64
construct_eptp(unsigned long root_hpa
)
1884 /* TODO write the value reading from MSR */
1885 eptp
= VMX_EPT_DEFAULT_MT
|
1886 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1887 eptp
|= (root_hpa
& PAGE_MASK
);
1892 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1894 unsigned long guest_cr3
;
1899 eptp
= construct_eptp(cr3
);
1900 vmcs_write64(EPT_POINTER
, eptp
);
1901 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1902 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1903 ept_load_pdptrs(vcpu
);
1906 vmx_flush_tlb(vcpu
);
1907 vmcs_writel(GUEST_CR3
, guest_cr3
);
1910 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1912 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1913 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1915 vcpu
->arch
.cr4
= cr4
;
1917 if (!is_paging(vcpu
)) {
1918 hw_cr4
&= ~X86_CR4_PAE
;
1919 hw_cr4
|= X86_CR4_PSE
;
1920 } else if (!(cr4
& X86_CR4_PAE
)) {
1921 hw_cr4
&= ~X86_CR4_PAE
;
1925 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1926 vmcs_writel(GUEST_CR4
, hw_cr4
);
1929 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1931 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1933 return vmcs_readl(sf
->base
);
1936 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1937 struct kvm_segment
*var
, int seg
)
1939 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1942 var
->base
= vmcs_readl(sf
->base
);
1943 var
->limit
= vmcs_read32(sf
->limit
);
1944 var
->selector
= vmcs_read16(sf
->selector
);
1945 ar
= vmcs_read32(sf
->ar_bytes
);
1946 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1948 var
->type
= ar
& 15;
1949 var
->s
= (ar
>> 4) & 1;
1950 var
->dpl
= (ar
>> 5) & 3;
1951 var
->present
= (ar
>> 7) & 1;
1952 var
->avl
= (ar
>> 12) & 1;
1953 var
->l
= (ar
>> 13) & 1;
1954 var
->db
= (ar
>> 14) & 1;
1955 var
->g
= (ar
>> 15) & 1;
1956 var
->unusable
= (ar
>> 16) & 1;
1959 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1961 if (!is_protmode(vcpu
))
1964 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1967 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
1970 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1977 ar
= var
->type
& 15;
1978 ar
|= (var
->s
& 1) << 4;
1979 ar
|= (var
->dpl
& 3) << 5;
1980 ar
|= (var
->present
& 1) << 7;
1981 ar
|= (var
->avl
& 1) << 12;
1982 ar
|= (var
->l
& 1) << 13;
1983 ar
|= (var
->db
& 1) << 14;
1984 ar
|= (var
->g
& 1) << 15;
1986 if (ar
== 0) /* a 0 value means unusable */
1987 ar
= AR_UNUSABLE_MASK
;
1992 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1993 struct kvm_segment
*var
, int seg
)
1995 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1996 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1999 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2000 vmx
->rmode
.tr
.selector
= var
->selector
;
2001 vmx
->rmode
.tr
.base
= var
->base
;
2002 vmx
->rmode
.tr
.limit
= var
->limit
;
2003 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2006 vmcs_writel(sf
->base
, var
->base
);
2007 vmcs_write32(sf
->limit
, var
->limit
);
2008 vmcs_write16(sf
->selector
, var
->selector
);
2009 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2011 * Hack real-mode segments into vm86 compatibility.
2013 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2014 vmcs_writel(sf
->base
, 0xf0000);
2017 ar
= vmx_segment_access_rights(var
);
2020 * Fix the "Accessed" bit in AR field of segment registers for older
2022 * IA32 arch specifies that at the time of processor reset the
2023 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2024 * is setting it to 0 in the usedland code. This causes invalid guest
2025 * state vmexit when "unrestricted guest" mode is turned on.
2026 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2027 * tree. Newer qemu binaries with that qemu fix would not need this
2030 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2031 ar
|= 0x1; /* Accessed */
2033 vmcs_write32(sf
->ar_bytes
, ar
);
2036 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2038 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
2040 *db
= (ar
>> 14) & 1;
2041 *l
= (ar
>> 13) & 1;
2044 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2046 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2047 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2050 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2052 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
2053 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
2056 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2058 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
2059 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
2062 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2064 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
2065 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
2068 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2070 struct kvm_segment var
;
2073 vmx_get_segment(vcpu
, &var
, seg
);
2074 ar
= vmx_segment_access_rights(&var
);
2076 if (var
.base
!= (var
.selector
<< 4))
2078 if (var
.limit
!= 0xffff)
2086 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
2088 struct kvm_segment cs
;
2089 unsigned int cs_rpl
;
2091 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2092 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
2096 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
2100 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
2101 if (cs
.dpl
> cs_rpl
)
2104 if (cs
.dpl
!= cs_rpl
)
2110 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2114 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2116 struct kvm_segment ss
;
2117 unsigned int ss_rpl
;
2119 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2120 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2124 if (ss
.type
!= 3 && ss
.type
!= 7)
2128 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2136 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2138 struct kvm_segment var
;
2141 vmx_get_segment(vcpu
, &var
, seg
);
2142 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2150 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2151 if (var
.dpl
< rpl
) /* DPL < RPL */
2155 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2161 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2163 struct kvm_segment tr
;
2165 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2169 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2171 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2179 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2181 struct kvm_segment ldtr
;
2183 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2187 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2197 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2199 struct kvm_segment cs
, ss
;
2201 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2202 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2204 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2205 (ss
.selector
& SELECTOR_RPL_MASK
));
2209 * Check if guest state is valid. Returns true if valid, false if
2211 * We assume that registers are always usable
2213 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2215 /* real mode guest state checks */
2216 if (!is_protmode(vcpu
)) {
2217 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2219 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2221 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2223 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2225 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2227 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2230 /* protected mode guest state checks */
2231 if (!cs_ss_rpl_check(vcpu
))
2233 if (!code_segment_valid(vcpu
))
2235 if (!stack_segment_valid(vcpu
))
2237 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2239 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2241 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2243 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2245 if (!tr_valid(vcpu
))
2247 if (!ldtr_valid(vcpu
))
2251 * - Add checks on RIP
2252 * - Add checks on RFLAGS
2258 static int init_rmode_tss(struct kvm
*kvm
)
2260 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2265 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2268 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2269 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2270 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2273 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2276 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2280 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2281 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2291 static int init_rmode_identity_map(struct kvm
*kvm
)
2294 pfn_t identity_map_pfn
;
2299 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2300 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2301 "haven't been allocated!\n");
2304 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2307 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2308 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2311 /* Set up identity-mapping pagetable for EPT in real mode */
2312 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2313 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2314 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2315 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2316 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2320 kvm
->arch
.ept_identity_pagetable_done
= true;
2326 static void seg_setup(int seg
)
2328 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2331 vmcs_write16(sf
->selector
, 0);
2332 vmcs_writel(sf
->base
, 0);
2333 vmcs_write32(sf
->limit
, 0xffff);
2334 if (enable_unrestricted_guest
) {
2336 if (seg
== VCPU_SREG_CS
)
2337 ar
|= 0x08; /* code segment */
2341 vmcs_write32(sf
->ar_bytes
, ar
);
2344 static int alloc_apic_access_page(struct kvm
*kvm
)
2346 struct kvm_userspace_memory_region kvm_userspace_mem
;
2349 mutex_lock(&kvm
->slots_lock
);
2350 if (kvm
->arch
.apic_access_page
)
2352 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2353 kvm_userspace_mem
.flags
= 0;
2354 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2355 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2356 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2360 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2362 mutex_unlock(&kvm
->slots_lock
);
2366 static int alloc_identity_pagetable(struct kvm
*kvm
)
2368 struct kvm_userspace_memory_region kvm_userspace_mem
;
2371 mutex_lock(&kvm
->slots_lock
);
2372 if (kvm
->arch
.ept_identity_pagetable
)
2374 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2375 kvm_userspace_mem
.flags
= 0;
2376 kvm_userspace_mem
.guest_phys_addr
=
2377 kvm
->arch
.ept_identity_map_addr
;
2378 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2379 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2383 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2384 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2386 mutex_unlock(&kvm
->slots_lock
);
2390 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2397 spin_lock(&vmx_vpid_lock
);
2398 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2399 if (vpid
< VMX_NR_VPIDS
) {
2401 __set_bit(vpid
, vmx_vpid_bitmap
);
2403 spin_unlock(&vmx_vpid_lock
);
2406 static void free_vpid(struct vcpu_vmx
*vmx
)
2410 spin_lock(&vmx_vpid_lock
);
2412 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2413 spin_unlock(&vmx_vpid_lock
);
2416 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2418 int f
= sizeof(unsigned long);
2420 if (!cpu_has_vmx_msr_bitmap())
2424 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2425 * have the write-low and read-high bitmap offsets the wrong way round.
2426 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2428 if (msr
<= 0x1fff) {
2429 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2430 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2431 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2433 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2434 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2438 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2441 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2442 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2446 * Sets up the vmcs for emulated real mode.
2448 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2450 u32 host_sysenter_cs
, msr_low
, msr_high
;
2452 u64 host_pat
, tsc_this
, tsc_base
;
2456 unsigned long kvm_vmx_return
;
2460 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2461 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2463 if (cpu_has_vmx_msr_bitmap())
2464 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2466 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2469 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2470 vmcs_config
.pin_based_exec_ctrl
);
2472 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2473 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2474 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2475 #ifdef CONFIG_X86_64
2476 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2477 CPU_BASED_CR8_LOAD_EXITING
;
2481 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2482 CPU_BASED_CR3_LOAD_EXITING
|
2483 CPU_BASED_INVLPG_EXITING
;
2484 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2486 if (cpu_has_secondary_exec_ctrls()) {
2487 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2488 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2490 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2492 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2494 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2495 enable_unrestricted_guest
= 0;
2497 if (!enable_unrestricted_guest
)
2498 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2500 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2501 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2505 vmcs_write32(PLE_GAP
, ple_gap
);
2506 vmcs_write32(PLE_WINDOW
, ple_window
);
2509 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2510 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2511 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2513 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2514 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2515 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2517 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2518 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2519 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2520 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2521 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2522 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2523 #ifdef CONFIG_X86_64
2524 rdmsrl(MSR_FS_BASE
, a
);
2525 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2526 rdmsrl(MSR_GS_BASE
, a
);
2527 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2529 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2530 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2533 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2535 native_store_idt(&dt
);
2536 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
2538 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2539 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2540 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2541 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2542 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
2543 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2544 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
2546 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2547 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2548 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2549 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2550 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2551 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2553 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2554 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2555 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2556 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2558 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2559 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2560 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2561 /* Write the default value follow host pat */
2562 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2563 /* Keep arch.pat sync with GUEST_IA32_PAT */
2564 vmx
->vcpu
.arch
.pat
= host_pat
;
2567 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2568 u32 index
= vmx_msr_index
[i
];
2569 u32 data_low
, data_high
;
2572 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2574 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2576 vmx
->guest_msrs
[j
].index
= i
;
2577 vmx
->guest_msrs
[j
].data
= 0;
2578 vmx
->guest_msrs
[j
].mask
= -1ull;
2582 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2584 /* 22.2.1, 20.8.1 */
2585 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2587 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2588 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2590 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2591 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2593 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2595 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2596 tsc_base
= tsc_this
;
2598 guest_write_tsc(0, tsc_base
);
2603 static int init_rmode(struct kvm
*kvm
)
2605 if (!init_rmode_tss(kvm
))
2607 if (!init_rmode_identity_map(kvm
))
2612 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2614 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2618 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2619 idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2620 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2625 vmx
->rmode
.vm86_active
= 0;
2627 vmx
->soft_vnmi_blocked
= 0;
2629 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2630 kvm_set_cr8(&vmx
->vcpu
, 0);
2631 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2632 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2633 msr
|= MSR_IA32_APICBASE_BSP
;
2634 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2636 fx_init(&vmx
->vcpu
);
2638 seg_setup(VCPU_SREG_CS
);
2640 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2641 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2643 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2644 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2645 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2647 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2648 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2651 seg_setup(VCPU_SREG_DS
);
2652 seg_setup(VCPU_SREG_ES
);
2653 seg_setup(VCPU_SREG_FS
);
2654 seg_setup(VCPU_SREG_GS
);
2655 seg_setup(VCPU_SREG_SS
);
2657 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2658 vmcs_writel(GUEST_TR_BASE
, 0);
2659 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2660 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2662 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2663 vmcs_writel(GUEST_LDTR_BASE
, 0);
2664 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2665 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2667 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2668 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2669 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2671 vmcs_writel(GUEST_RFLAGS
, 0x02);
2672 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2673 kvm_rip_write(vcpu
, 0xfff0);
2675 kvm_rip_write(vcpu
, 0);
2676 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2678 vmcs_writel(GUEST_DR7
, 0x400);
2680 vmcs_writel(GUEST_GDTR_BASE
, 0);
2681 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2683 vmcs_writel(GUEST_IDTR_BASE
, 0);
2684 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2686 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2687 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2688 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2690 /* Special registers */
2691 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2695 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2697 if (cpu_has_vmx_tpr_shadow()) {
2698 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2699 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2700 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2701 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2702 vmcs_write32(TPR_THRESHOLD
, 0);
2705 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2706 vmcs_write64(APIC_ACCESS_ADDR
,
2707 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2710 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2712 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2713 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
2714 vmx_set_cr4(&vmx
->vcpu
, 0);
2715 vmx_set_efer(&vmx
->vcpu
, 0);
2716 vmx_fpu_activate(&vmx
->vcpu
);
2717 update_exception_bitmap(&vmx
->vcpu
);
2719 vpid_sync_vcpu_all(vmx
);
2723 /* HACK: Don't enable emulation on guest boot/reset */
2724 vmx
->emulation_required
= 0;
2727 srcu_read_unlock(&vcpu
->kvm
->srcu
, idx
);
2731 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2733 u32 cpu_based_vm_exec_control
;
2735 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2736 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2737 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2740 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2742 u32 cpu_based_vm_exec_control
;
2744 if (!cpu_has_virtual_nmis()) {
2745 enable_irq_window(vcpu
);
2749 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2750 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2751 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2754 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2756 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2758 int irq
= vcpu
->arch
.interrupt
.nr
;
2760 trace_kvm_inj_virq(irq
);
2762 ++vcpu
->stat
.irq_injections
;
2763 if (vmx
->rmode
.vm86_active
) {
2764 vmx
->rmode
.irq
.pending
= true;
2765 vmx
->rmode
.irq
.vector
= irq
;
2766 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2767 if (vcpu
->arch
.interrupt
.soft
)
2768 vmx
->rmode
.irq
.rip
+=
2769 vmx
->vcpu
.arch
.event_exit_inst_len
;
2770 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2771 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2772 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2773 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2776 intr
= irq
| INTR_INFO_VALID_MASK
;
2777 if (vcpu
->arch
.interrupt
.soft
) {
2778 intr
|= INTR_TYPE_SOFT_INTR
;
2779 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2780 vmx
->vcpu
.arch
.event_exit_inst_len
);
2782 intr
|= INTR_TYPE_EXT_INTR
;
2783 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2786 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2788 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2790 if (!cpu_has_virtual_nmis()) {
2792 * Tracking the NMI-blocked state in software is built upon
2793 * finding the next open IRQ window. This, in turn, depends on
2794 * well-behaving guests: They have to keep IRQs disabled at
2795 * least as long as the NMI handler runs. Otherwise we may
2796 * cause NMI nesting, maybe breaking the guest. But as this is
2797 * highly unlikely, we can live with the residual risk.
2799 vmx
->soft_vnmi_blocked
= 1;
2800 vmx
->vnmi_blocked_time
= 0;
2803 ++vcpu
->stat
.nmi_injections
;
2804 if (vmx
->rmode
.vm86_active
) {
2805 vmx
->rmode
.irq
.pending
= true;
2806 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2807 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2808 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2809 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2810 INTR_INFO_VALID_MASK
);
2811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2812 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2815 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2816 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2819 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2821 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2824 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2825 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_NMI
));
2828 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2830 if (!cpu_has_virtual_nmis())
2831 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2833 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2834 GUEST_INTR_STATE_NMI
);
2837 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2839 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2841 if (!cpu_has_virtual_nmis()) {
2842 if (vmx
->soft_vnmi_blocked
!= masked
) {
2843 vmx
->soft_vnmi_blocked
= masked
;
2844 vmx
->vnmi_blocked_time
= 0;
2848 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2849 GUEST_INTR_STATE_NMI
);
2851 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2852 GUEST_INTR_STATE_NMI
);
2856 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2858 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2859 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2860 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2863 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2866 struct kvm_userspace_memory_region tss_mem
= {
2867 .slot
= TSS_PRIVATE_MEMSLOT
,
2868 .guest_phys_addr
= addr
,
2869 .memory_size
= PAGE_SIZE
* 3,
2873 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2876 kvm
->arch
.tss_addr
= addr
;
2880 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2881 int vec
, u32 err_code
)
2884 * Instruction with address size override prefix opcode 0x67
2885 * Cause the #SS fault with 0 error code in VM86 mode.
2887 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2888 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
)
2891 * Forward all other exceptions that are valid in real mode.
2892 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2893 * the required debugging infrastructure rework.
2897 if (vcpu
->guest_debug
&
2898 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2900 kvm_queue_exception(vcpu
, vec
);
2904 * Update instruction length as we may reinject the exception
2905 * from user space while in guest debugging mode.
2907 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
2908 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2909 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2920 kvm_queue_exception(vcpu
, vec
);
2927 * Trigger machine check on the host. We assume all the MSRs are already set up
2928 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2929 * We pass a fake environment to the machine check handler because we want
2930 * the guest to be always treated like user space, no matter what context
2931 * it used internally.
2933 static void kvm_machine_check(void)
2935 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2936 struct pt_regs regs
= {
2937 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
2938 .flags
= X86_EFLAGS_IF
,
2941 do_machine_check(®s
, 0);
2945 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
2947 /* already handled by vcpu_run */
2951 static int handle_exception(struct kvm_vcpu
*vcpu
)
2953 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2954 struct kvm_run
*kvm_run
= vcpu
->run
;
2955 u32 intr_info
, ex_no
, error_code
;
2956 unsigned long cr2
, rip
, dr6
;
2958 enum emulation_result er
;
2960 vect_info
= vmx
->idt_vectoring_info
;
2961 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2963 if (is_machine_check(intr_info
))
2964 return handle_machine_check(vcpu
);
2966 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2967 !is_page_fault(intr_info
)) {
2968 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2969 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
2970 vcpu
->run
->internal
.ndata
= 2;
2971 vcpu
->run
->internal
.data
[0] = vect_info
;
2972 vcpu
->run
->internal
.data
[1] = intr_info
;
2976 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2977 return 1; /* already handled by vmx_vcpu_run() */
2979 if (is_no_device(intr_info
)) {
2980 vmx_fpu_activate(vcpu
);
2984 if (is_invalid_opcode(intr_info
)) {
2985 er
= emulate_instruction(vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
2986 if (er
!= EMULATE_DONE
)
2987 kvm_queue_exception(vcpu
, UD_VECTOR
);
2992 rip
= kvm_rip_read(vcpu
);
2993 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2994 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2995 if (is_page_fault(intr_info
)) {
2996 /* EPT won't cause page fault directly */
2999 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3000 trace_kvm_page_fault(cr2
, error_code
);
3002 if (kvm_event_needs_reinjection(vcpu
))
3003 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3004 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
3007 if (vmx
->rmode
.vm86_active
&&
3008 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3010 if (vcpu
->arch
.halt_request
) {
3011 vcpu
->arch
.halt_request
= 0;
3012 return kvm_emulate_halt(vcpu
);
3017 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3020 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3021 if (!(vcpu
->guest_debug
&
3022 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3023 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3024 kvm_queue_exception(vcpu
, DB_VECTOR
);
3027 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3028 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3032 * Update instruction length as we may reinject #BP from
3033 * user space while in guest debugging mode. Reading it for
3034 * #DB as well causes no harm, it is not used in that case.
3036 vmx
->vcpu
.arch
.event_exit_inst_len
=
3037 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3038 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3039 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3040 kvm_run
->debug
.arch
.exception
= ex_no
;
3043 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3044 kvm_run
->ex
.exception
= ex_no
;
3045 kvm_run
->ex
.error_code
= error_code
;
3051 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3053 ++vcpu
->stat
.irq_exits
;
3057 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3059 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
3063 static int handle_io(struct kvm_vcpu
*vcpu
)
3065 unsigned long exit_qualification
;
3066 int size
, in
, string
;
3069 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3070 string
= (exit_qualification
& 16) != 0;
3071 in
= (exit_qualification
& 8) != 0;
3073 ++vcpu
->stat
.io_exits
;
3076 return !(emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DO_MMIO
);
3078 port
= exit_qualification
>> 16;
3079 size
= (exit_qualification
& 7) + 1;
3080 skip_emulated_instruction(vcpu
);
3082 return kvm_fast_pio_out(vcpu
, size
, port
);
3086 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3089 * Patch in the VMCALL instruction:
3091 hypercall
[0] = 0x0f;
3092 hypercall
[1] = 0x01;
3093 hypercall
[2] = 0xc1;
3096 static int handle_cr(struct kvm_vcpu
*vcpu
)
3098 unsigned long exit_qualification
, val
;
3102 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3103 cr
= exit_qualification
& 15;
3104 reg
= (exit_qualification
>> 8) & 15;
3105 switch ((exit_qualification
>> 4) & 3) {
3106 case 0: /* mov to cr */
3107 val
= kvm_register_read(vcpu
, reg
);
3108 trace_kvm_cr_write(cr
, val
);
3111 kvm_set_cr0(vcpu
, val
);
3112 skip_emulated_instruction(vcpu
);
3115 kvm_set_cr3(vcpu
, val
);
3116 skip_emulated_instruction(vcpu
);
3119 kvm_set_cr4(vcpu
, val
);
3120 skip_emulated_instruction(vcpu
);
3123 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3124 u8 cr8
= kvm_register_read(vcpu
, reg
);
3125 kvm_set_cr8(vcpu
, cr8
);
3126 skip_emulated_instruction(vcpu
);
3127 if (irqchip_in_kernel(vcpu
->kvm
))
3129 if (cr8_prev
<= cr8
)
3131 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3137 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3138 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3139 skip_emulated_instruction(vcpu
);
3140 vmx_fpu_activate(vcpu
);
3142 case 1: /*mov from cr*/
3145 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3146 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3147 skip_emulated_instruction(vcpu
);
3150 val
= kvm_get_cr8(vcpu
);
3151 kvm_register_write(vcpu
, reg
, val
);
3152 trace_kvm_cr_read(cr
, val
);
3153 skip_emulated_instruction(vcpu
);
3158 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3159 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3160 kvm_lmsw(vcpu
, val
);
3162 skip_emulated_instruction(vcpu
);
3167 vcpu
->run
->exit_reason
= 0;
3168 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3169 (int)(exit_qualification
>> 4) & 3, cr
);
3173 static int handle_dr(struct kvm_vcpu
*vcpu
)
3175 unsigned long exit_qualification
;
3178 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3179 if (!kvm_require_cpl(vcpu
, 0))
3181 dr
= vmcs_readl(GUEST_DR7
);
3184 * As the vm-exit takes precedence over the debug trap, we
3185 * need to emulate the latter, either for the host or the
3186 * guest debugging itself.
3188 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3189 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3190 vcpu
->run
->debug
.arch
.dr7
= dr
;
3191 vcpu
->run
->debug
.arch
.pc
=
3192 vmcs_readl(GUEST_CS_BASE
) +
3193 vmcs_readl(GUEST_RIP
);
3194 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3195 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3198 vcpu
->arch
.dr7
&= ~DR7_GD
;
3199 vcpu
->arch
.dr6
|= DR6_BD
;
3200 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3201 kvm_queue_exception(vcpu
, DB_VECTOR
);
3206 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3207 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3208 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3209 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3211 if (!kvm_get_dr(vcpu
, dr
, &val
))
3212 kvm_register_write(vcpu
, reg
, val
);
3214 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
3215 skip_emulated_instruction(vcpu
);
3219 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
3221 vmcs_writel(GUEST_DR7
, val
);
3224 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3226 kvm_emulate_cpuid(vcpu
);
3230 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3232 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3235 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3236 trace_kvm_msr_read_ex(ecx
);
3237 kvm_inject_gp(vcpu
, 0);
3241 trace_kvm_msr_read(ecx
, data
);
3243 /* FIXME: handling of bits 32:63 of rax, rdx */
3244 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3245 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3246 skip_emulated_instruction(vcpu
);
3250 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3252 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3253 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3254 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3256 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3257 trace_kvm_msr_write_ex(ecx
, data
);
3258 kvm_inject_gp(vcpu
, 0);
3262 trace_kvm_msr_write(ecx
, data
);
3263 skip_emulated_instruction(vcpu
);
3267 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3272 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3274 u32 cpu_based_vm_exec_control
;
3276 /* clear pending irq */
3277 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3278 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3279 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3281 ++vcpu
->stat
.irq_window_exits
;
3284 * If the user space waits to inject interrupts, exit as soon as
3287 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3288 vcpu
->run
->request_interrupt_window
&&
3289 !kvm_cpu_has_interrupt(vcpu
)) {
3290 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3296 static int handle_halt(struct kvm_vcpu
*vcpu
)
3298 skip_emulated_instruction(vcpu
);
3299 return kvm_emulate_halt(vcpu
);
3302 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3304 skip_emulated_instruction(vcpu
);
3305 kvm_emulate_hypercall(vcpu
);
3309 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3311 kvm_queue_exception(vcpu
, UD_VECTOR
);
3315 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3317 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3319 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3320 skip_emulated_instruction(vcpu
);
3324 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3326 skip_emulated_instruction(vcpu
);
3327 /* TODO: Add support for VT-d/pass-through device */
3331 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3333 unsigned long exit_qualification
;
3334 enum emulation_result er
;
3335 unsigned long offset
;
3337 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3338 offset
= exit_qualification
& 0xffful
;
3340 er
= emulate_instruction(vcpu
, 0, 0, 0);
3342 if (er
!= EMULATE_DONE
) {
3344 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3351 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3353 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3354 unsigned long exit_qualification
;
3355 bool has_error_code
= false;
3358 int reason
, type
, idt_v
;
3360 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3361 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3363 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3365 reason
= (u32
)exit_qualification
>> 30;
3366 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3368 case INTR_TYPE_NMI_INTR
:
3369 vcpu
->arch
.nmi_injected
= false;
3370 if (cpu_has_virtual_nmis())
3371 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3372 GUEST_INTR_STATE_NMI
);
3374 case INTR_TYPE_EXT_INTR
:
3375 case INTR_TYPE_SOFT_INTR
:
3376 kvm_clear_interrupt_queue(vcpu
);
3378 case INTR_TYPE_HARD_EXCEPTION
:
3379 if (vmx
->idt_vectoring_info
&
3380 VECTORING_INFO_DELIVER_CODE_MASK
) {
3381 has_error_code
= true;
3383 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3386 case INTR_TYPE_SOFT_EXCEPTION
:
3387 kvm_clear_exception_queue(vcpu
);
3393 tss_selector
= exit_qualification
;
3395 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3396 type
!= INTR_TYPE_EXT_INTR
&&
3397 type
!= INTR_TYPE_NMI_INTR
))
3398 skip_emulated_instruction(vcpu
);
3400 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
3401 has_error_code
, error_code
) == EMULATE_FAIL
) {
3402 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3403 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3404 vcpu
->run
->internal
.ndata
= 0;
3408 /* clear all local breakpoint enable flags */
3409 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3412 * TODO: What about debug traps on tss switch?
3413 * Are we supposed to inject them and update dr6?
3419 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3421 unsigned long exit_qualification
;
3425 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3427 if (exit_qualification
& (1 << 6)) {
3428 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3432 gla_validity
= (exit_qualification
>> 7) & 0x3;
3433 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3434 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3435 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3436 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3437 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3438 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3439 (long unsigned int)exit_qualification
);
3440 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3441 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3445 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3446 trace_kvm_page_fault(gpa
, exit_qualification
);
3447 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3450 static u64
ept_rsvd_mask(u64 spte
, int level
)
3455 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3456 mask
|= (1ULL << i
);
3459 /* bits 7:3 reserved */
3461 else if (level
== 2) {
3462 if (spte
& (1ULL << 7))
3463 /* 2MB ref, bits 20:12 reserved */
3466 /* bits 6:3 reserved */
3473 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3476 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3478 /* 010b (write-only) */
3479 WARN_ON((spte
& 0x7) == 0x2);
3481 /* 110b (write/execute) */
3482 WARN_ON((spte
& 0x7) == 0x6);
3484 /* 100b (execute-only) and value not supported by logical processor */
3485 if (!cpu_has_vmx_ept_execute_only())
3486 WARN_ON((spte
& 0x7) == 0x4);
3490 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3492 if (rsvd_bits
!= 0) {
3493 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3494 __func__
, rsvd_bits
);
3498 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3499 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3501 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3502 ept_mem_type
== 7) {
3503 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3504 __func__
, ept_mem_type
);
3511 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3517 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3519 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3520 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3522 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3524 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3525 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3527 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3528 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3533 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3535 u32 cpu_based_vm_exec_control
;
3537 /* clear pending NMI */
3538 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3539 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3540 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3541 ++vcpu
->stat
.nmi_window_exits
;
3546 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3549 enum emulation_result err
= EMULATE_DONE
;
3552 while (!guest_state_valid(vcpu
)) {
3553 err
= emulate_instruction(vcpu
, 0, 0, 0);
3555 if (err
== EMULATE_DO_MMIO
) {
3560 if (err
!= EMULATE_DONE
) {
3561 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3562 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3563 vcpu
->run
->internal
.ndata
= 0;
3568 if (signal_pending(current
))
3574 vmx
->emulation_required
= 0;
3580 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3581 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3583 static int handle_pause(struct kvm_vcpu
*vcpu
)
3585 skip_emulated_instruction(vcpu
);
3586 kvm_vcpu_on_spin(vcpu
);
3591 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3593 kvm_queue_exception(vcpu
, UD_VECTOR
);
3598 * The exit handlers return 1 if the exit was handled fully and guest execution
3599 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3600 * to be done to userspace and return 0.
3602 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3603 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3604 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3605 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3606 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3607 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3608 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3609 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3610 [EXIT_REASON_CPUID
] = handle_cpuid
,
3611 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3612 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3613 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3614 [EXIT_REASON_HLT
] = handle_halt
,
3615 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3616 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3617 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3618 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3619 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3620 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3621 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3622 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3623 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3624 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3625 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3626 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3627 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3628 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3629 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3630 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3631 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3632 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3633 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3634 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3635 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3638 static const int kvm_vmx_max_exit_handlers
=
3639 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3642 * The guest has exited. See if we can fix it or if we need userspace
3645 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3647 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3648 u32 exit_reason
= vmx
->exit_reason
;
3649 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3651 trace_kvm_exit(exit_reason
, vcpu
);
3653 /* If guest state is invalid, start emulating */
3654 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3655 return handle_invalid_guest_state(vcpu
);
3657 /* Access CR3 don't cause VMExit in paging mode, so we need
3658 * to sync with guest real CR3. */
3659 if (enable_ept
&& is_paging(vcpu
))
3660 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3662 if (unlikely(vmx
->fail
)) {
3663 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3664 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3665 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3669 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3670 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3671 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3672 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3673 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3674 "(0x%x) and exit reason is 0x%x\n",
3675 __func__
, vectoring_info
, exit_reason
);
3677 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3678 if (vmx_interrupt_allowed(vcpu
)) {
3679 vmx
->soft_vnmi_blocked
= 0;
3680 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3681 vcpu
->arch
.nmi_pending
) {
3683 * This CPU don't support us in finding the end of an
3684 * NMI-blocked window if the guest runs with IRQs
3685 * disabled. So we pull the trigger after 1 s of
3686 * futile waiting, but inform the user about this.
3688 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3689 "state on VCPU %d after 1 s timeout\n",
3690 __func__
, vcpu
->vcpu_id
);
3691 vmx
->soft_vnmi_blocked
= 0;
3695 if (exit_reason
< kvm_vmx_max_exit_handlers
3696 && kvm_vmx_exit_handlers
[exit_reason
])
3697 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3699 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3700 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3705 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3707 if (irr
== -1 || tpr
< irr
) {
3708 vmcs_write32(TPR_THRESHOLD
, 0);
3712 vmcs_write32(TPR_THRESHOLD
, irr
);
3715 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3718 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3722 bool idtv_info_valid
;
3724 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3726 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3728 /* Handle machine checks before interrupts are enabled */
3729 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3730 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3731 && is_machine_check(exit_intr_info
)))
3732 kvm_machine_check();
3734 /* We need to handle NMIs before interrupts are enabled */
3735 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3736 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
3737 kvm_before_handle_nmi(&vmx
->vcpu
);
3739 kvm_after_handle_nmi(&vmx
->vcpu
);
3742 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3744 if (cpu_has_virtual_nmis()) {
3745 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3746 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3748 * SDM 3: 27.7.1.2 (September 2008)
3749 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3750 * a guest IRET fault.
3751 * SDM 3: 23.2.2 (September 2008)
3752 * Bit 12 is undefined in any of the following cases:
3753 * If the VM exit sets the valid bit in the IDT-vectoring
3754 * information field.
3755 * If the VM exit is due to a double fault.
3757 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3758 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3759 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3760 GUEST_INTR_STATE_NMI
);
3761 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3762 vmx
->vnmi_blocked_time
+=
3763 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3765 vmx
->vcpu
.arch
.nmi_injected
= false;
3766 kvm_clear_exception_queue(&vmx
->vcpu
);
3767 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3769 if (!idtv_info_valid
)
3772 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3773 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3776 case INTR_TYPE_NMI_INTR
:
3777 vmx
->vcpu
.arch
.nmi_injected
= true;
3779 * SDM 3: 27.7.1.2 (September 2008)
3780 * Clear bit "block by NMI" before VM entry if a NMI
3783 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3784 GUEST_INTR_STATE_NMI
);
3786 case INTR_TYPE_SOFT_EXCEPTION
:
3787 vmx
->vcpu
.arch
.event_exit_inst_len
=
3788 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3790 case INTR_TYPE_HARD_EXCEPTION
:
3791 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3792 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3793 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3795 kvm_queue_exception(&vmx
->vcpu
, vector
);
3797 case INTR_TYPE_SOFT_INTR
:
3798 vmx
->vcpu
.arch
.event_exit_inst_len
=
3799 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3801 case INTR_TYPE_EXT_INTR
:
3802 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3803 type
== INTR_TYPE_SOFT_INTR
);
3811 * Failure to inject an interrupt should give us the information
3812 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3813 * when fetching the interrupt redirection bitmap in the real-mode
3814 * tss, this doesn't happen. So we do it ourselves.
3816 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3818 vmx
->rmode
.irq
.pending
= 0;
3819 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3821 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3822 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3823 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3824 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3827 vmx
->idt_vectoring_info
=
3828 VECTORING_INFO_VALID_MASK
3829 | INTR_TYPE_EXT_INTR
3830 | vmx
->rmode
.irq
.vector
;
3833 #ifdef CONFIG_X86_64
3841 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3843 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3845 /* Record the guest's net vcpu time for enforced NMI injections. */
3846 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3847 vmx
->entry_time
= ktime_get();
3849 /* Don't enter VMX if guest state is invalid, let the exit handler
3850 start emulation until we arrive back to a valid state */
3851 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3854 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3855 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3856 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3857 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3859 /* When single-stepping over STI and MOV SS, we must clear the
3860 * corresponding interruptibility bits in the guest state. Otherwise
3861 * vmentry fails as it then expects bit 14 (BS) in pending debug
3862 * exceptions being set, but that's not correct for the guest debugging
3864 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3865 vmx_set_interrupt_shadow(vcpu
, 0);
3868 * Loading guest fpu may have cleared host cr0.ts
3870 vmcs_writel(HOST_CR0
, read_cr0());
3873 /* Store host registers */
3874 "push %%"R
"dx; push %%"R
"bp;"
3876 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3878 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3879 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3881 /* Reload cr2 if changed */
3882 "mov %c[cr2](%0), %%"R
"ax \n\t"
3883 "mov %%cr2, %%"R
"dx \n\t"
3884 "cmp %%"R
"ax, %%"R
"dx \n\t"
3886 "mov %%"R
"ax, %%cr2 \n\t"
3888 /* Check if vmlaunch of vmresume is needed */
3889 "cmpl $0, %c[launched](%0) \n\t"
3890 /* Load guest registers. Don't clobber flags. */
3891 "mov %c[rax](%0), %%"R
"ax \n\t"
3892 "mov %c[rbx](%0), %%"R
"bx \n\t"
3893 "mov %c[rdx](%0), %%"R
"dx \n\t"
3894 "mov %c[rsi](%0), %%"R
"si \n\t"
3895 "mov %c[rdi](%0), %%"R
"di \n\t"
3896 "mov %c[rbp](%0), %%"R
"bp \n\t"
3897 #ifdef CONFIG_X86_64
3898 "mov %c[r8](%0), %%r8 \n\t"
3899 "mov %c[r9](%0), %%r9 \n\t"
3900 "mov %c[r10](%0), %%r10 \n\t"
3901 "mov %c[r11](%0), %%r11 \n\t"
3902 "mov %c[r12](%0), %%r12 \n\t"
3903 "mov %c[r13](%0), %%r13 \n\t"
3904 "mov %c[r14](%0), %%r14 \n\t"
3905 "mov %c[r15](%0), %%r15 \n\t"
3907 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3909 /* Enter guest mode */
3910 "jne .Llaunched \n\t"
3911 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3912 "jmp .Lkvm_vmx_return \n\t"
3913 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3914 ".Lkvm_vmx_return: "
3915 /* Save guest registers, load host registers, keep flags */
3916 "xchg %0, (%%"R
"sp) \n\t"
3917 "mov %%"R
"ax, %c[rax](%0) \n\t"
3918 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3919 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3920 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3921 "mov %%"R
"si, %c[rsi](%0) \n\t"
3922 "mov %%"R
"di, %c[rdi](%0) \n\t"
3923 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3924 #ifdef CONFIG_X86_64
3925 "mov %%r8, %c[r8](%0) \n\t"
3926 "mov %%r9, %c[r9](%0) \n\t"
3927 "mov %%r10, %c[r10](%0) \n\t"
3928 "mov %%r11, %c[r11](%0) \n\t"
3929 "mov %%r12, %c[r12](%0) \n\t"
3930 "mov %%r13, %c[r13](%0) \n\t"
3931 "mov %%r14, %c[r14](%0) \n\t"
3932 "mov %%r15, %c[r15](%0) \n\t"
3934 "mov %%cr2, %%"R
"ax \n\t"
3935 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3937 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3938 "setbe %c[fail](%0) \n\t"
3939 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3940 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3941 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3942 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3943 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3944 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3945 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3946 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3947 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3948 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3949 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3950 #ifdef CONFIG_X86_64
3951 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3952 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3953 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3954 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3955 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3956 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3957 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3958 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3960 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3962 , R
"bx", R
"di", R
"si"
3963 #ifdef CONFIG_X86_64
3964 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3968 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
3969 | (1 << VCPU_EXREG_PDPTR
));
3970 vcpu
->arch
.regs_dirty
= 0;
3972 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3973 if (vmx
->rmode
.irq
.pending
)
3974 fixup_rmode_irq(vmx
);
3976 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3979 vmx_complete_interrupts(vmx
);
3985 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3991 free_vmcs(vmx
->vmcs
);
3996 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3998 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4001 vmx_free_vmcs(vcpu
);
4002 kfree(vmx
->guest_msrs
);
4003 kvm_vcpu_uninit(vcpu
);
4004 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4007 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
4010 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
4014 return ERR_PTR(-ENOMEM
);
4018 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
4022 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
4023 if (!vmx
->guest_msrs
) {
4028 vmx
->vmcs
= alloc_vmcs();
4032 vmcs_clear(vmx
->vmcs
);
4035 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
4036 err
= vmx_vcpu_setup(vmx
);
4037 vmx_vcpu_put(&vmx
->vcpu
);
4041 if (vm_need_virtualize_apic_accesses(kvm
))
4042 if (alloc_apic_access_page(kvm
) != 0)
4046 if (!kvm
->arch
.ept_identity_map_addr
)
4047 kvm
->arch
.ept_identity_map_addr
=
4048 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4049 if (alloc_identity_pagetable(kvm
) != 0)
4056 free_vmcs(vmx
->vmcs
);
4058 kfree(vmx
->guest_msrs
);
4060 kvm_vcpu_uninit(&vmx
->vcpu
);
4063 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4064 return ERR_PTR(err
);
4067 static void __init
vmx_check_processor_compat(void *rtn
)
4069 struct vmcs_config vmcs_conf
;
4072 if (setup_vmcs_config(&vmcs_conf
) < 0)
4074 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
4075 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
4076 smp_processor_id());
4081 static int get_ept_level(void)
4083 return VMX_EPT_DEFAULT_GAW
+ 1;
4086 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4090 /* For VT-d and EPT combination
4091 * 1. MMIO: always map as UC
4093 * a. VT-d without snooping control feature: can't guarantee the
4094 * result, try to trust guest.
4095 * b. VT-d with snooping control feature: snooping control feature of
4096 * VT-d engine can guarantee the cache correctness. Just set it
4097 * to WB to keep consistent with host. So the same as item 3.
4098 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4099 * consistent with host MTRR
4102 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4103 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4104 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4105 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4106 VMX_EPT_MT_EPTE_SHIFT
;
4108 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4114 #define _ER(x) { EXIT_REASON_##x, #x }
4116 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4118 _ER(EXTERNAL_INTERRUPT
),
4120 _ER(PENDING_INTERRUPT
),
4140 _ER(IO_INSTRUCTION
),
4143 _ER(MWAIT_INSTRUCTION
),
4144 _ER(MONITOR_INSTRUCTION
),
4145 _ER(PAUSE_INSTRUCTION
),
4146 _ER(MCE_DURING_VMENTRY
),
4147 _ER(TPR_BELOW_THRESHOLD
),
4157 static int vmx_get_lpage_level(void)
4159 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
4160 return PT_DIRECTORY_LEVEL
;
4162 /* For shadow and EPT supported 1GB page */
4163 return PT_PDPE_LEVEL
;
4166 static inline u32
bit(int bitno
)
4168 return 1 << (bitno
& 31);
4171 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4173 struct kvm_cpuid_entry2
*best
;
4174 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4177 vmx
->rdtscp_enabled
= false;
4178 if (vmx_rdtscp_supported()) {
4179 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4180 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4181 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4182 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4183 vmx
->rdtscp_enabled
= true;
4185 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4186 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4193 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4197 static struct kvm_x86_ops vmx_x86_ops
= {
4198 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4199 .disabled_by_bios
= vmx_disabled_by_bios
,
4200 .hardware_setup
= hardware_setup
,
4201 .hardware_unsetup
= hardware_unsetup
,
4202 .check_processor_compatibility
= vmx_check_processor_compat
,
4203 .hardware_enable
= hardware_enable
,
4204 .hardware_disable
= hardware_disable
,
4205 .cpu_has_accelerated_tpr
= report_flexpriority
,
4207 .vcpu_create
= vmx_create_vcpu
,
4208 .vcpu_free
= vmx_free_vcpu
,
4209 .vcpu_reset
= vmx_vcpu_reset
,
4211 .prepare_guest_switch
= vmx_save_host_state
,
4212 .vcpu_load
= vmx_vcpu_load
,
4213 .vcpu_put
= vmx_vcpu_put
,
4215 .set_guest_debug
= set_guest_debug
,
4216 .get_msr
= vmx_get_msr
,
4217 .set_msr
= vmx_set_msr
,
4218 .get_segment_base
= vmx_get_segment_base
,
4219 .get_segment
= vmx_get_segment
,
4220 .set_segment
= vmx_set_segment
,
4221 .get_cpl
= vmx_get_cpl
,
4222 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4223 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
4224 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4225 .set_cr0
= vmx_set_cr0
,
4226 .set_cr3
= vmx_set_cr3
,
4227 .set_cr4
= vmx_set_cr4
,
4228 .set_efer
= vmx_set_efer
,
4229 .get_idt
= vmx_get_idt
,
4230 .set_idt
= vmx_set_idt
,
4231 .get_gdt
= vmx_get_gdt
,
4232 .set_gdt
= vmx_set_gdt
,
4233 .set_dr7
= vmx_set_dr7
,
4234 .cache_reg
= vmx_cache_reg
,
4235 .get_rflags
= vmx_get_rflags
,
4236 .set_rflags
= vmx_set_rflags
,
4237 .fpu_activate
= vmx_fpu_activate
,
4238 .fpu_deactivate
= vmx_fpu_deactivate
,
4240 .tlb_flush
= vmx_flush_tlb
,
4242 .run
= vmx_vcpu_run
,
4243 .handle_exit
= vmx_handle_exit
,
4244 .skip_emulated_instruction
= skip_emulated_instruction
,
4245 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4246 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4247 .patch_hypercall
= vmx_patch_hypercall
,
4248 .set_irq
= vmx_inject_irq
,
4249 .set_nmi
= vmx_inject_nmi
,
4250 .queue_exception
= vmx_queue_exception
,
4251 .interrupt_allowed
= vmx_interrupt_allowed
,
4252 .nmi_allowed
= vmx_nmi_allowed
,
4253 .get_nmi_mask
= vmx_get_nmi_mask
,
4254 .set_nmi_mask
= vmx_set_nmi_mask
,
4255 .enable_nmi_window
= enable_nmi_window
,
4256 .enable_irq_window
= enable_irq_window
,
4257 .update_cr8_intercept
= update_cr8_intercept
,
4259 .set_tss_addr
= vmx_set_tss_addr
,
4260 .get_tdp_level
= get_ept_level
,
4261 .get_mt_mask
= vmx_get_mt_mask
,
4263 .exit_reasons_str
= vmx_exit_reasons_str
,
4264 .get_lpage_level
= vmx_get_lpage_level
,
4266 .cpuid_update
= vmx_cpuid_update
,
4268 .rdtscp_supported
= vmx_rdtscp_supported
,
4270 .set_supported_cpuid
= vmx_set_supported_cpuid
,
4273 static int __init
vmx_init(void)
4277 rdmsrl_safe(MSR_EFER
, &host_efer
);
4279 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4280 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4282 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4283 if (!vmx_io_bitmap_a
)
4286 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4287 if (!vmx_io_bitmap_b
) {
4292 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4293 if (!vmx_msr_bitmap_legacy
) {
4298 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4299 if (!vmx_msr_bitmap_longmode
) {
4305 * Allow direct access to the PC debug port (it is often used for I/O
4306 * delays, but the vmexits simply slow things down).
4308 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4309 clear_bit(0x80, vmx_io_bitmap_a
);
4311 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4313 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4314 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4316 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4318 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
4319 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
4323 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4324 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4325 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4326 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4327 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4328 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4331 bypass_guest_pf
= 0;
4332 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
4333 VMX_EPT_WRITABLE_MASK
);
4334 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4335 VMX_EPT_EXECUTABLE_MASK
);
4340 if (bypass_guest_pf
)
4341 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4346 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4348 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4350 free_page((unsigned long)vmx_io_bitmap_b
);
4352 free_page((unsigned long)vmx_io_bitmap_a
);
4356 static void __exit
vmx_exit(void)
4358 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4359 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4360 free_page((unsigned long)vmx_io_bitmap_b
);
4361 free_page((unsigned long)vmx_io_bitmap_a
);
4366 module_init(vmx_init
)
4367 module_exit(vmx_exit
)