2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id vmx_cpu_id
[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
59 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
61 static bool __read_mostly enable_vpid
= 1;
62 module_param_named(vpid
, enable_vpid
, bool, 0444);
64 static bool __read_mostly flexpriority_enabled
= 1;
65 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
67 static bool __read_mostly enable_ept
= 1;
68 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
70 static bool __read_mostly enable_unrestricted_guest
= 1;
71 module_param_named(unrestricted_guest
,
72 enable_unrestricted_guest
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept_ad_bits
= 1;
75 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
77 static bool __read_mostly emulate_invalid_guest_state
= true;
78 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
80 static bool __read_mostly vmm_exclusive
= 1;
81 module_param(vmm_exclusive
, bool, S_IRUGO
);
83 static bool __read_mostly fasteoi
= 1;
84 module_param(fasteoi
, bool, S_IRUGO
);
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
91 static bool __read_mostly nested
= 0;
92 module_param(nested
, bool, S_IRUGO
);
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
125 module_param(ple_gap
, int, S_IRUGO
);
127 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
128 module_param(ple_window
, int, S_IRUGO
);
130 #define NR_AUTOLOAD_MSRS 8
131 #define VMCS02_POOL_SIZE 1
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
148 struct list_head loaded_vmcss_on_cpu_link
;
151 struct shared_msr_entry
{
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 typedef u64 natural_width
;
171 struct __packed vmcs12
{
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
178 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding
[7]; /* room for future expansion */
184 u64 vm_exit_msr_store_addr
;
185 u64 vm_exit_msr_load_addr
;
186 u64 vm_entry_msr_load_addr
;
188 u64 virtual_apic_page_addr
;
189 u64 apic_access_addr
;
191 u64 guest_physical_address
;
192 u64 vmcs_link_pointer
;
193 u64 guest_ia32_debugctl
;
196 u64 guest_ia32_perf_global_ctrl
;
203 u64 host_ia32_perf_global_ctrl
;
204 u64 padding64
[8]; /* room for future expansion */
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
211 natural_width cr0_guest_host_mask
;
212 natural_width cr4_guest_host_mask
;
213 natural_width cr0_read_shadow
;
214 natural_width cr4_read_shadow
;
215 natural_width cr3_target_value0
;
216 natural_width cr3_target_value1
;
217 natural_width cr3_target_value2
;
218 natural_width cr3_target_value3
;
219 natural_width exit_qualification
;
220 natural_width guest_linear_address
;
221 natural_width guest_cr0
;
222 natural_width guest_cr3
;
223 natural_width guest_cr4
;
224 natural_width guest_es_base
;
225 natural_width guest_cs_base
;
226 natural_width guest_ss_base
;
227 natural_width guest_ds_base
;
228 natural_width guest_fs_base
;
229 natural_width guest_gs_base
;
230 natural_width guest_ldtr_base
;
231 natural_width guest_tr_base
;
232 natural_width guest_gdtr_base
;
233 natural_width guest_idtr_base
;
234 natural_width guest_dr7
;
235 natural_width guest_rsp
;
236 natural_width guest_rip
;
237 natural_width guest_rflags
;
238 natural_width guest_pending_dbg_exceptions
;
239 natural_width guest_sysenter_esp
;
240 natural_width guest_sysenter_eip
;
241 natural_width host_cr0
;
242 natural_width host_cr3
;
243 natural_width host_cr4
;
244 natural_width host_fs_base
;
245 natural_width host_gs_base
;
246 natural_width host_tr_base
;
247 natural_width host_gdtr_base
;
248 natural_width host_idtr_base
;
249 natural_width host_ia32_sysenter_esp
;
250 natural_width host_ia32_sysenter_eip
;
251 natural_width host_rsp
;
252 natural_width host_rip
;
253 natural_width paddingl
[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control
;
255 u32 cpu_based_vm_exec_control
;
256 u32 exception_bitmap
;
257 u32 page_fault_error_code_mask
;
258 u32 page_fault_error_code_match
;
259 u32 cr3_target_count
;
260 u32 vm_exit_controls
;
261 u32 vm_exit_msr_store_count
;
262 u32 vm_exit_msr_load_count
;
263 u32 vm_entry_controls
;
264 u32 vm_entry_msr_load_count
;
265 u32 vm_entry_intr_info_field
;
266 u32 vm_entry_exception_error_code
;
267 u32 vm_entry_instruction_len
;
269 u32 secondary_vm_exec_control
;
270 u32 vm_instruction_error
;
272 u32 vm_exit_intr_info
;
273 u32 vm_exit_intr_error_code
;
274 u32 idt_vectoring_info_field
;
275 u32 idt_vectoring_error_code
;
276 u32 vm_exit_instruction_len
;
277 u32 vmx_instruction_info
;
284 u32 guest_ldtr_limit
;
286 u32 guest_gdtr_limit
;
287 u32 guest_idtr_limit
;
288 u32 guest_es_ar_bytes
;
289 u32 guest_cs_ar_bytes
;
290 u32 guest_ss_ar_bytes
;
291 u32 guest_ds_ar_bytes
;
292 u32 guest_fs_ar_bytes
;
293 u32 guest_gs_ar_bytes
;
294 u32 guest_ldtr_ar_bytes
;
295 u32 guest_tr_ar_bytes
;
296 u32 guest_interruptibility_info
;
297 u32 guest_activity_state
;
298 u32 guest_sysenter_cs
;
299 u32 host_ia32_sysenter_cs
;
300 u32 padding32
[8]; /* room for future expansion */
301 u16 virtual_processor_id
;
302 u16 guest_es_selector
;
303 u16 guest_cs_selector
;
304 u16 guest_ss_selector
;
305 u16 guest_ds_selector
;
306 u16 guest_fs_selector
;
307 u16 guest_gs_selector
;
308 u16 guest_ldtr_selector
;
309 u16 guest_tr_selector
;
310 u16 host_es_selector
;
311 u16 host_cs_selector
;
312 u16 host_ss_selector
;
313 u16 host_ds_selector
;
314 u16 host_fs_selector
;
315 u16 host_gs_selector
;
316 u16 host_tr_selector
;
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 #define VMCS12_REVISION 0x11e57ed0
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
331 #define VMCS12_SIZE 0x1000
333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
335 struct list_head list
;
337 struct loaded_vmcs vmcs02
;
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 /* Has the level1 guest done vmxon? */
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 /* The host-usable pointer to the above */
351 struct page
*current_vmcs12_page
;
352 struct vmcs12
*current_vmcs12
;
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool
;
357 u64 vmcs01_tsc_offset
;
358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending
;
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
364 struct page
*apic_access_page
;
368 struct kvm_vcpu vcpu
;
369 unsigned long host_rsp
;
372 bool nmi_known_unmasked
;
374 u32 idt_vectoring_info
;
376 struct shared_msr_entry
*guest_msrs
;
380 u64 msr_host_kernel_gs_base
;
381 u64 msr_guest_kernel_gs_base
;
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
388 struct loaded_vmcs vmcs01
;
389 struct loaded_vmcs
*loaded_vmcs
;
390 bool __launched
; /* temporary, used in vmx_vcpu_run */
391 struct msr_autoload
{
393 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
394 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
398 u16 fs_sel
, gs_sel
, ldt_sel
;
402 int gs_ldt_reload_needed
;
403 int fs_reload_needed
;
408 struct kvm_save_segment
{
413 } tr
, es
, ds
, fs
, gs
;
416 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg
[8];
420 bool emulation_required
;
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked
;
425 s64 vnmi_blocked_time
;
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested
;
434 enum segment_cache_field
{
443 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
445 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
453 static unsigned short vmcs_field_to_offset_table
[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
455 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
456 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
457 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
458 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
459 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
460 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
461 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
462 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
463 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
464 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
465 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
466 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
467 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
468 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
469 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
470 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
471 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
472 FIELD64(MSR_BITMAP
, msr_bitmap
),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
476 FIELD64(TSC_OFFSET
, tsc_offset
),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
478 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
479 FIELD64(EPT_POINTER
, ept_pointer
),
480 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
481 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
482 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
483 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
484 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
486 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
487 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
488 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
489 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
490 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
491 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
495 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
498 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
499 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
500 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
502 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
507 FIELD(TPR_THRESHOLD
, tpr_threshold
),
508 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
509 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
510 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
511 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
512 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
513 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
514 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
515 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
516 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
517 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
518 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
519 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
520 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
521 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
522 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
523 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
524 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
525 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
526 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
527 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
528 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
529 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
530 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
531 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
532 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
533 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
534 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
536 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
537 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
538 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
539 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
540 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
541 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
542 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
543 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
544 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
545 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
546 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
547 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
548 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
549 FIELD(GUEST_CR0
, guest_cr0
),
550 FIELD(GUEST_CR3
, guest_cr3
),
551 FIELD(GUEST_CR4
, guest_cr4
),
552 FIELD(GUEST_ES_BASE
, guest_es_base
),
553 FIELD(GUEST_CS_BASE
, guest_cs_base
),
554 FIELD(GUEST_SS_BASE
, guest_ss_base
),
555 FIELD(GUEST_DS_BASE
, guest_ds_base
),
556 FIELD(GUEST_FS_BASE
, guest_fs_base
),
557 FIELD(GUEST_GS_BASE
, guest_gs_base
),
558 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
559 FIELD(GUEST_TR_BASE
, guest_tr_base
),
560 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
561 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
562 FIELD(GUEST_DR7
, guest_dr7
),
563 FIELD(GUEST_RSP
, guest_rsp
),
564 FIELD(GUEST_RIP
, guest_rip
),
565 FIELD(GUEST_RFLAGS
, guest_rflags
),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
567 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
568 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
569 FIELD(HOST_CR0
, host_cr0
),
570 FIELD(HOST_CR3
, host_cr3
),
571 FIELD(HOST_CR4
, host_cr4
),
572 FIELD(HOST_FS_BASE
, host_fs_base
),
573 FIELD(HOST_GS_BASE
, host_gs_base
),
574 FIELD(HOST_TR_BASE
, host_tr_base
),
575 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
576 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
577 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
578 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
579 FIELD(HOST_RSP
, host_rsp
),
580 FIELD(HOST_RIP
, host_rip
),
582 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
584 static inline short vmcs_field_to_offset(unsigned long field
)
586 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
588 return vmcs_field_to_offset_table
[field
];
591 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
593 return to_vmx(vcpu
)->nested
.current_vmcs12
;
596 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
598 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
599 if (is_error_page(page
)) {
600 kvm_release_page_clean(page
);
606 static void nested_release_page(struct page
*page
)
608 kvm_release_page_dirty(page
);
611 static void nested_release_page_clean(struct page
*page
)
613 kvm_release_page_clean(page
);
616 static u64
construct_eptp(unsigned long root_hpa
);
617 static void kvm_cpu_vmxon(u64 addr
);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
620 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
621 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
622 struct kvm_segment
*var
, int seg
);
623 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
624 struct kvm_segment
*var
, int seg
);
626 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
627 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
629 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
633 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
635 static unsigned long *vmx_io_bitmap_a
;
636 static unsigned long *vmx_io_bitmap_b
;
637 static unsigned long *vmx_msr_bitmap_legacy
;
638 static unsigned long *vmx_msr_bitmap_longmode
;
640 static bool cpu_has_load_ia32_efer
;
641 static bool cpu_has_load_perf_global_ctrl
;
643 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
644 static DEFINE_SPINLOCK(vmx_vpid_lock
);
646 static struct vmcs_config
{
650 u32 pin_based_exec_ctrl
;
651 u32 cpu_based_exec_ctrl
;
652 u32 cpu_based_2nd_exec_ctrl
;
657 static struct vmx_capability
{
662 #define VMX_SEGMENT_FIELD(seg) \
663 [VCPU_SREG_##seg] = { \
664 .selector = GUEST_##seg##_SELECTOR, \
665 .base = GUEST_##seg##_BASE, \
666 .limit = GUEST_##seg##_LIMIT, \
667 .ar_bytes = GUEST_##seg##_AR_BYTES, \
670 static struct kvm_vmx_segment_field
{
675 } kvm_vmx_segment_fields
[] = {
676 VMX_SEGMENT_FIELD(CS
),
677 VMX_SEGMENT_FIELD(DS
),
678 VMX_SEGMENT_FIELD(ES
),
679 VMX_SEGMENT_FIELD(FS
),
680 VMX_SEGMENT_FIELD(GS
),
681 VMX_SEGMENT_FIELD(SS
),
682 VMX_SEGMENT_FIELD(TR
),
683 VMX_SEGMENT_FIELD(LDTR
),
686 static u64 host_efer
;
688 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
691 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
692 * away by decrementing the array size.
694 static const u32 vmx_msr_index
[] = {
696 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
698 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
702 static inline bool is_page_fault(u32 intr_info
)
704 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
705 INTR_INFO_VALID_MASK
)) ==
706 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
709 static inline bool is_no_device(u32 intr_info
)
711 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
712 INTR_INFO_VALID_MASK
)) ==
713 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
716 static inline bool is_invalid_opcode(u32 intr_info
)
718 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
719 INTR_INFO_VALID_MASK
)) ==
720 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
723 static inline bool is_external_interrupt(u32 intr_info
)
725 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
726 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
729 static inline bool is_machine_check(u32 intr_info
)
731 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
732 INTR_INFO_VALID_MASK
)) ==
733 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
736 static inline bool cpu_has_vmx_msr_bitmap(void)
738 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
741 static inline bool cpu_has_vmx_tpr_shadow(void)
743 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
746 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
748 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
751 static inline bool cpu_has_secondary_exec_ctrls(void)
753 return vmcs_config
.cpu_based_exec_ctrl
&
754 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
759 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
760 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
763 static inline bool cpu_has_vmx_flexpriority(void)
765 return cpu_has_vmx_tpr_shadow() &&
766 cpu_has_vmx_virtualize_apic_accesses();
769 static inline bool cpu_has_vmx_ept_execute_only(void)
771 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
776 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
779 static inline bool cpu_has_vmx_eptp_writeback(void)
781 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
784 static inline bool cpu_has_vmx_ept_2m_page(void)
786 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
789 static inline bool cpu_has_vmx_ept_1g_page(void)
791 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
794 static inline bool cpu_has_vmx_ept_4levels(void)
796 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
799 static inline bool cpu_has_vmx_ept_ad_bits(void)
801 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
804 static inline bool cpu_has_vmx_invept_individual_addr(void)
806 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
809 static inline bool cpu_has_vmx_invept_context(void)
811 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
814 static inline bool cpu_has_vmx_invept_global(void)
816 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
819 static inline bool cpu_has_vmx_invvpid_single(void)
821 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
824 static inline bool cpu_has_vmx_invvpid_global(void)
826 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
829 static inline bool cpu_has_vmx_ept(void)
831 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
832 SECONDARY_EXEC_ENABLE_EPT
;
835 static inline bool cpu_has_vmx_unrestricted_guest(void)
837 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
838 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
841 static inline bool cpu_has_vmx_ple(void)
843 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
844 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
847 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
849 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
852 static inline bool cpu_has_vmx_vpid(void)
854 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
855 SECONDARY_EXEC_ENABLE_VPID
;
858 static inline bool cpu_has_vmx_rdtscp(void)
860 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
861 SECONDARY_EXEC_RDTSCP
;
864 static inline bool cpu_has_vmx_invpcid(void)
866 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
867 SECONDARY_EXEC_ENABLE_INVPCID
;
870 static inline bool cpu_has_virtual_nmis(void)
872 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
875 static inline bool cpu_has_vmx_wbinvd_exit(void)
877 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
878 SECONDARY_EXEC_WBINVD_EXITING
;
881 static inline bool report_flexpriority(void)
883 return flexpriority_enabled
;
886 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
888 return vmcs12
->cpu_based_vm_exec_control
& bit
;
891 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
893 return (vmcs12
->cpu_based_vm_exec_control
&
894 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
895 (vmcs12
->secondary_vm_exec_control
& bit
);
898 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
899 struct kvm_vcpu
*vcpu
)
901 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
904 static inline bool is_exception(u32 intr_info
)
906 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
907 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
910 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
911 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
912 struct vmcs12
*vmcs12
,
913 u32 reason
, unsigned long qualification
);
915 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
919 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
920 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
925 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
931 } operand
= { vpid
, 0, gva
};
933 asm volatile (__ex(ASM_VMX_INVVPID
)
934 /* CF==1 or ZF==1 --> rc = -1 */
936 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
939 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
943 } operand
= {eptp
, gpa
};
945 asm volatile (__ex(ASM_VMX_INVEPT
)
946 /* CF==1 or ZF==1 --> rc = -1 */
947 "; ja 1f ; ud2 ; 1:\n"
948 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
951 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
955 i
= __find_msr_index(vmx
, msr
);
957 return &vmx
->guest_msrs
[i
];
961 static void vmcs_clear(struct vmcs
*vmcs
)
963 u64 phys_addr
= __pa(vmcs
);
966 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
967 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
970 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
974 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
976 vmcs_clear(loaded_vmcs
->vmcs
);
977 loaded_vmcs
->cpu
= -1;
978 loaded_vmcs
->launched
= 0;
981 static void vmcs_load(struct vmcs
*vmcs
)
983 u64 phys_addr
= __pa(vmcs
);
986 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
987 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
990 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
994 static void __loaded_vmcs_clear(void *arg
)
996 struct loaded_vmcs
*loaded_vmcs
= arg
;
997 int cpu
= raw_smp_processor_id();
999 if (loaded_vmcs
->cpu
!= cpu
)
1000 return; /* vcpu migration can race with cpu offline */
1001 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1002 per_cpu(current_vmcs
, cpu
) = NULL
;
1003 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1004 loaded_vmcs_init(loaded_vmcs
);
1007 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1009 if (loaded_vmcs
->cpu
!= -1)
1010 smp_call_function_single(
1011 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
1014 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1019 if (cpu_has_vmx_invvpid_single())
1020 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1023 static inline void vpid_sync_vcpu_global(void)
1025 if (cpu_has_vmx_invvpid_global())
1026 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1029 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1031 if (cpu_has_vmx_invvpid_single())
1032 vpid_sync_vcpu_single(vmx
);
1034 vpid_sync_vcpu_global();
1037 static inline void ept_sync_global(void)
1039 if (cpu_has_vmx_invept_global())
1040 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1043 static inline void ept_sync_context(u64 eptp
)
1046 if (cpu_has_vmx_invept_context())
1047 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1053 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
1056 if (cpu_has_vmx_invept_individual_addr())
1057 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
1060 ept_sync_context(eptp
);
1064 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1066 unsigned long value
;
1068 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1069 : "=a"(value
) : "d"(field
) : "cc");
1073 static __always_inline u16
vmcs_read16(unsigned long field
)
1075 return vmcs_readl(field
);
1078 static __always_inline u32
vmcs_read32(unsigned long field
)
1080 return vmcs_readl(field
);
1083 static __always_inline u64
vmcs_read64(unsigned long field
)
1085 #ifdef CONFIG_X86_64
1086 return vmcs_readl(field
);
1088 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1092 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1094 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1095 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1099 static void vmcs_writel(unsigned long field
, unsigned long value
)
1103 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1104 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1105 if (unlikely(error
))
1106 vmwrite_error(field
, value
);
1109 static void vmcs_write16(unsigned long field
, u16 value
)
1111 vmcs_writel(field
, value
);
1114 static void vmcs_write32(unsigned long field
, u32 value
)
1116 vmcs_writel(field
, value
);
1119 static void vmcs_write64(unsigned long field
, u64 value
)
1121 vmcs_writel(field
, value
);
1122 #ifndef CONFIG_X86_64
1124 vmcs_writel(field
+1, value
>> 32);
1128 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1130 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1133 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1135 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1138 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1140 vmx
->segment_cache
.bitmask
= 0;
1143 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1147 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1149 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1150 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1151 vmx
->segment_cache
.bitmask
= 0;
1153 ret
= vmx
->segment_cache
.bitmask
& mask
;
1154 vmx
->segment_cache
.bitmask
|= mask
;
1158 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1160 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1162 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1163 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1167 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1169 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1171 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1172 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1176 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1178 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1180 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1181 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1185 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1187 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1189 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1190 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1194 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1198 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1199 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1200 if ((vcpu
->guest_debug
&
1201 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1202 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1203 eb
|= 1u << BP_VECTOR
;
1204 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1207 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1208 if (vcpu
->fpu_active
)
1209 eb
&= ~(1u << NM_VECTOR
);
1211 /* When we are running a nested L2 guest and L1 specified for it a
1212 * certain exception bitmap, we must trap the same exceptions and pass
1213 * them to L1. When running L2, we will only handle the exceptions
1214 * specified above if L1 did not want them.
1216 if (is_guest_mode(vcpu
))
1217 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1219 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1222 static void clear_atomic_switch_msr_special(unsigned long entry
,
1225 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1226 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1229 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1232 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1236 if (cpu_has_load_ia32_efer
) {
1237 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1238 VM_EXIT_LOAD_IA32_EFER
);
1242 case MSR_CORE_PERF_GLOBAL_CTRL
:
1243 if (cpu_has_load_perf_global_ctrl
) {
1244 clear_atomic_switch_msr_special(
1245 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1246 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1252 for (i
= 0; i
< m
->nr
; ++i
)
1253 if (m
->guest
[i
].index
== msr
)
1259 m
->guest
[i
] = m
->guest
[m
->nr
];
1260 m
->host
[i
] = m
->host
[m
->nr
];
1261 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1262 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1265 static void add_atomic_switch_msr_special(unsigned long entry
,
1266 unsigned long exit
, unsigned long guest_val_vmcs
,
1267 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1269 vmcs_write64(guest_val_vmcs
, guest_val
);
1270 vmcs_write64(host_val_vmcs
, host_val
);
1271 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1272 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1275 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1276 u64 guest_val
, u64 host_val
)
1279 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1283 if (cpu_has_load_ia32_efer
) {
1284 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1285 VM_EXIT_LOAD_IA32_EFER
,
1288 guest_val
, host_val
);
1292 case MSR_CORE_PERF_GLOBAL_CTRL
:
1293 if (cpu_has_load_perf_global_ctrl
) {
1294 add_atomic_switch_msr_special(
1295 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1296 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1297 GUEST_IA32_PERF_GLOBAL_CTRL
,
1298 HOST_IA32_PERF_GLOBAL_CTRL
,
1299 guest_val
, host_val
);
1305 for (i
= 0; i
< m
->nr
; ++i
)
1306 if (m
->guest
[i
].index
== msr
)
1309 if (i
== NR_AUTOLOAD_MSRS
) {
1310 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1311 "Can't add msr %x\n", msr
);
1313 } else if (i
== m
->nr
) {
1315 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1316 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1319 m
->guest
[i
].index
= msr
;
1320 m
->guest
[i
].value
= guest_val
;
1321 m
->host
[i
].index
= msr
;
1322 m
->host
[i
].value
= host_val
;
1325 static void reload_tss(void)
1328 * VT restores TR but not its size. Useless.
1330 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1331 struct desc_struct
*descs
;
1333 descs
= (void *)gdt
->address
;
1334 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1338 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1343 guest_efer
= vmx
->vcpu
.arch
.efer
;
1346 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1349 ignore_bits
= EFER_NX
| EFER_SCE
;
1350 #ifdef CONFIG_X86_64
1351 ignore_bits
|= EFER_LMA
| EFER_LME
;
1352 /* SCE is meaningful only in long mode on Intel */
1353 if (guest_efer
& EFER_LMA
)
1354 ignore_bits
&= ~(u64
)EFER_SCE
;
1356 guest_efer
&= ~ignore_bits
;
1357 guest_efer
|= host_efer
& ignore_bits
;
1358 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1359 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1361 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1362 /* On ept, can't emulate nx, and must switch nx atomically */
1363 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1364 guest_efer
= vmx
->vcpu
.arch
.efer
;
1365 if (!(guest_efer
& EFER_LMA
))
1366 guest_efer
&= ~EFER_LME
;
1367 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1374 static unsigned long segment_base(u16 selector
)
1376 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1377 struct desc_struct
*d
;
1378 unsigned long table_base
;
1381 if (!(selector
& ~3))
1384 table_base
= gdt
->address
;
1386 if (selector
& 4) { /* from ldt */
1387 u16 ldt_selector
= kvm_read_ldt();
1389 if (!(ldt_selector
& ~3))
1392 table_base
= segment_base(ldt_selector
);
1394 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1395 v
= get_desc_base(d
);
1396 #ifdef CONFIG_X86_64
1397 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1398 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1403 static inline unsigned long kvm_read_tr_base(void)
1406 asm("str %0" : "=g"(tr
));
1407 return segment_base(tr
);
1410 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1412 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1415 if (vmx
->host_state
.loaded
)
1418 vmx
->host_state
.loaded
= 1;
1420 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1421 * allow segment selectors with cpl > 0 or ti == 1.
1423 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1424 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1425 savesegment(fs
, vmx
->host_state
.fs_sel
);
1426 if (!(vmx
->host_state
.fs_sel
& 7)) {
1427 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1428 vmx
->host_state
.fs_reload_needed
= 0;
1430 vmcs_write16(HOST_FS_SELECTOR
, 0);
1431 vmx
->host_state
.fs_reload_needed
= 1;
1433 savesegment(gs
, vmx
->host_state
.gs_sel
);
1434 if (!(vmx
->host_state
.gs_sel
& 7))
1435 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1437 vmcs_write16(HOST_GS_SELECTOR
, 0);
1438 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1441 #ifdef CONFIG_X86_64
1442 savesegment(ds
, vmx
->host_state
.ds_sel
);
1443 savesegment(es
, vmx
->host_state
.es_sel
);
1446 #ifdef CONFIG_X86_64
1447 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1448 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1450 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1451 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1454 #ifdef CONFIG_X86_64
1455 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1456 if (is_long_mode(&vmx
->vcpu
))
1457 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1459 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1460 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1461 vmx
->guest_msrs
[i
].data
,
1462 vmx
->guest_msrs
[i
].mask
);
1465 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1467 if (!vmx
->host_state
.loaded
)
1470 ++vmx
->vcpu
.stat
.host_state_reload
;
1471 vmx
->host_state
.loaded
= 0;
1472 #ifdef CONFIG_X86_64
1473 if (is_long_mode(&vmx
->vcpu
))
1474 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1476 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1477 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1478 #ifdef CONFIG_X86_64
1479 load_gs_index(vmx
->host_state
.gs_sel
);
1481 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1484 if (vmx
->host_state
.fs_reload_needed
)
1485 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1486 #ifdef CONFIG_X86_64
1487 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1488 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1489 loadsegment(es
, vmx
->host_state
.es_sel
);
1493 #ifdef CONFIG_X86_64
1494 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1498 load_gdt(&__get_cpu_var(host_gdt
));
1501 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1504 __vmx_load_host_state(vmx
);
1509 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1510 * vcpu mutex is already taken.
1512 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1514 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1515 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1518 kvm_cpu_vmxon(phys_addr
);
1519 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1520 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1522 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1523 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1524 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1527 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1528 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1529 unsigned long sysenter_esp
;
1531 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1532 local_irq_disable();
1533 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1534 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1538 * Linux uses per-cpu TSS and GDT, so set these when switching
1541 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1542 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1544 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1545 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1546 vmx
->loaded_vmcs
->cpu
= cpu
;
1550 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1552 __vmx_load_host_state(to_vmx(vcpu
));
1553 if (!vmm_exclusive
) {
1554 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1560 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1564 if (vcpu
->fpu_active
)
1566 vcpu
->fpu_active
= 1;
1567 cr0
= vmcs_readl(GUEST_CR0
);
1568 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1569 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1570 vmcs_writel(GUEST_CR0
, cr0
);
1571 update_exception_bitmap(vcpu
);
1572 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1573 if (is_guest_mode(vcpu
))
1574 vcpu
->arch
.cr0_guest_owned_bits
&=
1575 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1576 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1579 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1582 * Return the cr0 value that a nested guest would read. This is a combination
1583 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1584 * its hypervisor (cr0_read_shadow).
1586 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1588 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1589 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1591 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1593 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1594 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1597 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1599 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1600 * set this *before* calling this function.
1602 vmx_decache_cr0_guest_bits(vcpu
);
1603 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1604 update_exception_bitmap(vcpu
);
1605 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1606 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1607 if (is_guest_mode(vcpu
)) {
1609 * L1's specified read shadow might not contain the TS bit,
1610 * so now that we turned on shadowing of this bit, we need to
1611 * set this bit of the shadow. Like in nested_vmx_run we need
1612 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1613 * up-to-date here because we just decached cr0.TS (and we'll
1614 * only update vmcs12->guest_cr0 on nested exit).
1616 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1617 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1618 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1619 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1621 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1624 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1626 unsigned long rflags
, save_rflags
;
1628 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1629 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1630 rflags
= vmcs_readl(GUEST_RFLAGS
);
1631 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1632 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1633 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1634 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1636 to_vmx(vcpu
)->rflags
= rflags
;
1638 return to_vmx(vcpu
)->rflags
;
1641 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1643 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1644 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1645 to_vmx(vcpu
)->rflags
= rflags
;
1646 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1647 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1648 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1650 vmcs_writel(GUEST_RFLAGS
, rflags
);
1653 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1655 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1658 if (interruptibility
& GUEST_INTR_STATE_STI
)
1659 ret
|= KVM_X86_SHADOW_INT_STI
;
1660 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1661 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1666 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1668 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1669 u32 interruptibility
= interruptibility_old
;
1671 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1673 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1674 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1675 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1676 interruptibility
|= GUEST_INTR_STATE_STI
;
1678 if ((interruptibility
!= interruptibility_old
))
1679 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1682 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1686 rip
= kvm_rip_read(vcpu
);
1687 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1688 kvm_rip_write(vcpu
, rip
);
1690 /* skipping an emulated instruction also counts */
1691 vmx_set_interrupt_shadow(vcpu
, 0);
1695 * KVM wants to inject page-faults which it got to the guest. This function
1696 * checks whether in a nested guest, we need to inject them to L1 or L2.
1697 * This function assumes it is called with the exit reason in vmcs02 being
1698 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1701 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1703 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1705 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1706 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1709 nested_vmx_vmexit(vcpu
);
1713 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1714 bool has_error_code
, u32 error_code
,
1717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1718 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1720 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1721 nested_pf_handled(vcpu
))
1724 if (has_error_code
) {
1725 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1726 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1729 if (vmx
->rmode
.vm86_active
) {
1731 if (kvm_exception_is_soft(nr
))
1732 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1733 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1734 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1738 if (kvm_exception_is_soft(nr
)) {
1739 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1740 vmx
->vcpu
.arch
.event_exit_inst_len
);
1741 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1743 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1745 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1748 static bool vmx_rdtscp_supported(void)
1750 return cpu_has_vmx_rdtscp();
1753 static bool vmx_invpcid_supported(void)
1755 return cpu_has_vmx_invpcid() && enable_ept
;
1759 * Swap MSR entry in host/guest MSR entry array.
1761 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1763 struct shared_msr_entry tmp
;
1765 tmp
= vmx
->guest_msrs
[to
];
1766 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1767 vmx
->guest_msrs
[from
] = tmp
;
1771 * Set up the vmcs to automatically save and restore system
1772 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1773 * mode, as fiddling with msrs is very expensive.
1775 static void setup_msrs(struct vcpu_vmx
*vmx
)
1777 int save_nmsrs
, index
;
1778 unsigned long *msr_bitmap
;
1781 #ifdef CONFIG_X86_64
1782 if (is_long_mode(&vmx
->vcpu
)) {
1783 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1785 move_msr_up(vmx
, index
, save_nmsrs
++);
1786 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1788 move_msr_up(vmx
, index
, save_nmsrs
++);
1789 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1791 move_msr_up(vmx
, index
, save_nmsrs
++);
1792 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1793 if (index
>= 0 && vmx
->rdtscp_enabled
)
1794 move_msr_up(vmx
, index
, save_nmsrs
++);
1796 * MSR_STAR is only needed on long mode guests, and only
1797 * if efer.sce is enabled.
1799 index
= __find_msr_index(vmx
, MSR_STAR
);
1800 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1801 move_msr_up(vmx
, index
, save_nmsrs
++);
1804 index
= __find_msr_index(vmx
, MSR_EFER
);
1805 if (index
>= 0 && update_transition_efer(vmx
, index
))
1806 move_msr_up(vmx
, index
, save_nmsrs
++);
1808 vmx
->save_nmsrs
= save_nmsrs
;
1810 if (cpu_has_vmx_msr_bitmap()) {
1811 if (is_long_mode(&vmx
->vcpu
))
1812 msr_bitmap
= vmx_msr_bitmap_longmode
;
1814 msr_bitmap
= vmx_msr_bitmap_legacy
;
1816 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1821 * reads and returns guest's timestamp counter "register"
1822 * guest_tsc = host_tsc + tsc_offset -- 21.3
1824 static u64
guest_read_tsc(void)
1826 u64 host_tsc
, tsc_offset
;
1829 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1830 return host_tsc
+ tsc_offset
;
1834 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1835 * counter, even if a nested guest (L2) is currently running.
1837 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
)
1839 u64 host_tsc
, tsc_offset
;
1842 tsc_offset
= is_guest_mode(vcpu
) ?
1843 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1844 vmcs_read64(TSC_OFFSET
);
1845 return host_tsc
+ tsc_offset
;
1849 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1850 * software catchup for faster rates on slower CPUs.
1852 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1857 if (user_tsc_khz
> tsc_khz
) {
1858 vcpu
->arch
.tsc_catchup
= 1;
1859 vcpu
->arch
.tsc_always_catchup
= 1;
1861 WARN(1, "user requested TSC rate below hardware speed\n");
1865 * writes 'offset' into guest's timestamp counter offset register
1867 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1869 if (is_guest_mode(vcpu
)) {
1871 * We're here if L1 chose not to trap WRMSR to TSC. According
1872 * to the spec, this should set L1's TSC; The offset that L1
1873 * set for L2 remains unchanged, and still needs to be added
1874 * to the newly set TSC to get L2's TSC.
1876 struct vmcs12
*vmcs12
;
1877 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1878 /* recalculate vmcs02.TSC_OFFSET: */
1879 vmcs12
= get_vmcs12(vcpu
);
1880 vmcs_write64(TSC_OFFSET
, offset
+
1881 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1882 vmcs12
->tsc_offset
: 0));
1884 vmcs_write64(TSC_OFFSET
, offset
);
1888 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1890 u64 offset
= vmcs_read64(TSC_OFFSET
);
1891 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1892 if (is_guest_mode(vcpu
)) {
1893 /* Even when running L2, the adjustment needs to apply to L1 */
1894 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1898 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1900 return target_tsc
- native_read_tsc();
1903 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1905 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1906 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1910 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1911 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1912 * all guests if the "nested" module option is off, and can also be disabled
1913 * for a single guest by disabling its VMX cpuid bit.
1915 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1917 return nested
&& guest_cpuid_has_vmx(vcpu
);
1921 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1922 * returned for the various VMX controls MSRs when nested VMX is enabled.
1923 * The same values should also be used to verify that vmcs12 control fields are
1924 * valid during nested entry from L1 to L2.
1925 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1926 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1927 * bit in the high half is on if the corresponding bit in the control field
1928 * may be on. See also vmx_control_verify().
1929 * TODO: allow these variables to be modified (downgraded) by module options
1932 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1933 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1934 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1935 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1936 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1937 static __init
void nested_vmx_setup_ctls_msrs(void)
1940 * Note that as a general rule, the high half of the MSRs (bits in
1941 * the control fields which may be 1) should be initialized by the
1942 * intersection of the underlying hardware's MSR (i.e., features which
1943 * can be supported) and the list of features we want to expose -
1944 * because they are known to be properly supported in our code.
1945 * Also, usually, the low half of the MSRs (bits which must be 1) can
1946 * be set to 0, meaning that L1 may turn off any of these bits. The
1947 * reason is that if one of these bits is necessary, it will appear
1948 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1949 * fields of vmcs01 and vmcs02, will turn these bits off - and
1950 * nested_vmx_exit_handled() will not pass related exits to L1.
1951 * These rules have exceptions below.
1954 /* pin-based controls */
1956 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1957 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1959 nested_vmx_pinbased_ctls_low
= 0x16 ;
1960 nested_vmx_pinbased_ctls_high
= 0x16 |
1961 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1962 PIN_BASED_VIRTUAL_NMIS
;
1965 nested_vmx_exit_ctls_low
= 0;
1966 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1967 #ifdef CONFIG_X86_64
1968 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1970 nested_vmx_exit_ctls_high
= 0;
1973 /* entry controls */
1974 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1975 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1976 nested_vmx_entry_ctls_low
= 0;
1977 nested_vmx_entry_ctls_high
&=
1978 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1980 /* cpu-based controls */
1981 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1982 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1983 nested_vmx_procbased_ctls_low
= 0;
1984 nested_vmx_procbased_ctls_high
&=
1985 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1986 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1987 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1988 CPU_BASED_CR3_STORE_EXITING
|
1989 #ifdef CONFIG_X86_64
1990 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1992 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1993 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1994 CPU_BASED_RDPMC_EXITING
|
1995 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1997 * We can allow some features even when not supported by the
1998 * hardware. For example, L1 can specify an MSR bitmap - and we
1999 * can use it to avoid exits to L1 - even when L0 runs L2
2000 * without MSR bitmaps.
2002 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2004 /* secondary cpu-based controls */
2005 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2006 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2007 nested_vmx_secondary_ctls_low
= 0;
2008 nested_vmx_secondary_ctls_high
&=
2009 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2012 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2015 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2017 return ((control
& high
) | low
) == control
;
2020 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2022 return low
| ((u64
)high
<< 32);
2026 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2027 * also let it use VMX-specific MSRs.
2028 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2029 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2030 * like all other MSRs).
2032 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2034 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2035 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2037 * According to the spec, processors which do not support VMX
2038 * should throw a #GP(0) when VMX capability MSRs are read.
2040 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2044 switch (msr_index
) {
2045 case MSR_IA32_FEATURE_CONTROL
:
2048 case MSR_IA32_VMX_BASIC
:
2050 * This MSR reports some information about VMX support. We
2051 * should return information about the VMX we emulate for the
2052 * guest, and the VMCS structure we give it - not about the
2053 * VMX support of the underlying hardware.
2055 *pdata
= VMCS12_REVISION
|
2056 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2057 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2059 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2060 case MSR_IA32_VMX_PINBASED_CTLS
:
2061 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2062 nested_vmx_pinbased_ctls_high
);
2064 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2065 case MSR_IA32_VMX_PROCBASED_CTLS
:
2066 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2067 nested_vmx_procbased_ctls_high
);
2069 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2070 case MSR_IA32_VMX_EXIT_CTLS
:
2071 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2072 nested_vmx_exit_ctls_high
);
2074 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2075 case MSR_IA32_VMX_ENTRY_CTLS
:
2076 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2077 nested_vmx_entry_ctls_high
);
2079 case MSR_IA32_VMX_MISC
:
2083 * These MSRs specify bits which the guest must keep fixed (on or off)
2084 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2085 * We picked the standard core2 setting.
2087 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2088 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2089 case MSR_IA32_VMX_CR0_FIXED0
:
2090 *pdata
= VMXON_CR0_ALWAYSON
;
2092 case MSR_IA32_VMX_CR0_FIXED1
:
2095 case MSR_IA32_VMX_CR4_FIXED0
:
2096 *pdata
= VMXON_CR4_ALWAYSON
;
2098 case MSR_IA32_VMX_CR4_FIXED1
:
2101 case MSR_IA32_VMX_VMCS_ENUM
:
2104 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2105 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2106 nested_vmx_secondary_ctls_high
);
2108 case MSR_IA32_VMX_EPT_VPID_CAP
:
2109 /* Currently, no nested ept or nested vpid */
2119 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2121 if (!nested_vmx_allowed(vcpu
))
2124 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2125 /* TODO: the right thing. */
2128 * No need to treat VMX capability MSRs specially: If we don't handle
2129 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2135 * Reads an msr value (of 'msr_index') into 'pdata'.
2136 * Returns 0 on success, non-0 otherwise.
2137 * Assumes vcpu_load() was already called.
2139 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2142 struct shared_msr_entry
*msr
;
2145 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2149 switch (msr_index
) {
2150 #ifdef CONFIG_X86_64
2152 data
= vmcs_readl(GUEST_FS_BASE
);
2155 data
= vmcs_readl(GUEST_GS_BASE
);
2157 case MSR_KERNEL_GS_BASE
:
2158 vmx_load_host_state(to_vmx(vcpu
));
2159 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2163 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2165 data
= guest_read_tsc();
2167 case MSR_IA32_SYSENTER_CS
:
2168 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2170 case MSR_IA32_SYSENTER_EIP
:
2171 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2173 case MSR_IA32_SYSENTER_ESP
:
2174 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2177 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2179 /* Otherwise falls through */
2181 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2183 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2188 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2196 * Writes msr value into into the appropriate "register".
2197 * Returns 0 on success, non-0 otherwise.
2198 * Assumes vcpu_load() was already called.
2200 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2202 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2203 struct shared_msr_entry
*msr
;
2206 switch (msr_index
) {
2208 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2210 #ifdef CONFIG_X86_64
2212 vmx_segment_cache_clear(vmx
);
2213 vmcs_writel(GUEST_FS_BASE
, data
);
2216 vmx_segment_cache_clear(vmx
);
2217 vmcs_writel(GUEST_GS_BASE
, data
);
2219 case MSR_KERNEL_GS_BASE
:
2220 vmx_load_host_state(vmx
);
2221 vmx
->msr_guest_kernel_gs_base
= data
;
2224 case MSR_IA32_SYSENTER_CS
:
2225 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2227 case MSR_IA32_SYSENTER_EIP
:
2228 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2230 case MSR_IA32_SYSENTER_ESP
:
2231 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2234 kvm_write_tsc(vcpu
, data
);
2236 case MSR_IA32_CR_PAT
:
2237 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2238 vmcs_write64(GUEST_IA32_PAT
, data
);
2239 vcpu
->arch
.pat
= data
;
2242 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2245 if (!vmx
->rdtscp_enabled
)
2247 /* Check reserved bit, higher 32 bits should be zero */
2248 if ((data
>> 32) != 0)
2250 /* Otherwise falls through */
2252 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2254 msr
= find_msr_entry(vmx
, msr_index
);
2257 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2259 kvm_set_shared_msr(msr
->index
, msr
->data
,
2265 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2271 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2273 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2276 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2279 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2281 case VCPU_EXREG_PDPTR
:
2283 ept_save_pdptrs(vcpu
);
2290 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
2292 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
2293 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
2295 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2297 update_exception_bitmap(vcpu
);
2300 static __init
int cpu_has_kvm_support(void)
2302 return cpu_has_vmx();
2305 static __init
int vmx_disabled_by_bios(void)
2309 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2310 if (msr
& FEATURE_CONTROL_LOCKED
) {
2311 /* launched w/ TXT and VMX disabled */
2312 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2315 /* launched w/o TXT and VMX only enabled w/ TXT */
2316 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2317 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2318 && !tboot_enabled()) {
2319 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2320 "activate TXT before enabling KVM\n");
2323 /* launched w/o TXT and VMX disabled */
2324 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2325 && !tboot_enabled())
2332 static void kvm_cpu_vmxon(u64 addr
)
2334 asm volatile (ASM_VMX_VMXON_RAX
2335 : : "a"(&addr
), "m"(addr
)
2339 static int hardware_enable(void *garbage
)
2341 int cpu
= raw_smp_processor_id();
2342 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2345 if (read_cr4() & X86_CR4_VMXE
)
2348 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2349 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2351 test_bits
= FEATURE_CONTROL_LOCKED
;
2352 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2353 if (tboot_enabled())
2354 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2356 if ((old
& test_bits
) != test_bits
) {
2357 /* enable and lock */
2358 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2360 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2362 if (vmm_exclusive
) {
2363 kvm_cpu_vmxon(phys_addr
);
2367 store_gdt(&__get_cpu_var(host_gdt
));
2372 static void vmclear_local_loaded_vmcss(void)
2374 int cpu
= raw_smp_processor_id();
2375 struct loaded_vmcs
*v
, *n
;
2377 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2378 loaded_vmcss_on_cpu_link
)
2379 __loaded_vmcs_clear(v
);
2383 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2386 static void kvm_cpu_vmxoff(void)
2388 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2391 static void hardware_disable(void *garbage
)
2393 if (vmm_exclusive
) {
2394 vmclear_local_loaded_vmcss();
2397 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2400 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2401 u32 msr
, u32
*result
)
2403 u32 vmx_msr_low
, vmx_msr_high
;
2404 u32 ctl
= ctl_min
| ctl_opt
;
2406 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2408 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2409 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2411 /* Ensure minimum (required) set of control bits are supported. */
2419 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2421 u32 vmx_msr_low
, vmx_msr_high
;
2423 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2424 return vmx_msr_high
& ctl
;
2427 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2429 u32 vmx_msr_low
, vmx_msr_high
;
2430 u32 min
, opt
, min2
, opt2
;
2431 u32 _pin_based_exec_control
= 0;
2432 u32 _cpu_based_exec_control
= 0;
2433 u32 _cpu_based_2nd_exec_control
= 0;
2434 u32 _vmexit_control
= 0;
2435 u32 _vmentry_control
= 0;
2437 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2438 opt
= PIN_BASED_VIRTUAL_NMIS
;
2439 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2440 &_pin_based_exec_control
) < 0)
2443 min
= CPU_BASED_HLT_EXITING
|
2444 #ifdef CONFIG_X86_64
2445 CPU_BASED_CR8_LOAD_EXITING
|
2446 CPU_BASED_CR8_STORE_EXITING
|
2448 CPU_BASED_CR3_LOAD_EXITING
|
2449 CPU_BASED_CR3_STORE_EXITING
|
2450 CPU_BASED_USE_IO_BITMAPS
|
2451 CPU_BASED_MOV_DR_EXITING
|
2452 CPU_BASED_USE_TSC_OFFSETING
|
2453 CPU_BASED_MWAIT_EXITING
|
2454 CPU_BASED_MONITOR_EXITING
|
2455 CPU_BASED_INVLPG_EXITING
|
2456 CPU_BASED_RDPMC_EXITING
;
2458 opt
= CPU_BASED_TPR_SHADOW
|
2459 CPU_BASED_USE_MSR_BITMAPS
|
2460 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2461 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2462 &_cpu_based_exec_control
) < 0)
2464 #ifdef CONFIG_X86_64
2465 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2466 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2467 ~CPU_BASED_CR8_STORE_EXITING
;
2469 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2471 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2472 SECONDARY_EXEC_WBINVD_EXITING
|
2473 SECONDARY_EXEC_ENABLE_VPID
|
2474 SECONDARY_EXEC_ENABLE_EPT
|
2475 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2476 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2477 SECONDARY_EXEC_RDTSCP
|
2478 SECONDARY_EXEC_ENABLE_INVPCID
;
2479 if (adjust_vmx_controls(min2
, opt2
,
2480 MSR_IA32_VMX_PROCBASED_CTLS2
,
2481 &_cpu_based_2nd_exec_control
) < 0)
2484 #ifndef CONFIG_X86_64
2485 if (!(_cpu_based_2nd_exec_control
&
2486 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2487 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2489 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2490 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2492 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2493 CPU_BASED_CR3_STORE_EXITING
|
2494 CPU_BASED_INVLPG_EXITING
);
2495 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2496 vmx_capability
.ept
, vmx_capability
.vpid
);
2500 #ifdef CONFIG_X86_64
2501 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2503 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2504 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2505 &_vmexit_control
) < 0)
2509 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2510 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2511 &_vmentry_control
) < 0)
2514 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2516 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2517 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2520 #ifdef CONFIG_X86_64
2521 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2522 if (vmx_msr_high
& (1u<<16))
2526 /* Require Write-Back (WB) memory type for VMCS accesses. */
2527 if (((vmx_msr_high
>> 18) & 15) != 6)
2530 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2531 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2532 vmcs_conf
->revision_id
= vmx_msr_low
;
2534 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2535 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2536 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2537 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2538 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2540 cpu_has_load_ia32_efer
=
2541 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2542 VM_ENTRY_LOAD_IA32_EFER
)
2543 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2544 VM_EXIT_LOAD_IA32_EFER
);
2546 cpu_has_load_perf_global_ctrl
=
2547 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2548 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2549 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2550 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2553 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2554 * but due to arrata below it can't be used. Workaround is to use
2555 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2557 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2562 * BC86,AAY89,BD102 (model 44)
2566 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2567 switch (boot_cpu_data
.x86_model
) {
2573 cpu_has_load_perf_global_ctrl
= false;
2574 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2575 "does not work properly. Using workaround\n");
2585 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2587 int node
= cpu_to_node(cpu
);
2591 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2594 vmcs
= page_address(pages
);
2595 memset(vmcs
, 0, vmcs_config
.size
);
2596 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2600 static struct vmcs
*alloc_vmcs(void)
2602 return alloc_vmcs_cpu(raw_smp_processor_id());
2605 static void free_vmcs(struct vmcs
*vmcs
)
2607 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2611 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2613 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2615 if (!loaded_vmcs
->vmcs
)
2617 loaded_vmcs_clear(loaded_vmcs
);
2618 free_vmcs(loaded_vmcs
->vmcs
);
2619 loaded_vmcs
->vmcs
= NULL
;
2622 static void free_kvm_area(void)
2626 for_each_possible_cpu(cpu
) {
2627 free_vmcs(per_cpu(vmxarea
, cpu
));
2628 per_cpu(vmxarea
, cpu
) = NULL
;
2632 static __init
int alloc_kvm_area(void)
2636 for_each_possible_cpu(cpu
) {
2639 vmcs
= alloc_vmcs_cpu(cpu
);
2645 per_cpu(vmxarea
, cpu
) = vmcs
;
2650 static __init
int hardware_setup(void)
2652 if (setup_vmcs_config(&vmcs_config
) < 0)
2655 if (boot_cpu_has(X86_FEATURE_NX
))
2656 kvm_enable_efer_bits(EFER_NX
);
2658 if (!cpu_has_vmx_vpid())
2661 if (!cpu_has_vmx_ept() ||
2662 !cpu_has_vmx_ept_4levels()) {
2664 enable_unrestricted_guest
= 0;
2665 enable_ept_ad_bits
= 0;
2668 if (!cpu_has_vmx_ept_ad_bits())
2669 enable_ept_ad_bits
= 0;
2671 if (!cpu_has_vmx_unrestricted_guest())
2672 enable_unrestricted_guest
= 0;
2674 if (!cpu_has_vmx_flexpriority())
2675 flexpriority_enabled
= 0;
2677 if (!cpu_has_vmx_tpr_shadow())
2678 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2680 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2681 kvm_disable_largepages();
2683 if (!cpu_has_vmx_ple())
2687 nested_vmx_setup_ctls_msrs();
2689 return alloc_kvm_area();
2692 static __exit
void hardware_unsetup(void)
2697 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2699 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2701 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2702 vmcs_write16(sf
->selector
, save
->selector
);
2703 vmcs_writel(sf
->base
, save
->base
);
2704 vmcs_write32(sf
->limit
, save
->limit
);
2705 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2707 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2709 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2713 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2715 unsigned long flags
;
2716 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2718 vmx
->emulation_required
= 1;
2719 vmx
->rmode
.vm86_active
= 0;
2721 vmx_segment_cache_clear(vmx
);
2723 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2724 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2725 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2726 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2728 flags
= vmcs_readl(GUEST_RFLAGS
);
2729 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2730 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2731 vmcs_writel(GUEST_RFLAGS
, flags
);
2733 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2734 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2736 update_exception_bitmap(vcpu
);
2738 if (emulate_invalid_guest_state
)
2741 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2742 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2743 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2744 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2746 vmx_segment_cache_clear(vmx
);
2748 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2749 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2751 vmcs_write16(GUEST_CS_SELECTOR
,
2752 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2753 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2756 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2758 if (!kvm
->arch
.tss_addr
) {
2759 struct kvm_memslots
*slots
;
2760 struct kvm_memory_slot
*slot
;
2763 slots
= kvm_memslots(kvm
);
2764 slot
= id_to_memslot(slots
, 0);
2765 base_gfn
= slot
->base_gfn
+ slot
->npages
- 3;
2767 return base_gfn
<< PAGE_SHIFT
;
2769 return kvm
->arch
.tss_addr
;
2772 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2774 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2776 save
->selector
= vmcs_read16(sf
->selector
);
2777 save
->base
= vmcs_readl(sf
->base
);
2778 save
->limit
= vmcs_read32(sf
->limit
);
2779 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2780 vmcs_write16(sf
->selector
, save
->base
>> 4);
2781 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2782 vmcs_write32(sf
->limit
, 0xffff);
2783 vmcs_write32(sf
->ar_bytes
, 0xf3);
2784 if (save
->base
& 0xf)
2785 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2786 " aligned when entering protected mode (seg=%d)",
2790 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2792 unsigned long flags
;
2793 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2794 struct kvm_segment var
;
2796 if (enable_unrestricted_guest
)
2799 vmx
->emulation_required
= 1;
2800 vmx
->rmode
.vm86_active
= 1;
2803 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2804 * vcpu. Call it here with phys address pointing 16M below 4G.
2806 if (!vcpu
->kvm
->arch
.tss_addr
) {
2807 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2808 "called before entering vcpu\n");
2809 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2810 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2811 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2814 vmx_segment_cache_clear(vmx
);
2816 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2817 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2818 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2820 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2821 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2823 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2824 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2826 flags
= vmcs_readl(GUEST_RFLAGS
);
2827 vmx
->rmode
.save_rflags
= flags
;
2829 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2831 vmcs_writel(GUEST_RFLAGS
, flags
);
2832 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2833 update_exception_bitmap(vcpu
);
2835 if (emulate_invalid_guest_state
)
2836 goto continue_rmode
;
2838 vmx_get_segment(vcpu
, &var
, VCPU_SREG_SS
);
2839 vmx_set_segment(vcpu
, &var
, VCPU_SREG_SS
);
2841 vmx_get_segment(vcpu
, &var
, VCPU_SREG_CS
);
2842 vmx_set_segment(vcpu
, &var
, VCPU_SREG_CS
);
2844 vmx_get_segment(vcpu
, &var
, VCPU_SREG_ES
);
2845 vmx_set_segment(vcpu
, &var
, VCPU_SREG_ES
);
2847 vmx_get_segment(vcpu
, &var
, VCPU_SREG_DS
);
2848 vmx_set_segment(vcpu
, &var
, VCPU_SREG_DS
);
2850 vmx_get_segment(vcpu
, &var
, VCPU_SREG_GS
);
2851 vmx_set_segment(vcpu
, &var
, VCPU_SREG_GS
);
2853 vmx_get_segment(vcpu
, &var
, VCPU_SREG_FS
);
2854 vmx_set_segment(vcpu
, &var
, VCPU_SREG_FS
);
2857 kvm_mmu_reset_context(vcpu
);
2860 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2862 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2863 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2869 * Force kernel_gs_base reloading before EFER changes, as control
2870 * of this msr depends on is_long_mode().
2872 vmx_load_host_state(to_vmx(vcpu
));
2873 vcpu
->arch
.efer
= efer
;
2874 if (efer
& EFER_LMA
) {
2875 vmcs_write32(VM_ENTRY_CONTROLS
,
2876 vmcs_read32(VM_ENTRY_CONTROLS
) |
2877 VM_ENTRY_IA32E_MODE
);
2880 vmcs_write32(VM_ENTRY_CONTROLS
,
2881 vmcs_read32(VM_ENTRY_CONTROLS
) &
2882 ~VM_ENTRY_IA32E_MODE
);
2884 msr
->data
= efer
& ~EFER_LME
;
2889 #ifdef CONFIG_X86_64
2891 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2895 vmx_segment_cache_clear(to_vmx(vcpu
));
2897 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2898 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2899 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2901 vmcs_write32(GUEST_TR_AR_BYTES
,
2902 (guest_tr_ar
& ~AR_TYPE_MASK
)
2903 | AR_TYPE_BUSY_64_TSS
);
2905 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2908 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2910 vmcs_write32(VM_ENTRY_CONTROLS
,
2911 vmcs_read32(VM_ENTRY_CONTROLS
)
2912 & ~VM_ENTRY_IA32E_MODE
);
2913 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2918 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2920 vpid_sync_context(to_vmx(vcpu
));
2922 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2924 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2928 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2930 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2932 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2933 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2936 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2938 if (enable_ept
&& is_paging(vcpu
))
2939 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2940 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2943 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2945 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2947 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2948 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2951 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2953 if (!test_bit(VCPU_EXREG_PDPTR
,
2954 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2957 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2958 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2959 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2960 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2961 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2965 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2967 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2968 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2969 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2970 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2971 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2974 __set_bit(VCPU_EXREG_PDPTR
,
2975 (unsigned long *)&vcpu
->arch
.regs_avail
);
2976 __set_bit(VCPU_EXREG_PDPTR
,
2977 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2980 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2982 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2984 struct kvm_vcpu
*vcpu
)
2986 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2987 vmx_decache_cr3(vcpu
);
2988 if (!(cr0
& X86_CR0_PG
)) {
2989 /* From paging/starting to nonpaging */
2990 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2991 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2992 (CPU_BASED_CR3_LOAD_EXITING
|
2993 CPU_BASED_CR3_STORE_EXITING
));
2994 vcpu
->arch
.cr0
= cr0
;
2995 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2996 } else if (!is_paging(vcpu
)) {
2997 /* From nonpaging to paging */
2998 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2999 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3000 ~(CPU_BASED_CR3_LOAD_EXITING
|
3001 CPU_BASED_CR3_STORE_EXITING
));
3002 vcpu
->arch
.cr0
= cr0
;
3003 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3006 if (!(cr0
& X86_CR0_WP
))
3007 *hw_cr0
&= ~X86_CR0_WP
;
3010 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3012 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3013 unsigned long hw_cr0
;
3015 if (enable_unrestricted_guest
)
3016 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
3017 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3019 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
3021 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3024 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3027 #ifdef CONFIG_X86_64
3028 if (vcpu
->arch
.efer
& EFER_LME
) {
3029 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3031 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3037 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3039 if (!vcpu
->fpu_active
)
3040 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3042 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3043 vmcs_writel(GUEST_CR0
, hw_cr0
);
3044 vcpu
->arch
.cr0
= cr0
;
3045 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3048 static u64
construct_eptp(unsigned long root_hpa
)
3052 /* TODO write the value reading from MSR */
3053 eptp
= VMX_EPT_DEFAULT_MT
|
3054 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3055 if (enable_ept_ad_bits
)
3056 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3057 eptp
|= (root_hpa
& PAGE_MASK
);
3062 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3064 unsigned long guest_cr3
;
3069 eptp
= construct_eptp(cr3
);
3070 vmcs_write64(EPT_POINTER
, eptp
);
3071 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3072 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3073 ept_load_pdptrs(vcpu
);
3076 vmx_flush_tlb(vcpu
);
3077 vmcs_writel(GUEST_CR3
, guest_cr3
);
3080 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3082 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3083 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3085 if (cr4
& X86_CR4_VMXE
) {
3087 * To use VMXON (and later other VMX instructions), a guest
3088 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3089 * So basically the check on whether to allow nested VMX
3092 if (!nested_vmx_allowed(vcpu
))
3094 } else if (to_vmx(vcpu
)->nested
.vmxon
)
3097 vcpu
->arch
.cr4
= cr4
;
3099 if (!is_paging(vcpu
)) {
3100 hw_cr4
&= ~X86_CR4_PAE
;
3101 hw_cr4
|= X86_CR4_PSE
;
3102 } else if (!(cr4
& X86_CR4_PAE
)) {
3103 hw_cr4
&= ~X86_CR4_PAE
;
3107 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3108 vmcs_writel(GUEST_CR4
, hw_cr4
);
3112 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3113 struct kvm_segment
*var
, int seg
)
3115 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3116 struct kvm_save_segment
*save
;
3119 if (vmx
->rmode
.vm86_active
3120 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
3121 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
3122 || seg
== VCPU_SREG_GS
)
3123 && !emulate_invalid_guest_state
) {
3125 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
3126 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
3127 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
3128 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
3129 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
3132 var
->selector
= save
->selector
;
3133 var
->base
= save
->base
;
3134 var
->limit
= save
->limit
;
3136 if (seg
== VCPU_SREG_TR
3137 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3138 goto use_saved_rmode_seg
;
3140 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3141 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3142 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3143 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3144 use_saved_rmode_seg
:
3145 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
3147 var
->type
= ar
& 15;
3148 var
->s
= (ar
>> 4) & 1;
3149 var
->dpl
= (ar
>> 5) & 3;
3150 var
->present
= (ar
>> 7) & 1;
3151 var
->avl
= (ar
>> 12) & 1;
3152 var
->l
= (ar
>> 13) & 1;
3153 var
->db
= (ar
>> 14) & 1;
3154 var
->g
= (ar
>> 15) & 1;
3155 var
->unusable
= (ar
>> 16) & 1;
3158 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3160 struct kvm_segment s
;
3162 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3163 vmx_get_segment(vcpu
, &s
, seg
);
3166 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3169 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3171 if (!is_protmode(vcpu
))
3174 if (!is_long_mode(vcpu
)
3175 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3178 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
3181 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3183 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3186 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3187 * fail; use the cache instead.
3189 if (unlikely(vmx
->emulation_required
&& emulate_invalid_guest_state
)) {
3193 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3194 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3195 vmx
->cpl
= __vmx_get_cpl(vcpu
);
3202 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3206 if (var
->unusable
|| !var
->present
)
3209 ar
= var
->type
& 15;
3210 ar
|= (var
->s
& 1) << 4;
3211 ar
|= (var
->dpl
& 3) << 5;
3212 ar
|= (var
->present
& 1) << 7;
3213 ar
|= (var
->avl
& 1) << 12;
3214 ar
|= (var
->l
& 1) << 13;
3215 ar
|= (var
->db
& 1) << 14;
3216 ar
|= (var
->g
& 1) << 15;
3222 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3223 struct kvm_segment
*var
, int seg
)
3225 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3226 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3229 vmx_segment_cache_clear(vmx
);
3231 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
3232 vmcs_write16(sf
->selector
, var
->selector
);
3233 vmx
->rmode
.tr
.selector
= var
->selector
;
3234 vmx
->rmode
.tr
.base
= var
->base
;
3235 vmx
->rmode
.tr
.limit
= var
->limit
;
3236 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
3239 vmcs_writel(sf
->base
, var
->base
);
3240 vmcs_write32(sf
->limit
, var
->limit
);
3241 vmcs_write16(sf
->selector
, var
->selector
);
3242 if (vmx
->rmode
.vm86_active
&& var
->s
) {
3244 * Hack real-mode segments into vm86 compatibility.
3246 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
3247 vmcs_writel(sf
->base
, 0xf0000);
3250 ar
= vmx_segment_access_rights(var
);
3253 * Fix the "Accessed" bit in AR field of segment registers for older
3255 * IA32 arch specifies that at the time of processor reset the
3256 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3257 * is setting it to 0 in the usedland code. This causes invalid guest
3258 * state vmexit when "unrestricted guest" mode is turned on.
3259 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3260 * tree. Newer qemu binaries with that qemu fix would not need this
3263 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3264 ar
|= 0x1; /* Accessed */
3266 vmcs_write32(sf
->ar_bytes
, ar
);
3267 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3270 * Fix segments for real mode guest in hosts that don't have
3271 * "unrestricted_mode" or it was disabled.
3272 * This is done to allow migration of the guests from hosts with
3273 * unrestricted guest like Westmere to older host that don't have
3274 * unrestricted guest like Nehelem.
3276 if (!enable_unrestricted_guest
&& vmx
->rmode
.vm86_active
) {
3279 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
3280 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
3281 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
3282 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
3283 vmcs_write16(GUEST_CS_SELECTOR
,
3284 vmcs_readl(GUEST_CS_BASE
) >> 4);
3287 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
3290 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
3293 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
3296 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
3299 vmcs_write16(GUEST_SS_SELECTOR
,
3300 vmcs_readl(GUEST_SS_BASE
) >> 4);
3301 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
3302 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
3308 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3310 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3312 *db
= (ar
>> 14) & 1;
3313 *l
= (ar
>> 13) & 1;
3316 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3318 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3319 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3322 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3324 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3325 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3328 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3330 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3331 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3334 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3336 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3337 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3340 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3342 struct kvm_segment var
;
3345 vmx_get_segment(vcpu
, &var
, seg
);
3346 ar
= vmx_segment_access_rights(&var
);
3348 if (var
.base
!= (var
.selector
<< 4))
3350 if (var
.limit
!= 0xffff)
3358 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3360 struct kvm_segment cs
;
3361 unsigned int cs_rpl
;
3363 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3364 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3368 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3372 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3373 if (cs
.dpl
> cs_rpl
)
3376 if (cs
.dpl
!= cs_rpl
)
3382 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3386 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3388 struct kvm_segment ss
;
3389 unsigned int ss_rpl
;
3391 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3392 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3396 if (ss
.type
!= 3 && ss
.type
!= 7)
3400 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3408 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3410 struct kvm_segment var
;
3413 vmx_get_segment(vcpu
, &var
, seg
);
3414 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3422 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3423 if (var
.dpl
< rpl
) /* DPL < RPL */
3427 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3433 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3435 struct kvm_segment tr
;
3437 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3441 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3443 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3451 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3453 struct kvm_segment ldtr
;
3455 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3459 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3469 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3471 struct kvm_segment cs
, ss
;
3473 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3474 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3476 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3477 (ss
.selector
& SELECTOR_RPL_MASK
));
3481 * Check if guest state is valid. Returns true if valid, false if
3483 * We assume that registers are always usable
3485 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3487 /* real mode guest state checks */
3488 if (!is_protmode(vcpu
)) {
3489 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3491 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3493 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3495 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3497 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3499 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3502 /* protected mode guest state checks */
3503 if (!cs_ss_rpl_check(vcpu
))
3505 if (!code_segment_valid(vcpu
))
3507 if (!stack_segment_valid(vcpu
))
3509 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3511 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3513 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3515 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3517 if (!tr_valid(vcpu
))
3519 if (!ldtr_valid(vcpu
))
3523 * - Add checks on RIP
3524 * - Add checks on RFLAGS
3530 static int init_rmode_tss(struct kvm
*kvm
)
3534 int r
, idx
, ret
= 0;
3536 idx
= srcu_read_lock(&kvm
->srcu
);
3537 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3538 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3541 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3542 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3543 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3546 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3549 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3553 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3554 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3561 srcu_read_unlock(&kvm
->srcu
, idx
);
3565 static int init_rmode_identity_map(struct kvm
*kvm
)
3568 pfn_t identity_map_pfn
;
3573 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3574 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3575 "haven't been allocated!\n");
3578 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3581 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3582 idx
= srcu_read_lock(&kvm
->srcu
);
3583 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3586 /* Set up identity-mapping pagetable for EPT in real mode */
3587 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3588 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3589 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3590 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3591 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3595 kvm
->arch
.ept_identity_pagetable_done
= true;
3598 srcu_read_unlock(&kvm
->srcu
, idx
);
3602 static void seg_setup(int seg
)
3604 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3607 vmcs_write16(sf
->selector
, 0);
3608 vmcs_writel(sf
->base
, 0);
3609 vmcs_write32(sf
->limit
, 0xffff);
3610 if (enable_unrestricted_guest
) {
3612 if (seg
== VCPU_SREG_CS
)
3613 ar
|= 0x08; /* code segment */
3617 vmcs_write32(sf
->ar_bytes
, ar
);
3620 static int alloc_apic_access_page(struct kvm
*kvm
)
3622 struct kvm_userspace_memory_region kvm_userspace_mem
;
3625 mutex_lock(&kvm
->slots_lock
);
3626 if (kvm
->arch
.apic_access_page
)
3628 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3629 kvm_userspace_mem
.flags
= 0;
3630 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3631 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3632 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3636 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3638 mutex_unlock(&kvm
->slots_lock
);
3642 static int alloc_identity_pagetable(struct kvm
*kvm
)
3644 struct kvm_userspace_memory_region kvm_userspace_mem
;
3647 mutex_lock(&kvm
->slots_lock
);
3648 if (kvm
->arch
.ept_identity_pagetable
)
3650 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3651 kvm_userspace_mem
.flags
= 0;
3652 kvm_userspace_mem
.guest_phys_addr
=
3653 kvm
->arch
.ept_identity_map_addr
;
3654 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3655 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3659 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3660 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3662 mutex_unlock(&kvm
->slots_lock
);
3666 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3673 spin_lock(&vmx_vpid_lock
);
3674 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3675 if (vpid
< VMX_NR_VPIDS
) {
3677 __set_bit(vpid
, vmx_vpid_bitmap
);
3679 spin_unlock(&vmx_vpid_lock
);
3682 static void free_vpid(struct vcpu_vmx
*vmx
)
3686 spin_lock(&vmx_vpid_lock
);
3688 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3689 spin_unlock(&vmx_vpid_lock
);
3692 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3694 int f
= sizeof(unsigned long);
3696 if (!cpu_has_vmx_msr_bitmap())
3700 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3701 * have the write-low and read-high bitmap offsets the wrong way round.
3702 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3704 if (msr
<= 0x1fff) {
3705 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3706 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3707 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3709 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3710 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3714 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3717 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3718 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3722 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3723 * will not change in the lifetime of the guest.
3724 * Note that host-state that does change is set elsewhere. E.g., host-state
3725 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3727 static void vmx_set_constant_host_state(void)
3733 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3734 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3735 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3737 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3738 #ifdef CONFIG_X86_64
3740 * Load null selectors, so we can avoid reloading them in
3741 * __vmx_load_host_state(), in case userspace uses the null selectors
3742 * too (the expected case).
3744 vmcs_write16(HOST_DS_SELECTOR
, 0);
3745 vmcs_write16(HOST_ES_SELECTOR
, 0);
3747 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3748 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3750 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3751 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3753 native_store_idt(&dt
);
3754 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3756 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl
));
3757 vmcs_writel(HOST_RIP
, tmpl
); /* 22.2.5 */
3759 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3760 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3761 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3762 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3764 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3765 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3766 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3770 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3772 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3774 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3775 if (is_guest_mode(&vmx
->vcpu
))
3776 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3777 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3778 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3781 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3783 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3784 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3785 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3786 #ifdef CONFIG_X86_64
3787 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3788 CPU_BASED_CR8_LOAD_EXITING
;
3792 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3793 CPU_BASED_CR3_LOAD_EXITING
|
3794 CPU_BASED_INVLPG_EXITING
;
3795 return exec_control
;
3798 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3800 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3801 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3802 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3804 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3806 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3807 enable_unrestricted_guest
= 0;
3808 /* Enable INVPCID for non-ept guests may cause performance regression. */
3809 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
3811 if (!enable_unrestricted_guest
)
3812 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3814 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3815 return exec_control
;
3818 static void ept_set_mmio_spte_mask(void)
3821 * EPT Misconfigurations can be generated if the value of bits 2:0
3822 * of an EPT paging-structure entry is 110b (write/execute).
3823 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3826 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
3830 * Sets up the vmcs for emulated real mode.
3832 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3834 #ifdef CONFIG_X86_64
3840 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3841 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3843 if (cpu_has_vmx_msr_bitmap())
3844 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3846 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3849 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3850 vmcs_config
.pin_based_exec_ctrl
);
3852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
3854 if (cpu_has_secondary_exec_ctrls()) {
3855 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
3856 vmx_secondary_exec_control(vmx
));
3860 vmcs_write32(PLE_GAP
, ple_gap
);
3861 vmcs_write32(PLE_WINDOW
, ple_window
);
3864 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
3865 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
3866 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3868 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3869 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3870 vmx_set_constant_host_state();
3871 #ifdef CONFIG_X86_64
3872 rdmsrl(MSR_FS_BASE
, a
);
3873 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3874 rdmsrl(MSR_GS_BASE
, a
);
3875 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3877 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3878 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3881 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3882 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3883 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3884 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3885 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3887 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3888 u32 msr_low
, msr_high
;
3890 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3891 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3892 /* Write the default value follow host pat */
3893 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3894 /* Keep arch.pat sync with GUEST_IA32_PAT */
3895 vmx
->vcpu
.arch
.pat
= host_pat
;
3898 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3899 u32 index
= vmx_msr_index
[i
];
3900 u32 data_low
, data_high
;
3903 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3905 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3907 vmx
->guest_msrs
[j
].index
= i
;
3908 vmx
->guest_msrs
[j
].data
= 0;
3909 vmx
->guest_msrs
[j
].mask
= -1ull;
3913 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3915 /* 22.2.1, 20.8.1 */
3916 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3918 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3919 set_cr4_guest_host_mask(vmx
);
3921 kvm_write_tsc(&vmx
->vcpu
, 0);
3926 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3928 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3932 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3934 vmx
->rmode
.vm86_active
= 0;
3936 vmx
->soft_vnmi_blocked
= 0;
3938 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3939 kvm_set_cr8(&vmx
->vcpu
, 0);
3940 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3941 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3942 msr
|= MSR_IA32_APICBASE_BSP
;
3943 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3945 ret
= fx_init(&vmx
->vcpu
);
3949 vmx_segment_cache_clear(vmx
);
3951 seg_setup(VCPU_SREG_CS
);
3953 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3954 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3956 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3957 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3958 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3960 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3961 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3964 seg_setup(VCPU_SREG_DS
);
3965 seg_setup(VCPU_SREG_ES
);
3966 seg_setup(VCPU_SREG_FS
);
3967 seg_setup(VCPU_SREG_GS
);
3968 seg_setup(VCPU_SREG_SS
);
3970 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3971 vmcs_writel(GUEST_TR_BASE
, 0);
3972 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3973 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3975 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3976 vmcs_writel(GUEST_LDTR_BASE
, 0);
3977 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3978 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3980 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3981 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3982 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3984 vmcs_writel(GUEST_RFLAGS
, 0x02);
3985 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3986 kvm_rip_write(vcpu
, 0xfff0);
3988 kvm_rip_write(vcpu
, 0);
3989 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3991 vmcs_writel(GUEST_DR7
, 0x400);
3993 vmcs_writel(GUEST_GDTR_BASE
, 0);
3994 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3996 vmcs_writel(GUEST_IDTR_BASE
, 0);
3997 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3999 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4000 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4001 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4003 /* Special registers */
4004 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4008 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4010 if (cpu_has_vmx_tpr_shadow()) {
4011 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4012 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4013 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4014 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4015 vmcs_write32(TPR_THRESHOLD
, 0);
4018 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4019 vmcs_write64(APIC_ACCESS_ADDR
,
4020 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4023 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4025 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4026 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
4027 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4028 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
4029 vmx_set_cr4(&vmx
->vcpu
, 0);
4030 vmx_set_efer(&vmx
->vcpu
, 0);
4031 vmx_fpu_activate(&vmx
->vcpu
);
4032 update_exception_bitmap(&vmx
->vcpu
);
4034 vpid_sync_context(vmx
);
4038 /* HACK: Don't enable emulation on guest boot/reset */
4039 vmx
->emulation_required
= 0;
4046 * In nested virtualization, check if L1 asked to exit on external interrupts.
4047 * For most existing hypervisors, this will always return true.
4049 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4051 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4052 PIN_BASED_EXT_INTR_MASK
;
4055 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4057 u32 cpu_based_vm_exec_control
;
4058 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4060 * We get here if vmx_interrupt_allowed() said we can't
4061 * inject to L1 now because L2 must run. Ask L2 to exit
4062 * right after entry, so we can inject to L1 more promptly.
4064 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT
, vcpu
);
4068 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4069 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4070 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4073 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4075 u32 cpu_based_vm_exec_control
;
4077 if (!cpu_has_virtual_nmis()) {
4078 enable_irq_window(vcpu
);
4082 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4083 enable_irq_window(vcpu
);
4086 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4087 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4088 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4091 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4095 int irq
= vcpu
->arch
.interrupt
.nr
;
4097 trace_kvm_inj_virq(irq
);
4099 ++vcpu
->stat
.irq_injections
;
4100 if (vmx
->rmode
.vm86_active
) {
4102 if (vcpu
->arch
.interrupt
.soft
)
4103 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4104 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4105 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4108 intr
= irq
| INTR_INFO_VALID_MASK
;
4109 if (vcpu
->arch
.interrupt
.soft
) {
4110 intr
|= INTR_TYPE_SOFT_INTR
;
4111 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4112 vmx
->vcpu
.arch
.event_exit_inst_len
);
4114 intr
|= INTR_TYPE_EXT_INTR
;
4115 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4118 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4122 if (is_guest_mode(vcpu
))
4125 if (!cpu_has_virtual_nmis()) {
4127 * Tracking the NMI-blocked state in software is built upon
4128 * finding the next open IRQ window. This, in turn, depends on
4129 * well-behaving guests: They have to keep IRQs disabled at
4130 * least as long as the NMI handler runs. Otherwise we may
4131 * cause NMI nesting, maybe breaking the guest. But as this is
4132 * highly unlikely, we can live with the residual risk.
4134 vmx
->soft_vnmi_blocked
= 1;
4135 vmx
->vnmi_blocked_time
= 0;
4138 ++vcpu
->stat
.nmi_injections
;
4139 vmx
->nmi_known_unmasked
= false;
4140 if (vmx
->rmode
.vm86_active
) {
4141 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4142 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4145 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4146 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4149 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4151 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4154 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4155 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4156 | GUEST_INTR_STATE_NMI
));
4159 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4161 if (!cpu_has_virtual_nmis())
4162 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4163 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4165 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4168 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4170 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4172 if (!cpu_has_virtual_nmis()) {
4173 if (vmx
->soft_vnmi_blocked
!= masked
) {
4174 vmx
->soft_vnmi_blocked
= masked
;
4175 vmx
->vnmi_blocked_time
= 0;
4178 vmx
->nmi_known_unmasked
= !masked
;
4180 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4181 GUEST_INTR_STATE_NMI
);
4183 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4184 GUEST_INTR_STATE_NMI
);
4188 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4190 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4191 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4192 if (to_vmx(vcpu
)->nested
.nested_run_pending
||
4193 (vmcs12
->idt_vectoring_info_field
&
4194 VECTORING_INFO_VALID_MASK
))
4196 nested_vmx_vmexit(vcpu
);
4197 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
4198 vmcs12
->vm_exit_intr_info
= 0;
4199 /* fall through to normal code, but now in L1, not L2 */
4202 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4203 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4204 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4207 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4210 struct kvm_userspace_memory_region tss_mem
= {
4211 .slot
= TSS_PRIVATE_MEMSLOT
,
4212 .guest_phys_addr
= addr
,
4213 .memory_size
= PAGE_SIZE
* 3,
4217 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
4220 kvm
->arch
.tss_addr
= addr
;
4221 if (!init_rmode_tss(kvm
))
4227 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4228 int vec
, u32 err_code
)
4231 * Instruction with address size override prefix opcode 0x67
4232 * Cause the #SS fault with 0 error code in VM86 mode.
4234 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
4235 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
4238 * Forward all other exceptions that are valid in real mode.
4239 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4240 * the required debugging infrastructure rework.
4244 if (vcpu
->guest_debug
&
4245 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4247 kvm_queue_exception(vcpu
, vec
);
4251 * Update instruction length as we may reinject the exception
4252 * from user space while in guest debugging mode.
4254 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4255 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4256 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4267 kvm_queue_exception(vcpu
, vec
);
4274 * Trigger machine check on the host. We assume all the MSRs are already set up
4275 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4276 * We pass a fake environment to the machine check handler because we want
4277 * the guest to be always treated like user space, no matter what context
4278 * it used internally.
4280 static void kvm_machine_check(void)
4282 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4283 struct pt_regs regs
= {
4284 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4285 .flags
= X86_EFLAGS_IF
,
4288 do_machine_check(®s
, 0);
4292 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4294 /* already handled by vcpu_run */
4298 static int handle_exception(struct kvm_vcpu
*vcpu
)
4300 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4301 struct kvm_run
*kvm_run
= vcpu
->run
;
4302 u32 intr_info
, ex_no
, error_code
;
4303 unsigned long cr2
, rip
, dr6
;
4305 enum emulation_result er
;
4307 vect_info
= vmx
->idt_vectoring_info
;
4308 intr_info
= vmx
->exit_intr_info
;
4310 if (is_machine_check(intr_info
))
4311 return handle_machine_check(vcpu
);
4313 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4314 !is_page_fault(intr_info
)) {
4315 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4316 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4317 vcpu
->run
->internal
.ndata
= 2;
4318 vcpu
->run
->internal
.data
[0] = vect_info
;
4319 vcpu
->run
->internal
.data
[1] = intr_info
;
4323 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4324 return 1; /* already handled by vmx_vcpu_run() */
4326 if (is_no_device(intr_info
)) {
4327 vmx_fpu_activate(vcpu
);
4331 if (is_invalid_opcode(intr_info
)) {
4332 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4333 if (er
!= EMULATE_DONE
)
4334 kvm_queue_exception(vcpu
, UD_VECTOR
);
4339 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4340 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4341 if (is_page_fault(intr_info
)) {
4342 /* EPT won't cause page fault directly */
4344 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4345 trace_kvm_page_fault(cr2
, error_code
);
4347 if (kvm_event_needs_reinjection(vcpu
))
4348 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4349 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4352 if (vmx
->rmode
.vm86_active
&&
4353 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
4355 if (vcpu
->arch
.halt_request
) {
4356 vcpu
->arch
.halt_request
= 0;
4357 return kvm_emulate_halt(vcpu
);
4362 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4365 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4366 if (!(vcpu
->guest_debug
&
4367 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4368 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4369 kvm_queue_exception(vcpu
, DB_VECTOR
);
4372 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4373 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4377 * Update instruction length as we may reinject #BP from
4378 * user space while in guest debugging mode. Reading it for
4379 * #DB as well causes no harm, it is not used in that case.
4381 vmx
->vcpu
.arch
.event_exit_inst_len
=
4382 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4383 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4384 rip
= kvm_rip_read(vcpu
);
4385 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4386 kvm_run
->debug
.arch
.exception
= ex_no
;
4389 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4390 kvm_run
->ex
.exception
= ex_no
;
4391 kvm_run
->ex
.error_code
= error_code
;
4397 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4399 ++vcpu
->stat
.irq_exits
;
4403 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4405 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4409 static int handle_io(struct kvm_vcpu
*vcpu
)
4411 unsigned long exit_qualification
;
4412 int size
, in
, string
;
4415 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4416 string
= (exit_qualification
& 16) != 0;
4417 in
= (exit_qualification
& 8) != 0;
4419 ++vcpu
->stat
.io_exits
;
4422 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4424 port
= exit_qualification
>> 16;
4425 size
= (exit_qualification
& 7) + 1;
4426 skip_emulated_instruction(vcpu
);
4428 return kvm_fast_pio_out(vcpu
, size
, port
);
4432 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4435 * Patch in the VMCALL instruction:
4437 hypercall
[0] = 0x0f;
4438 hypercall
[1] = 0x01;
4439 hypercall
[2] = 0xc1;
4442 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4443 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4445 if (to_vmx(vcpu
)->nested
.vmxon
&&
4446 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4449 if (is_guest_mode(vcpu
)) {
4451 * We get here when L2 changed cr0 in a way that did not change
4452 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4453 * but did change L0 shadowed bits. This can currently happen
4454 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4455 * loading) while pretending to allow the guest to change it.
4457 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4458 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4460 vmcs_writel(CR0_READ_SHADOW
, val
);
4463 return kvm_set_cr0(vcpu
, val
);
4466 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4468 if (is_guest_mode(vcpu
)) {
4469 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4470 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4472 vmcs_writel(CR4_READ_SHADOW
, val
);
4475 return kvm_set_cr4(vcpu
, val
);
4478 /* called to set cr0 as approriate for clts instruction exit. */
4479 static void handle_clts(struct kvm_vcpu
*vcpu
)
4481 if (is_guest_mode(vcpu
)) {
4483 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4484 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4485 * just pretend it's off (also in arch.cr0 for fpu_activate).
4487 vmcs_writel(CR0_READ_SHADOW
,
4488 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4489 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4491 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4494 static int handle_cr(struct kvm_vcpu
*vcpu
)
4496 unsigned long exit_qualification
, val
;
4501 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4502 cr
= exit_qualification
& 15;
4503 reg
= (exit_qualification
>> 8) & 15;
4504 switch ((exit_qualification
>> 4) & 3) {
4505 case 0: /* mov to cr */
4506 val
= kvm_register_read(vcpu
, reg
);
4507 trace_kvm_cr_write(cr
, val
);
4510 err
= handle_set_cr0(vcpu
, val
);
4511 kvm_complete_insn_gp(vcpu
, err
);
4514 err
= kvm_set_cr3(vcpu
, val
);
4515 kvm_complete_insn_gp(vcpu
, err
);
4518 err
= handle_set_cr4(vcpu
, val
);
4519 kvm_complete_insn_gp(vcpu
, err
);
4522 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4523 u8 cr8
= kvm_register_read(vcpu
, reg
);
4524 err
= kvm_set_cr8(vcpu
, cr8
);
4525 kvm_complete_insn_gp(vcpu
, err
);
4526 if (irqchip_in_kernel(vcpu
->kvm
))
4528 if (cr8_prev
<= cr8
)
4530 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4537 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4538 skip_emulated_instruction(vcpu
);
4539 vmx_fpu_activate(vcpu
);
4541 case 1: /*mov from cr*/
4544 val
= kvm_read_cr3(vcpu
);
4545 kvm_register_write(vcpu
, reg
, val
);
4546 trace_kvm_cr_read(cr
, val
);
4547 skip_emulated_instruction(vcpu
);
4550 val
= kvm_get_cr8(vcpu
);
4551 kvm_register_write(vcpu
, reg
, val
);
4552 trace_kvm_cr_read(cr
, val
);
4553 skip_emulated_instruction(vcpu
);
4558 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4559 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4560 kvm_lmsw(vcpu
, val
);
4562 skip_emulated_instruction(vcpu
);
4567 vcpu
->run
->exit_reason
= 0;
4568 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4569 (int)(exit_qualification
>> 4) & 3, cr
);
4573 static int handle_dr(struct kvm_vcpu
*vcpu
)
4575 unsigned long exit_qualification
;
4578 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4579 if (!kvm_require_cpl(vcpu
, 0))
4581 dr
= vmcs_readl(GUEST_DR7
);
4584 * As the vm-exit takes precedence over the debug trap, we
4585 * need to emulate the latter, either for the host or the
4586 * guest debugging itself.
4588 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4589 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4590 vcpu
->run
->debug
.arch
.dr7
= dr
;
4591 vcpu
->run
->debug
.arch
.pc
=
4592 vmcs_readl(GUEST_CS_BASE
) +
4593 vmcs_readl(GUEST_RIP
);
4594 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4595 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4598 vcpu
->arch
.dr7
&= ~DR7_GD
;
4599 vcpu
->arch
.dr6
|= DR6_BD
;
4600 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4601 kvm_queue_exception(vcpu
, DB_VECTOR
);
4606 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4607 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4608 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4609 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4611 if (!kvm_get_dr(vcpu
, dr
, &val
))
4612 kvm_register_write(vcpu
, reg
, val
);
4614 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4615 skip_emulated_instruction(vcpu
);
4619 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4621 vmcs_writel(GUEST_DR7
, val
);
4624 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4626 kvm_emulate_cpuid(vcpu
);
4630 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4632 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4635 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4636 trace_kvm_msr_read_ex(ecx
);
4637 kvm_inject_gp(vcpu
, 0);
4641 trace_kvm_msr_read(ecx
, data
);
4643 /* FIXME: handling of bits 32:63 of rax, rdx */
4644 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4645 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4646 skip_emulated_instruction(vcpu
);
4650 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4652 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4653 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4654 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4656 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
4657 trace_kvm_msr_write_ex(ecx
, data
);
4658 kvm_inject_gp(vcpu
, 0);
4662 trace_kvm_msr_write(ecx
, data
);
4663 skip_emulated_instruction(vcpu
);
4667 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4669 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4673 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4675 u32 cpu_based_vm_exec_control
;
4677 /* clear pending irq */
4678 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4679 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4680 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4682 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4684 ++vcpu
->stat
.irq_window_exits
;
4687 * If the user space waits to inject interrupts, exit as soon as
4690 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4691 vcpu
->run
->request_interrupt_window
&&
4692 !kvm_cpu_has_interrupt(vcpu
)) {
4693 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4699 static int handle_halt(struct kvm_vcpu
*vcpu
)
4701 skip_emulated_instruction(vcpu
);
4702 return kvm_emulate_halt(vcpu
);
4705 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4707 skip_emulated_instruction(vcpu
);
4708 kvm_emulate_hypercall(vcpu
);
4712 static int handle_invd(struct kvm_vcpu
*vcpu
)
4714 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4717 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4719 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4721 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4722 skip_emulated_instruction(vcpu
);
4726 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
4730 err
= kvm_rdpmc(vcpu
);
4731 kvm_complete_insn_gp(vcpu
, err
);
4736 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4738 skip_emulated_instruction(vcpu
);
4739 kvm_emulate_wbinvd(vcpu
);
4743 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4745 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4746 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4748 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4749 skip_emulated_instruction(vcpu
);
4753 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4755 if (likely(fasteoi
)) {
4756 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4757 int access_type
, offset
;
4759 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4760 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4762 * Sane guest uses MOV to write EOI, with written value
4763 * not cared. So make a short-circuit here by avoiding
4764 * heavy instruction emulation.
4766 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4767 (offset
== APIC_EOI
)) {
4768 kvm_lapic_set_eoi(vcpu
);
4769 skip_emulated_instruction(vcpu
);
4773 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4776 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4778 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4779 unsigned long exit_qualification
;
4780 bool has_error_code
= false;
4783 int reason
, type
, idt_v
, idt_index
;
4785 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4786 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
4787 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4789 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4791 reason
= (u32
)exit_qualification
>> 30;
4792 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4794 case INTR_TYPE_NMI_INTR
:
4795 vcpu
->arch
.nmi_injected
= false;
4796 vmx_set_nmi_mask(vcpu
, true);
4798 case INTR_TYPE_EXT_INTR
:
4799 case INTR_TYPE_SOFT_INTR
:
4800 kvm_clear_interrupt_queue(vcpu
);
4802 case INTR_TYPE_HARD_EXCEPTION
:
4803 if (vmx
->idt_vectoring_info
&
4804 VECTORING_INFO_DELIVER_CODE_MASK
) {
4805 has_error_code
= true;
4807 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4810 case INTR_TYPE_SOFT_EXCEPTION
:
4811 kvm_clear_exception_queue(vcpu
);
4817 tss_selector
= exit_qualification
;
4819 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4820 type
!= INTR_TYPE_EXT_INTR
&&
4821 type
!= INTR_TYPE_NMI_INTR
))
4822 skip_emulated_instruction(vcpu
);
4824 if (kvm_task_switch(vcpu
, tss_selector
,
4825 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
4826 has_error_code
, error_code
) == EMULATE_FAIL
) {
4827 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4828 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4829 vcpu
->run
->internal
.ndata
= 0;
4833 /* clear all local breakpoint enable flags */
4834 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4837 * TODO: What about debug traps on tss switch?
4838 * Are we supposed to inject them and update dr6?
4844 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4846 unsigned long exit_qualification
;
4851 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4853 if (exit_qualification
& (1 << 6)) {
4854 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4858 gla_validity
= (exit_qualification
>> 7) & 0x3;
4859 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4860 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4861 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4862 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4863 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4864 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4865 (long unsigned int)exit_qualification
);
4866 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4867 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4871 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4872 trace_kvm_page_fault(gpa
, exit_qualification
);
4874 /* It is a write fault? */
4875 error_code
= exit_qualification
& (1U << 1);
4876 /* ept page table is present? */
4877 error_code
|= (exit_qualification
>> 3) & 0x1;
4879 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
4882 static u64
ept_rsvd_mask(u64 spte
, int level
)
4887 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4888 mask
|= (1ULL << i
);
4891 /* bits 7:3 reserved */
4893 else if (level
== 2) {
4894 if (spte
& (1ULL << 7))
4895 /* 2MB ref, bits 20:12 reserved */
4898 /* bits 6:3 reserved */
4905 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4908 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4910 /* 010b (write-only) */
4911 WARN_ON((spte
& 0x7) == 0x2);
4913 /* 110b (write/execute) */
4914 WARN_ON((spte
& 0x7) == 0x6);
4916 /* 100b (execute-only) and value not supported by logical processor */
4917 if (!cpu_has_vmx_ept_execute_only())
4918 WARN_ON((spte
& 0x7) == 0x4);
4922 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4924 if (rsvd_bits
!= 0) {
4925 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4926 __func__
, rsvd_bits
);
4930 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4931 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4933 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4934 ept_mem_type
== 7) {
4935 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4936 __func__
, ept_mem_type
);
4943 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4946 int nr_sptes
, i
, ret
;
4949 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4951 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
4952 if (likely(ret
== 1))
4953 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
4958 /* It is the real ept misconfig */
4959 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4960 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4962 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4964 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4965 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4967 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4968 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4973 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4975 u32 cpu_based_vm_exec_control
;
4977 /* clear pending NMI */
4978 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4979 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4980 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4981 ++vcpu
->stat
.nmi_window_exits
;
4982 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4987 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4989 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4990 enum emulation_result err
= EMULATE_DONE
;
4993 bool intr_window_requested
;
4994 unsigned count
= 130;
4996 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4997 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4999 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5000 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5001 return handle_interrupt_window(&vmx
->vcpu
);
5003 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5006 err
= emulate_instruction(vcpu
, 0);
5008 if (err
== EMULATE_DO_MMIO
) {
5013 if (err
!= EMULATE_DONE
) {
5014 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5015 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5016 vcpu
->run
->internal
.ndata
= 0;
5020 if (signal_pending(current
))
5026 vmx
->emulation_required
= !guest_state_valid(vcpu
);
5032 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5033 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5035 static int handle_pause(struct kvm_vcpu
*vcpu
)
5037 skip_emulated_instruction(vcpu
);
5038 kvm_vcpu_on_spin(vcpu
);
5043 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5045 kvm_queue_exception(vcpu
, UD_VECTOR
);
5050 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5051 * We could reuse a single VMCS for all the L2 guests, but we also want the
5052 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5053 * allows keeping them loaded on the processor, and in the future will allow
5054 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5055 * every entry if they never change.
5056 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5057 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5059 * The following functions allocate and free a vmcs02 in this pool.
5062 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5063 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5065 struct vmcs02_list
*item
;
5066 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5067 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5068 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5069 return &item
->vmcs02
;
5072 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5073 /* Recycle the least recently used VMCS. */
5074 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5075 struct vmcs02_list
, list
);
5076 item
->vmptr
= vmx
->nested
.current_vmptr
;
5077 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5078 return &item
->vmcs02
;
5081 /* Create a new VMCS */
5082 item
= (struct vmcs02_list
*)
5083 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5086 item
->vmcs02
.vmcs
= alloc_vmcs();
5087 if (!item
->vmcs02
.vmcs
) {
5091 loaded_vmcs_init(&item
->vmcs02
);
5092 item
->vmptr
= vmx
->nested
.current_vmptr
;
5093 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5094 vmx
->nested
.vmcs02_num
++;
5095 return &item
->vmcs02
;
5098 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5099 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5101 struct vmcs02_list
*item
;
5102 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5103 if (item
->vmptr
== vmptr
) {
5104 free_loaded_vmcs(&item
->vmcs02
);
5105 list_del(&item
->list
);
5107 vmx
->nested
.vmcs02_num
--;
5113 * Free all VMCSs saved for this vcpu, except the one pointed by
5114 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5115 * currently used, if running L2), and vmcs01 when running L2.
5117 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5119 struct vmcs02_list
*item
, *n
;
5120 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5121 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5122 free_loaded_vmcs(&item
->vmcs02
);
5123 list_del(&item
->list
);
5126 vmx
->nested
.vmcs02_num
= 0;
5128 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5129 free_loaded_vmcs(&vmx
->vmcs01
);
5133 * Emulate the VMXON instruction.
5134 * Currently, we just remember that VMX is active, and do not save or even
5135 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5136 * do not currently need to store anything in that guest-allocated memory
5137 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5138 * argument is different from the VMXON pointer (which the spec says they do).
5140 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5142 struct kvm_segment cs
;
5143 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5145 /* The Intel VMX Instruction Reference lists a bunch of bits that
5146 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5147 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5148 * Otherwise, we should fail with #UD. We test these now:
5150 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5151 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5152 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5153 kvm_queue_exception(vcpu
, UD_VECTOR
);
5157 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5158 if (is_long_mode(vcpu
) && !cs
.l
) {
5159 kvm_queue_exception(vcpu
, UD_VECTOR
);
5163 if (vmx_get_cpl(vcpu
)) {
5164 kvm_inject_gp(vcpu
, 0);
5168 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5169 vmx
->nested
.vmcs02_num
= 0;
5171 vmx
->nested
.vmxon
= true;
5173 skip_emulated_instruction(vcpu
);
5178 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5179 * for running VMX instructions (except VMXON, whose prerequisites are
5180 * slightly different). It also specifies what exception to inject otherwise.
5182 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5184 struct kvm_segment cs
;
5185 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5187 if (!vmx
->nested
.vmxon
) {
5188 kvm_queue_exception(vcpu
, UD_VECTOR
);
5192 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5193 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5194 (is_long_mode(vcpu
) && !cs
.l
)) {
5195 kvm_queue_exception(vcpu
, UD_VECTOR
);
5199 if (vmx_get_cpl(vcpu
)) {
5200 kvm_inject_gp(vcpu
, 0);
5208 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5209 * just stops using VMX.
5211 static void free_nested(struct vcpu_vmx
*vmx
)
5213 if (!vmx
->nested
.vmxon
)
5215 vmx
->nested
.vmxon
= false;
5216 if (vmx
->nested
.current_vmptr
!= -1ull) {
5217 kunmap(vmx
->nested
.current_vmcs12_page
);
5218 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5219 vmx
->nested
.current_vmptr
= -1ull;
5220 vmx
->nested
.current_vmcs12
= NULL
;
5222 /* Unpin physical memory we referred to in current vmcs02 */
5223 if (vmx
->nested
.apic_access_page
) {
5224 nested_release_page(vmx
->nested
.apic_access_page
);
5225 vmx
->nested
.apic_access_page
= 0;
5228 nested_free_all_saved_vmcss(vmx
);
5231 /* Emulate the VMXOFF instruction */
5232 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5234 if (!nested_vmx_check_permission(vcpu
))
5236 free_nested(to_vmx(vcpu
));
5237 skip_emulated_instruction(vcpu
);
5242 * Decode the memory-address operand of a vmx instruction, as recorded on an
5243 * exit caused by such an instruction (run by a guest hypervisor).
5244 * On success, returns 0. When the operand is invalid, returns 1 and throws
5247 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5248 unsigned long exit_qualification
,
5249 u32 vmx_instruction_info
, gva_t
*ret
)
5252 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5253 * Execution", on an exit, vmx_instruction_info holds most of the
5254 * addressing components of the operand. Only the displacement part
5255 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5256 * For how an actual address is calculated from all these components,
5257 * refer to Vol. 1, "Operand Addressing".
5259 int scaling
= vmx_instruction_info
& 3;
5260 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5261 bool is_reg
= vmx_instruction_info
& (1u << 10);
5262 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5263 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5264 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5265 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5266 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5269 kvm_queue_exception(vcpu
, UD_VECTOR
);
5273 /* Addr = segment_base + offset */
5274 /* offset = base + [index * scale] + displacement */
5275 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5277 *ret
+= kvm_register_read(vcpu
, base_reg
);
5279 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5280 *ret
+= exit_qualification
; /* holds the displacement */
5282 if (addr_size
== 1) /* 32 bit */
5286 * TODO: throw #GP (and return 1) in various cases that the VM*
5287 * instructions require it - e.g., offset beyond segment limit,
5288 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5289 * address, and so on. Currently these are not checked.
5295 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5296 * set the success or error code of an emulated VMX instruction, as specified
5297 * by Vol 2B, VMX Instruction Reference, "Conventions".
5299 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5301 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5302 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5303 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5306 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5308 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5309 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5310 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5314 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5315 u32 vm_instruction_error
)
5317 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5319 * failValid writes the error number to the current VMCS, which
5320 * can't be done there isn't a current VMCS.
5322 nested_vmx_failInvalid(vcpu
);
5325 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5326 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5327 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5329 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5332 /* Emulate the VMCLEAR instruction */
5333 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5335 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5338 struct vmcs12
*vmcs12
;
5340 struct x86_exception e
;
5342 if (!nested_vmx_check_permission(vcpu
))
5345 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5346 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5349 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5350 sizeof(vmptr
), &e
)) {
5351 kvm_inject_page_fault(vcpu
, &e
);
5355 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5356 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5357 skip_emulated_instruction(vcpu
);
5361 if (vmptr
== vmx
->nested
.current_vmptr
) {
5362 kunmap(vmx
->nested
.current_vmcs12_page
);
5363 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5364 vmx
->nested
.current_vmptr
= -1ull;
5365 vmx
->nested
.current_vmcs12
= NULL
;
5368 page
= nested_get_page(vcpu
, vmptr
);
5371 * For accurate processor emulation, VMCLEAR beyond available
5372 * physical memory should do nothing at all. However, it is
5373 * possible that a nested vmx bug, not a guest hypervisor bug,
5374 * resulted in this case, so let's shut down before doing any
5377 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5380 vmcs12
= kmap(page
);
5381 vmcs12
->launch_state
= 0;
5383 nested_release_page(page
);
5385 nested_free_vmcs02(vmx
, vmptr
);
5387 skip_emulated_instruction(vcpu
);
5388 nested_vmx_succeed(vcpu
);
5392 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5394 /* Emulate the VMLAUNCH instruction */
5395 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5397 return nested_vmx_run(vcpu
, true);
5400 /* Emulate the VMRESUME instruction */
5401 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5404 return nested_vmx_run(vcpu
, false);
5407 enum vmcs_field_type
{
5408 VMCS_FIELD_TYPE_U16
= 0,
5409 VMCS_FIELD_TYPE_U64
= 1,
5410 VMCS_FIELD_TYPE_U32
= 2,
5411 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5414 static inline int vmcs_field_type(unsigned long field
)
5416 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5417 return VMCS_FIELD_TYPE_U32
;
5418 return (field
>> 13) & 0x3 ;
5421 static inline int vmcs_field_readonly(unsigned long field
)
5423 return (((field
>> 10) & 0x3) == 1);
5427 * Read a vmcs12 field. Since these can have varying lengths and we return
5428 * one type, we chose the biggest type (u64) and zero-extend the return value
5429 * to that size. Note that the caller, handle_vmread, might need to use only
5430 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5431 * 64-bit fields are to be returned).
5433 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5434 unsigned long field
, u64
*ret
)
5436 short offset
= vmcs_field_to_offset(field
);
5442 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5444 switch (vmcs_field_type(field
)) {
5445 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5446 *ret
= *((natural_width
*)p
);
5448 case VMCS_FIELD_TYPE_U16
:
5451 case VMCS_FIELD_TYPE_U32
:
5454 case VMCS_FIELD_TYPE_U64
:
5458 return 0; /* can never happen. */
5463 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5464 * used before) all generate the same failure when it is missing.
5466 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5469 if (vmx
->nested
.current_vmptr
== -1ull) {
5470 nested_vmx_failInvalid(vcpu
);
5471 skip_emulated_instruction(vcpu
);
5477 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5479 unsigned long field
;
5481 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5482 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5485 if (!nested_vmx_check_permission(vcpu
) ||
5486 !nested_vmx_check_vmcs12(vcpu
))
5489 /* Decode instruction info and find the field to read */
5490 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5491 /* Read the field, zero-extended to a u64 field_value */
5492 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5493 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5494 skip_emulated_instruction(vcpu
);
5498 * Now copy part of this value to register or memory, as requested.
5499 * Note that the number of bits actually copied is 32 or 64 depending
5500 * on the guest's mode (32 or 64 bit), not on the given field's length.
5502 if (vmx_instruction_info
& (1u << 10)) {
5503 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5506 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5507 vmx_instruction_info
, &gva
))
5509 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5510 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5511 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5514 nested_vmx_succeed(vcpu
);
5515 skip_emulated_instruction(vcpu
);
5520 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5522 unsigned long field
;
5524 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5525 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5528 /* The value to write might be 32 or 64 bits, depending on L1's long
5529 * mode, and eventually we need to write that into a field of several
5530 * possible lengths. The code below first zero-extends the value to 64
5531 * bit (field_value), and then copies only the approriate number of
5532 * bits into the vmcs12 field.
5534 u64 field_value
= 0;
5535 struct x86_exception e
;
5537 if (!nested_vmx_check_permission(vcpu
) ||
5538 !nested_vmx_check_vmcs12(vcpu
))
5541 if (vmx_instruction_info
& (1u << 10))
5542 field_value
= kvm_register_read(vcpu
,
5543 (((vmx_instruction_info
) >> 3) & 0xf));
5545 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5546 vmx_instruction_info
, &gva
))
5548 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5549 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5550 kvm_inject_page_fault(vcpu
, &e
);
5556 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5557 if (vmcs_field_readonly(field
)) {
5558 nested_vmx_failValid(vcpu
,
5559 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5560 skip_emulated_instruction(vcpu
);
5564 offset
= vmcs_field_to_offset(field
);
5566 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5567 skip_emulated_instruction(vcpu
);
5570 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5572 switch (vmcs_field_type(field
)) {
5573 case VMCS_FIELD_TYPE_U16
:
5574 *(u16
*)p
= field_value
;
5576 case VMCS_FIELD_TYPE_U32
:
5577 *(u32
*)p
= field_value
;
5579 case VMCS_FIELD_TYPE_U64
:
5580 *(u64
*)p
= field_value
;
5582 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5583 *(natural_width
*)p
= field_value
;
5586 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5587 skip_emulated_instruction(vcpu
);
5591 nested_vmx_succeed(vcpu
);
5592 skip_emulated_instruction(vcpu
);
5596 /* Emulate the VMPTRLD instruction */
5597 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5602 struct x86_exception e
;
5604 if (!nested_vmx_check_permission(vcpu
))
5607 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5608 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5611 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5612 sizeof(vmptr
), &e
)) {
5613 kvm_inject_page_fault(vcpu
, &e
);
5617 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5618 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5619 skip_emulated_instruction(vcpu
);
5623 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5624 struct vmcs12
*new_vmcs12
;
5626 page
= nested_get_page(vcpu
, vmptr
);
5628 nested_vmx_failInvalid(vcpu
);
5629 skip_emulated_instruction(vcpu
);
5632 new_vmcs12
= kmap(page
);
5633 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5635 nested_release_page_clean(page
);
5636 nested_vmx_failValid(vcpu
,
5637 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5638 skip_emulated_instruction(vcpu
);
5641 if (vmx
->nested
.current_vmptr
!= -1ull) {
5642 kunmap(vmx
->nested
.current_vmcs12_page
);
5643 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5646 vmx
->nested
.current_vmptr
= vmptr
;
5647 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5648 vmx
->nested
.current_vmcs12_page
= page
;
5651 nested_vmx_succeed(vcpu
);
5652 skip_emulated_instruction(vcpu
);
5656 /* Emulate the VMPTRST instruction */
5657 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5659 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5660 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5662 struct x86_exception e
;
5664 if (!nested_vmx_check_permission(vcpu
))
5667 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5668 vmx_instruction_info
, &vmcs_gva
))
5670 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5671 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5672 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5674 kvm_inject_page_fault(vcpu
, &e
);
5677 nested_vmx_succeed(vcpu
);
5678 skip_emulated_instruction(vcpu
);
5683 * The exit handlers return 1 if the exit was handled fully and guest execution
5684 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5685 * to be done to userspace and return 0.
5687 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5688 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5689 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5690 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5691 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5692 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5693 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5694 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5695 [EXIT_REASON_CPUID
] = handle_cpuid
,
5696 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5697 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5698 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5699 [EXIT_REASON_HLT
] = handle_halt
,
5700 [EXIT_REASON_INVD
] = handle_invd
,
5701 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5702 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
5703 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5704 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5705 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5706 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5707 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5708 [EXIT_REASON_VMREAD
] = handle_vmread
,
5709 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5710 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5711 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5712 [EXIT_REASON_VMON
] = handle_vmon
,
5713 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5714 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5715 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5716 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5717 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5718 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5719 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5720 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5721 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5722 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5723 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5726 static const int kvm_vmx_max_exit_handlers
=
5727 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5730 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5731 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5732 * disinterest in the current event (read or write a specific MSR) by using an
5733 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5735 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5736 struct vmcs12
*vmcs12
, u32 exit_reason
)
5738 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5741 if (!nested_cpu_has(get_vmcs12(vcpu
), CPU_BASED_USE_MSR_BITMAPS
))
5745 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5746 * for the four combinations of read/write and low/high MSR numbers.
5747 * First we need to figure out which of the four to use:
5749 bitmap
= vmcs12
->msr_bitmap
;
5750 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5752 if (msr_index
>= 0xc0000000) {
5753 msr_index
-= 0xc0000000;
5757 /* Then read the msr_index'th bit from this bitmap: */
5758 if (msr_index
< 1024*8) {
5760 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5761 return 1 & (b
>> (msr_index
& 7));
5763 return 1; /* let L1 handle the wrong parameter */
5767 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5768 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5769 * intercept (via guest_host_mask etc.) the current event.
5771 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5772 struct vmcs12
*vmcs12
)
5774 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5775 int cr
= exit_qualification
& 15;
5776 int reg
= (exit_qualification
>> 8) & 15;
5777 unsigned long val
= kvm_register_read(vcpu
, reg
);
5779 switch ((exit_qualification
>> 4) & 3) {
5780 case 0: /* mov to cr */
5783 if (vmcs12
->cr0_guest_host_mask
&
5784 (val
^ vmcs12
->cr0_read_shadow
))
5788 if ((vmcs12
->cr3_target_count
>= 1 &&
5789 vmcs12
->cr3_target_value0
== val
) ||
5790 (vmcs12
->cr3_target_count
>= 2 &&
5791 vmcs12
->cr3_target_value1
== val
) ||
5792 (vmcs12
->cr3_target_count
>= 3 &&
5793 vmcs12
->cr3_target_value2
== val
) ||
5794 (vmcs12
->cr3_target_count
>= 4 &&
5795 vmcs12
->cr3_target_value3
== val
))
5797 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5801 if (vmcs12
->cr4_guest_host_mask
&
5802 (vmcs12
->cr4_read_shadow
^ val
))
5806 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5812 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5813 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5816 case 1: /* mov from cr */
5819 if (vmcs12
->cpu_based_vm_exec_control
&
5820 CPU_BASED_CR3_STORE_EXITING
)
5824 if (vmcs12
->cpu_based_vm_exec_control
&
5825 CPU_BASED_CR8_STORE_EXITING
)
5832 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5833 * cr0. Other attempted changes are ignored, with no exit.
5835 if (vmcs12
->cr0_guest_host_mask
& 0xe &
5836 (val
^ vmcs12
->cr0_read_shadow
))
5838 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
5839 !(vmcs12
->cr0_read_shadow
& 0x1) &&
5848 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5849 * should handle it ourselves in L0 (and then continue L2). Only call this
5850 * when in is_guest_mode (L2).
5852 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
5854 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5855 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5856 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5857 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5859 if (vmx
->nested
.nested_run_pending
)
5862 if (unlikely(vmx
->fail
)) {
5863 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
5864 vmcs_read32(VM_INSTRUCTION_ERROR
));
5868 switch (exit_reason
) {
5869 case EXIT_REASON_EXCEPTION_NMI
:
5870 if (!is_exception(intr_info
))
5872 else if (is_page_fault(intr_info
))
5874 return vmcs12
->exception_bitmap
&
5875 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
5876 case EXIT_REASON_EXTERNAL_INTERRUPT
:
5878 case EXIT_REASON_TRIPLE_FAULT
:
5880 case EXIT_REASON_PENDING_INTERRUPT
:
5881 case EXIT_REASON_NMI_WINDOW
:
5883 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5884 * (aka Interrupt Window Exiting) only when L1 turned it on,
5885 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5886 * Same for NMI Window Exiting.
5889 case EXIT_REASON_TASK_SWITCH
:
5891 case EXIT_REASON_CPUID
:
5893 case EXIT_REASON_HLT
:
5894 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
5895 case EXIT_REASON_INVD
:
5897 case EXIT_REASON_INVLPG
:
5898 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
5899 case EXIT_REASON_RDPMC
:
5900 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
5901 case EXIT_REASON_RDTSC
:
5902 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
5903 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
5904 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
5905 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
5906 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
5907 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
5909 * VMX instructions trap unconditionally. This allows L1 to
5910 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5913 case EXIT_REASON_CR_ACCESS
:
5914 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
5915 case EXIT_REASON_DR_ACCESS
:
5916 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
5917 case EXIT_REASON_IO_INSTRUCTION
:
5918 /* TODO: support IO bitmaps */
5920 case EXIT_REASON_MSR_READ
:
5921 case EXIT_REASON_MSR_WRITE
:
5922 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
5923 case EXIT_REASON_INVALID_STATE
:
5925 case EXIT_REASON_MWAIT_INSTRUCTION
:
5926 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
5927 case EXIT_REASON_MONITOR_INSTRUCTION
:
5928 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
5929 case EXIT_REASON_PAUSE_INSTRUCTION
:
5930 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
5931 nested_cpu_has2(vmcs12
,
5932 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
5933 case EXIT_REASON_MCE_DURING_VMENTRY
:
5935 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
5937 case EXIT_REASON_APIC_ACCESS
:
5938 return nested_cpu_has2(vmcs12
,
5939 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
5940 case EXIT_REASON_EPT_VIOLATION
:
5941 case EXIT_REASON_EPT_MISCONFIG
:
5943 case EXIT_REASON_WBINVD
:
5944 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
5945 case EXIT_REASON_XSETBV
:
5952 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
5954 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
5955 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
5959 * The guest has exited. See if we can fix it or if we need userspace
5962 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
5964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5965 u32 exit_reason
= vmx
->exit_reason
;
5966 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5968 /* If guest state is invalid, start emulating */
5969 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5970 return handle_invalid_guest_state(vcpu
);
5973 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5974 * we did not inject a still-pending event to L1 now because of
5975 * nested_run_pending, we need to re-enable this bit.
5977 if (vmx
->nested
.nested_run_pending
)
5978 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5980 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
5981 exit_reason
== EXIT_REASON_VMRESUME
))
5982 vmx
->nested
.nested_run_pending
= 1;
5984 vmx
->nested
.nested_run_pending
= 0;
5986 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
5987 nested_vmx_vmexit(vcpu
);
5991 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
5992 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5993 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5998 if (unlikely(vmx
->fail
)) {
5999 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6000 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6001 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6005 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6006 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6007 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6008 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
6009 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
6010 "(0x%x) and exit reason is 0x%x\n",
6011 __func__
, vectoring_info
, exit_reason
);
6013 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6014 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6015 get_vmcs12(vcpu
), vcpu
)))) {
6016 if (vmx_interrupt_allowed(vcpu
)) {
6017 vmx
->soft_vnmi_blocked
= 0;
6018 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6019 vcpu
->arch
.nmi_pending
) {
6021 * This CPU don't support us in finding the end of an
6022 * NMI-blocked window if the guest runs with IRQs
6023 * disabled. So we pull the trigger after 1 s of
6024 * futile waiting, but inform the user about this.
6026 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6027 "state on VCPU %d after 1 s timeout\n",
6028 __func__
, vcpu
->vcpu_id
);
6029 vmx
->soft_vnmi_blocked
= 0;
6033 if (exit_reason
< kvm_vmx_max_exit_handlers
6034 && kvm_vmx_exit_handlers
[exit_reason
])
6035 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6037 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6038 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6043 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6045 if (irr
== -1 || tpr
< irr
) {
6046 vmcs_write32(TPR_THRESHOLD
, 0);
6050 vmcs_write32(TPR_THRESHOLD
, irr
);
6053 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6057 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6058 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6061 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6062 exit_intr_info
= vmx
->exit_intr_info
;
6064 /* Handle machine checks before interrupts are enabled */
6065 if (is_machine_check(exit_intr_info
))
6066 kvm_machine_check();
6068 /* We need to handle NMIs before interrupts are enabled */
6069 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6070 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6071 kvm_before_handle_nmi(&vmx
->vcpu
);
6073 kvm_after_handle_nmi(&vmx
->vcpu
);
6077 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6082 bool idtv_info_valid
;
6084 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6086 if (cpu_has_virtual_nmis()) {
6087 if (vmx
->nmi_known_unmasked
)
6090 * Can't use vmx->exit_intr_info since we're not sure what
6091 * the exit reason is.
6093 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6094 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6095 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6097 * SDM 3: 27.7.1.2 (September 2008)
6098 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6099 * a guest IRET fault.
6100 * SDM 3: 23.2.2 (September 2008)
6101 * Bit 12 is undefined in any of the following cases:
6102 * If the VM exit sets the valid bit in the IDT-vectoring
6103 * information field.
6104 * If the VM exit is due to a double fault.
6106 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6107 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6108 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6109 GUEST_INTR_STATE_NMI
);
6111 vmx
->nmi_known_unmasked
=
6112 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6113 & GUEST_INTR_STATE_NMI
);
6114 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6115 vmx
->vnmi_blocked_time
+=
6116 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6119 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
6120 u32 idt_vectoring_info
,
6121 int instr_len_field
,
6122 int error_code_field
)
6126 bool idtv_info_valid
;
6128 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6130 vmx
->vcpu
.arch
.nmi_injected
= false;
6131 kvm_clear_exception_queue(&vmx
->vcpu
);
6132 kvm_clear_interrupt_queue(&vmx
->vcpu
);
6134 if (!idtv_info_valid
)
6137 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6139 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6140 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6143 case INTR_TYPE_NMI_INTR
:
6144 vmx
->vcpu
.arch
.nmi_injected
= true;
6146 * SDM 3: 27.7.1.2 (September 2008)
6147 * Clear bit "block by NMI" before VM entry if a NMI
6150 vmx_set_nmi_mask(&vmx
->vcpu
, false);
6152 case INTR_TYPE_SOFT_EXCEPTION
:
6153 vmx
->vcpu
.arch
.event_exit_inst_len
=
6154 vmcs_read32(instr_len_field
);
6156 case INTR_TYPE_HARD_EXCEPTION
:
6157 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6158 u32 err
= vmcs_read32(error_code_field
);
6159 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
6161 kvm_queue_exception(&vmx
->vcpu
, vector
);
6163 case INTR_TYPE_SOFT_INTR
:
6164 vmx
->vcpu
.arch
.event_exit_inst_len
=
6165 vmcs_read32(instr_len_field
);
6167 case INTR_TYPE_EXT_INTR
:
6168 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
6169 type
== INTR_TYPE_SOFT_INTR
);
6176 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6178 if (is_guest_mode(&vmx
->vcpu
))
6180 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
6181 VM_EXIT_INSTRUCTION_LEN
,
6182 IDT_VECTORING_ERROR_CODE
);
6185 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6187 if (is_guest_mode(vcpu
))
6189 __vmx_complete_interrupts(to_vmx(vcpu
),
6190 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6191 VM_ENTRY_INSTRUCTION_LEN
,
6192 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6194 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6197 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6200 struct perf_guest_switch_msr
*msrs
;
6202 msrs
= perf_guest_get_msrs(&nr_msrs
);
6207 for (i
= 0; i
< nr_msrs
; i
++)
6208 if (msrs
[i
].host
== msrs
[i
].guest
)
6209 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6211 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6215 #ifdef CONFIG_X86_64
6223 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6225 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6227 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
6228 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6229 if (vmcs12
->idt_vectoring_info_field
&
6230 VECTORING_INFO_VALID_MASK
) {
6231 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6232 vmcs12
->idt_vectoring_info_field
);
6233 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6234 vmcs12
->vm_exit_instruction_len
);
6235 if (vmcs12
->idt_vectoring_info_field
&
6236 VECTORING_INFO_DELIVER_CODE_MASK
)
6237 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6238 vmcs12
->idt_vectoring_error_code
);
6242 /* Record the guest's net vcpu time for enforced NMI injections. */
6243 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6244 vmx
->entry_time
= ktime_get();
6246 /* Don't enter VMX if guest state is invalid, let the exit handler
6247 start emulation until we arrive back to a valid state */
6248 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
6251 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6252 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6253 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6254 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6256 /* When single-stepping over STI and MOV SS, we must clear the
6257 * corresponding interruptibility bits in the guest state. Otherwise
6258 * vmentry fails as it then expects bit 14 (BS) in pending debug
6259 * exceptions being set, but that's not correct for the guest debugging
6261 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6262 vmx_set_interrupt_shadow(vcpu
, 0);
6264 atomic_switch_perf_msrs(vmx
);
6266 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6268 /* Store host registers */
6269 "push %%"R
"dx; push %%"R
"bp;"
6270 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
6272 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
6274 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
6275 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6277 /* Reload cr2 if changed */
6278 "mov %c[cr2](%0), %%"R
"ax \n\t"
6279 "mov %%cr2, %%"R
"dx \n\t"
6280 "cmp %%"R
"ax, %%"R
"dx \n\t"
6282 "mov %%"R
"ax, %%cr2 \n\t"
6284 /* Check if vmlaunch of vmresume is needed */
6285 "cmpl $0, %c[launched](%0) \n\t"
6286 /* Load guest registers. Don't clobber flags. */
6287 "mov %c[rax](%0), %%"R
"ax \n\t"
6288 "mov %c[rbx](%0), %%"R
"bx \n\t"
6289 "mov %c[rdx](%0), %%"R
"dx \n\t"
6290 "mov %c[rsi](%0), %%"R
"si \n\t"
6291 "mov %c[rdi](%0), %%"R
"di \n\t"
6292 "mov %c[rbp](%0), %%"R
"bp \n\t"
6293 #ifdef CONFIG_X86_64
6294 "mov %c[r8](%0), %%r8 \n\t"
6295 "mov %c[r9](%0), %%r9 \n\t"
6296 "mov %c[r10](%0), %%r10 \n\t"
6297 "mov %c[r11](%0), %%r11 \n\t"
6298 "mov %c[r12](%0), %%r12 \n\t"
6299 "mov %c[r13](%0), %%r13 \n\t"
6300 "mov %c[r14](%0), %%r14 \n\t"
6301 "mov %c[r15](%0), %%r15 \n\t"
6303 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
6305 /* Enter guest mode */
6306 "jne .Llaunched \n\t"
6307 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6308 "jmp .Lkvm_vmx_return \n\t"
6309 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6310 ".Lkvm_vmx_return: "
6311 /* Save guest registers, load host registers, keep flags */
6312 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
6314 "mov %%"R
"ax, %c[rax](%0) \n\t"
6315 "mov %%"R
"bx, %c[rbx](%0) \n\t"
6316 "pop"Q
" %c[rcx](%0) \n\t"
6317 "mov %%"R
"dx, %c[rdx](%0) \n\t"
6318 "mov %%"R
"si, %c[rsi](%0) \n\t"
6319 "mov %%"R
"di, %c[rdi](%0) \n\t"
6320 "mov %%"R
"bp, %c[rbp](%0) \n\t"
6321 #ifdef CONFIG_X86_64
6322 "mov %%r8, %c[r8](%0) \n\t"
6323 "mov %%r9, %c[r9](%0) \n\t"
6324 "mov %%r10, %c[r10](%0) \n\t"
6325 "mov %%r11, %c[r11](%0) \n\t"
6326 "mov %%r12, %c[r12](%0) \n\t"
6327 "mov %%r13, %c[r13](%0) \n\t"
6328 "mov %%r14, %c[r14](%0) \n\t"
6329 "mov %%r15, %c[r15](%0) \n\t"
6331 "mov %%cr2, %%"R
"ax \n\t"
6332 "mov %%"R
"ax, %c[cr2](%0) \n\t"
6334 "pop %%"R
"bp; pop %%"R
"dx \n\t"
6335 "setbe %c[fail](%0) \n\t"
6336 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6337 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6338 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6339 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6340 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6341 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6342 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6343 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6344 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6345 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6346 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6347 #ifdef CONFIG_X86_64
6348 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6349 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6350 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6351 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6352 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6353 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6354 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6355 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6357 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6358 [wordsize
]"i"(sizeof(ulong
))
6360 , R
"ax", R
"bx", R
"di", R
"si"
6361 #ifdef CONFIG_X86_64
6362 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6366 #ifndef CONFIG_X86_64
6368 * The sysexit path does not restore ds/es, so we must set them to
6369 * a reasonable value ourselves.
6371 * We can't defer this to vmx_load_host_state() since that function
6372 * may be executed in interrupt context, which saves and restore segments
6373 * around it, nullifying its effect.
6375 loadsegment(ds
, __USER_DS
);
6376 loadsegment(es
, __USER_DS
);
6379 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6380 | (1 << VCPU_EXREG_RFLAGS
)
6381 | (1 << VCPU_EXREG_CPL
)
6382 | (1 << VCPU_EXREG_PDPTR
)
6383 | (1 << VCPU_EXREG_SEGMENTS
)
6384 | (1 << VCPU_EXREG_CR3
));
6385 vcpu
->arch
.regs_dirty
= 0;
6387 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6389 if (is_guest_mode(vcpu
)) {
6390 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6391 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6392 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6393 vmcs12
->idt_vectoring_error_code
=
6394 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6395 vmcs12
->vm_exit_instruction_len
=
6396 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6400 vmx
->loaded_vmcs
->launched
= 1;
6402 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6403 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6405 vmx_complete_atomic_exit(vmx
);
6406 vmx_recover_nmi_blocking(vmx
);
6407 vmx_complete_interrupts(vmx
);
6413 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6415 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6419 free_loaded_vmcs(vmx
->loaded_vmcs
);
6420 kfree(vmx
->guest_msrs
);
6421 kvm_vcpu_uninit(vcpu
);
6422 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6425 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6428 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6432 return ERR_PTR(-ENOMEM
);
6436 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6440 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6442 if (!vmx
->guest_msrs
) {
6446 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6447 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6448 if (!vmx
->loaded_vmcs
->vmcs
)
6451 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6452 loaded_vmcs_init(vmx
->loaded_vmcs
);
6457 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6458 vmx
->vcpu
.cpu
= cpu
;
6459 err
= vmx_vcpu_setup(vmx
);
6460 vmx_vcpu_put(&vmx
->vcpu
);
6464 if (vm_need_virtualize_apic_accesses(kvm
))
6465 err
= alloc_apic_access_page(kvm
);
6470 if (!kvm
->arch
.ept_identity_map_addr
)
6471 kvm
->arch
.ept_identity_map_addr
=
6472 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6474 if (alloc_identity_pagetable(kvm
) != 0)
6476 if (!init_rmode_identity_map(kvm
))
6480 vmx
->nested
.current_vmptr
= -1ull;
6481 vmx
->nested
.current_vmcs12
= NULL
;
6486 free_loaded_vmcs(vmx
->loaded_vmcs
);
6488 kfree(vmx
->guest_msrs
);
6490 kvm_vcpu_uninit(&vmx
->vcpu
);
6493 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6494 return ERR_PTR(err
);
6497 static void __init
vmx_check_processor_compat(void *rtn
)
6499 struct vmcs_config vmcs_conf
;
6502 if (setup_vmcs_config(&vmcs_conf
) < 0)
6504 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6505 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6506 smp_processor_id());
6511 static int get_ept_level(void)
6513 return VMX_EPT_DEFAULT_GAW
+ 1;
6516 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6520 /* For VT-d and EPT combination
6521 * 1. MMIO: always map as UC
6523 * a. VT-d without snooping control feature: can't guarantee the
6524 * result, try to trust guest.
6525 * b. VT-d with snooping control feature: snooping control feature of
6526 * VT-d engine can guarantee the cache correctness. Just set it
6527 * to WB to keep consistent with host. So the same as item 3.
6528 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6529 * consistent with host MTRR
6532 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6533 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6534 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6535 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6536 VMX_EPT_MT_EPTE_SHIFT
;
6538 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6544 static int vmx_get_lpage_level(void)
6546 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6547 return PT_DIRECTORY_LEVEL
;
6549 /* For shadow and EPT supported 1GB page */
6550 return PT_PDPE_LEVEL
;
6553 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6555 struct kvm_cpuid_entry2
*best
;
6556 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6559 vmx
->rdtscp_enabled
= false;
6560 if (vmx_rdtscp_supported()) {
6561 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6562 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6563 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6564 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6565 vmx
->rdtscp_enabled
= true;
6567 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6568 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6574 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6575 /* Exposing INVPCID only when PCID is exposed */
6576 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
6577 if (vmx_invpcid_supported() &&
6578 best
&& (best
->ecx
& bit(X86_FEATURE_INVPCID
)) &&
6579 guest_cpuid_has_pcid(vcpu
)) {
6580 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
6581 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6584 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
6585 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6588 best
->ecx
&= ~bit(X86_FEATURE_INVPCID
);
6592 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6594 if (func
== 1 && nested
)
6595 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6599 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6600 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6601 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6602 * guest in a way that will both be appropriate to L1's requests, and our
6603 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6604 * function also has additional necessary side-effects, like setting various
6605 * vcpu->arch fields.
6607 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6609 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6612 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6613 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6614 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6615 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6616 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6617 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6618 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6619 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6620 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6621 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6622 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6623 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6624 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6625 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6626 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6627 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6628 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6629 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6630 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6631 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6632 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6633 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6634 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6635 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6636 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6637 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6638 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6639 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6640 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6641 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6642 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6643 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6644 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6645 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6646 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6647 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6649 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6650 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6651 vmcs12
->vm_entry_intr_info_field
);
6652 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6653 vmcs12
->vm_entry_exception_error_code
);
6654 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6655 vmcs12
->vm_entry_instruction_len
);
6656 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6657 vmcs12
->guest_interruptibility_info
);
6658 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6659 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6660 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6661 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6662 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6663 vmcs12
->guest_pending_dbg_exceptions
);
6664 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6665 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6667 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6669 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6670 (vmcs_config
.pin_based_exec_ctrl
|
6671 vmcs12
->pin_based_vm_exec_control
));
6674 * Whether page-faults are trapped is determined by a combination of
6675 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6676 * If enable_ept, L0 doesn't care about page faults and we should
6677 * set all of these to L1's desires. However, if !enable_ept, L0 does
6678 * care about (at least some) page faults, and because it is not easy
6679 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6680 * to exit on each and every L2 page fault. This is done by setting
6681 * MASK=MATCH=0 and (see below) EB.PF=1.
6682 * Note that below we don't need special code to set EB.PF beyond the
6683 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6684 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6685 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6687 * A problem with this approach (when !enable_ept) is that L1 may be
6688 * injected with more page faults than it asked for. This could have
6689 * caused problems, but in practice existing hypervisors don't care.
6690 * To fix this, we will need to emulate the PFEC checking (on the L1
6691 * page tables), using walk_addr(), when injecting PFs to L1.
6693 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6694 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6695 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6696 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6698 if (cpu_has_secondary_exec_ctrls()) {
6699 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6700 if (!vmx
->rdtscp_enabled
)
6701 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6702 /* Take the following fields only from vmcs12 */
6703 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6704 if (nested_cpu_has(vmcs12
,
6705 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6706 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6708 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6710 * Translate L1 physical address to host physical
6711 * address for vmcs02. Keep the page pinned, so this
6712 * physical address remains valid. We keep a reference
6713 * to it so we can release it later.
6715 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6716 nested_release_page(vmx
->nested
.apic_access_page
);
6717 vmx
->nested
.apic_access_page
=
6718 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6720 * If translation failed, no matter: This feature asks
6721 * to exit when accessing the given address, and if it
6722 * can never be accessed, this feature won't do
6725 if (!vmx
->nested
.apic_access_page
)
6727 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6729 vmcs_write64(APIC_ACCESS_ADDR
,
6730 page_to_phys(vmx
->nested
.apic_access_page
));
6733 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6738 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6739 * Some constant fields are set here by vmx_set_constant_host_state().
6740 * Other fields are different per CPU, and will be set later when
6741 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6743 vmx_set_constant_host_state();
6746 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6747 * entry, but only if the current (host) sp changed from the value
6748 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6749 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6750 * here we just force the write to happen on entry.
6754 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
6755 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
6756 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6757 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6758 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
6760 * Merging of IO and MSR bitmaps not currently supported.
6761 * Rather, exit every time.
6763 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
6764 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
6765 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
6767 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
6769 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6770 * bitwise-or of what L1 wants to trap for L2, and what we want to
6771 * trap. Note that CR0.TS also needs updating - we do this later.
6773 update_exception_bitmap(vcpu
);
6774 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
6775 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6777 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6778 vmcs_write32(VM_EXIT_CONTROLS
,
6779 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
6780 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
6781 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
6783 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
6784 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
6785 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6786 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6789 set_cr4_guest_host_mask(vmx
);
6791 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
6792 vmcs_write64(TSC_OFFSET
,
6793 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
6795 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6799 * Trivially support vpid by letting L2s share their parent
6800 * L1's vpid. TODO: move to a more elaborate solution, giving
6801 * each L2 its own vpid and exposing the vpid feature to L1.
6803 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6804 vmx_flush_tlb(vcpu
);
6807 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
6808 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
6809 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
6810 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6812 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6813 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6814 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6817 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6818 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6819 * The CR0_READ_SHADOW is what L2 should have expected to read given
6820 * the specifications by L1; It's not enough to take
6821 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6822 * have more bits than L1 expected.
6824 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
6825 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
6827 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
6828 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
6830 /* shadow page tables on either EPT or shadow page tables */
6831 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
6832 kvm_mmu_reset_context(vcpu
);
6834 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
6835 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
6839 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6840 * for running an L2 nested guest.
6842 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
6844 struct vmcs12
*vmcs12
;
6845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6847 struct loaded_vmcs
*vmcs02
;
6849 if (!nested_vmx_check_permission(vcpu
) ||
6850 !nested_vmx_check_vmcs12(vcpu
))
6853 skip_emulated_instruction(vcpu
);
6854 vmcs12
= get_vmcs12(vcpu
);
6857 * The nested entry process starts with enforcing various prerequisites
6858 * on vmcs12 as required by the Intel SDM, and act appropriately when
6859 * they fail: As the SDM explains, some conditions should cause the
6860 * instruction to fail, while others will cause the instruction to seem
6861 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6862 * To speed up the normal (success) code path, we should avoid checking
6863 * for misconfigurations which will anyway be caught by the processor
6864 * when using the merged vmcs02.
6866 if (vmcs12
->launch_state
== launch
) {
6867 nested_vmx_failValid(vcpu
,
6868 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6869 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
6873 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
6874 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
6875 /*TODO: Also verify bits beyond physical address width are 0*/
6876 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6880 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
6881 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
6882 /*TODO: Also verify bits beyond physical address width are 0*/
6883 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6887 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
6888 vmcs12
->vm_exit_msr_load_count
> 0 ||
6889 vmcs12
->vm_exit_msr_store_count
> 0) {
6890 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6892 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6896 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
6897 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
6898 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
6899 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
6900 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
6901 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
6902 !vmx_control_verify(vmcs12
->vm_exit_controls
,
6903 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
6904 !vmx_control_verify(vmcs12
->vm_entry_controls
,
6905 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
6907 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6911 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6912 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6913 nested_vmx_failValid(vcpu
,
6914 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
6918 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6919 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6920 nested_vmx_entry_failure(vcpu
, vmcs12
,
6921 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
6924 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
6925 nested_vmx_entry_failure(vcpu
, vmcs12
,
6926 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
6931 * We're finally done with prerequisite checking, and can start with
6935 vmcs02
= nested_get_current_vmcs02(vmx
);
6939 enter_guest_mode(vcpu
);
6941 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
6944 vmx
->loaded_vmcs
= vmcs02
;
6946 vmx_vcpu_load(vcpu
, cpu
);
6950 vmcs12
->launch_state
= 1;
6952 prepare_vmcs02(vcpu
, vmcs12
);
6955 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6956 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6957 * returned as far as L1 is concerned. It will only return (and set
6958 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6964 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6965 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6966 * This function returns the new value we should put in vmcs12.guest_cr0.
6967 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6968 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6969 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6970 * didn't trap the bit, because if L1 did, so would L0).
6971 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6972 * been modified by L2, and L1 knows it. So just leave the old value of
6973 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6974 * isn't relevant, because if L0 traps this bit it can set it to anything.
6975 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6976 * changed these bits, and therefore they need to be updated, but L0
6977 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6978 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6980 static inline unsigned long
6981 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6984 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
6985 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
6986 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
6987 vcpu
->arch
.cr0_guest_owned_bits
));
6990 static inline unsigned long
6991 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6994 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
6995 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
6996 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
6997 vcpu
->arch
.cr4_guest_owned_bits
));
7001 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7002 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7003 * and this function updates it to reflect the changes to the guest state while
7004 * L2 was running (and perhaps made some exits which were handled directly by L0
7005 * without going back to L1), and to reflect the exit reason.
7006 * Note that we do not have to copy here all VMCS fields, just those that
7007 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7008 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7009 * which already writes to vmcs12 directly.
7011 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7013 /* update guest state fields: */
7014 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
7015 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
7017 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
7018 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
7019 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
7020 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
7022 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
7023 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
7024 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
7025 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
7026 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
7027 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
7028 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
7029 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
7030 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
7031 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
7032 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
7033 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
7034 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
7035 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
7036 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
7037 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
7038 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
7039 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
7040 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
7041 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
7042 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
7043 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
7044 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
7045 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
7046 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
7047 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
7048 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
7049 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
7050 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
7051 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
7052 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
7053 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
7054 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
7055 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
7056 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
7057 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
7059 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
7060 vmcs12
->guest_interruptibility_info
=
7061 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
7062 vmcs12
->guest_pending_dbg_exceptions
=
7063 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
7065 /* TODO: These cannot have changed unless we have MSR bitmaps and
7066 * the relevant bit asks not to trap the change */
7067 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
7068 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
7069 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
7070 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
7071 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
7072 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
7074 /* update exit information fields: */
7076 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7077 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7079 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7080 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7081 vmcs12
->idt_vectoring_info_field
=
7082 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7083 vmcs12
->idt_vectoring_error_code
=
7084 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
7085 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7086 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7088 /* clear vm-entry fields which are to be cleared on exit */
7089 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
7090 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
7094 * A part of what we need to when the nested L2 guest exits and we want to
7095 * run its L1 parent, is to reset L1's guest state to the host state specified
7097 * This function is to be called not only on normal nested exit, but also on
7098 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7099 * Failures During or After Loading Guest State").
7100 * This function should be called when the active VMCS is L1's (vmcs01).
7102 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7104 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
7105 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7106 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7107 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7109 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7110 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7112 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7113 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7115 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7116 * actually changed, because it depends on the current state of
7117 * fpu_active (which may have changed).
7118 * Note that vmx_set_cr0 refers to efer set above.
7120 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
7122 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7123 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7124 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7126 update_exception_bitmap(vcpu
);
7127 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
7128 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7131 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7132 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7134 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
7135 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
7137 /* shadow page tables on either EPT or shadow page tables */
7138 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
7139 kvm_mmu_reset_context(vcpu
);
7143 * Trivially support vpid by letting L2s share their parent
7144 * L1's vpid. TODO: move to a more elaborate solution, giving
7145 * each L2 its own vpid and exposing the vpid feature to L1.
7147 vmx_flush_tlb(vcpu
);
7151 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
7152 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
7153 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
7154 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
7155 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
7156 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
7157 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
7158 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
7159 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
7160 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
7161 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
7162 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
7163 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
7164 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
7165 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
7167 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
7168 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
7169 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7170 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
7171 vmcs12
->host_ia32_perf_global_ctrl
);
7175 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7176 * and modify vmcs12 to make it see what it would expect to see there if
7177 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7179 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
7181 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7183 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7185 leave_guest_mode(vcpu
);
7186 prepare_vmcs12(vcpu
, vmcs12
);
7189 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7191 vmx_vcpu_load(vcpu
, cpu
);
7195 /* if no vmcs02 cache requested, remove the one we used */
7196 if (VMCS02_POOL_SIZE
== 0)
7197 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
7199 load_vmcs12_host_state(vcpu
, vmcs12
);
7201 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7202 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7204 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7207 /* Unpin physical memory we referred to in vmcs02 */
7208 if (vmx
->nested
.apic_access_page
) {
7209 nested_release_page(vmx
->nested
.apic_access_page
);
7210 vmx
->nested
.apic_access_page
= 0;
7214 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7215 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7216 * success or failure flag accordingly.
7218 if (unlikely(vmx
->fail
)) {
7220 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
7222 nested_vmx_succeed(vcpu
);
7226 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7227 * 23.7 "VM-entry failures during or after loading guest state" (this also
7228 * lists the acceptable exit-reason and exit-qualification parameters).
7229 * It should only be called before L2 actually succeeded to run, and when
7230 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7232 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
7233 struct vmcs12
*vmcs12
,
7234 u32 reason
, unsigned long qualification
)
7236 load_vmcs12_host_state(vcpu
, vmcs12
);
7237 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
7238 vmcs12
->exit_qualification
= qualification
;
7239 nested_vmx_succeed(vcpu
);
7242 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7243 struct x86_instruction_info
*info
,
7244 enum x86_intercept_stage stage
)
7246 return X86EMUL_CONTINUE
;
7249 static struct kvm_x86_ops vmx_x86_ops
= {
7250 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7251 .disabled_by_bios
= vmx_disabled_by_bios
,
7252 .hardware_setup
= hardware_setup
,
7253 .hardware_unsetup
= hardware_unsetup
,
7254 .check_processor_compatibility
= vmx_check_processor_compat
,
7255 .hardware_enable
= hardware_enable
,
7256 .hardware_disable
= hardware_disable
,
7257 .cpu_has_accelerated_tpr
= report_flexpriority
,
7259 .vcpu_create
= vmx_create_vcpu
,
7260 .vcpu_free
= vmx_free_vcpu
,
7261 .vcpu_reset
= vmx_vcpu_reset
,
7263 .prepare_guest_switch
= vmx_save_host_state
,
7264 .vcpu_load
= vmx_vcpu_load
,
7265 .vcpu_put
= vmx_vcpu_put
,
7267 .set_guest_debug
= set_guest_debug
,
7268 .get_msr
= vmx_get_msr
,
7269 .set_msr
= vmx_set_msr
,
7270 .get_segment_base
= vmx_get_segment_base
,
7271 .get_segment
= vmx_get_segment
,
7272 .set_segment
= vmx_set_segment
,
7273 .get_cpl
= vmx_get_cpl
,
7274 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7275 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7276 .decache_cr3
= vmx_decache_cr3
,
7277 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7278 .set_cr0
= vmx_set_cr0
,
7279 .set_cr3
= vmx_set_cr3
,
7280 .set_cr4
= vmx_set_cr4
,
7281 .set_efer
= vmx_set_efer
,
7282 .get_idt
= vmx_get_idt
,
7283 .set_idt
= vmx_set_idt
,
7284 .get_gdt
= vmx_get_gdt
,
7285 .set_gdt
= vmx_set_gdt
,
7286 .set_dr7
= vmx_set_dr7
,
7287 .cache_reg
= vmx_cache_reg
,
7288 .get_rflags
= vmx_get_rflags
,
7289 .set_rflags
= vmx_set_rflags
,
7290 .fpu_activate
= vmx_fpu_activate
,
7291 .fpu_deactivate
= vmx_fpu_deactivate
,
7293 .tlb_flush
= vmx_flush_tlb
,
7295 .run
= vmx_vcpu_run
,
7296 .handle_exit
= vmx_handle_exit
,
7297 .skip_emulated_instruction
= skip_emulated_instruction
,
7298 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7299 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7300 .patch_hypercall
= vmx_patch_hypercall
,
7301 .set_irq
= vmx_inject_irq
,
7302 .set_nmi
= vmx_inject_nmi
,
7303 .queue_exception
= vmx_queue_exception
,
7304 .cancel_injection
= vmx_cancel_injection
,
7305 .interrupt_allowed
= vmx_interrupt_allowed
,
7306 .nmi_allowed
= vmx_nmi_allowed
,
7307 .get_nmi_mask
= vmx_get_nmi_mask
,
7308 .set_nmi_mask
= vmx_set_nmi_mask
,
7309 .enable_nmi_window
= enable_nmi_window
,
7310 .enable_irq_window
= enable_irq_window
,
7311 .update_cr8_intercept
= update_cr8_intercept
,
7313 .set_tss_addr
= vmx_set_tss_addr
,
7314 .get_tdp_level
= get_ept_level
,
7315 .get_mt_mask
= vmx_get_mt_mask
,
7317 .get_exit_info
= vmx_get_exit_info
,
7319 .get_lpage_level
= vmx_get_lpage_level
,
7321 .cpuid_update
= vmx_cpuid_update
,
7323 .rdtscp_supported
= vmx_rdtscp_supported
,
7324 .invpcid_supported
= vmx_invpcid_supported
,
7326 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7328 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7330 .set_tsc_khz
= vmx_set_tsc_khz
,
7331 .write_tsc_offset
= vmx_write_tsc_offset
,
7332 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7333 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7334 .read_l1_tsc
= vmx_read_l1_tsc
,
7336 .set_tdp_cr3
= vmx_set_cr3
,
7338 .check_intercept
= vmx_check_intercept
,
7341 static int __init
vmx_init(void)
7345 rdmsrl_safe(MSR_EFER
, &host_efer
);
7347 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7348 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7350 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7351 if (!vmx_io_bitmap_a
)
7356 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7357 if (!vmx_io_bitmap_b
)
7360 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7361 if (!vmx_msr_bitmap_legacy
)
7365 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7366 if (!vmx_msr_bitmap_longmode
)
7371 * Allow direct access to the PC debug port (it is often used for I/O
7372 * delays, but the vmexits simply slow things down).
7374 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7375 clear_bit(0x80, vmx_io_bitmap_a
);
7377 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7379 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7380 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7382 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7384 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7385 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7389 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7390 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7391 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7392 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7393 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7394 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7397 kvm_mmu_set_mask_ptes(0ull,
7398 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
7399 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
7400 0ull, VMX_EPT_EXECUTABLE_MASK
);
7401 ept_set_mmio_spte_mask();
7409 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7411 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7413 free_page((unsigned long)vmx_io_bitmap_b
);
7415 free_page((unsigned long)vmx_io_bitmap_a
);
7419 static void __exit
vmx_exit(void)
7421 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7422 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7423 free_page((unsigned long)vmx_io_bitmap_b
);
7424 free_page((unsigned long)vmx_io_bitmap_a
);
7429 module_init(vmx_init
)
7430 module_exit(vmx_exit
)