2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
43 #include <asm/fpu/internal.h>
44 #include <asm/perf_event.h>
45 #include <asm/debugreg.h>
46 #include <asm/kexec.h>
48 #include <asm/irq_remapping.h>
53 #define __ex(x) __kvm_handle_fault_on_reboot(x)
54 #define __ex_clear(x, reg) \
55 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
57 MODULE_AUTHOR("Qumranet");
58 MODULE_LICENSE("GPL");
60 static const struct x86_cpu_id vmx_cpu_id
[] = {
61 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
64 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
66 static bool __read_mostly enable_vpid
= 1;
67 module_param_named(vpid
, enable_vpid
, bool, 0444);
69 static bool __read_mostly flexpriority_enabled
= 1;
70 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
72 static bool __read_mostly enable_ept
= 1;
73 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
75 static bool __read_mostly enable_unrestricted_guest
= 1;
76 module_param_named(unrestricted_guest
,
77 enable_unrestricted_guest
, bool, S_IRUGO
);
79 static bool __read_mostly enable_ept_ad_bits
= 1;
80 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
82 static bool __read_mostly emulate_invalid_guest_state
= true;
83 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
85 static bool __read_mostly vmm_exclusive
= 1;
86 module_param(vmm_exclusive
, bool, S_IRUGO
);
88 static bool __read_mostly fasteoi
= 1;
89 module_param(fasteoi
, bool, S_IRUGO
);
91 static bool __read_mostly enable_apicv
= 1;
92 module_param(enable_apicv
, bool, S_IRUGO
);
94 static bool __read_mostly enable_shadow_vmcs
= 1;
95 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
97 * If nested=1, nested virtualization is supported, i.e., guests may use
98 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
99 * use VMX instructions.
101 static bool __read_mostly nested
= 0;
102 module_param(nested
, bool, S_IRUGO
);
104 static u64 __read_mostly host_xss
;
106 static bool __read_mostly enable_pml
= 1;
107 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
109 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
110 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
111 #define KVM_VM_CR0_ALWAYS_ON \
112 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
113 #define KVM_CR4_GUEST_OWNED_BITS \
114 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
115 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
117 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
118 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
120 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
122 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
125 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
126 * ple_gap: upper bound on the amount of time between two successive
127 * executions of PAUSE in a loop. Also indicate if ple enabled.
128 * According to test, this time is usually smaller than 128 cycles.
129 * ple_window: upper bound on the amount of time a guest is allowed to execute
130 * in a PAUSE loop. Tests indicate that most spinlocks are held for
131 * less than 2^12 cycles
132 * Time is measured based on a counter that runs at the same rate as the TSC,
133 * refer SDM volume 3b section 21.6.13 & 22.1.3.
135 #define KVM_VMX_DEFAULT_PLE_GAP 128
136 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
139 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
140 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
142 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
143 module_param(ple_gap
, int, S_IRUGO
);
145 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
146 module_param(ple_window
, int, S_IRUGO
);
148 /* Default doubles per-vcpu window every exit. */
149 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
150 module_param(ple_window_grow
, int, S_IRUGO
);
152 /* Default resets per-vcpu window every exit to ple_window. */
153 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
154 module_param(ple_window_shrink
, int, S_IRUGO
);
156 /* Default is to compute the maximum so we can never overflow. */
157 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
158 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
159 module_param(ple_window_max
, int, S_IRUGO
);
161 extern const ulong vmx_return
;
163 #define NR_AUTOLOAD_MSRS 8
164 #define VMCS02_POOL_SIZE 1
173 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
174 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
175 * loaded on this CPU (so we can clear them if the CPU goes down).
181 struct list_head loaded_vmcss_on_cpu_link
;
184 struct shared_msr_entry
{
191 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
192 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
193 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
194 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
195 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
196 * More than one of these structures may exist, if L1 runs multiple L2 guests.
197 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
198 * underlying hardware which will be used to run L2.
199 * This structure is packed to ensure that its layout is identical across
200 * machines (necessary for live migration).
201 * If there are changes in this struct, VMCS12_REVISION must be changed.
203 typedef u64 natural_width
;
204 struct __packed vmcs12
{
205 /* According to the Intel spec, a VMCS region must start with the
206 * following two fields. Then follow implementation-specific data.
211 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
212 u32 padding
[7]; /* room for future expansion */
217 u64 vm_exit_msr_store_addr
;
218 u64 vm_exit_msr_load_addr
;
219 u64 vm_entry_msr_load_addr
;
221 u64 virtual_apic_page_addr
;
222 u64 apic_access_addr
;
223 u64 posted_intr_desc_addr
;
225 u64 eoi_exit_bitmap0
;
226 u64 eoi_exit_bitmap1
;
227 u64 eoi_exit_bitmap2
;
228 u64 eoi_exit_bitmap3
;
230 u64 guest_physical_address
;
231 u64 vmcs_link_pointer
;
232 u64 guest_ia32_debugctl
;
235 u64 guest_ia32_perf_global_ctrl
;
243 u64 host_ia32_perf_global_ctrl
;
244 u64 padding64
[8]; /* room for future expansion */
246 * To allow migration of L1 (complete with its L2 guests) between
247 * machines of different natural widths (32 or 64 bit), we cannot have
248 * unsigned long fields with no explict size. We use u64 (aliased
249 * natural_width) instead. Luckily, x86 is little-endian.
251 natural_width cr0_guest_host_mask
;
252 natural_width cr4_guest_host_mask
;
253 natural_width cr0_read_shadow
;
254 natural_width cr4_read_shadow
;
255 natural_width cr3_target_value0
;
256 natural_width cr3_target_value1
;
257 natural_width cr3_target_value2
;
258 natural_width cr3_target_value3
;
259 natural_width exit_qualification
;
260 natural_width guest_linear_address
;
261 natural_width guest_cr0
;
262 natural_width guest_cr3
;
263 natural_width guest_cr4
;
264 natural_width guest_es_base
;
265 natural_width guest_cs_base
;
266 natural_width guest_ss_base
;
267 natural_width guest_ds_base
;
268 natural_width guest_fs_base
;
269 natural_width guest_gs_base
;
270 natural_width guest_ldtr_base
;
271 natural_width guest_tr_base
;
272 natural_width guest_gdtr_base
;
273 natural_width guest_idtr_base
;
274 natural_width guest_dr7
;
275 natural_width guest_rsp
;
276 natural_width guest_rip
;
277 natural_width guest_rflags
;
278 natural_width guest_pending_dbg_exceptions
;
279 natural_width guest_sysenter_esp
;
280 natural_width guest_sysenter_eip
;
281 natural_width host_cr0
;
282 natural_width host_cr3
;
283 natural_width host_cr4
;
284 natural_width host_fs_base
;
285 natural_width host_gs_base
;
286 natural_width host_tr_base
;
287 natural_width host_gdtr_base
;
288 natural_width host_idtr_base
;
289 natural_width host_ia32_sysenter_esp
;
290 natural_width host_ia32_sysenter_eip
;
291 natural_width host_rsp
;
292 natural_width host_rip
;
293 natural_width paddingl
[8]; /* room for future expansion */
294 u32 pin_based_vm_exec_control
;
295 u32 cpu_based_vm_exec_control
;
296 u32 exception_bitmap
;
297 u32 page_fault_error_code_mask
;
298 u32 page_fault_error_code_match
;
299 u32 cr3_target_count
;
300 u32 vm_exit_controls
;
301 u32 vm_exit_msr_store_count
;
302 u32 vm_exit_msr_load_count
;
303 u32 vm_entry_controls
;
304 u32 vm_entry_msr_load_count
;
305 u32 vm_entry_intr_info_field
;
306 u32 vm_entry_exception_error_code
;
307 u32 vm_entry_instruction_len
;
309 u32 secondary_vm_exec_control
;
310 u32 vm_instruction_error
;
312 u32 vm_exit_intr_info
;
313 u32 vm_exit_intr_error_code
;
314 u32 idt_vectoring_info_field
;
315 u32 idt_vectoring_error_code
;
316 u32 vm_exit_instruction_len
;
317 u32 vmx_instruction_info
;
324 u32 guest_ldtr_limit
;
326 u32 guest_gdtr_limit
;
327 u32 guest_idtr_limit
;
328 u32 guest_es_ar_bytes
;
329 u32 guest_cs_ar_bytes
;
330 u32 guest_ss_ar_bytes
;
331 u32 guest_ds_ar_bytes
;
332 u32 guest_fs_ar_bytes
;
333 u32 guest_gs_ar_bytes
;
334 u32 guest_ldtr_ar_bytes
;
335 u32 guest_tr_ar_bytes
;
336 u32 guest_interruptibility_info
;
337 u32 guest_activity_state
;
338 u32 guest_sysenter_cs
;
339 u32 host_ia32_sysenter_cs
;
340 u32 vmx_preemption_timer_value
;
341 u32 padding32
[7]; /* room for future expansion */
342 u16 virtual_processor_id
;
344 u16 guest_es_selector
;
345 u16 guest_cs_selector
;
346 u16 guest_ss_selector
;
347 u16 guest_ds_selector
;
348 u16 guest_fs_selector
;
349 u16 guest_gs_selector
;
350 u16 guest_ldtr_selector
;
351 u16 guest_tr_selector
;
352 u16 guest_intr_status
;
353 u16 host_es_selector
;
354 u16 host_cs_selector
;
355 u16 host_ss_selector
;
356 u16 host_ds_selector
;
357 u16 host_fs_selector
;
358 u16 host_gs_selector
;
359 u16 host_tr_selector
;
363 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
364 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
365 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
367 #define VMCS12_REVISION 0x11e57ed0
370 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
371 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
372 * current implementation, 4K are reserved to avoid future complications.
374 #define VMCS12_SIZE 0x1000
376 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
378 struct list_head list
;
380 struct loaded_vmcs vmcs02
;
384 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
385 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
388 /* Has the level1 guest done vmxon? */
392 /* The guest-physical address of the current VMCS L1 keeps for L2 */
394 /* The host-usable pointer to the above */
395 struct page
*current_vmcs12_page
;
396 struct vmcs12
*current_vmcs12
;
397 struct vmcs
*current_shadow_vmcs
;
399 * Indicates if the shadow vmcs must be updated with the
400 * data hold by vmcs12
402 bool sync_shadow_vmcs
;
404 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
405 struct list_head vmcs02_pool
;
407 u64 vmcs01_tsc_offset
;
408 /* L2 must run next, and mustn't decide to exit to L1. */
409 bool nested_run_pending
;
411 * Guest pages referred to in vmcs02 with host-physical pointers, so
412 * we must keep them pinned while L2 runs.
414 struct page
*apic_access_page
;
415 struct page
*virtual_apic_page
;
416 struct page
*pi_desc_page
;
417 struct pi_desc
*pi_desc
;
420 u64 msr_ia32_feature_control
;
422 struct hrtimer preemption_timer
;
423 bool preemption_timer_expired
;
425 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
428 u32 nested_vmx_procbased_ctls_low
;
429 u32 nested_vmx_procbased_ctls_high
;
430 u32 nested_vmx_true_procbased_ctls_low
;
431 u32 nested_vmx_secondary_ctls_low
;
432 u32 nested_vmx_secondary_ctls_high
;
433 u32 nested_vmx_pinbased_ctls_low
;
434 u32 nested_vmx_pinbased_ctls_high
;
435 u32 nested_vmx_exit_ctls_low
;
436 u32 nested_vmx_exit_ctls_high
;
437 u32 nested_vmx_true_exit_ctls_low
;
438 u32 nested_vmx_entry_ctls_low
;
439 u32 nested_vmx_entry_ctls_high
;
440 u32 nested_vmx_true_entry_ctls_low
;
441 u32 nested_vmx_misc_low
;
442 u32 nested_vmx_misc_high
;
443 u32 nested_vmx_ept_caps
;
446 #define POSTED_INTR_ON 0
447 #define POSTED_INTR_SN 1
449 /* Posted-Interrupt Descriptor */
451 u32 pir
[8]; /* Posted interrupt requested */
454 /* bit 256 - Outstanding Notification */
456 /* bit 257 - Suppress Notification */
458 /* bit 271:258 - Reserved */
460 /* bit 279:272 - Notification Vector */
462 /* bit 287:280 - Reserved */
464 /* bit 319:288 - Notification Destination */
472 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
474 return test_and_set_bit(POSTED_INTR_ON
,
475 (unsigned long *)&pi_desc
->control
);
478 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
480 return test_and_clear_bit(POSTED_INTR_ON
,
481 (unsigned long *)&pi_desc
->control
);
484 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
486 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
489 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
491 return clear_bit(POSTED_INTR_SN
,
492 (unsigned long *)&pi_desc
->control
);
495 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
497 return set_bit(POSTED_INTR_SN
,
498 (unsigned long *)&pi_desc
->control
);
501 static inline int pi_test_on(struct pi_desc
*pi_desc
)
503 return test_bit(POSTED_INTR_ON
,
504 (unsigned long *)&pi_desc
->control
);
507 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
509 return test_bit(POSTED_INTR_SN
,
510 (unsigned long *)&pi_desc
->control
);
514 struct kvm_vcpu vcpu
;
515 unsigned long host_rsp
;
517 bool nmi_known_unmasked
;
519 u32 idt_vectoring_info
;
521 struct shared_msr_entry
*guest_msrs
;
524 unsigned long host_idt_base
;
526 u64 msr_host_kernel_gs_base
;
527 u64 msr_guest_kernel_gs_base
;
529 u32 vm_entry_controls_shadow
;
530 u32 vm_exit_controls_shadow
;
532 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
533 * non-nested (L1) guest, it always points to vmcs01. For a nested
534 * guest (L2), it points to a different VMCS.
536 struct loaded_vmcs vmcs01
;
537 struct loaded_vmcs
*loaded_vmcs
;
538 bool __launched
; /* temporary, used in vmx_vcpu_run */
539 struct msr_autoload
{
541 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
542 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
546 u16 fs_sel
, gs_sel
, ldt_sel
;
550 int gs_ldt_reload_needed
;
551 int fs_reload_needed
;
552 u64 msr_host_bndcfgs
;
553 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
558 struct kvm_segment segs
[8];
561 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
562 struct kvm_save_segment
{
570 bool emulation_required
;
572 /* Support for vnmi-less CPUs */
573 int soft_vnmi_blocked
;
575 s64 vnmi_blocked_time
;
578 /* Posted interrupt descriptor */
579 struct pi_desc pi_desc
;
581 /* Support for a guest hypervisor (nested VMX) */
582 struct nested_vmx nested
;
584 /* Dynamic PLE window. */
586 bool ple_window_dirty
;
588 /* Support for PML */
589 #define PML_ENTITY_NUM 512
593 enum segment_cache_field
{
602 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
604 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
607 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
609 return &(to_vmx(vcpu
)->pi_desc
);
612 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
613 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
614 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
615 [number##_HIGH] = VMCS12_OFFSET(name)+4
618 static unsigned long shadow_read_only_fields
[] = {
620 * We do NOT shadow fields that are modified when L0
621 * traps and emulates any vmx instruction (e.g. VMPTRLD,
622 * VMXON...) executed by L1.
623 * For example, VM_INSTRUCTION_ERROR is read
624 * by L1 if a vmx instruction fails (part of the error path).
625 * Note the code assumes this logic. If for some reason
626 * we start shadowing these fields then we need to
627 * force a shadow sync when L0 emulates vmx instructions
628 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
629 * by nested_vmx_failValid)
633 VM_EXIT_INSTRUCTION_LEN
,
634 IDT_VECTORING_INFO_FIELD
,
635 IDT_VECTORING_ERROR_CODE
,
636 VM_EXIT_INTR_ERROR_CODE
,
638 GUEST_LINEAR_ADDRESS
,
639 GUEST_PHYSICAL_ADDRESS
641 static int max_shadow_read_only_fields
=
642 ARRAY_SIZE(shadow_read_only_fields
);
644 static unsigned long shadow_read_write_fields
[] = {
651 GUEST_INTERRUPTIBILITY_INFO
,
664 CPU_BASED_VM_EXEC_CONTROL
,
665 VM_ENTRY_EXCEPTION_ERROR_CODE
,
666 VM_ENTRY_INTR_INFO_FIELD
,
667 VM_ENTRY_INSTRUCTION_LEN
,
668 VM_ENTRY_EXCEPTION_ERROR_CODE
,
674 static int max_shadow_read_write_fields
=
675 ARRAY_SIZE(shadow_read_write_fields
);
677 static const unsigned short vmcs_field_to_offset_table
[] = {
678 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
679 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
680 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
681 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
682 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
683 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
684 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
685 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
686 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
687 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
688 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
689 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
690 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
691 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
692 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
693 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
694 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
695 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
696 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
697 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
698 FIELD64(MSR_BITMAP
, msr_bitmap
),
699 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
700 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
701 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
702 FIELD64(TSC_OFFSET
, tsc_offset
),
703 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
704 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
705 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
706 FIELD64(EPT_POINTER
, ept_pointer
),
707 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
708 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
709 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
710 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
711 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
712 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
713 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
714 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
715 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
716 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
717 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
718 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
719 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
720 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
721 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
722 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
723 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
724 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
725 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
726 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
727 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
728 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
729 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
730 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
731 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
732 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
733 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
734 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
735 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
736 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
737 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
738 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
739 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
740 FIELD(TPR_THRESHOLD
, tpr_threshold
),
741 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
742 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
743 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
744 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
745 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
746 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
747 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
748 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
749 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
750 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
751 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
752 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
753 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
754 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
755 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
756 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
757 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
758 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
759 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
760 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
761 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
762 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
763 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
764 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
765 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
766 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
767 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
768 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
769 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
770 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
771 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
772 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
773 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
774 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
775 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
776 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
777 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
778 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
779 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
780 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
781 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
782 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
783 FIELD(GUEST_CR0
, guest_cr0
),
784 FIELD(GUEST_CR3
, guest_cr3
),
785 FIELD(GUEST_CR4
, guest_cr4
),
786 FIELD(GUEST_ES_BASE
, guest_es_base
),
787 FIELD(GUEST_CS_BASE
, guest_cs_base
),
788 FIELD(GUEST_SS_BASE
, guest_ss_base
),
789 FIELD(GUEST_DS_BASE
, guest_ds_base
),
790 FIELD(GUEST_FS_BASE
, guest_fs_base
),
791 FIELD(GUEST_GS_BASE
, guest_gs_base
),
792 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
793 FIELD(GUEST_TR_BASE
, guest_tr_base
),
794 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
795 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
796 FIELD(GUEST_DR7
, guest_dr7
),
797 FIELD(GUEST_RSP
, guest_rsp
),
798 FIELD(GUEST_RIP
, guest_rip
),
799 FIELD(GUEST_RFLAGS
, guest_rflags
),
800 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
801 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
802 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
803 FIELD(HOST_CR0
, host_cr0
),
804 FIELD(HOST_CR3
, host_cr3
),
805 FIELD(HOST_CR4
, host_cr4
),
806 FIELD(HOST_FS_BASE
, host_fs_base
),
807 FIELD(HOST_GS_BASE
, host_gs_base
),
808 FIELD(HOST_TR_BASE
, host_tr_base
),
809 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
810 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
811 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
812 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
813 FIELD(HOST_RSP
, host_rsp
),
814 FIELD(HOST_RIP
, host_rip
),
817 static inline short vmcs_field_to_offset(unsigned long field
)
819 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
821 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
822 vmcs_field_to_offset_table
[field
] == 0)
825 return vmcs_field_to_offset_table
[field
];
828 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
830 return to_vmx(vcpu
)->nested
.current_vmcs12
;
833 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
835 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
836 if (is_error_page(page
))
842 static void nested_release_page(struct page
*page
)
844 kvm_release_page_dirty(page
);
847 static void nested_release_page_clean(struct page
*page
)
849 kvm_release_page_clean(page
);
852 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
853 static u64
construct_eptp(unsigned long root_hpa
);
854 static void kvm_cpu_vmxon(u64 addr
);
855 static void kvm_cpu_vmxoff(void);
856 static bool vmx_mpx_supported(void);
857 static bool vmx_xsaves_supported(void);
858 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
);
859 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
860 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
861 struct kvm_segment
*var
, int seg
);
862 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
863 struct kvm_segment
*var
, int seg
);
864 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
865 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
866 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
867 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
868 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
869 static int alloc_identity_pagetable(struct kvm
*kvm
);
871 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
872 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
874 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
875 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
877 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
878 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
880 static unsigned long *vmx_io_bitmap_a
;
881 static unsigned long *vmx_io_bitmap_b
;
882 static unsigned long *vmx_msr_bitmap_legacy
;
883 static unsigned long *vmx_msr_bitmap_longmode
;
884 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
885 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
886 static unsigned long *vmx_msr_bitmap_nested
;
887 static unsigned long *vmx_vmread_bitmap
;
888 static unsigned long *vmx_vmwrite_bitmap
;
890 static bool cpu_has_load_ia32_efer
;
891 static bool cpu_has_load_perf_global_ctrl
;
893 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
894 static DEFINE_SPINLOCK(vmx_vpid_lock
);
896 static struct vmcs_config
{
900 u32 pin_based_exec_ctrl
;
901 u32 cpu_based_exec_ctrl
;
902 u32 cpu_based_2nd_exec_ctrl
;
907 static struct vmx_capability
{
912 #define VMX_SEGMENT_FIELD(seg) \
913 [VCPU_SREG_##seg] = { \
914 .selector = GUEST_##seg##_SELECTOR, \
915 .base = GUEST_##seg##_BASE, \
916 .limit = GUEST_##seg##_LIMIT, \
917 .ar_bytes = GUEST_##seg##_AR_BYTES, \
920 static const struct kvm_vmx_segment_field
{
925 } kvm_vmx_segment_fields
[] = {
926 VMX_SEGMENT_FIELD(CS
),
927 VMX_SEGMENT_FIELD(DS
),
928 VMX_SEGMENT_FIELD(ES
),
929 VMX_SEGMENT_FIELD(FS
),
930 VMX_SEGMENT_FIELD(GS
),
931 VMX_SEGMENT_FIELD(SS
),
932 VMX_SEGMENT_FIELD(TR
),
933 VMX_SEGMENT_FIELD(LDTR
),
936 static u64 host_efer
;
938 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
941 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
942 * away by decrementing the array size.
944 static const u32 vmx_msr_index
[] = {
946 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
948 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
951 static inline bool is_page_fault(u32 intr_info
)
953 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
954 INTR_INFO_VALID_MASK
)) ==
955 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
958 static inline bool is_no_device(u32 intr_info
)
960 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
961 INTR_INFO_VALID_MASK
)) ==
962 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
965 static inline bool is_invalid_opcode(u32 intr_info
)
967 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
968 INTR_INFO_VALID_MASK
)) ==
969 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
972 static inline bool is_external_interrupt(u32 intr_info
)
974 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
975 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
978 static inline bool is_machine_check(u32 intr_info
)
980 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
981 INTR_INFO_VALID_MASK
)) ==
982 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
985 static inline bool cpu_has_vmx_msr_bitmap(void)
987 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
990 static inline bool cpu_has_vmx_tpr_shadow(void)
992 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
995 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
997 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1000 static inline bool cpu_has_secondary_exec_ctrls(void)
1002 return vmcs_config
.cpu_based_exec_ctrl
&
1003 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1006 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1008 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1009 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1012 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1014 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1015 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1018 static inline bool cpu_has_vmx_apic_register_virt(void)
1020 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1021 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1024 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1026 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1027 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1030 static inline bool cpu_has_vmx_posted_intr(void)
1032 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1033 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1036 static inline bool cpu_has_vmx_apicv(void)
1038 return cpu_has_vmx_apic_register_virt() &&
1039 cpu_has_vmx_virtual_intr_delivery() &&
1040 cpu_has_vmx_posted_intr();
1043 static inline bool cpu_has_vmx_flexpriority(void)
1045 return cpu_has_vmx_tpr_shadow() &&
1046 cpu_has_vmx_virtualize_apic_accesses();
1049 static inline bool cpu_has_vmx_ept_execute_only(void)
1051 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1054 static inline bool cpu_has_vmx_ept_2m_page(void)
1056 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1059 static inline bool cpu_has_vmx_ept_1g_page(void)
1061 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1064 static inline bool cpu_has_vmx_ept_4levels(void)
1066 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1069 static inline bool cpu_has_vmx_ept_ad_bits(void)
1071 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1074 static inline bool cpu_has_vmx_invept_context(void)
1076 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1079 static inline bool cpu_has_vmx_invept_global(void)
1081 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1084 static inline bool cpu_has_vmx_invvpid_single(void)
1086 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1089 static inline bool cpu_has_vmx_invvpid_global(void)
1091 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1094 static inline bool cpu_has_vmx_ept(void)
1096 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1097 SECONDARY_EXEC_ENABLE_EPT
;
1100 static inline bool cpu_has_vmx_unrestricted_guest(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1106 static inline bool cpu_has_vmx_ple(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1112 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1114 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1117 static inline bool cpu_has_vmx_vpid(void)
1119 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1120 SECONDARY_EXEC_ENABLE_VPID
;
1123 static inline bool cpu_has_vmx_rdtscp(void)
1125 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1126 SECONDARY_EXEC_RDTSCP
;
1129 static inline bool cpu_has_vmx_invpcid(void)
1131 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1132 SECONDARY_EXEC_ENABLE_INVPCID
;
1135 static inline bool cpu_has_virtual_nmis(void)
1137 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1140 static inline bool cpu_has_vmx_wbinvd_exit(void)
1142 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1143 SECONDARY_EXEC_WBINVD_EXITING
;
1146 static inline bool cpu_has_vmx_shadow_vmcs(void)
1149 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1150 /* check if the cpu supports writing r/o exit information fields */
1151 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1154 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1155 SECONDARY_EXEC_SHADOW_VMCS
;
1158 static inline bool cpu_has_vmx_pml(void)
1160 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1163 static inline bool report_flexpriority(void)
1165 return flexpriority_enabled
;
1168 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1170 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1173 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1175 return (vmcs12
->cpu_based_vm_exec_control
&
1176 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1177 (vmcs12
->secondary_vm_exec_control
& bit
);
1180 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1182 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1185 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1187 return vmcs12
->pin_based_vm_exec_control
&
1188 PIN_BASED_VMX_PREEMPTION_TIMER
;
1191 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1193 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1196 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1198 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1199 vmx_xsaves_supported();
1202 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1204 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1207 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1209 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1212 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1214 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1217 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1219 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1222 static inline bool is_exception(u32 intr_info
)
1224 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1225 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1228 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1230 unsigned long exit_qualification
);
1231 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1232 struct vmcs12
*vmcs12
,
1233 u32 reason
, unsigned long qualification
);
1235 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1239 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1240 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1245 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1251 } operand
= { vpid
, 0, gva
};
1253 asm volatile (__ex(ASM_VMX_INVVPID
)
1254 /* CF==1 or ZF==1 --> rc = -1 */
1255 "; ja 1f ; ud2 ; 1:"
1256 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1259 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1263 } operand
= {eptp
, gpa
};
1265 asm volatile (__ex(ASM_VMX_INVEPT
)
1266 /* CF==1 or ZF==1 --> rc = -1 */
1267 "; ja 1f ; ud2 ; 1:\n"
1268 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1271 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1275 i
= __find_msr_index(vmx
, msr
);
1277 return &vmx
->guest_msrs
[i
];
1281 static void vmcs_clear(struct vmcs
*vmcs
)
1283 u64 phys_addr
= __pa(vmcs
);
1286 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1287 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1290 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1294 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1296 vmcs_clear(loaded_vmcs
->vmcs
);
1297 loaded_vmcs
->cpu
= -1;
1298 loaded_vmcs
->launched
= 0;
1301 static void vmcs_load(struct vmcs
*vmcs
)
1303 u64 phys_addr
= __pa(vmcs
);
1306 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1307 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1310 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1314 #ifdef CONFIG_KEXEC_CORE
1316 * This bitmap is used to indicate whether the vmclear
1317 * operation is enabled on all cpus. All disabled by
1320 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1322 static inline void crash_enable_local_vmclear(int cpu
)
1324 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1327 static inline void crash_disable_local_vmclear(int cpu
)
1329 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1332 static inline int crash_local_vmclear_enabled(int cpu
)
1334 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1337 static void crash_vmclear_local_loaded_vmcss(void)
1339 int cpu
= raw_smp_processor_id();
1340 struct loaded_vmcs
*v
;
1342 if (!crash_local_vmclear_enabled(cpu
))
1345 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1346 loaded_vmcss_on_cpu_link
)
1347 vmcs_clear(v
->vmcs
);
1350 static inline void crash_enable_local_vmclear(int cpu
) { }
1351 static inline void crash_disable_local_vmclear(int cpu
) { }
1352 #endif /* CONFIG_KEXEC_CORE */
1354 static void __loaded_vmcs_clear(void *arg
)
1356 struct loaded_vmcs
*loaded_vmcs
= arg
;
1357 int cpu
= raw_smp_processor_id();
1359 if (loaded_vmcs
->cpu
!= cpu
)
1360 return; /* vcpu migration can race with cpu offline */
1361 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1362 per_cpu(current_vmcs
, cpu
) = NULL
;
1363 crash_disable_local_vmclear(cpu
);
1364 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1367 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1368 * is before setting loaded_vmcs->vcpu to -1 which is done in
1369 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1370 * then adds the vmcs into percpu list before it is deleted.
1374 loaded_vmcs_init(loaded_vmcs
);
1375 crash_enable_local_vmclear(cpu
);
1378 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1380 int cpu
= loaded_vmcs
->cpu
;
1383 smp_call_function_single(cpu
,
1384 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1387 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1392 if (cpu_has_vmx_invvpid_single())
1393 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1396 static inline void vpid_sync_vcpu_global(void)
1398 if (cpu_has_vmx_invvpid_global())
1399 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1402 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1404 if (cpu_has_vmx_invvpid_single())
1405 vpid_sync_vcpu_single(vmx
);
1407 vpid_sync_vcpu_global();
1410 static inline void ept_sync_global(void)
1412 if (cpu_has_vmx_invept_global())
1413 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1416 static inline void ept_sync_context(u64 eptp
)
1419 if (cpu_has_vmx_invept_context())
1420 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1426 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1428 unsigned long value
;
1430 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1431 : "=a"(value
) : "d"(field
) : "cc");
1435 static __always_inline u16
vmcs_read16(unsigned long field
)
1437 return vmcs_readl(field
);
1440 static __always_inline u32
vmcs_read32(unsigned long field
)
1442 return vmcs_readl(field
);
1445 static __always_inline u64
vmcs_read64(unsigned long field
)
1447 #ifdef CONFIG_X86_64
1448 return vmcs_readl(field
);
1450 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1454 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1456 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1457 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1461 static void vmcs_writel(unsigned long field
, unsigned long value
)
1465 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1466 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1467 if (unlikely(error
))
1468 vmwrite_error(field
, value
);
1471 static void vmcs_write16(unsigned long field
, u16 value
)
1473 vmcs_writel(field
, value
);
1476 static void vmcs_write32(unsigned long field
, u32 value
)
1478 vmcs_writel(field
, value
);
1481 static void vmcs_write64(unsigned long field
, u64 value
)
1483 vmcs_writel(field
, value
);
1484 #ifndef CONFIG_X86_64
1486 vmcs_writel(field
+1, value
>> 32);
1490 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1492 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1495 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1497 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1500 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1502 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1503 vmx
->vm_entry_controls_shadow
= val
;
1506 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1508 if (vmx
->vm_entry_controls_shadow
!= val
)
1509 vm_entry_controls_init(vmx
, val
);
1512 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1514 return vmx
->vm_entry_controls_shadow
;
1518 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1520 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1523 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1525 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1528 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1530 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1531 vmx
->vm_exit_controls_shadow
= val
;
1534 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1536 if (vmx
->vm_exit_controls_shadow
!= val
)
1537 vm_exit_controls_init(vmx
, val
);
1540 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1542 return vmx
->vm_exit_controls_shadow
;
1546 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1548 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1551 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1553 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1556 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1558 vmx
->segment_cache
.bitmask
= 0;
1561 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1565 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1567 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1568 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1569 vmx
->segment_cache
.bitmask
= 0;
1571 ret
= vmx
->segment_cache
.bitmask
& mask
;
1572 vmx
->segment_cache
.bitmask
|= mask
;
1576 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1578 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1580 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1581 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1585 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1587 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1589 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1590 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1594 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1596 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1598 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1599 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1603 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1605 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1607 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1608 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1612 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1616 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1617 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1618 if ((vcpu
->guest_debug
&
1619 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1620 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1621 eb
|= 1u << BP_VECTOR
;
1622 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1625 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1626 if (vcpu
->fpu_active
)
1627 eb
&= ~(1u << NM_VECTOR
);
1629 /* When we are running a nested L2 guest and L1 specified for it a
1630 * certain exception bitmap, we must trap the same exceptions and pass
1631 * them to L1. When running L2, we will only handle the exceptions
1632 * specified above if L1 did not want them.
1634 if (is_guest_mode(vcpu
))
1635 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1637 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1640 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1641 unsigned long entry
, unsigned long exit
)
1643 vm_entry_controls_clearbit(vmx
, entry
);
1644 vm_exit_controls_clearbit(vmx
, exit
);
1647 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1650 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1654 if (cpu_has_load_ia32_efer
) {
1655 clear_atomic_switch_msr_special(vmx
,
1656 VM_ENTRY_LOAD_IA32_EFER
,
1657 VM_EXIT_LOAD_IA32_EFER
);
1661 case MSR_CORE_PERF_GLOBAL_CTRL
:
1662 if (cpu_has_load_perf_global_ctrl
) {
1663 clear_atomic_switch_msr_special(vmx
,
1664 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1665 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1671 for (i
= 0; i
< m
->nr
; ++i
)
1672 if (m
->guest
[i
].index
== msr
)
1678 m
->guest
[i
] = m
->guest
[m
->nr
];
1679 m
->host
[i
] = m
->host
[m
->nr
];
1680 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1681 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1684 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1685 unsigned long entry
, unsigned long exit
,
1686 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1687 u64 guest_val
, u64 host_val
)
1689 vmcs_write64(guest_val_vmcs
, guest_val
);
1690 vmcs_write64(host_val_vmcs
, host_val
);
1691 vm_entry_controls_setbit(vmx
, entry
);
1692 vm_exit_controls_setbit(vmx
, exit
);
1695 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1696 u64 guest_val
, u64 host_val
)
1699 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1703 if (cpu_has_load_ia32_efer
) {
1704 add_atomic_switch_msr_special(vmx
,
1705 VM_ENTRY_LOAD_IA32_EFER
,
1706 VM_EXIT_LOAD_IA32_EFER
,
1709 guest_val
, host_val
);
1713 case MSR_CORE_PERF_GLOBAL_CTRL
:
1714 if (cpu_has_load_perf_global_ctrl
) {
1715 add_atomic_switch_msr_special(vmx
,
1716 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1717 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1718 GUEST_IA32_PERF_GLOBAL_CTRL
,
1719 HOST_IA32_PERF_GLOBAL_CTRL
,
1720 guest_val
, host_val
);
1726 for (i
= 0; i
< m
->nr
; ++i
)
1727 if (m
->guest
[i
].index
== msr
)
1730 if (i
== NR_AUTOLOAD_MSRS
) {
1731 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1732 "Can't add msr %x\n", msr
);
1734 } else if (i
== m
->nr
) {
1736 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1737 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1740 m
->guest
[i
].index
= msr
;
1741 m
->guest
[i
].value
= guest_val
;
1742 m
->host
[i
].index
= msr
;
1743 m
->host
[i
].value
= host_val
;
1746 static void reload_tss(void)
1749 * VT restores TR but not its size. Useless.
1751 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1752 struct desc_struct
*descs
;
1754 descs
= (void *)gdt
->address
;
1755 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1759 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1764 guest_efer
= vmx
->vcpu
.arch
.efer
;
1767 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1770 ignore_bits
= EFER_NX
| EFER_SCE
;
1771 #ifdef CONFIG_X86_64
1772 ignore_bits
|= EFER_LMA
| EFER_LME
;
1773 /* SCE is meaningful only in long mode on Intel */
1774 if (guest_efer
& EFER_LMA
)
1775 ignore_bits
&= ~(u64
)EFER_SCE
;
1777 guest_efer
&= ~ignore_bits
;
1778 guest_efer
|= host_efer
& ignore_bits
;
1779 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1780 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1782 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1785 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1786 * On CPUs that support "load IA32_EFER", always switch EFER
1787 * atomically, since it's faster than switching it manually.
1789 if (cpu_has_load_ia32_efer
||
1790 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1791 guest_efer
= vmx
->vcpu
.arch
.efer
;
1792 if (!(guest_efer
& EFER_LMA
))
1793 guest_efer
&= ~EFER_LME
;
1794 if (guest_efer
!= host_efer
)
1795 add_atomic_switch_msr(vmx
, MSR_EFER
,
1796 guest_efer
, host_efer
);
1803 static unsigned long segment_base(u16 selector
)
1805 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1806 struct desc_struct
*d
;
1807 unsigned long table_base
;
1810 if (!(selector
& ~3))
1813 table_base
= gdt
->address
;
1815 if (selector
& 4) { /* from ldt */
1816 u16 ldt_selector
= kvm_read_ldt();
1818 if (!(ldt_selector
& ~3))
1821 table_base
= segment_base(ldt_selector
);
1823 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1824 v
= get_desc_base(d
);
1825 #ifdef CONFIG_X86_64
1826 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1827 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1832 static inline unsigned long kvm_read_tr_base(void)
1835 asm("str %0" : "=g"(tr
));
1836 return segment_base(tr
);
1839 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1841 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1844 if (vmx
->host_state
.loaded
)
1847 vmx
->host_state
.loaded
= 1;
1849 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1850 * allow segment selectors with cpl > 0 or ti == 1.
1852 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1853 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1854 savesegment(fs
, vmx
->host_state
.fs_sel
);
1855 if (!(vmx
->host_state
.fs_sel
& 7)) {
1856 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1857 vmx
->host_state
.fs_reload_needed
= 0;
1859 vmcs_write16(HOST_FS_SELECTOR
, 0);
1860 vmx
->host_state
.fs_reload_needed
= 1;
1862 savesegment(gs
, vmx
->host_state
.gs_sel
);
1863 if (!(vmx
->host_state
.gs_sel
& 7))
1864 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1866 vmcs_write16(HOST_GS_SELECTOR
, 0);
1867 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1870 #ifdef CONFIG_X86_64
1871 savesegment(ds
, vmx
->host_state
.ds_sel
);
1872 savesegment(es
, vmx
->host_state
.es_sel
);
1875 #ifdef CONFIG_X86_64
1876 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1877 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1879 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1880 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1883 #ifdef CONFIG_X86_64
1884 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1885 if (is_long_mode(&vmx
->vcpu
))
1886 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1888 if (boot_cpu_has(X86_FEATURE_MPX
))
1889 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1890 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1891 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1892 vmx
->guest_msrs
[i
].data
,
1893 vmx
->guest_msrs
[i
].mask
);
1896 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1898 if (!vmx
->host_state
.loaded
)
1901 ++vmx
->vcpu
.stat
.host_state_reload
;
1902 vmx
->host_state
.loaded
= 0;
1903 #ifdef CONFIG_X86_64
1904 if (is_long_mode(&vmx
->vcpu
))
1905 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1907 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1908 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1909 #ifdef CONFIG_X86_64
1910 load_gs_index(vmx
->host_state
.gs_sel
);
1912 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1915 if (vmx
->host_state
.fs_reload_needed
)
1916 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1917 #ifdef CONFIG_X86_64
1918 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1919 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1920 loadsegment(es
, vmx
->host_state
.es_sel
);
1924 #ifdef CONFIG_X86_64
1925 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1927 if (vmx
->host_state
.msr_host_bndcfgs
)
1928 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1930 * If the FPU is not active (through the host task or
1931 * the guest vcpu), then restore the cr0.TS bit.
1933 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
1935 load_gdt(this_cpu_ptr(&host_gdt
));
1938 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1941 __vmx_load_host_state(vmx
);
1946 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1947 * vcpu mutex is already taken.
1949 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1951 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1952 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1955 kvm_cpu_vmxon(phys_addr
);
1956 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1957 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1959 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1960 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1961 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1964 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1965 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1966 unsigned long sysenter_esp
;
1968 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1969 local_irq_disable();
1970 crash_disable_local_vmclear(cpu
);
1973 * Read loaded_vmcs->cpu should be before fetching
1974 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1975 * See the comments in __loaded_vmcs_clear().
1979 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1980 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1981 crash_enable_local_vmclear(cpu
);
1985 * Linux uses per-cpu TSS and GDT, so set these when switching
1988 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1989 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1991 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1992 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1993 vmx
->loaded_vmcs
->cpu
= cpu
;
1997 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1999 __vmx_load_host_state(to_vmx(vcpu
));
2000 if (!vmm_exclusive
) {
2001 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2007 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2011 if (vcpu
->fpu_active
)
2013 vcpu
->fpu_active
= 1;
2014 cr0
= vmcs_readl(GUEST_CR0
);
2015 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2016 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2017 vmcs_writel(GUEST_CR0
, cr0
);
2018 update_exception_bitmap(vcpu
);
2019 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2020 if (is_guest_mode(vcpu
))
2021 vcpu
->arch
.cr0_guest_owned_bits
&=
2022 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2023 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2026 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2029 * Return the cr0 value that a nested guest would read. This is a combination
2030 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2031 * its hypervisor (cr0_read_shadow).
2033 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2035 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2036 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2038 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2040 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2041 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2044 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2046 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2047 * set this *before* calling this function.
2049 vmx_decache_cr0_guest_bits(vcpu
);
2050 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2051 update_exception_bitmap(vcpu
);
2052 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2053 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2054 if (is_guest_mode(vcpu
)) {
2056 * L1's specified read shadow might not contain the TS bit,
2057 * so now that we turned on shadowing of this bit, we need to
2058 * set this bit of the shadow. Like in nested_vmx_run we need
2059 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2060 * up-to-date here because we just decached cr0.TS (and we'll
2061 * only update vmcs12->guest_cr0 on nested exit).
2063 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2064 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2065 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2066 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2068 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2071 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2073 unsigned long rflags
, save_rflags
;
2075 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2076 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2077 rflags
= vmcs_readl(GUEST_RFLAGS
);
2078 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2079 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2080 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2081 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2083 to_vmx(vcpu
)->rflags
= rflags
;
2085 return to_vmx(vcpu
)->rflags
;
2088 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2090 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2091 to_vmx(vcpu
)->rflags
= rflags
;
2092 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2093 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2094 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2096 vmcs_writel(GUEST_RFLAGS
, rflags
);
2099 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2101 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2104 if (interruptibility
& GUEST_INTR_STATE_STI
)
2105 ret
|= KVM_X86_SHADOW_INT_STI
;
2106 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2107 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2112 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2114 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2115 u32 interruptibility
= interruptibility_old
;
2117 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2119 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2120 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2121 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2122 interruptibility
|= GUEST_INTR_STATE_STI
;
2124 if ((interruptibility
!= interruptibility_old
))
2125 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2128 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2132 rip
= kvm_rip_read(vcpu
);
2133 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2134 kvm_rip_write(vcpu
, rip
);
2136 /* skipping an emulated instruction also counts */
2137 vmx_set_interrupt_shadow(vcpu
, 0);
2141 * KVM wants to inject page-faults which it got to the guest. This function
2142 * checks whether in a nested guest, we need to inject them to L1 or L2.
2144 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2146 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2148 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2151 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2152 vmcs_read32(VM_EXIT_INTR_INFO
),
2153 vmcs_readl(EXIT_QUALIFICATION
));
2157 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2158 bool has_error_code
, u32 error_code
,
2161 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2162 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2164 if (!reinject
&& is_guest_mode(vcpu
) &&
2165 nested_vmx_check_exception(vcpu
, nr
))
2168 if (has_error_code
) {
2169 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2170 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2173 if (vmx
->rmode
.vm86_active
) {
2175 if (kvm_exception_is_soft(nr
))
2176 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2177 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2178 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2182 if (kvm_exception_is_soft(nr
)) {
2183 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2184 vmx
->vcpu
.arch
.event_exit_inst_len
);
2185 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2187 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2189 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2192 static bool vmx_rdtscp_supported(void)
2194 return cpu_has_vmx_rdtscp();
2197 static bool vmx_invpcid_supported(void)
2199 return cpu_has_vmx_invpcid() && enable_ept
;
2203 * Swap MSR entry in host/guest MSR entry array.
2205 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2207 struct shared_msr_entry tmp
;
2209 tmp
= vmx
->guest_msrs
[to
];
2210 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2211 vmx
->guest_msrs
[from
] = tmp
;
2214 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2216 unsigned long *msr_bitmap
;
2218 if (is_guest_mode(vcpu
))
2219 msr_bitmap
= vmx_msr_bitmap_nested
;
2220 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2221 if (is_long_mode(vcpu
))
2222 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2224 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2226 if (is_long_mode(vcpu
))
2227 msr_bitmap
= vmx_msr_bitmap_longmode
;
2229 msr_bitmap
= vmx_msr_bitmap_legacy
;
2232 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2236 * Set up the vmcs to automatically save and restore system
2237 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2238 * mode, as fiddling with msrs is very expensive.
2240 static void setup_msrs(struct vcpu_vmx
*vmx
)
2242 int save_nmsrs
, index
;
2245 #ifdef CONFIG_X86_64
2246 if (is_long_mode(&vmx
->vcpu
)) {
2247 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2249 move_msr_up(vmx
, index
, save_nmsrs
++);
2250 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2252 move_msr_up(vmx
, index
, save_nmsrs
++);
2253 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2255 move_msr_up(vmx
, index
, save_nmsrs
++);
2256 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2257 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2258 move_msr_up(vmx
, index
, save_nmsrs
++);
2260 * MSR_STAR is only needed on long mode guests, and only
2261 * if efer.sce is enabled.
2263 index
= __find_msr_index(vmx
, MSR_STAR
);
2264 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2265 move_msr_up(vmx
, index
, save_nmsrs
++);
2268 index
= __find_msr_index(vmx
, MSR_EFER
);
2269 if (index
>= 0 && update_transition_efer(vmx
, index
))
2270 move_msr_up(vmx
, index
, save_nmsrs
++);
2272 vmx
->save_nmsrs
= save_nmsrs
;
2274 if (cpu_has_vmx_msr_bitmap())
2275 vmx_set_msr_bitmap(&vmx
->vcpu
);
2279 * reads and returns guest's timestamp counter "register"
2280 * guest_tsc = host_tsc + tsc_offset -- 21.3
2282 static u64
guest_read_tsc(void)
2284 u64 host_tsc
, tsc_offset
;
2287 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2288 return host_tsc
+ tsc_offset
;
2292 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2293 * counter, even if a nested guest (L2) is currently running.
2295 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2299 tsc_offset
= is_guest_mode(vcpu
) ?
2300 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2301 vmcs_read64(TSC_OFFSET
);
2302 return host_tsc
+ tsc_offset
;
2306 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2307 * software catchup for faster rates on slower CPUs.
2309 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2314 if (user_tsc_khz
> tsc_khz
) {
2315 vcpu
->arch
.tsc_catchup
= 1;
2316 vcpu
->arch
.tsc_always_catchup
= 1;
2318 WARN(1, "user requested TSC rate below hardware speed\n");
2321 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2323 return vmcs_read64(TSC_OFFSET
);
2327 * writes 'offset' into guest's timestamp counter offset register
2329 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2331 if (is_guest_mode(vcpu
)) {
2333 * We're here if L1 chose not to trap WRMSR to TSC. According
2334 * to the spec, this should set L1's TSC; The offset that L1
2335 * set for L2 remains unchanged, and still needs to be added
2336 * to the newly set TSC to get L2's TSC.
2338 struct vmcs12
*vmcs12
;
2339 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2340 /* recalculate vmcs02.TSC_OFFSET: */
2341 vmcs12
= get_vmcs12(vcpu
);
2342 vmcs_write64(TSC_OFFSET
, offset
+
2343 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2344 vmcs12
->tsc_offset
: 0));
2346 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2347 vmcs_read64(TSC_OFFSET
), offset
);
2348 vmcs_write64(TSC_OFFSET
, offset
);
2352 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2354 u64 offset
= vmcs_read64(TSC_OFFSET
);
2356 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2357 if (is_guest_mode(vcpu
)) {
2358 /* Even when running L2, the adjustment needs to apply to L1 */
2359 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2361 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2362 offset
+ adjustment
);
2365 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2367 return target_tsc
- rdtsc();
2370 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2372 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2373 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2377 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2378 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2379 * all guests if the "nested" module option is off, and can also be disabled
2380 * for a single guest by disabling its VMX cpuid bit.
2382 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2384 return nested
&& guest_cpuid_has_vmx(vcpu
);
2388 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2389 * returned for the various VMX controls MSRs when nested VMX is enabled.
2390 * The same values should also be used to verify that vmcs12 control fields are
2391 * valid during nested entry from L1 to L2.
2392 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2393 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2394 * bit in the high half is on if the corresponding bit in the control field
2395 * may be on. See also vmx_control_verify().
2397 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2400 * Note that as a general rule, the high half of the MSRs (bits in
2401 * the control fields which may be 1) should be initialized by the
2402 * intersection of the underlying hardware's MSR (i.e., features which
2403 * can be supported) and the list of features we want to expose -
2404 * because they are known to be properly supported in our code.
2405 * Also, usually, the low half of the MSRs (bits which must be 1) can
2406 * be set to 0, meaning that L1 may turn off any of these bits. The
2407 * reason is that if one of these bits is necessary, it will appear
2408 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2409 * fields of vmcs01 and vmcs02, will turn these bits off - and
2410 * nested_vmx_exit_handled() will not pass related exits to L1.
2411 * These rules have exceptions below.
2414 /* pin-based controls */
2415 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2416 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2417 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2418 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2419 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2420 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2421 PIN_BASED_EXT_INTR_MASK
|
2422 PIN_BASED_NMI_EXITING
|
2423 PIN_BASED_VIRTUAL_NMIS
;
2424 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2425 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2426 PIN_BASED_VMX_PREEMPTION_TIMER
;
2427 if (vmx_cpu_uses_apicv(&vmx
->vcpu
))
2428 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2429 PIN_BASED_POSTED_INTR
;
2432 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2433 vmx
->nested
.nested_vmx_exit_ctls_low
,
2434 vmx
->nested
.nested_vmx_exit_ctls_high
);
2435 vmx
->nested
.nested_vmx_exit_ctls_low
=
2436 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2438 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2439 #ifdef CONFIG_X86_64
2440 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2442 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2443 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2444 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2445 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2446 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2448 if (vmx_mpx_supported())
2449 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2451 /* We support free control of debug control saving. */
2452 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2453 vmx
->nested
.nested_vmx_exit_ctls_low
&
2454 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2456 /* entry controls */
2457 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2458 vmx
->nested
.nested_vmx_entry_ctls_low
,
2459 vmx
->nested
.nested_vmx_entry_ctls_high
);
2460 vmx
->nested
.nested_vmx_entry_ctls_low
=
2461 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2462 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2463 #ifdef CONFIG_X86_64
2464 VM_ENTRY_IA32E_MODE
|
2466 VM_ENTRY_LOAD_IA32_PAT
;
2467 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2468 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2469 if (vmx_mpx_supported())
2470 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2472 /* We support free control of debug control loading. */
2473 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2474 vmx
->nested
.nested_vmx_entry_ctls_low
&
2475 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2477 /* cpu-based controls */
2478 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2479 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2480 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2481 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2482 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2483 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2484 CPU_BASED_VIRTUAL_INTR_PENDING
|
2485 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2486 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2487 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2488 CPU_BASED_CR3_STORE_EXITING
|
2489 #ifdef CONFIG_X86_64
2490 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2492 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2493 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2494 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2495 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2496 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2498 * We can allow some features even when not supported by the
2499 * hardware. For example, L1 can specify an MSR bitmap - and we
2500 * can use it to avoid exits to L1 - even when L0 runs L2
2501 * without MSR bitmaps.
2503 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2504 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2505 CPU_BASED_USE_MSR_BITMAPS
;
2507 /* We support free control of CR3 access interception. */
2508 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2509 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2510 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2512 /* secondary cpu-based controls */
2513 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2514 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2515 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2516 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2517 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2518 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2519 SECONDARY_EXEC_RDTSCP
|
2520 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2521 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2522 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2523 SECONDARY_EXEC_WBINVD_EXITING
|
2524 SECONDARY_EXEC_XSAVES
|
2525 SECONDARY_EXEC_PCOMMIT
;
2528 /* nested EPT: emulate EPT also to L1 */
2529 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2530 SECONDARY_EXEC_ENABLE_EPT
;
2531 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2532 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2534 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2536 * For nested guests, we don't do anything specific
2537 * for single context invalidation. Hence, only advertise
2538 * support for global context invalidation.
2540 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2542 vmx
->nested
.nested_vmx_ept_caps
= 0;
2544 if (enable_unrestricted_guest
)
2545 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2546 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2548 /* miscellaneous data */
2549 rdmsr(MSR_IA32_VMX_MISC
,
2550 vmx
->nested
.nested_vmx_misc_low
,
2551 vmx
->nested
.nested_vmx_misc_high
);
2552 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2553 vmx
->nested
.nested_vmx_misc_low
|=
2554 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2555 VMX_MISC_ACTIVITY_HLT
;
2556 vmx
->nested
.nested_vmx_misc_high
= 0;
2559 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2562 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2564 return ((control
& high
) | low
) == control
;
2567 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2569 return low
| ((u64
)high
<< 32);
2572 /* Returns 0 on success, non-0 otherwise. */
2573 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2575 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2577 switch (msr_index
) {
2578 case MSR_IA32_VMX_BASIC
:
2580 * This MSR reports some information about VMX support. We
2581 * should return information about the VMX we emulate for the
2582 * guest, and the VMCS structure we give it - not about the
2583 * VMX support of the underlying hardware.
2585 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2586 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2587 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2589 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2590 case MSR_IA32_VMX_PINBASED_CTLS
:
2591 *pdata
= vmx_control_msr(
2592 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2593 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2595 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2596 *pdata
= vmx_control_msr(
2597 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2598 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2600 case MSR_IA32_VMX_PROCBASED_CTLS
:
2601 *pdata
= vmx_control_msr(
2602 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2603 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2605 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2606 *pdata
= vmx_control_msr(
2607 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2608 vmx
->nested
.nested_vmx_exit_ctls_high
);
2610 case MSR_IA32_VMX_EXIT_CTLS
:
2611 *pdata
= vmx_control_msr(
2612 vmx
->nested
.nested_vmx_exit_ctls_low
,
2613 vmx
->nested
.nested_vmx_exit_ctls_high
);
2615 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2616 *pdata
= vmx_control_msr(
2617 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2618 vmx
->nested
.nested_vmx_entry_ctls_high
);
2620 case MSR_IA32_VMX_ENTRY_CTLS
:
2621 *pdata
= vmx_control_msr(
2622 vmx
->nested
.nested_vmx_entry_ctls_low
,
2623 vmx
->nested
.nested_vmx_entry_ctls_high
);
2625 case MSR_IA32_VMX_MISC
:
2626 *pdata
= vmx_control_msr(
2627 vmx
->nested
.nested_vmx_misc_low
,
2628 vmx
->nested
.nested_vmx_misc_high
);
2631 * These MSRs specify bits which the guest must keep fixed (on or off)
2632 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2633 * We picked the standard core2 setting.
2635 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2636 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2637 case MSR_IA32_VMX_CR0_FIXED0
:
2638 *pdata
= VMXON_CR0_ALWAYSON
;
2640 case MSR_IA32_VMX_CR0_FIXED1
:
2643 case MSR_IA32_VMX_CR4_FIXED0
:
2644 *pdata
= VMXON_CR4_ALWAYSON
;
2646 case MSR_IA32_VMX_CR4_FIXED1
:
2649 case MSR_IA32_VMX_VMCS_ENUM
:
2650 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2652 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2653 *pdata
= vmx_control_msr(
2654 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2655 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2657 case MSR_IA32_VMX_EPT_VPID_CAP
:
2658 /* Currently, no nested vpid support */
2659 *pdata
= vmx
->nested
.nested_vmx_ept_caps
;
2669 * Reads an msr value (of 'msr_index') into 'pdata'.
2670 * Returns 0 on success, non-0 otherwise.
2671 * Assumes vcpu_load() was already called.
2673 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2675 struct shared_msr_entry
*msr
;
2677 switch (msr_info
->index
) {
2678 #ifdef CONFIG_X86_64
2680 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2683 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2685 case MSR_KERNEL_GS_BASE
:
2686 vmx_load_host_state(to_vmx(vcpu
));
2687 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2691 return kvm_get_msr_common(vcpu
, msr_info
);
2693 msr_info
->data
= guest_read_tsc();
2695 case MSR_IA32_SYSENTER_CS
:
2696 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2698 case MSR_IA32_SYSENTER_EIP
:
2699 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2701 case MSR_IA32_SYSENTER_ESP
:
2702 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2704 case MSR_IA32_BNDCFGS
:
2705 if (!vmx_mpx_supported())
2707 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2709 case MSR_IA32_FEATURE_CONTROL
:
2710 if (!nested_vmx_allowed(vcpu
))
2712 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2714 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2715 if (!nested_vmx_allowed(vcpu
))
2717 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2719 if (!vmx_xsaves_supported())
2721 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2724 if (!guest_cpuid_has_rdtscp(vcpu
))
2726 /* Otherwise falls through */
2728 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2730 msr_info
->data
= msr
->data
;
2733 return kvm_get_msr_common(vcpu
, msr_info
);
2739 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2742 * Writes msr value into into the appropriate "register".
2743 * Returns 0 on success, non-0 otherwise.
2744 * Assumes vcpu_load() was already called.
2746 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2748 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2749 struct shared_msr_entry
*msr
;
2751 u32 msr_index
= msr_info
->index
;
2752 u64 data
= msr_info
->data
;
2754 switch (msr_index
) {
2756 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2758 #ifdef CONFIG_X86_64
2760 vmx_segment_cache_clear(vmx
);
2761 vmcs_writel(GUEST_FS_BASE
, data
);
2764 vmx_segment_cache_clear(vmx
);
2765 vmcs_writel(GUEST_GS_BASE
, data
);
2767 case MSR_KERNEL_GS_BASE
:
2768 vmx_load_host_state(vmx
);
2769 vmx
->msr_guest_kernel_gs_base
= data
;
2772 case MSR_IA32_SYSENTER_CS
:
2773 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2775 case MSR_IA32_SYSENTER_EIP
:
2776 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2778 case MSR_IA32_SYSENTER_ESP
:
2779 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2781 case MSR_IA32_BNDCFGS
:
2782 if (!vmx_mpx_supported())
2784 vmcs_write64(GUEST_BNDCFGS
, data
);
2787 kvm_write_tsc(vcpu
, msr_info
);
2789 case MSR_IA32_CR_PAT
:
2790 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2791 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2793 vmcs_write64(GUEST_IA32_PAT
, data
);
2794 vcpu
->arch
.pat
= data
;
2797 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2799 case MSR_IA32_TSC_ADJUST
:
2800 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2802 case MSR_IA32_FEATURE_CONTROL
:
2803 if (!nested_vmx_allowed(vcpu
) ||
2804 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2805 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2807 vmx
->nested
.msr_ia32_feature_control
= data
;
2808 if (msr_info
->host_initiated
&& data
== 0)
2809 vmx_leave_nested(vcpu
);
2811 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2812 return 1; /* they are read-only */
2814 if (!vmx_xsaves_supported())
2817 * The only supported bit as of Skylake is bit 8, but
2818 * it is not supported on KVM.
2822 vcpu
->arch
.ia32_xss
= data
;
2823 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2824 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2825 vcpu
->arch
.ia32_xss
, host_xss
);
2827 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2830 if (!guest_cpuid_has_rdtscp(vcpu
))
2832 /* Check reserved bit, higher 32 bits should be zero */
2833 if ((data
>> 32) != 0)
2835 /* Otherwise falls through */
2837 msr
= find_msr_entry(vmx
, msr_index
);
2839 u64 old_msr_data
= msr
->data
;
2841 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2843 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2847 msr
->data
= old_msr_data
;
2851 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2857 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2859 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2862 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2865 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2867 case VCPU_EXREG_PDPTR
:
2869 ept_save_pdptrs(vcpu
);
2876 static __init
int cpu_has_kvm_support(void)
2878 return cpu_has_vmx();
2881 static __init
int vmx_disabled_by_bios(void)
2885 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2886 if (msr
& FEATURE_CONTROL_LOCKED
) {
2887 /* launched w/ TXT and VMX disabled */
2888 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2891 /* launched w/o TXT and VMX only enabled w/ TXT */
2892 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2893 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2894 && !tboot_enabled()) {
2895 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2896 "activate TXT before enabling KVM\n");
2899 /* launched w/o TXT and VMX disabled */
2900 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2901 && !tboot_enabled())
2908 static void kvm_cpu_vmxon(u64 addr
)
2910 asm volatile (ASM_VMX_VMXON_RAX
2911 : : "a"(&addr
), "m"(addr
)
2915 static int hardware_enable(void)
2917 int cpu
= raw_smp_processor_id();
2918 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2921 if (cr4_read_shadow() & X86_CR4_VMXE
)
2924 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2927 * Now we can enable the vmclear operation in kdump
2928 * since the loaded_vmcss_on_cpu list on this cpu
2929 * has been initialized.
2931 * Though the cpu is not in VMX operation now, there
2932 * is no problem to enable the vmclear operation
2933 * for the loaded_vmcss_on_cpu list is empty!
2935 crash_enable_local_vmclear(cpu
);
2937 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2939 test_bits
= FEATURE_CONTROL_LOCKED
;
2940 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2941 if (tboot_enabled())
2942 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2944 if ((old
& test_bits
) != test_bits
) {
2945 /* enable and lock */
2946 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2948 cr4_set_bits(X86_CR4_VMXE
);
2950 if (vmm_exclusive
) {
2951 kvm_cpu_vmxon(phys_addr
);
2955 native_store_gdt(this_cpu_ptr(&host_gdt
));
2960 static void vmclear_local_loaded_vmcss(void)
2962 int cpu
= raw_smp_processor_id();
2963 struct loaded_vmcs
*v
, *n
;
2965 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2966 loaded_vmcss_on_cpu_link
)
2967 __loaded_vmcs_clear(v
);
2971 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2974 static void kvm_cpu_vmxoff(void)
2976 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2979 static void hardware_disable(void)
2981 if (vmm_exclusive
) {
2982 vmclear_local_loaded_vmcss();
2985 cr4_clear_bits(X86_CR4_VMXE
);
2988 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2989 u32 msr
, u32
*result
)
2991 u32 vmx_msr_low
, vmx_msr_high
;
2992 u32 ctl
= ctl_min
| ctl_opt
;
2994 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2996 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2997 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2999 /* Ensure minimum (required) set of control bits are supported. */
3007 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3009 u32 vmx_msr_low
, vmx_msr_high
;
3011 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3012 return vmx_msr_high
& ctl
;
3015 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3017 u32 vmx_msr_low
, vmx_msr_high
;
3018 u32 min
, opt
, min2
, opt2
;
3019 u32 _pin_based_exec_control
= 0;
3020 u32 _cpu_based_exec_control
= 0;
3021 u32 _cpu_based_2nd_exec_control
= 0;
3022 u32 _vmexit_control
= 0;
3023 u32 _vmentry_control
= 0;
3025 min
= CPU_BASED_HLT_EXITING
|
3026 #ifdef CONFIG_X86_64
3027 CPU_BASED_CR8_LOAD_EXITING
|
3028 CPU_BASED_CR8_STORE_EXITING
|
3030 CPU_BASED_CR3_LOAD_EXITING
|
3031 CPU_BASED_CR3_STORE_EXITING
|
3032 CPU_BASED_USE_IO_BITMAPS
|
3033 CPU_BASED_MOV_DR_EXITING
|
3034 CPU_BASED_USE_TSC_OFFSETING
|
3035 CPU_BASED_MWAIT_EXITING
|
3036 CPU_BASED_MONITOR_EXITING
|
3037 CPU_BASED_INVLPG_EXITING
|
3038 CPU_BASED_RDPMC_EXITING
;
3040 opt
= CPU_BASED_TPR_SHADOW
|
3041 CPU_BASED_USE_MSR_BITMAPS
|
3042 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3043 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3044 &_cpu_based_exec_control
) < 0)
3046 #ifdef CONFIG_X86_64
3047 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3048 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3049 ~CPU_BASED_CR8_STORE_EXITING
;
3051 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3053 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3054 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3055 SECONDARY_EXEC_WBINVD_EXITING
|
3056 SECONDARY_EXEC_ENABLE_VPID
|
3057 SECONDARY_EXEC_ENABLE_EPT
|
3058 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3059 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3060 SECONDARY_EXEC_RDTSCP
|
3061 SECONDARY_EXEC_ENABLE_INVPCID
|
3062 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3063 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3064 SECONDARY_EXEC_SHADOW_VMCS
|
3065 SECONDARY_EXEC_XSAVES
|
3066 SECONDARY_EXEC_ENABLE_PML
|
3067 SECONDARY_EXEC_PCOMMIT
;
3068 if (adjust_vmx_controls(min2
, opt2
,
3069 MSR_IA32_VMX_PROCBASED_CTLS2
,
3070 &_cpu_based_2nd_exec_control
) < 0)
3073 #ifndef CONFIG_X86_64
3074 if (!(_cpu_based_2nd_exec_control
&
3075 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3076 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3079 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3080 _cpu_based_2nd_exec_control
&= ~(
3081 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3082 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3083 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3085 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3086 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3088 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3089 CPU_BASED_CR3_STORE_EXITING
|
3090 CPU_BASED_INVLPG_EXITING
);
3091 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3092 vmx_capability
.ept
, vmx_capability
.vpid
);
3095 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3096 #ifdef CONFIG_X86_64
3097 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3099 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3100 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3101 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3102 &_vmexit_control
) < 0)
3105 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3106 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3107 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3108 &_pin_based_exec_control
) < 0)
3111 if (!(_cpu_based_2nd_exec_control
&
3112 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3113 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3114 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3116 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3117 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3118 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3119 &_vmentry_control
) < 0)
3122 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3124 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3125 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3128 #ifdef CONFIG_X86_64
3129 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3130 if (vmx_msr_high
& (1u<<16))
3134 /* Require Write-Back (WB) memory type for VMCS accesses. */
3135 if (((vmx_msr_high
>> 18) & 15) != 6)
3138 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3139 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3140 vmcs_conf
->revision_id
= vmx_msr_low
;
3142 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3143 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3144 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3145 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3146 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3148 cpu_has_load_ia32_efer
=
3149 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3150 VM_ENTRY_LOAD_IA32_EFER
)
3151 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3152 VM_EXIT_LOAD_IA32_EFER
);
3154 cpu_has_load_perf_global_ctrl
=
3155 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3156 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3157 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3158 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3161 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3162 * but due to arrata below it can't be used. Workaround is to use
3163 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3165 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3170 * BC86,AAY89,BD102 (model 44)
3174 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3175 switch (boot_cpu_data
.x86_model
) {
3181 cpu_has_load_perf_global_ctrl
= false;
3182 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3183 "does not work properly. Using workaround\n");
3191 rdmsrl(MSR_IA32_XSS
, host_xss
);
3196 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3198 int node
= cpu_to_node(cpu
);
3202 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3205 vmcs
= page_address(pages
);
3206 memset(vmcs
, 0, vmcs_config
.size
);
3207 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3211 static struct vmcs
*alloc_vmcs(void)
3213 return alloc_vmcs_cpu(raw_smp_processor_id());
3216 static void free_vmcs(struct vmcs
*vmcs
)
3218 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3222 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3224 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3226 if (!loaded_vmcs
->vmcs
)
3228 loaded_vmcs_clear(loaded_vmcs
);
3229 free_vmcs(loaded_vmcs
->vmcs
);
3230 loaded_vmcs
->vmcs
= NULL
;
3233 static void free_kvm_area(void)
3237 for_each_possible_cpu(cpu
) {
3238 free_vmcs(per_cpu(vmxarea
, cpu
));
3239 per_cpu(vmxarea
, cpu
) = NULL
;
3243 static void init_vmcs_shadow_fields(void)
3247 /* No checks for read only fields yet */
3249 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3250 switch (shadow_read_write_fields
[i
]) {
3252 if (!vmx_mpx_supported())
3260 shadow_read_write_fields
[j
] =
3261 shadow_read_write_fields
[i
];
3264 max_shadow_read_write_fields
= j
;
3266 /* shadowed fields guest access without vmexit */
3267 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3268 clear_bit(shadow_read_write_fields
[i
],
3269 vmx_vmwrite_bitmap
);
3270 clear_bit(shadow_read_write_fields
[i
],
3273 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3274 clear_bit(shadow_read_only_fields
[i
],
3278 static __init
int alloc_kvm_area(void)
3282 for_each_possible_cpu(cpu
) {
3285 vmcs
= alloc_vmcs_cpu(cpu
);
3291 per_cpu(vmxarea
, cpu
) = vmcs
;
3296 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3298 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3301 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3302 struct kvm_segment
*save
)
3304 if (!emulate_invalid_guest_state
) {
3306 * CS and SS RPL should be equal during guest entry according
3307 * to VMX spec, but in reality it is not always so. Since vcpu
3308 * is in the middle of the transition from real mode to
3309 * protected mode it is safe to assume that RPL 0 is a good
3312 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3313 save
->selector
&= ~SEGMENT_RPL_MASK
;
3314 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3317 vmx_set_segment(vcpu
, save
, seg
);
3320 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3322 unsigned long flags
;
3323 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3326 * Update real mode segment cache. It may be not up-to-date if sement
3327 * register was written while vcpu was in a guest mode.
3329 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3330 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3331 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3332 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3333 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3334 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3336 vmx
->rmode
.vm86_active
= 0;
3338 vmx_segment_cache_clear(vmx
);
3340 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3342 flags
= vmcs_readl(GUEST_RFLAGS
);
3343 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3344 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3345 vmcs_writel(GUEST_RFLAGS
, flags
);
3347 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3348 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3350 update_exception_bitmap(vcpu
);
3352 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3353 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3354 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3355 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3356 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3357 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3360 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3362 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3363 struct kvm_segment var
= *save
;
3366 if (seg
== VCPU_SREG_CS
)
3369 if (!emulate_invalid_guest_state
) {
3370 var
.selector
= var
.base
>> 4;
3371 var
.base
= var
.base
& 0xffff0;
3381 if (save
->base
& 0xf)
3382 printk_once(KERN_WARNING
"kvm: segment base is not "
3383 "paragraph aligned when entering "
3384 "protected mode (seg=%d)", seg
);
3387 vmcs_write16(sf
->selector
, var
.selector
);
3388 vmcs_write32(sf
->base
, var
.base
);
3389 vmcs_write32(sf
->limit
, var
.limit
);
3390 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3393 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3395 unsigned long flags
;
3396 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3398 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3399 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3400 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3401 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3402 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3403 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3404 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3406 vmx
->rmode
.vm86_active
= 1;
3409 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3410 * vcpu. Warn the user that an update is overdue.
3412 if (!vcpu
->kvm
->arch
.tss_addr
)
3413 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3414 "called before entering vcpu\n");
3416 vmx_segment_cache_clear(vmx
);
3418 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3419 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3420 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3422 flags
= vmcs_readl(GUEST_RFLAGS
);
3423 vmx
->rmode
.save_rflags
= flags
;
3425 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3427 vmcs_writel(GUEST_RFLAGS
, flags
);
3428 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3429 update_exception_bitmap(vcpu
);
3431 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3432 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3433 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3434 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3435 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3436 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3438 kvm_mmu_reset_context(vcpu
);
3441 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3443 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3444 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3450 * Force kernel_gs_base reloading before EFER changes, as control
3451 * of this msr depends on is_long_mode().
3453 vmx_load_host_state(to_vmx(vcpu
));
3454 vcpu
->arch
.efer
= efer
;
3455 if (efer
& EFER_LMA
) {
3456 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3459 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3461 msr
->data
= efer
& ~EFER_LME
;
3466 #ifdef CONFIG_X86_64
3468 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3472 vmx_segment_cache_clear(to_vmx(vcpu
));
3474 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3475 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3476 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3478 vmcs_write32(GUEST_TR_AR_BYTES
,
3479 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3480 | VMX_AR_TYPE_BUSY_64_TSS
);
3482 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3485 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3487 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3488 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3493 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3495 vpid_sync_context(to_vmx(vcpu
));
3497 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3499 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3503 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3505 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3507 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3508 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3511 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3513 if (enable_ept
&& is_paging(vcpu
))
3514 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3515 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3518 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3520 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3522 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3523 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3526 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3528 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3530 if (!test_bit(VCPU_EXREG_PDPTR
,
3531 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3534 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3535 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3536 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3537 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3538 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3542 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3544 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3546 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3547 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3548 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3549 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3550 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3553 __set_bit(VCPU_EXREG_PDPTR
,
3554 (unsigned long *)&vcpu
->arch
.regs_avail
);
3555 __set_bit(VCPU_EXREG_PDPTR
,
3556 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3559 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3561 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3563 struct kvm_vcpu
*vcpu
)
3565 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3566 vmx_decache_cr3(vcpu
);
3567 if (!(cr0
& X86_CR0_PG
)) {
3568 /* From paging/starting to nonpaging */
3569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3570 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3571 (CPU_BASED_CR3_LOAD_EXITING
|
3572 CPU_BASED_CR3_STORE_EXITING
));
3573 vcpu
->arch
.cr0
= cr0
;
3574 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3575 } else if (!is_paging(vcpu
)) {
3576 /* From nonpaging to paging */
3577 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3578 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3579 ~(CPU_BASED_CR3_LOAD_EXITING
|
3580 CPU_BASED_CR3_STORE_EXITING
));
3581 vcpu
->arch
.cr0
= cr0
;
3582 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3585 if (!(cr0
& X86_CR0_WP
))
3586 *hw_cr0
&= ~X86_CR0_WP
;
3589 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3591 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3592 unsigned long hw_cr0
;
3594 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3595 if (enable_unrestricted_guest
)
3596 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3598 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3600 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3603 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3607 #ifdef CONFIG_X86_64
3608 if (vcpu
->arch
.efer
& EFER_LME
) {
3609 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3611 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3617 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3619 if (!vcpu
->fpu_active
)
3620 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3622 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3623 vmcs_writel(GUEST_CR0
, hw_cr0
);
3624 vcpu
->arch
.cr0
= cr0
;
3626 /* depends on vcpu->arch.cr0 to be set to a new value */
3627 vmx
->emulation_required
= emulation_required(vcpu
);
3630 static u64
construct_eptp(unsigned long root_hpa
)
3634 /* TODO write the value reading from MSR */
3635 eptp
= VMX_EPT_DEFAULT_MT
|
3636 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3637 if (enable_ept_ad_bits
)
3638 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3639 eptp
|= (root_hpa
& PAGE_MASK
);
3644 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3646 unsigned long guest_cr3
;
3651 eptp
= construct_eptp(cr3
);
3652 vmcs_write64(EPT_POINTER
, eptp
);
3653 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3654 guest_cr3
= kvm_read_cr3(vcpu
);
3656 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3657 ept_load_pdptrs(vcpu
);
3660 vmx_flush_tlb(vcpu
);
3661 vmcs_writel(GUEST_CR3
, guest_cr3
);
3664 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3667 * Pass through host's Machine Check Enable value to hw_cr4, which
3668 * is in force while we are in guest mode. Do not let guests control
3669 * this bit, even if host CR4.MCE == 0.
3671 unsigned long hw_cr4
=
3672 (cr4_read_shadow() & X86_CR4_MCE
) |
3673 (cr4
& ~X86_CR4_MCE
) |
3674 (to_vmx(vcpu
)->rmode
.vm86_active
?
3675 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3677 if (cr4
& X86_CR4_VMXE
) {
3679 * To use VMXON (and later other VMX instructions), a guest
3680 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3681 * So basically the check on whether to allow nested VMX
3684 if (!nested_vmx_allowed(vcpu
))
3687 if (to_vmx(vcpu
)->nested
.vmxon
&&
3688 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3691 vcpu
->arch
.cr4
= cr4
;
3693 if (!is_paging(vcpu
)) {
3694 hw_cr4
&= ~X86_CR4_PAE
;
3695 hw_cr4
|= X86_CR4_PSE
;
3697 * SMEP/SMAP is disabled if CPU is in non-paging mode
3698 * in hardware. However KVM always uses paging mode to
3699 * emulate guest non-paging mode with TDP.
3700 * To emulate this behavior, SMEP/SMAP needs to be
3701 * manually disabled when guest switches to non-paging
3704 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3705 } else if (!(cr4
& X86_CR4_PAE
)) {
3706 hw_cr4
&= ~X86_CR4_PAE
;
3710 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3711 vmcs_writel(GUEST_CR4
, hw_cr4
);
3715 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3716 struct kvm_segment
*var
, int seg
)
3718 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3721 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3722 *var
= vmx
->rmode
.segs
[seg
];
3723 if (seg
== VCPU_SREG_TR
3724 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3726 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3727 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3730 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3731 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3732 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3733 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3734 var
->unusable
= (ar
>> 16) & 1;
3735 var
->type
= ar
& 15;
3736 var
->s
= (ar
>> 4) & 1;
3737 var
->dpl
= (ar
>> 5) & 3;
3739 * Some userspaces do not preserve unusable property. Since usable
3740 * segment has to be present according to VMX spec we can use present
3741 * property to amend userspace bug by making unusable segment always
3742 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3743 * segment as unusable.
3745 var
->present
= !var
->unusable
;
3746 var
->avl
= (ar
>> 12) & 1;
3747 var
->l
= (ar
>> 13) & 1;
3748 var
->db
= (ar
>> 14) & 1;
3749 var
->g
= (ar
>> 15) & 1;
3752 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3754 struct kvm_segment s
;
3756 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3757 vmx_get_segment(vcpu
, &s
, seg
);
3760 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3763 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3765 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3767 if (unlikely(vmx
->rmode
.vm86_active
))
3770 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3771 return VMX_AR_DPL(ar
);
3775 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3779 if (var
->unusable
|| !var
->present
)
3782 ar
= var
->type
& 15;
3783 ar
|= (var
->s
& 1) << 4;
3784 ar
|= (var
->dpl
& 3) << 5;
3785 ar
|= (var
->present
& 1) << 7;
3786 ar
|= (var
->avl
& 1) << 12;
3787 ar
|= (var
->l
& 1) << 13;
3788 ar
|= (var
->db
& 1) << 14;
3789 ar
|= (var
->g
& 1) << 15;
3795 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3796 struct kvm_segment
*var
, int seg
)
3798 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3799 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3801 vmx_segment_cache_clear(vmx
);
3803 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3804 vmx
->rmode
.segs
[seg
] = *var
;
3805 if (seg
== VCPU_SREG_TR
)
3806 vmcs_write16(sf
->selector
, var
->selector
);
3808 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3812 vmcs_writel(sf
->base
, var
->base
);
3813 vmcs_write32(sf
->limit
, var
->limit
);
3814 vmcs_write16(sf
->selector
, var
->selector
);
3817 * Fix the "Accessed" bit in AR field of segment registers for older
3819 * IA32 arch specifies that at the time of processor reset the
3820 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3821 * is setting it to 0 in the userland code. This causes invalid guest
3822 * state vmexit when "unrestricted guest" mode is turned on.
3823 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3824 * tree. Newer qemu binaries with that qemu fix would not need this
3827 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3828 var
->type
|= 0x1; /* Accessed */
3830 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3833 vmx
->emulation_required
= emulation_required(vcpu
);
3836 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3838 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3840 *db
= (ar
>> 14) & 1;
3841 *l
= (ar
>> 13) & 1;
3844 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3846 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3847 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3850 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3852 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3853 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3856 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3858 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3859 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3862 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3864 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3865 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3868 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3870 struct kvm_segment var
;
3873 vmx_get_segment(vcpu
, &var
, seg
);
3875 if (seg
== VCPU_SREG_CS
)
3877 ar
= vmx_segment_access_rights(&var
);
3879 if (var
.base
!= (var
.selector
<< 4))
3881 if (var
.limit
!= 0xffff)
3889 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3891 struct kvm_segment cs
;
3892 unsigned int cs_rpl
;
3894 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3895 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3899 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3903 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3904 if (cs
.dpl
> cs_rpl
)
3907 if (cs
.dpl
!= cs_rpl
)
3913 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3917 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3919 struct kvm_segment ss
;
3920 unsigned int ss_rpl
;
3922 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3923 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
3927 if (ss
.type
!= 3 && ss
.type
!= 7)
3931 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3939 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3941 struct kvm_segment var
;
3944 vmx_get_segment(vcpu
, &var
, seg
);
3945 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
3953 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
3954 if (var
.dpl
< rpl
) /* DPL < RPL */
3958 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3964 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3966 struct kvm_segment tr
;
3968 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3972 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3974 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3982 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3984 struct kvm_segment ldtr
;
3986 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3990 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4000 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4002 struct kvm_segment cs
, ss
;
4004 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4005 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4007 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4008 (ss
.selector
& SEGMENT_RPL_MASK
));
4012 * Check if guest state is valid. Returns true if valid, false if
4014 * We assume that registers are always usable
4016 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4018 if (enable_unrestricted_guest
)
4021 /* real mode guest state checks */
4022 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4023 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4025 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4027 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4029 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4031 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4033 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4036 /* protected mode guest state checks */
4037 if (!cs_ss_rpl_check(vcpu
))
4039 if (!code_segment_valid(vcpu
))
4041 if (!stack_segment_valid(vcpu
))
4043 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4045 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4047 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4049 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4051 if (!tr_valid(vcpu
))
4053 if (!ldtr_valid(vcpu
))
4057 * - Add checks on RIP
4058 * - Add checks on RFLAGS
4064 static int init_rmode_tss(struct kvm
*kvm
)
4070 idx
= srcu_read_lock(&kvm
->srcu
);
4071 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4072 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4075 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4076 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4077 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4080 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4083 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4087 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4088 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4091 srcu_read_unlock(&kvm
->srcu
, idx
);
4095 static int init_rmode_identity_map(struct kvm
*kvm
)
4098 pfn_t identity_map_pfn
;
4104 /* Protect kvm->arch.ept_identity_pagetable_done. */
4105 mutex_lock(&kvm
->slots_lock
);
4107 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4110 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4112 r
= alloc_identity_pagetable(kvm
);
4116 idx
= srcu_read_lock(&kvm
->srcu
);
4117 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4120 /* Set up identity-mapping pagetable for EPT in real mode */
4121 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4122 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4123 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4124 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4125 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4129 kvm
->arch
.ept_identity_pagetable_done
= true;
4132 srcu_read_unlock(&kvm
->srcu
, idx
);
4135 mutex_unlock(&kvm
->slots_lock
);
4139 static void seg_setup(int seg
)
4141 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4144 vmcs_write16(sf
->selector
, 0);
4145 vmcs_writel(sf
->base
, 0);
4146 vmcs_write32(sf
->limit
, 0xffff);
4148 if (seg
== VCPU_SREG_CS
)
4149 ar
|= 0x08; /* code segment */
4151 vmcs_write32(sf
->ar_bytes
, ar
);
4154 static int alloc_apic_access_page(struct kvm
*kvm
)
4157 struct kvm_userspace_memory_region kvm_userspace_mem
;
4160 mutex_lock(&kvm
->slots_lock
);
4161 if (kvm
->arch
.apic_access_page_done
)
4163 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4164 kvm_userspace_mem
.flags
= 0;
4165 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
4166 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4167 r
= __x86_set_memory_region(kvm
, &kvm_userspace_mem
);
4171 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4172 if (is_error_page(page
)) {
4178 * Do not pin the page in memory, so that memory hot-unplug
4179 * is able to migrate it.
4182 kvm
->arch
.apic_access_page_done
= true;
4184 mutex_unlock(&kvm
->slots_lock
);
4188 static int alloc_identity_pagetable(struct kvm
*kvm
)
4190 /* Called with kvm->slots_lock held. */
4192 struct kvm_userspace_memory_region kvm_userspace_mem
;
4195 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4197 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4198 kvm_userspace_mem
.flags
= 0;
4199 kvm_userspace_mem
.guest_phys_addr
=
4200 kvm
->arch
.ept_identity_map_addr
;
4201 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4202 r
= __x86_set_memory_region(kvm
, &kvm_userspace_mem
);
4207 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4214 spin_lock(&vmx_vpid_lock
);
4215 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4216 if (vpid
< VMX_NR_VPIDS
) {
4218 __set_bit(vpid
, vmx_vpid_bitmap
);
4220 spin_unlock(&vmx_vpid_lock
);
4223 static void free_vpid(struct vcpu_vmx
*vmx
)
4227 spin_lock(&vmx_vpid_lock
);
4229 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4230 spin_unlock(&vmx_vpid_lock
);
4233 #define MSR_TYPE_R 1
4234 #define MSR_TYPE_W 2
4235 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4238 int f
= sizeof(unsigned long);
4240 if (!cpu_has_vmx_msr_bitmap())
4244 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4245 * have the write-low and read-high bitmap offsets the wrong way round.
4246 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4248 if (msr
<= 0x1fff) {
4249 if (type
& MSR_TYPE_R
)
4251 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4253 if (type
& MSR_TYPE_W
)
4255 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4257 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4259 if (type
& MSR_TYPE_R
)
4261 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4263 if (type
& MSR_TYPE_W
)
4265 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4270 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4273 int f
= sizeof(unsigned long);
4275 if (!cpu_has_vmx_msr_bitmap())
4279 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4280 * have the write-low and read-high bitmap offsets the wrong way round.
4281 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4283 if (msr
<= 0x1fff) {
4284 if (type
& MSR_TYPE_R
)
4286 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4288 if (type
& MSR_TYPE_W
)
4290 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4292 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4294 if (type
& MSR_TYPE_R
)
4296 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4298 if (type
& MSR_TYPE_W
)
4300 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4306 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4307 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4309 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4310 unsigned long *msr_bitmap_nested
,
4313 int f
= sizeof(unsigned long);
4315 if (!cpu_has_vmx_msr_bitmap()) {
4321 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4322 * have the write-low and read-high bitmap offsets the wrong way round.
4323 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4325 if (msr
<= 0x1fff) {
4326 if (type
& MSR_TYPE_R
&&
4327 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4329 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4331 if (type
& MSR_TYPE_W
&&
4332 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4334 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4336 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4338 if (type
& MSR_TYPE_R
&&
4339 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4341 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4343 if (type
& MSR_TYPE_W
&&
4344 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4346 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4351 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4354 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4355 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4356 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4357 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4360 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4362 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4364 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4368 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4370 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4372 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4376 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4378 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4380 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4384 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
4386 return enable_apicv
&& lapic_in_kernel(vcpu
);
4389 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4391 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4396 if (vmx
->nested
.pi_desc
&&
4397 vmx
->nested
.pi_pending
) {
4398 vmx
->nested
.pi_pending
= false;
4399 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4402 max_irr
= find_last_bit(
4403 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4408 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4413 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4414 kunmap(vmx
->nested
.virtual_apic_page
);
4416 status
= vmcs_read16(GUEST_INTR_STATUS
);
4417 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4419 status
|= (u8
)max_irr
;
4420 vmcs_write16(GUEST_INTR_STATUS
, status
);
4426 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4429 if (vcpu
->mode
== IN_GUEST_MODE
) {
4430 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4431 POSTED_INTR_VECTOR
);
4438 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4443 if (is_guest_mode(vcpu
) &&
4444 vector
== vmx
->nested
.posted_intr_nv
) {
4445 /* the PIR and ON have been set by L1. */
4446 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4448 * If a posted intr is not recognized by hardware,
4449 * we will accomplish it in the next vmentry.
4451 vmx
->nested
.pi_pending
= true;
4452 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4458 * Send interrupt to vcpu via posted interrupt way.
4459 * 1. If target vcpu is running(non-root mode), send posted interrupt
4460 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4461 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4462 * interrupt from PIR in next vmentry.
4464 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4466 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4469 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4473 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4476 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4477 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4478 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4479 kvm_vcpu_kick(vcpu
);
4482 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4484 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4486 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4489 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4492 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4498 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4499 * will not change in the lifetime of the guest.
4500 * Note that host-state that does change is set elsewhere. E.g., host-state
4501 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4503 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4510 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4511 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4513 /* Save the most likely value for this task's CR4 in the VMCS. */
4514 cr4
= cr4_read_shadow();
4515 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4516 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4518 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4519 #ifdef CONFIG_X86_64
4521 * Load null selectors, so we can avoid reloading them in
4522 * __vmx_load_host_state(), in case userspace uses the null selectors
4523 * too (the expected case).
4525 vmcs_write16(HOST_DS_SELECTOR
, 0);
4526 vmcs_write16(HOST_ES_SELECTOR
, 0);
4528 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4529 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4531 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4532 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4534 native_store_idt(&dt
);
4535 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4536 vmx
->host_idt_base
= dt
.address
;
4538 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4540 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4541 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4542 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4543 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4545 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4546 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4547 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4551 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4553 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4555 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4556 if (is_guest_mode(&vmx
->vcpu
))
4557 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4558 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4559 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4562 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4564 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4566 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4567 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4568 return pin_based_exec_ctrl
;
4571 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4573 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4575 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4576 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4578 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4579 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4580 #ifdef CONFIG_X86_64
4581 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4582 CPU_BASED_CR8_LOAD_EXITING
;
4586 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4587 CPU_BASED_CR3_LOAD_EXITING
|
4588 CPU_BASED_INVLPG_EXITING
;
4589 return exec_control
;
4592 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4594 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4595 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4596 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4598 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4600 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4601 enable_unrestricted_guest
= 0;
4602 /* Enable INVPCID for non-ept guests may cause performance regression. */
4603 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4605 if (!enable_unrestricted_guest
)
4606 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4608 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4609 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4610 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4611 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4612 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4613 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4615 We can NOT enable shadow_vmcs here because we don't have yet
4618 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4619 /* PML is enabled/disabled in creating/destorying vcpu */
4620 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4622 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4623 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4625 return exec_control
;
4628 static void ept_set_mmio_spte_mask(void)
4631 * EPT Misconfigurations can be generated if the value of bits 2:0
4632 * of an EPT paging-structure entry is 110b (write/execute).
4633 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4636 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4639 #define VMX_XSS_EXIT_BITMAP 0
4641 * Sets up the vmcs for emulated real mode.
4643 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4645 #ifdef CONFIG_X86_64
4651 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4652 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4654 if (enable_shadow_vmcs
) {
4655 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4656 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4658 if (cpu_has_vmx_msr_bitmap())
4659 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4661 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4664 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4666 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4668 if (cpu_has_secondary_exec_ctrls())
4669 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4670 vmx_secondary_exec_control(vmx
));
4672 if (vmx_cpu_uses_apicv(&vmx
->vcpu
)) {
4673 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4674 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4675 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4676 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4678 vmcs_write16(GUEST_INTR_STATUS
, 0);
4680 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4681 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4685 vmcs_write32(PLE_GAP
, ple_gap
);
4686 vmx
->ple_window
= ple_window
;
4687 vmx
->ple_window_dirty
= true;
4690 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4691 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4692 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4694 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4695 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4696 vmx_set_constant_host_state(vmx
);
4697 #ifdef CONFIG_X86_64
4698 rdmsrl(MSR_FS_BASE
, a
);
4699 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4700 rdmsrl(MSR_GS_BASE
, a
);
4701 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4703 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4704 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4707 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4708 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4709 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4710 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4711 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4713 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4714 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4716 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4717 u32 index
= vmx_msr_index
[i
];
4718 u32 data_low
, data_high
;
4721 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4723 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4725 vmx
->guest_msrs
[j
].index
= i
;
4726 vmx
->guest_msrs
[j
].data
= 0;
4727 vmx
->guest_msrs
[j
].mask
= -1ull;
4732 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4734 /* 22.2.1, 20.8.1 */
4735 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4737 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4738 set_cr4_guest_host_mask(vmx
);
4740 if (vmx_xsaves_supported())
4741 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4746 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4748 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4749 struct msr_data apic_base_msr
;
4752 vmx
->rmode
.vm86_active
= 0;
4754 vmx
->soft_vnmi_blocked
= 0;
4756 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4757 kvm_set_cr8(vcpu
, 0);
4760 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4761 MSR_IA32_APICBASE_ENABLE
;
4762 if (kvm_vcpu_is_reset_bsp(vcpu
))
4763 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4764 apic_base_msr
.host_initiated
= true;
4765 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4768 vmx_segment_cache_clear(vmx
);
4770 seg_setup(VCPU_SREG_CS
);
4771 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4772 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4774 seg_setup(VCPU_SREG_DS
);
4775 seg_setup(VCPU_SREG_ES
);
4776 seg_setup(VCPU_SREG_FS
);
4777 seg_setup(VCPU_SREG_GS
);
4778 seg_setup(VCPU_SREG_SS
);
4780 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4781 vmcs_writel(GUEST_TR_BASE
, 0);
4782 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4783 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4785 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4786 vmcs_writel(GUEST_LDTR_BASE
, 0);
4787 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4788 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4791 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4792 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4793 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4794 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4797 vmcs_writel(GUEST_RFLAGS
, 0x02);
4798 kvm_rip_write(vcpu
, 0xfff0);
4800 vmcs_writel(GUEST_GDTR_BASE
, 0);
4801 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4803 vmcs_writel(GUEST_IDTR_BASE
, 0);
4804 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4806 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4807 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4808 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4812 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4814 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4815 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4816 if (cpu_need_tpr_shadow(vcpu
))
4817 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4818 __pa(vcpu
->arch
.apic
->regs
));
4819 vmcs_write32(TPR_THRESHOLD
, 0);
4822 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4824 if (vmx_cpu_uses_apicv(vcpu
))
4825 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4828 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4830 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4831 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4832 vmx
->vcpu
.arch
.cr0
= cr0
;
4833 vmx_set_cr4(vcpu
, 0);
4835 vmx_set_efer(vcpu
, 0);
4836 vmx_fpu_activate(vcpu
);
4837 update_exception_bitmap(vcpu
);
4839 vpid_sync_context(vmx
);
4843 * In nested virtualization, check if L1 asked to exit on external interrupts.
4844 * For most existing hypervisors, this will always return true.
4846 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4848 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4849 PIN_BASED_EXT_INTR_MASK
;
4853 * In nested virtualization, check if L1 has set
4854 * VM_EXIT_ACK_INTR_ON_EXIT
4856 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4858 return get_vmcs12(vcpu
)->vm_exit_controls
&
4859 VM_EXIT_ACK_INTR_ON_EXIT
;
4862 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4864 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4865 PIN_BASED_NMI_EXITING
;
4868 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4870 u32 cpu_based_vm_exec_control
;
4872 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4873 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4874 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4877 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4879 u32 cpu_based_vm_exec_control
;
4881 if (!cpu_has_virtual_nmis() ||
4882 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4883 enable_irq_window(vcpu
);
4887 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4888 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4889 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4892 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4894 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4896 int irq
= vcpu
->arch
.interrupt
.nr
;
4898 trace_kvm_inj_virq(irq
);
4900 ++vcpu
->stat
.irq_injections
;
4901 if (vmx
->rmode
.vm86_active
) {
4903 if (vcpu
->arch
.interrupt
.soft
)
4904 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4905 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4906 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4909 intr
= irq
| INTR_INFO_VALID_MASK
;
4910 if (vcpu
->arch
.interrupt
.soft
) {
4911 intr
|= INTR_TYPE_SOFT_INTR
;
4912 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4913 vmx
->vcpu
.arch
.event_exit_inst_len
);
4915 intr
|= INTR_TYPE_EXT_INTR
;
4916 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4919 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4923 if (is_guest_mode(vcpu
))
4926 if (!cpu_has_virtual_nmis()) {
4928 * Tracking the NMI-blocked state in software is built upon
4929 * finding the next open IRQ window. This, in turn, depends on
4930 * well-behaving guests: They have to keep IRQs disabled at
4931 * least as long as the NMI handler runs. Otherwise we may
4932 * cause NMI nesting, maybe breaking the guest. But as this is
4933 * highly unlikely, we can live with the residual risk.
4935 vmx
->soft_vnmi_blocked
= 1;
4936 vmx
->vnmi_blocked_time
= 0;
4939 ++vcpu
->stat
.nmi_injections
;
4940 vmx
->nmi_known_unmasked
= false;
4941 if (vmx
->rmode
.vm86_active
) {
4942 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4943 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4946 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4947 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4950 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4952 if (!cpu_has_virtual_nmis())
4953 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4954 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4956 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4959 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4961 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4963 if (!cpu_has_virtual_nmis()) {
4964 if (vmx
->soft_vnmi_blocked
!= masked
) {
4965 vmx
->soft_vnmi_blocked
= masked
;
4966 vmx
->vnmi_blocked_time
= 0;
4969 vmx
->nmi_known_unmasked
= !masked
;
4971 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4972 GUEST_INTR_STATE_NMI
);
4974 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4975 GUEST_INTR_STATE_NMI
);
4979 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4981 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4984 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4987 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4988 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4989 | GUEST_INTR_STATE_NMI
));
4992 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4994 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4995 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4996 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4997 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5000 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5003 struct kvm_userspace_memory_region tss_mem
= {
5004 .slot
= TSS_PRIVATE_MEMSLOT
,
5005 .guest_phys_addr
= addr
,
5006 .memory_size
= PAGE_SIZE
* 3,
5010 ret
= x86_set_memory_region(kvm
, &tss_mem
);
5013 kvm
->arch
.tss_addr
= addr
;
5014 return init_rmode_tss(kvm
);
5017 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5022 * Update instruction length as we may reinject the exception
5023 * from user space while in guest debugging mode.
5025 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5026 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5027 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5031 if (vcpu
->guest_debug
&
5032 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5049 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5050 int vec
, u32 err_code
)
5053 * Instruction with address size override prefix opcode 0x67
5054 * Cause the #SS fault with 0 error code in VM86 mode.
5056 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5057 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5058 if (vcpu
->arch
.halt_request
) {
5059 vcpu
->arch
.halt_request
= 0;
5060 return kvm_vcpu_halt(vcpu
);
5068 * Forward all other exceptions that are valid in real mode.
5069 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5070 * the required debugging infrastructure rework.
5072 kvm_queue_exception(vcpu
, vec
);
5077 * Trigger machine check on the host. We assume all the MSRs are already set up
5078 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5079 * We pass a fake environment to the machine check handler because we want
5080 * the guest to be always treated like user space, no matter what context
5081 * it used internally.
5083 static void kvm_machine_check(void)
5085 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5086 struct pt_regs regs
= {
5087 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5088 .flags
= X86_EFLAGS_IF
,
5091 do_machine_check(®s
, 0);
5095 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5097 /* already handled by vcpu_run */
5101 static int handle_exception(struct kvm_vcpu
*vcpu
)
5103 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5104 struct kvm_run
*kvm_run
= vcpu
->run
;
5105 u32 intr_info
, ex_no
, error_code
;
5106 unsigned long cr2
, rip
, dr6
;
5108 enum emulation_result er
;
5110 vect_info
= vmx
->idt_vectoring_info
;
5111 intr_info
= vmx
->exit_intr_info
;
5113 if (is_machine_check(intr_info
))
5114 return handle_machine_check(vcpu
);
5116 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5117 return 1; /* already handled by vmx_vcpu_run() */
5119 if (is_no_device(intr_info
)) {
5120 vmx_fpu_activate(vcpu
);
5124 if (is_invalid_opcode(intr_info
)) {
5125 if (is_guest_mode(vcpu
)) {
5126 kvm_queue_exception(vcpu
, UD_VECTOR
);
5129 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5130 if (er
!= EMULATE_DONE
)
5131 kvm_queue_exception(vcpu
, UD_VECTOR
);
5136 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5137 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5140 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5141 * MMIO, it is better to report an internal error.
5142 * See the comments in vmx_handle_exit.
5144 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5145 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5146 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5147 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5148 vcpu
->run
->internal
.ndata
= 3;
5149 vcpu
->run
->internal
.data
[0] = vect_info
;
5150 vcpu
->run
->internal
.data
[1] = intr_info
;
5151 vcpu
->run
->internal
.data
[2] = error_code
;
5155 if (is_page_fault(intr_info
)) {
5156 /* EPT won't cause page fault directly */
5158 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5159 trace_kvm_page_fault(cr2
, error_code
);
5161 if (kvm_event_needs_reinjection(vcpu
))
5162 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5163 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5166 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5168 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5169 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5173 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5174 if (!(vcpu
->guest_debug
&
5175 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5176 vcpu
->arch
.dr6
&= ~15;
5177 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5178 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5179 skip_emulated_instruction(vcpu
);
5181 kvm_queue_exception(vcpu
, DB_VECTOR
);
5184 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5185 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5189 * Update instruction length as we may reinject #BP from
5190 * user space while in guest debugging mode. Reading it for
5191 * #DB as well causes no harm, it is not used in that case.
5193 vmx
->vcpu
.arch
.event_exit_inst_len
=
5194 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5195 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5196 rip
= kvm_rip_read(vcpu
);
5197 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5198 kvm_run
->debug
.arch
.exception
= ex_no
;
5201 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5202 kvm_run
->ex
.exception
= ex_no
;
5203 kvm_run
->ex
.error_code
= error_code
;
5209 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5211 ++vcpu
->stat
.irq_exits
;
5215 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5217 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5221 static int handle_io(struct kvm_vcpu
*vcpu
)
5223 unsigned long exit_qualification
;
5224 int size
, in
, string
;
5227 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5228 string
= (exit_qualification
& 16) != 0;
5229 in
= (exit_qualification
& 8) != 0;
5231 ++vcpu
->stat
.io_exits
;
5234 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5236 port
= exit_qualification
>> 16;
5237 size
= (exit_qualification
& 7) + 1;
5238 skip_emulated_instruction(vcpu
);
5240 return kvm_fast_pio_out(vcpu
, size
, port
);
5244 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5247 * Patch in the VMCALL instruction:
5249 hypercall
[0] = 0x0f;
5250 hypercall
[1] = 0x01;
5251 hypercall
[2] = 0xc1;
5254 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5256 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5257 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5259 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5260 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5261 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5262 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5263 return (val
& always_on
) == always_on
;
5266 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5267 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5269 if (is_guest_mode(vcpu
)) {
5270 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5271 unsigned long orig_val
= val
;
5274 * We get here when L2 changed cr0 in a way that did not change
5275 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5276 * but did change L0 shadowed bits. So we first calculate the
5277 * effective cr0 value that L1 would like to write into the
5278 * hardware. It consists of the L2-owned bits from the new
5279 * value combined with the L1-owned bits from L1's guest_cr0.
5281 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5282 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5284 if (!nested_cr0_valid(vcpu
, val
))
5287 if (kvm_set_cr0(vcpu
, val
))
5289 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5292 if (to_vmx(vcpu
)->nested
.vmxon
&&
5293 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5295 return kvm_set_cr0(vcpu
, val
);
5299 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5301 if (is_guest_mode(vcpu
)) {
5302 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5303 unsigned long orig_val
= val
;
5305 /* analogously to handle_set_cr0 */
5306 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5307 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5308 if (kvm_set_cr4(vcpu
, val
))
5310 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5313 return kvm_set_cr4(vcpu
, val
);
5316 /* called to set cr0 as approriate for clts instruction exit. */
5317 static void handle_clts(struct kvm_vcpu
*vcpu
)
5319 if (is_guest_mode(vcpu
)) {
5321 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5322 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5323 * just pretend it's off (also in arch.cr0 for fpu_activate).
5325 vmcs_writel(CR0_READ_SHADOW
,
5326 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5327 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5329 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5332 static int handle_cr(struct kvm_vcpu
*vcpu
)
5334 unsigned long exit_qualification
, val
;
5339 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5340 cr
= exit_qualification
& 15;
5341 reg
= (exit_qualification
>> 8) & 15;
5342 switch ((exit_qualification
>> 4) & 3) {
5343 case 0: /* mov to cr */
5344 val
= kvm_register_readl(vcpu
, reg
);
5345 trace_kvm_cr_write(cr
, val
);
5348 err
= handle_set_cr0(vcpu
, val
);
5349 kvm_complete_insn_gp(vcpu
, err
);
5352 err
= kvm_set_cr3(vcpu
, val
);
5353 kvm_complete_insn_gp(vcpu
, err
);
5356 err
= handle_set_cr4(vcpu
, val
);
5357 kvm_complete_insn_gp(vcpu
, err
);
5360 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5362 err
= kvm_set_cr8(vcpu
, cr8
);
5363 kvm_complete_insn_gp(vcpu
, err
);
5364 if (lapic_in_kernel(vcpu
))
5366 if (cr8_prev
<= cr8
)
5368 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5375 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5376 skip_emulated_instruction(vcpu
);
5377 vmx_fpu_activate(vcpu
);
5379 case 1: /*mov from cr*/
5382 val
= kvm_read_cr3(vcpu
);
5383 kvm_register_write(vcpu
, reg
, val
);
5384 trace_kvm_cr_read(cr
, val
);
5385 skip_emulated_instruction(vcpu
);
5388 val
= kvm_get_cr8(vcpu
);
5389 kvm_register_write(vcpu
, reg
, val
);
5390 trace_kvm_cr_read(cr
, val
);
5391 skip_emulated_instruction(vcpu
);
5396 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5397 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5398 kvm_lmsw(vcpu
, val
);
5400 skip_emulated_instruction(vcpu
);
5405 vcpu
->run
->exit_reason
= 0;
5406 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5407 (int)(exit_qualification
>> 4) & 3, cr
);
5411 static int handle_dr(struct kvm_vcpu
*vcpu
)
5413 unsigned long exit_qualification
;
5416 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5417 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5419 /* First, if DR does not exist, trigger UD */
5420 if (!kvm_require_dr(vcpu
, dr
))
5423 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5424 if (!kvm_require_cpl(vcpu
, 0))
5426 dr7
= vmcs_readl(GUEST_DR7
);
5429 * As the vm-exit takes precedence over the debug trap, we
5430 * need to emulate the latter, either for the host or the
5431 * guest debugging itself.
5433 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5434 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5435 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5436 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5437 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5438 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5441 vcpu
->arch
.dr6
&= ~15;
5442 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5443 kvm_queue_exception(vcpu
, DB_VECTOR
);
5448 if (vcpu
->guest_debug
== 0) {
5449 u32 cpu_based_vm_exec_control
;
5451 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5452 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5456 * No more DR vmexits; force a reload of the debug registers
5457 * and reenter on this instruction. The next vmexit will
5458 * retrieve the full state of the debug registers.
5460 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5464 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5465 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5468 if (kvm_get_dr(vcpu
, dr
, &val
))
5470 kvm_register_write(vcpu
, reg
, val
);
5472 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5475 skip_emulated_instruction(vcpu
);
5479 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5481 return vcpu
->arch
.dr6
;
5484 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5488 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5490 u32 cpu_based_vm_exec_control
;
5492 get_debugreg(vcpu
->arch
.db
[0], 0);
5493 get_debugreg(vcpu
->arch
.db
[1], 1);
5494 get_debugreg(vcpu
->arch
.db
[2], 2);
5495 get_debugreg(vcpu
->arch
.db
[3], 3);
5496 get_debugreg(vcpu
->arch
.dr6
, 6);
5497 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5499 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5501 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5502 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5503 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5506 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5508 vmcs_writel(GUEST_DR7
, val
);
5511 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5513 kvm_emulate_cpuid(vcpu
);
5517 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5519 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5520 struct msr_data msr_info
;
5522 msr_info
.index
= ecx
;
5523 msr_info
.host_initiated
= false;
5524 if (vmx_get_msr(vcpu
, &msr_info
)) {
5525 trace_kvm_msr_read_ex(ecx
);
5526 kvm_inject_gp(vcpu
, 0);
5530 trace_kvm_msr_read(ecx
, msr_info
.data
);
5532 /* FIXME: handling of bits 32:63 of rax, rdx */
5533 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5534 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5535 skip_emulated_instruction(vcpu
);
5539 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5541 struct msr_data msr
;
5542 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5543 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5544 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5548 msr
.host_initiated
= false;
5549 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5550 trace_kvm_msr_write_ex(ecx
, data
);
5551 kvm_inject_gp(vcpu
, 0);
5555 trace_kvm_msr_write(ecx
, data
);
5556 skip_emulated_instruction(vcpu
);
5560 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5562 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5566 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5568 u32 cpu_based_vm_exec_control
;
5570 /* clear pending irq */
5571 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5572 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5575 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5577 ++vcpu
->stat
.irq_window_exits
;
5581 static int handle_halt(struct kvm_vcpu
*vcpu
)
5583 return kvm_emulate_halt(vcpu
);
5586 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5588 kvm_emulate_hypercall(vcpu
);
5592 static int handle_invd(struct kvm_vcpu
*vcpu
)
5594 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5597 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5599 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5601 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5602 skip_emulated_instruction(vcpu
);
5606 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5610 err
= kvm_rdpmc(vcpu
);
5611 kvm_complete_insn_gp(vcpu
, err
);
5616 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5618 kvm_emulate_wbinvd(vcpu
);
5622 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5624 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5625 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5627 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5628 skip_emulated_instruction(vcpu
);
5632 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5634 skip_emulated_instruction(vcpu
);
5635 WARN(1, "this should never happen\n");
5639 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5641 skip_emulated_instruction(vcpu
);
5642 WARN(1, "this should never happen\n");
5646 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5648 if (likely(fasteoi
)) {
5649 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5650 int access_type
, offset
;
5652 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5653 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5655 * Sane guest uses MOV to write EOI, with written value
5656 * not cared. So make a short-circuit here by avoiding
5657 * heavy instruction emulation.
5659 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5660 (offset
== APIC_EOI
)) {
5661 kvm_lapic_set_eoi(vcpu
);
5662 skip_emulated_instruction(vcpu
);
5666 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5669 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5671 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5672 int vector
= exit_qualification
& 0xff;
5674 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5675 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5679 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5681 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5682 u32 offset
= exit_qualification
& 0xfff;
5684 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5685 kvm_apic_write_nodecode(vcpu
, offset
);
5689 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5691 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5692 unsigned long exit_qualification
;
5693 bool has_error_code
= false;
5696 int reason
, type
, idt_v
, idt_index
;
5698 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5699 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5700 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5702 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5704 reason
= (u32
)exit_qualification
>> 30;
5705 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5707 case INTR_TYPE_NMI_INTR
:
5708 vcpu
->arch
.nmi_injected
= false;
5709 vmx_set_nmi_mask(vcpu
, true);
5711 case INTR_TYPE_EXT_INTR
:
5712 case INTR_TYPE_SOFT_INTR
:
5713 kvm_clear_interrupt_queue(vcpu
);
5715 case INTR_TYPE_HARD_EXCEPTION
:
5716 if (vmx
->idt_vectoring_info
&
5717 VECTORING_INFO_DELIVER_CODE_MASK
) {
5718 has_error_code
= true;
5720 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5723 case INTR_TYPE_SOFT_EXCEPTION
:
5724 kvm_clear_exception_queue(vcpu
);
5730 tss_selector
= exit_qualification
;
5732 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5733 type
!= INTR_TYPE_EXT_INTR
&&
5734 type
!= INTR_TYPE_NMI_INTR
))
5735 skip_emulated_instruction(vcpu
);
5737 if (kvm_task_switch(vcpu
, tss_selector
,
5738 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5739 has_error_code
, error_code
) == EMULATE_FAIL
) {
5740 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5741 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5742 vcpu
->run
->internal
.ndata
= 0;
5747 * TODO: What about debug traps on tss switch?
5748 * Are we supposed to inject them and update dr6?
5754 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5756 unsigned long exit_qualification
;
5761 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5763 gla_validity
= (exit_qualification
>> 7) & 0x3;
5764 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5765 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5766 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5767 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5768 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5769 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5770 (long unsigned int)exit_qualification
);
5771 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5772 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5777 * EPT violation happened while executing iret from NMI,
5778 * "blocked by NMI" bit has to be set before next VM entry.
5779 * There are errata that may cause this bit to not be set:
5782 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5783 cpu_has_virtual_nmis() &&
5784 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5785 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5787 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5788 trace_kvm_page_fault(gpa
, exit_qualification
);
5790 /* It is a write fault? */
5791 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5792 /* It is a fetch fault? */
5793 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5794 /* ept page table is present? */
5795 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5797 vcpu
->arch
.exit_qualification
= exit_qualification
;
5799 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5802 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5807 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5808 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5809 skip_emulated_instruction(vcpu
);
5810 trace_kvm_fast_mmio(gpa
);
5814 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5815 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5816 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5819 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5820 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5822 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5825 /* It is the real ept misconfig */
5828 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5829 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5834 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5836 u32 cpu_based_vm_exec_control
;
5838 /* clear pending NMI */
5839 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5840 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5841 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5842 ++vcpu
->stat
.nmi_window_exits
;
5843 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5848 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5850 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5851 enum emulation_result err
= EMULATE_DONE
;
5854 bool intr_window_requested
;
5855 unsigned count
= 130;
5857 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5858 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5860 while (vmx
->emulation_required
&& count
-- != 0) {
5861 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5862 return handle_interrupt_window(&vmx
->vcpu
);
5864 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5867 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5869 if (err
== EMULATE_USER_EXIT
) {
5870 ++vcpu
->stat
.mmio_exits
;
5875 if (err
!= EMULATE_DONE
) {
5876 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5877 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5878 vcpu
->run
->internal
.ndata
= 0;
5882 if (vcpu
->arch
.halt_request
) {
5883 vcpu
->arch
.halt_request
= 0;
5884 ret
= kvm_vcpu_halt(vcpu
);
5888 if (signal_pending(current
))
5898 static int __grow_ple_window(int val
)
5900 if (ple_window_grow
< 1)
5903 val
= min(val
, ple_window_actual_max
);
5905 if (ple_window_grow
< ple_window
)
5906 val
*= ple_window_grow
;
5908 val
+= ple_window_grow
;
5913 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5918 if (modifier
< ple_window
)
5923 return max(val
, minimum
);
5926 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5928 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5929 int old
= vmx
->ple_window
;
5931 vmx
->ple_window
= __grow_ple_window(old
);
5933 if (vmx
->ple_window
!= old
)
5934 vmx
->ple_window_dirty
= true;
5936 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5939 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5941 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5942 int old
= vmx
->ple_window
;
5944 vmx
->ple_window
= __shrink_ple_window(old
,
5945 ple_window_shrink
, ple_window
);
5947 if (vmx
->ple_window
!= old
)
5948 vmx
->ple_window_dirty
= true;
5950 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5954 * ple_window_actual_max is computed to be one grow_ple_window() below
5955 * ple_window_max. (See __grow_ple_window for the reason.)
5956 * This prevents overflows, because ple_window_max is int.
5957 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5959 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5961 static void update_ple_window_actual_max(void)
5963 ple_window_actual_max
=
5964 __shrink_ple_window(max(ple_window_max
, ple_window
),
5965 ple_window_grow
, INT_MIN
);
5968 static __init
int hardware_setup(void)
5970 int r
= -ENOMEM
, i
, msr
;
5972 rdmsrl_safe(MSR_EFER
, &host_efer
);
5974 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
5975 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5977 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5978 if (!vmx_io_bitmap_a
)
5981 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5982 if (!vmx_io_bitmap_b
)
5985 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5986 if (!vmx_msr_bitmap_legacy
)
5989 vmx_msr_bitmap_legacy_x2apic
=
5990 (unsigned long *)__get_free_page(GFP_KERNEL
);
5991 if (!vmx_msr_bitmap_legacy_x2apic
)
5994 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5995 if (!vmx_msr_bitmap_longmode
)
5998 vmx_msr_bitmap_longmode_x2apic
=
5999 (unsigned long *)__get_free_page(GFP_KERNEL
);
6000 if (!vmx_msr_bitmap_longmode_x2apic
)
6004 vmx_msr_bitmap_nested
=
6005 (unsigned long *)__get_free_page(GFP_KERNEL
);
6006 if (!vmx_msr_bitmap_nested
)
6010 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6011 if (!vmx_vmread_bitmap
)
6014 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6015 if (!vmx_vmwrite_bitmap
)
6018 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6019 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6022 * Allow direct access to the PC debug port (it is often used for I/O
6023 * delays, but the vmexits simply slow things down).
6025 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6026 clear_bit(0x80, vmx_io_bitmap_a
);
6028 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6030 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6031 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6033 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6035 if (setup_vmcs_config(&vmcs_config
) < 0) {
6040 if (boot_cpu_has(X86_FEATURE_NX
))
6041 kvm_enable_efer_bits(EFER_NX
);
6043 if (!cpu_has_vmx_vpid())
6045 if (!cpu_has_vmx_shadow_vmcs())
6046 enable_shadow_vmcs
= 0;
6047 if (enable_shadow_vmcs
)
6048 init_vmcs_shadow_fields();
6050 if (!cpu_has_vmx_ept() ||
6051 !cpu_has_vmx_ept_4levels()) {
6053 enable_unrestricted_guest
= 0;
6054 enable_ept_ad_bits
= 0;
6057 if (!cpu_has_vmx_ept_ad_bits())
6058 enable_ept_ad_bits
= 0;
6060 if (!cpu_has_vmx_unrestricted_guest())
6061 enable_unrestricted_guest
= 0;
6063 if (!cpu_has_vmx_flexpriority())
6064 flexpriority_enabled
= 0;
6067 * set_apic_access_page_addr() is used to reload apic access
6068 * page upon invalidation. No need to do anything if not
6069 * using the APIC_ACCESS_ADDR VMCS field.
6071 if (!flexpriority_enabled
)
6072 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6074 if (!cpu_has_vmx_tpr_shadow())
6075 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6077 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6078 kvm_disable_largepages();
6080 if (!cpu_has_vmx_ple())
6083 if (!cpu_has_vmx_apicv())
6087 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6089 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6090 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6091 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6092 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6095 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6096 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6097 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6098 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6099 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6100 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6101 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6103 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6104 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6105 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6106 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6108 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6111 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6112 vmx_disable_intercept_msr_read_x2apic(msr
);
6114 /* According SDM, in x2apic mode, the whole id reg is used.
6115 * But in KVM, it only use the highest eight bits. Need to
6117 vmx_enable_intercept_msr_read_x2apic(0x802);
6119 vmx_enable_intercept_msr_read_x2apic(0x839);
6121 vmx_disable_intercept_msr_write_x2apic(0x808);
6123 vmx_disable_intercept_msr_write_x2apic(0x80b);
6125 vmx_disable_intercept_msr_write_x2apic(0x83f);
6129 kvm_mmu_set_mask_ptes(0ull,
6130 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6131 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6132 0ull, VMX_EPT_EXECUTABLE_MASK
);
6133 ept_set_mmio_spte_mask();
6138 update_ple_window_actual_max();
6141 * Only enable PML when hardware supports PML feature, and both EPT
6142 * and EPT A/D bit features are enabled -- PML depends on them to work.
6144 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6148 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6149 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6150 kvm_x86_ops
->flush_log_dirty
= NULL
;
6151 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6154 return alloc_kvm_area();
6157 free_page((unsigned long)vmx_vmwrite_bitmap
);
6159 free_page((unsigned long)vmx_vmread_bitmap
);
6162 free_page((unsigned long)vmx_msr_bitmap_nested
);
6164 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6166 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6168 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6170 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6172 free_page((unsigned long)vmx_io_bitmap_b
);
6174 free_page((unsigned long)vmx_io_bitmap_a
);
6179 static __exit
void hardware_unsetup(void)
6181 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6182 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6183 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6184 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6185 free_page((unsigned long)vmx_io_bitmap_b
);
6186 free_page((unsigned long)vmx_io_bitmap_a
);
6187 free_page((unsigned long)vmx_vmwrite_bitmap
);
6188 free_page((unsigned long)vmx_vmread_bitmap
);
6190 free_page((unsigned long)vmx_msr_bitmap_nested
);
6196 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6197 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6199 static int handle_pause(struct kvm_vcpu
*vcpu
)
6202 grow_ple_window(vcpu
);
6204 skip_emulated_instruction(vcpu
);
6205 kvm_vcpu_on_spin(vcpu
);
6210 static int handle_nop(struct kvm_vcpu
*vcpu
)
6212 skip_emulated_instruction(vcpu
);
6216 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6218 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6219 return handle_nop(vcpu
);
6222 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6227 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6229 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6230 return handle_nop(vcpu
);
6234 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6235 * We could reuse a single VMCS for all the L2 guests, but we also want the
6236 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6237 * allows keeping them loaded on the processor, and in the future will allow
6238 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6239 * every entry if they never change.
6240 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6241 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6243 * The following functions allocate and free a vmcs02 in this pool.
6246 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6247 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6249 struct vmcs02_list
*item
;
6250 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6251 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6252 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6253 return &item
->vmcs02
;
6256 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6257 /* Recycle the least recently used VMCS. */
6258 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6259 struct vmcs02_list
, list
);
6260 item
->vmptr
= vmx
->nested
.current_vmptr
;
6261 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6262 return &item
->vmcs02
;
6265 /* Create a new VMCS */
6266 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6269 item
->vmcs02
.vmcs
= alloc_vmcs();
6270 if (!item
->vmcs02
.vmcs
) {
6274 loaded_vmcs_init(&item
->vmcs02
);
6275 item
->vmptr
= vmx
->nested
.current_vmptr
;
6276 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6277 vmx
->nested
.vmcs02_num
++;
6278 return &item
->vmcs02
;
6281 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6282 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6284 struct vmcs02_list
*item
;
6285 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6286 if (item
->vmptr
== vmptr
) {
6287 free_loaded_vmcs(&item
->vmcs02
);
6288 list_del(&item
->list
);
6290 vmx
->nested
.vmcs02_num
--;
6296 * Free all VMCSs saved for this vcpu, except the one pointed by
6297 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6298 * must be &vmx->vmcs01.
6300 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6302 struct vmcs02_list
*item
, *n
;
6304 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6305 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6307 * Something will leak if the above WARN triggers. Better than
6310 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6313 free_loaded_vmcs(&item
->vmcs02
);
6314 list_del(&item
->list
);
6316 vmx
->nested
.vmcs02_num
--;
6321 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6322 * set the success or error code of an emulated VMX instruction, as specified
6323 * by Vol 2B, VMX Instruction Reference, "Conventions".
6325 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6327 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6328 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6329 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6332 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6334 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6335 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6336 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6340 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6341 u32 vm_instruction_error
)
6343 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6345 * failValid writes the error number to the current VMCS, which
6346 * can't be done there isn't a current VMCS.
6348 nested_vmx_failInvalid(vcpu
);
6351 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6352 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6353 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6355 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6357 * We don't need to force a shadow sync because
6358 * VM_INSTRUCTION_ERROR is not shadowed
6362 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6364 /* TODO: not to reset guest simply here. */
6365 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6366 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6369 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6371 struct vcpu_vmx
*vmx
=
6372 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6374 vmx
->nested
.preemption_timer_expired
= true;
6375 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6376 kvm_vcpu_kick(&vmx
->vcpu
);
6378 return HRTIMER_NORESTART
;
6382 * Decode the memory-address operand of a vmx instruction, as recorded on an
6383 * exit caused by such an instruction (run by a guest hypervisor).
6384 * On success, returns 0. When the operand is invalid, returns 1 and throws
6387 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6388 unsigned long exit_qualification
,
6389 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6393 struct kvm_segment s
;
6396 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6397 * Execution", on an exit, vmx_instruction_info holds most of the
6398 * addressing components of the operand. Only the displacement part
6399 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6400 * For how an actual address is calculated from all these components,
6401 * refer to Vol. 1, "Operand Addressing".
6403 int scaling
= vmx_instruction_info
& 3;
6404 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6405 bool is_reg
= vmx_instruction_info
& (1u << 10);
6406 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6407 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6408 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6409 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6410 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6413 kvm_queue_exception(vcpu
, UD_VECTOR
);
6417 /* Addr = segment_base + offset */
6418 /* offset = base + [index * scale] + displacement */
6419 off
= exit_qualification
; /* holds the displacement */
6421 off
+= kvm_register_read(vcpu
, base_reg
);
6423 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6424 vmx_get_segment(vcpu
, &s
, seg_reg
);
6425 *ret
= s
.base
+ off
;
6427 if (addr_size
== 1) /* 32 bit */
6430 /* Checks for #GP/#SS exceptions. */
6432 if (is_protmode(vcpu
)) {
6433 /* Protected mode: apply checks for segment validity in the
6435 * - segment type check (#GP(0) may be thrown)
6436 * - usability check (#GP(0)/#SS(0))
6437 * - limit check (#GP(0)/#SS(0))
6440 /* #GP(0) if the destination operand is located in a
6441 * read-only data segment or any code segment.
6443 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6445 /* #GP(0) if the source operand is located in an
6446 * execute-only code segment
6448 exn
= ((s
.type
& 0xa) == 8);
6451 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6454 if (is_long_mode(vcpu
)) {
6455 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6456 * non-canonical form. This is an only check for long mode.
6458 exn
= is_noncanonical_address(*ret
);
6459 } else if (is_protmode(vcpu
)) {
6460 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6462 exn
= (s
.unusable
!= 0);
6463 /* Protected mode: #GP(0)/#SS(0) if the memory
6464 * operand is outside the segment limit.
6466 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6469 kvm_queue_exception_e(vcpu
,
6470 seg_reg
== VCPU_SREG_SS
?
6471 SS_VECTOR
: GP_VECTOR
,
6480 * This function performs the various checks including
6481 * - if it's 4KB aligned
6482 * - No bits beyond the physical address width are set
6483 * - Returns 0 on success or else 1
6484 * (Intel SDM Section 30.3)
6486 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6491 struct x86_exception e
;
6493 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6494 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6496 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6497 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6500 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6501 sizeof(vmptr
), &e
)) {
6502 kvm_inject_page_fault(vcpu
, &e
);
6506 switch (exit_reason
) {
6507 case EXIT_REASON_VMON
:
6510 * The first 4 bytes of VMXON region contain the supported
6511 * VMCS revision identifier
6513 * Note - IA32_VMX_BASIC[48] will never be 1
6514 * for the nested case;
6515 * which replaces physical address width with 32
6518 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6519 nested_vmx_failInvalid(vcpu
);
6520 skip_emulated_instruction(vcpu
);
6524 page
= nested_get_page(vcpu
, vmptr
);
6526 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6527 nested_vmx_failInvalid(vcpu
);
6529 skip_emulated_instruction(vcpu
);
6533 vmx
->nested
.vmxon_ptr
= vmptr
;
6535 case EXIT_REASON_VMCLEAR
:
6536 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6537 nested_vmx_failValid(vcpu
,
6538 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6539 skip_emulated_instruction(vcpu
);
6543 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6544 nested_vmx_failValid(vcpu
,
6545 VMXERR_VMCLEAR_VMXON_POINTER
);
6546 skip_emulated_instruction(vcpu
);
6550 case EXIT_REASON_VMPTRLD
:
6551 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6552 nested_vmx_failValid(vcpu
,
6553 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6554 skip_emulated_instruction(vcpu
);
6558 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6559 nested_vmx_failValid(vcpu
,
6560 VMXERR_VMCLEAR_VMXON_POINTER
);
6561 skip_emulated_instruction(vcpu
);
6566 return 1; /* shouldn't happen */
6575 * Emulate the VMXON instruction.
6576 * Currently, we just remember that VMX is active, and do not save or even
6577 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6578 * do not currently need to store anything in that guest-allocated memory
6579 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6580 * argument is different from the VMXON pointer (which the spec says they do).
6582 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6584 struct kvm_segment cs
;
6585 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6586 struct vmcs
*shadow_vmcs
;
6587 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6588 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6590 /* The Intel VMX Instruction Reference lists a bunch of bits that
6591 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6592 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6593 * Otherwise, we should fail with #UD. We test these now:
6595 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6596 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6597 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6598 kvm_queue_exception(vcpu
, UD_VECTOR
);
6602 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6603 if (is_long_mode(vcpu
) && !cs
.l
) {
6604 kvm_queue_exception(vcpu
, UD_VECTOR
);
6608 if (vmx_get_cpl(vcpu
)) {
6609 kvm_inject_gp(vcpu
, 0);
6613 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6616 if (vmx
->nested
.vmxon
) {
6617 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6618 skip_emulated_instruction(vcpu
);
6622 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6623 != VMXON_NEEDED_FEATURES
) {
6624 kvm_inject_gp(vcpu
, 0);
6628 if (enable_shadow_vmcs
) {
6629 shadow_vmcs
= alloc_vmcs();
6632 /* mark vmcs as shadow */
6633 shadow_vmcs
->revision_id
|= (1u << 31);
6634 /* init shadow vmcs */
6635 vmcs_clear(shadow_vmcs
);
6636 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6639 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6640 vmx
->nested
.vmcs02_num
= 0;
6642 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6644 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6646 vmx
->nested
.vmxon
= true;
6648 skip_emulated_instruction(vcpu
);
6649 nested_vmx_succeed(vcpu
);
6654 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6655 * for running VMX instructions (except VMXON, whose prerequisites are
6656 * slightly different). It also specifies what exception to inject otherwise.
6658 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6660 struct kvm_segment cs
;
6661 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6663 if (!vmx
->nested
.vmxon
) {
6664 kvm_queue_exception(vcpu
, UD_VECTOR
);
6668 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6669 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6670 (is_long_mode(vcpu
) && !cs
.l
)) {
6671 kvm_queue_exception(vcpu
, UD_VECTOR
);
6675 if (vmx_get_cpl(vcpu
)) {
6676 kvm_inject_gp(vcpu
, 0);
6683 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6685 if (vmx
->nested
.current_vmptr
== -1ull)
6688 /* current_vmptr and current_vmcs12 are always set/reset together */
6689 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6692 if (enable_shadow_vmcs
) {
6693 /* copy to memory all shadowed fields in case
6694 they were modified */
6695 copy_shadow_to_vmcs12(vmx
);
6696 vmx
->nested
.sync_shadow_vmcs
= false;
6697 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6698 SECONDARY_EXEC_SHADOW_VMCS
);
6699 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6701 vmx
->nested
.posted_intr_nv
= -1;
6702 kunmap(vmx
->nested
.current_vmcs12_page
);
6703 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6704 vmx
->nested
.current_vmptr
= -1ull;
6705 vmx
->nested
.current_vmcs12
= NULL
;
6709 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6710 * just stops using VMX.
6712 static void free_nested(struct vcpu_vmx
*vmx
)
6714 if (!vmx
->nested
.vmxon
)
6717 vmx
->nested
.vmxon
= false;
6718 nested_release_vmcs12(vmx
);
6719 if (enable_shadow_vmcs
)
6720 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6721 /* Unpin physical memory we referred to in current vmcs02 */
6722 if (vmx
->nested
.apic_access_page
) {
6723 nested_release_page(vmx
->nested
.apic_access_page
);
6724 vmx
->nested
.apic_access_page
= NULL
;
6726 if (vmx
->nested
.virtual_apic_page
) {
6727 nested_release_page(vmx
->nested
.virtual_apic_page
);
6728 vmx
->nested
.virtual_apic_page
= NULL
;
6730 if (vmx
->nested
.pi_desc_page
) {
6731 kunmap(vmx
->nested
.pi_desc_page
);
6732 nested_release_page(vmx
->nested
.pi_desc_page
);
6733 vmx
->nested
.pi_desc_page
= NULL
;
6734 vmx
->nested
.pi_desc
= NULL
;
6737 nested_free_all_saved_vmcss(vmx
);
6740 /* Emulate the VMXOFF instruction */
6741 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6743 if (!nested_vmx_check_permission(vcpu
))
6745 free_nested(to_vmx(vcpu
));
6746 skip_emulated_instruction(vcpu
);
6747 nested_vmx_succeed(vcpu
);
6751 /* Emulate the VMCLEAR instruction */
6752 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6754 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6756 struct vmcs12
*vmcs12
;
6759 if (!nested_vmx_check_permission(vcpu
))
6762 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6765 if (vmptr
== vmx
->nested
.current_vmptr
)
6766 nested_release_vmcs12(vmx
);
6768 page
= nested_get_page(vcpu
, vmptr
);
6771 * For accurate processor emulation, VMCLEAR beyond available
6772 * physical memory should do nothing at all. However, it is
6773 * possible that a nested vmx bug, not a guest hypervisor bug,
6774 * resulted in this case, so let's shut down before doing any
6777 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6780 vmcs12
= kmap(page
);
6781 vmcs12
->launch_state
= 0;
6783 nested_release_page(page
);
6785 nested_free_vmcs02(vmx
, vmptr
);
6787 skip_emulated_instruction(vcpu
);
6788 nested_vmx_succeed(vcpu
);
6792 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6794 /* Emulate the VMLAUNCH instruction */
6795 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6797 return nested_vmx_run(vcpu
, true);
6800 /* Emulate the VMRESUME instruction */
6801 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6804 return nested_vmx_run(vcpu
, false);
6807 enum vmcs_field_type
{
6808 VMCS_FIELD_TYPE_U16
= 0,
6809 VMCS_FIELD_TYPE_U64
= 1,
6810 VMCS_FIELD_TYPE_U32
= 2,
6811 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6814 static inline int vmcs_field_type(unsigned long field
)
6816 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6817 return VMCS_FIELD_TYPE_U32
;
6818 return (field
>> 13) & 0x3 ;
6821 static inline int vmcs_field_readonly(unsigned long field
)
6823 return (((field
>> 10) & 0x3) == 1);
6827 * Read a vmcs12 field. Since these can have varying lengths and we return
6828 * one type, we chose the biggest type (u64) and zero-extend the return value
6829 * to that size. Note that the caller, handle_vmread, might need to use only
6830 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6831 * 64-bit fields are to be returned).
6833 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6834 unsigned long field
, u64
*ret
)
6836 short offset
= vmcs_field_to_offset(field
);
6842 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6844 switch (vmcs_field_type(field
)) {
6845 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6846 *ret
= *((natural_width
*)p
);
6848 case VMCS_FIELD_TYPE_U16
:
6851 case VMCS_FIELD_TYPE_U32
:
6854 case VMCS_FIELD_TYPE_U64
:
6864 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6865 unsigned long field
, u64 field_value
){
6866 short offset
= vmcs_field_to_offset(field
);
6867 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6871 switch (vmcs_field_type(field
)) {
6872 case VMCS_FIELD_TYPE_U16
:
6873 *(u16
*)p
= field_value
;
6875 case VMCS_FIELD_TYPE_U32
:
6876 *(u32
*)p
= field_value
;
6878 case VMCS_FIELD_TYPE_U64
:
6879 *(u64
*)p
= field_value
;
6881 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6882 *(natural_width
*)p
= field_value
;
6891 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6894 unsigned long field
;
6896 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6897 const unsigned long *fields
= shadow_read_write_fields
;
6898 const int num_fields
= max_shadow_read_write_fields
;
6902 vmcs_load(shadow_vmcs
);
6904 for (i
= 0; i
< num_fields
; i
++) {
6906 switch (vmcs_field_type(field
)) {
6907 case VMCS_FIELD_TYPE_U16
:
6908 field_value
= vmcs_read16(field
);
6910 case VMCS_FIELD_TYPE_U32
:
6911 field_value
= vmcs_read32(field
);
6913 case VMCS_FIELD_TYPE_U64
:
6914 field_value
= vmcs_read64(field
);
6916 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6917 field_value
= vmcs_readl(field
);
6923 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6926 vmcs_clear(shadow_vmcs
);
6927 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6932 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6934 const unsigned long *fields
[] = {
6935 shadow_read_write_fields
,
6936 shadow_read_only_fields
6938 const int max_fields
[] = {
6939 max_shadow_read_write_fields
,
6940 max_shadow_read_only_fields
6943 unsigned long field
;
6944 u64 field_value
= 0;
6945 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6947 vmcs_load(shadow_vmcs
);
6949 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6950 for (i
= 0; i
< max_fields
[q
]; i
++) {
6951 field
= fields
[q
][i
];
6952 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6954 switch (vmcs_field_type(field
)) {
6955 case VMCS_FIELD_TYPE_U16
:
6956 vmcs_write16(field
, (u16
)field_value
);
6958 case VMCS_FIELD_TYPE_U32
:
6959 vmcs_write32(field
, (u32
)field_value
);
6961 case VMCS_FIELD_TYPE_U64
:
6962 vmcs_write64(field
, (u64
)field_value
);
6964 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6965 vmcs_writel(field
, (long)field_value
);
6974 vmcs_clear(shadow_vmcs
);
6975 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6979 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6980 * used before) all generate the same failure when it is missing.
6982 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6984 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6985 if (vmx
->nested
.current_vmptr
== -1ull) {
6986 nested_vmx_failInvalid(vcpu
);
6987 skip_emulated_instruction(vcpu
);
6993 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6995 unsigned long field
;
6997 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6998 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7001 if (!nested_vmx_check_permission(vcpu
) ||
7002 !nested_vmx_check_vmcs12(vcpu
))
7005 /* Decode instruction info and find the field to read */
7006 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7007 /* Read the field, zero-extended to a u64 field_value */
7008 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7009 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7010 skip_emulated_instruction(vcpu
);
7014 * Now copy part of this value to register or memory, as requested.
7015 * Note that the number of bits actually copied is 32 or 64 depending
7016 * on the guest's mode (32 or 64 bit), not on the given field's length.
7018 if (vmx_instruction_info
& (1u << 10)) {
7019 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7022 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7023 vmx_instruction_info
, true, &gva
))
7025 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7026 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7027 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7030 nested_vmx_succeed(vcpu
);
7031 skip_emulated_instruction(vcpu
);
7036 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7038 unsigned long field
;
7040 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7041 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7042 /* The value to write might be 32 or 64 bits, depending on L1's long
7043 * mode, and eventually we need to write that into a field of several
7044 * possible lengths. The code below first zero-extends the value to 64
7045 * bit (field_value), and then copies only the approriate number of
7046 * bits into the vmcs12 field.
7048 u64 field_value
= 0;
7049 struct x86_exception e
;
7051 if (!nested_vmx_check_permission(vcpu
) ||
7052 !nested_vmx_check_vmcs12(vcpu
))
7055 if (vmx_instruction_info
& (1u << 10))
7056 field_value
= kvm_register_readl(vcpu
,
7057 (((vmx_instruction_info
) >> 3) & 0xf));
7059 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7060 vmx_instruction_info
, false, &gva
))
7062 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7063 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7064 kvm_inject_page_fault(vcpu
, &e
);
7070 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7071 if (vmcs_field_readonly(field
)) {
7072 nested_vmx_failValid(vcpu
,
7073 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7074 skip_emulated_instruction(vcpu
);
7078 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7079 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7080 skip_emulated_instruction(vcpu
);
7084 nested_vmx_succeed(vcpu
);
7085 skip_emulated_instruction(vcpu
);
7089 /* Emulate the VMPTRLD instruction */
7090 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7092 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7095 if (!nested_vmx_check_permission(vcpu
))
7098 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7101 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7102 struct vmcs12
*new_vmcs12
;
7104 page
= nested_get_page(vcpu
, vmptr
);
7106 nested_vmx_failInvalid(vcpu
);
7107 skip_emulated_instruction(vcpu
);
7110 new_vmcs12
= kmap(page
);
7111 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7113 nested_release_page_clean(page
);
7114 nested_vmx_failValid(vcpu
,
7115 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7116 skip_emulated_instruction(vcpu
);
7120 nested_release_vmcs12(vmx
);
7121 vmx
->nested
.current_vmptr
= vmptr
;
7122 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7123 vmx
->nested
.current_vmcs12_page
= page
;
7124 if (enable_shadow_vmcs
) {
7125 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7126 SECONDARY_EXEC_SHADOW_VMCS
);
7127 vmcs_write64(VMCS_LINK_POINTER
,
7128 __pa(vmx
->nested
.current_shadow_vmcs
));
7129 vmx
->nested
.sync_shadow_vmcs
= true;
7133 nested_vmx_succeed(vcpu
);
7134 skip_emulated_instruction(vcpu
);
7138 /* Emulate the VMPTRST instruction */
7139 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7141 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7142 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7144 struct x86_exception e
;
7146 if (!nested_vmx_check_permission(vcpu
))
7149 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7150 vmx_instruction_info
, true, &vmcs_gva
))
7152 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7153 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7154 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7156 kvm_inject_page_fault(vcpu
, &e
);
7159 nested_vmx_succeed(vcpu
);
7160 skip_emulated_instruction(vcpu
);
7164 /* Emulate the INVEPT instruction */
7165 static int handle_invept(struct kvm_vcpu
*vcpu
)
7167 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7168 u32 vmx_instruction_info
, types
;
7171 struct x86_exception e
;
7176 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7177 SECONDARY_EXEC_ENABLE_EPT
) ||
7178 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7179 kvm_queue_exception(vcpu
, UD_VECTOR
);
7183 if (!nested_vmx_check_permission(vcpu
))
7186 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7187 kvm_queue_exception(vcpu
, UD_VECTOR
);
7191 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7192 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7194 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7196 if (!(types
& (1UL << type
))) {
7197 nested_vmx_failValid(vcpu
,
7198 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7202 /* According to the Intel VMX instruction reference, the memory
7203 * operand is read even if it isn't needed (e.g., for type==global)
7205 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7206 vmx_instruction_info
, false, &gva
))
7208 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7209 sizeof(operand
), &e
)) {
7210 kvm_inject_page_fault(vcpu
, &e
);
7215 case VMX_EPT_EXTENT_GLOBAL
:
7216 kvm_mmu_sync_roots(vcpu
);
7217 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7218 nested_vmx_succeed(vcpu
);
7221 /* Trap single context invalidation invept calls */
7226 skip_emulated_instruction(vcpu
);
7230 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7232 kvm_queue_exception(vcpu
, UD_VECTOR
);
7236 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7238 unsigned long exit_qualification
;
7240 trace_kvm_pml_full(vcpu
->vcpu_id
);
7242 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7245 * PML buffer FULL happened while executing iret from NMI,
7246 * "blocked by NMI" bit has to be set before next VM entry.
7248 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7249 cpu_has_virtual_nmis() &&
7250 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7251 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7252 GUEST_INTR_STATE_NMI
);
7255 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7256 * here.., and there's no userspace involvement needed for PML.
7261 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7263 /* we never catch pcommit instruct for L1 guest. */
7269 * The exit handlers return 1 if the exit was handled fully and guest execution
7270 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7271 * to be done to userspace and return 0.
7273 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7274 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7275 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7276 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7277 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7278 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7279 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7280 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7281 [EXIT_REASON_CPUID
] = handle_cpuid
,
7282 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7283 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7284 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7285 [EXIT_REASON_HLT
] = handle_halt
,
7286 [EXIT_REASON_INVD
] = handle_invd
,
7287 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7288 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7289 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7290 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7291 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7292 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7293 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7294 [EXIT_REASON_VMREAD
] = handle_vmread
,
7295 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7296 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7297 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7298 [EXIT_REASON_VMON
] = handle_vmon
,
7299 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7300 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7301 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7302 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7303 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7304 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7305 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7306 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7307 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7308 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7309 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7310 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7311 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7312 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7313 [EXIT_REASON_INVEPT
] = handle_invept
,
7314 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7315 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7316 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7317 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7318 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7321 static const int kvm_vmx_max_exit_handlers
=
7322 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7324 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7325 struct vmcs12
*vmcs12
)
7327 unsigned long exit_qualification
;
7328 gpa_t bitmap
, last_bitmap
;
7333 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7334 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7336 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7338 port
= exit_qualification
>> 16;
7339 size
= (exit_qualification
& 7) + 1;
7341 last_bitmap
= (gpa_t
)-1;
7346 bitmap
= vmcs12
->io_bitmap_a
;
7347 else if (port
< 0x10000)
7348 bitmap
= vmcs12
->io_bitmap_b
;
7351 bitmap
+= (port
& 0x7fff) / 8;
7353 if (last_bitmap
!= bitmap
)
7354 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7356 if (b
& (1 << (port
& 7)))
7361 last_bitmap
= bitmap
;
7368 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7369 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7370 * disinterest in the current event (read or write a specific MSR) by using an
7371 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7373 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7374 struct vmcs12
*vmcs12
, u32 exit_reason
)
7376 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7379 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7383 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7384 * for the four combinations of read/write and low/high MSR numbers.
7385 * First we need to figure out which of the four to use:
7387 bitmap
= vmcs12
->msr_bitmap
;
7388 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7390 if (msr_index
>= 0xc0000000) {
7391 msr_index
-= 0xc0000000;
7395 /* Then read the msr_index'th bit from this bitmap: */
7396 if (msr_index
< 1024*8) {
7398 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7400 return 1 & (b
>> (msr_index
& 7));
7402 return true; /* let L1 handle the wrong parameter */
7406 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7407 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7408 * intercept (via guest_host_mask etc.) the current event.
7410 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7411 struct vmcs12
*vmcs12
)
7413 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7414 int cr
= exit_qualification
& 15;
7415 int reg
= (exit_qualification
>> 8) & 15;
7416 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7418 switch ((exit_qualification
>> 4) & 3) {
7419 case 0: /* mov to cr */
7422 if (vmcs12
->cr0_guest_host_mask
&
7423 (val
^ vmcs12
->cr0_read_shadow
))
7427 if ((vmcs12
->cr3_target_count
>= 1 &&
7428 vmcs12
->cr3_target_value0
== val
) ||
7429 (vmcs12
->cr3_target_count
>= 2 &&
7430 vmcs12
->cr3_target_value1
== val
) ||
7431 (vmcs12
->cr3_target_count
>= 3 &&
7432 vmcs12
->cr3_target_value2
== val
) ||
7433 (vmcs12
->cr3_target_count
>= 4 &&
7434 vmcs12
->cr3_target_value3
== val
))
7436 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7440 if (vmcs12
->cr4_guest_host_mask
&
7441 (vmcs12
->cr4_read_shadow
^ val
))
7445 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7451 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7452 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7455 case 1: /* mov from cr */
7458 if (vmcs12
->cpu_based_vm_exec_control
&
7459 CPU_BASED_CR3_STORE_EXITING
)
7463 if (vmcs12
->cpu_based_vm_exec_control
&
7464 CPU_BASED_CR8_STORE_EXITING
)
7471 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7472 * cr0. Other attempted changes are ignored, with no exit.
7474 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7475 (val
^ vmcs12
->cr0_read_shadow
))
7477 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7478 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7487 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7488 * should handle it ourselves in L0 (and then continue L2). Only call this
7489 * when in is_guest_mode (L2).
7491 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7493 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7494 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7495 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7496 u32 exit_reason
= vmx
->exit_reason
;
7498 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7499 vmcs_readl(EXIT_QUALIFICATION
),
7500 vmx
->idt_vectoring_info
,
7502 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7505 if (vmx
->nested
.nested_run_pending
)
7508 if (unlikely(vmx
->fail
)) {
7509 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7510 vmcs_read32(VM_INSTRUCTION_ERROR
));
7514 switch (exit_reason
) {
7515 case EXIT_REASON_EXCEPTION_NMI
:
7516 if (!is_exception(intr_info
))
7518 else if (is_page_fault(intr_info
))
7520 else if (is_no_device(intr_info
) &&
7521 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7523 return vmcs12
->exception_bitmap
&
7524 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7525 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7527 case EXIT_REASON_TRIPLE_FAULT
:
7529 case EXIT_REASON_PENDING_INTERRUPT
:
7530 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7531 case EXIT_REASON_NMI_WINDOW
:
7532 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7533 case EXIT_REASON_TASK_SWITCH
:
7535 case EXIT_REASON_CPUID
:
7536 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7539 case EXIT_REASON_HLT
:
7540 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7541 case EXIT_REASON_INVD
:
7543 case EXIT_REASON_INVLPG
:
7544 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7545 case EXIT_REASON_RDPMC
:
7546 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7547 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7548 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7549 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7550 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7551 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7552 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7553 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7554 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7556 * VMX instructions trap unconditionally. This allows L1 to
7557 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7560 case EXIT_REASON_CR_ACCESS
:
7561 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7562 case EXIT_REASON_DR_ACCESS
:
7563 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7564 case EXIT_REASON_IO_INSTRUCTION
:
7565 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7566 case EXIT_REASON_MSR_READ
:
7567 case EXIT_REASON_MSR_WRITE
:
7568 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7569 case EXIT_REASON_INVALID_STATE
:
7571 case EXIT_REASON_MWAIT_INSTRUCTION
:
7572 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7573 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7574 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7575 case EXIT_REASON_MONITOR_INSTRUCTION
:
7576 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7577 case EXIT_REASON_PAUSE_INSTRUCTION
:
7578 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7579 nested_cpu_has2(vmcs12
,
7580 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7581 case EXIT_REASON_MCE_DURING_VMENTRY
:
7583 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7584 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7585 case EXIT_REASON_APIC_ACCESS
:
7586 return nested_cpu_has2(vmcs12
,
7587 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7588 case EXIT_REASON_APIC_WRITE
:
7589 case EXIT_REASON_EOI_INDUCED
:
7590 /* apic_write and eoi_induced should exit unconditionally. */
7592 case EXIT_REASON_EPT_VIOLATION
:
7594 * L0 always deals with the EPT violation. If nested EPT is
7595 * used, and the nested mmu code discovers that the address is
7596 * missing in the guest EPT table (EPT12), the EPT violation
7597 * will be injected with nested_ept_inject_page_fault()
7600 case EXIT_REASON_EPT_MISCONFIG
:
7602 * L2 never uses directly L1's EPT, but rather L0's own EPT
7603 * table (shadow on EPT) or a merged EPT table that L0 built
7604 * (EPT on EPT). So any problems with the structure of the
7605 * table is L0's fault.
7608 case EXIT_REASON_WBINVD
:
7609 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7610 case EXIT_REASON_XSETBV
:
7612 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7614 * This should never happen, since it is not possible to
7615 * set XSS to a non-zero value---neither in L1 nor in L2.
7616 * If if it were, XSS would have to be checked against
7617 * the XSS exit bitmap in vmcs12.
7619 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7620 case EXIT_REASON_PCOMMIT
:
7621 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7627 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7629 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7630 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7633 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7635 struct page
*pml_pg
;
7637 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7641 vmx
->pml_pg
= pml_pg
;
7643 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7644 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7646 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7651 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7653 ASSERT(vmx
->pml_pg
);
7654 __free_page(vmx
->pml_pg
);
7657 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7660 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7666 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7668 /* Do nothing if PML buffer is empty */
7669 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7672 /* PML index always points to next available PML buffer entity */
7673 if (pml_idx
>= PML_ENTITY_NUM
)
7678 pml_buf
= page_address(vmx
->pml_pg
);
7679 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7682 gpa
= pml_buf
[pml_idx
];
7683 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7684 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7687 /* reset PML index */
7688 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7692 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7693 * Called before reporting dirty_bitmap to userspace.
7695 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7698 struct kvm_vcpu
*vcpu
;
7700 * We only need to kick vcpu out of guest mode here, as PML buffer
7701 * is flushed at beginning of all VMEXITs, and it's obvious that only
7702 * vcpus running in guest are possible to have unflushed GPAs in PML
7705 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7706 kvm_vcpu_kick(vcpu
);
7709 static void vmx_dump_sel(char *name
, uint32_t sel
)
7711 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7712 name
, vmcs_read32(sel
),
7713 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7714 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7715 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7718 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7720 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7721 name
, vmcs_read32(limit
),
7722 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7725 static void dump_vmcs(void)
7727 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7728 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7729 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7730 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7731 u32 secondary_exec_control
= 0;
7732 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7733 u64 efer
= vmcs_readl(GUEST_IA32_EFER
);
7736 if (cpu_has_secondary_exec_ctrls())
7737 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7739 pr_err("*** Guest State ***\n");
7740 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7741 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7742 vmcs_readl(CR0_GUEST_HOST_MASK
));
7743 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7744 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7745 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7746 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7747 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7749 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7750 vmcs_readl(GUEST_PDPTR0
), vmcs_readl(GUEST_PDPTR1
));
7751 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7752 vmcs_readl(GUEST_PDPTR2
), vmcs_readl(GUEST_PDPTR3
));
7754 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7755 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
7756 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7757 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
7758 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7759 vmcs_readl(GUEST_SYSENTER_ESP
),
7760 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
7761 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
7762 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
7763 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
7764 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
7765 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
7766 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
7767 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
7768 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
7769 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
7770 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
7771 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
7772 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
7773 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7774 efer
, vmcs_readl(GUEST_IA32_PAT
));
7775 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7776 vmcs_readl(GUEST_IA32_DEBUGCTL
),
7777 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
7778 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
7779 pr_err("PerfGlobCtl = 0x%016lx\n",
7780 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL
));
7781 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
7782 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS
));
7783 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7784 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
7785 vmcs_read32(GUEST_ACTIVITY_STATE
));
7786 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
7787 pr_err("InterruptStatus = %04x\n",
7788 vmcs_read16(GUEST_INTR_STATUS
));
7790 pr_err("*** Host State ***\n");
7791 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7792 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
7793 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7794 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
7795 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
7796 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
7797 vmcs_read16(HOST_TR_SELECTOR
));
7798 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7799 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
7800 vmcs_readl(HOST_TR_BASE
));
7801 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7802 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
7803 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7804 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
7805 vmcs_readl(HOST_CR4
));
7806 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7807 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
7808 vmcs_read32(HOST_IA32_SYSENTER_CS
),
7809 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
7810 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
7811 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7812 vmcs_readl(HOST_IA32_EFER
), vmcs_readl(HOST_IA32_PAT
));
7813 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7814 pr_err("PerfGlobCtl = 0x%016lx\n",
7815 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL
));
7817 pr_err("*** Control State ***\n");
7818 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7819 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
7820 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
7821 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7822 vmcs_read32(EXCEPTION_BITMAP
),
7823 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
7824 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
7825 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7826 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7827 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
7828 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
7829 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7830 vmcs_read32(VM_EXIT_INTR_INFO
),
7831 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7832 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
7833 pr_err(" reason=%08x qualification=%016lx\n",
7834 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
7835 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7836 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
7837 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
7838 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET
));
7839 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
7840 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
7841 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
7842 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
7843 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
7844 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER
));
7845 n
= vmcs_read32(CR3_TARGET_COUNT
);
7846 for (i
= 0; i
+ 1 < n
; i
+= 4)
7847 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7848 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
7849 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
7851 pr_err("CR3 target%u=%016lx\n",
7852 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
7853 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
7854 pr_err("PLE Gap=%08x Window=%08x\n",
7855 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
7856 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
7857 pr_err("Virtual processor ID = 0x%04x\n",
7858 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
7862 * The guest has exited. See if we can fix it or if we need userspace
7865 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7867 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7868 u32 exit_reason
= vmx
->exit_reason
;
7869 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7872 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7873 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7874 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7875 * mode as if vcpus is in root mode, the PML buffer must has been
7879 vmx_flush_pml_buffer(vcpu
);
7881 /* If guest state is invalid, start emulating */
7882 if (vmx
->emulation_required
)
7883 return handle_invalid_guest_state(vcpu
);
7885 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7886 nested_vmx_vmexit(vcpu
, exit_reason
,
7887 vmcs_read32(VM_EXIT_INTR_INFO
),
7888 vmcs_readl(EXIT_QUALIFICATION
));
7892 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7894 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7895 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7900 if (unlikely(vmx
->fail
)) {
7901 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7902 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7903 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7909 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7910 * delivery event since it indicates guest is accessing MMIO.
7911 * The vm-exit can be triggered again after return to guest that
7912 * will cause infinite loop.
7914 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7915 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7916 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7917 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7918 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7919 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7920 vcpu
->run
->internal
.ndata
= 2;
7921 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7922 vcpu
->run
->internal
.data
[1] = exit_reason
;
7926 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7927 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7928 get_vmcs12(vcpu
))))) {
7929 if (vmx_interrupt_allowed(vcpu
)) {
7930 vmx
->soft_vnmi_blocked
= 0;
7931 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7932 vcpu
->arch
.nmi_pending
) {
7934 * This CPU don't support us in finding the end of an
7935 * NMI-blocked window if the guest runs with IRQs
7936 * disabled. So we pull the trigger after 1 s of
7937 * futile waiting, but inform the user about this.
7939 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7940 "state on VCPU %d after 1 s timeout\n",
7941 __func__
, vcpu
->vcpu_id
);
7942 vmx
->soft_vnmi_blocked
= 0;
7946 if (exit_reason
< kvm_vmx_max_exit_handlers
7947 && kvm_vmx_exit_handlers
[exit_reason
])
7948 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7950 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7951 kvm_queue_exception(vcpu
, UD_VECTOR
);
7956 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7958 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7960 if (is_guest_mode(vcpu
) &&
7961 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7964 if (irr
== -1 || tpr
< irr
) {
7965 vmcs_write32(TPR_THRESHOLD
, 0);
7969 vmcs_write32(TPR_THRESHOLD
, irr
);
7972 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7974 u32 sec_exec_control
;
7977 * There is not point to enable virtualize x2apic without enable
7980 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7981 !vmx_cpu_uses_apicv(vcpu
))
7984 if (!cpu_need_tpr_shadow(vcpu
))
7987 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7990 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7991 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7993 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7994 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7996 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7998 vmx_set_msr_bitmap(vcpu
);
8001 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8003 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8006 * Currently we do not handle the nested case where L2 has an
8007 * APIC access page of its own; that page is still pinned.
8008 * Hence, we skip the case where the VCPU is in guest mode _and_
8009 * L1 prepared an APIC access page for L2.
8011 * For the case where L1 and L2 share the same APIC access page
8012 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8013 * in the vmcs12), this function will only update either the vmcs01
8014 * or the vmcs02. If the former, the vmcs02 will be updated by
8015 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8016 * the next L2->L1 exit.
8018 if (!is_guest_mode(vcpu
) ||
8019 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8020 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8021 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8024 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
8032 status
= vmcs_read16(GUEST_INTR_STATUS
);
8037 vmcs_write16(GUEST_INTR_STATUS
, status
);
8041 static void vmx_set_rvi(int vector
)
8049 status
= vmcs_read16(GUEST_INTR_STATUS
);
8050 old
= (u8
)status
& 0xff;
8051 if ((u8
)vector
!= old
) {
8053 status
|= (u8
)vector
;
8054 vmcs_write16(GUEST_INTR_STATUS
, status
);
8058 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8060 if (!is_guest_mode(vcpu
)) {
8061 vmx_set_rvi(max_irr
);
8069 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8072 if (nested_exit_on_intr(vcpu
))
8076 * Else, fall back to pre-APICv interrupt injection since L2
8077 * is run without virtual interrupt delivery.
8079 if (!kvm_event_needs_reinjection(vcpu
) &&
8080 vmx_interrupt_allowed(vcpu
)) {
8081 kvm_queue_interrupt(vcpu
, max_irr
, false);
8082 vmx_inject_irq(vcpu
);
8086 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
8088 u64
*eoi_exit_bitmap
= vcpu
->arch
.eoi_exit_bitmap
;
8089 if (!vmx_cpu_uses_apicv(vcpu
))
8092 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8093 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8094 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8095 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8098 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8102 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8103 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8106 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8107 exit_intr_info
= vmx
->exit_intr_info
;
8109 /* Handle machine checks before interrupts are enabled */
8110 if (is_machine_check(exit_intr_info
))
8111 kvm_machine_check();
8113 /* We need to handle NMIs before interrupts are enabled */
8114 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8115 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8116 kvm_before_handle_nmi(&vmx
->vcpu
);
8118 kvm_after_handle_nmi(&vmx
->vcpu
);
8122 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8124 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8127 * If external interrupt exists, IF bit is set in rflags/eflags on the
8128 * interrupt stack frame, and interrupt will be enabled on a return
8129 * from interrupt handler.
8131 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8132 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8133 unsigned int vector
;
8134 unsigned long entry
;
8136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8137 #ifdef CONFIG_X86_64
8141 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8142 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8143 entry
= gate_offset(*desc
);
8145 #ifdef CONFIG_X86_64
8146 "mov %%" _ASM_SP
", %[sp]\n\t"
8147 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8152 "orl $0x200, (%%" _ASM_SP
")\n\t"
8153 __ASM_SIZE(push
) " $%c[cs]\n\t"
8154 "call *%[entry]\n\t"
8156 #ifdef CONFIG_X86_64
8161 [ss
]"i"(__KERNEL_DS
),
8162 [cs
]"i"(__KERNEL_CS
)
8168 static bool vmx_has_high_real_mode_segbase(void)
8170 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8173 static bool vmx_mpx_supported(void)
8175 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8176 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8179 static bool vmx_xsaves_supported(void)
8181 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8182 SECONDARY_EXEC_XSAVES
;
8185 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8190 bool idtv_info_valid
;
8192 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8194 if (cpu_has_virtual_nmis()) {
8195 if (vmx
->nmi_known_unmasked
)
8198 * Can't use vmx->exit_intr_info since we're not sure what
8199 * the exit reason is.
8201 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8202 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8203 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8205 * SDM 3: 27.7.1.2 (September 2008)
8206 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8207 * a guest IRET fault.
8208 * SDM 3: 23.2.2 (September 2008)
8209 * Bit 12 is undefined in any of the following cases:
8210 * If the VM exit sets the valid bit in the IDT-vectoring
8211 * information field.
8212 * If the VM exit is due to a double fault.
8214 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8215 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8216 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8217 GUEST_INTR_STATE_NMI
);
8219 vmx
->nmi_known_unmasked
=
8220 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8221 & GUEST_INTR_STATE_NMI
);
8222 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8223 vmx
->vnmi_blocked_time
+=
8224 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8227 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8228 u32 idt_vectoring_info
,
8229 int instr_len_field
,
8230 int error_code_field
)
8234 bool idtv_info_valid
;
8236 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8238 vcpu
->arch
.nmi_injected
= false;
8239 kvm_clear_exception_queue(vcpu
);
8240 kvm_clear_interrupt_queue(vcpu
);
8242 if (!idtv_info_valid
)
8245 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8247 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8248 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8251 case INTR_TYPE_NMI_INTR
:
8252 vcpu
->arch
.nmi_injected
= true;
8254 * SDM 3: 27.7.1.2 (September 2008)
8255 * Clear bit "block by NMI" before VM entry if a NMI
8258 vmx_set_nmi_mask(vcpu
, false);
8260 case INTR_TYPE_SOFT_EXCEPTION
:
8261 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8263 case INTR_TYPE_HARD_EXCEPTION
:
8264 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8265 u32 err
= vmcs_read32(error_code_field
);
8266 kvm_requeue_exception_e(vcpu
, vector
, err
);
8268 kvm_requeue_exception(vcpu
, vector
);
8270 case INTR_TYPE_SOFT_INTR
:
8271 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8273 case INTR_TYPE_EXT_INTR
:
8274 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8281 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8283 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8284 VM_EXIT_INSTRUCTION_LEN
,
8285 IDT_VECTORING_ERROR_CODE
);
8288 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8290 __vmx_complete_interrupts(vcpu
,
8291 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8292 VM_ENTRY_INSTRUCTION_LEN
,
8293 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8295 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8298 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8301 struct perf_guest_switch_msr
*msrs
;
8303 msrs
= perf_guest_get_msrs(&nr_msrs
);
8308 for (i
= 0; i
< nr_msrs
; i
++)
8309 if (msrs
[i
].host
== msrs
[i
].guest
)
8310 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8312 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8316 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8318 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8319 unsigned long debugctlmsr
, cr4
;
8321 /* Record the guest's net vcpu time for enforced NMI injections. */
8322 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8323 vmx
->entry_time
= ktime_get();
8325 /* Don't enter VMX if guest state is invalid, let the exit handler
8326 start emulation until we arrive back to a valid state */
8327 if (vmx
->emulation_required
)
8330 if (vmx
->ple_window_dirty
) {
8331 vmx
->ple_window_dirty
= false;
8332 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8335 if (vmx
->nested
.sync_shadow_vmcs
) {
8336 copy_vmcs12_to_shadow(vmx
);
8337 vmx
->nested
.sync_shadow_vmcs
= false;
8340 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8341 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8342 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8343 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8345 cr4
= cr4_read_shadow();
8346 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8347 vmcs_writel(HOST_CR4
, cr4
);
8348 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8351 /* When single-stepping over STI and MOV SS, we must clear the
8352 * corresponding interruptibility bits in the guest state. Otherwise
8353 * vmentry fails as it then expects bit 14 (BS) in pending debug
8354 * exceptions being set, but that's not correct for the guest debugging
8356 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8357 vmx_set_interrupt_shadow(vcpu
, 0);
8359 atomic_switch_perf_msrs(vmx
);
8360 debugctlmsr
= get_debugctlmsr();
8362 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8364 /* Store host registers */
8365 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8366 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8367 "push %%" _ASM_CX
" \n\t"
8368 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8370 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8371 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8373 /* Reload cr2 if changed */
8374 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8375 "mov %%cr2, %%" _ASM_DX
" \n\t"
8376 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8378 "mov %%" _ASM_AX
", %%cr2 \n\t"
8380 /* Check if vmlaunch of vmresume is needed */
8381 "cmpl $0, %c[launched](%0) \n\t"
8382 /* Load guest registers. Don't clobber flags. */
8383 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8384 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8385 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8386 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8387 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8388 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8389 #ifdef CONFIG_X86_64
8390 "mov %c[r8](%0), %%r8 \n\t"
8391 "mov %c[r9](%0), %%r9 \n\t"
8392 "mov %c[r10](%0), %%r10 \n\t"
8393 "mov %c[r11](%0), %%r11 \n\t"
8394 "mov %c[r12](%0), %%r12 \n\t"
8395 "mov %c[r13](%0), %%r13 \n\t"
8396 "mov %c[r14](%0), %%r14 \n\t"
8397 "mov %c[r15](%0), %%r15 \n\t"
8399 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8401 /* Enter guest mode */
8403 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8405 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8407 /* Save guest registers, load host registers, keep flags */
8408 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8410 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8411 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8412 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8413 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8414 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8415 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8416 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8417 #ifdef CONFIG_X86_64
8418 "mov %%r8, %c[r8](%0) \n\t"
8419 "mov %%r9, %c[r9](%0) \n\t"
8420 "mov %%r10, %c[r10](%0) \n\t"
8421 "mov %%r11, %c[r11](%0) \n\t"
8422 "mov %%r12, %c[r12](%0) \n\t"
8423 "mov %%r13, %c[r13](%0) \n\t"
8424 "mov %%r14, %c[r14](%0) \n\t"
8425 "mov %%r15, %c[r15](%0) \n\t"
8427 "mov %%cr2, %%" _ASM_AX
" \n\t"
8428 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8430 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8431 "setbe %c[fail](%0) \n\t"
8432 ".pushsection .rodata \n\t"
8433 ".global vmx_return \n\t"
8434 "vmx_return: " _ASM_PTR
" 2b \n\t"
8436 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8437 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8438 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8439 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8440 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8441 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8442 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8443 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8444 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8445 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8446 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8447 #ifdef CONFIG_X86_64
8448 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8449 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8450 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8451 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8452 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8453 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8454 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8455 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8457 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8458 [wordsize
]"i"(sizeof(ulong
))
8460 #ifdef CONFIG_X86_64
8461 , "rax", "rbx", "rdi", "rsi"
8462 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8464 , "eax", "ebx", "edi", "esi"
8468 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8470 update_debugctlmsr(debugctlmsr
);
8472 #ifndef CONFIG_X86_64
8474 * The sysexit path does not restore ds/es, so we must set them to
8475 * a reasonable value ourselves.
8477 * We can't defer this to vmx_load_host_state() since that function
8478 * may be executed in interrupt context, which saves and restore segments
8479 * around it, nullifying its effect.
8481 loadsegment(ds
, __USER_DS
);
8482 loadsegment(es
, __USER_DS
);
8485 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8486 | (1 << VCPU_EXREG_RFLAGS
)
8487 | (1 << VCPU_EXREG_PDPTR
)
8488 | (1 << VCPU_EXREG_SEGMENTS
)
8489 | (1 << VCPU_EXREG_CR3
));
8490 vcpu
->arch
.regs_dirty
= 0;
8492 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8494 vmx
->loaded_vmcs
->launched
= 1;
8496 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8497 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8500 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8501 * we did not inject a still-pending event to L1 now because of
8502 * nested_run_pending, we need to re-enable this bit.
8504 if (vmx
->nested
.nested_run_pending
)
8505 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8507 vmx
->nested
.nested_run_pending
= 0;
8509 vmx_complete_atomic_exit(vmx
);
8510 vmx_recover_nmi_blocking(vmx
);
8511 vmx_complete_interrupts(vmx
);
8514 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8519 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8523 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8525 vmx_vcpu_load(vcpu
, cpu
);
8530 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8532 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8535 vmx_disable_pml(vmx
);
8537 leave_guest_mode(vcpu
);
8538 vmx_load_vmcs01(vcpu
);
8540 free_loaded_vmcs(vmx
->loaded_vmcs
);
8541 kfree(vmx
->guest_msrs
);
8542 kvm_vcpu_uninit(vcpu
);
8543 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8546 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8549 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8553 return ERR_PTR(-ENOMEM
);
8557 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8561 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8562 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8566 if (!vmx
->guest_msrs
) {
8570 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8571 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8572 if (!vmx
->loaded_vmcs
->vmcs
)
8575 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8576 loaded_vmcs_init(vmx
->loaded_vmcs
);
8581 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8582 vmx
->vcpu
.cpu
= cpu
;
8583 err
= vmx_vcpu_setup(vmx
);
8584 vmx_vcpu_put(&vmx
->vcpu
);
8588 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8589 err
= alloc_apic_access_page(kvm
);
8595 if (!kvm
->arch
.ept_identity_map_addr
)
8596 kvm
->arch
.ept_identity_map_addr
=
8597 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8598 err
= init_rmode_identity_map(kvm
);
8604 nested_vmx_setup_ctls_msrs(vmx
);
8606 vmx
->nested
.posted_intr_nv
= -1;
8607 vmx
->nested
.current_vmptr
= -1ull;
8608 vmx
->nested
.current_vmcs12
= NULL
;
8611 * If PML is turned on, failure on enabling PML just results in failure
8612 * of creating the vcpu, therefore we can simplify PML logic (by
8613 * avoiding dealing with cases, such as enabling PML partially on vcpus
8614 * for the guest, etc.
8617 err
= vmx_enable_pml(vmx
);
8625 free_loaded_vmcs(vmx
->loaded_vmcs
);
8627 kfree(vmx
->guest_msrs
);
8629 kvm_vcpu_uninit(&vmx
->vcpu
);
8632 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8633 return ERR_PTR(err
);
8636 static void __init
vmx_check_processor_compat(void *rtn
)
8638 struct vmcs_config vmcs_conf
;
8641 if (setup_vmcs_config(&vmcs_conf
) < 0)
8643 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8644 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8645 smp_processor_id());
8650 static int get_ept_level(void)
8652 return VMX_EPT_DEFAULT_GAW
+ 1;
8655 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8660 /* For VT-d and EPT combination
8661 * 1. MMIO: always map as UC
8663 * a. VT-d without snooping control feature: can't guarantee the
8664 * result, try to trust guest.
8665 * b. VT-d with snooping control feature: snooping control feature of
8666 * VT-d engine can guarantee the cache correctness. Just set it
8667 * to WB to keep consistent with host. So the same as item 3.
8668 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8669 * consistent with host MTRR
8672 cache
= MTRR_TYPE_UNCACHABLE
;
8676 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8677 ipat
= VMX_EPT_IPAT_BIT
;
8678 cache
= MTRR_TYPE_WRBACK
;
8682 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8683 ipat
= VMX_EPT_IPAT_BIT
;
8684 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8685 cache
= MTRR_TYPE_WRBACK
;
8687 cache
= MTRR_TYPE_UNCACHABLE
;
8691 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8694 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8697 static int vmx_get_lpage_level(void)
8699 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8700 return PT_DIRECTORY_LEVEL
;
8702 /* For shadow and EPT supported 1GB page */
8703 return PT_PDPE_LEVEL
;
8706 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
8709 * These bits in the secondary execution controls field
8710 * are dynamic, the others are mostly based on the hypervisor
8711 * architecture and the guest's CPUID. Do not touch the
8715 SECONDARY_EXEC_SHADOW_VMCS
|
8716 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
8717 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8719 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8721 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8722 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
8725 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8727 struct kvm_cpuid_entry2
*best
;
8728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8729 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
8731 if (vmx_rdtscp_supported()) {
8732 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
8733 if (!rdtscp_enabled
)
8734 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
8738 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8739 SECONDARY_EXEC_RDTSCP
;
8741 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8742 ~SECONDARY_EXEC_RDTSCP
;
8746 /* Exposing INVPCID only when PCID is exposed */
8747 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8748 if (vmx_invpcid_supported() &&
8749 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
8750 !guest_cpuid_has_pcid(vcpu
))) {
8751 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8754 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8757 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
8759 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
8760 if (guest_cpuid_has_pcommit(vcpu
))
8761 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8762 SECONDARY_EXEC_PCOMMIT
;
8764 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8765 ~SECONDARY_EXEC_PCOMMIT
;
8769 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8771 if (func
== 1 && nested
)
8772 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8775 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8776 struct x86_exception
*fault
)
8778 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8781 if (fault
->error_code
& PFERR_RSVD_MASK
)
8782 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8784 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8785 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8786 vmcs12
->guest_physical_address
= fault
->address
;
8789 /* Callbacks for nested_ept_init_mmu_context: */
8791 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8793 /* return the page table to be shadowed - in our case, EPT12 */
8794 return get_vmcs12(vcpu
)->ept_pointer
;
8797 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8799 WARN_ON(mmu_is_nested(vcpu
));
8800 kvm_init_shadow_ept_mmu(vcpu
,
8801 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8802 VMX_EPT_EXECUTE_ONLY_BIT
);
8803 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8804 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8805 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8807 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8810 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8812 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8815 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8818 bool inequality
, bit
;
8820 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8822 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
8823 vmcs12
->page_fault_error_code_match
;
8824 return inequality
^ bit
;
8827 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8828 struct x86_exception
*fault
)
8830 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8832 WARN_ON(!is_guest_mode(vcpu
));
8834 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
8835 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8836 vmcs_read32(VM_EXIT_INTR_INFO
),
8837 vmcs_readl(EXIT_QUALIFICATION
));
8839 kvm_inject_page_fault(vcpu
, fault
);
8842 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8843 struct vmcs12
*vmcs12
)
8845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8846 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8848 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8849 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
8850 vmcs12
->apic_access_addr
>> maxphyaddr
)
8854 * Translate L1 physical address to host physical
8855 * address for vmcs02. Keep the page pinned, so this
8856 * physical address remains valid. We keep a reference
8857 * to it so we can release it later.
8859 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8860 nested_release_page(vmx
->nested
.apic_access_page
);
8861 vmx
->nested
.apic_access_page
=
8862 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8865 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8866 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
8867 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
8870 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8871 nested_release_page(vmx
->nested
.virtual_apic_page
);
8872 vmx
->nested
.virtual_apic_page
=
8873 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8876 * Failing the vm entry is _not_ what the processor does
8877 * but it's basically the only possibility we have.
8878 * We could still enter the guest if CR8 load exits are
8879 * enabled, CR8 store exits are enabled, and virtualize APIC
8880 * access is disabled; in this case the processor would never
8881 * use the TPR shadow and we could simply clear the bit from
8882 * the execution control. But such a configuration is useless,
8883 * so let's keep the code simple.
8885 if (!vmx
->nested
.virtual_apic_page
)
8889 if (nested_cpu_has_posted_intr(vmcs12
)) {
8890 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
8891 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
8894 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
8895 kunmap(vmx
->nested
.pi_desc_page
);
8896 nested_release_page(vmx
->nested
.pi_desc_page
);
8898 vmx
->nested
.pi_desc_page
=
8899 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
8900 if (!vmx
->nested
.pi_desc_page
)
8903 vmx
->nested
.pi_desc
=
8904 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
8905 if (!vmx
->nested
.pi_desc
) {
8906 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
8909 vmx
->nested
.pi_desc
=
8910 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
8911 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
8918 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8920 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8923 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8926 /* Make sure short timeouts reliably trigger an immediate vmexit.
8927 * hrtimer_start does not guarantee this. */
8928 if (preemption_timeout
<= 1) {
8929 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8933 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8934 preemption_timeout
*= 1000000;
8935 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8936 hrtimer_start(&vmx
->nested
.preemption_timer
,
8937 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8940 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
8941 struct vmcs12
*vmcs12
)
8946 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8949 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
8953 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8955 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
8956 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
8963 * Merge L0's and L1's MSR bitmap, return false to indicate that
8964 * we do not use the hardware.
8966 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
8967 struct vmcs12
*vmcs12
)
8971 unsigned long *msr_bitmap
;
8973 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
8976 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
8981 msr_bitmap
= (unsigned long *)kmap(page
);
8983 nested_release_page_clean(page
);
8988 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
8989 if (nested_cpu_has_apic_reg_virt(vmcs12
))
8990 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8991 nested_vmx_disable_intercept_for_msr(
8993 vmx_msr_bitmap_nested
,
8995 /* TPR is allowed */
8996 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
8997 vmx_msr_bitmap_nested
,
8998 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8999 MSR_TYPE_R
| MSR_TYPE_W
);
9000 if (nested_cpu_has_vid(vmcs12
)) {
9001 /* EOI and self-IPI are allowed */
9002 nested_vmx_disable_intercept_for_msr(
9004 vmx_msr_bitmap_nested
,
9005 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9007 nested_vmx_disable_intercept_for_msr(
9009 vmx_msr_bitmap_nested
,
9010 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9015 * Enable reading intercept of all the x2apic
9016 * MSRs. We should not rely on vmcs12 to do any
9017 * optimizations here, it may have been modified
9020 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9021 __vmx_enable_intercept_for_msr(
9022 vmx_msr_bitmap_nested
,
9026 __vmx_enable_intercept_for_msr(
9027 vmx_msr_bitmap_nested
,
9028 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9030 __vmx_enable_intercept_for_msr(
9031 vmx_msr_bitmap_nested
,
9032 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9034 __vmx_enable_intercept_for_msr(
9035 vmx_msr_bitmap_nested
,
9036 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9040 nested_release_page_clean(page
);
9045 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9046 struct vmcs12
*vmcs12
)
9048 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9049 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9050 !nested_cpu_has_vid(vmcs12
) &&
9051 !nested_cpu_has_posted_intr(vmcs12
))
9055 * If virtualize x2apic mode is enabled,
9056 * virtualize apic access must be disabled.
9058 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9059 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9063 * If virtual interrupt delivery is enabled,
9064 * we must exit on external interrupts.
9066 if (nested_cpu_has_vid(vmcs12
) &&
9067 !nested_exit_on_intr(vcpu
))
9071 * bits 15:8 should be zero in posted_intr_nv,
9072 * the descriptor address has been already checked
9073 * in nested_get_vmcs12_pages.
9075 if (nested_cpu_has_posted_intr(vmcs12
) &&
9076 (!nested_cpu_has_vid(vmcs12
) ||
9077 !nested_exit_intr_ack_set(vcpu
) ||
9078 vmcs12
->posted_intr_nv
& 0xff00))
9081 /* tpr shadow is needed by all apicv features. */
9082 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9088 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9089 unsigned long count_field
,
9090 unsigned long addr_field
)
9095 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9096 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9102 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9103 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9104 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9105 pr_warn_ratelimited(
9106 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9107 addr_field
, maxphyaddr
, count
, addr
);
9113 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9114 struct vmcs12
*vmcs12
)
9116 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9117 vmcs12
->vm_exit_msr_store_count
== 0 &&
9118 vmcs12
->vm_entry_msr_load_count
== 0)
9119 return 0; /* Fast path */
9120 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9121 VM_EXIT_MSR_LOAD_ADDR
) ||
9122 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9123 VM_EXIT_MSR_STORE_ADDR
) ||
9124 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9125 VM_ENTRY_MSR_LOAD_ADDR
))
9130 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9131 struct vmx_msr_entry
*e
)
9133 /* x2APIC MSR accesses are not allowed */
9134 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9136 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9137 e
->index
== MSR_IA32_UCODE_REV
)
9139 if (e
->reserved
!= 0)
9144 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9145 struct vmx_msr_entry
*e
)
9147 if (e
->index
== MSR_FS_BASE
||
9148 e
->index
== MSR_GS_BASE
||
9149 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9150 nested_vmx_msr_check_common(vcpu
, e
))
9155 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9156 struct vmx_msr_entry
*e
)
9158 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9159 nested_vmx_msr_check_common(vcpu
, e
))
9165 * Load guest's/host's msr at nested entry/exit.
9166 * return 0 for success, entry index for failure.
9168 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9171 struct vmx_msr_entry e
;
9172 struct msr_data msr
;
9174 msr
.host_initiated
= false;
9175 for (i
= 0; i
< count
; i
++) {
9176 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9178 pr_warn_ratelimited(
9179 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9180 __func__
, i
, gpa
+ i
* sizeof(e
));
9183 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9184 pr_warn_ratelimited(
9185 "%s check failed (%u, 0x%x, 0x%x)\n",
9186 __func__
, i
, e
.index
, e
.reserved
);
9189 msr
.index
= e
.index
;
9191 if (kvm_set_msr(vcpu
, &msr
)) {
9192 pr_warn_ratelimited(
9193 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9194 __func__
, i
, e
.index
, e
.value
);
9203 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9206 struct vmx_msr_entry e
;
9208 for (i
= 0; i
< count
; i
++) {
9209 struct msr_data msr_info
;
9210 if (kvm_vcpu_read_guest(vcpu
,
9211 gpa
+ i
* sizeof(e
),
9212 &e
, 2 * sizeof(u32
))) {
9213 pr_warn_ratelimited(
9214 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9215 __func__
, i
, gpa
+ i
* sizeof(e
));
9218 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9219 pr_warn_ratelimited(
9220 "%s check failed (%u, 0x%x, 0x%x)\n",
9221 __func__
, i
, e
.index
, e
.reserved
);
9224 msr_info
.host_initiated
= false;
9225 msr_info
.index
= e
.index
;
9226 if (kvm_get_msr(vcpu
, &msr_info
)) {
9227 pr_warn_ratelimited(
9228 "%s cannot read MSR (%u, 0x%x)\n",
9229 __func__
, i
, e
.index
);
9232 if (kvm_vcpu_write_guest(vcpu
,
9233 gpa
+ i
* sizeof(e
) +
9234 offsetof(struct vmx_msr_entry
, value
),
9235 &msr_info
.data
, sizeof(msr_info
.data
))) {
9236 pr_warn_ratelimited(
9237 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9238 __func__
, i
, e
.index
, msr_info
.data
);
9246 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9247 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9248 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9249 * guest in a way that will both be appropriate to L1's requests, and our
9250 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9251 * function also has additional necessary side-effects, like setting various
9252 * vcpu->arch fields.
9254 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9259 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9260 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9261 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9262 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9263 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9264 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9265 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9266 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9267 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9268 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9269 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9270 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9271 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9272 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9273 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9274 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9275 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9276 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9277 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9278 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9279 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9280 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9281 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9282 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9283 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9284 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9285 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9286 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9287 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9288 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9289 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9290 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9291 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9292 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9293 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9294 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9296 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9297 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9298 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9300 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9301 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9303 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9304 vmcs12
->vm_entry_intr_info_field
);
9305 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9306 vmcs12
->vm_entry_exception_error_code
);
9307 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9308 vmcs12
->vm_entry_instruction_len
);
9309 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9310 vmcs12
->guest_interruptibility_info
);
9311 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9312 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9313 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9314 vmcs12
->guest_pending_dbg_exceptions
);
9315 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9316 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9318 if (nested_cpu_has_xsaves(vmcs12
))
9319 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9320 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9322 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9323 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9324 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9326 if (nested_cpu_has_posted_intr(vmcs12
)) {
9328 * Note that we use L0's vector here and in
9329 * vmx_deliver_nested_posted_interrupt.
9331 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9332 vmx
->nested
.pi_pending
= false;
9333 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9334 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9335 page_to_phys(vmx
->nested
.pi_desc_page
) +
9336 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9339 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9341 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9343 vmx
->nested
.preemption_timer_expired
= false;
9344 if (nested_cpu_has_preemption_timer(vmcs12
))
9345 vmx_start_preemption_timer(vcpu
);
9348 * Whether page-faults are trapped is determined by a combination of
9349 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9350 * If enable_ept, L0 doesn't care about page faults and we should
9351 * set all of these to L1's desires. However, if !enable_ept, L0 does
9352 * care about (at least some) page faults, and because it is not easy
9353 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9354 * to exit on each and every L2 page fault. This is done by setting
9355 * MASK=MATCH=0 and (see below) EB.PF=1.
9356 * Note that below we don't need special code to set EB.PF beyond the
9357 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9358 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9359 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9361 * A problem with this approach (when !enable_ept) is that L1 may be
9362 * injected with more page faults than it asked for. This could have
9363 * caused problems, but in practice existing hypervisors don't care.
9364 * To fix this, we will need to emulate the PFEC checking (on the L1
9365 * page tables), using walk_addr(), when injecting PFs to L1.
9367 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9368 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9369 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9370 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9372 if (cpu_has_secondary_exec_ctrls()) {
9373 exec_control
= vmx_secondary_exec_control(vmx
);
9375 /* Take the following fields only from vmcs12 */
9376 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9377 SECONDARY_EXEC_RDTSCP
|
9378 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9379 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9380 SECONDARY_EXEC_PCOMMIT
);
9381 if (nested_cpu_has(vmcs12
,
9382 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9383 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9385 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9387 * If translation failed, no matter: This feature asks
9388 * to exit when accessing the given address, and if it
9389 * can never be accessed, this feature won't do
9392 if (!vmx
->nested
.apic_access_page
)
9394 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9396 vmcs_write64(APIC_ACCESS_ADDR
,
9397 page_to_phys(vmx
->nested
.apic_access_page
));
9398 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9399 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9401 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9402 kvm_vcpu_reload_apic_access_page(vcpu
);
9405 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9406 vmcs_write64(EOI_EXIT_BITMAP0
,
9407 vmcs12
->eoi_exit_bitmap0
);
9408 vmcs_write64(EOI_EXIT_BITMAP1
,
9409 vmcs12
->eoi_exit_bitmap1
);
9410 vmcs_write64(EOI_EXIT_BITMAP2
,
9411 vmcs12
->eoi_exit_bitmap2
);
9412 vmcs_write64(EOI_EXIT_BITMAP3
,
9413 vmcs12
->eoi_exit_bitmap3
);
9414 vmcs_write16(GUEST_INTR_STATUS
,
9415 vmcs12
->guest_intr_status
);
9418 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9423 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9424 * Some constant fields are set here by vmx_set_constant_host_state().
9425 * Other fields are different per CPU, and will be set later when
9426 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9428 vmx_set_constant_host_state(vmx
);
9431 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9432 * entry, but only if the current (host) sp changed from the value
9433 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9434 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9435 * here we just force the write to happen on entry.
9439 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9440 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9441 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9442 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9443 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9445 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9446 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9447 page_to_phys(vmx
->nested
.virtual_apic_page
));
9448 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9451 if (cpu_has_vmx_msr_bitmap() &&
9452 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9453 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9454 /* MSR_BITMAP will be set by following vmx_set_efer. */
9456 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9459 * Merging of IO bitmap not currently supported.
9460 * Rather, exit every time.
9462 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9463 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9465 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9467 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9468 * bitwise-or of what L1 wants to trap for L2, and what we want to
9469 * trap. Note that CR0.TS also needs updating - we do this later.
9471 update_exception_bitmap(vcpu
);
9472 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9473 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9475 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9476 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9477 * bits are further modified by vmx_set_efer() below.
9479 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9481 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9482 * emulated by vmx_set_efer(), below.
9484 vm_entry_controls_init(vmx
,
9485 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9486 ~VM_ENTRY_IA32E_MODE
) |
9487 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9489 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9490 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9491 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9492 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9493 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9496 set_cr4_guest_host_mask(vmx
);
9498 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9499 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9501 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9502 vmcs_write64(TSC_OFFSET
,
9503 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9505 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9509 * Trivially support vpid by letting L2s share their parent
9510 * L1's vpid. TODO: move to a more elaborate solution, giving
9511 * each L2 its own vpid and exposing the vpid feature to L1.
9513 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9514 vmx_flush_tlb(vcpu
);
9517 if (nested_cpu_has_ept(vmcs12
)) {
9518 kvm_mmu_unload(vcpu
);
9519 nested_ept_init_mmu_context(vcpu
);
9522 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9523 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9524 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9525 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9527 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9528 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9529 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9532 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9533 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9534 * The CR0_READ_SHADOW is what L2 should have expected to read given
9535 * the specifications by L1; It's not enough to take
9536 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9537 * have more bits than L1 expected.
9539 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9540 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9542 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9543 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9545 /* shadow page tables on either EPT or shadow page tables */
9546 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9547 kvm_mmu_reset_context(vcpu
);
9550 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9553 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9556 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9557 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9558 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9559 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9562 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9563 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9567 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9568 * for running an L2 nested guest.
9570 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9572 struct vmcs12
*vmcs12
;
9573 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9575 struct loaded_vmcs
*vmcs02
;
9579 if (!nested_vmx_check_permission(vcpu
) ||
9580 !nested_vmx_check_vmcs12(vcpu
))
9583 skip_emulated_instruction(vcpu
);
9584 vmcs12
= get_vmcs12(vcpu
);
9586 if (enable_shadow_vmcs
)
9587 copy_shadow_to_vmcs12(vmx
);
9590 * The nested entry process starts with enforcing various prerequisites
9591 * on vmcs12 as required by the Intel SDM, and act appropriately when
9592 * they fail: As the SDM explains, some conditions should cause the
9593 * instruction to fail, while others will cause the instruction to seem
9594 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9595 * To speed up the normal (success) code path, we should avoid checking
9596 * for misconfigurations which will anyway be caught by the processor
9597 * when using the merged vmcs02.
9599 if (vmcs12
->launch_state
== launch
) {
9600 nested_vmx_failValid(vcpu
,
9601 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9602 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9606 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9607 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9608 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9612 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9613 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9617 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9618 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9622 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9623 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9627 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9628 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9632 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9633 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9634 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9635 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9636 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9637 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9638 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9639 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9640 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9641 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9642 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9643 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9644 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9645 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9646 vmx
->nested
.nested_vmx_entry_ctls_high
))
9648 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9652 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9653 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9654 nested_vmx_failValid(vcpu
,
9655 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9659 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9660 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9661 nested_vmx_entry_failure(vcpu
, vmcs12
,
9662 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9665 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9666 nested_vmx_entry_failure(vcpu
, vmcs12
,
9667 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9672 * If the load IA32_EFER VM-entry control is 1, the following checks
9673 * are performed on the field for the IA32_EFER MSR:
9674 * - Bits reserved in the IA32_EFER MSR must be 0.
9675 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9676 * the IA-32e mode guest VM-exit control. It must also be identical
9677 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9680 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9681 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9682 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9683 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9684 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9685 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9686 nested_vmx_entry_failure(vcpu
, vmcs12
,
9687 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9693 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9694 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9695 * the values of the LMA and LME bits in the field must each be that of
9696 * the host address-space size VM-exit control.
9698 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9699 ia32e
= (vmcs12
->vm_exit_controls
&
9700 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9701 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9702 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9703 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9704 nested_vmx_entry_failure(vcpu
, vmcs12
,
9705 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9711 * We're finally done with prerequisite checking, and can start with
9715 vmcs02
= nested_get_current_vmcs02(vmx
);
9719 enter_guest_mode(vcpu
);
9721 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9723 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9724 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9727 vmx
->loaded_vmcs
= vmcs02
;
9729 vmx_vcpu_load(vcpu
, cpu
);
9733 vmx_segment_cache_clear(vmx
);
9735 prepare_vmcs02(vcpu
, vmcs12
);
9737 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9738 vmcs12
->vm_entry_msr_load_addr
,
9739 vmcs12
->vm_entry_msr_load_count
);
9740 if (msr_entry_idx
) {
9741 leave_guest_mode(vcpu
);
9742 vmx_load_vmcs01(vcpu
);
9743 nested_vmx_entry_failure(vcpu
, vmcs12
,
9744 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9748 vmcs12
->launch_state
= 1;
9750 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9751 return kvm_vcpu_halt(vcpu
);
9753 vmx
->nested
.nested_run_pending
= 1;
9756 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9757 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9758 * returned as far as L1 is concerned. It will only return (and set
9759 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9765 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9766 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9767 * This function returns the new value we should put in vmcs12.guest_cr0.
9768 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9769 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9770 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9771 * didn't trap the bit, because if L1 did, so would L0).
9772 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9773 * been modified by L2, and L1 knows it. So just leave the old value of
9774 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9775 * isn't relevant, because if L0 traps this bit it can set it to anything.
9776 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9777 * changed these bits, and therefore they need to be updated, but L0
9778 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9779 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9781 static inline unsigned long
9782 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9785 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9786 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9787 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9788 vcpu
->arch
.cr0_guest_owned_bits
));
9791 static inline unsigned long
9792 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9795 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9796 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9797 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9798 vcpu
->arch
.cr4_guest_owned_bits
));
9801 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9802 struct vmcs12
*vmcs12
)
9807 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9808 nr
= vcpu
->arch
.exception
.nr
;
9809 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9811 if (kvm_exception_is_soft(nr
)) {
9812 vmcs12
->vm_exit_instruction_len
=
9813 vcpu
->arch
.event_exit_inst_len
;
9814 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
9816 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
9818 if (vcpu
->arch
.exception
.has_error_code
) {
9819 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
9820 vmcs12
->idt_vectoring_error_code
=
9821 vcpu
->arch
.exception
.error_code
;
9824 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9825 } else if (vcpu
->arch
.nmi_injected
) {
9826 vmcs12
->idt_vectoring_info_field
=
9827 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
9828 } else if (vcpu
->arch
.interrupt
.pending
) {
9829 nr
= vcpu
->arch
.interrupt
.nr
;
9830 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9832 if (vcpu
->arch
.interrupt
.soft
) {
9833 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
9834 vmcs12
->vm_entry_instruction_len
=
9835 vcpu
->arch
.event_exit_inst_len
;
9837 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
9839 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9843 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
9845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9847 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
9848 vmx
->nested
.preemption_timer_expired
) {
9849 if (vmx
->nested
.nested_run_pending
)
9851 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
9855 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
9856 if (vmx
->nested
.nested_run_pending
||
9857 vcpu
->arch
.interrupt
.pending
)
9859 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9860 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
9861 INTR_INFO_VALID_MASK
, 0);
9863 * The NMI-triggered VM exit counts as injection:
9864 * clear this one and block further NMIs.
9866 vcpu
->arch
.nmi_pending
= 0;
9867 vmx_set_nmi_mask(vcpu
, true);
9871 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
9872 nested_exit_on_intr(vcpu
)) {
9873 if (vmx
->nested
.nested_run_pending
)
9875 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
9879 return vmx_complete_nested_posted_interrupt(vcpu
);
9882 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
9885 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
9888 if (ktime_to_ns(remaining
) <= 0)
9891 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
9892 do_div(value
, 1000000);
9893 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9897 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9898 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9899 * and this function updates it to reflect the changes to the guest state while
9900 * L2 was running (and perhaps made some exits which were handled directly by L0
9901 * without going back to L1), and to reflect the exit reason.
9902 * Note that we do not have to copy here all VMCS fields, just those that
9903 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9904 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9905 * which already writes to vmcs12 directly.
9907 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9908 u32 exit_reason
, u32 exit_intr_info
,
9909 unsigned long exit_qualification
)
9911 /* update guest state fields: */
9912 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
9913 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
9915 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
9916 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
9917 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
9919 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
9920 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
9921 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
9922 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
9923 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
9924 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
9925 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
9926 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
9927 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
9928 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
9929 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
9930 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
9931 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
9932 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
9933 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
9934 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
9935 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
9936 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
9937 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
9938 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
9939 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
9940 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
9941 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
9942 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
9943 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
9944 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
9945 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
9946 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
9947 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
9948 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
9949 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
9950 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
9951 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
9952 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
9953 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
9954 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
9956 vmcs12
->guest_interruptibility_info
=
9957 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
9958 vmcs12
->guest_pending_dbg_exceptions
=
9959 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
9960 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
9961 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
9963 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
9965 if (nested_cpu_has_preemption_timer(vmcs12
)) {
9966 if (vmcs12
->vm_exit_controls
&
9967 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
9968 vmcs12
->vmx_preemption_timer_value
=
9969 vmx_get_preemption_timer_value(vcpu
);
9970 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
9974 * In some cases (usually, nested EPT), L2 is allowed to change its
9975 * own CR3 without exiting. If it has changed it, we must keep it.
9976 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9977 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9979 * Additionally, restore L2's PDPTR to vmcs12.
9982 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
9983 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
9984 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
9985 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
9986 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
9989 if (nested_cpu_has_vid(vmcs12
))
9990 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
9992 vmcs12
->vm_entry_controls
=
9993 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
9994 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
9996 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
9997 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
9998 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10001 /* TODO: These cannot have changed unless we have MSR bitmaps and
10002 * the relevant bit asks not to trap the change */
10003 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10004 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10005 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10006 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10007 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10008 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10009 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10010 if (vmx_mpx_supported())
10011 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10012 if (nested_cpu_has_xsaves(vmcs12
))
10013 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10015 /* update exit information fields: */
10017 vmcs12
->vm_exit_reason
= exit_reason
;
10018 vmcs12
->exit_qualification
= exit_qualification
;
10020 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10021 if ((vmcs12
->vm_exit_intr_info
&
10022 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10023 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10024 vmcs12
->vm_exit_intr_error_code
=
10025 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10026 vmcs12
->idt_vectoring_info_field
= 0;
10027 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10028 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10030 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10031 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10032 * instead of reading the real value. */
10033 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10036 * Transfer the event that L0 or L1 may wanted to inject into
10037 * L2 to IDT_VECTORING_INFO_FIELD.
10039 vmcs12_save_pending_event(vcpu
, vmcs12
);
10043 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10044 * preserved above and would only end up incorrectly in L1.
10046 vcpu
->arch
.nmi_injected
= false;
10047 kvm_clear_exception_queue(vcpu
);
10048 kvm_clear_interrupt_queue(vcpu
);
10052 * A part of what we need to when the nested L2 guest exits and we want to
10053 * run its L1 parent, is to reset L1's guest state to the host state specified
10055 * This function is to be called not only on normal nested exit, but also on
10056 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10057 * Failures During or After Loading Guest State").
10058 * This function should be called when the active VMCS is L1's (vmcs01).
10060 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10061 struct vmcs12
*vmcs12
)
10063 struct kvm_segment seg
;
10065 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10066 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10067 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10068 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10070 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10071 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10073 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10074 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10075 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10077 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10078 * actually changed, because it depends on the current state of
10079 * fpu_active (which may have changed).
10080 * Note that vmx_set_cr0 refers to efer set above.
10082 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10084 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10085 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10086 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10088 update_exception_bitmap(vcpu
);
10089 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10090 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10093 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10094 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10096 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10097 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10099 nested_ept_uninit_mmu_context(vcpu
);
10101 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10102 kvm_mmu_reset_context(vcpu
);
10105 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10109 * Trivially support vpid by letting L2s share their parent
10110 * L1's vpid. TODO: move to a more elaborate solution, giving
10111 * each L2 its own vpid and exposing the vpid feature to L1.
10113 vmx_flush_tlb(vcpu
);
10117 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10118 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10119 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10120 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10121 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10123 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10124 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10125 vmcs_write64(GUEST_BNDCFGS
, 0);
10127 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10128 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10129 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10131 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10132 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10133 vmcs12
->host_ia32_perf_global_ctrl
);
10135 /* Set L1 segment info according to Intel SDM
10136 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10137 seg
= (struct kvm_segment
) {
10139 .limit
= 0xFFFFFFFF,
10140 .selector
= vmcs12
->host_cs_selector
,
10146 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10150 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10151 seg
= (struct kvm_segment
) {
10153 .limit
= 0xFFFFFFFF,
10160 seg
.selector
= vmcs12
->host_ds_selector
;
10161 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10162 seg
.selector
= vmcs12
->host_es_selector
;
10163 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10164 seg
.selector
= vmcs12
->host_ss_selector
;
10165 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10166 seg
.selector
= vmcs12
->host_fs_selector
;
10167 seg
.base
= vmcs12
->host_fs_base
;
10168 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10169 seg
.selector
= vmcs12
->host_gs_selector
;
10170 seg
.base
= vmcs12
->host_gs_base
;
10171 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10172 seg
= (struct kvm_segment
) {
10173 .base
= vmcs12
->host_tr_base
,
10175 .selector
= vmcs12
->host_tr_selector
,
10179 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10181 kvm_set_dr(vcpu
, 7, 0x400);
10182 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10184 if (cpu_has_vmx_msr_bitmap())
10185 vmx_set_msr_bitmap(vcpu
);
10187 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10188 vmcs12
->vm_exit_msr_load_count
))
10189 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10193 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10194 * and modify vmcs12 to make it see what it would expect to see there if
10195 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10197 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10198 u32 exit_intr_info
,
10199 unsigned long exit_qualification
)
10201 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10202 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10204 /* trying to cancel vmlaunch/vmresume is a bug */
10205 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10207 leave_guest_mode(vcpu
);
10208 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10209 exit_qualification
);
10211 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10212 vmcs12
->vm_exit_msr_store_count
))
10213 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10215 vmx_load_vmcs01(vcpu
);
10217 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10218 && nested_exit_intr_ack_set(vcpu
)) {
10219 int irq
= kvm_cpu_get_interrupt(vcpu
);
10221 vmcs12
->vm_exit_intr_info
= irq
|
10222 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10225 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10226 vmcs12
->exit_qualification
,
10227 vmcs12
->idt_vectoring_info_field
,
10228 vmcs12
->vm_exit_intr_info
,
10229 vmcs12
->vm_exit_intr_error_code
,
10232 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10233 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10234 vmx_segment_cache_clear(vmx
);
10236 /* if no vmcs02 cache requested, remove the one we used */
10237 if (VMCS02_POOL_SIZE
== 0)
10238 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10240 load_vmcs12_host_state(vcpu
, vmcs12
);
10242 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10243 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10245 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10248 /* Unpin physical memory we referred to in vmcs02 */
10249 if (vmx
->nested
.apic_access_page
) {
10250 nested_release_page(vmx
->nested
.apic_access_page
);
10251 vmx
->nested
.apic_access_page
= NULL
;
10253 if (vmx
->nested
.virtual_apic_page
) {
10254 nested_release_page(vmx
->nested
.virtual_apic_page
);
10255 vmx
->nested
.virtual_apic_page
= NULL
;
10257 if (vmx
->nested
.pi_desc_page
) {
10258 kunmap(vmx
->nested
.pi_desc_page
);
10259 nested_release_page(vmx
->nested
.pi_desc_page
);
10260 vmx
->nested
.pi_desc_page
= NULL
;
10261 vmx
->nested
.pi_desc
= NULL
;
10265 * We are now running in L2, mmu_notifier will force to reload the
10266 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10268 kvm_vcpu_reload_apic_access_page(vcpu
);
10271 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10272 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10273 * success or failure flag accordingly.
10275 if (unlikely(vmx
->fail
)) {
10277 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10279 nested_vmx_succeed(vcpu
);
10280 if (enable_shadow_vmcs
)
10281 vmx
->nested
.sync_shadow_vmcs
= true;
10283 /* in case we halted in L2 */
10284 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10288 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10290 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10292 if (is_guest_mode(vcpu
))
10293 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10294 free_nested(to_vmx(vcpu
));
10298 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10299 * 23.7 "VM-entry failures during or after loading guest state" (this also
10300 * lists the acceptable exit-reason and exit-qualification parameters).
10301 * It should only be called before L2 actually succeeded to run, and when
10302 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10304 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10305 struct vmcs12
*vmcs12
,
10306 u32 reason
, unsigned long qualification
)
10308 load_vmcs12_host_state(vcpu
, vmcs12
);
10309 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10310 vmcs12
->exit_qualification
= qualification
;
10311 nested_vmx_succeed(vcpu
);
10312 if (enable_shadow_vmcs
)
10313 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10316 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10317 struct x86_instruction_info
*info
,
10318 enum x86_intercept_stage stage
)
10320 return X86EMUL_CONTINUE
;
10323 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10326 shrink_ple_window(vcpu
);
10329 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10330 struct kvm_memory_slot
*slot
)
10332 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10333 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10336 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10337 struct kvm_memory_slot
*slot
)
10339 kvm_mmu_slot_set_dirty(kvm
, slot
);
10342 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10344 kvm_flush_pml_buffers(kvm
);
10347 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10348 struct kvm_memory_slot
*memslot
,
10349 gfn_t offset
, unsigned long mask
)
10351 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10355 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10358 * @host_irq: host irq of the interrupt
10359 * @guest_irq: gsi of the interrupt
10360 * @set: set or unset PI
10361 * returns 0 on success, < 0 on failure
10363 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10364 uint32_t guest_irq
, bool set
)
10366 struct kvm_kernel_irq_routing_entry
*e
;
10367 struct kvm_irq_routing_table
*irq_rt
;
10368 struct kvm_lapic_irq irq
;
10369 struct kvm_vcpu
*vcpu
;
10370 struct vcpu_data vcpu_info
;
10371 int idx
, ret
= -EINVAL
;
10373 if (!kvm_arch_has_assigned_device(kvm
) ||
10374 !irq_remapping_cap(IRQ_POSTING_CAP
))
10377 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10378 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10379 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10381 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10382 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10385 * VT-d PI cannot support posting multicast/broadcast
10386 * interrupts to a vCPU, we still use interrupt remapping
10387 * for these kind of interrupts.
10389 * For lowest-priority interrupts, we only support
10390 * those with single CPU as the destination, e.g. user
10391 * configures the interrupts via /proc/irq or uses
10392 * irqbalance to make the interrupts single-CPU.
10394 * We will support full lowest-priority interrupt later.
10397 kvm_set_msi_irq(e
, &irq
);
10398 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
))
10401 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10402 vcpu_info
.vector
= irq
.vector
;
10404 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, e
->gsi
,
10405 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10408 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10410 /* suppress notification event before unposting */
10411 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10412 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10413 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10417 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10425 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10429 static struct kvm_x86_ops vmx_x86_ops
= {
10430 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10431 .disabled_by_bios
= vmx_disabled_by_bios
,
10432 .hardware_setup
= hardware_setup
,
10433 .hardware_unsetup
= hardware_unsetup
,
10434 .check_processor_compatibility
= vmx_check_processor_compat
,
10435 .hardware_enable
= hardware_enable
,
10436 .hardware_disable
= hardware_disable
,
10437 .cpu_has_accelerated_tpr
= report_flexpriority
,
10438 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10440 .vcpu_create
= vmx_create_vcpu
,
10441 .vcpu_free
= vmx_free_vcpu
,
10442 .vcpu_reset
= vmx_vcpu_reset
,
10444 .prepare_guest_switch
= vmx_save_host_state
,
10445 .vcpu_load
= vmx_vcpu_load
,
10446 .vcpu_put
= vmx_vcpu_put
,
10448 .update_db_bp_intercept
= update_exception_bitmap
,
10449 .get_msr
= vmx_get_msr
,
10450 .set_msr
= vmx_set_msr
,
10451 .get_segment_base
= vmx_get_segment_base
,
10452 .get_segment
= vmx_get_segment
,
10453 .set_segment
= vmx_set_segment
,
10454 .get_cpl
= vmx_get_cpl
,
10455 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10456 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10457 .decache_cr3
= vmx_decache_cr3
,
10458 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10459 .set_cr0
= vmx_set_cr0
,
10460 .set_cr3
= vmx_set_cr3
,
10461 .set_cr4
= vmx_set_cr4
,
10462 .set_efer
= vmx_set_efer
,
10463 .get_idt
= vmx_get_idt
,
10464 .set_idt
= vmx_set_idt
,
10465 .get_gdt
= vmx_get_gdt
,
10466 .set_gdt
= vmx_set_gdt
,
10467 .get_dr6
= vmx_get_dr6
,
10468 .set_dr6
= vmx_set_dr6
,
10469 .set_dr7
= vmx_set_dr7
,
10470 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10471 .cache_reg
= vmx_cache_reg
,
10472 .get_rflags
= vmx_get_rflags
,
10473 .set_rflags
= vmx_set_rflags
,
10474 .fpu_activate
= vmx_fpu_activate
,
10475 .fpu_deactivate
= vmx_fpu_deactivate
,
10477 .tlb_flush
= vmx_flush_tlb
,
10479 .run
= vmx_vcpu_run
,
10480 .handle_exit
= vmx_handle_exit
,
10481 .skip_emulated_instruction
= skip_emulated_instruction
,
10482 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10483 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10484 .patch_hypercall
= vmx_patch_hypercall
,
10485 .set_irq
= vmx_inject_irq
,
10486 .set_nmi
= vmx_inject_nmi
,
10487 .queue_exception
= vmx_queue_exception
,
10488 .cancel_injection
= vmx_cancel_injection
,
10489 .interrupt_allowed
= vmx_interrupt_allowed
,
10490 .nmi_allowed
= vmx_nmi_allowed
,
10491 .get_nmi_mask
= vmx_get_nmi_mask
,
10492 .set_nmi_mask
= vmx_set_nmi_mask
,
10493 .enable_nmi_window
= enable_nmi_window
,
10494 .enable_irq_window
= enable_irq_window
,
10495 .update_cr8_intercept
= update_cr8_intercept
,
10496 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10497 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10498 .cpu_uses_apicv
= vmx_cpu_uses_apicv
,
10499 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10500 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10501 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10502 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10503 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10505 .set_tss_addr
= vmx_set_tss_addr
,
10506 .get_tdp_level
= get_ept_level
,
10507 .get_mt_mask
= vmx_get_mt_mask
,
10509 .get_exit_info
= vmx_get_exit_info
,
10511 .get_lpage_level
= vmx_get_lpage_level
,
10513 .cpuid_update
= vmx_cpuid_update
,
10515 .rdtscp_supported
= vmx_rdtscp_supported
,
10516 .invpcid_supported
= vmx_invpcid_supported
,
10518 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10520 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10522 .set_tsc_khz
= vmx_set_tsc_khz
,
10523 .read_tsc_offset
= vmx_read_tsc_offset
,
10524 .write_tsc_offset
= vmx_write_tsc_offset
,
10525 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10526 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10527 .read_l1_tsc
= vmx_read_l1_tsc
,
10529 .set_tdp_cr3
= vmx_set_cr3
,
10531 .check_intercept
= vmx_check_intercept
,
10532 .handle_external_intr
= vmx_handle_external_intr
,
10533 .mpx_supported
= vmx_mpx_supported
,
10534 .xsaves_supported
= vmx_xsaves_supported
,
10536 .check_nested_events
= vmx_check_nested_events
,
10538 .sched_in
= vmx_sched_in
,
10540 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10541 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10542 .flush_log_dirty
= vmx_flush_log_dirty
,
10543 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10545 .pmu_ops
= &intel_pmu_ops
,
10547 .update_pi_irte
= vmx_update_pi_irte
,
10550 static int __init
vmx_init(void)
10552 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10553 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10557 #ifdef CONFIG_KEXEC_CORE
10558 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10559 crash_vmclear_local_loaded_vmcss
);
10565 static void __exit
vmx_exit(void)
10567 #ifdef CONFIG_KEXEC_CORE
10568 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10575 module_init(vmx_init
)
10576 module_exit(vmx_exit
)