2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending
;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page
*apic_access_page
;
376 u64 msr_ia32_feature_control
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
421 u32 vm_entry_controls_shadow
;
422 u32 vm_exit_controls_shadow
;
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
428 struct loaded_vmcs vmcs01
;
429 struct loaded_vmcs
*loaded_vmcs
;
430 bool __launched
; /* temporary, used in vmx_vcpu_run */
431 struct msr_autoload
{
433 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
434 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
438 u16 fs_sel
, gs_sel
, ldt_sel
;
442 int gs_ldt_reload_needed
;
443 int fs_reload_needed
;
444 u64 msr_host_bndcfgs
;
449 struct kvm_segment segs
[8];
452 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
453 struct kvm_save_segment
{
461 bool emulation_required
;
463 /* Support for vnmi-less CPUs */
464 int soft_vnmi_blocked
;
466 s64 vnmi_blocked_time
;
471 /* Posted interrupt descriptor */
472 struct pi_desc pi_desc
;
474 /* Support for a guest hypervisor (nested VMX) */
475 struct nested_vmx nested
;
478 enum segment_cache_field
{
487 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
489 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
492 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
493 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
494 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
495 [number##_HIGH] = VMCS12_OFFSET(name)+4
498 static const unsigned long shadow_read_only_fields
[] = {
500 * We do NOT shadow fields that are modified when L0
501 * traps and emulates any vmx instruction (e.g. VMPTRLD,
502 * VMXON...) executed by L1.
503 * For example, VM_INSTRUCTION_ERROR is read
504 * by L1 if a vmx instruction fails (part of the error path).
505 * Note the code assumes this logic. If for some reason
506 * we start shadowing these fields then we need to
507 * force a shadow sync when L0 emulates vmx instructions
508 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
509 * by nested_vmx_failValid)
513 VM_EXIT_INSTRUCTION_LEN
,
514 IDT_VECTORING_INFO_FIELD
,
515 IDT_VECTORING_ERROR_CODE
,
516 VM_EXIT_INTR_ERROR_CODE
,
518 GUEST_LINEAR_ADDRESS
,
519 GUEST_PHYSICAL_ADDRESS
521 static const int max_shadow_read_only_fields
=
522 ARRAY_SIZE(shadow_read_only_fields
);
524 static const unsigned long shadow_read_write_fields
[] = {
530 GUEST_INTERRUPTIBILITY_INFO
,
542 CPU_BASED_VM_EXEC_CONTROL
,
543 VM_ENTRY_EXCEPTION_ERROR_CODE
,
544 VM_ENTRY_INTR_INFO_FIELD
,
545 VM_ENTRY_INSTRUCTION_LEN
,
546 VM_ENTRY_EXCEPTION_ERROR_CODE
,
552 static const int max_shadow_read_write_fields
=
553 ARRAY_SIZE(shadow_read_write_fields
);
555 static const unsigned short vmcs_field_to_offset_table
[] = {
556 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
557 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
558 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
559 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
560 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
561 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
562 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
563 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
564 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
565 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
566 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
567 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
568 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
569 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
570 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
571 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
572 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
573 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
574 FIELD64(MSR_BITMAP
, msr_bitmap
),
575 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
576 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
577 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
578 FIELD64(TSC_OFFSET
, tsc_offset
),
579 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
580 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
581 FIELD64(EPT_POINTER
, ept_pointer
),
582 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
583 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
584 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
585 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
586 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
587 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
588 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
589 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
590 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
591 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
592 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
593 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
594 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
595 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
596 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
597 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
598 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
599 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
600 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
601 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
602 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
603 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
604 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
605 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
606 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
607 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
608 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
609 FIELD(TPR_THRESHOLD
, tpr_threshold
),
610 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
611 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
612 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
613 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
614 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
615 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
616 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
617 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
618 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
619 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
620 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
621 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
622 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
623 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
624 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
625 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
626 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
627 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
628 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
629 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
630 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
631 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
632 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
633 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
634 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
635 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
636 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
637 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
638 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
639 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
640 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
641 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
642 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
643 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
644 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
645 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
646 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
647 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
648 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
649 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
650 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
651 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
652 FIELD(GUEST_CR0
, guest_cr0
),
653 FIELD(GUEST_CR3
, guest_cr3
),
654 FIELD(GUEST_CR4
, guest_cr4
),
655 FIELD(GUEST_ES_BASE
, guest_es_base
),
656 FIELD(GUEST_CS_BASE
, guest_cs_base
),
657 FIELD(GUEST_SS_BASE
, guest_ss_base
),
658 FIELD(GUEST_DS_BASE
, guest_ds_base
),
659 FIELD(GUEST_FS_BASE
, guest_fs_base
),
660 FIELD(GUEST_GS_BASE
, guest_gs_base
),
661 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
662 FIELD(GUEST_TR_BASE
, guest_tr_base
),
663 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
664 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
665 FIELD(GUEST_DR7
, guest_dr7
),
666 FIELD(GUEST_RSP
, guest_rsp
),
667 FIELD(GUEST_RIP
, guest_rip
),
668 FIELD(GUEST_RFLAGS
, guest_rflags
),
669 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
670 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
671 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
672 FIELD(HOST_CR0
, host_cr0
),
673 FIELD(HOST_CR3
, host_cr3
),
674 FIELD(HOST_CR4
, host_cr4
),
675 FIELD(HOST_FS_BASE
, host_fs_base
),
676 FIELD(HOST_GS_BASE
, host_gs_base
),
677 FIELD(HOST_TR_BASE
, host_tr_base
),
678 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
679 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
680 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
681 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
682 FIELD(HOST_RSP
, host_rsp
),
683 FIELD(HOST_RIP
, host_rip
),
685 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
687 static inline short vmcs_field_to_offset(unsigned long field
)
689 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
691 return vmcs_field_to_offset_table
[field
];
694 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
696 return to_vmx(vcpu
)->nested
.current_vmcs12
;
699 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
701 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
702 if (is_error_page(page
))
708 static void nested_release_page(struct page
*page
)
710 kvm_release_page_dirty(page
);
713 static void nested_release_page_clean(struct page
*page
)
715 kvm_release_page_clean(page
);
718 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
719 static u64
construct_eptp(unsigned long root_hpa
);
720 static void kvm_cpu_vmxon(u64 addr
);
721 static void kvm_cpu_vmxoff(void);
722 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
723 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
724 struct kvm_segment
*var
, int seg
);
725 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
726 struct kvm_segment
*var
, int seg
);
727 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
728 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
729 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
730 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
731 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
733 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
734 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
736 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
737 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
739 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
740 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
742 static unsigned long *vmx_io_bitmap_a
;
743 static unsigned long *vmx_io_bitmap_b
;
744 static unsigned long *vmx_msr_bitmap_legacy
;
745 static unsigned long *vmx_msr_bitmap_longmode
;
746 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
747 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
748 static unsigned long *vmx_vmread_bitmap
;
749 static unsigned long *vmx_vmwrite_bitmap
;
751 static bool cpu_has_load_ia32_efer
;
752 static bool cpu_has_load_perf_global_ctrl
;
754 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
755 static DEFINE_SPINLOCK(vmx_vpid_lock
);
757 static struct vmcs_config
{
761 u32 pin_based_exec_ctrl
;
762 u32 cpu_based_exec_ctrl
;
763 u32 cpu_based_2nd_exec_ctrl
;
768 static struct vmx_capability
{
773 #define VMX_SEGMENT_FIELD(seg) \
774 [VCPU_SREG_##seg] = { \
775 .selector = GUEST_##seg##_SELECTOR, \
776 .base = GUEST_##seg##_BASE, \
777 .limit = GUEST_##seg##_LIMIT, \
778 .ar_bytes = GUEST_##seg##_AR_BYTES, \
781 static const struct kvm_vmx_segment_field
{
786 } kvm_vmx_segment_fields
[] = {
787 VMX_SEGMENT_FIELD(CS
),
788 VMX_SEGMENT_FIELD(DS
),
789 VMX_SEGMENT_FIELD(ES
),
790 VMX_SEGMENT_FIELD(FS
),
791 VMX_SEGMENT_FIELD(GS
),
792 VMX_SEGMENT_FIELD(SS
),
793 VMX_SEGMENT_FIELD(TR
),
794 VMX_SEGMENT_FIELD(LDTR
),
797 static u64 host_efer
;
799 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
802 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
803 * away by decrementing the array size.
805 static const u32 vmx_msr_index
[] = {
807 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
809 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
811 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
813 static inline bool is_page_fault(u32 intr_info
)
815 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
816 INTR_INFO_VALID_MASK
)) ==
817 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
820 static inline bool is_no_device(u32 intr_info
)
822 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
823 INTR_INFO_VALID_MASK
)) ==
824 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
827 static inline bool is_invalid_opcode(u32 intr_info
)
829 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
830 INTR_INFO_VALID_MASK
)) ==
831 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
834 static inline bool is_external_interrupt(u32 intr_info
)
836 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
837 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
840 static inline bool is_machine_check(u32 intr_info
)
842 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
843 INTR_INFO_VALID_MASK
)) ==
844 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
847 static inline bool cpu_has_vmx_msr_bitmap(void)
849 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
852 static inline bool cpu_has_vmx_tpr_shadow(void)
854 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
857 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
859 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
862 static inline bool cpu_has_secondary_exec_ctrls(void)
864 return vmcs_config
.cpu_based_exec_ctrl
&
865 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
868 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
870 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
871 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
874 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
876 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
877 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
880 static inline bool cpu_has_vmx_apic_register_virt(void)
882 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
883 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
886 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
888 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
889 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
892 static inline bool cpu_has_vmx_posted_intr(void)
894 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
897 static inline bool cpu_has_vmx_apicv(void)
899 return cpu_has_vmx_apic_register_virt() &&
900 cpu_has_vmx_virtual_intr_delivery() &&
901 cpu_has_vmx_posted_intr();
904 static inline bool cpu_has_vmx_flexpriority(void)
906 return cpu_has_vmx_tpr_shadow() &&
907 cpu_has_vmx_virtualize_apic_accesses();
910 static inline bool cpu_has_vmx_ept_execute_only(void)
912 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
915 static inline bool cpu_has_vmx_eptp_uncacheable(void)
917 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
920 static inline bool cpu_has_vmx_eptp_writeback(void)
922 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
925 static inline bool cpu_has_vmx_ept_2m_page(void)
927 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
930 static inline bool cpu_has_vmx_ept_1g_page(void)
932 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
935 static inline bool cpu_has_vmx_ept_4levels(void)
937 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
940 static inline bool cpu_has_vmx_ept_ad_bits(void)
942 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
945 static inline bool cpu_has_vmx_invept_context(void)
947 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
950 static inline bool cpu_has_vmx_invept_global(void)
952 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
955 static inline bool cpu_has_vmx_invvpid_single(void)
957 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
960 static inline bool cpu_has_vmx_invvpid_global(void)
962 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
965 static inline bool cpu_has_vmx_ept(void)
967 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
968 SECONDARY_EXEC_ENABLE_EPT
;
971 static inline bool cpu_has_vmx_unrestricted_guest(void)
973 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
974 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
977 static inline bool cpu_has_vmx_ple(void)
979 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
980 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
983 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
985 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
988 static inline bool cpu_has_vmx_vpid(void)
990 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
991 SECONDARY_EXEC_ENABLE_VPID
;
994 static inline bool cpu_has_vmx_rdtscp(void)
996 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
997 SECONDARY_EXEC_RDTSCP
;
1000 static inline bool cpu_has_vmx_invpcid(void)
1002 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1003 SECONDARY_EXEC_ENABLE_INVPCID
;
1006 static inline bool cpu_has_virtual_nmis(void)
1008 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1011 static inline bool cpu_has_vmx_wbinvd_exit(void)
1013 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1014 SECONDARY_EXEC_WBINVD_EXITING
;
1017 static inline bool cpu_has_vmx_shadow_vmcs(void)
1020 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1021 /* check if the cpu supports writing r/o exit information fields */
1022 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1025 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1026 SECONDARY_EXEC_SHADOW_VMCS
;
1029 static inline bool report_flexpriority(void)
1031 return flexpriority_enabled
;
1034 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1036 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1039 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1041 return (vmcs12
->cpu_based_vm_exec_control
&
1042 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1043 (vmcs12
->secondary_vm_exec_control
& bit
);
1046 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1048 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1051 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1053 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1056 static inline bool is_exception(u32 intr_info
)
1058 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1059 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1062 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1064 unsigned long exit_qualification
);
1065 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1066 struct vmcs12
*vmcs12
,
1067 u32 reason
, unsigned long qualification
);
1069 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1073 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1074 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1079 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1085 } operand
= { vpid
, 0, gva
};
1087 asm volatile (__ex(ASM_VMX_INVVPID
)
1088 /* CF==1 or ZF==1 --> rc = -1 */
1089 "; ja 1f ; ud2 ; 1:"
1090 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1093 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1097 } operand
= {eptp
, gpa
};
1099 asm volatile (__ex(ASM_VMX_INVEPT
)
1100 /* CF==1 or ZF==1 --> rc = -1 */
1101 "; ja 1f ; ud2 ; 1:\n"
1102 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1105 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1109 i
= __find_msr_index(vmx
, msr
);
1111 return &vmx
->guest_msrs
[i
];
1115 static void vmcs_clear(struct vmcs
*vmcs
)
1117 u64 phys_addr
= __pa(vmcs
);
1120 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1121 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1124 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1128 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1130 vmcs_clear(loaded_vmcs
->vmcs
);
1131 loaded_vmcs
->cpu
= -1;
1132 loaded_vmcs
->launched
= 0;
1135 static void vmcs_load(struct vmcs
*vmcs
)
1137 u64 phys_addr
= __pa(vmcs
);
1140 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1141 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1144 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1150 * This bitmap is used to indicate whether the vmclear
1151 * operation is enabled on all cpus. All disabled by
1154 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1156 static inline void crash_enable_local_vmclear(int cpu
)
1158 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1161 static inline void crash_disable_local_vmclear(int cpu
)
1163 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1166 static inline int crash_local_vmclear_enabled(int cpu
)
1168 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1171 static void crash_vmclear_local_loaded_vmcss(void)
1173 int cpu
= raw_smp_processor_id();
1174 struct loaded_vmcs
*v
;
1176 if (!crash_local_vmclear_enabled(cpu
))
1179 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1180 loaded_vmcss_on_cpu_link
)
1181 vmcs_clear(v
->vmcs
);
1184 static inline void crash_enable_local_vmclear(int cpu
) { }
1185 static inline void crash_disable_local_vmclear(int cpu
) { }
1186 #endif /* CONFIG_KEXEC */
1188 static void __loaded_vmcs_clear(void *arg
)
1190 struct loaded_vmcs
*loaded_vmcs
= arg
;
1191 int cpu
= raw_smp_processor_id();
1193 if (loaded_vmcs
->cpu
!= cpu
)
1194 return; /* vcpu migration can race with cpu offline */
1195 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1196 per_cpu(current_vmcs
, cpu
) = NULL
;
1197 crash_disable_local_vmclear(cpu
);
1198 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1201 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1202 * is before setting loaded_vmcs->vcpu to -1 which is done in
1203 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1204 * then adds the vmcs into percpu list before it is deleted.
1208 loaded_vmcs_init(loaded_vmcs
);
1209 crash_enable_local_vmclear(cpu
);
1212 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1214 int cpu
= loaded_vmcs
->cpu
;
1217 smp_call_function_single(cpu
,
1218 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1221 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1226 if (cpu_has_vmx_invvpid_single())
1227 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1230 static inline void vpid_sync_vcpu_global(void)
1232 if (cpu_has_vmx_invvpid_global())
1233 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1236 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1238 if (cpu_has_vmx_invvpid_single())
1239 vpid_sync_vcpu_single(vmx
);
1241 vpid_sync_vcpu_global();
1244 static inline void ept_sync_global(void)
1246 if (cpu_has_vmx_invept_global())
1247 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1250 static inline void ept_sync_context(u64 eptp
)
1253 if (cpu_has_vmx_invept_context())
1254 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1260 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1262 unsigned long value
;
1264 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1265 : "=a"(value
) : "d"(field
) : "cc");
1269 static __always_inline u16
vmcs_read16(unsigned long field
)
1271 return vmcs_readl(field
);
1274 static __always_inline u32
vmcs_read32(unsigned long field
)
1276 return vmcs_readl(field
);
1279 static __always_inline u64
vmcs_read64(unsigned long field
)
1281 #ifdef CONFIG_X86_64
1282 return vmcs_readl(field
);
1284 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1288 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1290 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1291 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1295 static void vmcs_writel(unsigned long field
, unsigned long value
)
1299 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1300 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1301 if (unlikely(error
))
1302 vmwrite_error(field
, value
);
1305 static void vmcs_write16(unsigned long field
, u16 value
)
1307 vmcs_writel(field
, value
);
1310 static void vmcs_write32(unsigned long field
, u32 value
)
1312 vmcs_writel(field
, value
);
1315 static void vmcs_write64(unsigned long field
, u64 value
)
1317 vmcs_writel(field
, value
);
1318 #ifndef CONFIG_X86_64
1320 vmcs_writel(field
+1, value
>> 32);
1324 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1326 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1329 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1331 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1334 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1336 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1337 vmx
->vm_entry_controls_shadow
= val
;
1340 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1342 if (vmx
->vm_entry_controls_shadow
!= val
)
1343 vm_entry_controls_init(vmx
, val
);
1346 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1348 return vmx
->vm_entry_controls_shadow
;
1352 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1354 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1357 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1359 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1362 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1364 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1365 vmx
->vm_exit_controls_shadow
= val
;
1368 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1370 if (vmx
->vm_exit_controls_shadow
!= val
)
1371 vm_exit_controls_init(vmx
, val
);
1374 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1376 return vmx
->vm_exit_controls_shadow
;
1380 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1382 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1385 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1387 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1390 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1392 vmx
->segment_cache
.bitmask
= 0;
1395 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1399 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1401 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1402 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1403 vmx
->segment_cache
.bitmask
= 0;
1405 ret
= vmx
->segment_cache
.bitmask
& mask
;
1406 vmx
->segment_cache
.bitmask
|= mask
;
1410 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1412 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1414 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1415 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1419 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1421 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1423 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1424 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1428 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1430 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1432 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1433 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1437 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1439 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1441 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1442 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1446 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1450 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1451 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1452 if ((vcpu
->guest_debug
&
1453 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1454 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1455 eb
|= 1u << BP_VECTOR
;
1456 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1459 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1460 if (vcpu
->fpu_active
)
1461 eb
&= ~(1u << NM_VECTOR
);
1463 /* When we are running a nested L2 guest and L1 specified for it a
1464 * certain exception bitmap, we must trap the same exceptions and pass
1465 * them to L1. When running L2, we will only handle the exceptions
1466 * specified above if L1 did not want them.
1468 if (is_guest_mode(vcpu
))
1469 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1471 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1474 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1475 unsigned long entry
, unsigned long exit
)
1477 vm_entry_controls_clearbit(vmx
, entry
);
1478 vm_exit_controls_clearbit(vmx
, exit
);
1481 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1484 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1488 if (cpu_has_load_ia32_efer
) {
1489 clear_atomic_switch_msr_special(vmx
,
1490 VM_ENTRY_LOAD_IA32_EFER
,
1491 VM_EXIT_LOAD_IA32_EFER
);
1495 case MSR_CORE_PERF_GLOBAL_CTRL
:
1496 if (cpu_has_load_perf_global_ctrl
) {
1497 clear_atomic_switch_msr_special(vmx
,
1498 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1499 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1505 for (i
= 0; i
< m
->nr
; ++i
)
1506 if (m
->guest
[i
].index
== msr
)
1512 m
->guest
[i
] = m
->guest
[m
->nr
];
1513 m
->host
[i
] = m
->host
[m
->nr
];
1514 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1515 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1518 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1519 unsigned long entry
, unsigned long exit
,
1520 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1521 u64 guest_val
, u64 host_val
)
1523 vmcs_write64(guest_val_vmcs
, guest_val
);
1524 vmcs_write64(host_val_vmcs
, host_val
);
1525 vm_entry_controls_setbit(vmx
, entry
);
1526 vm_exit_controls_setbit(vmx
, exit
);
1529 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1530 u64 guest_val
, u64 host_val
)
1533 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1537 if (cpu_has_load_ia32_efer
) {
1538 add_atomic_switch_msr_special(vmx
,
1539 VM_ENTRY_LOAD_IA32_EFER
,
1540 VM_EXIT_LOAD_IA32_EFER
,
1543 guest_val
, host_val
);
1547 case MSR_CORE_PERF_GLOBAL_CTRL
:
1548 if (cpu_has_load_perf_global_ctrl
) {
1549 add_atomic_switch_msr_special(vmx
,
1550 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1551 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1552 GUEST_IA32_PERF_GLOBAL_CTRL
,
1553 HOST_IA32_PERF_GLOBAL_CTRL
,
1554 guest_val
, host_val
);
1560 for (i
= 0; i
< m
->nr
; ++i
)
1561 if (m
->guest
[i
].index
== msr
)
1564 if (i
== NR_AUTOLOAD_MSRS
) {
1565 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1566 "Can't add msr %x\n", msr
);
1568 } else if (i
== m
->nr
) {
1570 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1571 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1574 m
->guest
[i
].index
= msr
;
1575 m
->guest
[i
].value
= guest_val
;
1576 m
->host
[i
].index
= msr
;
1577 m
->host
[i
].value
= host_val
;
1580 static void reload_tss(void)
1583 * VT restores TR but not its size. Useless.
1585 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1586 struct desc_struct
*descs
;
1588 descs
= (void *)gdt
->address
;
1589 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1593 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1598 guest_efer
= vmx
->vcpu
.arch
.efer
;
1601 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1604 ignore_bits
= EFER_NX
| EFER_SCE
;
1605 #ifdef CONFIG_X86_64
1606 ignore_bits
|= EFER_LMA
| EFER_LME
;
1607 /* SCE is meaningful only in long mode on Intel */
1608 if (guest_efer
& EFER_LMA
)
1609 ignore_bits
&= ~(u64
)EFER_SCE
;
1611 guest_efer
&= ~ignore_bits
;
1612 guest_efer
|= host_efer
& ignore_bits
;
1613 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1614 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1616 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1617 /* On ept, can't emulate nx, and must switch nx atomically */
1618 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1619 guest_efer
= vmx
->vcpu
.arch
.efer
;
1620 if (!(guest_efer
& EFER_LMA
))
1621 guest_efer
&= ~EFER_LME
;
1622 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1629 static unsigned long segment_base(u16 selector
)
1631 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1632 struct desc_struct
*d
;
1633 unsigned long table_base
;
1636 if (!(selector
& ~3))
1639 table_base
= gdt
->address
;
1641 if (selector
& 4) { /* from ldt */
1642 u16 ldt_selector
= kvm_read_ldt();
1644 if (!(ldt_selector
& ~3))
1647 table_base
= segment_base(ldt_selector
);
1649 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1650 v
= get_desc_base(d
);
1651 #ifdef CONFIG_X86_64
1652 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1653 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1658 static inline unsigned long kvm_read_tr_base(void)
1661 asm("str %0" : "=g"(tr
));
1662 return segment_base(tr
);
1665 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1667 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1670 if (vmx
->host_state
.loaded
)
1673 vmx
->host_state
.loaded
= 1;
1675 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1676 * allow segment selectors with cpl > 0 or ti == 1.
1678 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1679 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1680 savesegment(fs
, vmx
->host_state
.fs_sel
);
1681 if (!(vmx
->host_state
.fs_sel
& 7)) {
1682 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1683 vmx
->host_state
.fs_reload_needed
= 0;
1685 vmcs_write16(HOST_FS_SELECTOR
, 0);
1686 vmx
->host_state
.fs_reload_needed
= 1;
1688 savesegment(gs
, vmx
->host_state
.gs_sel
);
1689 if (!(vmx
->host_state
.gs_sel
& 7))
1690 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1692 vmcs_write16(HOST_GS_SELECTOR
, 0);
1693 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1696 #ifdef CONFIG_X86_64
1697 savesegment(ds
, vmx
->host_state
.ds_sel
);
1698 savesegment(es
, vmx
->host_state
.es_sel
);
1701 #ifdef CONFIG_X86_64
1702 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1703 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1705 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1706 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1709 #ifdef CONFIG_X86_64
1710 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1711 if (is_long_mode(&vmx
->vcpu
))
1712 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1714 if (boot_cpu_has(X86_FEATURE_MPX
))
1715 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1716 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1717 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1718 vmx
->guest_msrs
[i
].data
,
1719 vmx
->guest_msrs
[i
].mask
);
1722 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1724 if (!vmx
->host_state
.loaded
)
1727 ++vmx
->vcpu
.stat
.host_state_reload
;
1728 vmx
->host_state
.loaded
= 0;
1729 #ifdef CONFIG_X86_64
1730 if (is_long_mode(&vmx
->vcpu
))
1731 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1733 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1734 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1735 #ifdef CONFIG_X86_64
1736 load_gs_index(vmx
->host_state
.gs_sel
);
1738 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1741 if (vmx
->host_state
.fs_reload_needed
)
1742 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1743 #ifdef CONFIG_X86_64
1744 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1745 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1746 loadsegment(es
, vmx
->host_state
.es_sel
);
1750 #ifdef CONFIG_X86_64
1751 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1753 if (vmx
->host_state
.msr_host_bndcfgs
)
1754 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1756 * If the FPU is not active (through the host task or
1757 * the guest vcpu), then restore the cr0.TS bit.
1759 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1761 load_gdt(&__get_cpu_var(host_gdt
));
1764 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1767 __vmx_load_host_state(vmx
);
1772 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1773 * vcpu mutex is already taken.
1775 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1777 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1778 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1781 kvm_cpu_vmxon(phys_addr
);
1782 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1783 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1785 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1786 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1787 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1790 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1791 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1792 unsigned long sysenter_esp
;
1794 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1795 local_irq_disable();
1796 crash_disable_local_vmclear(cpu
);
1799 * Read loaded_vmcs->cpu should be before fetching
1800 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1801 * See the comments in __loaded_vmcs_clear().
1805 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1806 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1807 crash_enable_local_vmclear(cpu
);
1811 * Linux uses per-cpu TSS and GDT, so set these when switching
1814 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1815 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1817 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1818 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1819 vmx
->loaded_vmcs
->cpu
= cpu
;
1823 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1825 __vmx_load_host_state(to_vmx(vcpu
));
1826 if (!vmm_exclusive
) {
1827 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1833 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1837 if (vcpu
->fpu_active
)
1839 vcpu
->fpu_active
= 1;
1840 cr0
= vmcs_readl(GUEST_CR0
);
1841 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1842 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1843 vmcs_writel(GUEST_CR0
, cr0
);
1844 update_exception_bitmap(vcpu
);
1845 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1846 if (is_guest_mode(vcpu
))
1847 vcpu
->arch
.cr0_guest_owned_bits
&=
1848 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1849 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1852 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1855 * Return the cr0 value that a nested guest would read. This is a combination
1856 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1857 * its hypervisor (cr0_read_shadow).
1859 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1861 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1862 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1864 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1866 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1867 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1870 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1872 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1873 * set this *before* calling this function.
1875 vmx_decache_cr0_guest_bits(vcpu
);
1876 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1877 update_exception_bitmap(vcpu
);
1878 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1879 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1880 if (is_guest_mode(vcpu
)) {
1882 * L1's specified read shadow might not contain the TS bit,
1883 * so now that we turned on shadowing of this bit, we need to
1884 * set this bit of the shadow. Like in nested_vmx_run we need
1885 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1886 * up-to-date here because we just decached cr0.TS (and we'll
1887 * only update vmcs12->guest_cr0 on nested exit).
1889 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1890 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1891 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1892 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1894 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1897 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1899 unsigned long rflags
, save_rflags
;
1901 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1902 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1903 rflags
= vmcs_readl(GUEST_RFLAGS
);
1904 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1905 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1906 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1907 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1909 to_vmx(vcpu
)->rflags
= rflags
;
1911 return to_vmx(vcpu
)->rflags
;
1914 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1916 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1917 to_vmx(vcpu
)->rflags
= rflags
;
1918 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1919 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1920 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1922 vmcs_writel(GUEST_RFLAGS
, rflags
);
1925 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1927 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1930 if (interruptibility
& GUEST_INTR_STATE_STI
)
1931 ret
|= KVM_X86_SHADOW_INT_STI
;
1932 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1933 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1938 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1940 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1941 u32 interruptibility
= interruptibility_old
;
1943 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1945 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1946 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1947 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1948 interruptibility
|= GUEST_INTR_STATE_STI
;
1950 if ((interruptibility
!= interruptibility_old
))
1951 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1954 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1958 rip
= kvm_rip_read(vcpu
);
1959 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1960 kvm_rip_write(vcpu
, rip
);
1962 /* skipping an emulated instruction also counts */
1963 vmx_set_interrupt_shadow(vcpu
, 0);
1967 * KVM wants to inject page-faults which it got to the guest. This function
1968 * checks whether in a nested guest, we need to inject them to L1 or L2.
1970 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1972 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1974 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1977 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
1978 vmcs_read32(VM_EXIT_INTR_INFO
),
1979 vmcs_readl(EXIT_QUALIFICATION
));
1983 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1984 bool has_error_code
, u32 error_code
,
1987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1988 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1990 if (!reinject
&& is_guest_mode(vcpu
) &&
1991 nested_vmx_check_exception(vcpu
, nr
))
1994 if (has_error_code
) {
1995 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1996 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1999 if (vmx
->rmode
.vm86_active
) {
2001 if (kvm_exception_is_soft(nr
))
2002 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2003 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2004 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2008 if (kvm_exception_is_soft(nr
)) {
2009 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2010 vmx
->vcpu
.arch
.event_exit_inst_len
);
2011 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2013 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2015 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2018 static bool vmx_rdtscp_supported(void)
2020 return cpu_has_vmx_rdtscp();
2023 static bool vmx_invpcid_supported(void)
2025 return cpu_has_vmx_invpcid() && enable_ept
;
2029 * Swap MSR entry in host/guest MSR entry array.
2031 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2033 struct shared_msr_entry tmp
;
2035 tmp
= vmx
->guest_msrs
[to
];
2036 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2037 vmx
->guest_msrs
[from
] = tmp
;
2040 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2042 unsigned long *msr_bitmap
;
2044 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2045 if (is_long_mode(vcpu
))
2046 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2048 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2050 if (is_long_mode(vcpu
))
2051 msr_bitmap
= vmx_msr_bitmap_longmode
;
2053 msr_bitmap
= vmx_msr_bitmap_legacy
;
2056 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2060 * Set up the vmcs to automatically save and restore system
2061 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2062 * mode, as fiddling with msrs is very expensive.
2064 static void setup_msrs(struct vcpu_vmx
*vmx
)
2066 int save_nmsrs
, index
;
2069 #ifdef CONFIG_X86_64
2070 if (is_long_mode(&vmx
->vcpu
)) {
2071 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2073 move_msr_up(vmx
, index
, save_nmsrs
++);
2074 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2076 move_msr_up(vmx
, index
, save_nmsrs
++);
2077 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2079 move_msr_up(vmx
, index
, save_nmsrs
++);
2080 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2081 if (index
>= 0 && vmx
->rdtscp_enabled
)
2082 move_msr_up(vmx
, index
, save_nmsrs
++);
2084 * MSR_STAR is only needed on long mode guests, and only
2085 * if efer.sce is enabled.
2087 index
= __find_msr_index(vmx
, MSR_STAR
);
2088 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2089 move_msr_up(vmx
, index
, save_nmsrs
++);
2092 index
= __find_msr_index(vmx
, MSR_EFER
);
2093 if (index
>= 0 && update_transition_efer(vmx
, index
))
2094 move_msr_up(vmx
, index
, save_nmsrs
++);
2096 vmx
->save_nmsrs
= save_nmsrs
;
2098 if (cpu_has_vmx_msr_bitmap())
2099 vmx_set_msr_bitmap(&vmx
->vcpu
);
2103 * reads and returns guest's timestamp counter "register"
2104 * guest_tsc = host_tsc + tsc_offset -- 21.3
2106 static u64
guest_read_tsc(void)
2108 u64 host_tsc
, tsc_offset
;
2111 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2112 return host_tsc
+ tsc_offset
;
2116 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2117 * counter, even if a nested guest (L2) is currently running.
2119 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2123 tsc_offset
= is_guest_mode(vcpu
) ?
2124 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2125 vmcs_read64(TSC_OFFSET
);
2126 return host_tsc
+ tsc_offset
;
2130 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2131 * software catchup for faster rates on slower CPUs.
2133 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2138 if (user_tsc_khz
> tsc_khz
) {
2139 vcpu
->arch
.tsc_catchup
= 1;
2140 vcpu
->arch
.tsc_always_catchup
= 1;
2142 WARN(1, "user requested TSC rate below hardware speed\n");
2145 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2147 return vmcs_read64(TSC_OFFSET
);
2151 * writes 'offset' into guest's timestamp counter offset register
2153 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2155 if (is_guest_mode(vcpu
)) {
2157 * We're here if L1 chose not to trap WRMSR to TSC. According
2158 * to the spec, this should set L1's TSC; The offset that L1
2159 * set for L2 remains unchanged, and still needs to be added
2160 * to the newly set TSC to get L2's TSC.
2162 struct vmcs12
*vmcs12
;
2163 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2164 /* recalculate vmcs02.TSC_OFFSET: */
2165 vmcs12
= get_vmcs12(vcpu
);
2166 vmcs_write64(TSC_OFFSET
, offset
+
2167 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2168 vmcs12
->tsc_offset
: 0));
2170 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2171 vmcs_read64(TSC_OFFSET
), offset
);
2172 vmcs_write64(TSC_OFFSET
, offset
);
2176 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2178 u64 offset
= vmcs_read64(TSC_OFFSET
);
2180 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2181 if (is_guest_mode(vcpu
)) {
2182 /* Even when running L2, the adjustment needs to apply to L1 */
2183 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2185 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2186 offset
+ adjustment
);
2189 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2191 return target_tsc
- native_read_tsc();
2194 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2196 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2197 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2201 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2202 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2203 * all guests if the "nested" module option is off, and can also be disabled
2204 * for a single guest by disabling its VMX cpuid bit.
2206 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2208 return nested
&& guest_cpuid_has_vmx(vcpu
);
2212 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2213 * returned for the various VMX controls MSRs when nested VMX is enabled.
2214 * The same values should also be used to verify that vmcs12 control fields are
2215 * valid during nested entry from L1 to L2.
2216 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2217 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2218 * bit in the high half is on if the corresponding bit in the control field
2219 * may be on. See also vmx_control_verify().
2220 * TODO: allow these variables to be modified (downgraded) by module options
2223 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2224 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2225 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2226 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2227 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2228 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2229 static u32 nested_vmx_ept_caps
;
2230 static __init
void nested_vmx_setup_ctls_msrs(void)
2233 * Note that as a general rule, the high half of the MSRs (bits in
2234 * the control fields which may be 1) should be initialized by the
2235 * intersection of the underlying hardware's MSR (i.e., features which
2236 * can be supported) and the list of features we want to expose -
2237 * because they are known to be properly supported in our code.
2238 * Also, usually, the low half of the MSRs (bits which must be 1) can
2239 * be set to 0, meaning that L1 may turn off any of these bits. The
2240 * reason is that if one of these bits is necessary, it will appear
2241 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2242 * fields of vmcs01 and vmcs02, will turn these bits off - and
2243 * nested_vmx_exit_handled() will not pass related exits to L1.
2244 * These rules have exceptions below.
2247 /* pin-based controls */
2248 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2249 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2251 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2252 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2254 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2255 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2256 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2257 PIN_BASED_VMX_PREEMPTION_TIMER
;
2258 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2262 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2265 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2266 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2267 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2268 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2269 nested_vmx_exit_ctls_high
&=
2270 #ifdef CONFIG_X86_64
2271 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2273 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
|
2274 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2275 if (!(nested_vmx_pinbased_ctls_high
& PIN_BASED_VMX_PREEMPTION_TIMER
) ||
2276 !(nested_vmx_exit_ctls_high
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)) {
2277 nested_vmx_exit_ctls_high
&= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2278 nested_vmx_pinbased_ctls_high
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2280 nested_vmx_exit_ctls_high
|= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2281 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
);
2283 /* entry controls */
2284 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2285 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2286 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2287 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2288 nested_vmx_entry_ctls_high
&=
2289 #ifdef CONFIG_X86_64
2290 VM_ENTRY_IA32E_MODE
|
2292 VM_ENTRY_LOAD_IA32_PAT
;
2293 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2294 VM_ENTRY_LOAD_IA32_EFER
);
2296 /* cpu-based controls */
2297 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2298 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2299 nested_vmx_procbased_ctls_low
= 0;
2300 nested_vmx_procbased_ctls_high
&=
2301 CPU_BASED_VIRTUAL_INTR_PENDING
|
2302 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2303 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2304 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2305 CPU_BASED_CR3_STORE_EXITING
|
2306 #ifdef CONFIG_X86_64
2307 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2309 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2310 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2311 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2312 CPU_BASED_PAUSE_EXITING
|
2313 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2315 * We can allow some features even when not supported by the
2316 * hardware. For example, L1 can specify an MSR bitmap - and we
2317 * can use it to avoid exits to L1 - even when L0 runs L2
2318 * without MSR bitmaps.
2320 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2322 /* secondary cpu-based controls */
2323 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2324 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2325 nested_vmx_secondary_ctls_low
= 0;
2326 nested_vmx_secondary_ctls_high
&=
2327 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2328 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2329 SECONDARY_EXEC_WBINVD_EXITING
;
2332 /* nested EPT: emulate EPT also to L1 */
2333 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2334 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2335 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2337 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2339 * Since invept is completely emulated we support both global
2340 * and context invalidation independent of what host cpu
2343 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2344 VMX_EPT_EXTENT_CONTEXT_BIT
;
2346 nested_vmx_ept_caps
= 0;
2348 /* miscellaneous data */
2349 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2350 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2351 VMX_MISC_SAVE_EFER_LMA
;
2352 nested_vmx_misc_low
|= VMX_MISC_ACTIVITY_HLT
;
2353 nested_vmx_misc_high
= 0;
2356 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2359 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2361 return ((control
& high
) | low
) == control
;
2364 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2366 return low
| ((u64
)high
<< 32);
2369 /* Returns 0 on success, non-0 otherwise. */
2370 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2372 switch (msr_index
) {
2373 case MSR_IA32_VMX_BASIC
:
2375 * This MSR reports some information about VMX support. We
2376 * should return information about the VMX we emulate for the
2377 * guest, and the VMCS structure we give it - not about the
2378 * VMX support of the underlying hardware.
2380 *pdata
= VMCS12_REVISION
|
2381 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2382 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2384 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2385 case MSR_IA32_VMX_PINBASED_CTLS
:
2386 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2387 nested_vmx_pinbased_ctls_high
);
2389 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2390 case MSR_IA32_VMX_PROCBASED_CTLS
:
2391 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2392 nested_vmx_procbased_ctls_high
);
2394 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2395 case MSR_IA32_VMX_EXIT_CTLS
:
2396 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2397 nested_vmx_exit_ctls_high
);
2399 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2400 case MSR_IA32_VMX_ENTRY_CTLS
:
2401 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2402 nested_vmx_entry_ctls_high
);
2404 case MSR_IA32_VMX_MISC
:
2405 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2406 nested_vmx_misc_high
);
2409 * These MSRs specify bits which the guest must keep fixed (on or off)
2410 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2411 * We picked the standard core2 setting.
2413 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2414 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2415 case MSR_IA32_VMX_CR0_FIXED0
:
2416 *pdata
= VMXON_CR0_ALWAYSON
;
2418 case MSR_IA32_VMX_CR0_FIXED1
:
2421 case MSR_IA32_VMX_CR4_FIXED0
:
2422 *pdata
= VMXON_CR4_ALWAYSON
;
2424 case MSR_IA32_VMX_CR4_FIXED1
:
2427 case MSR_IA32_VMX_VMCS_ENUM
:
2430 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2431 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2432 nested_vmx_secondary_ctls_high
);
2434 case MSR_IA32_VMX_EPT_VPID_CAP
:
2435 /* Currently, no nested vpid support */
2436 *pdata
= nested_vmx_ept_caps
;
2446 * Reads an msr value (of 'msr_index') into 'pdata'.
2447 * Returns 0 on success, non-0 otherwise.
2448 * Assumes vcpu_load() was already called.
2450 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2453 struct shared_msr_entry
*msr
;
2456 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2460 switch (msr_index
) {
2461 #ifdef CONFIG_X86_64
2463 data
= vmcs_readl(GUEST_FS_BASE
);
2466 data
= vmcs_readl(GUEST_GS_BASE
);
2468 case MSR_KERNEL_GS_BASE
:
2469 vmx_load_host_state(to_vmx(vcpu
));
2470 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2474 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2476 data
= guest_read_tsc();
2478 case MSR_IA32_SYSENTER_CS
:
2479 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2481 case MSR_IA32_SYSENTER_EIP
:
2482 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2484 case MSR_IA32_SYSENTER_ESP
:
2485 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2487 case MSR_IA32_FEATURE_CONTROL
:
2488 if (!nested_vmx_allowed(vcpu
))
2490 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2492 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2493 if (!nested_vmx_allowed(vcpu
))
2495 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2497 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2499 /* Otherwise falls through */
2501 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2506 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2513 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2516 * Writes msr value into into the appropriate "register".
2517 * Returns 0 on success, non-0 otherwise.
2518 * Assumes vcpu_load() was already called.
2520 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2522 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2523 struct shared_msr_entry
*msr
;
2525 u32 msr_index
= msr_info
->index
;
2526 u64 data
= msr_info
->data
;
2528 switch (msr_index
) {
2530 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2532 #ifdef CONFIG_X86_64
2534 vmx_segment_cache_clear(vmx
);
2535 vmcs_writel(GUEST_FS_BASE
, data
);
2538 vmx_segment_cache_clear(vmx
);
2539 vmcs_writel(GUEST_GS_BASE
, data
);
2541 case MSR_KERNEL_GS_BASE
:
2542 vmx_load_host_state(vmx
);
2543 vmx
->msr_guest_kernel_gs_base
= data
;
2546 case MSR_IA32_SYSENTER_CS
:
2547 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2549 case MSR_IA32_SYSENTER_EIP
:
2550 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2552 case MSR_IA32_SYSENTER_ESP
:
2553 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2556 kvm_write_tsc(vcpu
, msr_info
);
2558 case MSR_IA32_CR_PAT
:
2559 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2560 vmcs_write64(GUEST_IA32_PAT
, data
);
2561 vcpu
->arch
.pat
= data
;
2564 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2566 case MSR_IA32_TSC_ADJUST
:
2567 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2569 case MSR_IA32_FEATURE_CONTROL
:
2570 if (!nested_vmx_allowed(vcpu
) ||
2571 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2572 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2574 vmx
->nested
.msr_ia32_feature_control
= data
;
2575 if (msr_info
->host_initiated
&& data
== 0)
2576 vmx_leave_nested(vcpu
);
2578 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2579 return 1; /* they are read-only */
2581 if (!vmx
->rdtscp_enabled
)
2583 /* Check reserved bit, higher 32 bits should be zero */
2584 if ((data
>> 32) != 0)
2586 /* Otherwise falls through */
2588 msr
= find_msr_entry(vmx
, msr_index
);
2591 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2593 kvm_set_shared_msr(msr
->index
, msr
->data
,
2599 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2605 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2607 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2610 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2613 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2615 case VCPU_EXREG_PDPTR
:
2617 ept_save_pdptrs(vcpu
);
2624 static __init
int cpu_has_kvm_support(void)
2626 return cpu_has_vmx();
2629 static __init
int vmx_disabled_by_bios(void)
2633 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2634 if (msr
& FEATURE_CONTROL_LOCKED
) {
2635 /* launched w/ TXT and VMX disabled */
2636 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2639 /* launched w/o TXT and VMX only enabled w/ TXT */
2640 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2641 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2642 && !tboot_enabled()) {
2643 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2644 "activate TXT before enabling KVM\n");
2647 /* launched w/o TXT and VMX disabled */
2648 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2649 && !tboot_enabled())
2656 static void kvm_cpu_vmxon(u64 addr
)
2658 asm volatile (ASM_VMX_VMXON_RAX
2659 : : "a"(&addr
), "m"(addr
)
2663 static int hardware_enable(void *garbage
)
2665 int cpu
= raw_smp_processor_id();
2666 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2669 if (read_cr4() & X86_CR4_VMXE
)
2672 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2675 * Now we can enable the vmclear operation in kdump
2676 * since the loaded_vmcss_on_cpu list on this cpu
2677 * has been initialized.
2679 * Though the cpu is not in VMX operation now, there
2680 * is no problem to enable the vmclear operation
2681 * for the loaded_vmcss_on_cpu list is empty!
2683 crash_enable_local_vmclear(cpu
);
2685 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2687 test_bits
= FEATURE_CONTROL_LOCKED
;
2688 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2689 if (tboot_enabled())
2690 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2692 if ((old
& test_bits
) != test_bits
) {
2693 /* enable and lock */
2694 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2696 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2698 if (vmm_exclusive
) {
2699 kvm_cpu_vmxon(phys_addr
);
2703 native_store_gdt(&__get_cpu_var(host_gdt
));
2708 static void vmclear_local_loaded_vmcss(void)
2710 int cpu
= raw_smp_processor_id();
2711 struct loaded_vmcs
*v
, *n
;
2713 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2714 loaded_vmcss_on_cpu_link
)
2715 __loaded_vmcs_clear(v
);
2719 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2722 static void kvm_cpu_vmxoff(void)
2724 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2727 static void hardware_disable(void *garbage
)
2729 if (vmm_exclusive
) {
2730 vmclear_local_loaded_vmcss();
2733 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2736 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2737 u32 msr
, u32
*result
)
2739 u32 vmx_msr_low
, vmx_msr_high
;
2740 u32 ctl
= ctl_min
| ctl_opt
;
2742 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2744 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2745 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2747 /* Ensure minimum (required) set of control bits are supported. */
2755 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2757 u32 vmx_msr_low
, vmx_msr_high
;
2759 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2760 return vmx_msr_high
& ctl
;
2763 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2765 u32 vmx_msr_low
, vmx_msr_high
;
2766 u32 min
, opt
, min2
, opt2
;
2767 u32 _pin_based_exec_control
= 0;
2768 u32 _cpu_based_exec_control
= 0;
2769 u32 _cpu_based_2nd_exec_control
= 0;
2770 u32 _vmexit_control
= 0;
2771 u32 _vmentry_control
= 0;
2773 min
= CPU_BASED_HLT_EXITING
|
2774 #ifdef CONFIG_X86_64
2775 CPU_BASED_CR8_LOAD_EXITING
|
2776 CPU_BASED_CR8_STORE_EXITING
|
2778 CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 CPU_BASED_USE_IO_BITMAPS
|
2781 CPU_BASED_MOV_DR_EXITING
|
2782 CPU_BASED_USE_TSC_OFFSETING
|
2783 CPU_BASED_MWAIT_EXITING
|
2784 CPU_BASED_MONITOR_EXITING
|
2785 CPU_BASED_INVLPG_EXITING
|
2786 CPU_BASED_RDPMC_EXITING
;
2788 opt
= CPU_BASED_TPR_SHADOW
|
2789 CPU_BASED_USE_MSR_BITMAPS
|
2790 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2791 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2792 &_cpu_based_exec_control
) < 0)
2794 #ifdef CONFIG_X86_64
2795 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2796 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2797 ~CPU_BASED_CR8_STORE_EXITING
;
2799 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2801 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2802 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2803 SECONDARY_EXEC_WBINVD_EXITING
|
2804 SECONDARY_EXEC_ENABLE_VPID
|
2805 SECONDARY_EXEC_ENABLE_EPT
|
2806 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2807 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2808 SECONDARY_EXEC_RDTSCP
|
2809 SECONDARY_EXEC_ENABLE_INVPCID
|
2810 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2811 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2812 SECONDARY_EXEC_SHADOW_VMCS
;
2813 if (adjust_vmx_controls(min2
, opt2
,
2814 MSR_IA32_VMX_PROCBASED_CTLS2
,
2815 &_cpu_based_2nd_exec_control
) < 0)
2818 #ifndef CONFIG_X86_64
2819 if (!(_cpu_based_2nd_exec_control
&
2820 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2821 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2824 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2825 _cpu_based_2nd_exec_control
&= ~(
2826 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2827 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2828 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2830 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2831 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2833 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2834 CPU_BASED_CR3_STORE_EXITING
|
2835 CPU_BASED_INVLPG_EXITING
);
2836 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2837 vmx_capability
.ept
, vmx_capability
.vpid
);
2841 #ifdef CONFIG_X86_64
2842 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2844 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2845 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2846 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2847 &_vmexit_control
) < 0)
2850 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2851 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2852 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2853 &_pin_based_exec_control
) < 0)
2856 if (!(_cpu_based_2nd_exec_control
&
2857 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2858 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2859 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2862 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2863 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2864 &_vmentry_control
) < 0)
2867 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2869 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2870 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2873 #ifdef CONFIG_X86_64
2874 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2875 if (vmx_msr_high
& (1u<<16))
2879 /* Require Write-Back (WB) memory type for VMCS accesses. */
2880 if (((vmx_msr_high
>> 18) & 15) != 6)
2883 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2884 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2885 vmcs_conf
->revision_id
= vmx_msr_low
;
2887 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2888 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2889 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2890 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2891 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2893 cpu_has_load_ia32_efer
=
2894 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2895 VM_ENTRY_LOAD_IA32_EFER
)
2896 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2897 VM_EXIT_LOAD_IA32_EFER
);
2899 cpu_has_load_perf_global_ctrl
=
2900 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2901 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2902 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2903 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2906 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2907 * but due to arrata below it can't be used. Workaround is to use
2908 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2910 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2915 * BC86,AAY89,BD102 (model 44)
2919 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2920 switch (boot_cpu_data
.x86_model
) {
2926 cpu_has_load_perf_global_ctrl
= false;
2927 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2928 "does not work properly. Using workaround\n");
2938 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2940 int node
= cpu_to_node(cpu
);
2944 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2947 vmcs
= page_address(pages
);
2948 memset(vmcs
, 0, vmcs_config
.size
);
2949 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2953 static struct vmcs
*alloc_vmcs(void)
2955 return alloc_vmcs_cpu(raw_smp_processor_id());
2958 static void free_vmcs(struct vmcs
*vmcs
)
2960 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2964 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2966 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2968 if (!loaded_vmcs
->vmcs
)
2970 loaded_vmcs_clear(loaded_vmcs
);
2971 free_vmcs(loaded_vmcs
->vmcs
);
2972 loaded_vmcs
->vmcs
= NULL
;
2975 static void free_kvm_area(void)
2979 for_each_possible_cpu(cpu
) {
2980 free_vmcs(per_cpu(vmxarea
, cpu
));
2981 per_cpu(vmxarea
, cpu
) = NULL
;
2985 static __init
int alloc_kvm_area(void)
2989 for_each_possible_cpu(cpu
) {
2992 vmcs
= alloc_vmcs_cpu(cpu
);
2998 per_cpu(vmxarea
, cpu
) = vmcs
;
3003 static __init
int hardware_setup(void)
3005 if (setup_vmcs_config(&vmcs_config
) < 0)
3008 if (boot_cpu_has(X86_FEATURE_NX
))
3009 kvm_enable_efer_bits(EFER_NX
);
3011 if (!cpu_has_vmx_vpid())
3013 if (!cpu_has_vmx_shadow_vmcs())
3014 enable_shadow_vmcs
= 0;
3016 if (!cpu_has_vmx_ept() ||
3017 !cpu_has_vmx_ept_4levels()) {
3019 enable_unrestricted_guest
= 0;
3020 enable_ept_ad_bits
= 0;
3023 if (!cpu_has_vmx_ept_ad_bits())
3024 enable_ept_ad_bits
= 0;
3026 if (!cpu_has_vmx_unrestricted_guest())
3027 enable_unrestricted_guest
= 0;
3029 if (!cpu_has_vmx_flexpriority())
3030 flexpriority_enabled
= 0;
3032 if (!cpu_has_vmx_tpr_shadow())
3033 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3035 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3036 kvm_disable_largepages();
3038 if (!cpu_has_vmx_ple())
3041 if (!cpu_has_vmx_apicv())
3045 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3047 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3048 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3049 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3053 nested_vmx_setup_ctls_msrs();
3055 return alloc_kvm_area();
3058 static __exit
void hardware_unsetup(void)
3063 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3065 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3068 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3069 struct kvm_segment
*save
)
3071 if (!emulate_invalid_guest_state
) {
3073 * CS and SS RPL should be equal during guest entry according
3074 * to VMX spec, but in reality it is not always so. Since vcpu
3075 * is in the middle of the transition from real mode to
3076 * protected mode it is safe to assume that RPL 0 is a good
3079 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3080 save
->selector
&= ~SELECTOR_RPL_MASK
;
3081 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3084 vmx_set_segment(vcpu
, save
, seg
);
3087 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3089 unsigned long flags
;
3090 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3093 * Update real mode segment cache. It may be not up-to-date if sement
3094 * register was written while vcpu was in a guest mode.
3096 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3097 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3098 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3099 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3100 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3101 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3103 vmx
->rmode
.vm86_active
= 0;
3105 vmx_segment_cache_clear(vmx
);
3107 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3109 flags
= vmcs_readl(GUEST_RFLAGS
);
3110 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3111 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3112 vmcs_writel(GUEST_RFLAGS
, flags
);
3114 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3115 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3117 update_exception_bitmap(vcpu
);
3119 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3120 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3121 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3122 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3123 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3124 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3126 /* CPL is always 0 when CPU enters protected mode */
3127 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3131 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3133 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3134 struct kvm_segment var
= *save
;
3137 if (seg
== VCPU_SREG_CS
)
3140 if (!emulate_invalid_guest_state
) {
3141 var
.selector
= var
.base
>> 4;
3142 var
.base
= var
.base
& 0xffff0;
3152 if (save
->base
& 0xf)
3153 printk_once(KERN_WARNING
"kvm: segment base is not "
3154 "paragraph aligned when entering "
3155 "protected mode (seg=%d)", seg
);
3158 vmcs_write16(sf
->selector
, var
.selector
);
3159 vmcs_write32(sf
->base
, var
.base
);
3160 vmcs_write32(sf
->limit
, var
.limit
);
3161 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3164 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3166 unsigned long flags
;
3167 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3169 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3170 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3171 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3172 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3173 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3174 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3175 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3177 vmx
->rmode
.vm86_active
= 1;
3180 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3181 * vcpu. Warn the user that an update is overdue.
3183 if (!vcpu
->kvm
->arch
.tss_addr
)
3184 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3185 "called before entering vcpu\n");
3187 vmx_segment_cache_clear(vmx
);
3189 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3190 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3191 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3193 flags
= vmcs_readl(GUEST_RFLAGS
);
3194 vmx
->rmode
.save_rflags
= flags
;
3196 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3198 vmcs_writel(GUEST_RFLAGS
, flags
);
3199 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3200 update_exception_bitmap(vcpu
);
3202 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3203 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3204 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3205 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3206 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3207 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3209 kvm_mmu_reset_context(vcpu
);
3212 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3214 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3215 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3221 * Force kernel_gs_base reloading before EFER changes, as control
3222 * of this msr depends on is_long_mode().
3224 vmx_load_host_state(to_vmx(vcpu
));
3225 vcpu
->arch
.efer
= efer
;
3226 if (efer
& EFER_LMA
) {
3227 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3230 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3232 msr
->data
= efer
& ~EFER_LME
;
3237 #ifdef CONFIG_X86_64
3239 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3243 vmx_segment_cache_clear(to_vmx(vcpu
));
3245 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3246 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3247 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3249 vmcs_write32(GUEST_TR_AR_BYTES
,
3250 (guest_tr_ar
& ~AR_TYPE_MASK
)
3251 | AR_TYPE_BUSY_64_TSS
);
3253 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3256 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3258 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3259 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3264 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3266 vpid_sync_context(to_vmx(vcpu
));
3268 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3270 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3274 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3276 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3278 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3279 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3282 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3284 if (enable_ept
&& is_paging(vcpu
))
3285 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3286 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3289 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3291 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3293 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3294 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3297 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3299 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3301 if (!test_bit(VCPU_EXREG_PDPTR
,
3302 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3305 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3306 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3307 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3308 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3309 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3313 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3315 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3317 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3318 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3319 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3320 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3321 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3324 __set_bit(VCPU_EXREG_PDPTR
,
3325 (unsigned long *)&vcpu
->arch
.regs_avail
);
3326 __set_bit(VCPU_EXREG_PDPTR
,
3327 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3330 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3332 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3334 struct kvm_vcpu
*vcpu
)
3336 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3337 vmx_decache_cr3(vcpu
);
3338 if (!(cr0
& X86_CR0_PG
)) {
3339 /* From paging/starting to nonpaging */
3340 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3341 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3342 (CPU_BASED_CR3_LOAD_EXITING
|
3343 CPU_BASED_CR3_STORE_EXITING
));
3344 vcpu
->arch
.cr0
= cr0
;
3345 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3346 } else if (!is_paging(vcpu
)) {
3347 /* From nonpaging to paging */
3348 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3349 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3350 ~(CPU_BASED_CR3_LOAD_EXITING
|
3351 CPU_BASED_CR3_STORE_EXITING
));
3352 vcpu
->arch
.cr0
= cr0
;
3353 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3356 if (!(cr0
& X86_CR0_WP
))
3357 *hw_cr0
&= ~X86_CR0_WP
;
3360 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3362 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3363 unsigned long hw_cr0
;
3365 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3366 if (enable_unrestricted_guest
)
3367 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3369 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3371 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3374 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3378 #ifdef CONFIG_X86_64
3379 if (vcpu
->arch
.efer
& EFER_LME
) {
3380 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3382 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3388 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3390 if (!vcpu
->fpu_active
)
3391 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3393 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3394 vmcs_writel(GUEST_CR0
, hw_cr0
);
3395 vcpu
->arch
.cr0
= cr0
;
3397 /* depends on vcpu->arch.cr0 to be set to a new value */
3398 vmx
->emulation_required
= emulation_required(vcpu
);
3401 static u64
construct_eptp(unsigned long root_hpa
)
3405 /* TODO write the value reading from MSR */
3406 eptp
= VMX_EPT_DEFAULT_MT
|
3407 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3408 if (enable_ept_ad_bits
)
3409 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3410 eptp
|= (root_hpa
& PAGE_MASK
);
3415 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3417 unsigned long guest_cr3
;
3422 eptp
= construct_eptp(cr3
);
3423 vmcs_write64(EPT_POINTER
, eptp
);
3424 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3425 guest_cr3
= kvm_read_cr3(vcpu
);
3427 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3428 ept_load_pdptrs(vcpu
);
3431 vmx_flush_tlb(vcpu
);
3432 vmcs_writel(GUEST_CR3
, guest_cr3
);
3435 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3437 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3438 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3440 if (cr4
& X86_CR4_VMXE
) {
3442 * To use VMXON (and later other VMX instructions), a guest
3443 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3444 * So basically the check on whether to allow nested VMX
3447 if (!nested_vmx_allowed(vcpu
))
3450 if (to_vmx(vcpu
)->nested
.vmxon
&&
3451 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3454 vcpu
->arch
.cr4
= cr4
;
3456 if (!is_paging(vcpu
)) {
3457 hw_cr4
&= ~X86_CR4_PAE
;
3458 hw_cr4
|= X86_CR4_PSE
;
3460 * SMEP is disabled if CPU is in non-paging mode in
3461 * hardware. However KVM always uses paging mode to
3462 * emulate guest non-paging mode with TDP.
3463 * To emulate this behavior, SMEP needs to be manually
3464 * disabled when guest switches to non-paging mode.
3466 hw_cr4
&= ~X86_CR4_SMEP
;
3467 } else if (!(cr4
& X86_CR4_PAE
)) {
3468 hw_cr4
&= ~X86_CR4_PAE
;
3472 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3473 vmcs_writel(GUEST_CR4
, hw_cr4
);
3477 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3478 struct kvm_segment
*var
, int seg
)
3480 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3483 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3484 *var
= vmx
->rmode
.segs
[seg
];
3485 if (seg
== VCPU_SREG_TR
3486 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3488 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3489 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3492 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3493 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3494 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3495 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3496 var
->unusable
= (ar
>> 16) & 1;
3497 var
->type
= ar
& 15;
3498 var
->s
= (ar
>> 4) & 1;
3499 var
->dpl
= (ar
>> 5) & 3;
3501 * Some userspaces do not preserve unusable property. Since usable
3502 * segment has to be present according to VMX spec we can use present
3503 * property to amend userspace bug by making unusable segment always
3504 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3505 * segment as unusable.
3507 var
->present
= !var
->unusable
;
3508 var
->avl
= (ar
>> 12) & 1;
3509 var
->l
= (ar
>> 13) & 1;
3510 var
->db
= (ar
>> 14) & 1;
3511 var
->g
= (ar
>> 15) & 1;
3514 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3516 struct kvm_segment s
;
3518 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3519 vmx_get_segment(vcpu
, &s
, seg
);
3522 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3525 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3527 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3529 if (!is_protmode(vcpu
))
3532 if (!is_long_mode(vcpu
)
3533 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3536 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3537 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3538 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3545 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3549 if (var
->unusable
|| !var
->present
)
3552 ar
= var
->type
& 15;
3553 ar
|= (var
->s
& 1) << 4;
3554 ar
|= (var
->dpl
& 3) << 5;
3555 ar
|= (var
->present
& 1) << 7;
3556 ar
|= (var
->avl
& 1) << 12;
3557 ar
|= (var
->l
& 1) << 13;
3558 ar
|= (var
->db
& 1) << 14;
3559 ar
|= (var
->g
& 1) << 15;
3565 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3566 struct kvm_segment
*var
, int seg
)
3568 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3569 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3571 vmx_segment_cache_clear(vmx
);
3572 if (seg
== VCPU_SREG_CS
)
3573 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3575 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3576 vmx
->rmode
.segs
[seg
] = *var
;
3577 if (seg
== VCPU_SREG_TR
)
3578 vmcs_write16(sf
->selector
, var
->selector
);
3580 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3584 vmcs_writel(sf
->base
, var
->base
);
3585 vmcs_write32(sf
->limit
, var
->limit
);
3586 vmcs_write16(sf
->selector
, var
->selector
);
3589 * Fix the "Accessed" bit in AR field of segment registers for older
3591 * IA32 arch specifies that at the time of processor reset the
3592 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3593 * is setting it to 0 in the userland code. This causes invalid guest
3594 * state vmexit when "unrestricted guest" mode is turned on.
3595 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3596 * tree. Newer qemu binaries with that qemu fix would not need this
3599 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3600 var
->type
|= 0x1; /* Accessed */
3602 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3605 vmx
->emulation_required
|= emulation_required(vcpu
);
3608 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3610 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3612 *db
= (ar
>> 14) & 1;
3613 *l
= (ar
>> 13) & 1;
3616 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3618 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3619 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3622 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3624 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3625 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3628 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3630 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3631 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3634 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3636 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3637 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3640 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3642 struct kvm_segment var
;
3645 vmx_get_segment(vcpu
, &var
, seg
);
3647 if (seg
== VCPU_SREG_CS
)
3649 ar
= vmx_segment_access_rights(&var
);
3651 if (var
.base
!= (var
.selector
<< 4))
3653 if (var
.limit
!= 0xffff)
3661 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3663 struct kvm_segment cs
;
3664 unsigned int cs_rpl
;
3666 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3667 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3671 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3675 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3676 if (cs
.dpl
> cs_rpl
)
3679 if (cs
.dpl
!= cs_rpl
)
3685 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3689 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3691 struct kvm_segment ss
;
3692 unsigned int ss_rpl
;
3694 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3695 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3699 if (ss
.type
!= 3 && ss
.type
!= 7)
3703 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3711 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3713 struct kvm_segment var
;
3716 vmx_get_segment(vcpu
, &var
, seg
);
3717 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3725 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3726 if (var
.dpl
< rpl
) /* DPL < RPL */
3730 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3736 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3738 struct kvm_segment tr
;
3740 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3744 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3746 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3754 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3756 struct kvm_segment ldtr
;
3758 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3762 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3772 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3774 struct kvm_segment cs
, ss
;
3776 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3777 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3779 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3780 (ss
.selector
& SELECTOR_RPL_MASK
));
3784 * Check if guest state is valid. Returns true if valid, false if
3786 * We assume that registers are always usable
3788 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3790 if (enable_unrestricted_guest
)
3793 /* real mode guest state checks */
3794 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3795 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3797 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3799 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3801 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3803 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3805 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3808 /* protected mode guest state checks */
3809 if (!cs_ss_rpl_check(vcpu
))
3811 if (!code_segment_valid(vcpu
))
3813 if (!stack_segment_valid(vcpu
))
3815 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3817 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3819 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3821 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3823 if (!tr_valid(vcpu
))
3825 if (!ldtr_valid(vcpu
))
3829 * - Add checks on RIP
3830 * - Add checks on RFLAGS
3836 static int init_rmode_tss(struct kvm
*kvm
)
3840 int r
, idx
, ret
= 0;
3842 idx
= srcu_read_lock(&kvm
->srcu
);
3843 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3844 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3847 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3848 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3849 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3852 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3855 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3859 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3860 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3867 srcu_read_unlock(&kvm
->srcu
, idx
);
3871 static int init_rmode_identity_map(struct kvm
*kvm
)
3874 pfn_t identity_map_pfn
;
3879 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3880 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3881 "haven't been allocated!\n");
3884 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3887 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3888 idx
= srcu_read_lock(&kvm
->srcu
);
3889 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3892 /* Set up identity-mapping pagetable for EPT in real mode */
3893 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3894 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3895 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3896 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3897 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3901 kvm
->arch
.ept_identity_pagetable_done
= true;
3904 srcu_read_unlock(&kvm
->srcu
, idx
);
3908 static void seg_setup(int seg
)
3910 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3913 vmcs_write16(sf
->selector
, 0);
3914 vmcs_writel(sf
->base
, 0);
3915 vmcs_write32(sf
->limit
, 0xffff);
3917 if (seg
== VCPU_SREG_CS
)
3918 ar
|= 0x08; /* code segment */
3920 vmcs_write32(sf
->ar_bytes
, ar
);
3923 static int alloc_apic_access_page(struct kvm
*kvm
)
3926 struct kvm_userspace_memory_region kvm_userspace_mem
;
3929 mutex_lock(&kvm
->slots_lock
);
3930 if (kvm
->arch
.apic_access_page
)
3932 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3933 kvm_userspace_mem
.flags
= 0;
3934 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3935 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3936 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3940 page
= gfn_to_page(kvm
, 0xfee00);
3941 if (is_error_page(page
)) {
3946 kvm
->arch
.apic_access_page
= page
;
3948 mutex_unlock(&kvm
->slots_lock
);
3952 static int alloc_identity_pagetable(struct kvm
*kvm
)
3955 struct kvm_userspace_memory_region kvm_userspace_mem
;
3958 mutex_lock(&kvm
->slots_lock
);
3959 if (kvm
->arch
.ept_identity_pagetable
)
3961 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3962 kvm_userspace_mem
.flags
= 0;
3963 kvm_userspace_mem
.guest_phys_addr
=
3964 kvm
->arch
.ept_identity_map_addr
;
3965 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3966 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3970 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3971 if (is_error_page(page
)) {
3976 kvm
->arch
.ept_identity_pagetable
= page
;
3978 mutex_unlock(&kvm
->slots_lock
);
3982 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3989 spin_lock(&vmx_vpid_lock
);
3990 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3991 if (vpid
< VMX_NR_VPIDS
) {
3993 __set_bit(vpid
, vmx_vpid_bitmap
);
3995 spin_unlock(&vmx_vpid_lock
);
3998 static void free_vpid(struct vcpu_vmx
*vmx
)
4002 spin_lock(&vmx_vpid_lock
);
4004 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4005 spin_unlock(&vmx_vpid_lock
);
4008 #define MSR_TYPE_R 1
4009 #define MSR_TYPE_W 2
4010 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4013 int f
= sizeof(unsigned long);
4015 if (!cpu_has_vmx_msr_bitmap())
4019 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4020 * have the write-low and read-high bitmap offsets the wrong way round.
4021 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4023 if (msr
<= 0x1fff) {
4024 if (type
& MSR_TYPE_R
)
4026 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4028 if (type
& MSR_TYPE_W
)
4030 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4032 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4034 if (type
& MSR_TYPE_R
)
4036 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4038 if (type
& MSR_TYPE_W
)
4040 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4045 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4048 int f
= sizeof(unsigned long);
4050 if (!cpu_has_vmx_msr_bitmap())
4054 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4055 * have the write-low and read-high bitmap offsets the wrong way round.
4056 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4058 if (msr
<= 0x1fff) {
4059 if (type
& MSR_TYPE_R
)
4061 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4063 if (type
& MSR_TYPE_W
)
4065 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4067 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4069 if (type
& MSR_TYPE_R
)
4071 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4073 if (type
& MSR_TYPE_W
)
4075 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4080 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4083 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4084 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4085 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4086 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4089 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4091 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4093 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4097 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4099 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4101 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4105 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4107 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4109 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4113 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4115 return enable_apicv
&& irqchip_in_kernel(kvm
);
4119 * Send interrupt to vcpu via posted interrupt way.
4120 * 1. If target vcpu is running(non-root mode), send posted interrupt
4121 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4122 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4123 * interrupt from PIR in next vmentry.
4125 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4127 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4130 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4133 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4134 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4136 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4137 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4138 POSTED_INTR_VECTOR
);
4141 kvm_vcpu_kick(vcpu
);
4144 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4146 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4148 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4151 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4154 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4160 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4161 * will not change in the lifetime of the guest.
4162 * Note that host-state that does change is set elsewhere. E.g., host-state
4163 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4165 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4171 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4172 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4173 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4175 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4176 #ifdef CONFIG_X86_64
4178 * Load null selectors, so we can avoid reloading them in
4179 * __vmx_load_host_state(), in case userspace uses the null selectors
4180 * too (the expected case).
4182 vmcs_write16(HOST_DS_SELECTOR
, 0);
4183 vmcs_write16(HOST_ES_SELECTOR
, 0);
4185 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4186 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4188 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4189 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4191 native_store_idt(&dt
);
4192 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4193 vmx
->host_idt_base
= dt
.address
;
4195 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4197 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4198 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4199 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4200 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4202 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4203 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4204 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4208 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4210 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4212 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4213 if (is_guest_mode(&vmx
->vcpu
))
4214 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4215 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4216 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4219 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4221 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4223 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4224 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4225 return pin_based_exec_ctrl
;
4228 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4230 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4231 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4232 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4233 #ifdef CONFIG_X86_64
4234 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4235 CPU_BASED_CR8_LOAD_EXITING
;
4239 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4240 CPU_BASED_CR3_LOAD_EXITING
|
4241 CPU_BASED_INVLPG_EXITING
;
4242 return exec_control
;
4245 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4247 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4248 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4249 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4251 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4253 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4254 enable_unrestricted_guest
= 0;
4255 /* Enable INVPCID for non-ept guests may cause performance regression. */
4256 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4258 if (!enable_unrestricted_guest
)
4259 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4261 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4262 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4263 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4264 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4265 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4266 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4268 We can NOT enable shadow_vmcs here because we don't have yet
4271 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4272 return exec_control
;
4275 static void ept_set_mmio_spte_mask(void)
4278 * EPT Misconfigurations can be generated if the value of bits 2:0
4279 * of an EPT paging-structure entry is 110b (write/execute).
4280 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4283 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4287 * Sets up the vmcs for emulated real mode.
4289 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4291 #ifdef CONFIG_X86_64
4297 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4298 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4300 if (enable_shadow_vmcs
) {
4301 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4302 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4304 if (cpu_has_vmx_msr_bitmap())
4305 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4307 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4310 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4312 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4314 if (cpu_has_secondary_exec_ctrls()) {
4315 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4316 vmx_secondary_exec_control(vmx
));
4319 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4320 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4321 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4322 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4323 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4325 vmcs_write16(GUEST_INTR_STATUS
, 0);
4327 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4328 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4332 vmcs_write32(PLE_GAP
, ple_gap
);
4333 vmcs_write32(PLE_WINDOW
, ple_window
);
4336 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4337 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4338 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4340 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4341 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4342 vmx_set_constant_host_state(vmx
);
4343 #ifdef CONFIG_X86_64
4344 rdmsrl(MSR_FS_BASE
, a
);
4345 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4346 rdmsrl(MSR_GS_BASE
, a
);
4347 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4349 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4350 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4353 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4354 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4355 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4356 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4357 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4359 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4360 u32 msr_low
, msr_high
;
4362 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4363 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4364 /* Write the default value follow host pat */
4365 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4366 /* Keep arch.pat sync with GUEST_IA32_PAT */
4367 vmx
->vcpu
.arch
.pat
= host_pat
;
4370 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4371 u32 index
= vmx_msr_index
[i
];
4372 u32 data_low
, data_high
;
4375 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4377 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4379 vmx
->guest_msrs
[j
].index
= i
;
4380 vmx
->guest_msrs
[j
].data
= 0;
4381 vmx
->guest_msrs
[j
].mask
= -1ull;
4386 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4388 /* 22.2.1, 20.8.1 */
4389 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4391 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4392 set_cr4_guest_host_mask(vmx
);
4397 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4399 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4400 struct msr_data apic_base_msr
;
4402 vmx
->rmode
.vm86_active
= 0;
4404 vmx
->soft_vnmi_blocked
= 0;
4406 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4407 kvm_set_cr8(&vmx
->vcpu
, 0);
4408 apic_base_msr
.data
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4409 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4410 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4411 apic_base_msr
.host_initiated
= true;
4412 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4414 vmx_segment_cache_clear(vmx
);
4416 seg_setup(VCPU_SREG_CS
);
4417 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4418 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4420 seg_setup(VCPU_SREG_DS
);
4421 seg_setup(VCPU_SREG_ES
);
4422 seg_setup(VCPU_SREG_FS
);
4423 seg_setup(VCPU_SREG_GS
);
4424 seg_setup(VCPU_SREG_SS
);
4426 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4427 vmcs_writel(GUEST_TR_BASE
, 0);
4428 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4429 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4431 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4432 vmcs_writel(GUEST_LDTR_BASE
, 0);
4433 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4434 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4436 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4437 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4438 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4440 vmcs_writel(GUEST_RFLAGS
, 0x02);
4441 kvm_rip_write(vcpu
, 0xfff0);
4443 vmcs_writel(GUEST_GDTR_BASE
, 0);
4444 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4446 vmcs_writel(GUEST_IDTR_BASE
, 0);
4447 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4449 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4450 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4451 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4453 /* Special registers */
4454 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4458 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4460 if (cpu_has_vmx_tpr_shadow()) {
4461 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4462 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4463 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4464 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4465 vmcs_write32(TPR_THRESHOLD
, 0);
4468 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4469 vmcs_write64(APIC_ACCESS_ADDR
,
4470 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4472 if (vmx_vm_has_apicv(vcpu
->kvm
))
4473 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4476 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4478 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4479 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4480 vmx_set_cr4(&vmx
->vcpu
, 0);
4481 vmx_set_efer(&vmx
->vcpu
, 0);
4482 vmx_fpu_activate(&vmx
->vcpu
);
4483 update_exception_bitmap(&vmx
->vcpu
);
4485 vpid_sync_context(vmx
);
4489 * In nested virtualization, check if L1 asked to exit on external interrupts.
4490 * For most existing hypervisors, this will always return true.
4492 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4494 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4495 PIN_BASED_EXT_INTR_MASK
;
4498 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4500 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4501 PIN_BASED_NMI_EXITING
;
4504 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4506 u32 cpu_based_vm_exec_control
;
4508 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4510 * We get here if vmx_interrupt_allowed() said we can't
4511 * inject to L1 now because L2 must run. The caller will have
4512 * to make L2 exit right after entry, so we can inject to L1
4517 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4518 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4519 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4523 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4525 u32 cpu_based_vm_exec_control
;
4527 if (!cpu_has_virtual_nmis())
4528 return enable_irq_window(vcpu
);
4530 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4531 return enable_irq_window(vcpu
);
4533 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4534 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4535 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4539 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4543 int irq
= vcpu
->arch
.interrupt
.nr
;
4545 trace_kvm_inj_virq(irq
);
4547 ++vcpu
->stat
.irq_injections
;
4548 if (vmx
->rmode
.vm86_active
) {
4550 if (vcpu
->arch
.interrupt
.soft
)
4551 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4552 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4553 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4556 intr
= irq
| INTR_INFO_VALID_MASK
;
4557 if (vcpu
->arch
.interrupt
.soft
) {
4558 intr
|= INTR_TYPE_SOFT_INTR
;
4559 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4560 vmx
->vcpu
.arch
.event_exit_inst_len
);
4562 intr
|= INTR_TYPE_EXT_INTR
;
4563 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4566 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4568 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4570 if (is_guest_mode(vcpu
))
4573 if (!cpu_has_virtual_nmis()) {
4575 * Tracking the NMI-blocked state in software is built upon
4576 * finding the next open IRQ window. This, in turn, depends on
4577 * well-behaving guests: They have to keep IRQs disabled at
4578 * least as long as the NMI handler runs. Otherwise we may
4579 * cause NMI nesting, maybe breaking the guest. But as this is
4580 * highly unlikely, we can live with the residual risk.
4582 vmx
->soft_vnmi_blocked
= 1;
4583 vmx
->vnmi_blocked_time
= 0;
4586 ++vcpu
->stat
.nmi_injections
;
4587 vmx
->nmi_known_unmasked
= false;
4588 if (vmx
->rmode
.vm86_active
) {
4589 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4590 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4593 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4594 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4597 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4599 if (!cpu_has_virtual_nmis())
4600 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4601 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4603 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4606 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4608 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4610 if (!cpu_has_virtual_nmis()) {
4611 if (vmx
->soft_vnmi_blocked
!= masked
) {
4612 vmx
->soft_vnmi_blocked
= masked
;
4613 vmx
->vnmi_blocked_time
= 0;
4616 vmx
->nmi_known_unmasked
= !masked
;
4618 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4619 GUEST_INTR_STATE_NMI
);
4621 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4622 GUEST_INTR_STATE_NMI
);
4626 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4628 if (is_guest_mode(vcpu
)) {
4629 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4631 if (nested_exit_on_nmi(vcpu
)) {
4632 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
4633 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
4634 INTR_INFO_VALID_MASK
, 0);
4636 * The NMI-triggered VM exit counts as injection:
4637 * clear this one and block further NMIs.
4639 vcpu
->arch
.nmi_pending
= 0;
4640 vmx_set_nmi_mask(vcpu
, true);
4645 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4648 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4649 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4650 | GUEST_INTR_STATE_NMI
));
4653 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4655 if (is_guest_mode(vcpu
)) {
4656 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4658 if (nested_exit_on_intr(vcpu
)) {
4659 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
,
4662 * fall through to normal code, but now in L1, not L2
4667 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4668 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4669 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4672 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4675 struct kvm_userspace_memory_region tss_mem
= {
4676 .slot
= TSS_PRIVATE_MEMSLOT
,
4677 .guest_phys_addr
= addr
,
4678 .memory_size
= PAGE_SIZE
* 3,
4682 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4685 kvm
->arch
.tss_addr
= addr
;
4686 if (!init_rmode_tss(kvm
))
4692 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4697 * Update instruction length as we may reinject the exception
4698 * from user space while in guest debugging mode.
4700 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4701 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4702 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4706 if (vcpu
->guest_debug
&
4707 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4724 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4725 int vec
, u32 err_code
)
4728 * Instruction with address size override prefix opcode 0x67
4729 * Cause the #SS fault with 0 error code in VM86 mode.
4731 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4732 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4733 if (vcpu
->arch
.halt_request
) {
4734 vcpu
->arch
.halt_request
= 0;
4735 return kvm_emulate_halt(vcpu
);
4743 * Forward all other exceptions that are valid in real mode.
4744 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4745 * the required debugging infrastructure rework.
4747 kvm_queue_exception(vcpu
, vec
);
4752 * Trigger machine check on the host. We assume all the MSRs are already set up
4753 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4754 * We pass a fake environment to the machine check handler because we want
4755 * the guest to be always treated like user space, no matter what context
4756 * it used internally.
4758 static void kvm_machine_check(void)
4760 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4761 struct pt_regs regs
= {
4762 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4763 .flags
= X86_EFLAGS_IF
,
4766 do_machine_check(®s
, 0);
4770 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4772 /* already handled by vcpu_run */
4776 static int handle_exception(struct kvm_vcpu
*vcpu
)
4778 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4779 struct kvm_run
*kvm_run
= vcpu
->run
;
4780 u32 intr_info
, ex_no
, error_code
;
4781 unsigned long cr2
, rip
, dr6
;
4783 enum emulation_result er
;
4785 vect_info
= vmx
->idt_vectoring_info
;
4786 intr_info
= vmx
->exit_intr_info
;
4788 if (is_machine_check(intr_info
))
4789 return handle_machine_check(vcpu
);
4791 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4792 return 1; /* already handled by vmx_vcpu_run() */
4794 if (is_no_device(intr_info
)) {
4795 vmx_fpu_activate(vcpu
);
4799 if (is_invalid_opcode(intr_info
)) {
4800 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4801 if (er
!= EMULATE_DONE
)
4802 kvm_queue_exception(vcpu
, UD_VECTOR
);
4807 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4808 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4811 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4812 * MMIO, it is better to report an internal error.
4813 * See the comments in vmx_handle_exit.
4815 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4816 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4817 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4818 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4819 vcpu
->run
->internal
.ndata
= 2;
4820 vcpu
->run
->internal
.data
[0] = vect_info
;
4821 vcpu
->run
->internal
.data
[1] = intr_info
;
4825 if (is_page_fault(intr_info
)) {
4826 /* EPT won't cause page fault directly */
4828 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4829 trace_kvm_page_fault(cr2
, error_code
);
4831 if (kvm_event_needs_reinjection(vcpu
))
4832 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4833 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4836 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4838 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4839 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4843 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4844 if (!(vcpu
->guest_debug
&
4845 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4846 vcpu
->arch
.dr6
&= ~15;
4847 vcpu
->arch
.dr6
|= dr6
;
4848 kvm_queue_exception(vcpu
, DB_VECTOR
);
4851 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4852 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4856 * Update instruction length as we may reinject #BP from
4857 * user space while in guest debugging mode. Reading it for
4858 * #DB as well causes no harm, it is not used in that case.
4860 vmx
->vcpu
.arch
.event_exit_inst_len
=
4861 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4862 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4863 rip
= kvm_rip_read(vcpu
);
4864 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4865 kvm_run
->debug
.arch
.exception
= ex_no
;
4868 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4869 kvm_run
->ex
.exception
= ex_no
;
4870 kvm_run
->ex
.error_code
= error_code
;
4876 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4878 ++vcpu
->stat
.irq_exits
;
4882 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4884 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4888 static int handle_io(struct kvm_vcpu
*vcpu
)
4890 unsigned long exit_qualification
;
4891 int size
, in
, string
;
4894 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4895 string
= (exit_qualification
& 16) != 0;
4896 in
= (exit_qualification
& 8) != 0;
4898 ++vcpu
->stat
.io_exits
;
4901 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4903 port
= exit_qualification
>> 16;
4904 size
= (exit_qualification
& 7) + 1;
4905 skip_emulated_instruction(vcpu
);
4907 return kvm_fast_pio_out(vcpu
, size
, port
);
4911 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4914 * Patch in the VMCALL instruction:
4916 hypercall
[0] = 0x0f;
4917 hypercall
[1] = 0x01;
4918 hypercall
[2] = 0xc1;
4921 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4923 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4925 if (nested_vmx_secondary_ctls_high
&
4926 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4927 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4928 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4929 return (val
& always_on
) == always_on
;
4932 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4933 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4935 if (is_guest_mode(vcpu
)) {
4936 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4937 unsigned long orig_val
= val
;
4940 * We get here when L2 changed cr0 in a way that did not change
4941 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4942 * but did change L0 shadowed bits. So we first calculate the
4943 * effective cr0 value that L1 would like to write into the
4944 * hardware. It consists of the L2-owned bits from the new
4945 * value combined with the L1-owned bits from L1's guest_cr0.
4947 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4948 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4950 if (!nested_cr0_valid(vmcs12
, val
))
4953 if (kvm_set_cr0(vcpu
, val
))
4955 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4958 if (to_vmx(vcpu
)->nested
.vmxon
&&
4959 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4961 return kvm_set_cr0(vcpu
, val
);
4965 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4967 if (is_guest_mode(vcpu
)) {
4968 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4969 unsigned long orig_val
= val
;
4971 /* analogously to handle_set_cr0 */
4972 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4973 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4974 if (kvm_set_cr4(vcpu
, val
))
4976 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4979 return kvm_set_cr4(vcpu
, val
);
4982 /* called to set cr0 as approriate for clts instruction exit. */
4983 static void handle_clts(struct kvm_vcpu
*vcpu
)
4985 if (is_guest_mode(vcpu
)) {
4987 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4988 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4989 * just pretend it's off (also in arch.cr0 for fpu_activate).
4991 vmcs_writel(CR0_READ_SHADOW
,
4992 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4993 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4995 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4998 static int handle_cr(struct kvm_vcpu
*vcpu
)
5000 unsigned long exit_qualification
, val
;
5005 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5006 cr
= exit_qualification
& 15;
5007 reg
= (exit_qualification
>> 8) & 15;
5008 switch ((exit_qualification
>> 4) & 3) {
5009 case 0: /* mov to cr */
5010 val
= kvm_register_read(vcpu
, reg
);
5011 trace_kvm_cr_write(cr
, val
);
5014 err
= handle_set_cr0(vcpu
, val
);
5015 kvm_complete_insn_gp(vcpu
, err
);
5018 err
= kvm_set_cr3(vcpu
, val
);
5019 kvm_complete_insn_gp(vcpu
, err
);
5022 err
= handle_set_cr4(vcpu
, val
);
5023 kvm_complete_insn_gp(vcpu
, err
);
5026 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5027 u8 cr8
= kvm_register_read(vcpu
, reg
);
5028 err
= kvm_set_cr8(vcpu
, cr8
);
5029 kvm_complete_insn_gp(vcpu
, err
);
5030 if (irqchip_in_kernel(vcpu
->kvm
))
5032 if (cr8_prev
<= cr8
)
5034 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5041 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5042 skip_emulated_instruction(vcpu
);
5043 vmx_fpu_activate(vcpu
);
5045 case 1: /*mov from cr*/
5048 val
= kvm_read_cr3(vcpu
);
5049 kvm_register_write(vcpu
, reg
, val
);
5050 trace_kvm_cr_read(cr
, val
);
5051 skip_emulated_instruction(vcpu
);
5054 val
= kvm_get_cr8(vcpu
);
5055 kvm_register_write(vcpu
, reg
, val
);
5056 trace_kvm_cr_read(cr
, val
);
5057 skip_emulated_instruction(vcpu
);
5062 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5063 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5064 kvm_lmsw(vcpu
, val
);
5066 skip_emulated_instruction(vcpu
);
5071 vcpu
->run
->exit_reason
= 0;
5072 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5073 (int)(exit_qualification
>> 4) & 3, cr
);
5077 static int handle_dr(struct kvm_vcpu
*vcpu
)
5079 unsigned long exit_qualification
;
5082 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5083 if (!kvm_require_cpl(vcpu
, 0))
5085 dr
= vmcs_readl(GUEST_DR7
);
5088 * As the vm-exit takes precedence over the debug trap, we
5089 * need to emulate the latter, either for the host or the
5090 * guest debugging itself.
5092 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5093 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5094 vcpu
->run
->debug
.arch
.dr7
= dr
;
5095 vcpu
->run
->debug
.arch
.pc
=
5096 vmcs_readl(GUEST_CS_BASE
) +
5097 vmcs_readl(GUEST_RIP
);
5098 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5099 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5102 vcpu
->arch
.dr7
&= ~DR7_GD
;
5103 vcpu
->arch
.dr6
|= DR6_BD
;
5104 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5105 kvm_queue_exception(vcpu
, DB_VECTOR
);
5110 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5111 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5112 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5113 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5116 if (kvm_get_dr(vcpu
, dr
, &val
))
5118 kvm_register_write(vcpu
, reg
, val
);
5120 if (kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]))
5123 skip_emulated_instruction(vcpu
);
5127 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5129 return vcpu
->arch
.dr6
;
5132 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5136 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5138 vmcs_writel(GUEST_DR7
, val
);
5141 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5143 kvm_emulate_cpuid(vcpu
);
5147 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5149 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5152 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5153 trace_kvm_msr_read_ex(ecx
);
5154 kvm_inject_gp(vcpu
, 0);
5158 trace_kvm_msr_read(ecx
, data
);
5160 /* FIXME: handling of bits 32:63 of rax, rdx */
5161 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5162 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5163 skip_emulated_instruction(vcpu
);
5167 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5169 struct msr_data msr
;
5170 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5171 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5172 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5176 msr
.host_initiated
= false;
5177 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5178 trace_kvm_msr_write_ex(ecx
, data
);
5179 kvm_inject_gp(vcpu
, 0);
5183 trace_kvm_msr_write(ecx
, data
);
5184 skip_emulated_instruction(vcpu
);
5188 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5190 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5194 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5196 u32 cpu_based_vm_exec_control
;
5198 /* clear pending irq */
5199 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5200 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5201 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5203 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5205 ++vcpu
->stat
.irq_window_exits
;
5208 * If the user space waits to inject interrupts, exit as soon as
5211 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5212 vcpu
->run
->request_interrupt_window
&&
5213 !kvm_cpu_has_interrupt(vcpu
)) {
5214 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5220 static int handle_halt(struct kvm_vcpu
*vcpu
)
5222 skip_emulated_instruction(vcpu
);
5223 return kvm_emulate_halt(vcpu
);
5226 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5228 skip_emulated_instruction(vcpu
);
5229 kvm_emulate_hypercall(vcpu
);
5233 static int handle_invd(struct kvm_vcpu
*vcpu
)
5235 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5238 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5240 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5242 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5243 skip_emulated_instruction(vcpu
);
5247 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5251 err
= kvm_rdpmc(vcpu
);
5252 kvm_complete_insn_gp(vcpu
, err
);
5257 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5259 skip_emulated_instruction(vcpu
);
5260 kvm_emulate_wbinvd(vcpu
);
5264 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5266 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5267 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5269 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5270 skip_emulated_instruction(vcpu
);
5274 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5276 if (likely(fasteoi
)) {
5277 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5278 int access_type
, offset
;
5280 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5281 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5283 * Sane guest uses MOV to write EOI, with written value
5284 * not cared. So make a short-circuit here by avoiding
5285 * heavy instruction emulation.
5287 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5288 (offset
== APIC_EOI
)) {
5289 kvm_lapic_set_eoi(vcpu
);
5290 skip_emulated_instruction(vcpu
);
5294 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5297 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5299 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5300 int vector
= exit_qualification
& 0xff;
5302 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5303 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5307 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5309 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5310 u32 offset
= exit_qualification
& 0xfff;
5312 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5313 kvm_apic_write_nodecode(vcpu
, offset
);
5317 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5319 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5320 unsigned long exit_qualification
;
5321 bool has_error_code
= false;
5324 int reason
, type
, idt_v
, idt_index
;
5326 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5327 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5328 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5330 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5332 reason
= (u32
)exit_qualification
>> 30;
5333 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5335 case INTR_TYPE_NMI_INTR
:
5336 vcpu
->arch
.nmi_injected
= false;
5337 vmx_set_nmi_mask(vcpu
, true);
5339 case INTR_TYPE_EXT_INTR
:
5340 case INTR_TYPE_SOFT_INTR
:
5341 kvm_clear_interrupt_queue(vcpu
);
5343 case INTR_TYPE_HARD_EXCEPTION
:
5344 if (vmx
->idt_vectoring_info
&
5345 VECTORING_INFO_DELIVER_CODE_MASK
) {
5346 has_error_code
= true;
5348 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5351 case INTR_TYPE_SOFT_EXCEPTION
:
5352 kvm_clear_exception_queue(vcpu
);
5358 tss_selector
= exit_qualification
;
5360 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5361 type
!= INTR_TYPE_EXT_INTR
&&
5362 type
!= INTR_TYPE_NMI_INTR
))
5363 skip_emulated_instruction(vcpu
);
5365 if (kvm_task_switch(vcpu
, tss_selector
,
5366 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5367 has_error_code
, error_code
) == EMULATE_FAIL
) {
5368 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5369 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5370 vcpu
->run
->internal
.ndata
= 0;
5374 /* clear all local breakpoint enable flags */
5375 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5378 * TODO: What about debug traps on tss switch?
5379 * Are we supposed to inject them and update dr6?
5385 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5387 unsigned long exit_qualification
;
5392 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5394 gla_validity
= (exit_qualification
>> 7) & 0x3;
5395 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5396 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5397 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5398 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5399 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5400 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5401 (long unsigned int)exit_qualification
);
5402 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5403 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5408 * EPT violation happened while executing iret from NMI,
5409 * "blocked by NMI" bit has to be set before next VM entry.
5410 * There are errata that may cause this bit to not be set:
5413 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5414 cpu_has_virtual_nmis() &&
5415 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5416 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5418 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5419 trace_kvm_page_fault(gpa
, exit_qualification
);
5421 /* It is a write fault? */
5422 error_code
= exit_qualification
& (1U << 1);
5423 /* It is a fetch fault? */
5424 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5425 /* ept page table is present? */
5426 error_code
|= (exit_qualification
>> 3) & 0x1;
5428 vcpu
->arch
.exit_qualification
= exit_qualification
;
5430 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5433 static u64
ept_rsvd_mask(u64 spte
, int level
)
5438 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5439 mask
|= (1ULL << i
);
5442 /* bits 7:3 reserved */
5444 else if (level
== 2) {
5445 if (spte
& (1ULL << 7))
5446 /* 2MB ref, bits 20:12 reserved */
5449 /* bits 6:3 reserved */
5456 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5459 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5461 /* 010b (write-only) */
5462 WARN_ON((spte
& 0x7) == 0x2);
5464 /* 110b (write/execute) */
5465 WARN_ON((spte
& 0x7) == 0x6);
5467 /* 100b (execute-only) and value not supported by logical processor */
5468 if (!cpu_has_vmx_ept_execute_only())
5469 WARN_ON((spte
& 0x7) == 0x4);
5473 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5475 if (rsvd_bits
!= 0) {
5476 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5477 __func__
, rsvd_bits
);
5481 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5482 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5484 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5485 ept_mem_type
== 7) {
5486 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5487 __func__
, ept_mem_type
);
5494 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5497 int nr_sptes
, i
, ret
;
5500 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5502 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5503 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5504 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5507 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5508 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5510 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5513 /* It is the real ept misconfig */
5514 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5515 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5517 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5519 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5520 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5522 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5523 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5528 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5530 u32 cpu_based_vm_exec_control
;
5532 /* clear pending NMI */
5533 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5534 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5535 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5536 ++vcpu
->stat
.nmi_window_exits
;
5537 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5542 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5544 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5545 enum emulation_result err
= EMULATE_DONE
;
5548 bool intr_window_requested
;
5549 unsigned count
= 130;
5551 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5552 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5554 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5555 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5556 return handle_interrupt_window(&vmx
->vcpu
);
5558 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5561 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5563 if (err
== EMULATE_USER_EXIT
) {
5564 ++vcpu
->stat
.mmio_exits
;
5569 if (err
!= EMULATE_DONE
) {
5570 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5571 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5572 vcpu
->run
->internal
.ndata
= 0;
5576 if (vcpu
->arch
.halt_request
) {
5577 vcpu
->arch
.halt_request
= 0;
5578 ret
= kvm_emulate_halt(vcpu
);
5582 if (signal_pending(current
))
5588 vmx
->emulation_required
= emulation_required(vcpu
);
5594 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5595 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5597 static int handle_pause(struct kvm_vcpu
*vcpu
)
5599 skip_emulated_instruction(vcpu
);
5600 kvm_vcpu_on_spin(vcpu
);
5605 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5607 kvm_queue_exception(vcpu
, UD_VECTOR
);
5612 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5613 * We could reuse a single VMCS for all the L2 guests, but we also want the
5614 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5615 * allows keeping them loaded on the processor, and in the future will allow
5616 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5617 * every entry if they never change.
5618 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5619 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5621 * The following functions allocate and free a vmcs02 in this pool.
5624 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5625 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5627 struct vmcs02_list
*item
;
5628 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5629 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5630 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5631 return &item
->vmcs02
;
5634 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5635 /* Recycle the least recently used VMCS. */
5636 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5637 struct vmcs02_list
, list
);
5638 item
->vmptr
= vmx
->nested
.current_vmptr
;
5639 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5640 return &item
->vmcs02
;
5643 /* Create a new VMCS */
5644 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5647 item
->vmcs02
.vmcs
= alloc_vmcs();
5648 if (!item
->vmcs02
.vmcs
) {
5652 loaded_vmcs_init(&item
->vmcs02
);
5653 item
->vmptr
= vmx
->nested
.current_vmptr
;
5654 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5655 vmx
->nested
.vmcs02_num
++;
5656 return &item
->vmcs02
;
5659 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5660 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5662 struct vmcs02_list
*item
;
5663 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5664 if (item
->vmptr
== vmptr
) {
5665 free_loaded_vmcs(&item
->vmcs02
);
5666 list_del(&item
->list
);
5668 vmx
->nested
.vmcs02_num
--;
5674 * Free all VMCSs saved for this vcpu, except the one pointed by
5675 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5676 * currently used, if running L2), and vmcs01 when running L2.
5678 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5680 struct vmcs02_list
*item
, *n
;
5681 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5682 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5683 free_loaded_vmcs(&item
->vmcs02
);
5684 list_del(&item
->list
);
5687 vmx
->nested
.vmcs02_num
= 0;
5689 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5690 free_loaded_vmcs(&vmx
->vmcs01
);
5694 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5695 * set the success or error code of an emulated VMX instruction, as specified
5696 * by Vol 2B, VMX Instruction Reference, "Conventions".
5698 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5700 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5701 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5702 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5705 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5707 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5708 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5709 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5713 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5714 u32 vm_instruction_error
)
5716 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5718 * failValid writes the error number to the current VMCS, which
5719 * can't be done there isn't a current VMCS.
5721 nested_vmx_failInvalid(vcpu
);
5724 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5725 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5726 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5728 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5730 * We don't need to force a shadow sync because
5731 * VM_INSTRUCTION_ERROR is not shadowed
5736 * Emulate the VMXON instruction.
5737 * Currently, we just remember that VMX is active, and do not save or even
5738 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5739 * do not currently need to store anything in that guest-allocated memory
5740 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5741 * argument is different from the VMXON pointer (which the spec says they do).
5743 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5745 struct kvm_segment cs
;
5746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5747 struct vmcs
*shadow_vmcs
;
5748 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5749 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5751 /* The Intel VMX Instruction Reference lists a bunch of bits that
5752 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5753 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5754 * Otherwise, we should fail with #UD. We test these now:
5756 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5757 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5758 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5759 kvm_queue_exception(vcpu
, UD_VECTOR
);
5763 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5764 if (is_long_mode(vcpu
) && !cs
.l
) {
5765 kvm_queue_exception(vcpu
, UD_VECTOR
);
5769 if (vmx_get_cpl(vcpu
)) {
5770 kvm_inject_gp(vcpu
, 0);
5773 if (vmx
->nested
.vmxon
) {
5774 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5775 skip_emulated_instruction(vcpu
);
5779 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5780 != VMXON_NEEDED_FEATURES
) {
5781 kvm_inject_gp(vcpu
, 0);
5785 if (enable_shadow_vmcs
) {
5786 shadow_vmcs
= alloc_vmcs();
5789 /* mark vmcs as shadow */
5790 shadow_vmcs
->revision_id
|= (1u << 31);
5791 /* init shadow vmcs */
5792 vmcs_clear(shadow_vmcs
);
5793 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5796 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5797 vmx
->nested
.vmcs02_num
= 0;
5799 vmx
->nested
.vmxon
= true;
5801 skip_emulated_instruction(vcpu
);
5802 nested_vmx_succeed(vcpu
);
5807 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5808 * for running VMX instructions (except VMXON, whose prerequisites are
5809 * slightly different). It also specifies what exception to inject otherwise.
5811 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5813 struct kvm_segment cs
;
5814 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5816 if (!vmx
->nested
.vmxon
) {
5817 kvm_queue_exception(vcpu
, UD_VECTOR
);
5821 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5822 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5823 (is_long_mode(vcpu
) && !cs
.l
)) {
5824 kvm_queue_exception(vcpu
, UD_VECTOR
);
5828 if (vmx_get_cpl(vcpu
)) {
5829 kvm_inject_gp(vcpu
, 0);
5836 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5839 if (enable_shadow_vmcs
) {
5840 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5841 /* copy to memory all shadowed fields in case
5842 they were modified */
5843 copy_shadow_to_vmcs12(vmx
);
5844 vmx
->nested
.sync_shadow_vmcs
= false;
5845 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5846 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5847 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5848 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5851 kunmap(vmx
->nested
.current_vmcs12_page
);
5852 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5856 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5857 * just stops using VMX.
5859 static void free_nested(struct vcpu_vmx
*vmx
)
5861 if (!vmx
->nested
.vmxon
)
5863 vmx
->nested
.vmxon
= false;
5864 if (vmx
->nested
.current_vmptr
!= -1ull) {
5865 nested_release_vmcs12(vmx
);
5866 vmx
->nested
.current_vmptr
= -1ull;
5867 vmx
->nested
.current_vmcs12
= NULL
;
5869 if (enable_shadow_vmcs
)
5870 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5871 /* Unpin physical memory we referred to in current vmcs02 */
5872 if (vmx
->nested
.apic_access_page
) {
5873 nested_release_page(vmx
->nested
.apic_access_page
);
5874 vmx
->nested
.apic_access_page
= 0;
5877 nested_free_all_saved_vmcss(vmx
);
5880 /* Emulate the VMXOFF instruction */
5881 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5883 if (!nested_vmx_check_permission(vcpu
))
5885 free_nested(to_vmx(vcpu
));
5886 skip_emulated_instruction(vcpu
);
5887 nested_vmx_succeed(vcpu
);
5892 * Decode the memory-address operand of a vmx instruction, as recorded on an
5893 * exit caused by such an instruction (run by a guest hypervisor).
5894 * On success, returns 0. When the operand is invalid, returns 1 and throws
5897 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5898 unsigned long exit_qualification
,
5899 u32 vmx_instruction_info
, gva_t
*ret
)
5902 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5903 * Execution", on an exit, vmx_instruction_info holds most of the
5904 * addressing components of the operand. Only the displacement part
5905 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5906 * For how an actual address is calculated from all these components,
5907 * refer to Vol. 1, "Operand Addressing".
5909 int scaling
= vmx_instruction_info
& 3;
5910 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5911 bool is_reg
= vmx_instruction_info
& (1u << 10);
5912 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5913 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5914 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5915 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5916 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5919 kvm_queue_exception(vcpu
, UD_VECTOR
);
5923 /* Addr = segment_base + offset */
5924 /* offset = base + [index * scale] + displacement */
5925 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5927 *ret
+= kvm_register_read(vcpu
, base_reg
);
5929 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5930 *ret
+= exit_qualification
; /* holds the displacement */
5932 if (addr_size
== 1) /* 32 bit */
5936 * TODO: throw #GP (and return 1) in various cases that the VM*
5937 * instructions require it - e.g., offset beyond segment limit,
5938 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5939 * address, and so on. Currently these are not checked.
5944 /* Emulate the VMCLEAR instruction */
5945 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5950 struct vmcs12
*vmcs12
;
5952 struct x86_exception e
;
5954 if (!nested_vmx_check_permission(vcpu
))
5957 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5958 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5961 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5962 sizeof(vmptr
), &e
)) {
5963 kvm_inject_page_fault(vcpu
, &e
);
5967 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5968 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5969 skip_emulated_instruction(vcpu
);
5973 if (vmptr
== vmx
->nested
.current_vmptr
) {
5974 nested_release_vmcs12(vmx
);
5975 vmx
->nested
.current_vmptr
= -1ull;
5976 vmx
->nested
.current_vmcs12
= NULL
;
5979 page
= nested_get_page(vcpu
, vmptr
);
5982 * For accurate processor emulation, VMCLEAR beyond available
5983 * physical memory should do nothing at all. However, it is
5984 * possible that a nested vmx bug, not a guest hypervisor bug,
5985 * resulted in this case, so let's shut down before doing any
5988 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5991 vmcs12
= kmap(page
);
5992 vmcs12
->launch_state
= 0;
5994 nested_release_page(page
);
5996 nested_free_vmcs02(vmx
, vmptr
);
5998 skip_emulated_instruction(vcpu
);
5999 nested_vmx_succeed(vcpu
);
6003 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6005 /* Emulate the VMLAUNCH instruction */
6006 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6008 return nested_vmx_run(vcpu
, true);
6011 /* Emulate the VMRESUME instruction */
6012 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6015 return nested_vmx_run(vcpu
, false);
6018 enum vmcs_field_type
{
6019 VMCS_FIELD_TYPE_U16
= 0,
6020 VMCS_FIELD_TYPE_U64
= 1,
6021 VMCS_FIELD_TYPE_U32
= 2,
6022 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6025 static inline int vmcs_field_type(unsigned long field
)
6027 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6028 return VMCS_FIELD_TYPE_U32
;
6029 return (field
>> 13) & 0x3 ;
6032 static inline int vmcs_field_readonly(unsigned long field
)
6034 return (((field
>> 10) & 0x3) == 1);
6038 * Read a vmcs12 field. Since these can have varying lengths and we return
6039 * one type, we chose the biggest type (u64) and zero-extend the return value
6040 * to that size. Note that the caller, handle_vmread, might need to use only
6041 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6042 * 64-bit fields are to be returned).
6044 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6045 unsigned long field
, u64
*ret
)
6047 short offset
= vmcs_field_to_offset(field
);
6053 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6055 switch (vmcs_field_type(field
)) {
6056 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6057 *ret
= *((natural_width
*)p
);
6059 case VMCS_FIELD_TYPE_U16
:
6062 case VMCS_FIELD_TYPE_U32
:
6065 case VMCS_FIELD_TYPE_U64
:
6069 return 0; /* can never happen. */
6074 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6075 unsigned long field
, u64 field_value
){
6076 short offset
= vmcs_field_to_offset(field
);
6077 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6081 switch (vmcs_field_type(field
)) {
6082 case VMCS_FIELD_TYPE_U16
:
6083 *(u16
*)p
= field_value
;
6085 case VMCS_FIELD_TYPE_U32
:
6086 *(u32
*)p
= field_value
;
6088 case VMCS_FIELD_TYPE_U64
:
6089 *(u64
*)p
= field_value
;
6091 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6092 *(natural_width
*)p
= field_value
;
6095 return false; /* can never happen. */
6100 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6103 unsigned long field
;
6105 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6106 const unsigned long *fields
= shadow_read_write_fields
;
6107 const int num_fields
= max_shadow_read_write_fields
;
6109 vmcs_load(shadow_vmcs
);
6111 for (i
= 0; i
< num_fields
; i
++) {
6113 switch (vmcs_field_type(field
)) {
6114 case VMCS_FIELD_TYPE_U16
:
6115 field_value
= vmcs_read16(field
);
6117 case VMCS_FIELD_TYPE_U32
:
6118 field_value
= vmcs_read32(field
);
6120 case VMCS_FIELD_TYPE_U64
:
6121 field_value
= vmcs_read64(field
);
6123 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6124 field_value
= vmcs_readl(field
);
6127 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6130 vmcs_clear(shadow_vmcs
);
6131 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6134 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6136 const unsigned long *fields
[] = {
6137 shadow_read_write_fields
,
6138 shadow_read_only_fields
6140 const int max_fields
[] = {
6141 max_shadow_read_write_fields
,
6142 max_shadow_read_only_fields
6145 unsigned long field
;
6146 u64 field_value
= 0;
6147 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6149 vmcs_load(shadow_vmcs
);
6151 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6152 for (i
= 0; i
< max_fields
[q
]; i
++) {
6153 field
= fields
[q
][i
];
6154 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6156 switch (vmcs_field_type(field
)) {
6157 case VMCS_FIELD_TYPE_U16
:
6158 vmcs_write16(field
, (u16
)field_value
);
6160 case VMCS_FIELD_TYPE_U32
:
6161 vmcs_write32(field
, (u32
)field_value
);
6163 case VMCS_FIELD_TYPE_U64
:
6164 vmcs_write64(field
, (u64
)field_value
);
6166 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6167 vmcs_writel(field
, (long)field_value
);
6173 vmcs_clear(shadow_vmcs
);
6174 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6178 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6179 * used before) all generate the same failure when it is missing.
6181 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6183 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6184 if (vmx
->nested
.current_vmptr
== -1ull) {
6185 nested_vmx_failInvalid(vcpu
);
6186 skip_emulated_instruction(vcpu
);
6192 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6194 unsigned long field
;
6196 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6197 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6200 if (!nested_vmx_check_permission(vcpu
) ||
6201 !nested_vmx_check_vmcs12(vcpu
))
6204 /* Decode instruction info and find the field to read */
6205 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6206 /* Read the field, zero-extended to a u64 field_value */
6207 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6208 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6209 skip_emulated_instruction(vcpu
);
6213 * Now copy part of this value to register or memory, as requested.
6214 * Note that the number of bits actually copied is 32 or 64 depending
6215 * on the guest's mode (32 or 64 bit), not on the given field's length.
6217 if (vmx_instruction_info
& (1u << 10)) {
6218 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6221 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6222 vmx_instruction_info
, &gva
))
6224 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6225 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6226 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6229 nested_vmx_succeed(vcpu
);
6230 skip_emulated_instruction(vcpu
);
6235 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6237 unsigned long field
;
6239 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6240 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6241 /* The value to write might be 32 or 64 bits, depending on L1's long
6242 * mode, and eventually we need to write that into a field of several
6243 * possible lengths. The code below first zero-extends the value to 64
6244 * bit (field_value), and then copies only the approriate number of
6245 * bits into the vmcs12 field.
6247 u64 field_value
= 0;
6248 struct x86_exception e
;
6250 if (!nested_vmx_check_permission(vcpu
) ||
6251 !nested_vmx_check_vmcs12(vcpu
))
6254 if (vmx_instruction_info
& (1u << 10))
6255 field_value
= kvm_register_read(vcpu
,
6256 (((vmx_instruction_info
) >> 3) & 0xf));
6258 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6259 vmx_instruction_info
, &gva
))
6261 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6262 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6263 kvm_inject_page_fault(vcpu
, &e
);
6269 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6270 if (vmcs_field_readonly(field
)) {
6271 nested_vmx_failValid(vcpu
,
6272 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6273 skip_emulated_instruction(vcpu
);
6277 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6278 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6279 skip_emulated_instruction(vcpu
);
6283 nested_vmx_succeed(vcpu
);
6284 skip_emulated_instruction(vcpu
);
6288 /* Emulate the VMPTRLD instruction */
6289 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6291 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6294 struct x86_exception e
;
6297 if (!nested_vmx_check_permission(vcpu
))
6300 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6301 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6304 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6305 sizeof(vmptr
), &e
)) {
6306 kvm_inject_page_fault(vcpu
, &e
);
6310 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6311 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6312 skip_emulated_instruction(vcpu
);
6316 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6317 struct vmcs12
*new_vmcs12
;
6319 page
= nested_get_page(vcpu
, vmptr
);
6321 nested_vmx_failInvalid(vcpu
);
6322 skip_emulated_instruction(vcpu
);
6325 new_vmcs12
= kmap(page
);
6326 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6328 nested_release_page_clean(page
);
6329 nested_vmx_failValid(vcpu
,
6330 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6331 skip_emulated_instruction(vcpu
);
6334 if (vmx
->nested
.current_vmptr
!= -1ull)
6335 nested_release_vmcs12(vmx
);
6337 vmx
->nested
.current_vmptr
= vmptr
;
6338 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6339 vmx
->nested
.current_vmcs12_page
= page
;
6340 if (enable_shadow_vmcs
) {
6341 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6342 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6344 vmcs_write64(VMCS_LINK_POINTER
,
6345 __pa(vmx
->nested
.current_shadow_vmcs
));
6346 vmx
->nested
.sync_shadow_vmcs
= true;
6350 nested_vmx_succeed(vcpu
);
6351 skip_emulated_instruction(vcpu
);
6355 /* Emulate the VMPTRST instruction */
6356 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6358 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6359 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6361 struct x86_exception e
;
6363 if (!nested_vmx_check_permission(vcpu
))
6366 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6367 vmx_instruction_info
, &vmcs_gva
))
6369 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6370 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6371 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6373 kvm_inject_page_fault(vcpu
, &e
);
6376 nested_vmx_succeed(vcpu
);
6377 skip_emulated_instruction(vcpu
);
6381 /* Emulate the INVEPT instruction */
6382 static int handle_invept(struct kvm_vcpu
*vcpu
)
6384 u32 vmx_instruction_info
, types
;
6387 struct x86_exception e
;
6391 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6393 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6394 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6395 kvm_queue_exception(vcpu
, UD_VECTOR
);
6399 if (!nested_vmx_check_permission(vcpu
))
6402 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6403 kvm_queue_exception(vcpu
, UD_VECTOR
);
6407 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6408 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6410 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6412 if (!(types
& (1UL << type
))) {
6413 nested_vmx_failValid(vcpu
,
6414 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6418 /* According to the Intel VMX instruction reference, the memory
6419 * operand is read even if it isn't needed (e.g., for type==global)
6421 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6422 vmx_instruction_info
, &gva
))
6424 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6425 sizeof(operand
), &e
)) {
6426 kvm_inject_page_fault(vcpu
, &e
);
6431 case VMX_EPT_EXTENT_CONTEXT
:
6432 if ((operand
.eptp
& eptp_mask
) !=
6433 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6435 case VMX_EPT_EXTENT_GLOBAL
:
6436 kvm_mmu_sync_roots(vcpu
);
6437 kvm_mmu_flush_tlb(vcpu
);
6438 nested_vmx_succeed(vcpu
);
6445 skip_emulated_instruction(vcpu
);
6450 * The exit handlers return 1 if the exit was handled fully and guest execution
6451 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6452 * to be done to userspace and return 0.
6454 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6455 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6456 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6457 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6458 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6459 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6460 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6461 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6462 [EXIT_REASON_CPUID
] = handle_cpuid
,
6463 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6464 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6465 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6466 [EXIT_REASON_HLT
] = handle_halt
,
6467 [EXIT_REASON_INVD
] = handle_invd
,
6468 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6469 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6470 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6471 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6472 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6473 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6474 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6475 [EXIT_REASON_VMREAD
] = handle_vmread
,
6476 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6477 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6478 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6479 [EXIT_REASON_VMON
] = handle_vmon
,
6480 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6481 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6482 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6483 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6484 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6485 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6486 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6487 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6488 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6489 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6490 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6491 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6492 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6493 [EXIT_REASON_INVEPT
] = handle_invept
,
6496 static const int kvm_vmx_max_exit_handlers
=
6497 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6499 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6500 struct vmcs12
*vmcs12
)
6502 unsigned long exit_qualification
;
6503 gpa_t bitmap
, last_bitmap
;
6508 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6509 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6511 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6513 port
= exit_qualification
>> 16;
6514 size
= (exit_qualification
& 7) + 1;
6516 last_bitmap
= (gpa_t
)-1;
6521 bitmap
= vmcs12
->io_bitmap_a
;
6522 else if (port
< 0x10000)
6523 bitmap
= vmcs12
->io_bitmap_b
;
6526 bitmap
+= (port
& 0x7fff) / 8;
6528 if (last_bitmap
!= bitmap
)
6529 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6531 if (b
& (1 << (port
& 7)))
6536 last_bitmap
= bitmap
;
6543 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6544 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6545 * disinterest in the current event (read or write a specific MSR) by using an
6546 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6548 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6549 struct vmcs12
*vmcs12
, u32 exit_reason
)
6551 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6554 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6558 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6559 * for the four combinations of read/write and low/high MSR numbers.
6560 * First we need to figure out which of the four to use:
6562 bitmap
= vmcs12
->msr_bitmap
;
6563 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6565 if (msr_index
>= 0xc0000000) {
6566 msr_index
-= 0xc0000000;
6570 /* Then read the msr_index'th bit from this bitmap: */
6571 if (msr_index
< 1024*8) {
6573 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6575 return 1 & (b
>> (msr_index
& 7));
6577 return 1; /* let L1 handle the wrong parameter */
6581 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6582 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6583 * intercept (via guest_host_mask etc.) the current event.
6585 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6586 struct vmcs12
*vmcs12
)
6588 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6589 int cr
= exit_qualification
& 15;
6590 int reg
= (exit_qualification
>> 8) & 15;
6591 unsigned long val
= kvm_register_read(vcpu
, reg
);
6593 switch ((exit_qualification
>> 4) & 3) {
6594 case 0: /* mov to cr */
6597 if (vmcs12
->cr0_guest_host_mask
&
6598 (val
^ vmcs12
->cr0_read_shadow
))
6602 if ((vmcs12
->cr3_target_count
>= 1 &&
6603 vmcs12
->cr3_target_value0
== val
) ||
6604 (vmcs12
->cr3_target_count
>= 2 &&
6605 vmcs12
->cr3_target_value1
== val
) ||
6606 (vmcs12
->cr3_target_count
>= 3 &&
6607 vmcs12
->cr3_target_value2
== val
) ||
6608 (vmcs12
->cr3_target_count
>= 4 &&
6609 vmcs12
->cr3_target_value3
== val
))
6611 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6615 if (vmcs12
->cr4_guest_host_mask
&
6616 (vmcs12
->cr4_read_shadow
^ val
))
6620 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6626 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6627 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6630 case 1: /* mov from cr */
6633 if (vmcs12
->cpu_based_vm_exec_control
&
6634 CPU_BASED_CR3_STORE_EXITING
)
6638 if (vmcs12
->cpu_based_vm_exec_control
&
6639 CPU_BASED_CR8_STORE_EXITING
)
6646 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6647 * cr0. Other attempted changes are ignored, with no exit.
6649 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6650 (val
^ vmcs12
->cr0_read_shadow
))
6652 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6653 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6662 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6663 * should handle it ourselves in L0 (and then continue L2). Only call this
6664 * when in is_guest_mode (L2).
6666 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6668 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6669 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6670 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6671 u32 exit_reason
= vmx
->exit_reason
;
6673 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6674 vmcs_readl(EXIT_QUALIFICATION
),
6675 vmx
->idt_vectoring_info
,
6677 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6680 if (vmx
->nested
.nested_run_pending
)
6683 if (unlikely(vmx
->fail
)) {
6684 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6685 vmcs_read32(VM_INSTRUCTION_ERROR
));
6689 switch (exit_reason
) {
6690 case EXIT_REASON_EXCEPTION_NMI
:
6691 if (!is_exception(intr_info
))
6693 else if (is_page_fault(intr_info
))
6695 else if (is_no_device(intr_info
) &&
6696 !(nested_read_cr0(vmcs12
) & X86_CR0_TS
))
6698 return vmcs12
->exception_bitmap
&
6699 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6700 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6702 case EXIT_REASON_TRIPLE_FAULT
:
6704 case EXIT_REASON_PENDING_INTERRUPT
:
6705 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6706 case EXIT_REASON_NMI_WINDOW
:
6707 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6708 case EXIT_REASON_TASK_SWITCH
:
6710 case EXIT_REASON_CPUID
:
6712 case EXIT_REASON_HLT
:
6713 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6714 case EXIT_REASON_INVD
:
6716 case EXIT_REASON_INVLPG
:
6717 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6718 case EXIT_REASON_RDPMC
:
6719 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6720 case EXIT_REASON_RDTSC
:
6721 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6722 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6723 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6724 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6725 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6726 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6727 case EXIT_REASON_INVEPT
:
6729 * VMX instructions trap unconditionally. This allows L1 to
6730 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6733 case EXIT_REASON_CR_ACCESS
:
6734 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6735 case EXIT_REASON_DR_ACCESS
:
6736 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6737 case EXIT_REASON_IO_INSTRUCTION
:
6738 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6739 case EXIT_REASON_MSR_READ
:
6740 case EXIT_REASON_MSR_WRITE
:
6741 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6742 case EXIT_REASON_INVALID_STATE
:
6744 case EXIT_REASON_MWAIT_INSTRUCTION
:
6745 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6746 case EXIT_REASON_MONITOR_INSTRUCTION
:
6747 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6748 case EXIT_REASON_PAUSE_INSTRUCTION
:
6749 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6750 nested_cpu_has2(vmcs12
,
6751 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6752 case EXIT_REASON_MCE_DURING_VMENTRY
:
6754 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6756 case EXIT_REASON_APIC_ACCESS
:
6757 return nested_cpu_has2(vmcs12
,
6758 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6759 case EXIT_REASON_EPT_VIOLATION
:
6761 * L0 always deals with the EPT violation. If nested EPT is
6762 * used, and the nested mmu code discovers that the address is
6763 * missing in the guest EPT table (EPT12), the EPT violation
6764 * will be injected with nested_ept_inject_page_fault()
6767 case EXIT_REASON_EPT_MISCONFIG
:
6769 * L2 never uses directly L1's EPT, but rather L0's own EPT
6770 * table (shadow on EPT) or a merged EPT table that L0 built
6771 * (EPT on EPT). So any problems with the structure of the
6772 * table is L0's fault.
6775 case EXIT_REASON_PREEMPTION_TIMER
:
6776 return vmcs12
->pin_based_vm_exec_control
&
6777 PIN_BASED_VMX_PREEMPTION_TIMER
;
6778 case EXIT_REASON_WBINVD
:
6779 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6780 case EXIT_REASON_XSETBV
:
6787 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6789 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6790 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6793 static void nested_adjust_preemption_timer(struct kvm_vcpu
*vcpu
)
6796 u32 preempt_val_l1
, preempt_val_l2
, preempt_scale
;
6798 if (!(get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
6799 PIN_BASED_VMX_PREEMPTION_TIMER
))
6801 preempt_scale
= native_read_msr(MSR_IA32_VMX_MISC
) &
6802 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE
;
6803 preempt_val_l2
= vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
6804 delta_tsc_l1
= vmx_read_l1_tsc(vcpu
, native_read_tsc())
6805 - vcpu
->arch
.last_guest_tsc
;
6806 preempt_val_l1
= delta_tsc_l1
>> preempt_scale
;
6807 if (preempt_val_l2
<= preempt_val_l1
)
6810 preempt_val_l2
-= preempt_val_l1
;
6811 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, preempt_val_l2
);
6815 * The guest has exited. See if we can fix it or if we need userspace
6818 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6820 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6821 u32 exit_reason
= vmx
->exit_reason
;
6822 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6824 /* If guest state is invalid, start emulating */
6825 if (vmx
->emulation_required
)
6826 return handle_invalid_guest_state(vcpu
);
6828 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6829 nested_vmx_vmexit(vcpu
, exit_reason
,
6830 vmcs_read32(VM_EXIT_INTR_INFO
),
6831 vmcs_readl(EXIT_QUALIFICATION
));
6835 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6836 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6837 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6842 if (unlikely(vmx
->fail
)) {
6843 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6844 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6845 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6851 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6852 * delivery event since it indicates guest is accessing MMIO.
6853 * The vm-exit can be triggered again after return to guest that
6854 * will cause infinite loop.
6856 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6857 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6858 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6859 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6860 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6861 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6862 vcpu
->run
->internal
.ndata
= 2;
6863 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6864 vcpu
->run
->internal
.data
[1] = exit_reason
;
6868 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6869 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6870 get_vmcs12(vcpu
))))) {
6871 if (vmx_interrupt_allowed(vcpu
)) {
6872 vmx
->soft_vnmi_blocked
= 0;
6873 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6874 vcpu
->arch
.nmi_pending
) {
6876 * This CPU don't support us in finding the end of an
6877 * NMI-blocked window if the guest runs with IRQs
6878 * disabled. So we pull the trigger after 1 s of
6879 * futile waiting, but inform the user about this.
6881 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6882 "state on VCPU %d after 1 s timeout\n",
6883 __func__
, vcpu
->vcpu_id
);
6884 vmx
->soft_vnmi_blocked
= 0;
6888 if (exit_reason
< kvm_vmx_max_exit_handlers
6889 && kvm_vmx_exit_handlers
[exit_reason
])
6890 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6892 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6893 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6898 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6900 if (irr
== -1 || tpr
< irr
) {
6901 vmcs_write32(TPR_THRESHOLD
, 0);
6905 vmcs_write32(TPR_THRESHOLD
, irr
);
6908 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6910 u32 sec_exec_control
;
6913 * There is not point to enable virtualize x2apic without enable
6916 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6917 !vmx_vm_has_apicv(vcpu
->kvm
))
6920 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6923 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6926 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6927 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6929 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6930 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6932 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6934 vmx_set_msr_bitmap(vcpu
);
6937 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6942 if (!vmx_vm_has_apicv(kvm
))
6948 status
= vmcs_read16(GUEST_INTR_STATUS
);
6953 vmcs_write16(GUEST_INTR_STATUS
, status
);
6957 static void vmx_set_rvi(int vector
)
6962 status
= vmcs_read16(GUEST_INTR_STATUS
);
6963 old
= (u8
)status
& 0xff;
6964 if ((u8
)vector
!= old
) {
6966 status
|= (u8
)vector
;
6967 vmcs_write16(GUEST_INTR_STATUS
, status
);
6971 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6976 vmx_set_rvi(max_irr
);
6979 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6981 if (!vmx_vm_has_apicv(vcpu
->kvm
))
6984 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6985 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6986 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6987 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6990 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6994 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6995 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6998 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6999 exit_intr_info
= vmx
->exit_intr_info
;
7001 /* Handle machine checks before interrupts are enabled */
7002 if (is_machine_check(exit_intr_info
))
7003 kvm_machine_check();
7005 /* We need to handle NMIs before interrupts are enabled */
7006 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7007 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7008 kvm_before_handle_nmi(&vmx
->vcpu
);
7010 kvm_after_handle_nmi(&vmx
->vcpu
);
7014 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7016 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7019 * If external interrupt exists, IF bit is set in rflags/eflags on the
7020 * interrupt stack frame, and interrupt will be enabled on a return
7021 * from interrupt handler.
7023 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7024 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7025 unsigned int vector
;
7026 unsigned long entry
;
7028 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7029 #ifdef CONFIG_X86_64
7033 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7034 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7035 entry
= gate_offset(*desc
);
7037 #ifdef CONFIG_X86_64
7038 "mov %%" _ASM_SP
", %[sp]\n\t"
7039 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7044 "orl $0x200, (%%" _ASM_SP
")\n\t"
7045 __ASM_SIZE(push
) " $%c[cs]\n\t"
7046 "call *%[entry]\n\t"
7048 #ifdef CONFIG_X86_64
7053 [ss
]"i"(__KERNEL_DS
),
7054 [cs
]"i"(__KERNEL_CS
)
7060 static bool vmx_mpx_supported(void)
7062 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7063 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7066 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7071 bool idtv_info_valid
;
7073 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7075 if (cpu_has_virtual_nmis()) {
7076 if (vmx
->nmi_known_unmasked
)
7079 * Can't use vmx->exit_intr_info since we're not sure what
7080 * the exit reason is.
7082 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7083 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7084 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7086 * SDM 3: 27.7.1.2 (September 2008)
7087 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7088 * a guest IRET fault.
7089 * SDM 3: 23.2.2 (September 2008)
7090 * Bit 12 is undefined in any of the following cases:
7091 * If the VM exit sets the valid bit in the IDT-vectoring
7092 * information field.
7093 * If the VM exit is due to a double fault.
7095 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7096 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7097 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7098 GUEST_INTR_STATE_NMI
);
7100 vmx
->nmi_known_unmasked
=
7101 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7102 & GUEST_INTR_STATE_NMI
);
7103 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7104 vmx
->vnmi_blocked_time
+=
7105 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7108 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7109 u32 idt_vectoring_info
,
7110 int instr_len_field
,
7111 int error_code_field
)
7115 bool idtv_info_valid
;
7117 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7119 vcpu
->arch
.nmi_injected
= false;
7120 kvm_clear_exception_queue(vcpu
);
7121 kvm_clear_interrupt_queue(vcpu
);
7123 if (!idtv_info_valid
)
7126 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7128 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7129 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7132 case INTR_TYPE_NMI_INTR
:
7133 vcpu
->arch
.nmi_injected
= true;
7135 * SDM 3: 27.7.1.2 (September 2008)
7136 * Clear bit "block by NMI" before VM entry if a NMI
7139 vmx_set_nmi_mask(vcpu
, false);
7141 case INTR_TYPE_SOFT_EXCEPTION
:
7142 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7144 case INTR_TYPE_HARD_EXCEPTION
:
7145 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7146 u32 err
= vmcs_read32(error_code_field
);
7147 kvm_requeue_exception_e(vcpu
, vector
, err
);
7149 kvm_requeue_exception(vcpu
, vector
);
7151 case INTR_TYPE_SOFT_INTR
:
7152 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7154 case INTR_TYPE_EXT_INTR
:
7155 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7162 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7164 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7165 VM_EXIT_INSTRUCTION_LEN
,
7166 IDT_VECTORING_ERROR_CODE
);
7169 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7171 __vmx_complete_interrupts(vcpu
,
7172 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7173 VM_ENTRY_INSTRUCTION_LEN
,
7174 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7176 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7179 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7182 struct perf_guest_switch_msr
*msrs
;
7184 msrs
= perf_guest_get_msrs(&nr_msrs
);
7189 for (i
= 0; i
< nr_msrs
; i
++)
7190 if (msrs
[i
].host
== msrs
[i
].guest
)
7191 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7193 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7197 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7199 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7200 unsigned long debugctlmsr
;
7202 /* Record the guest's net vcpu time for enforced NMI injections. */
7203 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7204 vmx
->entry_time
= ktime_get();
7206 /* Don't enter VMX if guest state is invalid, let the exit handler
7207 start emulation until we arrive back to a valid state */
7208 if (vmx
->emulation_required
)
7211 if (vmx
->nested
.sync_shadow_vmcs
) {
7212 copy_vmcs12_to_shadow(vmx
);
7213 vmx
->nested
.sync_shadow_vmcs
= false;
7216 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7217 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7218 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7219 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7221 /* When single-stepping over STI and MOV SS, we must clear the
7222 * corresponding interruptibility bits in the guest state. Otherwise
7223 * vmentry fails as it then expects bit 14 (BS) in pending debug
7224 * exceptions being set, but that's not correct for the guest debugging
7226 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7227 vmx_set_interrupt_shadow(vcpu
, 0);
7229 atomic_switch_perf_msrs(vmx
);
7230 debugctlmsr
= get_debugctlmsr();
7232 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
)
7233 nested_adjust_preemption_timer(vcpu
);
7234 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7236 /* Store host registers */
7237 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7238 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7239 "push %%" _ASM_CX
" \n\t"
7240 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7242 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7243 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7245 /* Reload cr2 if changed */
7246 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7247 "mov %%cr2, %%" _ASM_DX
" \n\t"
7248 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7250 "mov %%" _ASM_AX
", %%cr2 \n\t"
7252 /* Check if vmlaunch of vmresume is needed */
7253 "cmpl $0, %c[launched](%0) \n\t"
7254 /* Load guest registers. Don't clobber flags. */
7255 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7256 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7257 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7258 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7259 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7260 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7261 #ifdef CONFIG_X86_64
7262 "mov %c[r8](%0), %%r8 \n\t"
7263 "mov %c[r9](%0), %%r9 \n\t"
7264 "mov %c[r10](%0), %%r10 \n\t"
7265 "mov %c[r11](%0), %%r11 \n\t"
7266 "mov %c[r12](%0), %%r12 \n\t"
7267 "mov %c[r13](%0), %%r13 \n\t"
7268 "mov %c[r14](%0), %%r14 \n\t"
7269 "mov %c[r15](%0), %%r15 \n\t"
7271 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7273 /* Enter guest mode */
7275 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7277 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7279 /* Save guest registers, load host registers, keep flags */
7280 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7282 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7283 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7284 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7285 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7286 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7287 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7288 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7289 #ifdef CONFIG_X86_64
7290 "mov %%r8, %c[r8](%0) \n\t"
7291 "mov %%r9, %c[r9](%0) \n\t"
7292 "mov %%r10, %c[r10](%0) \n\t"
7293 "mov %%r11, %c[r11](%0) \n\t"
7294 "mov %%r12, %c[r12](%0) \n\t"
7295 "mov %%r13, %c[r13](%0) \n\t"
7296 "mov %%r14, %c[r14](%0) \n\t"
7297 "mov %%r15, %c[r15](%0) \n\t"
7299 "mov %%cr2, %%" _ASM_AX
" \n\t"
7300 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7302 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7303 "setbe %c[fail](%0) \n\t"
7304 ".pushsection .rodata \n\t"
7305 ".global vmx_return \n\t"
7306 "vmx_return: " _ASM_PTR
" 2b \n\t"
7308 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7309 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7310 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7311 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7312 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7313 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7314 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7315 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7316 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7317 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7318 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7319 #ifdef CONFIG_X86_64
7320 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7321 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7322 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7323 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7324 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7325 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7326 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7327 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7329 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7330 [wordsize
]"i"(sizeof(ulong
))
7332 #ifdef CONFIG_X86_64
7333 , "rax", "rbx", "rdi", "rsi"
7334 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7336 , "eax", "ebx", "edi", "esi"
7340 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7342 update_debugctlmsr(debugctlmsr
);
7344 #ifndef CONFIG_X86_64
7346 * The sysexit path does not restore ds/es, so we must set them to
7347 * a reasonable value ourselves.
7349 * We can't defer this to vmx_load_host_state() since that function
7350 * may be executed in interrupt context, which saves and restore segments
7351 * around it, nullifying its effect.
7353 loadsegment(ds
, __USER_DS
);
7354 loadsegment(es
, __USER_DS
);
7357 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7358 | (1 << VCPU_EXREG_RFLAGS
)
7359 | (1 << VCPU_EXREG_CPL
)
7360 | (1 << VCPU_EXREG_PDPTR
)
7361 | (1 << VCPU_EXREG_SEGMENTS
)
7362 | (1 << VCPU_EXREG_CR3
));
7363 vcpu
->arch
.regs_dirty
= 0;
7365 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7367 vmx
->loaded_vmcs
->launched
= 1;
7369 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7370 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7373 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7374 * we did not inject a still-pending event to L1 now because of
7375 * nested_run_pending, we need to re-enable this bit.
7377 if (vmx
->nested
.nested_run_pending
)
7378 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7380 vmx
->nested
.nested_run_pending
= 0;
7382 vmx_complete_atomic_exit(vmx
);
7383 vmx_recover_nmi_blocking(vmx
);
7384 vmx_complete_interrupts(vmx
);
7387 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7389 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7392 free_loaded_vmcs(vmx
->loaded_vmcs
);
7394 kfree(vmx
->guest_msrs
);
7395 kvm_vcpu_uninit(vcpu
);
7396 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7399 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7402 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7406 return ERR_PTR(-ENOMEM
);
7410 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7414 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7416 if (!vmx
->guest_msrs
) {
7420 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7421 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7422 if (!vmx
->loaded_vmcs
->vmcs
)
7425 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7426 loaded_vmcs_init(vmx
->loaded_vmcs
);
7431 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7432 vmx
->vcpu
.cpu
= cpu
;
7433 err
= vmx_vcpu_setup(vmx
);
7434 vmx_vcpu_put(&vmx
->vcpu
);
7438 if (vm_need_virtualize_apic_accesses(kvm
)) {
7439 err
= alloc_apic_access_page(kvm
);
7445 if (!kvm
->arch
.ept_identity_map_addr
)
7446 kvm
->arch
.ept_identity_map_addr
=
7447 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7449 if (alloc_identity_pagetable(kvm
) != 0)
7451 if (!init_rmode_identity_map(kvm
))
7455 vmx
->nested
.current_vmptr
= -1ull;
7456 vmx
->nested
.current_vmcs12
= NULL
;
7461 free_loaded_vmcs(vmx
->loaded_vmcs
);
7463 kfree(vmx
->guest_msrs
);
7465 kvm_vcpu_uninit(&vmx
->vcpu
);
7468 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7469 return ERR_PTR(err
);
7472 static void __init
vmx_check_processor_compat(void *rtn
)
7474 struct vmcs_config vmcs_conf
;
7477 if (setup_vmcs_config(&vmcs_conf
) < 0)
7479 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7480 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7481 smp_processor_id());
7486 static int get_ept_level(void)
7488 return VMX_EPT_DEFAULT_GAW
+ 1;
7491 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7495 /* For VT-d and EPT combination
7496 * 1. MMIO: always map as UC
7498 * a. VT-d without snooping control feature: can't guarantee the
7499 * result, try to trust guest.
7500 * b. VT-d with snooping control feature: snooping control feature of
7501 * VT-d engine can guarantee the cache correctness. Just set it
7502 * to WB to keep consistent with host. So the same as item 3.
7503 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7504 * consistent with host MTRR
7507 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7508 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7509 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7510 VMX_EPT_MT_EPTE_SHIFT
;
7512 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7518 static int vmx_get_lpage_level(void)
7520 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7521 return PT_DIRECTORY_LEVEL
;
7523 /* For shadow and EPT supported 1GB page */
7524 return PT_PDPE_LEVEL
;
7527 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7529 struct kvm_cpuid_entry2
*best
;
7530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7533 vmx
->rdtscp_enabled
= false;
7534 if (vmx_rdtscp_supported()) {
7535 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7536 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7537 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7538 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7539 vmx
->rdtscp_enabled
= true;
7541 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7542 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7548 /* Exposing INVPCID only when PCID is exposed */
7549 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7550 if (vmx_invpcid_supported() &&
7551 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7552 guest_cpuid_has_pcid(vcpu
)) {
7553 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7554 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7555 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7558 if (cpu_has_secondary_exec_ctrls()) {
7559 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7560 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7561 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7565 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7569 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7571 if (func
== 1 && nested
)
7572 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7575 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7576 struct x86_exception
*fault
)
7578 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7581 if (fault
->error_code
& PFERR_RSVD_MASK
)
7582 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7584 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7585 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7586 vmcs12
->guest_physical_address
= fault
->address
;
7589 /* Callbacks for nested_ept_init_mmu_context: */
7591 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7593 /* return the page table to be shadowed - in our case, EPT12 */
7594 return get_vmcs12(vcpu
)->ept_pointer
;
7597 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7599 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7600 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7602 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7603 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7604 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7606 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7609 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7611 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7614 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7615 struct x86_exception
*fault
)
7617 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7619 WARN_ON(!is_guest_mode(vcpu
));
7621 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7622 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7623 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7624 vmcs_read32(VM_EXIT_INTR_INFO
),
7625 vmcs_readl(EXIT_QUALIFICATION
));
7627 kvm_inject_page_fault(vcpu
, fault
);
7631 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7632 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7633 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7634 * guest in a way that will both be appropriate to L1's requests, and our
7635 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7636 * function also has additional necessary side-effects, like setting various
7637 * vcpu->arch fields.
7639 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7641 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7645 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7646 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7647 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7648 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7649 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7650 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7651 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7652 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7653 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7654 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7655 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7656 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7657 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7658 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7659 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7660 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7661 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7662 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7663 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7664 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7665 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7666 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7667 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7668 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7669 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7670 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7671 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7672 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7673 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7674 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7675 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7676 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7677 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7678 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7679 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7680 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7682 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7684 vmcs12
->vm_entry_intr_info_field
);
7685 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7686 vmcs12
->vm_entry_exception_error_code
);
7687 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7688 vmcs12
->vm_entry_instruction_len
);
7689 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7690 vmcs12
->guest_interruptibility_info
);
7691 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7692 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7693 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7694 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7695 vmcs12
->guest_pending_dbg_exceptions
);
7696 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7697 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7699 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7701 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7702 (vmcs_config
.pin_based_exec_ctrl
|
7703 vmcs12
->pin_based_vm_exec_control
));
7705 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7706 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7707 vmcs12
->vmx_preemption_timer_value
);
7710 * Whether page-faults are trapped is determined by a combination of
7711 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7712 * If enable_ept, L0 doesn't care about page faults and we should
7713 * set all of these to L1's desires. However, if !enable_ept, L0 does
7714 * care about (at least some) page faults, and because it is not easy
7715 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7716 * to exit on each and every L2 page fault. This is done by setting
7717 * MASK=MATCH=0 and (see below) EB.PF=1.
7718 * Note that below we don't need special code to set EB.PF beyond the
7719 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7720 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7721 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7723 * A problem with this approach (when !enable_ept) is that L1 may be
7724 * injected with more page faults than it asked for. This could have
7725 * caused problems, but in practice existing hypervisors don't care.
7726 * To fix this, we will need to emulate the PFEC checking (on the L1
7727 * page tables), using walk_addr(), when injecting PFs to L1.
7729 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7730 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7731 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7732 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7734 if (cpu_has_secondary_exec_ctrls()) {
7735 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7736 if (!vmx
->rdtscp_enabled
)
7737 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7738 /* Take the following fields only from vmcs12 */
7739 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7740 if (nested_cpu_has(vmcs12
,
7741 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7742 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7744 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7746 * Translate L1 physical address to host physical
7747 * address for vmcs02. Keep the page pinned, so this
7748 * physical address remains valid. We keep a reference
7749 * to it so we can release it later.
7751 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7752 nested_release_page(vmx
->nested
.apic_access_page
);
7753 vmx
->nested
.apic_access_page
=
7754 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7756 * If translation failed, no matter: This feature asks
7757 * to exit when accessing the given address, and if it
7758 * can never be accessed, this feature won't do
7761 if (!vmx
->nested
.apic_access_page
)
7763 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7765 vmcs_write64(APIC_ACCESS_ADDR
,
7766 page_to_phys(vmx
->nested
.apic_access_page
));
7767 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
7769 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7770 vmcs_write64(APIC_ACCESS_ADDR
,
7771 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
7774 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7779 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7780 * Some constant fields are set here by vmx_set_constant_host_state().
7781 * Other fields are different per CPU, and will be set later when
7782 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7784 vmx_set_constant_host_state(vmx
);
7787 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7788 * entry, but only if the current (host) sp changed from the value
7789 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7790 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7791 * here we just force the write to happen on entry.
7795 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7796 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7797 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7798 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7799 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7801 * Merging of IO and MSR bitmaps not currently supported.
7802 * Rather, exit every time.
7804 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7805 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7806 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7808 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7810 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7811 * bitwise-or of what L1 wants to trap for L2, and what we want to
7812 * trap. Note that CR0.TS also needs updating - we do this later.
7814 update_exception_bitmap(vcpu
);
7815 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7816 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7818 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7819 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7820 * bits are further modified by vmx_set_efer() below.
7822 exit_control
= vmcs_config
.vmexit_ctrl
;
7823 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7824 exit_control
|= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
7825 vm_exit_controls_init(vmx
, exit_control
);
7827 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7828 * emulated by vmx_set_efer(), below.
7830 vm_entry_controls_init(vmx
,
7831 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7832 ~VM_ENTRY_IA32E_MODE
) |
7833 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7835 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7836 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7837 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7838 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7839 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7842 set_cr4_guest_host_mask(vmx
);
7844 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7845 vmcs_write64(TSC_OFFSET
,
7846 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7848 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7852 * Trivially support vpid by letting L2s share their parent
7853 * L1's vpid. TODO: move to a more elaborate solution, giving
7854 * each L2 its own vpid and exposing the vpid feature to L1.
7856 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7857 vmx_flush_tlb(vcpu
);
7860 if (nested_cpu_has_ept(vmcs12
)) {
7861 kvm_mmu_unload(vcpu
);
7862 nested_ept_init_mmu_context(vcpu
);
7865 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7866 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7867 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7868 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7870 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7871 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7872 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7875 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7876 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7877 * The CR0_READ_SHADOW is what L2 should have expected to read given
7878 * the specifications by L1; It's not enough to take
7879 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7880 * have more bits than L1 expected.
7882 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7883 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7885 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7886 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7888 /* shadow page tables on either EPT or shadow page tables */
7889 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7890 kvm_mmu_reset_context(vcpu
);
7893 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7896 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7899 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7900 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7901 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7902 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7905 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7906 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7910 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7911 * for running an L2 nested guest.
7913 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7915 struct vmcs12
*vmcs12
;
7916 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7918 struct loaded_vmcs
*vmcs02
;
7921 if (!nested_vmx_check_permission(vcpu
) ||
7922 !nested_vmx_check_vmcs12(vcpu
))
7925 skip_emulated_instruction(vcpu
);
7926 vmcs12
= get_vmcs12(vcpu
);
7928 if (enable_shadow_vmcs
)
7929 copy_shadow_to_vmcs12(vmx
);
7932 * The nested entry process starts with enforcing various prerequisites
7933 * on vmcs12 as required by the Intel SDM, and act appropriately when
7934 * they fail: As the SDM explains, some conditions should cause the
7935 * instruction to fail, while others will cause the instruction to seem
7936 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7937 * To speed up the normal (success) code path, we should avoid checking
7938 * for misconfigurations which will anyway be caught by the processor
7939 * when using the merged vmcs02.
7941 if (vmcs12
->launch_state
== launch
) {
7942 nested_vmx_failValid(vcpu
,
7943 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7944 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7948 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
7949 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
7950 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7954 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7955 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7956 /*TODO: Also verify bits beyond physical address width are 0*/
7957 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7961 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7962 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7963 /*TODO: Also verify bits beyond physical address width are 0*/
7964 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7968 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7969 vmcs12
->vm_exit_msr_load_count
> 0 ||
7970 vmcs12
->vm_exit_msr_store_count
> 0) {
7971 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7973 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7977 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7978 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7979 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7980 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7981 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7982 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7983 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7984 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7985 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7986 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7988 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7992 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7993 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7994 nested_vmx_failValid(vcpu
,
7995 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7999 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8000 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8001 nested_vmx_entry_failure(vcpu
, vmcs12
,
8002 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8005 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8006 nested_vmx_entry_failure(vcpu
, vmcs12
,
8007 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8012 * If the load IA32_EFER VM-entry control is 1, the following checks
8013 * are performed on the field for the IA32_EFER MSR:
8014 * - Bits reserved in the IA32_EFER MSR must be 0.
8015 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8016 * the IA-32e mode guest VM-exit control. It must also be identical
8017 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8020 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8021 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8022 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8023 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8024 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8025 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8026 nested_vmx_entry_failure(vcpu
, vmcs12
,
8027 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8033 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8034 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8035 * the values of the LMA and LME bits in the field must each be that of
8036 * the host address-space size VM-exit control.
8038 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8039 ia32e
= (vmcs12
->vm_exit_controls
&
8040 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8041 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8042 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8043 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8044 nested_vmx_entry_failure(vcpu
, vmcs12
,
8045 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8051 * We're finally done with prerequisite checking, and can start with
8055 vmcs02
= nested_get_current_vmcs02(vmx
);
8059 enter_guest_mode(vcpu
);
8061 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8064 vmx
->loaded_vmcs
= vmcs02
;
8066 vmx_vcpu_load(vcpu
, cpu
);
8070 vmx_segment_cache_clear(vmx
);
8072 vmcs12
->launch_state
= 1;
8074 prepare_vmcs02(vcpu
, vmcs12
);
8076 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8077 return kvm_emulate_halt(vcpu
);
8079 vmx
->nested
.nested_run_pending
= 1;
8082 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8083 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8084 * returned as far as L1 is concerned. It will only return (and set
8085 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8091 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8092 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8093 * This function returns the new value we should put in vmcs12.guest_cr0.
8094 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8095 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8096 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8097 * didn't trap the bit, because if L1 did, so would L0).
8098 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8099 * been modified by L2, and L1 knows it. So just leave the old value of
8100 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8101 * isn't relevant, because if L0 traps this bit it can set it to anything.
8102 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8103 * changed these bits, and therefore they need to be updated, but L0
8104 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8105 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8107 static inline unsigned long
8108 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8111 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8112 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8113 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8114 vcpu
->arch
.cr0_guest_owned_bits
));
8117 static inline unsigned long
8118 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8121 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8122 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8123 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8124 vcpu
->arch
.cr4_guest_owned_bits
));
8127 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8128 struct vmcs12
*vmcs12
)
8133 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8134 nr
= vcpu
->arch
.exception
.nr
;
8135 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8137 if (kvm_exception_is_soft(nr
)) {
8138 vmcs12
->vm_exit_instruction_len
=
8139 vcpu
->arch
.event_exit_inst_len
;
8140 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8142 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8144 if (vcpu
->arch
.exception
.has_error_code
) {
8145 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8146 vmcs12
->idt_vectoring_error_code
=
8147 vcpu
->arch
.exception
.error_code
;
8150 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8151 } else if (vcpu
->arch
.nmi_injected
) {
8152 vmcs12
->idt_vectoring_info_field
=
8153 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8154 } else if (vcpu
->arch
.interrupt
.pending
) {
8155 nr
= vcpu
->arch
.interrupt
.nr
;
8156 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8158 if (vcpu
->arch
.interrupt
.soft
) {
8159 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8160 vmcs12
->vm_entry_instruction_len
=
8161 vcpu
->arch
.event_exit_inst_len
;
8163 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8165 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8170 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8171 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8172 * and this function updates it to reflect the changes to the guest state while
8173 * L2 was running (and perhaps made some exits which were handled directly by L0
8174 * without going back to L1), and to reflect the exit reason.
8175 * Note that we do not have to copy here all VMCS fields, just those that
8176 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8177 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8178 * which already writes to vmcs12 directly.
8180 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8181 u32 exit_reason
, u32 exit_intr_info
,
8182 unsigned long exit_qualification
)
8184 /* update guest state fields: */
8185 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8186 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8188 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8189 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8190 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8191 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8193 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8194 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8195 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8196 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8197 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8198 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8199 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8200 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8201 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8202 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8203 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8204 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8205 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8206 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8207 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8208 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8209 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8210 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8211 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8212 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8213 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8214 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8215 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8216 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8217 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8218 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8219 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8220 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8221 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8222 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8223 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8224 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8225 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8226 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8227 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8228 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8230 vmcs12
->guest_interruptibility_info
=
8231 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8232 vmcs12
->guest_pending_dbg_exceptions
=
8233 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8234 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8235 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8237 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8239 if ((vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
) &&
8240 (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
))
8241 vmcs12
->vmx_preemption_timer_value
=
8242 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
8245 * In some cases (usually, nested EPT), L2 is allowed to change its
8246 * own CR3 without exiting. If it has changed it, we must keep it.
8247 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8248 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8250 * Additionally, restore L2's PDPTR to vmcs12.
8253 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8254 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8255 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8256 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8257 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8260 vmcs12
->vm_entry_controls
=
8261 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8262 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8264 /* TODO: These cannot have changed unless we have MSR bitmaps and
8265 * the relevant bit asks not to trap the change */
8266 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8267 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8268 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8269 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8270 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8271 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8272 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8273 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8275 /* update exit information fields: */
8277 vmcs12
->vm_exit_reason
= exit_reason
;
8278 vmcs12
->exit_qualification
= exit_qualification
;
8280 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8281 if ((vmcs12
->vm_exit_intr_info
&
8282 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8283 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8284 vmcs12
->vm_exit_intr_error_code
=
8285 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8286 vmcs12
->idt_vectoring_info_field
= 0;
8287 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8288 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8290 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8291 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8292 * instead of reading the real value. */
8293 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8296 * Transfer the event that L0 or L1 may wanted to inject into
8297 * L2 to IDT_VECTORING_INFO_FIELD.
8299 vmcs12_save_pending_event(vcpu
, vmcs12
);
8303 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8304 * preserved above and would only end up incorrectly in L1.
8306 vcpu
->arch
.nmi_injected
= false;
8307 kvm_clear_exception_queue(vcpu
);
8308 kvm_clear_interrupt_queue(vcpu
);
8312 * A part of what we need to when the nested L2 guest exits and we want to
8313 * run its L1 parent, is to reset L1's guest state to the host state specified
8315 * This function is to be called not only on normal nested exit, but also on
8316 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8317 * Failures During or After Loading Guest State").
8318 * This function should be called when the active VMCS is L1's (vmcs01).
8320 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8321 struct vmcs12
*vmcs12
)
8323 struct kvm_segment seg
;
8325 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8326 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8327 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8328 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8330 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8331 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8333 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8334 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8335 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8337 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8338 * actually changed, because it depends on the current state of
8339 * fpu_active (which may have changed).
8340 * Note that vmx_set_cr0 refers to efer set above.
8342 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8344 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8345 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8346 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8348 update_exception_bitmap(vcpu
);
8349 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8350 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8353 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8354 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8356 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8357 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8359 nested_ept_uninit_mmu_context(vcpu
);
8361 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8362 kvm_mmu_reset_context(vcpu
);
8365 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8369 * Trivially support vpid by letting L2s share their parent
8370 * L1's vpid. TODO: move to a more elaborate solution, giving
8371 * each L2 its own vpid and exposing the vpid feature to L1.
8373 vmx_flush_tlb(vcpu
);
8377 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8378 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8379 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8380 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8381 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8383 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8384 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8385 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8387 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8388 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8389 vmcs12
->host_ia32_perf_global_ctrl
);
8391 /* Set L1 segment info according to Intel SDM
8392 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8393 seg
= (struct kvm_segment
) {
8395 .limit
= 0xFFFFFFFF,
8396 .selector
= vmcs12
->host_cs_selector
,
8402 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8406 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8407 seg
= (struct kvm_segment
) {
8409 .limit
= 0xFFFFFFFF,
8416 seg
.selector
= vmcs12
->host_ds_selector
;
8417 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8418 seg
.selector
= vmcs12
->host_es_selector
;
8419 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8420 seg
.selector
= vmcs12
->host_ss_selector
;
8421 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8422 seg
.selector
= vmcs12
->host_fs_selector
;
8423 seg
.base
= vmcs12
->host_fs_base
;
8424 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8425 seg
.selector
= vmcs12
->host_gs_selector
;
8426 seg
.base
= vmcs12
->host_gs_base
;
8427 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8428 seg
= (struct kvm_segment
) {
8429 .base
= vmcs12
->host_tr_base
,
8431 .selector
= vmcs12
->host_tr_selector
,
8435 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8437 kvm_set_dr(vcpu
, 7, 0x400);
8438 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8442 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8443 * and modify vmcs12 to make it see what it would expect to see there if
8444 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8446 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8448 unsigned long exit_qualification
)
8450 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8452 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8454 /* trying to cancel vmlaunch/vmresume is a bug */
8455 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8457 leave_guest_mode(vcpu
);
8458 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8459 exit_qualification
);
8461 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8462 vmcs12
->exit_qualification
,
8463 vmcs12
->idt_vectoring_info_field
,
8464 vmcs12
->vm_exit_intr_info
,
8465 vmcs12
->vm_exit_intr_error_code
,
8469 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8471 vmx_vcpu_load(vcpu
, cpu
);
8475 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8476 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8477 vmx_segment_cache_clear(vmx
);
8479 /* if no vmcs02 cache requested, remove the one we used */
8480 if (VMCS02_POOL_SIZE
== 0)
8481 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8483 load_vmcs12_host_state(vcpu
, vmcs12
);
8485 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8486 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8488 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8491 /* Unpin physical memory we referred to in vmcs02 */
8492 if (vmx
->nested
.apic_access_page
) {
8493 nested_release_page(vmx
->nested
.apic_access_page
);
8494 vmx
->nested
.apic_access_page
= 0;
8498 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8499 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8500 * success or failure flag accordingly.
8502 if (unlikely(vmx
->fail
)) {
8504 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8506 nested_vmx_succeed(vcpu
);
8507 if (enable_shadow_vmcs
)
8508 vmx
->nested
.sync_shadow_vmcs
= true;
8512 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8514 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8516 if (is_guest_mode(vcpu
))
8517 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8518 free_nested(to_vmx(vcpu
));
8522 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8523 * 23.7 "VM-entry failures during or after loading guest state" (this also
8524 * lists the acceptable exit-reason and exit-qualification parameters).
8525 * It should only be called before L2 actually succeeded to run, and when
8526 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8528 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8529 struct vmcs12
*vmcs12
,
8530 u32 reason
, unsigned long qualification
)
8532 load_vmcs12_host_state(vcpu
, vmcs12
);
8533 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8534 vmcs12
->exit_qualification
= qualification
;
8535 nested_vmx_succeed(vcpu
);
8536 if (enable_shadow_vmcs
)
8537 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8540 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8541 struct x86_instruction_info
*info
,
8542 enum x86_intercept_stage stage
)
8544 return X86EMUL_CONTINUE
;
8547 static struct kvm_x86_ops vmx_x86_ops
= {
8548 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8549 .disabled_by_bios
= vmx_disabled_by_bios
,
8550 .hardware_setup
= hardware_setup
,
8551 .hardware_unsetup
= hardware_unsetup
,
8552 .check_processor_compatibility
= vmx_check_processor_compat
,
8553 .hardware_enable
= hardware_enable
,
8554 .hardware_disable
= hardware_disable
,
8555 .cpu_has_accelerated_tpr
= report_flexpriority
,
8557 .vcpu_create
= vmx_create_vcpu
,
8558 .vcpu_free
= vmx_free_vcpu
,
8559 .vcpu_reset
= vmx_vcpu_reset
,
8561 .prepare_guest_switch
= vmx_save_host_state
,
8562 .vcpu_load
= vmx_vcpu_load
,
8563 .vcpu_put
= vmx_vcpu_put
,
8565 .update_db_bp_intercept
= update_exception_bitmap
,
8566 .get_msr
= vmx_get_msr
,
8567 .set_msr
= vmx_set_msr
,
8568 .get_segment_base
= vmx_get_segment_base
,
8569 .get_segment
= vmx_get_segment
,
8570 .set_segment
= vmx_set_segment
,
8571 .get_cpl
= vmx_get_cpl
,
8572 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8573 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8574 .decache_cr3
= vmx_decache_cr3
,
8575 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8576 .set_cr0
= vmx_set_cr0
,
8577 .set_cr3
= vmx_set_cr3
,
8578 .set_cr4
= vmx_set_cr4
,
8579 .set_efer
= vmx_set_efer
,
8580 .get_idt
= vmx_get_idt
,
8581 .set_idt
= vmx_set_idt
,
8582 .get_gdt
= vmx_get_gdt
,
8583 .set_gdt
= vmx_set_gdt
,
8584 .get_dr6
= vmx_get_dr6
,
8585 .set_dr6
= vmx_set_dr6
,
8586 .set_dr7
= vmx_set_dr7
,
8587 .cache_reg
= vmx_cache_reg
,
8588 .get_rflags
= vmx_get_rflags
,
8589 .set_rflags
= vmx_set_rflags
,
8590 .fpu_activate
= vmx_fpu_activate
,
8591 .fpu_deactivate
= vmx_fpu_deactivate
,
8593 .tlb_flush
= vmx_flush_tlb
,
8595 .run
= vmx_vcpu_run
,
8596 .handle_exit
= vmx_handle_exit
,
8597 .skip_emulated_instruction
= skip_emulated_instruction
,
8598 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8599 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8600 .patch_hypercall
= vmx_patch_hypercall
,
8601 .set_irq
= vmx_inject_irq
,
8602 .set_nmi
= vmx_inject_nmi
,
8603 .queue_exception
= vmx_queue_exception
,
8604 .cancel_injection
= vmx_cancel_injection
,
8605 .interrupt_allowed
= vmx_interrupt_allowed
,
8606 .nmi_allowed
= vmx_nmi_allowed
,
8607 .get_nmi_mask
= vmx_get_nmi_mask
,
8608 .set_nmi_mask
= vmx_set_nmi_mask
,
8609 .enable_nmi_window
= enable_nmi_window
,
8610 .enable_irq_window
= enable_irq_window
,
8611 .update_cr8_intercept
= update_cr8_intercept
,
8612 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8613 .vm_has_apicv
= vmx_vm_has_apicv
,
8614 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8615 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8616 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8617 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8618 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8620 .set_tss_addr
= vmx_set_tss_addr
,
8621 .get_tdp_level
= get_ept_level
,
8622 .get_mt_mask
= vmx_get_mt_mask
,
8624 .get_exit_info
= vmx_get_exit_info
,
8626 .get_lpage_level
= vmx_get_lpage_level
,
8628 .cpuid_update
= vmx_cpuid_update
,
8630 .rdtscp_supported
= vmx_rdtscp_supported
,
8631 .invpcid_supported
= vmx_invpcid_supported
,
8633 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8635 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8637 .set_tsc_khz
= vmx_set_tsc_khz
,
8638 .read_tsc_offset
= vmx_read_tsc_offset
,
8639 .write_tsc_offset
= vmx_write_tsc_offset
,
8640 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8641 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8642 .read_l1_tsc
= vmx_read_l1_tsc
,
8644 .set_tdp_cr3
= vmx_set_cr3
,
8646 .check_intercept
= vmx_check_intercept
,
8647 .handle_external_intr
= vmx_handle_external_intr
,
8648 .mpx_supported
= vmx_mpx_supported
,
8651 static int __init
vmx_init(void)
8655 rdmsrl_safe(MSR_EFER
, &host_efer
);
8657 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8658 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8660 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8661 if (!vmx_io_bitmap_a
)
8666 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8667 if (!vmx_io_bitmap_b
)
8670 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8671 if (!vmx_msr_bitmap_legacy
)
8674 vmx_msr_bitmap_legacy_x2apic
=
8675 (unsigned long *)__get_free_page(GFP_KERNEL
);
8676 if (!vmx_msr_bitmap_legacy_x2apic
)
8679 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8680 if (!vmx_msr_bitmap_longmode
)
8683 vmx_msr_bitmap_longmode_x2apic
=
8684 (unsigned long *)__get_free_page(GFP_KERNEL
);
8685 if (!vmx_msr_bitmap_longmode_x2apic
)
8687 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8688 if (!vmx_vmread_bitmap
)
8691 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8692 if (!vmx_vmwrite_bitmap
)
8695 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8696 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8697 /* shadowed read/write fields */
8698 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8699 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8700 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8702 /* shadowed read only fields */
8703 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8704 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8707 * Allow direct access to the PC debug port (it is often used for I/O
8708 * delays, but the vmexits simply slow things down).
8710 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8711 clear_bit(0x80, vmx_io_bitmap_a
);
8713 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8715 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8716 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8718 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8720 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8721 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8726 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8727 crash_vmclear_local_loaded_vmcss
);
8730 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8731 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8732 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8733 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8734 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8735 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8736 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
8738 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8739 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8740 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8741 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8744 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8745 vmx_disable_intercept_msr_read_x2apic(msr
);
8747 /* According SDM, in x2apic mode, the whole id reg is used.
8748 * But in KVM, it only use the highest eight bits. Need to
8750 vmx_enable_intercept_msr_read_x2apic(0x802);
8752 vmx_enable_intercept_msr_read_x2apic(0x839);
8754 vmx_disable_intercept_msr_write_x2apic(0x808);
8756 vmx_disable_intercept_msr_write_x2apic(0x80b);
8758 vmx_disable_intercept_msr_write_x2apic(0x83f);
8762 kvm_mmu_set_mask_ptes(0ull,
8763 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8764 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8765 0ull, VMX_EPT_EXECUTABLE_MASK
);
8766 ept_set_mmio_spte_mask();
8774 free_page((unsigned long)vmx_vmwrite_bitmap
);
8776 free_page((unsigned long)vmx_vmread_bitmap
);
8778 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8780 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8782 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8784 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8786 free_page((unsigned long)vmx_io_bitmap_b
);
8788 free_page((unsigned long)vmx_io_bitmap_a
);
8792 static void __exit
vmx_exit(void)
8794 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8795 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8796 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8797 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8798 free_page((unsigned long)vmx_io_bitmap_b
);
8799 free_page((unsigned long)vmx_io_bitmap_a
);
8800 free_page((unsigned long)vmx_vmwrite_bitmap
);
8801 free_page((unsigned long)vmx_vmread_bitmap
);
8804 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8811 module_init(vmx_init
)
8812 module_exit(vmx_exit
)