2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
154 module_param(ple_gap
, int, S_IRUGO
);
156 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
157 module_param(ple_window
, int, S_IRUGO
);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
161 module_param(ple_window_grow
, int, S_IRUGO
);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
165 module_param(ple_window_shrink
, int, S_IRUGO
);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
169 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
170 module_param(ple_window_max
, int, S_IRUGO
);
172 extern const ulong vmx_return
;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
192 struct list_head loaded_vmcss_on_cpu_link
;
195 struct shared_msr_entry
{
202 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
203 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
204 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
205 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
206 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
207 * More than one of these structures may exist, if L1 runs multiple L2 guests.
208 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
209 * underlying hardware which will be used to run L2.
210 * This structure is packed to ensure that its layout is identical across
211 * machines (necessary for live migration).
212 * If there are changes in this struct, VMCS12_REVISION must be changed.
214 typedef u64 natural_width
;
215 struct __packed vmcs12
{
216 /* According to the Intel spec, a VMCS region must start with the
217 * following two fields. Then follow implementation-specific data.
222 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
223 u32 padding
[7]; /* room for future expansion */
228 u64 vm_exit_msr_store_addr
;
229 u64 vm_exit_msr_load_addr
;
230 u64 vm_entry_msr_load_addr
;
232 u64 virtual_apic_page_addr
;
233 u64 apic_access_addr
;
234 u64 posted_intr_desc_addr
;
236 u64 eoi_exit_bitmap0
;
237 u64 eoi_exit_bitmap1
;
238 u64 eoi_exit_bitmap2
;
239 u64 eoi_exit_bitmap3
;
241 u64 guest_physical_address
;
242 u64 vmcs_link_pointer
;
243 u64 guest_ia32_debugctl
;
246 u64 guest_ia32_perf_global_ctrl
;
254 u64 host_ia32_perf_global_ctrl
;
255 u64 padding64
[8]; /* room for future expansion */
257 * To allow migration of L1 (complete with its L2 guests) between
258 * machines of different natural widths (32 or 64 bit), we cannot have
259 * unsigned long fields with no explict size. We use u64 (aliased
260 * natural_width) instead. Luckily, x86 is little-endian.
262 natural_width cr0_guest_host_mask
;
263 natural_width cr4_guest_host_mask
;
264 natural_width cr0_read_shadow
;
265 natural_width cr4_read_shadow
;
266 natural_width cr3_target_value0
;
267 natural_width cr3_target_value1
;
268 natural_width cr3_target_value2
;
269 natural_width cr3_target_value3
;
270 natural_width exit_qualification
;
271 natural_width guest_linear_address
;
272 natural_width guest_cr0
;
273 natural_width guest_cr3
;
274 natural_width guest_cr4
;
275 natural_width guest_es_base
;
276 natural_width guest_cs_base
;
277 natural_width guest_ss_base
;
278 natural_width guest_ds_base
;
279 natural_width guest_fs_base
;
280 natural_width guest_gs_base
;
281 natural_width guest_ldtr_base
;
282 natural_width guest_tr_base
;
283 natural_width guest_gdtr_base
;
284 natural_width guest_idtr_base
;
285 natural_width guest_dr7
;
286 natural_width guest_rsp
;
287 natural_width guest_rip
;
288 natural_width guest_rflags
;
289 natural_width guest_pending_dbg_exceptions
;
290 natural_width guest_sysenter_esp
;
291 natural_width guest_sysenter_eip
;
292 natural_width host_cr0
;
293 natural_width host_cr3
;
294 natural_width host_cr4
;
295 natural_width host_fs_base
;
296 natural_width host_gs_base
;
297 natural_width host_tr_base
;
298 natural_width host_gdtr_base
;
299 natural_width host_idtr_base
;
300 natural_width host_ia32_sysenter_esp
;
301 natural_width host_ia32_sysenter_eip
;
302 natural_width host_rsp
;
303 natural_width host_rip
;
304 natural_width paddingl
[8]; /* room for future expansion */
305 u32 pin_based_vm_exec_control
;
306 u32 cpu_based_vm_exec_control
;
307 u32 exception_bitmap
;
308 u32 page_fault_error_code_mask
;
309 u32 page_fault_error_code_match
;
310 u32 cr3_target_count
;
311 u32 vm_exit_controls
;
312 u32 vm_exit_msr_store_count
;
313 u32 vm_exit_msr_load_count
;
314 u32 vm_entry_controls
;
315 u32 vm_entry_msr_load_count
;
316 u32 vm_entry_intr_info_field
;
317 u32 vm_entry_exception_error_code
;
318 u32 vm_entry_instruction_len
;
320 u32 secondary_vm_exec_control
;
321 u32 vm_instruction_error
;
323 u32 vm_exit_intr_info
;
324 u32 vm_exit_intr_error_code
;
325 u32 idt_vectoring_info_field
;
326 u32 idt_vectoring_error_code
;
327 u32 vm_exit_instruction_len
;
328 u32 vmx_instruction_info
;
335 u32 guest_ldtr_limit
;
337 u32 guest_gdtr_limit
;
338 u32 guest_idtr_limit
;
339 u32 guest_es_ar_bytes
;
340 u32 guest_cs_ar_bytes
;
341 u32 guest_ss_ar_bytes
;
342 u32 guest_ds_ar_bytes
;
343 u32 guest_fs_ar_bytes
;
344 u32 guest_gs_ar_bytes
;
345 u32 guest_ldtr_ar_bytes
;
346 u32 guest_tr_ar_bytes
;
347 u32 guest_interruptibility_info
;
348 u32 guest_activity_state
;
349 u32 guest_sysenter_cs
;
350 u32 host_ia32_sysenter_cs
;
351 u32 vmx_preemption_timer_value
;
352 u32 padding32
[7]; /* room for future expansion */
353 u16 virtual_processor_id
;
355 u16 guest_es_selector
;
356 u16 guest_cs_selector
;
357 u16 guest_ss_selector
;
358 u16 guest_ds_selector
;
359 u16 guest_fs_selector
;
360 u16 guest_gs_selector
;
361 u16 guest_ldtr_selector
;
362 u16 guest_tr_selector
;
363 u16 guest_intr_status
;
364 u16 host_es_selector
;
365 u16 host_cs_selector
;
366 u16 host_ss_selector
;
367 u16 host_ds_selector
;
368 u16 host_fs_selector
;
369 u16 host_gs_selector
;
370 u16 host_tr_selector
;
374 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
375 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
376 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
378 #define VMCS12_REVISION 0x11e57ed0
381 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
382 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
383 * current implementation, 4K are reserved to avoid future complications.
385 #define VMCS12_SIZE 0x1000
387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
389 struct list_head list
;
391 struct loaded_vmcs vmcs02
;
395 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
396 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
399 /* Has the level1 guest done vmxon? */
403 /* The guest-physical address of the current VMCS L1 keeps for L2 */
405 /* The host-usable pointer to the above */
406 struct page
*current_vmcs12_page
;
407 struct vmcs12
*current_vmcs12
;
408 struct vmcs
*current_shadow_vmcs
;
410 * Indicates if the shadow vmcs must be updated with the
411 * data hold by vmcs12
413 bool sync_shadow_vmcs
;
415 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
416 struct list_head vmcs02_pool
;
418 u64 vmcs01_tsc_offset
;
419 /* L2 must run next, and mustn't decide to exit to L1. */
420 bool nested_run_pending
;
422 * Guest pages referred to in vmcs02 with host-physical pointers, so
423 * we must keep them pinned while L2 runs.
425 struct page
*apic_access_page
;
426 struct page
*virtual_apic_page
;
427 struct page
*pi_desc_page
;
428 struct pi_desc
*pi_desc
;
432 struct hrtimer preemption_timer
;
433 bool preemption_timer_expired
;
435 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
441 u32 nested_vmx_procbased_ctls_low
;
442 u32 nested_vmx_procbased_ctls_high
;
443 u32 nested_vmx_true_procbased_ctls_low
;
444 u32 nested_vmx_secondary_ctls_low
;
445 u32 nested_vmx_secondary_ctls_high
;
446 u32 nested_vmx_pinbased_ctls_low
;
447 u32 nested_vmx_pinbased_ctls_high
;
448 u32 nested_vmx_exit_ctls_low
;
449 u32 nested_vmx_exit_ctls_high
;
450 u32 nested_vmx_true_exit_ctls_low
;
451 u32 nested_vmx_entry_ctls_low
;
452 u32 nested_vmx_entry_ctls_high
;
453 u32 nested_vmx_true_entry_ctls_low
;
454 u32 nested_vmx_misc_low
;
455 u32 nested_vmx_misc_high
;
456 u32 nested_vmx_ept_caps
;
457 u32 nested_vmx_vpid_caps
;
460 #define POSTED_INTR_ON 0
461 #define POSTED_INTR_SN 1
463 /* Posted-Interrupt Descriptor */
465 u32 pir
[8]; /* Posted interrupt requested */
468 /* bit 256 - Outstanding Notification */
470 /* bit 257 - Suppress Notification */
472 /* bit 271:258 - Reserved */
474 /* bit 279:272 - Notification Vector */
476 /* bit 287:280 - Reserved */
478 /* bit 319:288 - Notification Destination */
486 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
488 return test_and_set_bit(POSTED_INTR_ON
,
489 (unsigned long *)&pi_desc
->control
);
492 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
494 return test_and_clear_bit(POSTED_INTR_ON
,
495 (unsigned long *)&pi_desc
->control
);
498 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
500 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
503 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
505 return clear_bit(POSTED_INTR_SN
,
506 (unsigned long *)&pi_desc
->control
);
509 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
511 return set_bit(POSTED_INTR_SN
,
512 (unsigned long *)&pi_desc
->control
);
515 static inline int pi_test_on(struct pi_desc
*pi_desc
)
517 return test_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
523 return test_bit(POSTED_INTR_SN
,
524 (unsigned long *)&pi_desc
->control
);
528 struct kvm_vcpu vcpu
;
529 unsigned long host_rsp
;
531 bool nmi_known_unmasked
;
533 u32 idt_vectoring_info
;
535 struct shared_msr_entry
*guest_msrs
;
538 unsigned long host_idt_base
;
540 u64 msr_host_kernel_gs_base
;
541 u64 msr_guest_kernel_gs_base
;
543 u32 vm_entry_controls_shadow
;
544 u32 vm_exit_controls_shadow
;
546 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
547 * non-nested (L1) guest, it always points to vmcs01. For a nested
548 * guest (L2), it points to a different VMCS.
550 struct loaded_vmcs vmcs01
;
551 struct loaded_vmcs
*loaded_vmcs
;
552 bool __launched
; /* temporary, used in vmx_vcpu_run */
553 struct msr_autoload
{
555 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
556 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
560 u16 fs_sel
, gs_sel
, ldt_sel
;
564 int gs_ldt_reload_needed
;
565 int fs_reload_needed
;
566 u64 msr_host_bndcfgs
;
567 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
572 struct kvm_segment segs
[8];
575 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
576 struct kvm_save_segment
{
584 bool emulation_required
;
586 /* Support for vnmi-less CPUs */
587 int soft_vnmi_blocked
;
589 s64 vnmi_blocked_time
;
592 /* Posted interrupt descriptor */
593 struct pi_desc pi_desc
;
595 /* Support for a guest hypervisor (nested VMX) */
596 struct nested_vmx nested
;
598 /* Dynamic PLE window. */
600 bool ple_window_dirty
;
602 /* Support for PML */
603 #define PML_ENTITY_NUM 512
606 /* apic deadline value in host tsc */
609 u64 current_tsc_ratio
;
611 bool guest_pkru_valid
;
616 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
617 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
618 * in msr_ia32_feature_control_valid_bits.
620 u64 msr_ia32_feature_control
;
621 u64 msr_ia32_feature_control_valid_bits
;
624 enum segment_cache_field
{
633 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
635 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
638 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
640 return &(to_vmx(vcpu
)->pi_desc
);
643 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
644 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
645 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
646 [number##_HIGH] = VMCS12_OFFSET(name)+4
649 static unsigned long shadow_read_only_fields
[] = {
651 * We do NOT shadow fields that are modified when L0
652 * traps and emulates any vmx instruction (e.g. VMPTRLD,
653 * VMXON...) executed by L1.
654 * For example, VM_INSTRUCTION_ERROR is read
655 * by L1 if a vmx instruction fails (part of the error path).
656 * Note the code assumes this logic. If for some reason
657 * we start shadowing these fields then we need to
658 * force a shadow sync when L0 emulates vmx instructions
659 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
660 * by nested_vmx_failValid)
664 VM_EXIT_INSTRUCTION_LEN
,
665 IDT_VECTORING_INFO_FIELD
,
666 IDT_VECTORING_ERROR_CODE
,
667 VM_EXIT_INTR_ERROR_CODE
,
669 GUEST_LINEAR_ADDRESS
,
670 GUEST_PHYSICAL_ADDRESS
672 static int max_shadow_read_only_fields
=
673 ARRAY_SIZE(shadow_read_only_fields
);
675 static unsigned long shadow_read_write_fields
[] = {
682 GUEST_INTERRUPTIBILITY_INFO
,
695 CPU_BASED_VM_EXEC_CONTROL
,
696 VM_ENTRY_EXCEPTION_ERROR_CODE
,
697 VM_ENTRY_INTR_INFO_FIELD
,
698 VM_ENTRY_INSTRUCTION_LEN
,
699 VM_ENTRY_EXCEPTION_ERROR_CODE
,
705 static int max_shadow_read_write_fields
=
706 ARRAY_SIZE(shadow_read_write_fields
);
708 static const unsigned short vmcs_field_to_offset_table
[] = {
709 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
710 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
711 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
712 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
713 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
714 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
715 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
716 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
717 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
718 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
719 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
720 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
721 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
722 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
723 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
724 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
725 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
726 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
727 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
728 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
729 FIELD64(MSR_BITMAP
, msr_bitmap
),
730 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
731 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
732 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
733 FIELD64(TSC_OFFSET
, tsc_offset
),
734 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
735 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
736 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
737 FIELD64(EPT_POINTER
, ept_pointer
),
738 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
739 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
740 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
741 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
742 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
743 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
744 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
745 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
746 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
747 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
748 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
749 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
750 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
751 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
752 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
753 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
754 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
755 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
756 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
757 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
758 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
759 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
760 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
761 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
762 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
763 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
764 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
765 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
766 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
767 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
768 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
769 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
770 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
771 FIELD(TPR_THRESHOLD
, tpr_threshold
),
772 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
773 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
774 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
775 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
776 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
777 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
778 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
779 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
780 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
781 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
782 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
783 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
784 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
785 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
786 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
787 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
788 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
789 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
790 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
791 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
792 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
793 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
794 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
795 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
796 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
797 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
798 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
799 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
800 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
801 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
802 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
803 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
804 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
805 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
806 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
807 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
808 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
809 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
810 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
811 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
812 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
813 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
814 FIELD(GUEST_CR0
, guest_cr0
),
815 FIELD(GUEST_CR3
, guest_cr3
),
816 FIELD(GUEST_CR4
, guest_cr4
),
817 FIELD(GUEST_ES_BASE
, guest_es_base
),
818 FIELD(GUEST_CS_BASE
, guest_cs_base
),
819 FIELD(GUEST_SS_BASE
, guest_ss_base
),
820 FIELD(GUEST_DS_BASE
, guest_ds_base
),
821 FIELD(GUEST_FS_BASE
, guest_fs_base
),
822 FIELD(GUEST_GS_BASE
, guest_gs_base
),
823 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
824 FIELD(GUEST_TR_BASE
, guest_tr_base
),
825 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
826 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
827 FIELD(GUEST_DR7
, guest_dr7
),
828 FIELD(GUEST_RSP
, guest_rsp
),
829 FIELD(GUEST_RIP
, guest_rip
),
830 FIELD(GUEST_RFLAGS
, guest_rflags
),
831 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
832 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
833 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
834 FIELD(HOST_CR0
, host_cr0
),
835 FIELD(HOST_CR3
, host_cr3
),
836 FIELD(HOST_CR4
, host_cr4
),
837 FIELD(HOST_FS_BASE
, host_fs_base
),
838 FIELD(HOST_GS_BASE
, host_gs_base
),
839 FIELD(HOST_TR_BASE
, host_tr_base
),
840 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
841 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
842 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
843 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
844 FIELD(HOST_RSP
, host_rsp
),
845 FIELD(HOST_RIP
, host_rip
),
848 static inline short vmcs_field_to_offset(unsigned long field
)
850 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
852 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
853 vmcs_field_to_offset_table
[field
] == 0)
856 return vmcs_field_to_offset_table
[field
];
859 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
861 return to_vmx(vcpu
)->nested
.current_vmcs12
;
864 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
866 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
867 if (is_error_page(page
))
873 static void nested_release_page(struct page
*page
)
875 kvm_release_page_dirty(page
);
878 static void nested_release_page_clean(struct page
*page
)
880 kvm_release_page_clean(page
);
883 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
884 static u64
construct_eptp(unsigned long root_hpa
);
885 static void kvm_cpu_vmxon(u64 addr
);
886 static void kvm_cpu_vmxoff(void);
887 static bool vmx_xsaves_supported(void);
888 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
889 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
890 struct kvm_segment
*var
, int seg
);
891 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
892 struct kvm_segment
*var
, int seg
);
893 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
894 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
895 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
896 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
897 static int alloc_identity_pagetable(struct kvm
*kvm
);
899 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
900 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
902 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
903 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
905 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
906 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
909 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
910 * can find which vCPU should be waken up.
912 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
913 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
915 static unsigned long *vmx_io_bitmap_a
;
916 static unsigned long *vmx_io_bitmap_b
;
917 static unsigned long *vmx_msr_bitmap_legacy
;
918 static unsigned long *vmx_msr_bitmap_longmode
;
919 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
920 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
921 static unsigned long *vmx_msr_bitmap_nested
;
922 static unsigned long *vmx_vmread_bitmap
;
923 static unsigned long *vmx_vmwrite_bitmap
;
925 static bool cpu_has_load_ia32_efer
;
926 static bool cpu_has_load_perf_global_ctrl
;
928 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
929 static DEFINE_SPINLOCK(vmx_vpid_lock
);
931 static struct vmcs_config
{
935 u32 pin_based_exec_ctrl
;
936 u32 cpu_based_exec_ctrl
;
937 u32 cpu_based_2nd_exec_ctrl
;
942 static struct vmx_capability
{
947 #define VMX_SEGMENT_FIELD(seg) \
948 [VCPU_SREG_##seg] = { \
949 .selector = GUEST_##seg##_SELECTOR, \
950 .base = GUEST_##seg##_BASE, \
951 .limit = GUEST_##seg##_LIMIT, \
952 .ar_bytes = GUEST_##seg##_AR_BYTES, \
955 static const struct kvm_vmx_segment_field
{
960 } kvm_vmx_segment_fields
[] = {
961 VMX_SEGMENT_FIELD(CS
),
962 VMX_SEGMENT_FIELD(DS
),
963 VMX_SEGMENT_FIELD(ES
),
964 VMX_SEGMENT_FIELD(FS
),
965 VMX_SEGMENT_FIELD(GS
),
966 VMX_SEGMENT_FIELD(SS
),
967 VMX_SEGMENT_FIELD(TR
),
968 VMX_SEGMENT_FIELD(LDTR
),
971 static u64 host_efer
;
973 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
976 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
977 * away by decrementing the array size.
979 static const u32 vmx_msr_index
[] = {
981 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
983 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
986 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
988 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
989 INTR_INFO_VALID_MASK
)) ==
990 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
993 static inline bool is_debug(u32 intr_info
)
995 return is_exception_n(intr_info
, DB_VECTOR
);
998 static inline bool is_breakpoint(u32 intr_info
)
1000 return is_exception_n(intr_info
, BP_VECTOR
);
1003 static inline bool is_page_fault(u32 intr_info
)
1005 return is_exception_n(intr_info
, PF_VECTOR
);
1008 static inline bool is_no_device(u32 intr_info
)
1010 return is_exception_n(intr_info
, NM_VECTOR
);
1013 static inline bool is_invalid_opcode(u32 intr_info
)
1015 return is_exception_n(intr_info
, UD_VECTOR
);
1018 static inline bool is_external_interrupt(u32 intr_info
)
1020 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1021 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1024 static inline bool is_machine_check(u32 intr_info
)
1026 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1027 INTR_INFO_VALID_MASK
)) ==
1028 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1031 static inline bool cpu_has_vmx_msr_bitmap(void)
1033 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1036 static inline bool cpu_has_vmx_tpr_shadow(void)
1038 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1041 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1043 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1046 static inline bool cpu_has_secondary_exec_ctrls(void)
1048 return vmcs_config
.cpu_based_exec_ctrl
&
1049 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1052 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1054 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1055 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1058 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1060 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1061 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1064 static inline bool cpu_has_vmx_apic_register_virt(void)
1066 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1067 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1070 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1072 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1073 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1077 * Comment's format: document - errata name - stepping - processor name.
1079 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1081 static u32 vmx_preemption_cpu_tfms
[] = {
1082 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1084 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1085 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1086 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1088 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1090 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1091 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1093 * 320767.pdf - AAP86 - B1 -
1094 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1097 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1099 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1101 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1103 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1104 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1105 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1109 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1111 u32 eax
= cpuid_eax(0x00000001), i
;
1113 /* Clear the reserved bits */
1114 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1115 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1116 if (eax
== vmx_preemption_cpu_tfms
[i
])
1122 static inline bool cpu_has_vmx_preemption_timer(void)
1124 return vmcs_config
.pin_based_exec_ctrl
&
1125 PIN_BASED_VMX_PREEMPTION_TIMER
;
1128 static inline bool cpu_has_vmx_posted_intr(void)
1130 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1131 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1134 static inline bool cpu_has_vmx_apicv(void)
1136 return cpu_has_vmx_apic_register_virt() &&
1137 cpu_has_vmx_virtual_intr_delivery() &&
1138 cpu_has_vmx_posted_intr();
1141 static inline bool cpu_has_vmx_flexpriority(void)
1143 return cpu_has_vmx_tpr_shadow() &&
1144 cpu_has_vmx_virtualize_apic_accesses();
1147 static inline bool cpu_has_vmx_ept_execute_only(void)
1149 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1152 static inline bool cpu_has_vmx_ept_2m_page(void)
1154 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1157 static inline bool cpu_has_vmx_ept_1g_page(void)
1159 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1162 static inline bool cpu_has_vmx_ept_4levels(void)
1164 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1167 static inline bool cpu_has_vmx_ept_ad_bits(void)
1169 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1172 static inline bool cpu_has_vmx_invept_context(void)
1174 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1177 static inline bool cpu_has_vmx_invept_global(void)
1179 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1182 static inline bool cpu_has_vmx_invvpid_single(void)
1184 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1187 static inline bool cpu_has_vmx_invvpid_global(void)
1189 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1192 static inline bool cpu_has_vmx_ept(void)
1194 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1195 SECONDARY_EXEC_ENABLE_EPT
;
1198 static inline bool cpu_has_vmx_unrestricted_guest(void)
1200 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1201 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1204 static inline bool cpu_has_vmx_ple(void)
1206 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1207 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1210 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1212 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1215 static inline bool cpu_has_vmx_vpid(void)
1217 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1218 SECONDARY_EXEC_ENABLE_VPID
;
1221 static inline bool cpu_has_vmx_rdtscp(void)
1223 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1224 SECONDARY_EXEC_RDTSCP
;
1227 static inline bool cpu_has_vmx_invpcid(void)
1229 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1230 SECONDARY_EXEC_ENABLE_INVPCID
;
1233 static inline bool cpu_has_virtual_nmis(void)
1235 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1238 static inline bool cpu_has_vmx_wbinvd_exit(void)
1240 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1241 SECONDARY_EXEC_WBINVD_EXITING
;
1244 static inline bool cpu_has_vmx_shadow_vmcs(void)
1247 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1248 /* check if the cpu supports writing r/o exit information fields */
1249 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1252 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1253 SECONDARY_EXEC_SHADOW_VMCS
;
1256 static inline bool cpu_has_vmx_pml(void)
1258 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1261 static inline bool cpu_has_vmx_tsc_scaling(void)
1263 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1264 SECONDARY_EXEC_TSC_SCALING
;
1267 static inline bool report_flexpriority(void)
1269 return flexpriority_enabled
;
1272 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1274 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1277 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1279 return (vmcs12
->cpu_based_vm_exec_control
&
1280 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1281 (vmcs12
->secondary_vm_exec_control
& bit
);
1284 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1286 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1289 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1291 return vmcs12
->pin_based_vm_exec_control
&
1292 PIN_BASED_VMX_PREEMPTION_TIMER
;
1295 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1297 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1300 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1302 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1303 vmx_xsaves_supported();
1306 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1308 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1311 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1313 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1316 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1318 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1321 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1323 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1326 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1328 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1331 static inline bool is_exception(u32 intr_info
)
1333 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1334 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1337 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1339 unsigned long exit_qualification
);
1340 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1341 struct vmcs12
*vmcs12
,
1342 u32 reason
, unsigned long qualification
);
1344 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1348 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1349 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1354 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1360 } operand
= { vpid
, 0, gva
};
1362 asm volatile (__ex(ASM_VMX_INVVPID
)
1363 /* CF==1 or ZF==1 --> rc = -1 */
1364 "; ja 1f ; ud2 ; 1:"
1365 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1368 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1372 } operand
= {eptp
, gpa
};
1374 asm volatile (__ex(ASM_VMX_INVEPT
)
1375 /* CF==1 or ZF==1 --> rc = -1 */
1376 "; ja 1f ; ud2 ; 1:\n"
1377 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1380 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1384 i
= __find_msr_index(vmx
, msr
);
1386 return &vmx
->guest_msrs
[i
];
1390 static void vmcs_clear(struct vmcs
*vmcs
)
1392 u64 phys_addr
= __pa(vmcs
);
1395 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1396 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1399 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1403 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1405 vmcs_clear(loaded_vmcs
->vmcs
);
1406 loaded_vmcs
->cpu
= -1;
1407 loaded_vmcs
->launched
= 0;
1410 static void vmcs_load(struct vmcs
*vmcs
)
1412 u64 phys_addr
= __pa(vmcs
);
1415 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1416 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1419 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1423 #ifdef CONFIG_KEXEC_CORE
1425 * This bitmap is used to indicate whether the vmclear
1426 * operation is enabled on all cpus. All disabled by
1429 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1431 static inline void crash_enable_local_vmclear(int cpu
)
1433 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1436 static inline void crash_disable_local_vmclear(int cpu
)
1438 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1441 static inline int crash_local_vmclear_enabled(int cpu
)
1443 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1446 static void crash_vmclear_local_loaded_vmcss(void)
1448 int cpu
= raw_smp_processor_id();
1449 struct loaded_vmcs
*v
;
1451 if (!crash_local_vmclear_enabled(cpu
))
1454 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1455 loaded_vmcss_on_cpu_link
)
1456 vmcs_clear(v
->vmcs
);
1459 static inline void crash_enable_local_vmclear(int cpu
) { }
1460 static inline void crash_disable_local_vmclear(int cpu
) { }
1461 #endif /* CONFIG_KEXEC_CORE */
1463 static void __loaded_vmcs_clear(void *arg
)
1465 struct loaded_vmcs
*loaded_vmcs
= arg
;
1466 int cpu
= raw_smp_processor_id();
1468 if (loaded_vmcs
->cpu
!= cpu
)
1469 return; /* vcpu migration can race with cpu offline */
1470 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1471 per_cpu(current_vmcs
, cpu
) = NULL
;
1472 crash_disable_local_vmclear(cpu
);
1473 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1476 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1477 * is before setting loaded_vmcs->vcpu to -1 which is done in
1478 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1479 * then adds the vmcs into percpu list before it is deleted.
1483 loaded_vmcs_init(loaded_vmcs
);
1484 crash_enable_local_vmclear(cpu
);
1487 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1489 int cpu
= loaded_vmcs
->cpu
;
1492 smp_call_function_single(cpu
,
1493 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1496 static inline void vpid_sync_vcpu_single(int vpid
)
1501 if (cpu_has_vmx_invvpid_single())
1502 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1505 static inline void vpid_sync_vcpu_global(void)
1507 if (cpu_has_vmx_invvpid_global())
1508 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1511 static inline void vpid_sync_context(int vpid
)
1513 if (cpu_has_vmx_invvpid_single())
1514 vpid_sync_vcpu_single(vpid
);
1516 vpid_sync_vcpu_global();
1519 static inline void ept_sync_global(void)
1521 if (cpu_has_vmx_invept_global())
1522 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1525 static inline void ept_sync_context(u64 eptp
)
1528 if (cpu_has_vmx_invept_context())
1529 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1535 static __always_inline
void vmcs_check16(unsigned long field
)
1537 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1538 "16-bit accessor invalid for 64-bit field");
1539 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1540 "16-bit accessor invalid for 64-bit high field");
1541 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1542 "16-bit accessor invalid for 32-bit high field");
1543 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1544 "16-bit accessor invalid for natural width field");
1547 static __always_inline
void vmcs_check32(unsigned long field
)
1549 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1550 "32-bit accessor invalid for 16-bit field");
1551 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1552 "32-bit accessor invalid for natural width field");
1555 static __always_inline
void vmcs_check64(unsigned long field
)
1557 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1558 "64-bit accessor invalid for 16-bit field");
1559 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1560 "64-bit accessor invalid for 64-bit high field");
1561 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1562 "64-bit accessor invalid for 32-bit field");
1563 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1564 "64-bit accessor invalid for natural width field");
1567 static __always_inline
void vmcs_checkl(unsigned long field
)
1569 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1570 "Natural width accessor invalid for 16-bit field");
1571 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1572 "Natural width accessor invalid for 64-bit field");
1573 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1574 "Natural width accessor invalid for 64-bit high field");
1575 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1576 "Natural width accessor invalid for 32-bit field");
1579 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1581 unsigned long value
;
1583 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1584 : "=a"(value
) : "d"(field
) : "cc");
1588 static __always_inline u16
vmcs_read16(unsigned long field
)
1590 vmcs_check16(field
);
1591 return __vmcs_readl(field
);
1594 static __always_inline u32
vmcs_read32(unsigned long field
)
1596 vmcs_check32(field
);
1597 return __vmcs_readl(field
);
1600 static __always_inline u64
vmcs_read64(unsigned long field
)
1602 vmcs_check64(field
);
1603 #ifdef CONFIG_X86_64
1604 return __vmcs_readl(field
);
1606 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1610 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1613 return __vmcs_readl(field
);
1616 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1618 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1619 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1623 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1627 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1628 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1629 if (unlikely(error
))
1630 vmwrite_error(field
, value
);
1633 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1635 vmcs_check16(field
);
1636 __vmcs_writel(field
, value
);
1639 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1641 vmcs_check32(field
);
1642 __vmcs_writel(field
, value
);
1645 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1647 vmcs_check64(field
);
1648 __vmcs_writel(field
, value
);
1649 #ifndef CONFIG_X86_64
1651 __vmcs_writel(field
+1, value
>> 32);
1655 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1658 __vmcs_writel(field
, value
);
1661 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1663 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1664 "vmcs_clear_bits does not support 64-bit fields");
1665 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1668 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1670 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1671 "vmcs_set_bits does not support 64-bit fields");
1672 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1675 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1677 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1680 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1682 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1683 vmx
->vm_entry_controls_shadow
= val
;
1686 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1688 if (vmx
->vm_entry_controls_shadow
!= val
)
1689 vm_entry_controls_init(vmx
, val
);
1692 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1694 return vmx
->vm_entry_controls_shadow
;
1698 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1700 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1703 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1705 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1708 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1710 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1713 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1715 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1716 vmx
->vm_exit_controls_shadow
= val
;
1719 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1721 if (vmx
->vm_exit_controls_shadow
!= val
)
1722 vm_exit_controls_init(vmx
, val
);
1725 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1727 return vmx
->vm_exit_controls_shadow
;
1731 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1733 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1736 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1738 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1741 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1743 vmx
->segment_cache
.bitmask
= 0;
1746 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1750 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1752 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1753 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1754 vmx
->segment_cache
.bitmask
= 0;
1756 ret
= vmx
->segment_cache
.bitmask
& mask
;
1757 vmx
->segment_cache
.bitmask
|= mask
;
1761 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1763 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1765 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1766 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1770 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1772 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1774 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1775 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1779 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1781 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1783 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1784 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1788 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1790 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1792 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1793 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1797 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1801 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1802 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1803 if ((vcpu
->guest_debug
&
1804 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1805 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1806 eb
|= 1u << BP_VECTOR
;
1807 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1810 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1811 if (vcpu
->fpu_active
)
1812 eb
&= ~(1u << NM_VECTOR
);
1814 /* When we are running a nested L2 guest and L1 specified for it a
1815 * certain exception bitmap, we must trap the same exceptions and pass
1816 * them to L1. When running L2, we will only handle the exceptions
1817 * specified above if L1 did not want them.
1819 if (is_guest_mode(vcpu
))
1820 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1822 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1825 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1826 unsigned long entry
, unsigned long exit
)
1828 vm_entry_controls_clearbit(vmx
, entry
);
1829 vm_exit_controls_clearbit(vmx
, exit
);
1832 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1835 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1839 if (cpu_has_load_ia32_efer
) {
1840 clear_atomic_switch_msr_special(vmx
,
1841 VM_ENTRY_LOAD_IA32_EFER
,
1842 VM_EXIT_LOAD_IA32_EFER
);
1846 case MSR_CORE_PERF_GLOBAL_CTRL
:
1847 if (cpu_has_load_perf_global_ctrl
) {
1848 clear_atomic_switch_msr_special(vmx
,
1849 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1856 for (i
= 0; i
< m
->nr
; ++i
)
1857 if (m
->guest
[i
].index
== msr
)
1863 m
->guest
[i
] = m
->guest
[m
->nr
];
1864 m
->host
[i
] = m
->host
[m
->nr
];
1865 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1866 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1869 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1870 unsigned long entry
, unsigned long exit
,
1871 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1872 u64 guest_val
, u64 host_val
)
1874 vmcs_write64(guest_val_vmcs
, guest_val
);
1875 vmcs_write64(host_val_vmcs
, host_val
);
1876 vm_entry_controls_setbit(vmx
, entry
);
1877 vm_exit_controls_setbit(vmx
, exit
);
1880 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1881 u64 guest_val
, u64 host_val
)
1884 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1888 if (cpu_has_load_ia32_efer
) {
1889 add_atomic_switch_msr_special(vmx
,
1890 VM_ENTRY_LOAD_IA32_EFER
,
1891 VM_EXIT_LOAD_IA32_EFER
,
1894 guest_val
, host_val
);
1898 case MSR_CORE_PERF_GLOBAL_CTRL
:
1899 if (cpu_has_load_perf_global_ctrl
) {
1900 add_atomic_switch_msr_special(vmx
,
1901 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1902 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1903 GUEST_IA32_PERF_GLOBAL_CTRL
,
1904 HOST_IA32_PERF_GLOBAL_CTRL
,
1905 guest_val
, host_val
);
1909 case MSR_IA32_PEBS_ENABLE
:
1910 /* PEBS needs a quiescent period after being disabled (to write
1911 * a record). Disabling PEBS through VMX MSR swapping doesn't
1912 * provide that period, so a CPU could write host's record into
1915 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1918 for (i
= 0; i
< m
->nr
; ++i
)
1919 if (m
->guest
[i
].index
== msr
)
1922 if (i
== NR_AUTOLOAD_MSRS
) {
1923 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1924 "Can't add msr %x\n", msr
);
1926 } else if (i
== m
->nr
) {
1928 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1929 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1932 m
->guest
[i
].index
= msr
;
1933 m
->guest
[i
].value
= guest_val
;
1934 m
->host
[i
].index
= msr
;
1935 m
->host
[i
].value
= host_val
;
1938 static void reload_tss(void)
1941 * VT restores TR but not its size. Useless.
1943 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1944 struct desc_struct
*descs
;
1946 descs
= (void *)gdt
->address
;
1947 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1951 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1953 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1954 u64 ignore_bits
= 0;
1958 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1959 * host CPUID is more efficient than testing guest CPUID
1960 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1962 if (boot_cpu_has(X86_FEATURE_SMEP
))
1963 guest_efer
|= EFER_NX
;
1964 else if (!(guest_efer
& EFER_NX
))
1965 ignore_bits
|= EFER_NX
;
1969 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1971 ignore_bits
|= EFER_SCE
;
1972 #ifdef CONFIG_X86_64
1973 ignore_bits
|= EFER_LMA
| EFER_LME
;
1974 /* SCE is meaningful only in long mode on Intel */
1975 if (guest_efer
& EFER_LMA
)
1976 ignore_bits
&= ~(u64
)EFER_SCE
;
1979 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1982 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1983 * On CPUs that support "load IA32_EFER", always switch EFER
1984 * atomically, since it's faster than switching it manually.
1986 if (cpu_has_load_ia32_efer
||
1987 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1988 if (!(guest_efer
& EFER_LMA
))
1989 guest_efer
&= ~EFER_LME
;
1990 if (guest_efer
!= host_efer
)
1991 add_atomic_switch_msr(vmx
, MSR_EFER
,
1992 guest_efer
, host_efer
);
1995 guest_efer
&= ~ignore_bits
;
1996 guest_efer
|= host_efer
& ignore_bits
;
1998 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1999 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2005 static unsigned long segment_base(u16 selector
)
2007 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2008 struct desc_struct
*d
;
2009 unsigned long table_base
;
2012 if (!(selector
& ~3))
2015 table_base
= gdt
->address
;
2017 if (selector
& 4) { /* from ldt */
2018 u16 ldt_selector
= kvm_read_ldt();
2020 if (!(ldt_selector
& ~3))
2023 table_base
= segment_base(ldt_selector
);
2025 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
2026 v
= get_desc_base(d
);
2027 #ifdef CONFIG_X86_64
2028 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
2029 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
2034 static inline unsigned long kvm_read_tr_base(void)
2037 asm("str %0" : "=g"(tr
));
2038 return segment_base(tr
);
2041 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2043 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2046 if (vmx
->host_state
.loaded
)
2049 vmx
->host_state
.loaded
= 1;
2051 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2052 * allow segment selectors with cpl > 0 or ti == 1.
2054 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2055 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2056 savesegment(fs
, vmx
->host_state
.fs_sel
);
2057 if (!(vmx
->host_state
.fs_sel
& 7)) {
2058 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2059 vmx
->host_state
.fs_reload_needed
= 0;
2061 vmcs_write16(HOST_FS_SELECTOR
, 0);
2062 vmx
->host_state
.fs_reload_needed
= 1;
2064 savesegment(gs
, vmx
->host_state
.gs_sel
);
2065 if (!(vmx
->host_state
.gs_sel
& 7))
2066 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2068 vmcs_write16(HOST_GS_SELECTOR
, 0);
2069 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2072 #ifdef CONFIG_X86_64
2073 savesegment(ds
, vmx
->host_state
.ds_sel
);
2074 savesegment(es
, vmx
->host_state
.es_sel
);
2077 #ifdef CONFIG_X86_64
2078 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2079 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2081 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2082 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2085 #ifdef CONFIG_X86_64
2086 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2087 if (is_long_mode(&vmx
->vcpu
))
2088 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2090 if (boot_cpu_has(X86_FEATURE_MPX
))
2091 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2092 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2093 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2094 vmx
->guest_msrs
[i
].data
,
2095 vmx
->guest_msrs
[i
].mask
);
2098 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2100 if (!vmx
->host_state
.loaded
)
2103 ++vmx
->vcpu
.stat
.host_state_reload
;
2104 vmx
->host_state
.loaded
= 0;
2105 #ifdef CONFIG_X86_64
2106 if (is_long_mode(&vmx
->vcpu
))
2107 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2109 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2110 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2111 #ifdef CONFIG_X86_64
2112 load_gs_index(vmx
->host_state
.gs_sel
);
2114 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2117 if (vmx
->host_state
.fs_reload_needed
)
2118 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2119 #ifdef CONFIG_X86_64
2120 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2121 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2122 loadsegment(es
, vmx
->host_state
.es_sel
);
2126 #ifdef CONFIG_X86_64
2127 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2129 if (vmx
->host_state
.msr_host_bndcfgs
)
2130 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2132 * If the FPU is not active (through the host task or
2133 * the guest vcpu), then restore the cr0.TS bit.
2135 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2137 load_gdt(this_cpu_ptr(&host_gdt
));
2140 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2143 __vmx_load_host_state(vmx
);
2147 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2149 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2150 struct pi_desc old
, new;
2153 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2154 !irq_remapping_cap(IRQ_POSTING_CAP
))
2158 old
.control
= new.control
= pi_desc
->control
;
2161 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2162 * are two possible cases:
2163 * 1. After running 'pre_block', context switch
2164 * happened. For this case, 'sn' was set in
2165 * vmx_vcpu_put(), so we need to clear it here.
2166 * 2. After running 'pre_block', we were blocked,
2167 * and woken up by some other guy. For this case,
2168 * we don't need to do anything, 'pi_post_block'
2169 * will do everything for us. However, we cannot
2170 * check whether it is case #1 or case #2 here
2171 * (maybe, not needed), so we also clear sn here,
2172 * I think it is not a big deal.
2174 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2175 if (vcpu
->cpu
!= cpu
) {
2176 dest
= cpu_physical_id(cpu
);
2178 if (x2apic_enabled())
2181 new.ndst
= (dest
<< 8) & 0xFF00;
2184 /* set 'NV' to 'notification vector' */
2185 new.nv
= POSTED_INTR_VECTOR
;
2188 /* Allow posting non-urgent interrupts */
2190 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2191 new.control
) != old
.control
);
2195 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2196 * vcpu mutex is already taken.
2198 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2200 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2201 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2204 kvm_cpu_vmxon(phys_addr
);
2205 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2206 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2208 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2209 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2210 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2213 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2214 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2215 unsigned long sysenter_esp
;
2217 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2218 local_irq_disable();
2219 crash_disable_local_vmclear(cpu
);
2222 * Read loaded_vmcs->cpu should be before fetching
2223 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2224 * See the comments in __loaded_vmcs_clear().
2228 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2229 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2230 crash_enable_local_vmclear(cpu
);
2234 * Linux uses per-cpu TSS and GDT, so set these when switching
2237 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2238 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2240 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2241 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2243 vmx
->loaded_vmcs
->cpu
= cpu
;
2246 /* Setup TSC multiplier */
2247 if (kvm_has_tsc_control
&&
2248 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
) {
2249 vmx
->current_tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2250 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2253 vmx_vcpu_pi_load(vcpu
, cpu
);
2254 vmx
->host_pkru
= read_pkru();
2257 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2259 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2261 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2262 !irq_remapping_cap(IRQ_POSTING_CAP
))
2265 /* Set SN when the vCPU is preempted */
2266 if (vcpu
->preempted
)
2270 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2272 vmx_vcpu_pi_put(vcpu
);
2274 __vmx_load_host_state(to_vmx(vcpu
));
2275 if (!vmm_exclusive
) {
2276 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2282 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2286 if (vcpu
->fpu_active
)
2288 vcpu
->fpu_active
= 1;
2289 cr0
= vmcs_readl(GUEST_CR0
);
2290 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2291 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2292 vmcs_writel(GUEST_CR0
, cr0
);
2293 update_exception_bitmap(vcpu
);
2294 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2295 if (is_guest_mode(vcpu
))
2296 vcpu
->arch
.cr0_guest_owned_bits
&=
2297 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2298 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2301 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2304 * Return the cr0 value that a nested guest would read. This is a combination
2305 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2306 * its hypervisor (cr0_read_shadow).
2308 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2310 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2311 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2313 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2315 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2316 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2319 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2321 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2322 * set this *before* calling this function.
2324 vmx_decache_cr0_guest_bits(vcpu
);
2325 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2326 update_exception_bitmap(vcpu
);
2327 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2328 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2329 if (is_guest_mode(vcpu
)) {
2331 * L1's specified read shadow might not contain the TS bit,
2332 * so now that we turned on shadowing of this bit, we need to
2333 * set this bit of the shadow. Like in nested_vmx_run we need
2334 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2335 * up-to-date here because we just decached cr0.TS (and we'll
2336 * only update vmcs12->guest_cr0 on nested exit).
2338 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2339 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2340 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2341 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2343 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2346 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2348 unsigned long rflags
, save_rflags
;
2350 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2351 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2352 rflags
= vmcs_readl(GUEST_RFLAGS
);
2353 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2354 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2355 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2356 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2358 to_vmx(vcpu
)->rflags
= rflags
;
2360 return to_vmx(vcpu
)->rflags
;
2363 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2365 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2366 to_vmx(vcpu
)->rflags
= rflags
;
2367 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2368 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2369 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2371 vmcs_writel(GUEST_RFLAGS
, rflags
);
2374 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2376 return to_vmx(vcpu
)->guest_pkru
;
2379 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2381 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2384 if (interruptibility
& GUEST_INTR_STATE_STI
)
2385 ret
|= KVM_X86_SHADOW_INT_STI
;
2386 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2387 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2392 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2394 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2395 u32 interruptibility
= interruptibility_old
;
2397 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2399 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2400 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2401 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2402 interruptibility
|= GUEST_INTR_STATE_STI
;
2404 if ((interruptibility
!= interruptibility_old
))
2405 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2408 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2412 rip
= kvm_rip_read(vcpu
);
2413 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2414 kvm_rip_write(vcpu
, rip
);
2416 /* skipping an emulated instruction also counts */
2417 vmx_set_interrupt_shadow(vcpu
, 0);
2421 * KVM wants to inject page-faults which it got to the guest. This function
2422 * checks whether in a nested guest, we need to inject them to L1 or L2.
2424 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2426 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2428 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2431 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2432 vmcs_read32(VM_EXIT_INTR_INFO
),
2433 vmcs_readl(EXIT_QUALIFICATION
));
2437 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2438 bool has_error_code
, u32 error_code
,
2441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2442 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2444 if (!reinject
&& is_guest_mode(vcpu
) &&
2445 nested_vmx_check_exception(vcpu
, nr
))
2448 if (has_error_code
) {
2449 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2450 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2453 if (vmx
->rmode
.vm86_active
) {
2455 if (kvm_exception_is_soft(nr
))
2456 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2457 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2458 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2462 if (kvm_exception_is_soft(nr
)) {
2463 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2464 vmx
->vcpu
.arch
.event_exit_inst_len
);
2465 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2467 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2469 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2472 static bool vmx_rdtscp_supported(void)
2474 return cpu_has_vmx_rdtscp();
2477 static bool vmx_invpcid_supported(void)
2479 return cpu_has_vmx_invpcid() && enable_ept
;
2483 * Swap MSR entry in host/guest MSR entry array.
2485 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2487 struct shared_msr_entry tmp
;
2489 tmp
= vmx
->guest_msrs
[to
];
2490 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2491 vmx
->guest_msrs
[from
] = tmp
;
2494 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2496 unsigned long *msr_bitmap
;
2498 if (is_guest_mode(vcpu
))
2499 msr_bitmap
= vmx_msr_bitmap_nested
;
2500 else if (cpu_has_secondary_exec_ctrls() &&
2501 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2502 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2503 if (is_long_mode(vcpu
))
2504 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2506 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2508 if (is_long_mode(vcpu
))
2509 msr_bitmap
= vmx_msr_bitmap_longmode
;
2511 msr_bitmap
= vmx_msr_bitmap_legacy
;
2514 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2518 * Set up the vmcs to automatically save and restore system
2519 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2520 * mode, as fiddling with msrs is very expensive.
2522 static void setup_msrs(struct vcpu_vmx
*vmx
)
2524 int save_nmsrs
, index
;
2527 #ifdef CONFIG_X86_64
2528 if (is_long_mode(&vmx
->vcpu
)) {
2529 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2531 move_msr_up(vmx
, index
, save_nmsrs
++);
2532 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2534 move_msr_up(vmx
, index
, save_nmsrs
++);
2535 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2537 move_msr_up(vmx
, index
, save_nmsrs
++);
2538 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2539 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2540 move_msr_up(vmx
, index
, save_nmsrs
++);
2542 * MSR_STAR is only needed on long mode guests, and only
2543 * if efer.sce is enabled.
2545 index
= __find_msr_index(vmx
, MSR_STAR
);
2546 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2547 move_msr_up(vmx
, index
, save_nmsrs
++);
2550 index
= __find_msr_index(vmx
, MSR_EFER
);
2551 if (index
>= 0 && update_transition_efer(vmx
, index
))
2552 move_msr_up(vmx
, index
, save_nmsrs
++);
2554 vmx
->save_nmsrs
= save_nmsrs
;
2556 if (cpu_has_vmx_msr_bitmap())
2557 vmx_set_msr_bitmap(&vmx
->vcpu
);
2561 * reads and returns guest's timestamp counter "register"
2562 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2563 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2565 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2567 u64 host_tsc
, tsc_offset
;
2570 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2571 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2575 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2576 * counter, even if a nested guest (L2) is currently running.
2578 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2582 tsc_offset
= is_guest_mode(vcpu
) ?
2583 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2584 vmcs_read64(TSC_OFFSET
);
2585 return host_tsc
+ tsc_offset
;
2588 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2590 return vmcs_read64(TSC_OFFSET
);
2594 * writes 'offset' into guest's timestamp counter offset register
2596 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2598 if (is_guest_mode(vcpu
)) {
2600 * We're here if L1 chose not to trap WRMSR to TSC. According
2601 * to the spec, this should set L1's TSC; The offset that L1
2602 * set for L2 remains unchanged, and still needs to be added
2603 * to the newly set TSC to get L2's TSC.
2605 struct vmcs12
*vmcs12
;
2606 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2607 /* recalculate vmcs02.TSC_OFFSET: */
2608 vmcs12
= get_vmcs12(vcpu
);
2609 vmcs_write64(TSC_OFFSET
, offset
+
2610 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2611 vmcs12
->tsc_offset
: 0));
2613 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2614 vmcs_read64(TSC_OFFSET
), offset
);
2615 vmcs_write64(TSC_OFFSET
, offset
);
2619 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2621 u64 offset
= vmcs_read64(TSC_OFFSET
);
2623 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2624 if (is_guest_mode(vcpu
)) {
2625 /* Even when running L2, the adjustment needs to apply to L1 */
2626 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2628 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2629 offset
+ adjustment
);
2632 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2634 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2635 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2639 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2640 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2641 * all guests if the "nested" module option is off, and can also be disabled
2642 * for a single guest by disabling its VMX cpuid bit.
2644 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2646 return nested
&& guest_cpuid_has_vmx(vcpu
);
2650 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2651 * returned for the various VMX controls MSRs when nested VMX is enabled.
2652 * The same values should also be used to verify that vmcs12 control fields are
2653 * valid during nested entry from L1 to L2.
2654 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2655 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2656 * bit in the high half is on if the corresponding bit in the control field
2657 * may be on. See also vmx_control_verify().
2659 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2662 * Note that as a general rule, the high half of the MSRs (bits in
2663 * the control fields which may be 1) should be initialized by the
2664 * intersection of the underlying hardware's MSR (i.e., features which
2665 * can be supported) and the list of features we want to expose -
2666 * because they are known to be properly supported in our code.
2667 * Also, usually, the low half of the MSRs (bits which must be 1) can
2668 * be set to 0, meaning that L1 may turn off any of these bits. The
2669 * reason is that if one of these bits is necessary, it will appear
2670 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2671 * fields of vmcs01 and vmcs02, will turn these bits off - and
2672 * nested_vmx_exit_handled() will not pass related exits to L1.
2673 * These rules have exceptions below.
2676 /* pin-based controls */
2677 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2678 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2679 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2680 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2681 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2682 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2683 PIN_BASED_EXT_INTR_MASK
|
2684 PIN_BASED_NMI_EXITING
|
2685 PIN_BASED_VIRTUAL_NMIS
;
2686 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2687 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2688 PIN_BASED_VMX_PREEMPTION_TIMER
;
2689 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2690 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2691 PIN_BASED_POSTED_INTR
;
2694 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2695 vmx
->nested
.nested_vmx_exit_ctls_low
,
2696 vmx
->nested
.nested_vmx_exit_ctls_high
);
2697 vmx
->nested
.nested_vmx_exit_ctls_low
=
2698 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2700 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2701 #ifdef CONFIG_X86_64
2702 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2704 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2705 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2706 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2707 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2708 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2710 if (kvm_mpx_supported())
2711 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2713 /* We support free control of debug control saving. */
2714 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2715 vmx
->nested
.nested_vmx_exit_ctls_low
&
2716 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2718 /* entry controls */
2719 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2720 vmx
->nested
.nested_vmx_entry_ctls_low
,
2721 vmx
->nested
.nested_vmx_entry_ctls_high
);
2722 vmx
->nested
.nested_vmx_entry_ctls_low
=
2723 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2724 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2725 #ifdef CONFIG_X86_64
2726 VM_ENTRY_IA32E_MODE
|
2728 VM_ENTRY_LOAD_IA32_PAT
;
2729 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2730 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2731 if (kvm_mpx_supported())
2732 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2734 /* We support free control of debug control loading. */
2735 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2736 vmx
->nested
.nested_vmx_entry_ctls_low
&
2737 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2739 /* cpu-based controls */
2740 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2741 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2742 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2743 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2744 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2745 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2746 CPU_BASED_VIRTUAL_INTR_PENDING
|
2747 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2748 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2749 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2750 CPU_BASED_CR3_STORE_EXITING
|
2751 #ifdef CONFIG_X86_64
2752 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2754 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2755 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2756 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2757 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2758 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2760 * We can allow some features even when not supported by the
2761 * hardware. For example, L1 can specify an MSR bitmap - and we
2762 * can use it to avoid exits to L1 - even when L0 runs L2
2763 * without MSR bitmaps.
2765 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2766 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2767 CPU_BASED_USE_MSR_BITMAPS
;
2769 /* We support free control of CR3 access interception. */
2770 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2771 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2772 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2774 /* secondary cpu-based controls */
2775 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2776 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2777 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2778 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2779 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2780 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2781 SECONDARY_EXEC_RDTSCP
|
2782 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2783 SECONDARY_EXEC_ENABLE_VPID
|
2784 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2785 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2786 SECONDARY_EXEC_WBINVD_EXITING
|
2787 SECONDARY_EXEC_XSAVES
|
2788 SECONDARY_EXEC_PCOMMIT
;
2791 /* nested EPT: emulate EPT also to L1 */
2792 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2793 SECONDARY_EXEC_ENABLE_EPT
;
2794 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2795 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2797 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2799 * For nested guests, we don't do anything specific
2800 * for single context invalidation. Hence, only advertise
2801 * support for global context invalidation.
2803 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2805 vmx
->nested
.nested_vmx_ept_caps
= 0;
2808 * Old versions of KVM use the single-context version without
2809 * checking for support, so declare that it is supported even
2810 * though it is treated as global context. The alternative is
2811 * not failing the single-context invvpid, and it is worse.
2814 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2815 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
|
2816 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2818 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2820 if (enable_unrestricted_guest
)
2821 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2822 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2824 /* miscellaneous data */
2825 rdmsr(MSR_IA32_VMX_MISC
,
2826 vmx
->nested
.nested_vmx_misc_low
,
2827 vmx
->nested
.nested_vmx_misc_high
);
2828 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2829 vmx
->nested
.nested_vmx_misc_low
|=
2830 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2831 VMX_MISC_ACTIVITY_HLT
;
2832 vmx
->nested
.nested_vmx_misc_high
= 0;
2835 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2838 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2840 return ((control
& high
) | low
) == control
;
2843 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2845 return low
| ((u64
)high
<< 32);
2848 /* Returns 0 on success, non-0 otherwise. */
2849 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2851 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2853 switch (msr_index
) {
2854 case MSR_IA32_VMX_BASIC
:
2856 * This MSR reports some information about VMX support. We
2857 * should return information about the VMX we emulate for the
2858 * guest, and the VMCS structure we give it - not about the
2859 * VMX support of the underlying hardware.
2861 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2862 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2863 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2865 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2866 case MSR_IA32_VMX_PINBASED_CTLS
:
2867 *pdata
= vmx_control_msr(
2868 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2869 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2871 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2872 *pdata
= vmx_control_msr(
2873 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2874 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2876 case MSR_IA32_VMX_PROCBASED_CTLS
:
2877 *pdata
= vmx_control_msr(
2878 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2879 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2881 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2882 *pdata
= vmx_control_msr(
2883 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2884 vmx
->nested
.nested_vmx_exit_ctls_high
);
2886 case MSR_IA32_VMX_EXIT_CTLS
:
2887 *pdata
= vmx_control_msr(
2888 vmx
->nested
.nested_vmx_exit_ctls_low
,
2889 vmx
->nested
.nested_vmx_exit_ctls_high
);
2891 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2892 *pdata
= vmx_control_msr(
2893 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2894 vmx
->nested
.nested_vmx_entry_ctls_high
);
2896 case MSR_IA32_VMX_ENTRY_CTLS
:
2897 *pdata
= vmx_control_msr(
2898 vmx
->nested
.nested_vmx_entry_ctls_low
,
2899 vmx
->nested
.nested_vmx_entry_ctls_high
);
2901 case MSR_IA32_VMX_MISC
:
2902 *pdata
= vmx_control_msr(
2903 vmx
->nested
.nested_vmx_misc_low
,
2904 vmx
->nested
.nested_vmx_misc_high
);
2907 * These MSRs specify bits which the guest must keep fixed (on or off)
2908 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2909 * We picked the standard core2 setting.
2911 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2912 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2913 case MSR_IA32_VMX_CR0_FIXED0
:
2914 *pdata
= VMXON_CR0_ALWAYSON
;
2916 case MSR_IA32_VMX_CR0_FIXED1
:
2919 case MSR_IA32_VMX_CR4_FIXED0
:
2920 *pdata
= VMXON_CR4_ALWAYSON
;
2922 case MSR_IA32_VMX_CR4_FIXED1
:
2925 case MSR_IA32_VMX_VMCS_ENUM
:
2926 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2928 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2929 *pdata
= vmx_control_msr(
2930 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2931 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2933 case MSR_IA32_VMX_EPT_VPID_CAP
:
2934 /* Currently, no nested vpid support */
2935 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2936 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2945 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
2948 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
2950 return !(val
& ~valid_bits
);
2954 * Reads an msr value (of 'msr_index') into 'pdata'.
2955 * Returns 0 on success, non-0 otherwise.
2956 * Assumes vcpu_load() was already called.
2958 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2960 struct shared_msr_entry
*msr
;
2962 switch (msr_info
->index
) {
2963 #ifdef CONFIG_X86_64
2965 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2968 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2970 case MSR_KERNEL_GS_BASE
:
2971 vmx_load_host_state(to_vmx(vcpu
));
2972 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2976 return kvm_get_msr_common(vcpu
, msr_info
);
2978 msr_info
->data
= guest_read_tsc(vcpu
);
2980 case MSR_IA32_SYSENTER_CS
:
2981 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2983 case MSR_IA32_SYSENTER_EIP
:
2984 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2986 case MSR_IA32_SYSENTER_ESP
:
2987 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2989 case MSR_IA32_BNDCFGS
:
2990 if (!kvm_mpx_supported())
2992 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2994 case MSR_IA32_MCG_EXT_CTL
:
2995 if (!msr_info
->host_initiated
&&
2996 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
2997 FEATURE_CONTROL_LMCE
))
2999 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3001 case MSR_IA32_FEATURE_CONTROL
:
3002 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3004 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3005 if (!nested_vmx_allowed(vcpu
))
3007 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3009 if (!vmx_xsaves_supported())
3011 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3014 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3016 /* Otherwise falls through */
3018 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3020 msr_info
->data
= msr
->data
;
3023 return kvm_get_msr_common(vcpu
, msr_info
);
3029 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3032 * Writes msr value into into the appropriate "register".
3033 * Returns 0 on success, non-0 otherwise.
3034 * Assumes vcpu_load() was already called.
3036 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3039 struct shared_msr_entry
*msr
;
3041 u32 msr_index
= msr_info
->index
;
3042 u64 data
= msr_info
->data
;
3044 switch (msr_index
) {
3046 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3048 #ifdef CONFIG_X86_64
3050 vmx_segment_cache_clear(vmx
);
3051 vmcs_writel(GUEST_FS_BASE
, data
);
3054 vmx_segment_cache_clear(vmx
);
3055 vmcs_writel(GUEST_GS_BASE
, data
);
3057 case MSR_KERNEL_GS_BASE
:
3058 vmx_load_host_state(vmx
);
3059 vmx
->msr_guest_kernel_gs_base
= data
;
3062 case MSR_IA32_SYSENTER_CS
:
3063 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3065 case MSR_IA32_SYSENTER_EIP
:
3066 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3068 case MSR_IA32_SYSENTER_ESP
:
3069 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3071 case MSR_IA32_BNDCFGS
:
3072 if (!kvm_mpx_supported())
3074 vmcs_write64(GUEST_BNDCFGS
, data
);
3077 kvm_write_tsc(vcpu
, msr_info
);
3079 case MSR_IA32_CR_PAT
:
3080 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3081 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3083 vmcs_write64(GUEST_IA32_PAT
, data
);
3084 vcpu
->arch
.pat
= data
;
3087 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3089 case MSR_IA32_TSC_ADJUST
:
3090 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3092 case MSR_IA32_MCG_EXT_CTL
:
3093 if ((!msr_info
->host_initiated
&&
3094 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3095 FEATURE_CONTROL_LMCE
)) ||
3096 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3098 vcpu
->arch
.mcg_ext_ctl
= data
;
3100 case MSR_IA32_FEATURE_CONTROL
:
3101 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3102 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3103 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3105 vmx
->msr_ia32_feature_control
= data
;
3106 if (msr_info
->host_initiated
&& data
== 0)
3107 vmx_leave_nested(vcpu
);
3109 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3110 return 1; /* they are read-only */
3112 if (!vmx_xsaves_supported())
3115 * The only supported bit as of Skylake is bit 8, but
3116 * it is not supported on KVM.
3120 vcpu
->arch
.ia32_xss
= data
;
3121 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3122 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3123 vcpu
->arch
.ia32_xss
, host_xss
);
3125 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3128 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3130 /* Check reserved bit, higher 32 bits should be zero */
3131 if ((data
>> 32) != 0)
3133 /* Otherwise falls through */
3135 msr
= find_msr_entry(vmx
, msr_index
);
3137 u64 old_msr_data
= msr
->data
;
3139 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3141 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3145 msr
->data
= old_msr_data
;
3149 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3155 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3157 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3160 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3163 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3165 case VCPU_EXREG_PDPTR
:
3167 ept_save_pdptrs(vcpu
);
3174 static __init
int cpu_has_kvm_support(void)
3176 return cpu_has_vmx();
3179 static __init
int vmx_disabled_by_bios(void)
3183 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3184 if (msr
& FEATURE_CONTROL_LOCKED
) {
3185 /* launched w/ TXT and VMX disabled */
3186 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3189 /* launched w/o TXT and VMX only enabled w/ TXT */
3190 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3191 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3192 && !tboot_enabled()) {
3193 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3194 "activate TXT before enabling KVM\n");
3197 /* launched w/o TXT and VMX disabled */
3198 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3199 && !tboot_enabled())
3206 static void kvm_cpu_vmxon(u64 addr
)
3208 intel_pt_handle_vmx(1);
3210 asm volatile (ASM_VMX_VMXON_RAX
3211 : : "a"(&addr
), "m"(addr
)
3215 static int hardware_enable(void)
3217 int cpu
= raw_smp_processor_id();
3218 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3221 if (cr4_read_shadow() & X86_CR4_VMXE
)
3224 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3225 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3226 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3229 * Now we can enable the vmclear operation in kdump
3230 * since the loaded_vmcss_on_cpu list on this cpu
3231 * has been initialized.
3233 * Though the cpu is not in VMX operation now, there
3234 * is no problem to enable the vmclear operation
3235 * for the loaded_vmcss_on_cpu list is empty!
3237 crash_enable_local_vmclear(cpu
);
3239 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3241 test_bits
= FEATURE_CONTROL_LOCKED
;
3242 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3243 if (tboot_enabled())
3244 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3246 if ((old
& test_bits
) != test_bits
) {
3247 /* enable and lock */
3248 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3250 cr4_set_bits(X86_CR4_VMXE
);
3252 if (vmm_exclusive
) {
3253 kvm_cpu_vmxon(phys_addr
);
3257 native_store_gdt(this_cpu_ptr(&host_gdt
));
3262 static void vmclear_local_loaded_vmcss(void)
3264 int cpu
= raw_smp_processor_id();
3265 struct loaded_vmcs
*v
, *n
;
3267 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3268 loaded_vmcss_on_cpu_link
)
3269 __loaded_vmcs_clear(v
);
3273 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3276 static void kvm_cpu_vmxoff(void)
3278 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3280 intel_pt_handle_vmx(0);
3283 static void hardware_disable(void)
3285 if (vmm_exclusive
) {
3286 vmclear_local_loaded_vmcss();
3289 cr4_clear_bits(X86_CR4_VMXE
);
3292 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3293 u32 msr
, u32
*result
)
3295 u32 vmx_msr_low
, vmx_msr_high
;
3296 u32 ctl
= ctl_min
| ctl_opt
;
3298 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3300 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3301 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3303 /* Ensure minimum (required) set of control bits are supported. */
3311 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3313 u32 vmx_msr_low
, vmx_msr_high
;
3315 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3316 return vmx_msr_high
& ctl
;
3319 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3321 u32 vmx_msr_low
, vmx_msr_high
;
3322 u32 min
, opt
, min2
, opt2
;
3323 u32 _pin_based_exec_control
= 0;
3324 u32 _cpu_based_exec_control
= 0;
3325 u32 _cpu_based_2nd_exec_control
= 0;
3326 u32 _vmexit_control
= 0;
3327 u32 _vmentry_control
= 0;
3329 min
= CPU_BASED_HLT_EXITING
|
3330 #ifdef CONFIG_X86_64
3331 CPU_BASED_CR8_LOAD_EXITING
|
3332 CPU_BASED_CR8_STORE_EXITING
|
3334 CPU_BASED_CR3_LOAD_EXITING
|
3335 CPU_BASED_CR3_STORE_EXITING
|
3336 CPU_BASED_USE_IO_BITMAPS
|
3337 CPU_BASED_MOV_DR_EXITING
|
3338 CPU_BASED_USE_TSC_OFFSETING
|
3339 CPU_BASED_MWAIT_EXITING
|
3340 CPU_BASED_MONITOR_EXITING
|
3341 CPU_BASED_INVLPG_EXITING
|
3342 CPU_BASED_RDPMC_EXITING
;
3344 opt
= CPU_BASED_TPR_SHADOW
|
3345 CPU_BASED_USE_MSR_BITMAPS
|
3346 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3347 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3348 &_cpu_based_exec_control
) < 0)
3350 #ifdef CONFIG_X86_64
3351 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3352 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3353 ~CPU_BASED_CR8_STORE_EXITING
;
3355 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3357 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3358 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3359 SECONDARY_EXEC_WBINVD_EXITING
|
3360 SECONDARY_EXEC_ENABLE_VPID
|
3361 SECONDARY_EXEC_ENABLE_EPT
|
3362 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3363 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3364 SECONDARY_EXEC_RDTSCP
|
3365 SECONDARY_EXEC_ENABLE_INVPCID
|
3366 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3367 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3368 SECONDARY_EXEC_SHADOW_VMCS
|
3369 SECONDARY_EXEC_XSAVES
|
3370 SECONDARY_EXEC_ENABLE_PML
|
3371 SECONDARY_EXEC_PCOMMIT
|
3372 SECONDARY_EXEC_TSC_SCALING
;
3373 if (adjust_vmx_controls(min2
, opt2
,
3374 MSR_IA32_VMX_PROCBASED_CTLS2
,
3375 &_cpu_based_2nd_exec_control
) < 0)
3378 #ifndef CONFIG_X86_64
3379 if (!(_cpu_based_2nd_exec_control
&
3380 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3381 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3384 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3385 _cpu_based_2nd_exec_control
&= ~(
3386 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3387 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3388 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3390 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3391 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3393 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3394 CPU_BASED_CR3_STORE_EXITING
|
3395 CPU_BASED_INVLPG_EXITING
);
3396 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3397 vmx_capability
.ept
, vmx_capability
.vpid
);
3400 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3401 #ifdef CONFIG_X86_64
3402 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3404 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3405 VM_EXIT_CLEAR_BNDCFGS
;
3406 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3407 &_vmexit_control
) < 0)
3410 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3411 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3412 PIN_BASED_VMX_PREEMPTION_TIMER
;
3413 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3414 &_pin_based_exec_control
) < 0)
3417 if (cpu_has_broken_vmx_preemption_timer())
3418 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3419 if (!(_cpu_based_2nd_exec_control
&
3420 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3421 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3423 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3424 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3425 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3426 &_vmentry_control
) < 0)
3429 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3431 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3432 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3435 #ifdef CONFIG_X86_64
3436 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3437 if (vmx_msr_high
& (1u<<16))
3441 /* Require Write-Back (WB) memory type for VMCS accesses. */
3442 if (((vmx_msr_high
>> 18) & 15) != 6)
3445 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3446 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3447 vmcs_conf
->revision_id
= vmx_msr_low
;
3449 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3450 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3451 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3452 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3453 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3455 cpu_has_load_ia32_efer
=
3456 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3457 VM_ENTRY_LOAD_IA32_EFER
)
3458 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3459 VM_EXIT_LOAD_IA32_EFER
);
3461 cpu_has_load_perf_global_ctrl
=
3462 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3463 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3464 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3465 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3468 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3469 * but due to errata below it can't be used. Workaround is to use
3470 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3472 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3477 * BC86,AAY89,BD102 (model 44)
3481 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3482 switch (boot_cpu_data
.x86_model
) {
3488 cpu_has_load_perf_global_ctrl
= false;
3489 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3490 "does not work properly. Using workaround\n");
3497 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3498 rdmsrl(MSR_IA32_XSS
, host_xss
);
3503 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3505 int node
= cpu_to_node(cpu
);
3509 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3512 vmcs
= page_address(pages
);
3513 memset(vmcs
, 0, vmcs_config
.size
);
3514 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3518 static struct vmcs
*alloc_vmcs(void)
3520 return alloc_vmcs_cpu(raw_smp_processor_id());
3523 static void free_vmcs(struct vmcs
*vmcs
)
3525 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3529 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3531 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3533 if (!loaded_vmcs
->vmcs
)
3535 loaded_vmcs_clear(loaded_vmcs
);
3536 free_vmcs(loaded_vmcs
->vmcs
);
3537 loaded_vmcs
->vmcs
= NULL
;
3540 static void free_kvm_area(void)
3544 for_each_possible_cpu(cpu
) {
3545 free_vmcs(per_cpu(vmxarea
, cpu
));
3546 per_cpu(vmxarea
, cpu
) = NULL
;
3550 static void init_vmcs_shadow_fields(void)
3554 /* No checks for read only fields yet */
3556 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3557 switch (shadow_read_write_fields
[i
]) {
3559 if (!kvm_mpx_supported())
3567 shadow_read_write_fields
[j
] =
3568 shadow_read_write_fields
[i
];
3571 max_shadow_read_write_fields
= j
;
3573 /* shadowed fields guest access without vmexit */
3574 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3575 clear_bit(shadow_read_write_fields
[i
],
3576 vmx_vmwrite_bitmap
);
3577 clear_bit(shadow_read_write_fields
[i
],
3580 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3581 clear_bit(shadow_read_only_fields
[i
],
3585 static __init
int alloc_kvm_area(void)
3589 for_each_possible_cpu(cpu
) {
3592 vmcs
= alloc_vmcs_cpu(cpu
);
3598 per_cpu(vmxarea
, cpu
) = vmcs
;
3603 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3605 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3608 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3609 struct kvm_segment
*save
)
3611 if (!emulate_invalid_guest_state
) {
3613 * CS and SS RPL should be equal during guest entry according
3614 * to VMX spec, but in reality it is not always so. Since vcpu
3615 * is in the middle of the transition from real mode to
3616 * protected mode it is safe to assume that RPL 0 is a good
3619 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3620 save
->selector
&= ~SEGMENT_RPL_MASK
;
3621 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3624 vmx_set_segment(vcpu
, save
, seg
);
3627 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3629 unsigned long flags
;
3630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3633 * Update real mode segment cache. It may be not up-to-date if sement
3634 * register was written while vcpu was in a guest mode.
3636 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3637 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3638 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3639 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3640 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3641 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3643 vmx
->rmode
.vm86_active
= 0;
3645 vmx_segment_cache_clear(vmx
);
3647 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3649 flags
= vmcs_readl(GUEST_RFLAGS
);
3650 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3651 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3652 vmcs_writel(GUEST_RFLAGS
, flags
);
3654 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3655 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3657 update_exception_bitmap(vcpu
);
3659 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3660 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3661 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3662 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3663 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3664 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3667 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3669 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3670 struct kvm_segment var
= *save
;
3673 if (seg
== VCPU_SREG_CS
)
3676 if (!emulate_invalid_guest_state
) {
3677 var
.selector
= var
.base
>> 4;
3678 var
.base
= var
.base
& 0xffff0;
3688 if (save
->base
& 0xf)
3689 printk_once(KERN_WARNING
"kvm: segment base is not "
3690 "paragraph aligned when entering "
3691 "protected mode (seg=%d)", seg
);
3694 vmcs_write16(sf
->selector
, var
.selector
);
3695 vmcs_write32(sf
->base
, var
.base
);
3696 vmcs_write32(sf
->limit
, var
.limit
);
3697 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3700 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3702 unsigned long flags
;
3703 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3705 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3706 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3707 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3708 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3709 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3710 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3711 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3713 vmx
->rmode
.vm86_active
= 1;
3716 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3717 * vcpu. Warn the user that an update is overdue.
3719 if (!vcpu
->kvm
->arch
.tss_addr
)
3720 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3721 "called before entering vcpu\n");
3723 vmx_segment_cache_clear(vmx
);
3725 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3726 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3727 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3729 flags
= vmcs_readl(GUEST_RFLAGS
);
3730 vmx
->rmode
.save_rflags
= flags
;
3732 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3734 vmcs_writel(GUEST_RFLAGS
, flags
);
3735 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3736 update_exception_bitmap(vcpu
);
3738 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3739 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3740 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3741 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3742 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3743 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3745 kvm_mmu_reset_context(vcpu
);
3748 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3750 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3751 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3757 * Force kernel_gs_base reloading before EFER changes, as control
3758 * of this msr depends on is_long_mode().
3760 vmx_load_host_state(to_vmx(vcpu
));
3761 vcpu
->arch
.efer
= efer
;
3762 if (efer
& EFER_LMA
) {
3763 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3766 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3768 msr
->data
= efer
& ~EFER_LME
;
3773 #ifdef CONFIG_X86_64
3775 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3779 vmx_segment_cache_clear(to_vmx(vcpu
));
3781 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3782 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3783 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3785 vmcs_write32(GUEST_TR_AR_BYTES
,
3786 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3787 | VMX_AR_TYPE_BUSY_64_TSS
);
3789 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3792 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3794 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3795 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3800 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3802 vpid_sync_context(vpid
);
3804 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3806 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3810 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3812 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3815 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3817 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3819 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3820 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3823 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3825 if (enable_ept
&& is_paging(vcpu
))
3826 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3827 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3830 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3832 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3834 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3835 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3838 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3840 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3842 if (!test_bit(VCPU_EXREG_PDPTR
,
3843 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3846 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3847 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3848 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3849 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3850 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3854 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3856 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3858 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3859 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3860 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3861 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3862 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3865 __set_bit(VCPU_EXREG_PDPTR
,
3866 (unsigned long *)&vcpu
->arch
.regs_avail
);
3867 __set_bit(VCPU_EXREG_PDPTR
,
3868 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3871 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3873 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3875 struct kvm_vcpu
*vcpu
)
3877 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3878 vmx_decache_cr3(vcpu
);
3879 if (!(cr0
& X86_CR0_PG
)) {
3880 /* From paging/starting to nonpaging */
3881 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3882 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3883 (CPU_BASED_CR3_LOAD_EXITING
|
3884 CPU_BASED_CR3_STORE_EXITING
));
3885 vcpu
->arch
.cr0
= cr0
;
3886 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3887 } else if (!is_paging(vcpu
)) {
3888 /* From nonpaging to paging */
3889 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3890 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3891 ~(CPU_BASED_CR3_LOAD_EXITING
|
3892 CPU_BASED_CR3_STORE_EXITING
));
3893 vcpu
->arch
.cr0
= cr0
;
3894 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3897 if (!(cr0
& X86_CR0_WP
))
3898 *hw_cr0
&= ~X86_CR0_WP
;
3901 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3904 unsigned long hw_cr0
;
3906 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3907 if (enable_unrestricted_guest
)
3908 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3910 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3912 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3915 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3919 #ifdef CONFIG_X86_64
3920 if (vcpu
->arch
.efer
& EFER_LME
) {
3921 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3923 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3929 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3931 if (!vcpu
->fpu_active
)
3932 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3934 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3935 vmcs_writel(GUEST_CR0
, hw_cr0
);
3936 vcpu
->arch
.cr0
= cr0
;
3938 /* depends on vcpu->arch.cr0 to be set to a new value */
3939 vmx
->emulation_required
= emulation_required(vcpu
);
3942 static u64
construct_eptp(unsigned long root_hpa
)
3946 /* TODO write the value reading from MSR */
3947 eptp
= VMX_EPT_DEFAULT_MT
|
3948 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3949 if (enable_ept_ad_bits
)
3950 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3951 eptp
|= (root_hpa
& PAGE_MASK
);
3956 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3958 unsigned long guest_cr3
;
3963 eptp
= construct_eptp(cr3
);
3964 vmcs_write64(EPT_POINTER
, eptp
);
3965 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3966 guest_cr3
= kvm_read_cr3(vcpu
);
3968 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3969 ept_load_pdptrs(vcpu
);
3972 vmx_flush_tlb(vcpu
);
3973 vmcs_writel(GUEST_CR3
, guest_cr3
);
3976 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3979 * Pass through host's Machine Check Enable value to hw_cr4, which
3980 * is in force while we are in guest mode. Do not let guests control
3981 * this bit, even if host CR4.MCE == 0.
3983 unsigned long hw_cr4
=
3984 (cr4_read_shadow() & X86_CR4_MCE
) |
3985 (cr4
& ~X86_CR4_MCE
) |
3986 (to_vmx(vcpu
)->rmode
.vm86_active
?
3987 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3989 if (cr4
& X86_CR4_VMXE
) {
3991 * To use VMXON (and later other VMX instructions), a guest
3992 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3993 * So basically the check on whether to allow nested VMX
3996 if (!nested_vmx_allowed(vcpu
))
3999 if (to_vmx(vcpu
)->nested
.vmxon
&&
4000 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
4003 vcpu
->arch
.cr4
= cr4
;
4005 if (!is_paging(vcpu
)) {
4006 hw_cr4
&= ~X86_CR4_PAE
;
4007 hw_cr4
|= X86_CR4_PSE
;
4008 } else if (!(cr4
& X86_CR4_PAE
)) {
4009 hw_cr4
&= ~X86_CR4_PAE
;
4013 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4015 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4016 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4017 * to be manually disabled when guest switches to non-paging
4020 * If !enable_unrestricted_guest, the CPU is always running
4021 * with CR0.PG=1 and CR4 needs to be modified.
4022 * If enable_unrestricted_guest, the CPU automatically
4023 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4025 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4027 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4028 vmcs_writel(GUEST_CR4
, hw_cr4
);
4032 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4033 struct kvm_segment
*var
, int seg
)
4035 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4038 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4039 *var
= vmx
->rmode
.segs
[seg
];
4040 if (seg
== VCPU_SREG_TR
4041 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4043 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4044 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4047 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4048 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4049 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4050 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4051 var
->unusable
= (ar
>> 16) & 1;
4052 var
->type
= ar
& 15;
4053 var
->s
= (ar
>> 4) & 1;
4054 var
->dpl
= (ar
>> 5) & 3;
4056 * Some userspaces do not preserve unusable property. Since usable
4057 * segment has to be present according to VMX spec we can use present
4058 * property to amend userspace bug by making unusable segment always
4059 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4060 * segment as unusable.
4062 var
->present
= !var
->unusable
;
4063 var
->avl
= (ar
>> 12) & 1;
4064 var
->l
= (ar
>> 13) & 1;
4065 var
->db
= (ar
>> 14) & 1;
4066 var
->g
= (ar
>> 15) & 1;
4069 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4071 struct kvm_segment s
;
4073 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4074 vmx_get_segment(vcpu
, &s
, seg
);
4077 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4080 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4082 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4084 if (unlikely(vmx
->rmode
.vm86_active
))
4087 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4088 return VMX_AR_DPL(ar
);
4092 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4096 if (var
->unusable
|| !var
->present
)
4099 ar
= var
->type
& 15;
4100 ar
|= (var
->s
& 1) << 4;
4101 ar
|= (var
->dpl
& 3) << 5;
4102 ar
|= (var
->present
& 1) << 7;
4103 ar
|= (var
->avl
& 1) << 12;
4104 ar
|= (var
->l
& 1) << 13;
4105 ar
|= (var
->db
& 1) << 14;
4106 ar
|= (var
->g
& 1) << 15;
4112 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4113 struct kvm_segment
*var
, int seg
)
4115 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4116 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4118 vmx_segment_cache_clear(vmx
);
4120 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4121 vmx
->rmode
.segs
[seg
] = *var
;
4122 if (seg
== VCPU_SREG_TR
)
4123 vmcs_write16(sf
->selector
, var
->selector
);
4125 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4129 vmcs_writel(sf
->base
, var
->base
);
4130 vmcs_write32(sf
->limit
, var
->limit
);
4131 vmcs_write16(sf
->selector
, var
->selector
);
4134 * Fix the "Accessed" bit in AR field of segment registers for older
4136 * IA32 arch specifies that at the time of processor reset the
4137 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4138 * is setting it to 0 in the userland code. This causes invalid guest
4139 * state vmexit when "unrestricted guest" mode is turned on.
4140 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4141 * tree. Newer qemu binaries with that qemu fix would not need this
4144 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4145 var
->type
|= 0x1; /* Accessed */
4147 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4150 vmx
->emulation_required
= emulation_required(vcpu
);
4153 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4155 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4157 *db
= (ar
>> 14) & 1;
4158 *l
= (ar
>> 13) & 1;
4161 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4163 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4164 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4167 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4169 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4170 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4173 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4175 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4176 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4179 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4181 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4182 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4185 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4187 struct kvm_segment var
;
4190 vmx_get_segment(vcpu
, &var
, seg
);
4192 if (seg
== VCPU_SREG_CS
)
4194 ar
= vmx_segment_access_rights(&var
);
4196 if (var
.base
!= (var
.selector
<< 4))
4198 if (var
.limit
!= 0xffff)
4206 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4208 struct kvm_segment cs
;
4209 unsigned int cs_rpl
;
4211 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4212 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4216 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4220 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4221 if (cs
.dpl
> cs_rpl
)
4224 if (cs
.dpl
!= cs_rpl
)
4230 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4234 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4236 struct kvm_segment ss
;
4237 unsigned int ss_rpl
;
4239 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4240 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4244 if (ss
.type
!= 3 && ss
.type
!= 7)
4248 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4256 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4258 struct kvm_segment var
;
4261 vmx_get_segment(vcpu
, &var
, seg
);
4262 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4270 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4271 if (var
.dpl
< rpl
) /* DPL < RPL */
4275 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4281 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4283 struct kvm_segment tr
;
4285 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4289 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4291 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4299 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4301 struct kvm_segment ldtr
;
4303 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4307 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4317 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4319 struct kvm_segment cs
, ss
;
4321 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4322 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4324 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4325 (ss
.selector
& SEGMENT_RPL_MASK
));
4329 * Check if guest state is valid. Returns true if valid, false if
4331 * We assume that registers are always usable
4333 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4335 if (enable_unrestricted_guest
)
4338 /* real mode guest state checks */
4339 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4340 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4342 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4344 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4346 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4348 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4350 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4353 /* protected mode guest state checks */
4354 if (!cs_ss_rpl_check(vcpu
))
4356 if (!code_segment_valid(vcpu
))
4358 if (!stack_segment_valid(vcpu
))
4360 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4362 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4364 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4366 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4368 if (!tr_valid(vcpu
))
4370 if (!ldtr_valid(vcpu
))
4374 * - Add checks on RIP
4375 * - Add checks on RFLAGS
4381 static int init_rmode_tss(struct kvm
*kvm
)
4387 idx
= srcu_read_lock(&kvm
->srcu
);
4388 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4389 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4392 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4393 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4394 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4397 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4400 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4404 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4405 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4408 srcu_read_unlock(&kvm
->srcu
, idx
);
4412 static int init_rmode_identity_map(struct kvm
*kvm
)
4415 kvm_pfn_t identity_map_pfn
;
4421 /* Protect kvm->arch.ept_identity_pagetable_done. */
4422 mutex_lock(&kvm
->slots_lock
);
4424 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4427 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4429 r
= alloc_identity_pagetable(kvm
);
4433 idx
= srcu_read_lock(&kvm
->srcu
);
4434 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4437 /* Set up identity-mapping pagetable for EPT in real mode */
4438 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4439 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4440 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4441 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4442 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4446 kvm
->arch
.ept_identity_pagetable_done
= true;
4449 srcu_read_unlock(&kvm
->srcu
, idx
);
4452 mutex_unlock(&kvm
->slots_lock
);
4456 static void seg_setup(int seg
)
4458 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4461 vmcs_write16(sf
->selector
, 0);
4462 vmcs_writel(sf
->base
, 0);
4463 vmcs_write32(sf
->limit
, 0xffff);
4465 if (seg
== VCPU_SREG_CS
)
4466 ar
|= 0x08; /* code segment */
4468 vmcs_write32(sf
->ar_bytes
, ar
);
4471 static int alloc_apic_access_page(struct kvm
*kvm
)
4476 mutex_lock(&kvm
->slots_lock
);
4477 if (kvm
->arch
.apic_access_page_done
)
4479 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4480 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4484 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4485 if (is_error_page(page
)) {
4491 * Do not pin the page in memory, so that memory hot-unplug
4492 * is able to migrate it.
4495 kvm
->arch
.apic_access_page_done
= true;
4497 mutex_unlock(&kvm
->slots_lock
);
4501 static int alloc_identity_pagetable(struct kvm
*kvm
)
4503 /* Called with kvm->slots_lock held. */
4507 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4509 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4510 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4515 static int allocate_vpid(void)
4521 spin_lock(&vmx_vpid_lock
);
4522 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4523 if (vpid
< VMX_NR_VPIDS
)
4524 __set_bit(vpid
, vmx_vpid_bitmap
);
4527 spin_unlock(&vmx_vpid_lock
);
4531 static void free_vpid(int vpid
)
4533 if (!enable_vpid
|| vpid
== 0)
4535 spin_lock(&vmx_vpid_lock
);
4536 __clear_bit(vpid
, vmx_vpid_bitmap
);
4537 spin_unlock(&vmx_vpid_lock
);
4540 #define MSR_TYPE_R 1
4541 #define MSR_TYPE_W 2
4542 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4545 int f
= sizeof(unsigned long);
4547 if (!cpu_has_vmx_msr_bitmap())
4551 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4552 * have the write-low and read-high bitmap offsets the wrong way round.
4553 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4555 if (msr
<= 0x1fff) {
4556 if (type
& MSR_TYPE_R
)
4558 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4560 if (type
& MSR_TYPE_W
)
4562 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4564 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4566 if (type
& MSR_TYPE_R
)
4568 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4570 if (type
& MSR_TYPE_W
)
4572 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4577 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4580 int f
= sizeof(unsigned long);
4582 if (!cpu_has_vmx_msr_bitmap())
4586 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4587 * have the write-low and read-high bitmap offsets the wrong way round.
4588 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4590 if (msr
<= 0x1fff) {
4591 if (type
& MSR_TYPE_R
)
4593 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4595 if (type
& MSR_TYPE_W
)
4597 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4599 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4601 if (type
& MSR_TYPE_R
)
4603 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4605 if (type
& MSR_TYPE_W
)
4607 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4613 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4614 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4616 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4617 unsigned long *msr_bitmap_nested
,
4620 int f
= sizeof(unsigned long);
4622 if (!cpu_has_vmx_msr_bitmap()) {
4628 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4629 * have the write-low and read-high bitmap offsets the wrong way round.
4630 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4632 if (msr
<= 0x1fff) {
4633 if (type
& MSR_TYPE_R
&&
4634 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4636 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4638 if (type
& MSR_TYPE_W
&&
4639 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4641 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4643 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4645 if (type
& MSR_TYPE_R
&&
4646 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4648 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4650 if (type
& MSR_TYPE_W
&&
4651 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4653 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4658 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4661 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4662 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4663 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4664 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4667 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4669 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4671 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4675 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4677 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4679 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4683 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4685 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4687 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4691 static bool vmx_get_enable_apicv(void)
4693 return enable_apicv
;
4696 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4698 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4703 if (vmx
->nested
.pi_desc
&&
4704 vmx
->nested
.pi_pending
) {
4705 vmx
->nested
.pi_pending
= false;
4706 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4709 max_irr
= find_last_bit(
4710 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4715 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4720 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4721 kunmap(vmx
->nested
.virtual_apic_page
);
4723 status
= vmcs_read16(GUEST_INTR_STATUS
);
4724 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4726 status
|= (u8
)max_irr
;
4727 vmcs_write16(GUEST_INTR_STATUS
, status
);
4733 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4736 if (vcpu
->mode
== IN_GUEST_MODE
) {
4737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4740 * Currently, we don't support urgent interrupt,
4741 * all interrupts are recognized as non-urgent
4742 * interrupt, so we cannot post interrupts when
4745 * If the vcpu is in guest mode, it means it is
4746 * running instead of being scheduled out and
4747 * waiting in the run queue, and that's the only
4748 * case when 'SN' is set currently, warning if
4751 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4753 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4754 POSTED_INTR_VECTOR
);
4761 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4764 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4766 if (is_guest_mode(vcpu
) &&
4767 vector
== vmx
->nested
.posted_intr_nv
) {
4768 /* the PIR and ON have been set by L1. */
4769 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4771 * If a posted intr is not recognized by hardware,
4772 * we will accomplish it in the next vmentry.
4774 vmx
->nested
.pi_pending
= true;
4775 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4781 * Send interrupt to vcpu via posted interrupt way.
4782 * 1. If target vcpu is running(non-root mode), send posted interrupt
4783 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4784 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4785 * interrupt from PIR in next vmentry.
4787 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4789 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4792 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4796 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4799 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4800 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4801 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4802 kvm_vcpu_kick(vcpu
);
4805 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4807 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4809 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4812 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4816 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4817 * will not change in the lifetime of the guest.
4818 * Note that host-state that does change is set elsewhere. E.g., host-state
4819 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4821 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4828 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4829 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4831 /* Save the most likely value for this task's CR4 in the VMCS. */
4832 cr4
= cr4_read_shadow();
4833 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4834 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4836 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4837 #ifdef CONFIG_X86_64
4839 * Load null selectors, so we can avoid reloading them in
4840 * __vmx_load_host_state(), in case userspace uses the null selectors
4841 * too (the expected case).
4843 vmcs_write16(HOST_DS_SELECTOR
, 0);
4844 vmcs_write16(HOST_ES_SELECTOR
, 0);
4846 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4847 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4849 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4850 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4852 native_store_idt(&dt
);
4853 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4854 vmx
->host_idt_base
= dt
.address
;
4856 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4858 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4859 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4860 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4861 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4863 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4864 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4865 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4869 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4871 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4873 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4874 if (is_guest_mode(&vmx
->vcpu
))
4875 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4876 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4877 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4880 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4882 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4884 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4885 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4886 /* Enable the preemption timer dynamically */
4887 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4888 return pin_based_exec_ctrl
;
4891 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4895 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4896 if (cpu_has_secondary_exec_ctrls()) {
4897 if (kvm_vcpu_apicv_active(vcpu
))
4898 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4899 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4900 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4902 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4903 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4904 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4907 if (cpu_has_vmx_msr_bitmap())
4908 vmx_set_msr_bitmap(vcpu
);
4911 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4913 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4915 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4916 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4918 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4919 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4920 #ifdef CONFIG_X86_64
4921 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4922 CPU_BASED_CR8_LOAD_EXITING
;
4926 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4927 CPU_BASED_CR3_LOAD_EXITING
|
4928 CPU_BASED_INVLPG_EXITING
;
4929 return exec_control
;
4932 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4934 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4935 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4936 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4938 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4940 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4941 enable_unrestricted_guest
= 0;
4942 /* Enable INVPCID for non-ept guests may cause performance regression. */
4943 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4945 if (!enable_unrestricted_guest
)
4946 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4948 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4949 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4950 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4951 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4952 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4953 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4955 We can NOT enable shadow_vmcs here because we don't have yet
4958 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4961 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4963 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4964 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4966 return exec_control
;
4969 static void ept_set_mmio_spte_mask(void)
4972 * EPT Misconfigurations can be generated if the value of bits 2:0
4973 * of an EPT paging-structure entry is 110b (write/execute).
4974 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4977 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4980 #define VMX_XSS_EXIT_BITMAP 0
4982 * Sets up the vmcs for emulated real mode.
4984 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4986 #ifdef CONFIG_X86_64
4992 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4993 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4995 if (enable_shadow_vmcs
) {
4996 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4997 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4999 if (cpu_has_vmx_msr_bitmap())
5000 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5002 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5005 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5006 vmx
->hv_deadline_tsc
= -1;
5008 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5010 if (cpu_has_secondary_exec_ctrls())
5011 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5012 vmx_secondary_exec_control(vmx
));
5014 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5015 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5016 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5017 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5018 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5020 vmcs_write16(GUEST_INTR_STATUS
, 0);
5022 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5023 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5027 vmcs_write32(PLE_GAP
, ple_gap
);
5028 vmx
->ple_window
= ple_window
;
5029 vmx
->ple_window_dirty
= true;
5032 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5033 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5034 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5036 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5037 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5038 vmx_set_constant_host_state(vmx
);
5039 #ifdef CONFIG_X86_64
5040 rdmsrl(MSR_FS_BASE
, a
);
5041 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5042 rdmsrl(MSR_GS_BASE
, a
);
5043 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5045 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5046 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5049 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5050 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5051 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5052 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5053 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5055 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5056 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5058 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5059 u32 index
= vmx_msr_index
[i
];
5060 u32 data_low
, data_high
;
5063 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5065 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5067 vmx
->guest_msrs
[j
].index
= i
;
5068 vmx
->guest_msrs
[j
].data
= 0;
5069 vmx
->guest_msrs
[j
].mask
= -1ull;
5074 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5076 /* 22.2.1, 20.8.1 */
5077 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5079 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
5080 set_cr4_guest_host_mask(vmx
);
5082 if (vmx_xsaves_supported())
5083 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5088 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5090 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5091 struct msr_data apic_base_msr
;
5094 vmx
->rmode
.vm86_active
= 0;
5096 vmx
->soft_vnmi_blocked
= 0;
5098 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5099 kvm_set_cr8(vcpu
, 0);
5102 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5103 MSR_IA32_APICBASE_ENABLE
;
5104 if (kvm_vcpu_is_reset_bsp(vcpu
))
5105 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5106 apic_base_msr
.host_initiated
= true;
5107 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5110 vmx_segment_cache_clear(vmx
);
5112 seg_setup(VCPU_SREG_CS
);
5113 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5114 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5116 seg_setup(VCPU_SREG_DS
);
5117 seg_setup(VCPU_SREG_ES
);
5118 seg_setup(VCPU_SREG_FS
);
5119 seg_setup(VCPU_SREG_GS
);
5120 seg_setup(VCPU_SREG_SS
);
5122 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5123 vmcs_writel(GUEST_TR_BASE
, 0);
5124 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5125 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5127 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5128 vmcs_writel(GUEST_LDTR_BASE
, 0);
5129 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5130 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5133 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5134 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5135 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5136 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5139 vmcs_writel(GUEST_RFLAGS
, 0x02);
5140 kvm_rip_write(vcpu
, 0xfff0);
5142 vmcs_writel(GUEST_GDTR_BASE
, 0);
5143 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5145 vmcs_writel(GUEST_IDTR_BASE
, 0);
5146 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5148 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5149 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5150 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5154 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5156 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5157 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5158 if (cpu_need_tpr_shadow(vcpu
))
5159 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5160 __pa(vcpu
->arch
.apic
->regs
));
5161 vmcs_write32(TPR_THRESHOLD
, 0);
5164 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5166 if (kvm_vcpu_apicv_active(vcpu
))
5167 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5170 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5172 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5173 vmx
->vcpu
.arch
.cr0
= cr0
;
5174 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5175 vmx_set_cr4(vcpu
, 0);
5176 vmx_set_efer(vcpu
, 0);
5177 vmx_fpu_activate(vcpu
);
5178 update_exception_bitmap(vcpu
);
5180 vpid_sync_context(vmx
->vpid
);
5184 * In nested virtualization, check if L1 asked to exit on external interrupts.
5185 * For most existing hypervisors, this will always return true.
5187 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5189 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5190 PIN_BASED_EXT_INTR_MASK
;
5194 * In nested virtualization, check if L1 has set
5195 * VM_EXIT_ACK_INTR_ON_EXIT
5197 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5199 return get_vmcs12(vcpu
)->vm_exit_controls
&
5200 VM_EXIT_ACK_INTR_ON_EXIT
;
5203 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5205 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5206 PIN_BASED_NMI_EXITING
;
5209 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5211 u32 cpu_based_vm_exec_control
;
5213 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5214 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5215 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5218 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5220 u32 cpu_based_vm_exec_control
;
5222 if (!cpu_has_virtual_nmis() ||
5223 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5224 enable_irq_window(vcpu
);
5228 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5229 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5230 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5233 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5235 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5237 int irq
= vcpu
->arch
.interrupt
.nr
;
5239 trace_kvm_inj_virq(irq
);
5241 ++vcpu
->stat
.irq_injections
;
5242 if (vmx
->rmode
.vm86_active
) {
5244 if (vcpu
->arch
.interrupt
.soft
)
5245 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5246 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5247 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5250 intr
= irq
| INTR_INFO_VALID_MASK
;
5251 if (vcpu
->arch
.interrupt
.soft
) {
5252 intr
|= INTR_TYPE_SOFT_INTR
;
5253 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5254 vmx
->vcpu
.arch
.event_exit_inst_len
);
5256 intr
|= INTR_TYPE_EXT_INTR
;
5257 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5260 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5264 if (is_guest_mode(vcpu
))
5267 if (!cpu_has_virtual_nmis()) {
5269 * Tracking the NMI-blocked state in software is built upon
5270 * finding the next open IRQ window. This, in turn, depends on
5271 * well-behaving guests: They have to keep IRQs disabled at
5272 * least as long as the NMI handler runs. Otherwise we may
5273 * cause NMI nesting, maybe breaking the guest. But as this is
5274 * highly unlikely, we can live with the residual risk.
5276 vmx
->soft_vnmi_blocked
= 1;
5277 vmx
->vnmi_blocked_time
= 0;
5280 ++vcpu
->stat
.nmi_injections
;
5281 vmx
->nmi_known_unmasked
= false;
5282 if (vmx
->rmode
.vm86_active
) {
5283 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5284 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5287 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5288 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5291 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5293 if (!cpu_has_virtual_nmis())
5294 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5295 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5297 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5300 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5302 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5304 if (!cpu_has_virtual_nmis()) {
5305 if (vmx
->soft_vnmi_blocked
!= masked
) {
5306 vmx
->soft_vnmi_blocked
= masked
;
5307 vmx
->vnmi_blocked_time
= 0;
5310 vmx
->nmi_known_unmasked
= !masked
;
5312 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5313 GUEST_INTR_STATE_NMI
);
5315 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5316 GUEST_INTR_STATE_NMI
);
5320 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5322 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5325 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5328 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5329 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5330 | GUEST_INTR_STATE_NMI
));
5333 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5335 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5336 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5337 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5338 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5341 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5345 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5349 kvm
->arch
.tss_addr
= addr
;
5350 return init_rmode_tss(kvm
);
5353 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5358 * Update instruction length as we may reinject the exception
5359 * from user space while in guest debugging mode.
5361 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5362 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5363 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5367 if (vcpu
->guest_debug
&
5368 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5385 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5386 int vec
, u32 err_code
)
5389 * Instruction with address size override prefix opcode 0x67
5390 * Cause the #SS fault with 0 error code in VM86 mode.
5392 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5393 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5394 if (vcpu
->arch
.halt_request
) {
5395 vcpu
->arch
.halt_request
= 0;
5396 return kvm_vcpu_halt(vcpu
);
5404 * Forward all other exceptions that are valid in real mode.
5405 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5406 * the required debugging infrastructure rework.
5408 kvm_queue_exception(vcpu
, vec
);
5413 * Trigger machine check on the host. We assume all the MSRs are already set up
5414 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5415 * We pass a fake environment to the machine check handler because we want
5416 * the guest to be always treated like user space, no matter what context
5417 * it used internally.
5419 static void kvm_machine_check(void)
5421 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5422 struct pt_regs regs
= {
5423 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5424 .flags
= X86_EFLAGS_IF
,
5427 do_machine_check(®s
, 0);
5431 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5433 /* already handled by vcpu_run */
5437 static int handle_exception(struct kvm_vcpu
*vcpu
)
5439 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5440 struct kvm_run
*kvm_run
= vcpu
->run
;
5441 u32 intr_info
, ex_no
, error_code
;
5442 unsigned long cr2
, rip
, dr6
;
5444 enum emulation_result er
;
5446 vect_info
= vmx
->idt_vectoring_info
;
5447 intr_info
= vmx
->exit_intr_info
;
5449 if (is_machine_check(intr_info
))
5450 return handle_machine_check(vcpu
);
5452 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5453 return 1; /* already handled by vmx_vcpu_run() */
5455 if (is_no_device(intr_info
)) {
5456 vmx_fpu_activate(vcpu
);
5460 if (is_invalid_opcode(intr_info
)) {
5461 if (is_guest_mode(vcpu
)) {
5462 kvm_queue_exception(vcpu
, UD_VECTOR
);
5465 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5466 if (er
!= EMULATE_DONE
)
5467 kvm_queue_exception(vcpu
, UD_VECTOR
);
5472 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5473 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5476 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5477 * MMIO, it is better to report an internal error.
5478 * See the comments in vmx_handle_exit.
5480 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5481 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5482 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5483 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5484 vcpu
->run
->internal
.ndata
= 3;
5485 vcpu
->run
->internal
.data
[0] = vect_info
;
5486 vcpu
->run
->internal
.data
[1] = intr_info
;
5487 vcpu
->run
->internal
.data
[2] = error_code
;
5491 if (is_page_fault(intr_info
)) {
5492 /* EPT won't cause page fault directly */
5494 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5495 trace_kvm_page_fault(cr2
, error_code
);
5497 if (kvm_event_needs_reinjection(vcpu
))
5498 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5499 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5502 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5504 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5505 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5509 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5512 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5513 if (!(vcpu
->guest_debug
&
5514 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5515 vcpu
->arch
.dr6
&= ~15;
5516 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5517 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5518 skip_emulated_instruction(vcpu
);
5520 kvm_queue_exception(vcpu
, DB_VECTOR
);
5523 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5524 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5528 * Update instruction length as we may reinject #BP from
5529 * user space while in guest debugging mode. Reading it for
5530 * #DB as well causes no harm, it is not used in that case.
5532 vmx
->vcpu
.arch
.event_exit_inst_len
=
5533 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5534 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5535 rip
= kvm_rip_read(vcpu
);
5536 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5537 kvm_run
->debug
.arch
.exception
= ex_no
;
5540 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5541 kvm_run
->ex
.exception
= ex_no
;
5542 kvm_run
->ex
.error_code
= error_code
;
5548 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5550 ++vcpu
->stat
.irq_exits
;
5554 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5556 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5560 static int handle_io(struct kvm_vcpu
*vcpu
)
5562 unsigned long exit_qualification
;
5563 int size
, in
, string
;
5566 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5567 string
= (exit_qualification
& 16) != 0;
5568 in
= (exit_qualification
& 8) != 0;
5570 ++vcpu
->stat
.io_exits
;
5573 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5575 port
= exit_qualification
>> 16;
5576 size
= (exit_qualification
& 7) + 1;
5577 skip_emulated_instruction(vcpu
);
5579 return kvm_fast_pio_out(vcpu
, size
, port
);
5583 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5586 * Patch in the VMCALL instruction:
5588 hypercall
[0] = 0x0f;
5589 hypercall
[1] = 0x01;
5590 hypercall
[2] = 0xc1;
5593 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5595 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5596 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5598 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5599 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5600 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5601 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5602 return (val
& always_on
) == always_on
;
5605 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5606 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5608 if (is_guest_mode(vcpu
)) {
5609 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5610 unsigned long orig_val
= val
;
5613 * We get here when L2 changed cr0 in a way that did not change
5614 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5615 * but did change L0 shadowed bits. So we first calculate the
5616 * effective cr0 value that L1 would like to write into the
5617 * hardware. It consists of the L2-owned bits from the new
5618 * value combined with the L1-owned bits from L1's guest_cr0.
5620 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5621 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5623 if (!nested_cr0_valid(vcpu
, val
))
5626 if (kvm_set_cr0(vcpu
, val
))
5628 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5631 if (to_vmx(vcpu
)->nested
.vmxon
&&
5632 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5634 return kvm_set_cr0(vcpu
, val
);
5638 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5640 if (is_guest_mode(vcpu
)) {
5641 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5642 unsigned long orig_val
= val
;
5644 /* analogously to handle_set_cr0 */
5645 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5646 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5647 if (kvm_set_cr4(vcpu
, val
))
5649 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5652 return kvm_set_cr4(vcpu
, val
);
5655 /* called to set cr0 as appropriate for clts instruction exit. */
5656 static void handle_clts(struct kvm_vcpu
*vcpu
)
5658 if (is_guest_mode(vcpu
)) {
5660 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5661 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5662 * just pretend it's off (also in arch.cr0 for fpu_activate).
5664 vmcs_writel(CR0_READ_SHADOW
,
5665 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5666 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5668 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5671 static int handle_cr(struct kvm_vcpu
*vcpu
)
5673 unsigned long exit_qualification
, val
;
5678 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5679 cr
= exit_qualification
& 15;
5680 reg
= (exit_qualification
>> 8) & 15;
5681 switch ((exit_qualification
>> 4) & 3) {
5682 case 0: /* mov to cr */
5683 val
= kvm_register_readl(vcpu
, reg
);
5684 trace_kvm_cr_write(cr
, val
);
5687 err
= handle_set_cr0(vcpu
, val
);
5688 kvm_complete_insn_gp(vcpu
, err
);
5691 err
= kvm_set_cr3(vcpu
, val
);
5692 kvm_complete_insn_gp(vcpu
, err
);
5695 err
= handle_set_cr4(vcpu
, val
);
5696 kvm_complete_insn_gp(vcpu
, err
);
5699 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5701 err
= kvm_set_cr8(vcpu
, cr8
);
5702 kvm_complete_insn_gp(vcpu
, err
);
5703 if (lapic_in_kernel(vcpu
))
5705 if (cr8_prev
<= cr8
)
5707 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5714 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5715 skip_emulated_instruction(vcpu
);
5716 vmx_fpu_activate(vcpu
);
5718 case 1: /*mov from cr*/
5721 val
= kvm_read_cr3(vcpu
);
5722 kvm_register_write(vcpu
, reg
, val
);
5723 trace_kvm_cr_read(cr
, val
);
5724 skip_emulated_instruction(vcpu
);
5727 val
= kvm_get_cr8(vcpu
);
5728 kvm_register_write(vcpu
, reg
, val
);
5729 trace_kvm_cr_read(cr
, val
);
5730 skip_emulated_instruction(vcpu
);
5735 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5736 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5737 kvm_lmsw(vcpu
, val
);
5739 skip_emulated_instruction(vcpu
);
5744 vcpu
->run
->exit_reason
= 0;
5745 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5746 (int)(exit_qualification
>> 4) & 3, cr
);
5750 static int handle_dr(struct kvm_vcpu
*vcpu
)
5752 unsigned long exit_qualification
;
5755 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5756 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5758 /* First, if DR does not exist, trigger UD */
5759 if (!kvm_require_dr(vcpu
, dr
))
5762 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5763 if (!kvm_require_cpl(vcpu
, 0))
5765 dr7
= vmcs_readl(GUEST_DR7
);
5768 * As the vm-exit takes precedence over the debug trap, we
5769 * need to emulate the latter, either for the host or the
5770 * guest debugging itself.
5772 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5773 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5774 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5775 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5776 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5777 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5780 vcpu
->arch
.dr6
&= ~15;
5781 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5782 kvm_queue_exception(vcpu
, DB_VECTOR
);
5787 if (vcpu
->guest_debug
== 0) {
5788 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5789 CPU_BASED_MOV_DR_EXITING
);
5792 * No more DR vmexits; force a reload of the debug registers
5793 * and reenter on this instruction. The next vmexit will
5794 * retrieve the full state of the debug registers.
5796 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5800 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5801 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5804 if (kvm_get_dr(vcpu
, dr
, &val
))
5806 kvm_register_write(vcpu
, reg
, val
);
5808 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5811 skip_emulated_instruction(vcpu
);
5815 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5817 return vcpu
->arch
.dr6
;
5820 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5824 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5826 get_debugreg(vcpu
->arch
.db
[0], 0);
5827 get_debugreg(vcpu
->arch
.db
[1], 1);
5828 get_debugreg(vcpu
->arch
.db
[2], 2);
5829 get_debugreg(vcpu
->arch
.db
[3], 3);
5830 get_debugreg(vcpu
->arch
.dr6
, 6);
5831 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5833 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5834 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5837 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5839 vmcs_writel(GUEST_DR7
, val
);
5842 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5844 kvm_emulate_cpuid(vcpu
);
5848 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5850 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5851 struct msr_data msr_info
;
5853 msr_info
.index
= ecx
;
5854 msr_info
.host_initiated
= false;
5855 if (vmx_get_msr(vcpu
, &msr_info
)) {
5856 trace_kvm_msr_read_ex(ecx
);
5857 kvm_inject_gp(vcpu
, 0);
5861 trace_kvm_msr_read(ecx
, msr_info
.data
);
5863 /* FIXME: handling of bits 32:63 of rax, rdx */
5864 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5865 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5866 skip_emulated_instruction(vcpu
);
5870 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5872 struct msr_data msr
;
5873 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5874 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5875 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5879 msr
.host_initiated
= false;
5880 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5881 trace_kvm_msr_write_ex(ecx
, data
);
5882 kvm_inject_gp(vcpu
, 0);
5886 trace_kvm_msr_write(ecx
, data
);
5887 skip_emulated_instruction(vcpu
);
5891 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5893 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5897 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5899 u32 cpu_based_vm_exec_control
;
5901 /* clear pending irq */
5902 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5903 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5904 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5906 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5908 ++vcpu
->stat
.irq_window_exits
;
5912 static int handle_halt(struct kvm_vcpu
*vcpu
)
5914 return kvm_emulate_halt(vcpu
);
5917 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5919 return kvm_emulate_hypercall(vcpu
);
5922 static int handle_invd(struct kvm_vcpu
*vcpu
)
5924 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5927 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5929 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5931 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5932 skip_emulated_instruction(vcpu
);
5936 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5940 err
= kvm_rdpmc(vcpu
);
5941 kvm_complete_insn_gp(vcpu
, err
);
5946 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5948 kvm_emulate_wbinvd(vcpu
);
5952 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5954 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5955 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5957 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5958 skip_emulated_instruction(vcpu
);
5962 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5964 skip_emulated_instruction(vcpu
);
5965 WARN(1, "this should never happen\n");
5969 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5971 skip_emulated_instruction(vcpu
);
5972 WARN(1, "this should never happen\n");
5976 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5978 if (likely(fasteoi
)) {
5979 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5980 int access_type
, offset
;
5982 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5983 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5985 * Sane guest uses MOV to write EOI, with written value
5986 * not cared. So make a short-circuit here by avoiding
5987 * heavy instruction emulation.
5989 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5990 (offset
== APIC_EOI
)) {
5991 kvm_lapic_set_eoi(vcpu
);
5992 skip_emulated_instruction(vcpu
);
5996 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5999 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6001 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6002 int vector
= exit_qualification
& 0xff;
6004 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6005 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6009 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6011 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6012 u32 offset
= exit_qualification
& 0xfff;
6014 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6015 kvm_apic_write_nodecode(vcpu
, offset
);
6019 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6021 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6022 unsigned long exit_qualification
;
6023 bool has_error_code
= false;
6026 int reason
, type
, idt_v
, idt_index
;
6028 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6029 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6030 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6032 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6034 reason
= (u32
)exit_qualification
>> 30;
6035 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6037 case INTR_TYPE_NMI_INTR
:
6038 vcpu
->arch
.nmi_injected
= false;
6039 vmx_set_nmi_mask(vcpu
, true);
6041 case INTR_TYPE_EXT_INTR
:
6042 case INTR_TYPE_SOFT_INTR
:
6043 kvm_clear_interrupt_queue(vcpu
);
6045 case INTR_TYPE_HARD_EXCEPTION
:
6046 if (vmx
->idt_vectoring_info
&
6047 VECTORING_INFO_DELIVER_CODE_MASK
) {
6048 has_error_code
= true;
6050 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6053 case INTR_TYPE_SOFT_EXCEPTION
:
6054 kvm_clear_exception_queue(vcpu
);
6060 tss_selector
= exit_qualification
;
6062 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6063 type
!= INTR_TYPE_EXT_INTR
&&
6064 type
!= INTR_TYPE_NMI_INTR
))
6065 skip_emulated_instruction(vcpu
);
6067 if (kvm_task_switch(vcpu
, tss_selector
,
6068 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6069 has_error_code
, error_code
) == EMULATE_FAIL
) {
6070 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6071 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6072 vcpu
->run
->internal
.ndata
= 0;
6077 * TODO: What about debug traps on tss switch?
6078 * Are we supposed to inject them and update dr6?
6084 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6086 unsigned long exit_qualification
;
6091 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6093 gla_validity
= (exit_qualification
>> 7) & 0x3;
6094 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
6095 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6096 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6097 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6098 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6099 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6100 (long unsigned int)exit_qualification
);
6101 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6102 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6107 * EPT violation happened while executing iret from NMI,
6108 * "blocked by NMI" bit has to be set before next VM entry.
6109 * There are errata that may cause this bit to not be set:
6112 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6113 cpu_has_virtual_nmis() &&
6114 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6115 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6117 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6118 trace_kvm_page_fault(gpa
, exit_qualification
);
6120 /* It is a write fault? */
6121 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
6122 /* It is a fetch fault? */
6123 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6124 /* ept page table is present? */
6125 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
6127 vcpu
->arch
.exit_qualification
= exit_qualification
;
6129 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6132 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6137 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6138 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6139 skip_emulated_instruction(vcpu
);
6140 trace_kvm_fast_mmio(gpa
);
6144 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6145 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6146 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6149 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6150 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6152 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6155 /* It is the real ept misconfig */
6158 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6159 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6164 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6166 u32 cpu_based_vm_exec_control
;
6168 /* clear pending NMI */
6169 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6170 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6171 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6172 ++vcpu
->stat
.nmi_window_exits
;
6173 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6178 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6180 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6181 enum emulation_result err
= EMULATE_DONE
;
6184 bool intr_window_requested
;
6185 unsigned count
= 130;
6187 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6188 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6190 while (vmx
->emulation_required
&& count
-- != 0) {
6191 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6192 return handle_interrupt_window(&vmx
->vcpu
);
6194 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6197 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6199 if (err
== EMULATE_USER_EXIT
) {
6200 ++vcpu
->stat
.mmio_exits
;
6205 if (err
!= EMULATE_DONE
) {
6206 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6207 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6208 vcpu
->run
->internal
.ndata
= 0;
6212 if (vcpu
->arch
.halt_request
) {
6213 vcpu
->arch
.halt_request
= 0;
6214 ret
= kvm_vcpu_halt(vcpu
);
6218 if (signal_pending(current
))
6228 static int __grow_ple_window(int val
)
6230 if (ple_window_grow
< 1)
6233 val
= min(val
, ple_window_actual_max
);
6235 if (ple_window_grow
< ple_window
)
6236 val
*= ple_window_grow
;
6238 val
+= ple_window_grow
;
6243 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6248 if (modifier
< ple_window
)
6253 return max(val
, minimum
);
6256 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6258 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6259 int old
= vmx
->ple_window
;
6261 vmx
->ple_window
= __grow_ple_window(old
);
6263 if (vmx
->ple_window
!= old
)
6264 vmx
->ple_window_dirty
= true;
6266 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6269 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6271 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6272 int old
= vmx
->ple_window
;
6274 vmx
->ple_window
= __shrink_ple_window(old
,
6275 ple_window_shrink
, ple_window
);
6277 if (vmx
->ple_window
!= old
)
6278 vmx
->ple_window_dirty
= true;
6280 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6284 * ple_window_actual_max is computed to be one grow_ple_window() below
6285 * ple_window_max. (See __grow_ple_window for the reason.)
6286 * This prevents overflows, because ple_window_max is int.
6287 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6289 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6291 static void update_ple_window_actual_max(void)
6293 ple_window_actual_max
=
6294 __shrink_ple_window(max(ple_window_max
, ple_window
),
6295 ple_window_grow
, INT_MIN
);
6299 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6301 static void wakeup_handler(void)
6303 struct kvm_vcpu
*vcpu
;
6304 int cpu
= smp_processor_id();
6306 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6307 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6308 blocked_vcpu_list
) {
6309 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6311 if (pi_test_on(pi_desc
) == 1)
6312 kvm_vcpu_kick(vcpu
);
6314 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6317 static __init
int hardware_setup(void)
6319 int r
= -ENOMEM
, i
, msr
;
6321 rdmsrl_safe(MSR_EFER
, &host_efer
);
6323 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6324 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6326 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6327 if (!vmx_io_bitmap_a
)
6330 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6331 if (!vmx_io_bitmap_b
)
6334 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6335 if (!vmx_msr_bitmap_legacy
)
6338 vmx_msr_bitmap_legacy_x2apic
=
6339 (unsigned long *)__get_free_page(GFP_KERNEL
);
6340 if (!vmx_msr_bitmap_legacy_x2apic
)
6343 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6344 if (!vmx_msr_bitmap_longmode
)
6347 vmx_msr_bitmap_longmode_x2apic
=
6348 (unsigned long *)__get_free_page(GFP_KERNEL
);
6349 if (!vmx_msr_bitmap_longmode_x2apic
)
6353 vmx_msr_bitmap_nested
=
6354 (unsigned long *)__get_free_page(GFP_KERNEL
);
6355 if (!vmx_msr_bitmap_nested
)
6359 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6360 if (!vmx_vmread_bitmap
)
6363 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6364 if (!vmx_vmwrite_bitmap
)
6367 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6368 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6371 * Allow direct access to the PC debug port (it is often used for I/O
6372 * delays, but the vmexits simply slow things down).
6374 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6375 clear_bit(0x80, vmx_io_bitmap_a
);
6377 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6379 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6380 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6382 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6384 if (setup_vmcs_config(&vmcs_config
) < 0) {
6389 if (boot_cpu_has(X86_FEATURE_NX
))
6390 kvm_enable_efer_bits(EFER_NX
);
6392 if (!cpu_has_vmx_vpid())
6394 if (!cpu_has_vmx_shadow_vmcs())
6395 enable_shadow_vmcs
= 0;
6396 if (enable_shadow_vmcs
)
6397 init_vmcs_shadow_fields();
6399 if (!cpu_has_vmx_ept() ||
6400 !cpu_has_vmx_ept_4levels()) {
6402 enable_unrestricted_guest
= 0;
6403 enable_ept_ad_bits
= 0;
6406 if (!cpu_has_vmx_ept_ad_bits())
6407 enable_ept_ad_bits
= 0;
6409 if (!cpu_has_vmx_unrestricted_guest())
6410 enable_unrestricted_guest
= 0;
6412 if (!cpu_has_vmx_flexpriority())
6413 flexpriority_enabled
= 0;
6416 * set_apic_access_page_addr() is used to reload apic access
6417 * page upon invalidation. No need to do anything if not
6418 * using the APIC_ACCESS_ADDR VMCS field.
6420 if (!flexpriority_enabled
)
6421 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6423 if (!cpu_has_vmx_tpr_shadow())
6424 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6426 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6427 kvm_disable_largepages();
6429 if (!cpu_has_vmx_ple())
6432 if (!cpu_has_vmx_apicv())
6435 if (cpu_has_vmx_tsc_scaling()) {
6436 kvm_has_tsc_control
= true;
6437 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6438 kvm_tsc_scaling_ratio_frac_bits
= 48;
6441 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6442 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6443 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6444 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6445 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6446 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6447 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6449 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6450 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6451 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6452 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6454 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6456 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6457 vmx_disable_intercept_msr_read_x2apic(msr
);
6459 /* According SDM, in x2apic mode, the whole id reg is used. But in
6460 * KVM, it only use the highest eight bits. Need to intercept it */
6461 vmx_enable_intercept_msr_read_x2apic(0x802);
6463 vmx_enable_intercept_msr_read_x2apic(0x839);
6465 vmx_disable_intercept_msr_write_x2apic(0x808);
6467 vmx_disable_intercept_msr_write_x2apic(0x80b);
6469 vmx_disable_intercept_msr_write_x2apic(0x83f);
6472 kvm_mmu_set_mask_ptes(0ull,
6473 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6474 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6475 0ull, VMX_EPT_EXECUTABLE_MASK
);
6476 ept_set_mmio_spte_mask();
6481 update_ple_window_actual_max();
6484 * Only enable PML when hardware supports PML feature, and both EPT
6485 * and EPT A/D bit features are enabled -- PML depends on them to work.
6487 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6491 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6492 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6493 kvm_x86_ops
->flush_log_dirty
= NULL
;
6494 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6497 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6500 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6501 cpu_preemption_timer_multi
=
6502 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6504 kvm_x86_ops
->set_hv_timer
= NULL
;
6505 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6508 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6510 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6512 return alloc_kvm_area();
6515 free_page((unsigned long)vmx_vmwrite_bitmap
);
6517 free_page((unsigned long)vmx_vmread_bitmap
);
6520 free_page((unsigned long)vmx_msr_bitmap_nested
);
6522 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6524 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6526 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6528 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6530 free_page((unsigned long)vmx_io_bitmap_b
);
6532 free_page((unsigned long)vmx_io_bitmap_a
);
6537 static __exit
void hardware_unsetup(void)
6539 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6540 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6541 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6542 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6543 free_page((unsigned long)vmx_io_bitmap_b
);
6544 free_page((unsigned long)vmx_io_bitmap_a
);
6545 free_page((unsigned long)vmx_vmwrite_bitmap
);
6546 free_page((unsigned long)vmx_vmread_bitmap
);
6548 free_page((unsigned long)vmx_msr_bitmap_nested
);
6554 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6555 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6557 static int handle_pause(struct kvm_vcpu
*vcpu
)
6560 grow_ple_window(vcpu
);
6562 skip_emulated_instruction(vcpu
);
6563 kvm_vcpu_on_spin(vcpu
);
6568 static int handle_nop(struct kvm_vcpu
*vcpu
)
6570 skip_emulated_instruction(vcpu
);
6574 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6576 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6577 return handle_nop(vcpu
);
6580 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6585 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6587 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6588 return handle_nop(vcpu
);
6592 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6593 * We could reuse a single VMCS for all the L2 guests, but we also want the
6594 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6595 * allows keeping them loaded on the processor, and in the future will allow
6596 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6597 * every entry if they never change.
6598 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6599 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6601 * The following functions allocate and free a vmcs02 in this pool.
6604 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6605 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6607 struct vmcs02_list
*item
;
6608 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6609 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6610 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6611 return &item
->vmcs02
;
6614 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6615 /* Recycle the least recently used VMCS. */
6616 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6617 struct vmcs02_list
, list
);
6618 item
->vmptr
= vmx
->nested
.current_vmptr
;
6619 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6620 return &item
->vmcs02
;
6623 /* Create a new VMCS */
6624 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6627 item
->vmcs02
.vmcs
= alloc_vmcs();
6628 if (!item
->vmcs02
.vmcs
) {
6632 loaded_vmcs_init(&item
->vmcs02
);
6633 item
->vmptr
= vmx
->nested
.current_vmptr
;
6634 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6635 vmx
->nested
.vmcs02_num
++;
6636 return &item
->vmcs02
;
6639 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6640 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6642 struct vmcs02_list
*item
;
6643 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6644 if (item
->vmptr
== vmptr
) {
6645 free_loaded_vmcs(&item
->vmcs02
);
6646 list_del(&item
->list
);
6648 vmx
->nested
.vmcs02_num
--;
6654 * Free all VMCSs saved for this vcpu, except the one pointed by
6655 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6656 * must be &vmx->vmcs01.
6658 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6660 struct vmcs02_list
*item
, *n
;
6662 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6663 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6665 * Something will leak if the above WARN triggers. Better than
6668 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6671 free_loaded_vmcs(&item
->vmcs02
);
6672 list_del(&item
->list
);
6674 vmx
->nested
.vmcs02_num
--;
6679 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6680 * set the success or error code of an emulated VMX instruction, as specified
6681 * by Vol 2B, VMX Instruction Reference, "Conventions".
6683 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6685 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6686 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6687 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6690 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6692 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6693 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6694 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6698 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6699 u32 vm_instruction_error
)
6701 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6703 * failValid writes the error number to the current VMCS, which
6704 * can't be done there isn't a current VMCS.
6706 nested_vmx_failInvalid(vcpu
);
6709 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6710 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6711 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6713 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6715 * We don't need to force a shadow sync because
6716 * VM_INSTRUCTION_ERROR is not shadowed
6720 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6722 /* TODO: not to reset guest simply here. */
6723 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6724 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6727 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6729 struct vcpu_vmx
*vmx
=
6730 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6732 vmx
->nested
.preemption_timer_expired
= true;
6733 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6734 kvm_vcpu_kick(&vmx
->vcpu
);
6736 return HRTIMER_NORESTART
;
6740 * Decode the memory-address operand of a vmx instruction, as recorded on an
6741 * exit caused by such an instruction (run by a guest hypervisor).
6742 * On success, returns 0. When the operand is invalid, returns 1 and throws
6745 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6746 unsigned long exit_qualification
,
6747 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6751 struct kvm_segment s
;
6754 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6755 * Execution", on an exit, vmx_instruction_info holds most of the
6756 * addressing components of the operand. Only the displacement part
6757 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6758 * For how an actual address is calculated from all these components,
6759 * refer to Vol. 1, "Operand Addressing".
6761 int scaling
= vmx_instruction_info
& 3;
6762 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6763 bool is_reg
= vmx_instruction_info
& (1u << 10);
6764 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6765 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6766 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6767 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6768 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6771 kvm_queue_exception(vcpu
, UD_VECTOR
);
6775 /* Addr = segment_base + offset */
6776 /* offset = base + [index * scale] + displacement */
6777 off
= exit_qualification
; /* holds the displacement */
6779 off
+= kvm_register_read(vcpu
, base_reg
);
6781 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6782 vmx_get_segment(vcpu
, &s
, seg_reg
);
6783 *ret
= s
.base
+ off
;
6785 if (addr_size
== 1) /* 32 bit */
6788 /* Checks for #GP/#SS exceptions. */
6790 if (is_protmode(vcpu
)) {
6791 /* Protected mode: apply checks for segment validity in the
6793 * - segment type check (#GP(0) may be thrown)
6794 * - usability check (#GP(0)/#SS(0))
6795 * - limit check (#GP(0)/#SS(0))
6798 /* #GP(0) if the destination operand is located in a
6799 * read-only data segment or any code segment.
6801 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6803 /* #GP(0) if the source operand is located in an
6804 * execute-only code segment
6806 exn
= ((s
.type
& 0xa) == 8);
6809 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6812 if (is_long_mode(vcpu
)) {
6813 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6814 * non-canonical form. This is an only check for long mode.
6816 exn
= is_noncanonical_address(*ret
);
6817 } else if (is_protmode(vcpu
)) {
6818 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6820 exn
= (s
.unusable
!= 0);
6821 /* Protected mode: #GP(0)/#SS(0) if the memory
6822 * operand is outside the segment limit.
6824 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6827 kvm_queue_exception_e(vcpu
,
6828 seg_reg
== VCPU_SREG_SS
?
6829 SS_VECTOR
: GP_VECTOR
,
6838 * This function performs the various checks including
6839 * - if it's 4KB aligned
6840 * - No bits beyond the physical address width are set
6841 * - Returns 0 on success or else 1
6842 * (Intel SDM Section 30.3)
6844 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6849 struct x86_exception e
;
6851 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6852 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6854 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6855 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6858 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6859 sizeof(vmptr
), &e
)) {
6860 kvm_inject_page_fault(vcpu
, &e
);
6864 switch (exit_reason
) {
6865 case EXIT_REASON_VMON
:
6868 * The first 4 bytes of VMXON region contain the supported
6869 * VMCS revision identifier
6871 * Note - IA32_VMX_BASIC[48] will never be 1
6872 * for the nested case;
6873 * which replaces physical address width with 32
6876 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6877 nested_vmx_failInvalid(vcpu
);
6878 skip_emulated_instruction(vcpu
);
6882 page
= nested_get_page(vcpu
, vmptr
);
6884 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6885 nested_vmx_failInvalid(vcpu
);
6887 skip_emulated_instruction(vcpu
);
6891 vmx
->nested
.vmxon_ptr
= vmptr
;
6893 case EXIT_REASON_VMCLEAR
:
6894 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6895 nested_vmx_failValid(vcpu
,
6896 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6897 skip_emulated_instruction(vcpu
);
6901 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6902 nested_vmx_failValid(vcpu
,
6903 VMXERR_VMCLEAR_VMXON_POINTER
);
6904 skip_emulated_instruction(vcpu
);
6908 case EXIT_REASON_VMPTRLD
:
6909 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6910 nested_vmx_failValid(vcpu
,
6911 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6912 skip_emulated_instruction(vcpu
);
6916 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6917 nested_vmx_failValid(vcpu
,
6918 VMXERR_VMCLEAR_VMXON_POINTER
);
6919 skip_emulated_instruction(vcpu
);
6924 return 1; /* shouldn't happen */
6933 * Emulate the VMXON instruction.
6934 * Currently, we just remember that VMX is active, and do not save or even
6935 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6936 * do not currently need to store anything in that guest-allocated memory
6937 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6938 * argument is different from the VMXON pointer (which the spec says they do).
6940 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6942 struct kvm_segment cs
;
6943 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6944 struct vmcs
*shadow_vmcs
;
6945 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6946 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6948 /* The Intel VMX Instruction Reference lists a bunch of bits that
6949 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6950 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6951 * Otherwise, we should fail with #UD. We test these now:
6953 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6954 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6955 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6956 kvm_queue_exception(vcpu
, UD_VECTOR
);
6960 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6961 if (is_long_mode(vcpu
) && !cs
.l
) {
6962 kvm_queue_exception(vcpu
, UD_VECTOR
);
6966 if (vmx_get_cpl(vcpu
)) {
6967 kvm_inject_gp(vcpu
, 0);
6971 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6974 if (vmx
->nested
.vmxon
) {
6975 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6976 skip_emulated_instruction(vcpu
);
6980 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6981 != VMXON_NEEDED_FEATURES
) {
6982 kvm_inject_gp(vcpu
, 0);
6986 if (enable_shadow_vmcs
) {
6987 shadow_vmcs
= alloc_vmcs();
6990 /* mark vmcs as shadow */
6991 shadow_vmcs
->revision_id
|= (1u << 31);
6992 /* init shadow vmcs */
6993 vmcs_clear(shadow_vmcs
);
6994 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6997 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6998 vmx
->nested
.vmcs02_num
= 0;
7000 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7002 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7004 vmx
->nested
.vmxon
= true;
7006 skip_emulated_instruction(vcpu
);
7007 nested_vmx_succeed(vcpu
);
7012 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7013 * for running VMX instructions (except VMXON, whose prerequisites are
7014 * slightly different). It also specifies what exception to inject otherwise.
7016 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7018 struct kvm_segment cs
;
7019 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7021 if (!vmx
->nested
.vmxon
) {
7022 kvm_queue_exception(vcpu
, UD_VECTOR
);
7026 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7027 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
7028 (is_long_mode(vcpu
) && !cs
.l
)) {
7029 kvm_queue_exception(vcpu
, UD_VECTOR
);
7033 if (vmx_get_cpl(vcpu
)) {
7034 kvm_inject_gp(vcpu
, 0);
7041 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7043 if (vmx
->nested
.current_vmptr
== -1ull)
7046 /* current_vmptr and current_vmcs12 are always set/reset together */
7047 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7050 if (enable_shadow_vmcs
) {
7051 /* copy to memory all shadowed fields in case
7052 they were modified */
7053 copy_shadow_to_vmcs12(vmx
);
7054 vmx
->nested
.sync_shadow_vmcs
= false;
7055 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7056 SECONDARY_EXEC_SHADOW_VMCS
);
7057 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7059 vmx
->nested
.posted_intr_nv
= -1;
7060 kunmap(vmx
->nested
.current_vmcs12_page
);
7061 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7062 vmx
->nested
.current_vmptr
= -1ull;
7063 vmx
->nested
.current_vmcs12
= NULL
;
7067 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7068 * just stops using VMX.
7070 static void free_nested(struct vcpu_vmx
*vmx
)
7072 if (!vmx
->nested
.vmxon
)
7075 vmx
->nested
.vmxon
= false;
7076 free_vpid(vmx
->nested
.vpid02
);
7077 nested_release_vmcs12(vmx
);
7078 if (enable_shadow_vmcs
)
7079 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
7080 /* Unpin physical memory we referred to in current vmcs02 */
7081 if (vmx
->nested
.apic_access_page
) {
7082 nested_release_page(vmx
->nested
.apic_access_page
);
7083 vmx
->nested
.apic_access_page
= NULL
;
7085 if (vmx
->nested
.virtual_apic_page
) {
7086 nested_release_page(vmx
->nested
.virtual_apic_page
);
7087 vmx
->nested
.virtual_apic_page
= NULL
;
7089 if (vmx
->nested
.pi_desc_page
) {
7090 kunmap(vmx
->nested
.pi_desc_page
);
7091 nested_release_page(vmx
->nested
.pi_desc_page
);
7092 vmx
->nested
.pi_desc_page
= NULL
;
7093 vmx
->nested
.pi_desc
= NULL
;
7096 nested_free_all_saved_vmcss(vmx
);
7099 /* Emulate the VMXOFF instruction */
7100 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7102 if (!nested_vmx_check_permission(vcpu
))
7104 free_nested(to_vmx(vcpu
));
7105 skip_emulated_instruction(vcpu
);
7106 nested_vmx_succeed(vcpu
);
7110 /* Emulate the VMCLEAR instruction */
7111 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7113 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7115 struct vmcs12
*vmcs12
;
7118 if (!nested_vmx_check_permission(vcpu
))
7121 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7124 if (vmptr
== vmx
->nested
.current_vmptr
)
7125 nested_release_vmcs12(vmx
);
7127 page
= nested_get_page(vcpu
, vmptr
);
7130 * For accurate processor emulation, VMCLEAR beyond available
7131 * physical memory should do nothing at all. However, it is
7132 * possible that a nested vmx bug, not a guest hypervisor bug,
7133 * resulted in this case, so let's shut down before doing any
7136 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7139 vmcs12
= kmap(page
);
7140 vmcs12
->launch_state
= 0;
7142 nested_release_page(page
);
7144 nested_free_vmcs02(vmx
, vmptr
);
7146 skip_emulated_instruction(vcpu
);
7147 nested_vmx_succeed(vcpu
);
7151 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7153 /* Emulate the VMLAUNCH instruction */
7154 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7156 return nested_vmx_run(vcpu
, true);
7159 /* Emulate the VMRESUME instruction */
7160 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7163 return nested_vmx_run(vcpu
, false);
7166 enum vmcs_field_type
{
7167 VMCS_FIELD_TYPE_U16
= 0,
7168 VMCS_FIELD_TYPE_U64
= 1,
7169 VMCS_FIELD_TYPE_U32
= 2,
7170 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7173 static inline int vmcs_field_type(unsigned long field
)
7175 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7176 return VMCS_FIELD_TYPE_U32
;
7177 return (field
>> 13) & 0x3 ;
7180 static inline int vmcs_field_readonly(unsigned long field
)
7182 return (((field
>> 10) & 0x3) == 1);
7186 * Read a vmcs12 field. Since these can have varying lengths and we return
7187 * one type, we chose the biggest type (u64) and zero-extend the return value
7188 * to that size. Note that the caller, handle_vmread, might need to use only
7189 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7190 * 64-bit fields are to be returned).
7192 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7193 unsigned long field
, u64
*ret
)
7195 short offset
= vmcs_field_to_offset(field
);
7201 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7203 switch (vmcs_field_type(field
)) {
7204 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7205 *ret
= *((natural_width
*)p
);
7207 case VMCS_FIELD_TYPE_U16
:
7210 case VMCS_FIELD_TYPE_U32
:
7213 case VMCS_FIELD_TYPE_U64
:
7223 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7224 unsigned long field
, u64 field_value
){
7225 short offset
= vmcs_field_to_offset(field
);
7226 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7230 switch (vmcs_field_type(field
)) {
7231 case VMCS_FIELD_TYPE_U16
:
7232 *(u16
*)p
= field_value
;
7234 case VMCS_FIELD_TYPE_U32
:
7235 *(u32
*)p
= field_value
;
7237 case VMCS_FIELD_TYPE_U64
:
7238 *(u64
*)p
= field_value
;
7240 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7241 *(natural_width
*)p
= field_value
;
7250 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7253 unsigned long field
;
7255 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7256 const unsigned long *fields
= shadow_read_write_fields
;
7257 const int num_fields
= max_shadow_read_write_fields
;
7261 vmcs_load(shadow_vmcs
);
7263 for (i
= 0; i
< num_fields
; i
++) {
7265 switch (vmcs_field_type(field
)) {
7266 case VMCS_FIELD_TYPE_U16
:
7267 field_value
= vmcs_read16(field
);
7269 case VMCS_FIELD_TYPE_U32
:
7270 field_value
= vmcs_read32(field
);
7272 case VMCS_FIELD_TYPE_U64
:
7273 field_value
= vmcs_read64(field
);
7275 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7276 field_value
= vmcs_readl(field
);
7282 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7285 vmcs_clear(shadow_vmcs
);
7286 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7291 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7293 const unsigned long *fields
[] = {
7294 shadow_read_write_fields
,
7295 shadow_read_only_fields
7297 const int max_fields
[] = {
7298 max_shadow_read_write_fields
,
7299 max_shadow_read_only_fields
7302 unsigned long field
;
7303 u64 field_value
= 0;
7304 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7306 vmcs_load(shadow_vmcs
);
7308 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7309 for (i
= 0; i
< max_fields
[q
]; i
++) {
7310 field
= fields
[q
][i
];
7311 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7313 switch (vmcs_field_type(field
)) {
7314 case VMCS_FIELD_TYPE_U16
:
7315 vmcs_write16(field
, (u16
)field_value
);
7317 case VMCS_FIELD_TYPE_U32
:
7318 vmcs_write32(field
, (u32
)field_value
);
7320 case VMCS_FIELD_TYPE_U64
:
7321 vmcs_write64(field
, (u64
)field_value
);
7323 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7324 vmcs_writel(field
, (long)field_value
);
7333 vmcs_clear(shadow_vmcs
);
7334 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7338 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7339 * used before) all generate the same failure when it is missing.
7341 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7343 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7344 if (vmx
->nested
.current_vmptr
== -1ull) {
7345 nested_vmx_failInvalid(vcpu
);
7346 skip_emulated_instruction(vcpu
);
7352 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7354 unsigned long field
;
7356 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7357 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7360 if (!nested_vmx_check_permission(vcpu
) ||
7361 !nested_vmx_check_vmcs12(vcpu
))
7364 /* Decode instruction info and find the field to read */
7365 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7366 /* Read the field, zero-extended to a u64 field_value */
7367 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7368 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7369 skip_emulated_instruction(vcpu
);
7373 * Now copy part of this value to register or memory, as requested.
7374 * Note that the number of bits actually copied is 32 or 64 depending
7375 * on the guest's mode (32 or 64 bit), not on the given field's length.
7377 if (vmx_instruction_info
& (1u << 10)) {
7378 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7381 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7382 vmx_instruction_info
, true, &gva
))
7384 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7385 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7386 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7389 nested_vmx_succeed(vcpu
);
7390 skip_emulated_instruction(vcpu
);
7395 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7397 unsigned long field
;
7399 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7400 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7401 /* The value to write might be 32 or 64 bits, depending on L1's long
7402 * mode, and eventually we need to write that into a field of several
7403 * possible lengths. The code below first zero-extends the value to 64
7404 * bit (field_value), and then copies only the appropriate number of
7405 * bits into the vmcs12 field.
7407 u64 field_value
= 0;
7408 struct x86_exception e
;
7410 if (!nested_vmx_check_permission(vcpu
) ||
7411 !nested_vmx_check_vmcs12(vcpu
))
7414 if (vmx_instruction_info
& (1u << 10))
7415 field_value
= kvm_register_readl(vcpu
,
7416 (((vmx_instruction_info
) >> 3) & 0xf));
7418 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7419 vmx_instruction_info
, false, &gva
))
7421 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7422 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7423 kvm_inject_page_fault(vcpu
, &e
);
7429 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7430 if (vmcs_field_readonly(field
)) {
7431 nested_vmx_failValid(vcpu
,
7432 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7433 skip_emulated_instruction(vcpu
);
7437 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7438 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7439 skip_emulated_instruction(vcpu
);
7443 nested_vmx_succeed(vcpu
);
7444 skip_emulated_instruction(vcpu
);
7448 /* Emulate the VMPTRLD instruction */
7449 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7451 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7454 if (!nested_vmx_check_permission(vcpu
))
7457 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7460 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7461 struct vmcs12
*new_vmcs12
;
7463 page
= nested_get_page(vcpu
, vmptr
);
7465 nested_vmx_failInvalid(vcpu
);
7466 skip_emulated_instruction(vcpu
);
7469 new_vmcs12
= kmap(page
);
7470 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7472 nested_release_page_clean(page
);
7473 nested_vmx_failValid(vcpu
,
7474 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7475 skip_emulated_instruction(vcpu
);
7479 nested_release_vmcs12(vmx
);
7480 vmx
->nested
.current_vmptr
= vmptr
;
7481 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7482 vmx
->nested
.current_vmcs12_page
= page
;
7483 if (enable_shadow_vmcs
) {
7484 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7485 SECONDARY_EXEC_SHADOW_VMCS
);
7486 vmcs_write64(VMCS_LINK_POINTER
,
7487 __pa(vmx
->nested
.current_shadow_vmcs
));
7488 vmx
->nested
.sync_shadow_vmcs
= true;
7492 nested_vmx_succeed(vcpu
);
7493 skip_emulated_instruction(vcpu
);
7497 /* Emulate the VMPTRST instruction */
7498 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7500 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7501 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7503 struct x86_exception e
;
7505 if (!nested_vmx_check_permission(vcpu
))
7508 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7509 vmx_instruction_info
, true, &vmcs_gva
))
7511 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7512 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7513 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7515 kvm_inject_page_fault(vcpu
, &e
);
7518 nested_vmx_succeed(vcpu
);
7519 skip_emulated_instruction(vcpu
);
7523 /* Emulate the INVEPT instruction */
7524 static int handle_invept(struct kvm_vcpu
*vcpu
)
7526 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7527 u32 vmx_instruction_info
, types
;
7530 struct x86_exception e
;
7535 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7536 SECONDARY_EXEC_ENABLE_EPT
) ||
7537 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7538 kvm_queue_exception(vcpu
, UD_VECTOR
);
7542 if (!nested_vmx_check_permission(vcpu
))
7545 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7546 kvm_queue_exception(vcpu
, UD_VECTOR
);
7550 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7551 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7553 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7555 if (!(types
& (1UL << type
))) {
7556 nested_vmx_failValid(vcpu
,
7557 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7558 skip_emulated_instruction(vcpu
);
7562 /* According to the Intel VMX instruction reference, the memory
7563 * operand is read even if it isn't needed (e.g., for type==global)
7565 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7566 vmx_instruction_info
, false, &gva
))
7568 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7569 sizeof(operand
), &e
)) {
7570 kvm_inject_page_fault(vcpu
, &e
);
7575 case VMX_EPT_EXTENT_GLOBAL
:
7576 kvm_mmu_sync_roots(vcpu
);
7577 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7578 nested_vmx_succeed(vcpu
);
7581 /* Trap single context invalidation invept calls */
7586 skip_emulated_instruction(vcpu
);
7590 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7592 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7593 u32 vmx_instruction_info
;
7594 unsigned long type
, types
;
7596 struct x86_exception e
;
7599 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7600 SECONDARY_EXEC_ENABLE_VPID
) ||
7601 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7602 kvm_queue_exception(vcpu
, UD_VECTOR
);
7606 if (!nested_vmx_check_permission(vcpu
))
7609 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7610 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7612 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7614 if (!(types
& (1UL << type
))) {
7615 nested_vmx_failValid(vcpu
,
7616 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7617 skip_emulated_instruction(vcpu
);
7621 /* according to the intel vmx instruction reference, the memory
7622 * operand is read even if it isn't needed (e.g., for type==global)
7624 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7625 vmx_instruction_info
, false, &gva
))
7627 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7629 kvm_inject_page_fault(vcpu
, &e
);
7634 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7636 * Old versions of KVM use the single-context version so we
7637 * have to support it; just treat it the same as all-context.
7639 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7640 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7641 nested_vmx_succeed(vcpu
);
7644 /* Trap individual address invalidation invvpid calls */
7649 skip_emulated_instruction(vcpu
);
7653 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7655 unsigned long exit_qualification
;
7657 trace_kvm_pml_full(vcpu
->vcpu_id
);
7659 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7662 * PML buffer FULL happened while executing iret from NMI,
7663 * "blocked by NMI" bit has to be set before next VM entry.
7665 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7666 cpu_has_virtual_nmis() &&
7667 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7668 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7669 GUEST_INTR_STATE_NMI
);
7672 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7673 * here.., and there's no userspace involvement needed for PML.
7678 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7680 /* we never catch pcommit instruct for L1 guest. */
7685 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7687 kvm_lapic_expired_hv_timer(vcpu
);
7692 * The exit handlers return 1 if the exit was handled fully and guest execution
7693 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7694 * to be done to userspace and return 0.
7696 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7697 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7698 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7699 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7700 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7701 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7702 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7703 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7704 [EXIT_REASON_CPUID
] = handle_cpuid
,
7705 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7706 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7707 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7708 [EXIT_REASON_HLT
] = handle_halt
,
7709 [EXIT_REASON_INVD
] = handle_invd
,
7710 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7711 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7712 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7713 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7714 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7715 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7716 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7717 [EXIT_REASON_VMREAD
] = handle_vmread
,
7718 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7719 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7720 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7721 [EXIT_REASON_VMON
] = handle_vmon
,
7722 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7723 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7724 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7725 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7726 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7727 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7728 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7729 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7730 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7731 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7732 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7733 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7734 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7735 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7736 [EXIT_REASON_INVEPT
] = handle_invept
,
7737 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7738 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7739 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7740 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7741 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7742 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7745 static const int kvm_vmx_max_exit_handlers
=
7746 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7748 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7749 struct vmcs12
*vmcs12
)
7751 unsigned long exit_qualification
;
7752 gpa_t bitmap
, last_bitmap
;
7757 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7758 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7760 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7762 port
= exit_qualification
>> 16;
7763 size
= (exit_qualification
& 7) + 1;
7765 last_bitmap
= (gpa_t
)-1;
7770 bitmap
= vmcs12
->io_bitmap_a
;
7771 else if (port
< 0x10000)
7772 bitmap
= vmcs12
->io_bitmap_b
;
7775 bitmap
+= (port
& 0x7fff) / 8;
7777 if (last_bitmap
!= bitmap
)
7778 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7780 if (b
& (1 << (port
& 7)))
7785 last_bitmap
= bitmap
;
7792 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7793 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7794 * disinterest in the current event (read or write a specific MSR) by using an
7795 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7797 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7798 struct vmcs12
*vmcs12
, u32 exit_reason
)
7800 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7803 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7807 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7808 * for the four combinations of read/write and low/high MSR numbers.
7809 * First we need to figure out which of the four to use:
7811 bitmap
= vmcs12
->msr_bitmap
;
7812 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7814 if (msr_index
>= 0xc0000000) {
7815 msr_index
-= 0xc0000000;
7819 /* Then read the msr_index'th bit from this bitmap: */
7820 if (msr_index
< 1024*8) {
7822 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7824 return 1 & (b
>> (msr_index
& 7));
7826 return true; /* let L1 handle the wrong parameter */
7830 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7831 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7832 * intercept (via guest_host_mask etc.) the current event.
7834 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7835 struct vmcs12
*vmcs12
)
7837 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7838 int cr
= exit_qualification
& 15;
7839 int reg
= (exit_qualification
>> 8) & 15;
7840 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7842 switch ((exit_qualification
>> 4) & 3) {
7843 case 0: /* mov to cr */
7846 if (vmcs12
->cr0_guest_host_mask
&
7847 (val
^ vmcs12
->cr0_read_shadow
))
7851 if ((vmcs12
->cr3_target_count
>= 1 &&
7852 vmcs12
->cr3_target_value0
== val
) ||
7853 (vmcs12
->cr3_target_count
>= 2 &&
7854 vmcs12
->cr3_target_value1
== val
) ||
7855 (vmcs12
->cr3_target_count
>= 3 &&
7856 vmcs12
->cr3_target_value2
== val
) ||
7857 (vmcs12
->cr3_target_count
>= 4 &&
7858 vmcs12
->cr3_target_value3
== val
))
7860 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7864 if (vmcs12
->cr4_guest_host_mask
&
7865 (vmcs12
->cr4_read_shadow
^ val
))
7869 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7875 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7876 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7879 case 1: /* mov from cr */
7882 if (vmcs12
->cpu_based_vm_exec_control
&
7883 CPU_BASED_CR3_STORE_EXITING
)
7887 if (vmcs12
->cpu_based_vm_exec_control
&
7888 CPU_BASED_CR8_STORE_EXITING
)
7895 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7896 * cr0. Other attempted changes are ignored, with no exit.
7898 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7899 (val
^ vmcs12
->cr0_read_shadow
))
7901 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7902 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7911 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7912 * should handle it ourselves in L0 (and then continue L2). Only call this
7913 * when in is_guest_mode (L2).
7915 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7917 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7918 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7919 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7920 u32 exit_reason
= vmx
->exit_reason
;
7922 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7923 vmcs_readl(EXIT_QUALIFICATION
),
7924 vmx
->idt_vectoring_info
,
7926 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7929 if (vmx
->nested
.nested_run_pending
)
7932 if (unlikely(vmx
->fail
)) {
7933 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7934 vmcs_read32(VM_INSTRUCTION_ERROR
));
7938 switch (exit_reason
) {
7939 case EXIT_REASON_EXCEPTION_NMI
:
7940 if (!is_exception(intr_info
))
7942 else if (is_page_fault(intr_info
))
7944 else if (is_no_device(intr_info
) &&
7945 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7947 else if (is_debug(intr_info
) &&
7949 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7951 else if (is_breakpoint(intr_info
) &&
7952 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7954 return vmcs12
->exception_bitmap
&
7955 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7956 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7958 case EXIT_REASON_TRIPLE_FAULT
:
7960 case EXIT_REASON_PENDING_INTERRUPT
:
7961 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7962 case EXIT_REASON_NMI_WINDOW
:
7963 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7964 case EXIT_REASON_TASK_SWITCH
:
7966 case EXIT_REASON_CPUID
:
7967 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7970 case EXIT_REASON_HLT
:
7971 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7972 case EXIT_REASON_INVD
:
7974 case EXIT_REASON_INVLPG
:
7975 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7976 case EXIT_REASON_RDPMC
:
7977 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7978 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7979 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7980 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7981 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7982 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7983 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7984 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7985 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7987 * VMX instructions trap unconditionally. This allows L1 to
7988 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7991 case EXIT_REASON_CR_ACCESS
:
7992 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7993 case EXIT_REASON_DR_ACCESS
:
7994 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7995 case EXIT_REASON_IO_INSTRUCTION
:
7996 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7997 case EXIT_REASON_MSR_READ
:
7998 case EXIT_REASON_MSR_WRITE
:
7999 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8000 case EXIT_REASON_INVALID_STATE
:
8002 case EXIT_REASON_MWAIT_INSTRUCTION
:
8003 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8004 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8005 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8006 case EXIT_REASON_MONITOR_INSTRUCTION
:
8007 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8008 case EXIT_REASON_PAUSE_INSTRUCTION
:
8009 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8010 nested_cpu_has2(vmcs12
,
8011 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8012 case EXIT_REASON_MCE_DURING_VMENTRY
:
8014 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8015 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8016 case EXIT_REASON_APIC_ACCESS
:
8017 return nested_cpu_has2(vmcs12
,
8018 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8019 case EXIT_REASON_APIC_WRITE
:
8020 case EXIT_REASON_EOI_INDUCED
:
8021 /* apic_write and eoi_induced should exit unconditionally. */
8023 case EXIT_REASON_EPT_VIOLATION
:
8025 * L0 always deals with the EPT violation. If nested EPT is
8026 * used, and the nested mmu code discovers that the address is
8027 * missing in the guest EPT table (EPT12), the EPT violation
8028 * will be injected with nested_ept_inject_page_fault()
8031 case EXIT_REASON_EPT_MISCONFIG
:
8033 * L2 never uses directly L1's EPT, but rather L0's own EPT
8034 * table (shadow on EPT) or a merged EPT table that L0 built
8035 * (EPT on EPT). So any problems with the structure of the
8036 * table is L0's fault.
8039 case EXIT_REASON_WBINVD
:
8040 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8041 case EXIT_REASON_XSETBV
:
8043 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8045 * This should never happen, since it is not possible to
8046 * set XSS to a non-zero value---neither in L1 nor in L2.
8047 * If if it were, XSS would have to be checked against
8048 * the XSS exit bitmap in vmcs12.
8050 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8051 case EXIT_REASON_PCOMMIT
:
8052 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
8053 case EXIT_REASON_PREEMPTION_TIMER
:
8060 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8062 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8063 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8066 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
8068 struct page
*pml_pg
;
8070 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
8074 vmx
->pml_pg
= pml_pg
;
8076 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
8077 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8082 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8085 __free_page(vmx
->pml_pg
);
8090 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8092 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8096 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8098 /* Do nothing if PML buffer is empty */
8099 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8102 /* PML index always points to next available PML buffer entity */
8103 if (pml_idx
>= PML_ENTITY_NUM
)
8108 pml_buf
= page_address(vmx
->pml_pg
);
8109 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8112 gpa
= pml_buf
[pml_idx
];
8113 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8114 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8117 /* reset PML index */
8118 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8122 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8123 * Called before reporting dirty_bitmap to userspace.
8125 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8128 struct kvm_vcpu
*vcpu
;
8130 * We only need to kick vcpu out of guest mode here, as PML buffer
8131 * is flushed at beginning of all VMEXITs, and it's obvious that only
8132 * vcpus running in guest are possible to have unflushed GPAs in PML
8135 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8136 kvm_vcpu_kick(vcpu
);
8139 static void vmx_dump_sel(char *name
, uint32_t sel
)
8141 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8142 name
, vmcs_read32(sel
),
8143 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8144 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8145 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8148 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8150 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8151 name
, vmcs_read32(limit
),
8152 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8155 static void dump_vmcs(void)
8157 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8158 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8159 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8160 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8161 u32 secondary_exec_control
= 0;
8162 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8163 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8166 if (cpu_has_secondary_exec_ctrls())
8167 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8169 pr_err("*** Guest State ***\n");
8170 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8171 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8172 vmcs_readl(CR0_GUEST_HOST_MASK
));
8173 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8174 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8175 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8176 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8177 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8179 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8180 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8181 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8182 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8184 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8185 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8186 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8187 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8188 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8189 vmcs_readl(GUEST_SYSENTER_ESP
),
8190 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8191 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8192 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8193 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8194 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8195 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8196 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8197 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8198 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8199 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8200 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8201 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8202 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8203 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8204 efer
, vmcs_read64(GUEST_IA32_PAT
));
8205 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8206 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8207 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8208 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8209 pr_err("PerfGlobCtl = 0x%016llx\n",
8210 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8211 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8212 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8213 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8214 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8215 vmcs_read32(GUEST_ACTIVITY_STATE
));
8216 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8217 pr_err("InterruptStatus = %04x\n",
8218 vmcs_read16(GUEST_INTR_STATUS
));
8220 pr_err("*** Host State ***\n");
8221 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8222 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8223 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8224 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8225 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8226 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8227 vmcs_read16(HOST_TR_SELECTOR
));
8228 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8229 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8230 vmcs_readl(HOST_TR_BASE
));
8231 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8232 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8233 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8234 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8235 vmcs_readl(HOST_CR4
));
8236 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8237 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8238 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8239 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8240 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8241 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8242 vmcs_read64(HOST_IA32_EFER
),
8243 vmcs_read64(HOST_IA32_PAT
));
8244 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8245 pr_err("PerfGlobCtl = 0x%016llx\n",
8246 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8248 pr_err("*** Control State ***\n");
8249 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8250 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8251 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8252 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8253 vmcs_read32(EXCEPTION_BITMAP
),
8254 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8255 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8256 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8257 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8258 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8259 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8260 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8261 vmcs_read32(VM_EXIT_INTR_INFO
),
8262 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8263 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8264 pr_err(" reason=%08x qualification=%016lx\n",
8265 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8266 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8267 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8268 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8269 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8270 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8271 pr_err("TSC Multiplier = 0x%016llx\n",
8272 vmcs_read64(TSC_MULTIPLIER
));
8273 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8274 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8275 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8276 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8277 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8278 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8279 n
= vmcs_read32(CR3_TARGET_COUNT
);
8280 for (i
= 0; i
+ 1 < n
; i
+= 4)
8281 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8282 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8283 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8285 pr_err("CR3 target%u=%016lx\n",
8286 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8287 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8288 pr_err("PLE Gap=%08x Window=%08x\n",
8289 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8290 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8291 pr_err("Virtual processor ID = 0x%04x\n",
8292 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8296 * The guest has exited. See if we can fix it or if we need userspace
8299 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8301 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8302 u32 exit_reason
= vmx
->exit_reason
;
8303 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8305 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8308 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8309 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8310 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8311 * mode as if vcpus is in root mode, the PML buffer must has been
8315 vmx_flush_pml_buffer(vcpu
);
8317 /* If guest state is invalid, start emulating */
8318 if (vmx
->emulation_required
)
8319 return handle_invalid_guest_state(vcpu
);
8321 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8322 nested_vmx_vmexit(vcpu
, exit_reason
,
8323 vmcs_read32(VM_EXIT_INTR_INFO
),
8324 vmcs_readl(EXIT_QUALIFICATION
));
8328 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8330 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8331 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8336 if (unlikely(vmx
->fail
)) {
8337 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8338 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8339 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8345 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8346 * delivery event since it indicates guest is accessing MMIO.
8347 * The vm-exit can be triggered again after return to guest that
8348 * will cause infinite loop.
8350 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8351 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8352 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8353 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8354 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8355 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8356 vcpu
->run
->internal
.ndata
= 2;
8357 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8358 vcpu
->run
->internal
.data
[1] = exit_reason
;
8362 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8363 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8364 get_vmcs12(vcpu
))))) {
8365 if (vmx_interrupt_allowed(vcpu
)) {
8366 vmx
->soft_vnmi_blocked
= 0;
8367 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8368 vcpu
->arch
.nmi_pending
) {
8370 * This CPU don't support us in finding the end of an
8371 * NMI-blocked window if the guest runs with IRQs
8372 * disabled. So we pull the trigger after 1 s of
8373 * futile waiting, but inform the user about this.
8375 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8376 "state on VCPU %d after 1 s timeout\n",
8377 __func__
, vcpu
->vcpu_id
);
8378 vmx
->soft_vnmi_blocked
= 0;
8382 if (exit_reason
< kvm_vmx_max_exit_handlers
8383 && kvm_vmx_exit_handlers
[exit_reason
])
8384 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8386 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8387 kvm_queue_exception(vcpu
, UD_VECTOR
);
8392 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8394 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8396 if (is_guest_mode(vcpu
) &&
8397 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8400 if (irr
== -1 || tpr
< irr
) {
8401 vmcs_write32(TPR_THRESHOLD
, 0);
8405 vmcs_write32(TPR_THRESHOLD
, irr
);
8408 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8410 u32 sec_exec_control
;
8413 * There is not point to enable virtualize x2apic without enable
8416 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8417 !kvm_vcpu_apicv_active(vcpu
))
8420 if (!cpu_need_tpr_shadow(vcpu
))
8423 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8426 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8427 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8429 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8430 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8432 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8434 vmx_set_msr_bitmap(vcpu
);
8437 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8439 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8442 * Currently we do not handle the nested case where L2 has an
8443 * APIC access page of its own; that page is still pinned.
8444 * Hence, we skip the case where the VCPU is in guest mode _and_
8445 * L1 prepared an APIC access page for L2.
8447 * For the case where L1 and L2 share the same APIC access page
8448 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8449 * in the vmcs12), this function will only update either the vmcs01
8450 * or the vmcs02. If the former, the vmcs02 will be updated by
8451 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8452 * the next L2->L1 exit.
8454 if (!is_guest_mode(vcpu
) ||
8455 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8456 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8457 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8460 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8468 status
= vmcs_read16(GUEST_INTR_STATUS
);
8470 if (max_isr
!= old
) {
8472 status
|= max_isr
<< 8;
8473 vmcs_write16(GUEST_INTR_STATUS
, status
);
8477 static void vmx_set_rvi(int vector
)
8485 status
= vmcs_read16(GUEST_INTR_STATUS
);
8486 old
= (u8
)status
& 0xff;
8487 if ((u8
)vector
!= old
) {
8489 status
|= (u8
)vector
;
8490 vmcs_write16(GUEST_INTR_STATUS
, status
);
8494 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8496 if (!is_guest_mode(vcpu
)) {
8497 vmx_set_rvi(max_irr
);
8505 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8508 if (nested_exit_on_intr(vcpu
))
8512 * Else, fall back to pre-APICv interrupt injection since L2
8513 * is run without virtual interrupt delivery.
8515 if (!kvm_event_needs_reinjection(vcpu
) &&
8516 vmx_interrupt_allowed(vcpu
)) {
8517 kvm_queue_interrupt(vcpu
, max_irr
, false);
8518 vmx_inject_irq(vcpu
);
8522 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8524 if (!kvm_vcpu_apicv_active(vcpu
))
8527 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8528 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8529 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8530 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8533 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8537 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8538 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8541 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8542 exit_intr_info
= vmx
->exit_intr_info
;
8544 /* Handle machine checks before interrupts are enabled */
8545 if (is_machine_check(exit_intr_info
))
8546 kvm_machine_check();
8548 /* We need to handle NMIs before interrupts are enabled */
8549 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8550 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8551 kvm_before_handle_nmi(&vmx
->vcpu
);
8553 kvm_after_handle_nmi(&vmx
->vcpu
);
8557 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8559 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8560 register void *__sp
asm(_ASM_SP
);
8563 * If external interrupt exists, IF bit is set in rflags/eflags on the
8564 * interrupt stack frame, and interrupt will be enabled on a return
8565 * from interrupt handler.
8567 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8568 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8569 unsigned int vector
;
8570 unsigned long entry
;
8572 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8573 #ifdef CONFIG_X86_64
8577 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8578 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8579 entry
= gate_offset(*desc
);
8581 #ifdef CONFIG_X86_64
8582 "mov %%" _ASM_SP
", %[sp]\n\t"
8583 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8588 __ASM_SIZE(push
) " $%c[cs]\n\t"
8589 "call *%[entry]\n\t"
8591 #ifdef CONFIG_X86_64
8597 [ss
]"i"(__KERNEL_DS
),
8598 [cs
]"i"(__KERNEL_CS
)
8603 static bool vmx_has_high_real_mode_segbase(void)
8605 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8608 static bool vmx_mpx_supported(void)
8610 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8611 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8614 static bool vmx_xsaves_supported(void)
8616 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8617 SECONDARY_EXEC_XSAVES
;
8620 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8625 bool idtv_info_valid
;
8627 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8629 if (cpu_has_virtual_nmis()) {
8630 if (vmx
->nmi_known_unmasked
)
8633 * Can't use vmx->exit_intr_info since we're not sure what
8634 * the exit reason is.
8636 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8637 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8638 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8640 * SDM 3: 27.7.1.2 (September 2008)
8641 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8642 * a guest IRET fault.
8643 * SDM 3: 23.2.2 (September 2008)
8644 * Bit 12 is undefined in any of the following cases:
8645 * If the VM exit sets the valid bit in the IDT-vectoring
8646 * information field.
8647 * If the VM exit is due to a double fault.
8649 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8650 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8651 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8652 GUEST_INTR_STATE_NMI
);
8654 vmx
->nmi_known_unmasked
=
8655 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8656 & GUEST_INTR_STATE_NMI
);
8657 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8658 vmx
->vnmi_blocked_time
+=
8659 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8662 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8663 u32 idt_vectoring_info
,
8664 int instr_len_field
,
8665 int error_code_field
)
8669 bool idtv_info_valid
;
8671 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8673 vcpu
->arch
.nmi_injected
= false;
8674 kvm_clear_exception_queue(vcpu
);
8675 kvm_clear_interrupt_queue(vcpu
);
8677 if (!idtv_info_valid
)
8680 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8682 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8683 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8686 case INTR_TYPE_NMI_INTR
:
8687 vcpu
->arch
.nmi_injected
= true;
8689 * SDM 3: 27.7.1.2 (September 2008)
8690 * Clear bit "block by NMI" before VM entry if a NMI
8693 vmx_set_nmi_mask(vcpu
, false);
8695 case INTR_TYPE_SOFT_EXCEPTION
:
8696 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8698 case INTR_TYPE_HARD_EXCEPTION
:
8699 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8700 u32 err
= vmcs_read32(error_code_field
);
8701 kvm_requeue_exception_e(vcpu
, vector
, err
);
8703 kvm_requeue_exception(vcpu
, vector
);
8705 case INTR_TYPE_SOFT_INTR
:
8706 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8708 case INTR_TYPE_EXT_INTR
:
8709 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8716 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8718 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8719 VM_EXIT_INSTRUCTION_LEN
,
8720 IDT_VECTORING_ERROR_CODE
);
8723 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8725 __vmx_complete_interrupts(vcpu
,
8726 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8727 VM_ENTRY_INSTRUCTION_LEN
,
8728 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8730 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8733 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8736 struct perf_guest_switch_msr
*msrs
;
8738 msrs
= perf_guest_get_msrs(&nr_msrs
);
8743 for (i
= 0; i
< nr_msrs
; i
++)
8744 if (msrs
[i
].host
== msrs
[i
].guest
)
8745 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8747 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8751 void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8753 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8757 if (vmx
->hv_deadline_tsc
== -1)
8761 if (vmx
->hv_deadline_tsc
> tscl
)
8762 /* sure to be 32 bit only because checked on set_hv_timer */
8763 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8764 cpu_preemption_timer_multi
);
8768 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8771 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8773 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8774 unsigned long debugctlmsr
, cr4
;
8776 /* Record the guest's net vcpu time for enforced NMI injections. */
8777 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8778 vmx
->entry_time
= ktime_get();
8780 /* Don't enter VMX if guest state is invalid, let the exit handler
8781 start emulation until we arrive back to a valid state */
8782 if (vmx
->emulation_required
)
8785 if (vmx
->ple_window_dirty
) {
8786 vmx
->ple_window_dirty
= false;
8787 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8790 if (vmx
->nested
.sync_shadow_vmcs
) {
8791 copy_vmcs12_to_shadow(vmx
);
8792 vmx
->nested
.sync_shadow_vmcs
= false;
8795 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8796 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8797 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8798 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8800 cr4
= cr4_read_shadow();
8801 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8802 vmcs_writel(HOST_CR4
, cr4
);
8803 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8806 /* When single-stepping over STI and MOV SS, we must clear the
8807 * corresponding interruptibility bits in the guest state. Otherwise
8808 * vmentry fails as it then expects bit 14 (BS) in pending debug
8809 * exceptions being set, but that's not correct for the guest debugging
8811 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8812 vmx_set_interrupt_shadow(vcpu
, 0);
8814 if (vmx
->guest_pkru_valid
)
8815 __write_pkru(vmx
->guest_pkru
);
8817 atomic_switch_perf_msrs(vmx
);
8818 debugctlmsr
= get_debugctlmsr();
8820 vmx_arm_hv_timer(vcpu
);
8822 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8824 /* Store host registers */
8825 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8826 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8827 "push %%" _ASM_CX
" \n\t"
8828 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8830 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8831 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8833 /* Reload cr2 if changed */
8834 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8835 "mov %%cr2, %%" _ASM_DX
" \n\t"
8836 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8838 "mov %%" _ASM_AX
", %%cr2 \n\t"
8840 /* Check if vmlaunch of vmresume is needed */
8841 "cmpl $0, %c[launched](%0) \n\t"
8842 /* Load guest registers. Don't clobber flags. */
8843 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8844 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8845 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8846 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8847 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8848 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8849 #ifdef CONFIG_X86_64
8850 "mov %c[r8](%0), %%r8 \n\t"
8851 "mov %c[r9](%0), %%r9 \n\t"
8852 "mov %c[r10](%0), %%r10 \n\t"
8853 "mov %c[r11](%0), %%r11 \n\t"
8854 "mov %c[r12](%0), %%r12 \n\t"
8855 "mov %c[r13](%0), %%r13 \n\t"
8856 "mov %c[r14](%0), %%r14 \n\t"
8857 "mov %c[r15](%0), %%r15 \n\t"
8859 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8861 /* Enter guest mode */
8863 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8865 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8867 /* Save guest registers, load host registers, keep flags */
8868 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8870 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8871 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8872 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8873 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8874 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8875 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8876 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8877 #ifdef CONFIG_X86_64
8878 "mov %%r8, %c[r8](%0) \n\t"
8879 "mov %%r9, %c[r9](%0) \n\t"
8880 "mov %%r10, %c[r10](%0) \n\t"
8881 "mov %%r11, %c[r11](%0) \n\t"
8882 "mov %%r12, %c[r12](%0) \n\t"
8883 "mov %%r13, %c[r13](%0) \n\t"
8884 "mov %%r14, %c[r14](%0) \n\t"
8885 "mov %%r15, %c[r15](%0) \n\t"
8887 "mov %%cr2, %%" _ASM_AX
" \n\t"
8888 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8890 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8891 "setbe %c[fail](%0) \n\t"
8892 ".pushsection .rodata \n\t"
8893 ".global vmx_return \n\t"
8894 "vmx_return: " _ASM_PTR
" 2b \n\t"
8896 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8897 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8898 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8899 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8900 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8901 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8902 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8903 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8904 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8905 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8906 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8907 #ifdef CONFIG_X86_64
8908 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8909 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8910 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8911 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8912 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8913 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8914 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8915 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8917 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8918 [wordsize
]"i"(sizeof(ulong
))
8920 #ifdef CONFIG_X86_64
8921 , "rax", "rbx", "rdi", "rsi"
8922 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8924 , "eax", "ebx", "edi", "esi"
8928 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8930 update_debugctlmsr(debugctlmsr
);
8932 #ifndef CONFIG_X86_64
8934 * The sysexit path does not restore ds/es, so we must set them to
8935 * a reasonable value ourselves.
8937 * We can't defer this to vmx_load_host_state() since that function
8938 * may be executed in interrupt context, which saves and restore segments
8939 * around it, nullifying its effect.
8941 loadsegment(ds
, __USER_DS
);
8942 loadsegment(es
, __USER_DS
);
8945 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8946 | (1 << VCPU_EXREG_RFLAGS
)
8947 | (1 << VCPU_EXREG_PDPTR
)
8948 | (1 << VCPU_EXREG_SEGMENTS
)
8949 | (1 << VCPU_EXREG_CR3
));
8950 vcpu
->arch
.regs_dirty
= 0;
8952 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8954 vmx
->loaded_vmcs
->launched
= 1;
8956 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8959 * eager fpu is enabled if PKEY is supported and CR4 is switched
8960 * back on host, so it is safe to read guest PKRU from current
8963 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8964 vmx
->guest_pkru
= __read_pkru();
8965 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
8966 vmx
->guest_pkru_valid
= true;
8967 __write_pkru(vmx
->host_pkru
);
8969 vmx
->guest_pkru_valid
= false;
8973 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8974 * we did not inject a still-pending event to L1 now because of
8975 * nested_run_pending, we need to re-enable this bit.
8977 if (vmx
->nested
.nested_run_pending
)
8978 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8980 vmx
->nested
.nested_run_pending
= 0;
8982 vmx_complete_atomic_exit(vmx
);
8983 vmx_recover_nmi_blocking(vmx
);
8984 vmx_complete_interrupts(vmx
);
8987 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8989 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8992 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8996 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8998 vmx_vcpu_load(vcpu
, cpu
);
9003 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9008 vmx_destroy_pml_buffer(vmx
);
9009 free_vpid(vmx
->vpid
);
9010 leave_guest_mode(vcpu
);
9011 vmx_load_vmcs01(vcpu
);
9013 free_loaded_vmcs(vmx
->loaded_vmcs
);
9014 kfree(vmx
->guest_msrs
);
9015 kvm_vcpu_uninit(vcpu
);
9016 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9019 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9022 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9026 return ERR_PTR(-ENOMEM
);
9028 vmx
->vpid
= allocate_vpid();
9030 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9034 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9035 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9039 if (!vmx
->guest_msrs
) {
9043 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9044 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9045 if (!vmx
->loaded_vmcs
->vmcs
)
9048 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9049 loaded_vmcs_init(vmx
->loaded_vmcs
);
9054 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9055 vmx
->vcpu
.cpu
= cpu
;
9056 err
= vmx_vcpu_setup(vmx
);
9057 vmx_vcpu_put(&vmx
->vcpu
);
9061 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9062 err
= alloc_apic_access_page(kvm
);
9068 if (!kvm
->arch
.ept_identity_map_addr
)
9069 kvm
->arch
.ept_identity_map_addr
=
9070 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9071 err
= init_rmode_identity_map(kvm
);
9077 nested_vmx_setup_ctls_msrs(vmx
);
9078 vmx
->nested
.vpid02
= allocate_vpid();
9081 vmx
->nested
.posted_intr_nv
= -1;
9082 vmx
->nested
.current_vmptr
= -1ull;
9083 vmx
->nested
.current_vmcs12
= NULL
;
9086 * If PML is turned on, failure on enabling PML just results in failure
9087 * of creating the vcpu, therefore we can simplify PML logic (by
9088 * avoiding dealing with cases, such as enabling PML partially on vcpus
9089 * for the guest, etc.
9092 err
= vmx_create_pml_buffer(vmx
);
9097 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9102 free_vpid(vmx
->nested
.vpid02
);
9103 free_loaded_vmcs(vmx
->loaded_vmcs
);
9105 kfree(vmx
->guest_msrs
);
9107 kvm_vcpu_uninit(&vmx
->vcpu
);
9109 free_vpid(vmx
->vpid
);
9110 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9111 return ERR_PTR(err
);
9114 static void __init
vmx_check_processor_compat(void *rtn
)
9116 struct vmcs_config vmcs_conf
;
9119 if (setup_vmcs_config(&vmcs_conf
) < 0)
9121 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9122 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9123 smp_processor_id());
9128 static int get_ept_level(void)
9130 return VMX_EPT_DEFAULT_GAW
+ 1;
9133 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9138 /* For VT-d and EPT combination
9139 * 1. MMIO: always map as UC
9141 * a. VT-d without snooping control feature: can't guarantee the
9142 * result, try to trust guest.
9143 * b. VT-d with snooping control feature: snooping control feature of
9144 * VT-d engine can guarantee the cache correctness. Just set it
9145 * to WB to keep consistent with host. So the same as item 3.
9146 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9147 * consistent with host MTRR
9150 cache
= MTRR_TYPE_UNCACHABLE
;
9154 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9155 ipat
= VMX_EPT_IPAT_BIT
;
9156 cache
= MTRR_TYPE_WRBACK
;
9160 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9161 ipat
= VMX_EPT_IPAT_BIT
;
9162 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9163 cache
= MTRR_TYPE_WRBACK
;
9165 cache
= MTRR_TYPE_UNCACHABLE
;
9169 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9172 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9175 static int vmx_get_lpage_level(void)
9177 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9178 return PT_DIRECTORY_LEVEL
;
9180 /* For shadow and EPT supported 1GB page */
9181 return PT_PDPE_LEVEL
;
9184 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9187 * These bits in the secondary execution controls field
9188 * are dynamic, the others are mostly based on the hypervisor
9189 * architecture and the guest's CPUID. Do not touch the
9193 SECONDARY_EXEC_SHADOW_VMCS
|
9194 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9195 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9197 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9199 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9200 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9203 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9205 struct kvm_cpuid_entry2
*best
;
9206 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9207 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9209 if (vmx_rdtscp_supported()) {
9210 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9211 if (!rdtscp_enabled
)
9212 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9216 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9217 SECONDARY_EXEC_RDTSCP
;
9219 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9220 ~SECONDARY_EXEC_RDTSCP
;
9224 /* Exposing INVPCID only when PCID is exposed */
9225 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9226 if (vmx_invpcid_supported() &&
9227 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9228 !guest_cpuid_has_pcid(vcpu
))) {
9229 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9232 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9235 if (cpu_has_secondary_exec_ctrls())
9236 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9238 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
9239 if (guest_cpuid_has_pcommit(vcpu
))
9240 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9241 SECONDARY_EXEC_PCOMMIT
;
9243 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9244 ~SECONDARY_EXEC_PCOMMIT
;
9247 if (nested_vmx_allowed(vcpu
))
9248 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9249 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9251 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9252 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9255 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9257 if (func
== 1 && nested
)
9258 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9261 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9262 struct x86_exception
*fault
)
9264 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9267 if (fault
->error_code
& PFERR_RSVD_MASK
)
9268 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9270 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9271 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9272 vmcs12
->guest_physical_address
= fault
->address
;
9275 /* Callbacks for nested_ept_init_mmu_context: */
9277 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9279 /* return the page table to be shadowed - in our case, EPT12 */
9280 return get_vmcs12(vcpu
)->ept_pointer
;
9283 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9285 WARN_ON(mmu_is_nested(vcpu
));
9286 kvm_init_shadow_ept_mmu(vcpu
,
9287 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9288 VMX_EPT_EXECUTE_ONLY_BIT
);
9289 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9290 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9291 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9293 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9296 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9298 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9301 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9304 bool inequality
, bit
;
9306 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9308 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9309 vmcs12
->page_fault_error_code_match
;
9310 return inequality
^ bit
;
9313 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9314 struct x86_exception
*fault
)
9316 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9318 WARN_ON(!is_guest_mode(vcpu
));
9320 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9321 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9322 vmcs_read32(VM_EXIT_INTR_INFO
),
9323 vmcs_readl(EXIT_QUALIFICATION
));
9325 kvm_inject_page_fault(vcpu
, fault
);
9328 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9329 struct vmcs12
*vmcs12
)
9331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9332 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9334 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9335 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9336 vmcs12
->apic_access_addr
>> maxphyaddr
)
9340 * Translate L1 physical address to host physical
9341 * address for vmcs02. Keep the page pinned, so this
9342 * physical address remains valid. We keep a reference
9343 * to it so we can release it later.
9345 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9346 nested_release_page(vmx
->nested
.apic_access_page
);
9347 vmx
->nested
.apic_access_page
=
9348 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9351 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9352 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9353 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9356 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9357 nested_release_page(vmx
->nested
.virtual_apic_page
);
9358 vmx
->nested
.virtual_apic_page
=
9359 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9362 * Failing the vm entry is _not_ what the processor does
9363 * but it's basically the only possibility we have.
9364 * We could still enter the guest if CR8 load exits are
9365 * enabled, CR8 store exits are enabled, and virtualize APIC
9366 * access is disabled; in this case the processor would never
9367 * use the TPR shadow and we could simply clear the bit from
9368 * the execution control. But such a configuration is useless,
9369 * so let's keep the code simple.
9371 if (!vmx
->nested
.virtual_apic_page
)
9375 if (nested_cpu_has_posted_intr(vmcs12
)) {
9376 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9377 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9380 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9381 kunmap(vmx
->nested
.pi_desc_page
);
9382 nested_release_page(vmx
->nested
.pi_desc_page
);
9384 vmx
->nested
.pi_desc_page
=
9385 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9386 if (!vmx
->nested
.pi_desc_page
)
9389 vmx
->nested
.pi_desc
=
9390 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9391 if (!vmx
->nested
.pi_desc
) {
9392 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9395 vmx
->nested
.pi_desc
=
9396 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9397 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9404 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9406 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9409 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9412 /* Make sure short timeouts reliably trigger an immediate vmexit.
9413 * hrtimer_start does not guarantee this. */
9414 if (preemption_timeout
<= 1) {
9415 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9419 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9420 preemption_timeout
*= 1000000;
9421 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9422 hrtimer_start(&vmx
->nested
.preemption_timer
,
9423 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9426 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9427 struct vmcs12
*vmcs12
)
9432 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9435 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9439 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9441 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9442 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9449 * Merge L0's and L1's MSR bitmap, return false to indicate that
9450 * we do not use the hardware.
9452 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9453 struct vmcs12
*vmcs12
)
9457 unsigned long *msr_bitmap
;
9459 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9462 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9467 msr_bitmap
= (unsigned long *)kmap(page
);
9469 nested_release_page_clean(page
);
9474 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9475 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9476 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9477 nested_vmx_disable_intercept_for_msr(
9479 vmx_msr_bitmap_nested
,
9481 /* TPR is allowed */
9482 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9483 vmx_msr_bitmap_nested
,
9484 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9485 MSR_TYPE_R
| MSR_TYPE_W
);
9486 if (nested_cpu_has_vid(vmcs12
)) {
9487 /* EOI and self-IPI are allowed */
9488 nested_vmx_disable_intercept_for_msr(
9490 vmx_msr_bitmap_nested
,
9491 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9493 nested_vmx_disable_intercept_for_msr(
9495 vmx_msr_bitmap_nested
,
9496 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9501 * Enable reading intercept of all the x2apic
9502 * MSRs. We should not rely on vmcs12 to do any
9503 * optimizations here, it may have been modified
9506 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9507 __vmx_enable_intercept_for_msr(
9508 vmx_msr_bitmap_nested
,
9512 __vmx_enable_intercept_for_msr(
9513 vmx_msr_bitmap_nested
,
9514 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9516 __vmx_enable_intercept_for_msr(
9517 vmx_msr_bitmap_nested
,
9518 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9520 __vmx_enable_intercept_for_msr(
9521 vmx_msr_bitmap_nested
,
9522 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9526 nested_release_page_clean(page
);
9531 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9532 struct vmcs12
*vmcs12
)
9534 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9535 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9536 !nested_cpu_has_vid(vmcs12
) &&
9537 !nested_cpu_has_posted_intr(vmcs12
))
9541 * If virtualize x2apic mode is enabled,
9542 * virtualize apic access must be disabled.
9544 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9545 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9549 * If virtual interrupt delivery is enabled,
9550 * we must exit on external interrupts.
9552 if (nested_cpu_has_vid(vmcs12
) &&
9553 !nested_exit_on_intr(vcpu
))
9557 * bits 15:8 should be zero in posted_intr_nv,
9558 * the descriptor address has been already checked
9559 * in nested_get_vmcs12_pages.
9561 if (nested_cpu_has_posted_intr(vmcs12
) &&
9562 (!nested_cpu_has_vid(vmcs12
) ||
9563 !nested_exit_intr_ack_set(vcpu
) ||
9564 vmcs12
->posted_intr_nv
& 0xff00))
9567 /* tpr shadow is needed by all apicv features. */
9568 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9574 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9575 unsigned long count_field
,
9576 unsigned long addr_field
)
9581 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9582 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9588 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9589 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9590 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9591 pr_warn_ratelimited(
9592 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9593 addr_field
, maxphyaddr
, count
, addr
);
9599 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9600 struct vmcs12
*vmcs12
)
9602 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9603 vmcs12
->vm_exit_msr_store_count
== 0 &&
9604 vmcs12
->vm_entry_msr_load_count
== 0)
9605 return 0; /* Fast path */
9606 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9607 VM_EXIT_MSR_LOAD_ADDR
) ||
9608 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9609 VM_EXIT_MSR_STORE_ADDR
) ||
9610 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9611 VM_ENTRY_MSR_LOAD_ADDR
))
9616 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9617 struct vmx_msr_entry
*e
)
9619 /* x2APIC MSR accesses are not allowed */
9620 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9622 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9623 e
->index
== MSR_IA32_UCODE_REV
)
9625 if (e
->reserved
!= 0)
9630 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9631 struct vmx_msr_entry
*e
)
9633 if (e
->index
== MSR_FS_BASE
||
9634 e
->index
== MSR_GS_BASE
||
9635 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9636 nested_vmx_msr_check_common(vcpu
, e
))
9641 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9642 struct vmx_msr_entry
*e
)
9644 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9645 nested_vmx_msr_check_common(vcpu
, e
))
9651 * Load guest's/host's msr at nested entry/exit.
9652 * return 0 for success, entry index for failure.
9654 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9657 struct vmx_msr_entry e
;
9658 struct msr_data msr
;
9660 msr
.host_initiated
= false;
9661 for (i
= 0; i
< count
; i
++) {
9662 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9664 pr_warn_ratelimited(
9665 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9666 __func__
, i
, gpa
+ i
* sizeof(e
));
9669 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9670 pr_warn_ratelimited(
9671 "%s check failed (%u, 0x%x, 0x%x)\n",
9672 __func__
, i
, e
.index
, e
.reserved
);
9675 msr
.index
= e
.index
;
9677 if (kvm_set_msr(vcpu
, &msr
)) {
9678 pr_warn_ratelimited(
9679 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9680 __func__
, i
, e
.index
, e
.value
);
9689 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9692 struct vmx_msr_entry e
;
9694 for (i
= 0; i
< count
; i
++) {
9695 struct msr_data msr_info
;
9696 if (kvm_vcpu_read_guest(vcpu
,
9697 gpa
+ i
* sizeof(e
),
9698 &e
, 2 * sizeof(u32
))) {
9699 pr_warn_ratelimited(
9700 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9701 __func__
, i
, gpa
+ i
* sizeof(e
));
9704 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9705 pr_warn_ratelimited(
9706 "%s check failed (%u, 0x%x, 0x%x)\n",
9707 __func__
, i
, e
.index
, e
.reserved
);
9710 msr_info
.host_initiated
= false;
9711 msr_info
.index
= e
.index
;
9712 if (kvm_get_msr(vcpu
, &msr_info
)) {
9713 pr_warn_ratelimited(
9714 "%s cannot read MSR (%u, 0x%x)\n",
9715 __func__
, i
, e
.index
);
9718 if (kvm_vcpu_write_guest(vcpu
,
9719 gpa
+ i
* sizeof(e
) +
9720 offsetof(struct vmx_msr_entry
, value
),
9721 &msr_info
.data
, sizeof(msr_info
.data
))) {
9722 pr_warn_ratelimited(
9723 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9724 __func__
, i
, e
.index
, msr_info
.data
);
9732 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9733 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9734 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9735 * guest in a way that will both be appropriate to L1's requests, and our
9736 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9737 * function also has additional necessary side-effects, like setting various
9738 * vcpu->arch fields.
9740 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9742 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9745 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9746 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9747 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9748 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9749 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9750 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9751 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9752 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9753 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9754 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9755 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9756 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9757 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9758 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9759 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9760 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9761 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9762 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9763 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9764 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9765 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9766 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9767 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9768 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9769 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9770 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9771 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9772 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9773 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9774 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9775 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9776 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9777 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9778 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9779 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9780 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9782 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9783 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9784 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9786 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9787 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9790 vmcs12
->vm_entry_intr_info_field
);
9791 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9792 vmcs12
->vm_entry_exception_error_code
);
9793 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9794 vmcs12
->vm_entry_instruction_len
);
9795 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9796 vmcs12
->guest_interruptibility_info
);
9797 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9798 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9799 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9800 vmcs12
->guest_pending_dbg_exceptions
);
9801 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9802 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9804 if (nested_cpu_has_xsaves(vmcs12
))
9805 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9806 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9808 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9810 /* Preemption timer setting is only taken from vmcs01. */
9811 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9812 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9813 if (vmx
->hv_deadline_tsc
== -1)
9814 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9816 /* Posted interrupts setting is only taken from vmcs12. */
9817 if (nested_cpu_has_posted_intr(vmcs12
)) {
9819 * Note that we use L0's vector here and in
9820 * vmx_deliver_nested_posted_interrupt.
9822 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9823 vmx
->nested
.pi_pending
= false;
9824 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9825 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9826 page_to_phys(vmx
->nested
.pi_desc_page
) +
9827 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9830 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9832 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9834 vmx
->nested
.preemption_timer_expired
= false;
9835 if (nested_cpu_has_preemption_timer(vmcs12
))
9836 vmx_start_preemption_timer(vcpu
);
9839 * Whether page-faults are trapped is determined by a combination of
9840 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9841 * If enable_ept, L0 doesn't care about page faults and we should
9842 * set all of these to L1's desires. However, if !enable_ept, L0 does
9843 * care about (at least some) page faults, and because it is not easy
9844 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9845 * to exit on each and every L2 page fault. This is done by setting
9846 * MASK=MATCH=0 and (see below) EB.PF=1.
9847 * Note that below we don't need special code to set EB.PF beyond the
9848 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9849 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9850 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9852 * A problem with this approach (when !enable_ept) is that L1 may be
9853 * injected with more page faults than it asked for. This could have
9854 * caused problems, but in practice existing hypervisors don't care.
9855 * To fix this, we will need to emulate the PFEC checking (on the L1
9856 * page tables), using walk_addr(), when injecting PFs to L1.
9858 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9859 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9860 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9861 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9863 if (cpu_has_secondary_exec_ctrls()) {
9864 exec_control
= vmx_secondary_exec_control(vmx
);
9866 /* Take the following fields only from vmcs12 */
9867 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9868 SECONDARY_EXEC_RDTSCP
|
9869 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9870 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9871 SECONDARY_EXEC_PCOMMIT
);
9872 if (nested_cpu_has(vmcs12
,
9873 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9874 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9876 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9878 * If translation failed, no matter: This feature asks
9879 * to exit when accessing the given address, and if it
9880 * can never be accessed, this feature won't do
9883 if (!vmx
->nested
.apic_access_page
)
9885 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9887 vmcs_write64(APIC_ACCESS_ADDR
,
9888 page_to_phys(vmx
->nested
.apic_access_page
));
9889 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9890 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9892 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9893 kvm_vcpu_reload_apic_access_page(vcpu
);
9896 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9897 vmcs_write64(EOI_EXIT_BITMAP0
,
9898 vmcs12
->eoi_exit_bitmap0
);
9899 vmcs_write64(EOI_EXIT_BITMAP1
,
9900 vmcs12
->eoi_exit_bitmap1
);
9901 vmcs_write64(EOI_EXIT_BITMAP2
,
9902 vmcs12
->eoi_exit_bitmap2
);
9903 vmcs_write64(EOI_EXIT_BITMAP3
,
9904 vmcs12
->eoi_exit_bitmap3
);
9905 vmcs_write16(GUEST_INTR_STATUS
,
9906 vmcs12
->guest_intr_status
);
9909 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9914 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9915 * Some constant fields are set here by vmx_set_constant_host_state().
9916 * Other fields are different per CPU, and will be set later when
9917 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9919 vmx_set_constant_host_state(vmx
);
9922 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9923 * entry, but only if the current (host) sp changed from the value
9924 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9925 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9926 * here we just force the write to happen on entry.
9930 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9931 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9932 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9933 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9934 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9936 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9937 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9938 page_to_phys(vmx
->nested
.virtual_apic_page
));
9939 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9942 if (cpu_has_vmx_msr_bitmap() &&
9943 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9944 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9945 /* MSR_BITMAP will be set by following vmx_set_efer. */
9947 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9950 * Merging of IO bitmap not currently supported.
9951 * Rather, exit every time.
9953 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9954 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9956 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9958 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9959 * bitwise-or of what L1 wants to trap for L2, and what we want to
9960 * trap. Note that CR0.TS also needs updating - we do this later.
9962 update_exception_bitmap(vcpu
);
9963 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9964 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9966 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9967 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9968 * bits are further modified by vmx_set_efer() below.
9970 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9972 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9973 * emulated by vmx_set_efer(), below.
9975 vm_entry_controls_init(vmx
,
9976 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9977 ~VM_ENTRY_IA32E_MODE
) |
9978 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9980 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9981 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9982 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9983 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9984 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9987 set_cr4_guest_host_mask(vmx
);
9989 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9990 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9992 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9993 vmcs_write64(TSC_OFFSET
,
9994 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9996 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10000 * There is no direct mapping between vpid02 and vpid12, the
10001 * vpid02 is per-vCPU for L0 and reused while the value of
10002 * vpid12 is changed w/ one invvpid during nested vmentry.
10003 * The vpid12 is allocated by L1 for L2, so it will not
10004 * influence global bitmap(for vpid01 and vpid02 allocation)
10005 * even if spawn a lot of nested vCPUs.
10007 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10008 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10009 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10010 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10011 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10014 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10015 vmx_flush_tlb(vcpu
);
10020 if (nested_cpu_has_ept(vmcs12
)) {
10021 kvm_mmu_unload(vcpu
);
10022 nested_ept_init_mmu_context(vcpu
);
10025 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
10026 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10027 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10028 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10030 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10031 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10032 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10035 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10036 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10037 * The CR0_READ_SHADOW is what L2 should have expected to read given
10038 * the specifications by L1; It's not enough to take
10039 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10040 * have more bits than L1 expected.
10042 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10043 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10045 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10046 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10048 /* shadow page tables on either EPT or shadow page tables */
10049 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
10050 kvm_mmu_reset_context(vcpu
);
10053 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10056 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10059 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10060 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10061 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10062 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10065 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10066 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10070 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10071 * for running an L2 nested guest.
10073 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10075 struct vmcs12
*vmcs12
;
10076 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10078 struct loaded_vmcs
*vmcs02
;
10082 if (!nested_vmx_check_permission(vcpu
) ||
10083 !nested_vmx_check_vmcs12(vcpu
))
10086 skip_emulated_instruction(vcpu
);
10087 vmcs12
= get_vmcs12(vcpu
);
10089 if (enable_shadow_vmcs
)
10090 copy_shadow_to_vmcs12(vmx
);
10093 * The nested entry process starts with enforcing various prerequisites
10094 * on vmcs12 as required by the Intel SDM, and act appropriately when
10095 * they fail: As the SDM explains, some conditions should cause the
10096 * instruction to fail, while others will cause the instruction to seem
10097 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10098 * To speed up the normal (success) code path, we should avoid checking
10099 * for misconfigurations which will anyway be caught by the processor
10100 * when using the merged vmcs02.
10102 if (vmcs12
->launch_state
== launch
) {
10103 nested_vmx_failValid(vcpu
,
10104 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10105 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10109 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10110 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
10111 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10115 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
10116 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10120 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
10121 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10125 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
10126 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10130 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
10131 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10135 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10136 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
10137 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10138 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10139 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10140 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10141 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10142 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10143 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10144 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10145 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
10146 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10147 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10148 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
10149 vmx
->nested
.nested_vmx_entry_ctls_high
))
10151 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10155 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
10156 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10157 nested_vmx_failValid(vcpu
,
10158 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
10162 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10163 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10164 nested_vmx_entry_failure(vcpu
, vmcs12
,
10165 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10168 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
10169 nested_vmx_entry_failure(vcpu
, vmcs12
,
10170 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
10175 * If the load IA32_EFER VM-entry control is 1, the following checks
10176 * are performed on the field for the IA32_EFER MSR:
10177 * - Bits reserved in the IA32_EFER MSR must be 0.
10178 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10179 * the IA-32e mode guest VM-exit control. It must also be identical
10180 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10183 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10184 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10185 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10186 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10187 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10188 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10189 nested_vmx_entry_failure(vcpu
, vmcs12
,
10190 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10196 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10197 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10198 * the values of the LMA and LME bits in the field must each be that of
10199 * the host address-space size VM-exit control.
10201 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10202 ia32e
= (vmcs12
->vm_exit_controls
&
10203 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10204 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10205 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10206 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10207 nested_vmx_entry_failure(vcpu
, vmcs12
,
10208 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10214 * We're finally done with prerequisite checking, and can start with
10215 * the nested entry.
10218 vmcs02
= nested_get_current_vmcs02(vmx
);
10222 enter_guest_mode(vcpu
);
10224 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
10226 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10227 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10230 vmx
->loaded_vmcs
= vmcs02
;
10231 vmx_vcpu_put(vcpu
);
10232 vmx_vcpu_load(vcpu
, cpu
);
10236 vmx_segment_cache_clear(vmx
);
10238 prepare_vmcs02(vcpu
, vmcs12
);
10240 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10241 vmcs12
->vm_entry_msr_load_addr
,
10242 vmcs12
->vm_entry_msr_load_count
);
10243 if (msr_entry_idx
) {
10244 leave_guest_mode(vcpu
);
10245 vmx_load_vmcs01(vcpu
);
10246 nested_vmx_entry_failure(vcpu
, vmcs12
,
10247 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10251 vmcs12
->launch_state
= 1;
10253 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10254 return kvm_vcpu_halt(vcpu
);
10256 vmx
->nested
.nested_run_pending
= 1;
10259 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10260 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10261 * returned as far as L1 is concerned. It will only return (and set
10262 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10268 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10269 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10270 * This function returns the new value we should put in vmcs12.guest_cr0.
10271 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10272 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10273 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10274 * didn't trap the bit, because if L1 did, so would L0).
10275 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10276 * been modified by L2, and L1 knows it. So just leave the old value of
10277 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10278 * isn't relevant, because if L0 traps this bit it can set it to anything.
10279 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10280 * changed these bits, and therefore they need to be updated, but L0
10281 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10282 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10284 static inline unsigned long
10285 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10288 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10289 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10290 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10291 vcpu
->arch
.cr0_guest_owned_bits
));
10294 static inline unsigned long
10295 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10298 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10299 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10300 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10301 vcpu
->arch
.cr4_guest_owned_bits
));
10304 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10305 struct vmcs12
*vmcs12
)
10310 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10311 nr
= vcpu
->arch
.exception
.nr
;
10312 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10314 if (kvm_exception_is_soft(nr
)) {
10315 vmcs12
->vm_exit_instruction_len
=
10316 vcpu
->arch
.event_exit_inst_len
;
10317 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10319 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10321 if (vcpu
->arch
.exception
.has_error_code
) {
10322 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10323 vmcs12
->idt_vectoring_error_code
=
10324 vcpu
->arch
.exception
.error_code
;
10327 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10328 } else if (vcpu
->arch
.nmi_injected
) {
10329 vmcs12
->idt_vectoring_info_field
=
10330 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10331 } else if (vcpu
->arch
.interrupt
.pending
) {
10332 nr
= vcpu
->arch
.interrupt
.nr
;
10333 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10335 if (vcpu
->arch
.interrupt
.soft
) {
10336 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10337 vmcs12
->vm_entry_instruction_len
=
10338 vcpu
->arch
.event_exit_inst_len
;
10340 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10342 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10346 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10348 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10350 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10351 vmx
->nested
.preemption_timer_expired
) {
10352 if (vmx
->nested
.nested_run_pending
)
10354 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10358 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10359 if (vmx
->nested
.nested_run_pending
||
10360 vcpu
->arch
.interrupt
.pending
)
10362 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10363 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10364 INTR_INFO_VALID_MASK
, 0);
10366 * The NMI-triggered VM exit counts as injection:
10367 * clear this one and block further NMIs.
10369 vcpu
->arch
.nmi_pending
= 0;
10370 vmx_set_nmi_mask(vcpu
, true);
10374 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10375 nested_exit_on_intr(vcpu
)) {
10376 if (vmx
->nested
.nested_run_pending
)
10378 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10382 return vmx_complete_nested_posted_interrupt(vcpu
);
10385 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10387 ktime_t remaining
=
10388 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10391 if (ktime_to_ns(remaining
) <= 0)
10394 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10395 do_div(value
, 1000000);
10396 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10400 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10401 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10402 * and this function updates it to reflect the changes to the guest state while
10403 * L2 was running (and perhaps made some exits which were handled directly by L0
10404 * without going back to L1), and to reflect the exit reason.
10405 * Note that we do not have to copy here all VMCS fields, just those that
10406 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10407 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10408 * which already writes to vmcs12 directly.
10410 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10411 u32 exit_reason
, u32 exit_intr_info
,
10412 unsigned long exit_qualification
)
10414 /* update guest state fields: */
10415 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10416 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10418 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10419 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10420 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10422 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10423 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10424 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10425 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10426 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10427 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10428 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10429 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10430 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10431 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10432 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10433 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10434 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10435 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10436 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10437 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10438 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10439 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10440 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10441 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10442 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10443 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10444 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10445 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10446 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10447 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10448 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10449 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10450 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10451 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10452 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10453 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10454 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10455 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10456 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10457 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10459 vmcs12
->guest_interruptibility_info
=
10460 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10461 vmcs12
->guest_pending_dbg_exceptions
=
10462 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10463 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10464 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10466 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10468 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10469 if (vmcs12
->vm_exit_controls
&
10470 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10471 vmcs12
->vmx_preemption_timer_value
=
10472 vmx_get_preemption_timer_value(vcpu
);
10473 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10477 * In some cases (usually, nested EPT), L2 is allowed to change its
10478 * own CR3 without exiting. If it has changed it, we must keep it.
10479 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10480 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10482 * Additionally, restore L2's PDPTR to vmcs12.
10485 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10486 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10487 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10488 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10489 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10492 if (nested_cpu_has_vid(vmcs12
))
10493 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10495 vmcs12
->vm_entry_controls
=
10496 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10497 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10499 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10500 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10501 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10504 /* TODO: These cannot have changed unless we have MSR bitmaps and
10505 * the relevant bit asks not to trap the change */
10506 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10507 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10508 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10509 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10510 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10511 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10512 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10513 if (kvm_mpx_supported())
10514 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10515 if (nested_cpu_has_xsaves(vmcs12
))
10516 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10518 /* update exit information fields: */
10520 vmcs12
->vm_exit_reason
= exit_reason
;
10521 vmcs12
->exit_qualification
= exit_qualification
;
10523 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10524 if ((vmcs12
->vm_exit_intr_info
&
10525 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10526 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10527 vmcs12
->vm_exit_intr_error_code
=
10528 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10529 vmcs12
->idt_vectoring_info_field
= 0;
10530 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10531 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10533 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10534 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10535 * instead of reading the real value. */
10536 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10539 * Transfer the event that L0 or L1 may wanted to inject into
10540 * L2 to IDT_VECTORING_INFO_FIELD.
10542 vmcs12_save_pending_event(vcpu
, vmcs12
);
10546 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10547 * preserved above and would only end up incorrectly in L1.
10549 vcpu
->arch
.nmi_injected
= false;
10550 kvm_clear_exception_queue(vcpu
);
10551 kvm_clear_interrupt_queue(vcpu
);
10555 * A part of what we need to when the nested L2 guest exits and we want to
10556 * run its L1 parent, is to reset L1's guest state to the host state specified
10558 * This function is to be called not only on normal nested exit, but also on
10559 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10560 * Failures During or After Loading Guest State").
10561 * This function should be called when the active VMCS is L1's (vmcs01).
10563 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10564 struct vmcs12
*vmcs12
)
10566 struct kvm_segment seg
;
10568 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10569 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10570 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10571 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10573 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10574 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10576 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10577 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10578 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10580 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10581 * actually changed, because it depends on the current state of
10582 * fpu_active (which may have changed).
10583 * Note that vmx_set_cr0 refers to efer set above.
10585 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10587 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10588 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10589 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10591 update_exception_bitmap(vcpu
);
10592 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10593 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10596 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10597 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10599 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10600 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10602 nested_ept_uninit_mmu_context(vcpu
);
10604 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10605 kvm_mmu_reset_context(vcpu
);
10608 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10612 * Trivially support vpid by letting L2s share their parent
10613 * L1's vpid. TODO: move to a more elaborate solution, giving
10614 * each L2 its own vpid and exposing the vpid feature to L1.
10616 vmx_flush_tlb(vcpu
);
10620 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10621 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10622 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10623 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10624 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10626 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10627 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10628 vmcs_write64(GUEST_BNDCFGS
, 0);
10630 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10631 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10632 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10634 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10635 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10636 vmcs12
->host_ia32_perf_global_ctrl
);
10638 /* Set L1 segment info according to Intel SDM
10639 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10640 seg
= (struct kvm_segment
) {
10642 .limit
= 0xFFFFFFFF,
10643 .selector
= vmcs12
->host_cs_selector
,
10649 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10653 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10654 seg
= (struct kvm_segment
) {
10656 .limit
= 0xFFFFFFFF,
10663 seg
.selector
= vmcs12
->host_ds_selector
;
10664 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10665 seg
.selector
= vmcs12
->host_es_selector
;
10666 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10667 seg
.selector
= vmcs12
->host_ss_selector
;
10668 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10669 seg
.selector
= vmcs12
->host_fs_selector
;
10670 seg
.base
= vmcs12
->host_fs_base
;
10671 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10672 seg
.selector
= vmcs12
->host_gs_selector
;
10673 seg
.base
= vmcs12
->host_gs_base
;
10674 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10675 seg
= (struct kvm_segment
) {
10676 .base
= vmcs12
->host_tr_base
,
10678 .selector
= vmcs12
->host_tr_selector
,
10682 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10684 kvm_set_dr(vcpu
, 7, 0x400);
10685 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10687 if (cpu_has_vmx_msr_bitmap())
10688 vmx_set_msr_bitmap(vcpu
);
10690 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10691 vmcs12
->vm_exit_msr_load_count
))
10692 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10696 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10697 * and modify vmcs12 to make it see what it would expect to see there if
10698 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10700 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10701 u32 exit_intr_info
,
10702 unsigned long exit_qualification
)
10704 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10705 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10707 /* trying to cancel vmlaunch/vmresume is a bug */
10708 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10710 leave_guest_mode(vcpu
);
10711 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10712 exit_qualification
);
10714 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10715 vmcs12
->vm_exit_msr_store_count
))
10716 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10718 vmx_load_vmcs01(vcpu
);
10720 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10721 && nested_exit_intr_ack_set(vcpu
)) {
10722 int irq
= kvm_cpu_get_interrupt(vcpu
);
10724 vmcs12
->vm_exit_intr_info
= irq
|
10725 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10728 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10729 vmcs12
->exit_qualification
,
10730 vmcs12
->idt_vectoring_info_field
,
10731 vmcs12
->vm_exit_intr_info
,
10732 vmcs12
->vm_exit_intr_error_code
,
10735 vm_entry_controls_reset_shadow(vmx
);
10736 vm_exit_controls_reset_shadow(vmx
);
10737 vmx_segment_cache_clear(vmx
);
10739 /* if no vmcs02 cache requested, remove the one we used */
10740 if (VMCS02_POOL_SIZE
== 0)
10741 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10743 load_vmcs12_host_state(vcpu
, vmcs12
);
10745 /* Update any VMCS fields that might have changed while L2 ran */
10746 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10747 if (vmx
->hv_deadline_tsc
== -1)
10748 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10749 PIN_BASED_VMX_PREEMPTION_TIMER
);
10751 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10752 PIN_BASED_VMX_PREEMPTION_TIMER
);
10754 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10757 /* Unpin physical memory we referred to in vmcs02 */
10758 if (vmx
->nested
.apic_access_page
) {
10759 nested_release_page(vmx
->nested
.apic_access_page
);
10760 vmx
->nested
.apic_access_page
= NULL
;
10762 if (vmx
->nested
.virtual_apic_page
) {
10763 nested_release_page(vmx
->nested
.virtual_apic_page
);
10764 vmx
->nested
.virtual_apic_page
= NULL
;
10766 if (vmx
->nested
.pi_desc_page
) {
10767 kunmap(vmx
->nested
.pi_desc_page
);
10768 nested_release_page(vmx
->nested
.pi_desc_page
);
10769 vmx
->nested
.pi_desc_page
= NULL
;
10770 vmx
->nested
.pi_desc
= NULL
;
10774 * We are now running in L2, mmu_notifier will force to reload the
10775 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10777 kvm_vcpu_reload_apic_access_page(vcpu
);
10780 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10781 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10782 * success or failure flag accordingly.
10784 if (unlikely(vmx
->fail
)) {
10786 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10788 nested_vmx_succeed(vcpu
);
10789 if (enable_shadow_vmcs
)
10790 vmx
->nested
.sync_shadow_vmcs
= true;
10792 /* in case we halted in L2 */
10793 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10797 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10799 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10801 if (is_guest_mode(vcpu
))
10802 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10803 free_nested(to_vmx(vcpu
));
10807 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10808 * 23.7 "VM-entry failures during or after loading guest state" (this also
10809 * lists the acceptable exit-reason and exit-qualification parameters).
10810 * It should only be called before L2 actually succeeded to run, and when
10811 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10813 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10814 struct vmcs12
*vmcs12
,
10815 u32 reason
, unsigned long qualification
)
10817 load_vmcs12_host_state(vcpu
, vmcs12
);
10818 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10819 vmcs12
->exit_qualification
= qualification
;
10820 nested_vmx_succeed(vcpu
);
10821 if (enable_shadow_vmcs
)
10822 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10825 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10826 struct x86_instruction_info
*info
,
10827 enum x86_intercept_stage stage
)
10829 return X86EMUL_CONTINUE
;
10832 #ifdef CONFIG_X86_64
10833 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10834 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
10835 u64 divisor
, u64
*result
)
10837 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
10839 /* To avoid the overflow on divq */
10840 if (high
>= divisor
)
10843 /* Low hold the result, high hold rem which is discarded */
10844 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
10845 "rm" (divisor
), "0" (low
), "1" (high
));
10851 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
10853 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10854 u64 tscl
= rdtsc();
10855 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
10856 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
10858 /* Convert to host delta tsc if tsc scaling is enabled */
10859 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
10860 u64_shl_div_u64(delta_tsc
,
10861 kvm_tsc_scaling_ratio_frac_bits
,
10862 vcpu
->arch
.tsc_scaling_ratio
,
10867 * If the delta tsc can't fit in the 32 bit after the multi shift,
10868 * we can't use the preemption timer.
10869 * It's possible that it fits on later vmentries, but checking
10870 * on every vmentry is costly so we just use an hrtimer.
10872 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
10875 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
10876 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10877 PIN_BASED_VMX_PREEMPTION_TIMER
);
10881 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
10883 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10884 vmx
->hv_deadline_tsc
= -1;
10885 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10886 PIN_BASED_VMX_PREEMPTION_TIMER
);
10890 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10893 shrink_ple_window(vcpu
);
10896 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10897 struct kvm_memory_slot
*slot
)
10899 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10900 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10903 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10904 struct kvm_memory_slot
*slot
)
10906 kvm_mmu_slot_set_dirty(kvm
, slot
);
10909 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10911 kvm_flush_pml_buffers(kvm
);
10914 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10915 struct kvm_memory_slot
*memslot
,
10916 gfn_t offset
, unsigned long mask
)
10918 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10922 * This routine does the following things for vCPU which is going
10923 * to be blocked if VT-d PI is enabled.
10924 * - Store the vCPU to the wakeup list, so when interrupts happen
10925 * we can find the right vCPU to wake up.
10926 * - Change the Posted-interrupt descriptor as below:
10927 * 'NDST' <-- vcpu->pre_pcpu
10928 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10929 * - If 'ON' is set during this process, which means at least one
10930 * interrupt is posted for this vCPU, we cannot block it, in
10931 * this case, return 1, otherwise, return 0.
10934 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
10936 unsigned long flags
;
10938 struct pi_desc old
, new;
10939 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10941 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10942 !irq_remapping_cap(IRQ_POSTING_CAP
))
10945 vcpu
->pre_pcpu
= vcpu
->cpu
;
10946 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10947 vcpu
->pre_pcpu
), flags
);
10948 list_add_tail(&vcpu
->blocked_vcpu_list
,
10949 &per_cpu(blocked_vcpu_on_cpu
,
10951 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10952 vcpu
->pre_pcpu
), flags
);
10955 old
.control
= new.control
= pi_desc
->control
;
10958 * We should not block the vCPU if
10959 * an interrupt is posted for it.
10961 if (pi_test_on(pi_desc
) == 1) {
10962 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10963 vcpu
->pre_pcpu
), flags
);
10964 list_del(&vcpu
->blocked_vcpu_list
);
10965 spin_unlock_irqrestore(
10966 &per_cpu(blocked_vcpu_on_cpu_lock
,
10967 vcpu
->pre_pcpu
), flags
);
10968 vcpu
->pre_pcpu
= -1;
10973 WARN((pi_desc
->sn
== 1),
10974 "Warning: SN field of posted-interrupts "
10975 "is set before blocking\n");
10978 * Since vCPU can be preempted during this process,
10979 * vcpu->cpu could be different with pre_pcpu, we
10980 * need to set pre_pcpu as the destination of wakeup
10981 * notification event, then we can find the right vCPU
10982 * to wakeup in wakeup handler if interrupts happen
10983 * when the vCPU is in blocked state.
10985 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10987 if (x2apic_enabled())
10990 new.ndst
= (dest
<< 8) & 0xFF00;
10992 /* set 'NV' to 'wakeup vector' */
10993 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10994 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10995 new.control
) != old
.control
);
11000 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11002 if (pi_pre_block(vcpu
))
11005 if (kvm_lapic_hv_timer_in_use(vcpu
))
11006 kvm_lapic_switch_to_sw_timer(vcpu
);
11011 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11013 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11014 struct pi_desc old
, new;
11016 unsigned long flags
;
11018 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11019 !irq_remapping_cap(IRQ_POSTING_CAP
))
11023 old
.control
= new.control
= pi_desc
->control
;
11025 dest
= cpu_physical_id(vcpu
->cpu
);
11027 if (x2apic_enabled())
11030 new.ndst
= (dest
<< 8) & 0xFF00;
11032 /* Allow posting non-urgent interrupts */
11035 /* set 'NV' to 'notification vector' */
11036 new.nv
= POSTED_INTR_VECTOR
;
11037 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11038 new.control
) != old
.control
);
11040 if(vcpu
->pre_pcpu
!= -1) {
11042 &per_cpu(blocked_vcpu_on_cpu_lock
,
11043 vcpu
->pre_pcpu
), flags
);
11044 list_del(&vcpu
->blocked_vcpu_list
);
11045 spin_unlock_irqrestore(
11046 &per_cpu(blocked_vcpu_on_cpu_lock
,
11047 vcpu
->pre_pcpu
), flags
);
11048 vcpu
->pre_pcpu
= -1;
11052 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11054 if (kvm_x86_ops
->set_hv_timer
)
11055 kvm_lapic_switch_to_hv_timer(vcpu
);
11057 pi_post_block(vcpu
);
11061 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11064 * @host_irq: host irq of the interrupt
11065 * @guest_irq: gsi of the interrupt
11066 * @set: set or unset PI
11067 * returns 0 on success, < 0 on failure
11069 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11070 uint32_t guest_irq
, bool set
)
11072 struct kvm_kernel_irq_routing_entry
*e
;
11073 struct kvm_irq_routing_table
*irq_rt
;
11074 struct kvm_lapic_irq irq
;
11075 struct kvm_vcpu
*vcpu
;
11076 struct vcpu_data vcpu_info
;
11077 int idx
, ret
= -EINVAL
;
11079 if (!kvm_arch_has_assigned_device(kvm
) ||
11080 !irq_remapping_cap(IRQ_POSTING_CAP
))
11083 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11084 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11085 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11087 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11088 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11091 * VT-d PI cannot support posting multicast/broadcast
11092 * interrupts to a vCPU, we still use interrupt remapping
11093 * for these kind of interrupts.
11095 * For lowest-priority interrupts, we only support
11096 * those with single CPU as the destination, e.g. user
11097 * configures the interrupts via /proc/irq or uses
11098 * irqbalance to make the interrupts single-CPU.
11100 * We will support full lowest-priority interrupt later.
11103 kvm_set_msi_irq(e
, &irq
);
11104 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11106 * Make sure the IRTE is in remapped mode if
11107 * we don't handle it in posted mode.
11109 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11112 "failed to back to remapped mode, irq: %u\n",
11120 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11121 vcpu_info
.vector
= irq
.vector
;
11123 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11124 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11127 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11129 /* suppress notification event before unposting */
11130 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11131 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11132 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11136 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11144 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11148 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11150 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11151 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11152 FEATURE_CONTROL_LMCE
;
11154 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11155 ~FEATURE_CONTROL_LMCE
;
11158 static struct kvm_x86_ops vmx_x86_ops
= {
11159 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11160 .disabled_by_bios
= vmx_disabled_by_bios
,
11161 .hardware_setup
= hardware_setup
,
11162 .hardware_unsetup
= hardware_unsetup
,
11163 .check_processor_compatibility
= vmx_check_processor_compat
,
11164 .hardware_enable
= hardware_enable
,
11165 .hardware_disable
= hardware_disable
,
11166 .cpu_has_accelerated_tpr
= report_flexpriority
,
11167 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11169 .vcpu_create
= vmx_create_vcpu
,
11170 .vcpu_free
= vmx_free_vcpu
,
11171 .vcpu_reset
= vmx_vcpu_reset
,
11173 .prepare_guest_switch
= vmx_save_host_state
,
11174 .vcpu_load
= vmx_vcpu_load
,
11175 .vcpu_put
= vmx_vcpu_put
,
11177 .update_bp_intercept
= update_exception_bitmap
,
11178 .get_msr
= vmx_get_msr
,
11179 .set_msr
= vmx_set_msr
,
11180 .get_segment_base
= vmx_get_segment_base
,
11181 .get_segment
= vmx_get_segment
,
11182 .set_segment
= vmx_set_segment
,
11183 .get_cpl
= vmx_get_cpl
,
11184 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11185 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11186 .decache_cr3
= vmx_decache_cr3
,
11187 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11188 .set_cr0
= vmx_set_cr0
,
11189 .set_cr3
= vmx_set_cr3
,
11190 .set_cr4
= vmx_set_cr4
,
11191 .set_efer
= vmx_set_efer
,
11192 .get_idt
= vmx_get_idt
,
11193 .set_idt
= vmx_set_idt
,
11194 .get_gdt
= vmx_get_gdt
,
11195 .set_gdt
= vmx_set_gdt
,
11196 .get_dr6
= vmx_get_dr6
,
11197 .set_dr6
= vmx_set_dr6
,
11198 .set_dr7
= vmx_set_dr7
,
11199 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11200 .cache_reg
= vmx_cache_reg
,
11201 .get_rflags
= vmx_get_rflags
,
11202 .set_rflags
= vmx_set_rflags
,
11204 .get_pkru
= vmx_get_pkru
,
11206 .fpu_activate
= vmx_fpu_activate
,
11207 .fpu_deactivate
= vmx_fpu_deactivate
,
11209 .tlb_flush
= vmx_flush_tlb
,
11211 .run
= vmx_vcpu_run
,
11212 .handle_exit
= vmx_handle_exit
,
11213 .skip_emulated_instruction
= skip_emulated_instruction
,
11214 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11215 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11216 .patch_hypercall
= vmx_patch_hypercall
,
11217 .set_irq
= vmx_inject_irq
,
11218 .set_nmi
= vmx_inject_nmi
,
11219 .queue_exception
= vmx_queue_exception
,
11220 .cancel_injection
= vmx_cancel_injection
,
11221 .interrupt_allowed
= vmx_interrupt_allowed
,
11222 .nmi_allowed
= vmx_nmi_allowed
,
11223 .get_nmi_mask
= vmx_get_nmi_mask
,
11224 .set_nmi_mask
= vmx_set_nmi_mask
,
11225 .enable_nmi_window
= enable_nmi_window
,
11226 .enable_irq_window
= enable_irq_window
,
11227 .update_cr8_intercept
= update_cr8_intercept
,
11228 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11229 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11230 .get_enable_apicv
= vmx_get_enable_apicv
,
11231 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11232 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11233 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11234 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11235 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11236 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11238 .set_tss_addr
= vmx_set_tss_addr
,
11239 .get_tdp_level
= get_ept_level
,
11240 .get_mt_mask
= vmx_get_mt_mask
,
11242 .get_exit_info
= vmx_get_exit_info
,
11244 .get_lpage_level
= vmx_get_lpage_level
,
11246 .cpuid_update
= vmx_cpuid_update
,
11248 .rdtscp_supported
= vmx_rdtscp_supported
,
11249 .invpcid_supported
= vmx_invpcid_supported
,
11251 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11253 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11255 .read_tsc_offset
= vmx_read_tsc_offset
,
11256 .write_tsc_offset
= vmx_write_tsc_offset
,
11257 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
11258 .read_l1_tsc
= vmx_read_l1_tsc
,
11260 .set_tdp_cr3
= vmx_set_cr3
,
11262 .check_intercept
= vmx_check_intercept
,
11263 .handle_external_intr
= vmx_handle_external_intr
,
11264 .mpx_supported
= vmx_mpx_supported
,
11265 .xsaves_supported
= vmx_xsaves_supported
,
11267 .check_nested_events
= vmx_check_nested_events
,
11269 .sched_in
= vmx_sched_in
,
11271 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11272 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11273 .flush_log_dirty
= vmx_flush_log_dirty
,
11274 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11276 .pre_block
= vmx_pre_block
,
11277 .post_block
= vmx_post_block
,
11279 .pmu_ops
= &intel_pmu_ops
,
11281 .update_pi_irte
= vmx_update_pi_irte
,
11283 #ifdef CONFIG_X86_64
11284 .set_hv_timer
= vmx_set_hv_timer
,
11285 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11288 .setup_mce
= vmx_setup_mce
,
11291 static int __init
vmx_init(void)
11293 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11294 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11298 #ifdef CONFIG_KEXEC_CORE
11299 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11300 crash_vmclear_local_loaded_vmcss
);
11306 static void __exit
vmx_exit(void)
11308 #ifdef CONFIG_KEXEC_CORE
11309 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11316 module_init(vmx_init
)
11317 module_exit(vmx_exit
)