2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
154 module_param(ple_gap
, int, S_IRUGO
);
156 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
157 module_param(ple_window
, int, S_IRUGO
);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
161 module_param(ple_window_grow
, int, S_IRUGO
);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
165 module_param(ple_window_shrink
, int, S_IRUGO
);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
169 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
170 module_param(ple_window_max
, int, S_IRUGO
);
172 extern const ulong vmx_return
;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
192 struct list_head loaded_vmcss_on_cpu_link
;
195 struct shared_msr_entry
{
202 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
203 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
204 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
205 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
206 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
207 * More than one of these structures may exist, if L1 runs multiple L2 guests.
208 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
209 * underlying hardware which will be used to run L2.
210 * This structure is packed to ensure that its layout is identical across
211 * machines (necessary for live migration).
212 * If there are changes in this struct, VMCS12_REVISION must be changed.
214 typedef u64 natural_width
;
215 struct __packed vmcs12
{
216 /* According to the Intel spec, a VMCS region must start with the
217 * following two fields. Then follow implementation-specific data.
222 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
223 u32 padding
[7]; /* room for future expansion */
228 u64 vm_exit_msr_store_addr
;
229 u64 vm_exit_msr_load_addr
;
230 u64 vm_entry_msr_load_addr
;
232 u64 virtual_apic_page_addr
;
233 u64 apic_access_addr
;
234 u64 posted_intr_desc_addr
;
236 u64 eoi_exit_bitmap0
;
237 u64 eoi_exit_bitmap1
;
238 u64 eoi_exit_bitmap2
;
239 u64 eoi_exit_bitmap3
;
241 u64 guest_physical_address
;
242 u64 vmcs_link_pointer
;
243 u64 guest_ia32_debugctl
;
246 u64 guest_ia32_perf_global_ctrl
;
254 u64 host_ia32_perf_global_ctrl
;
255 u64 padding64
[8]; /* room for future expansion */
257 * To allow migration of L1 (complete with its L2 guests) between
258 * machines of different natural widths (32 or 64 bit), we cannot have
259 * unsigned long fields with no explict size. We use u64 (aliased
260 * natural_width) instead. Luckily, x86 is little-endian.
262 natural_width cr0_guest_host_mask
;
263 natural_width cr4_guest_host_mask
;
264 natural_width cr0_read_shadow
;
265 natural_width cr4_read_shadow
;
266 natural_width cr3_target_value0
;
267 natural_width cr3_target_value1
;
268 natural_width cr3_target_value2
;
269 natural_width cr3_target_value3
;
270 natural_width exit_qualification
;
271 natural_width guest_linear_address
;
272 natural_width guest_cr0
;
273 natural_width guest_cr3
;
274 natural_width guest_cr4
;
275 natural_width guest_es_base
;
276 natural_width guest_cs_base
;
277 natural_width guest_ss_base
;
278 natural_width guest_ds_base
;
279 natural_width guest_fs_base
;
280 natural_width guest_gs_base
;
281 natural_width guest_ldtr_base
;
282 natural_width guest_tr_base
;
283 natural_width guest_gdtr_base
;
284 natural_width guest_idtr_base
;
285 natural_width guest_dr7
;
286 natural_width guest_rsp
;
287 natural_width guest_rip
;
288 natural_width guest_rflags
;
289 natural_width guest_pending_dbg_exceptions
;
290 natural_width guest_sysenter_esp
;
291 natural_width guest_sysenter_eip
;
292 natural_width host_cr0
;
293 natural_width host_cr3
;
294 natural_width host_cr4
;
295 natural_width host_fs_base
;
296 natural_width host_gs_base
;
297 natural_width host_tr_base
;
298 natural_width host_gdtr_base
;
299 natural_width host_idtr_base
;
300 natural_width host_ia32_sysenter_esp
;
301 natural_width host_ia32_sysenter_eip
;
302 natural_width host_rsp
;
303 natural_width host_rip
;
304 natural_width paddingl
[8]; /* room for future expansion */
305 u32 pin_based_vm_exec_control
;
306 u32 cpu_based_vm_exec_control
;
307 u32 exception_bitmap
;
308 u32 page_fault_error_code_mask
;
309 u32 page_fault_error_code_match
;
310 u32 cr3_target_count
;
311 u32 vm_exit_controls
;
312 u32 vm_exit_msr_store_count
;
313 u32 vm_exit_msr_load_count
;
314 u32 vm_entry_controls
;
315 u32 vm_entry_msr_load_count
;
316 u32 vm_entry_intr_info_field
;
317 u32 vm_entry_exception_error_code
;
318 u32 vm_entry_instruction_len
;
320 u32 secondary_vm_exec_control
;
321 u32 vm_instruction_error
;
323 u32 vm_exit_intr_info
;
324 u32 vm_exit_intr_error_code
;
325 u32 idt_vectoring_info_field
;
326 u32 idt_vectoring_error_code
;
327 u32 vm_exit_instruction_len
;
328 u32 vmx_instruction_info
;
335 u32 guest_ldtr_limit
;
337 u32 guest_gdtr_limit
;
338 u32 guest_idtr_limit
;
339 u32 guest_es_ar_bytes
;
340 u32 guest_cs_ar_bytes
;
341 u32 guest_ss_ar_bytes
;
342 u32 guest_ds_ar_bytes
;
343 u32 guest_fs_ar_bytes
;
344 u32 guest_gs_ar_bytes
;
345 u32 guest_ldtr_ar_bytes
;
346 u32 guest_tr_ar_bytes
;
347 u32 guest_interruptibility_info
;
348 u32 guest_activity_state
;
349 u32 guest_sysenter_cs
;
350 u32 host_ia32_sysenter_cs
;
351 u32 vmx_preemption_timer_value
;
352 u32 padding32
[7]; /* room for future expansion */
353 u16 virtual_processor_id
;
355 u16 guest_es_selector
;
356 u16 guest_cs_selector
;
357 u16 guest_ss_selector
;
358 u16 guest_ds_selector
;
359 u16 guest_fs_selector
;
360 u16 guest_gs_selector
;
361 u16 guest_ldtr_selector
;
362 u16 guest_tr_selector
;
363 u16 guest_intr_status
;
364 u16 host_es_selector
;
365 u16 host_cs_selector
;
366 u16 host_ss_selector
;
367 u16 host_ds_selector
;
368 u16 host_fs_selector
;
369 u16 host_gs_selector
;
370 u16 host_tr_selector
;
374 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
375 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
376 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
378 #define VMCS12_REVISION 0x11e57ed0
381 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
382 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
383 * current implementation, 4K are reserved to avoid future complications.
385 #define VMCS12_SIZE 0x1000
387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
389 struct list_head list
;
391 struct loaded_vmcs vmcs02
;
395 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
396 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
399 /* Has the level1 guest done vmxon? */
403 /* The guest-physical address of the current VMCS L1 keeps for L2 */
405 /* The host-usable pointer to the above */
406 struct page
*current_vmcs12_page
;
407 struct vmcs12
*current_vmcs12
;
408 struct vmcs
*current_shadow_vmcs
;
410 * Indicates if the shadow vmcs must be updated with the
411 * data hold by vmcs12
413 bool sync_shadow_vmcs
;
415 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
416 struct list_head vmcs02_pool
;
418 u64 vmcs01_tsc_offset
;
419 /* L2 must run next, and mustn't decide to exit to L1. */
420 bool nested_run_pending
;
422 * Guest pages referred to in vmcs02 with host-physical pointers, so
423 * we must keep them pinned while L2 runs.
425 struct page
*apic_access_page
;
426 struct page
*virtual_apic_page
;
427 struct page
*pi_desc_page
;
428 struct pi_desc
*pi_desc
;
432 struct hrtimer preemption_timer
;
433 bool preemption_timer_expired
;
435 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
441 u32 nested_vmx_procbased_ctls_low
;
442 u32 nested_vmx_procbased_ctls_high
;
443 u32 nested_vmx_true_procbased_ctls_low
;
444 u32 nested_vmx_secondary_ctls_low
;
445 u32 nested_vmx_secondary_ctls_high
;
446 u32 nested_vmx_pinbased_ctls_low
;
447 u32 nested_vmx_pinbased_ctls_high
;
448 u32 nested_vmx_exit_ctls_low
;
449 u32 nested_vmx_exit_ctls_high
;
450 u32 nested_vmx_true_exit_ctls_low
;
451 u32 nested_vmx_entry_ctls_low
;
452 u32 nested_vmx_entry_ctls_high
;
453 u32 nested_vmx_true_entry_ctls_low
;
454 u32 nested_vmx_misc_low
;
455 u32 nested_vmx_misc_high
;
456 u32 nested_vmx_ept_caps
;
457 u32 nested_vmx_vpid_caps
;
460 #define POSTED_INTR_ON 0
461 #define POSTED_INTR_SN 1
463 /* Posted-Interrupt Descriptor */
465 u32 pir
[8]; /* Posted interrupt requested */
468 /* bit 256 - Outstanding Notification */
470 /* bit 257 - Suppress Notification */
472 /* bit 271:258 - Reserved */
474 /* bit 279:272 - Notification Vector */
476 /* bit 287:280 - Reserved */
478 /* bit 319:288 - Notification Destination */
486 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
488 return test_and_set_bit(POSTED_INTR_ON
,
489 (unsigned long *)&pi_desc
->control
);
492 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
494 return test_and_clear_bit(POSTED_INTR_ON
,
495 (unsigned long *)&pi_desc
->control
);
498 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
500 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
503 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
505 return clear_bit(POSTED_INTR_SN
,
506 (unsigned long *)&pi_desc
->control
);
509 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
511 return set_bit(POSTED_INTR_SN
,
512 (unsigned long *)&pi_desc
->control
);
515 static inline int pi_test_on(struct pi_desc
*pi_desc
)
517 return test_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
523 return test_bit(POSTED_INTR_SN
,
524 (unsigned long *)&pi_desc
->control
);
528 struct kvm_vcpu vcpu
;
529 unsigned long host_rsp
;
531 bool nmi_known_unmasked
;
533 u32 idt_vectoring_info
;
535 struct shared_msr_entry
*guest_msrs
;
538 unsigned long host_idt_base
;
540 u64 msr_host_kernel_gs_base
;
541 u64 msr_guest_kernel_gs_base
;
543 u32 vm_entry_controls_shadow
;
544 u32 vm_exit_controls_shadow
;
546 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
547 * non-nested (L1) guest, it always points to vmcs01. For a nested
548 * guest (L2), it points to a different VMCS.
550 struct loaded_vmcs vmcs01
;
551 struct loaded_vmcs
*loaded_vmcs
;
552 bool __launched
; /* temporary, used in vmx_vcpu_run */
553 struct msr_autoload
{
555 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
556 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
560 u16 fs_sel
, gs_sel
, ldt_sel
;
564 int gs_ldt_reload_needed
;
565 int fs_reload_needed
;
566 u64 msr_host_bndcfgs
;
567 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
572 struct kvm_segment segs
[8];
575 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
576 struct kvm_save_segment
{
584 bool emulation_required
;
586 /* Support for vnmi-less CPUs */
587 int soft_vnmi_blocked
;
589 s64 vnmi_blocked_time
;
592 /* Posted interrupt descriptor */
593 struct pi_desc pi_desc
;
595 /* Support for a guest hypervisor (nested VMX) */
596 struct nested_vmx nested
;
598 /* Dynamic PLE window. */
600 bool ple_window_dirty
;
602 /* Support for PML */
603 #define PML_ENTITY_NUM 512
606 /* apic deadline value in host tsc */
609 u64 current_tsc_ratio
;
611 bool guest_pkru_valid
;
616 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
617 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
618 * in msr_ia32_feature_control_valid_bits.
620 u64 msr_ia32_feature_control
;
621 u64 msr_ia32_feature_control_valid_bits
;
624 enum segment_cache_field
{
633 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
635 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
638 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
640 return &(to_vmx(vcpu
)->pi_desc
);
643 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
644 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
645 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
646 [number##_HIGH] = VMCS12_OFFSET(name)+4
649 static unsigned long shadow_read_only_fields
[] = {
651 * We do NOT shadow fields that are modified when L0
652 * traps and emulates any vmx instruction (e.g. VMPTRLD,
653 * VMXON...) executed by L1.
654 * For example, VM_INSTRUCTION_ERROR is read
655 * by L1 if a vmx instruction fails (part of the error path).
656 * Note the code assumes this logic. If for some reason
657 * we start shadowing these fields then we need to
658 * force a shadow sync when L0 emulates vmx instructions
659 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
660 * by nested_vmx_failValid)
664 VM_EXIT_INSTRUCTION_LEN
,
665 IDT_VECTORING_INFO_FIELD
,
666 IDT_VECTORING_ERROR_CODE
,
667 VM_EXIT_INTR_ERROR_CODE
,
669 GUEST_LINEAR_ADDRESS
,
670 GUEST_PHYSICAL_ADDRESS
672 static int max_shadow_read_only_fields
=
673 ARRAY_SIZE(shadow_read_only_fields
);
675 static unsigned long shadow_read_write_fields
[] = {
682 GUEST_INTERRUPTIBILITY_INFO
,
695 CPU_BASED_VM_EXEC_CONTROL
,
696 VM_ENTRY_EXCEPTION_ERROR_CODE
,
697 VM_ENTRY_INTR_INFO_FIELD
,
698 VM_ENTRY_INSTRUCTION_LEN
,
699 VM_ENTRY_EXCEPTION_ERROR_CODE
,
705 static int max_shadow_read_write_fields
=
706 ARRAY_SIZE(shadow_read_write_fields
);
708 static const unsigned short vmcs_field_to_offset_table
[] = {
709 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
710 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
711 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
712 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
713 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
714 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
715 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
716 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
717 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
718 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
719 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
720 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
721 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
722 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
723 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
724 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
725 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
726 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
727 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
728 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
729 FIELD64(MSR_BITMAP
, msr_bitmap
),
730 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
731 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
732 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
733 FIELD64(TSC_OFFSET
, tsc_offset
),
734 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
735 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
736 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
737 FIELD64(EPT_POINTER
, ept_pointer
),
738 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
739 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
740 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
741 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
742 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
743 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
744 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
745 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
746 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
747 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
748 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
749 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
750 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
751 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
752 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
753 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
754 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
755 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
756 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
757 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
758 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
759 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
760 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
761 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
762 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
763 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
764 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
765 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
766 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
767 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
768 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
769 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
770 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
771 FIELD(TPR_THRESHOLD
, tpr_threshold
),
772 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
773 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
774 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
775 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
776 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
777 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
778 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
779 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
780 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
781 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
782 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
783 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
784 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
785 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
786 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
787 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
788 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
789 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
790 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
791 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
792 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
793 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
794 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
795 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
796 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
797 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
798 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
799 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
800 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
801 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
802 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
803 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
804 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
805 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
806 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
807 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
808 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
809 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
810 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
811 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
812 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
813 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
814 FIELD(GUEST_CR0
, guest_cr0
),
815 FIELD(GUEST_CR3
, guest_cr3
),
816 FIELD(GUEST_CR4
, guest_cr4
),
817 FIELD(GUEST_ES_BASE
, guest_es_base
),
818 FIELD(GUEST_CS_BASE
, guest_cs_base
),
819 FIELD(GUEST_SS_BASE
, guest_ss_base
),
820 FIELD(GUEST_DS_BASE
, guest_ds_base
),
821 FIELD(GUEST_FS_BASE
, guest_fs_base
),
822 FIELD(GUEST_GS_BASE
, guest_gs_base
),
823 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
824 FIELD(GUEST_TR_BASE
, guest_tr_base
),
825 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
826 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
827 FIELD(GUEST_DR7
, guest_dr7
),
828 FIELD(GUEST_RSP
, guest_rsp
),
829 FIELD(GUEST_RIP
, guest_rip
),
830 FIELD(GUEST_RFLAGS
, guest_rflags
),
831 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
832 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
833 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
834 FIELD(HOST_CR0
, host_cr0
),
835 FIELD(HOST_CR3
, host_cr3
),
836 FIELD(HOST_CR4
, host_cr4
),
837 FIELD(HOST_FS_BASE
, host_fs_base
),
838 FIELD(HOST_GS_BASE
, host_gs_base
),
839 FIELD(HOST_TR_BASE
, host_tr_base
),
840 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
841 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
842 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
843 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
844 FIELD(HOST_RSP
, host_rsp
),
845 FIELD(HOST_RIP
, host_rip
),
848 static inline short vmcs_field_to_offset(unsigned long field
)
850 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
852 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
853 vmcs_field_to_offset_table
[field
] == 0)
856 return vmcs_field_to_offset_table
[field
];
859 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
861 return to_vmx(vcpu
)->nested
.current_vmcs12
;
864 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
866 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
867 if (is_error_page(page
))
873 static void nested_release_page(struct page
*page
)
875 kvm_release_page_dirty(page
);
878 static void nested_release_page_clean(struct page
*page
)
880 kvm_release_page_clean(page
);
883 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
884 static u64
construct_eptp(unsigned long root_hpa
);
885 static void kvm_cpu_vmxon(u64 addr
);
886 static void kvm_cpu_vmxoff(void);
887 static bool vmx_xsaves_supported(void);
888 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
889 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
890 struct kvm_segment
*var
, int seg
);
891 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
892 struct kvm_segment
*var
, int seg
);
893 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
894 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
895 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
896 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
897 static int alloc_identity_pagetable(struct kvm
*kvm
);
899 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
900 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
902 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
903 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
905 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
906 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
909 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
910 * can find which vCPU should be waken up.
912 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
913 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
915 static unsigned long *vmx_io_bitmap_a
;
916 static unsigned long *vmx_io_bitmap_b
;
917 static unsigned long *vmx_msr_bitmap_legacy
;
918 static unsigned long *vmx_msr_bitmap_longmode
;
919 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
920 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
921 static unsigned long *vmx_msr_bitmap_nested
;
922 static unsigned long *vmx_vmread_bitmap
;
923 static unsigned long *vmx_vmwrite_bitmap
;
925 static bool cpu_has_load_ia32_efer
;
926 static bool cpu_has_load_perf_global_ctrl
;
928 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
929 static DEFINE_SPINLOCK(vmx_vpid_lock
);
931 static struct vmcs_config
{
935 u32 pin_based_exec_ctrl
;
936 u32 cpu_based_exec_ctrl
;
937 u32 cpu_based_2nd_exec_ctrl
;
942 static struct vmx_capability
{
947 #define VMX_SEGMENT_FIELD(seg) \
948 [VCPU_SREG_##seg] = { \
949 .selector = GUEST_##seg##_SELECTOR, \
950 .base = GUEST_##seg##_BASE, \
951 .limit = GUEST_##seg##_LIMIT, \
952 .ar_bytes = GUEST_##seg##_AR_BYTES, \
955 static const struct kvm_vmx_segment_field
{
960 } kvm_vmx_segment_fields
[] = {
961 VMX_SEGMENT_FIELD(CS
),
962 VMX_SEGMENT_FIELD(DS
),
963 VMX_SEGMENT_FIELD(ES
),
964 VMX_SEGMENT_FIELD(FS
),
965 VMX_SEGMENT_FIELD(GS
),
966 VMX_SEGMENT_FIELD(SS
),
967 VMX_SEGMENT_FIELD(TR
),
968 VMX_SEGMENT_FIELD(LDTR
),
971 static u64 host_efer
;
973 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
976 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
977 * away by decrementing the array size.
979 static const u32 vmx_msr_index
[] = {
981 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
983 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
986 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
988 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
989 INTR_INFO_VALID_MASK
)) ==
990 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
993 static inline bool is_debug(u32 intr_info
)
995 return is_exception_n(intr_info
, DB_VECTOR
);
998 static inline bool is_breakpoint(u32 intr_info
)
1000 return is_exception_n(intr_info
, BP_VECTOR
);
1003 static inline bool is_page_fault(u32 intr_info
)
1005 return is_exception_n(intr_info
, PF_VECTOR
);
1008 static inline bool is_no_device(u32 intr_info
)
1010 return is_exception_n(intr_info
, NM_VECTOR
);
1013 static inline bool is_invalid_opcode(u32 intr_info
)
1015 return is_exception_n(intr_info
, UD_VECTOR
);
1018 static inline bool is_external_interrupt(u32 intr_info
)
1020 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1021 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1024 static inline bool is_machine_check(u32 intr_info
)
1026 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1027 INTR_INFO_VALID_MASK
)) ==
1028 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1031 static inline bool cpu_has_vmx_msr_bitmap(void)
1033 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1036 static inline bool cpu_has_vmx_tpr_shadow(void)
1038 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1041 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1043 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1046 static inline bool cpu_has_secondary_exec_ctrls(void)
1048 return vmcs_config
.cpu_based_exec_ctrl
&
1049 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1052 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1054 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1055 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1058 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1060 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1061 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1064 static inline bool cpu_has_vmx_apic_register_virt(void)
1066 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1067 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1070 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1072 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1073 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1077 * Comment's format: document - errata name - stepping - processor name.
1079 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1081 static u32 vmx_preemption_cpu_tfms
[] = {
1082 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1084 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1085 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1086 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1088 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1090 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1091 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1093 * 320767.pdf - AAP86 - B1 -
1094 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1097 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1099 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1101 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1103 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1104 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1105 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1109 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1111 u32 eax
= cpuid_eax(0x00000001), i
;
1113 /* Clear the reserved bits */
1114 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1115 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1116 if (eax
== vmx_preemption_cpu_tfms
[i
])
1122 static inline bool cpu_has_vmx_preemption_timer(void)
1124 if (cpu_has_broken_vmx_preemption_timer())
1127 return vmcs_config
.pin_based_exec_ctrl
&
1128 PIN_BASED_VMX_PREEMPTION_TIMER
;
1131 static inline bool cpu_has_vmx_posted_intr(void)
1133 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1134 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1137 static inline bool cpu_has_vmx_apicv(void)
1139 return cpu_has_vmx_apic_register_virt() &&
1140 cpu_has_vmx_virtual_intr_delivery() &&
1141 cpu_has_vmx_posted_intr();
1144 static inline bool cpu_has_vmx_flexpriority(void)
1146 return cpu_has_vmx_tpr_shadow() &&
1147 cpu_has_vmx_virtualize_apic_accesses();
1150 static inline bool cpu_has_vmx_ept_execute_only(void)
1152 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1155 static inline bool cpu_has_vmx_ept_2m_page(void)
1157 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1160 static inline bool cpu_has_vmx_ept_1g_page(void)
1162 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1165 static inline bool cpu_has_vmx_ept_4levels(void)
1167 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1170 static inline bool cpu_has_vmx_ept_ad_bits(void)
1172 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1175 static inline bool cpu_has_vmx_invept_context(void)
1177 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1180 static inline bool cpu_has_vmx_invept_global(void)
1182 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1185 static inline bool cpu_has_vmx_invvpid_single(void)
1187 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1190 static inline bool cpu_has_vmx_invvpid_global(void)
1192 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1195 static inline bool cpu_has_vmx_ept(void)
1197 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1198 SECONDARY_EXEC_ENABLE_EPT
;
1201 static inline bool cpu_has_vmx_unrestricted_guest(void)
1203 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1204 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1207 static inline bool cpu_has_vmx_ple(void)
1209 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1210 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1213 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1215 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1218 static inline bool cpu_has_vmx_vpid(void)
1220 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1221 SECONDARY_EXEC_ENABLE_VPID
;
1224 static inline bool cpu_has_vmx_rdtscp(void)
1226 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1227 SECONDARY_EXEC_RDTSCP
;
1230 static inline bool cpu_has_vmx_invpcid(void)
1232 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1233 SECONDARY_EXEC_ENABLE_INVPCID
;
1236 static inline bool cpu_has_virtual_nmis(void)
1238 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1241 static inline bool cpu_has_vmx_wbinvd_exit(void)
1243 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1244 SECONDARY_EXEC_WBINVD_EXITING
;
1247 static inline bool cpu_has_vmx_shadow_vmcs(void)
1250 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1251 /* check if the cpu supports writing r/o exit information fields */
1252 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1255 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1256 SECONDARY_EXEC_SHADOW_VMCS
;
1259 static inline bool cpu_has_vmx_pml(void)
1261 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1264 static inline bool cpu_has_vmx_tsc_scaling(void)
1266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1267 SECONDARY_EXEC_TSC_SCALING
;
1270 static inline bool report_flexpriority(void)
1272 return flexpriority_enabled
;
1275 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1277 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1280 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1282 return (vmcs12
->cpu_based_vm_exec_control
&
1283 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1284 (vmcs12
->secondary_vm_exec_control
& bit
);
1287 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1289 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1292 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1294 return vmcs12
->pin_based_vm_exec_control
&
1295 PIN_BASED_VMX_PREEMPTION_TIMER
;
1298 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1300 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1303 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1305 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1306 vmx_xsaves_supported();
1309 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1311 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1314 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1316 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1319 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1321 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1324 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1326 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1329 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1331 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1334 static inline bool is_exception(u32 intr_info
)
1336 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1337 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1340 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1342 unsigned long exit_qualification
);
1343 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1344 struct vmcs12
*vmcs12
,
1345 u32 reason
, unsigned long qualification
);
1347 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1351 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1352 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1357 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1363 } operand
= { vpid
, 0, gva
};
1365 asm volatile (__ex(ASM_VMX_INVVPID
)
1366 /* CF==1 or ZF==1 --> rc = -1 */
1367 "; ja 1f ; ud2 ; 1:"
1368 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1371 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1375 } operand
= {eptp
, gpa
};
1377 asm volatile (__ex(ASM_VMX_INVEPT
)
1378 /* CF==1 or ZF==1 --> rc = -1 */
1379 "; ja 1f ; ud2 ; 1:\n"
1380 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1383 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1387 i
= __find_msr_index(vmx
, msr
);
1389 return &vmx
->guest_msrs
[i
];
1393 static void vmcs_clear(struct vmcs
*vmcs
)
1395 u64 phys_addr
= __pa(vmcs
);
1398 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1399 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1402 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1406 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1408 vmcs_clear(loaded_vmcs
->vmcs
);
1409 loaded_vmcs
->cpu
= -1;
1410 loaded_vmcs
->launched
= 0;
1413 static void vmcs_load(struct vmcs
*vmcs
)
1415 u64 phys_addr
= __pa(vmcs
);
1418 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1419 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1422 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1426 #ifdef CONFIG_KEXEC_CORE
1428 * This bitmap is used to indicate whether the vmclear
1429 * operation is enabled on all cpus. All disabled by
1432 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1434 static inline void crash_enable_local_vmclear(int cpu
)
1436 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1439 static inline void crash_disable_local_vmclear(int cpu
)
1441 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1444 static inline int crash_local_vmclear_enabled(int cpu
)
1446 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1449 static void crash_vmclear_local_loaded_vmcss(void)
1451 int cpu
= raw_smp_processor_id();
1452 struct loaded_vmcs
*v
;
1454 if (!crash_local_vmclear_enabled(cpu
))
1457 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1458 loaded_vmcss_on_cpu_link
)
1459 vmcs_clear(v
->vmcs
);
1462 static inline void crash_enable_local_vmclear(int cpu
) { }
1463 static inline void crash_disable_local_vmclear(int cpu
) { }
1464 #endif /* CONFIG_KEXEC_CORE */
1466 static void __loaded_vmcs_clear(void *arg
)
1468 struct loaded_vmcs
*loaded_vmcs
= arg
;
1469 int cpu
= raw_smp_processor_id();
1471 if (loaded_vmcs
->cpu
!= cpu
)
1472 return; /* vcpu migration can race with cpu offline */
1473 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1474 per_cpu(current_vmcs
, cpu
) = NULL
;
1475 crash_disable_local_vmclear(cpu
);
1476 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1479 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1480 * is before setting loaded_vmcs->vcpu to -1 which is done in
1481 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1482 * then adds the vmcs into percpu list before it is deleted.
1486 loaded_vmcs_init(loaded_vmcs
);
1487 crash_enable_local_vmclear(cpu
);
1490 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1492 int cpu
= loaded_vmcs
->cpu
;
1495 smp_call_function_single(cpu
,
1496 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1499 static inline void vpid_sync_vcpu_single(int vpid
)
1504 if (cpu_has_vmx_invvpid_single())
1505 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1508 static inline void vpid_sync_vcpu_global(void)
1510 if (cpu_has_vmx_invvpid_global())
1511 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1514 static inline void vpid_sync_context(int vpid
)
1516 if (cpu_has_vmx_invvpid_single())
1517 vpid_sync_vcpu_single(vpid
);
1519 vpid_sync_vcpu_global();
1522 static inline void ept_sync_global(void)
1524 if (cpu_has_vmx_invept_global())
1525 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1528 static inline void ept_sync_context(u64 eptp
)
1531 if (cpu_has_vmx_invept_context())
1532 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1538 static __always_inline
void vmcs_check16(unsigned long field
)
1540 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1541 "16-bit accessor invalid for 64-bit field");
1542 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1543 "16-bit accessor invalid for 64-bit high field");
1544 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1545 "16-bit accessor invalid for 32-bit high field");
1546 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1547 "16-bit accessor invalid for natural width field");
1550 static __always_inline
void vmcs_check32(unsigned long field
)
1552 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1553 "32-bit accessor invalid for 16-bit field");
1554 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1555 "32-bit accessor invalid for natural width field");
1558 static __always_inline
void vmcs_check64(unsigned long field
)
1560 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1561 "64-bit accessor invalid for 16-bit field");
1562 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1563 "64-bit accessor invalid for 64-bit high field");
1564 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1565 "64-bit accessor invalid for 32-bit field");
1566 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1567 "64-bit accessor invalid for natural width field");
1570 static __always_inline
void vmcs_checkl(unsigned long field
)
1572 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1573 "Natural width accessor invalid for 16-bit field");
1574 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1575 "Natural width accessor invalid for 64-bit field");
1576 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1577 "Natural width accessor invalid for 64-bit high field");
1578 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1579 "Natural width accessor invalid for 32-bit field");
1582 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1584 unsigned long value
;
1586 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1587 : "=a"(value
) : "d"(field
) : "cc");
1591 static __always_inline u16
vmcs_read16(unsigned long field
)
1593 vmcs_check16(field
);
1594 return __vmcs_readl(field
);
1597 static __always_inline u32
vmcs_read32(unsigned long field
)
1599 vmcs_check32(field
);
1600 return __vmcs_readl(field
);
1603 static __always_inline u64
vmcs_read64(unsigned long field
)
1605 vmcs_check64(field
);
1606 #ifdef CONFIG_X86_64
1607 return __vmcs_readl(field
);
1609 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1613 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1616 return __vmcs_readl(field
);
1619 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1621 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1622 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1626 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1630 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1631 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1632 if (unlikely(error
))
1633 vmwrite_error(field
, value
);
1636 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1638 vmcs_check16(field
);
1639 __vmcs_writel(field
, value
);
1642 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1644 vmcs_check32(field
);
1645 __vmcs_writel(field
, value
);
1648 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1650 vmcs_check64(field
);
1651 __vmcs_writel(field
, value
);
1652 #ifndef CONFIG_X86_64
1654 __vmcs_writel(field
+1, value
>> 32);
1658 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1661 __vmcs_writel(field
, value
);
1664 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1666 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1667 "vmcs_clear_bits does not support 64-bit fields");
1668 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1671 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1673 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1674 "vmcs_set_bits does not support 64-bit fields");
1675 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1678 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1680 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1681 vmx
->vm_entry_controls_shadow
= val
;
1684 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1686 if (vmx
->vm_entry_controls_shadow
!= val
)
1687 vm_entry_controls_init(vmx
, val
);
1690 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1692 return vmx
->vm_entry_controls_shadow
;
1696 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1698 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1701 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1703 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1706 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1708 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1709 vmx
->vm_exit_controls_shadow
= val
;
1712 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1714 if (vmx
->vm_exit_controls_shadow
!= val
)
1715 vm_exit_controls_init(vmx
, val
);
1718 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1720 return vmx
->vm_exit_controls_shadow
;
1724 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1726 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1729 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1731 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1734 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1736 vmx
->segment_cache
.bitmask
= 0;
1739 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1743 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1745 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1746 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1747 vmx
->segment_cache
.bitmask
= 0;
1749 ret
= vmx
->segment_cache
.bitmask
& mask
;
1750 vmx
->segment_cache
.bitmask
|= mask
;
1754 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1756 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1758 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1759 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1763 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1765 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1767 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1768 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1772 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1774 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1776 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1777 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1781 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1783 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1785 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1786 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1790 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1794 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1795 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1796 if ((vcpu
->guest_debug
&
1797 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1798 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1799 eb
|= 1u << BP_VECTOR
;
1800 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1803 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1804 if (vcpu
->fpu_active
)
1805 eb
&= ~(1u << NM_VECTOR
);
1807 /* When we are running a nested L2 guest and L1 specified for it a
1808 * certain exception bitmap, we must trap the same exceptions and pass
1809 * them to L1. When running L2, we will only handle the exceptions
1810 * specified above if L1 did not want them.
1812 if (is_guest_mode(vcpu
))
1813 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1815 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1818 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1819 unsigned long entry
, unsigned long exit
)
1821 vm_entry_controls_clearbit(vmx
, entry
);
1822 vm_exit_controls_clearbit(vmx
, exit
);
1825 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1828 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1832 if (cpu_has_load_ia32_efer
) {
1833 clear_atomic_switch_msr_special(vmx
,
1834 VM_ENTRY_LOAD_IA32_EFER
,
1835 VM_EXIT_LOAD_IA32_EFER
);
1839 case MSR_CORE_PERF_GLOBAL_CTRL
:
1840 if (cpu_has_load_perf_global_ctrl
) {
1841 clear_atomic_switch_msr_special(vmx
,
1842 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1843 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1849 for (i
= 0; i
< m
->nr
; ++i
)
1850 if (m
->guest
[i
].index
== msr
)
1856 m
->guest
[i
] = m
->guest
[m
->nr
];
1857 m
->host
[i
] = m
->host
[m
->nr
];
1858 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1859 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1862 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1863 unsigned long entry
, unsigned long exit
,
1864 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1865 u64 guest_val
, u64 host_val
)
1867 vmcs_write64(guest_val_vmcs
, guest_val
);
1868 vmcs_write64(host_val_vmcs
, host_val
);
1869 vm_entry_controls_setbit(vmx
, entry
);
1870 vm_exit_controls_setbit(vmx
, exit
);
1873 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1874 u64 guest_val
, u64 host_val
)
1877 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1881 if (cpu_has_load_ia32_efer
) {
1882 add_atomic_switch_msr_special(vmx
,
1883 VM_ENTRY_LOAD_IA32_EFER
,
1884 VM_EXIT_LOAD_IA32_EFER
,
1887 guest_val
, host_val
);
1891 case MSR_CORE_PERF_GLOBAL_CTRL
:
1892 if (cpu_has_load_perf_global_ctrl
) {
1893 add_atomic_switch_msr_special(vmx
,
1894 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1895 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1896 GUEST_IA32_PERF_GLOBAL_CTRL
,
1897 HOST_IA32_PERF_GLOBAL_CTRL
,
1898 guest_val
, host_val
);
1902 case MSR_IA32_PEBS_ENABLE
:
1903 /* PEBS needs a quiescent period after being disabled (to write
1904 * a record). Disabling PEBS through VMX MSR swapping doesn't
1905 * provide that period, so a CPU could write host's record into
1908 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1911 for (i
= 0; i
< m
->nr
; ++i
)
1912 if (m
->guest
[i
].index
== msr
)
1915 if (i
== NR_AUTOLOAD_MSRS
) {
1916 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1917 "Can't add msr %x\n", msr
);
1919 } else if (i
== m
->nr
) {
1921 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1922 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1925 m
->guest
[i
].index
= msr
;
1926 m
->guest
[i
].value
= guest_val
;
1927 m
->host
[i
].index
= msr
;
1928 m
->host
[i
].value
= host_val
;
1931 static void reload_tss(void)
1934 * VT restores TR but not its size. Useless.
1936 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1937 struct desc_struct
*descs
;
1939 descs
= (void *)gdt
->address
;
1940 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1944 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1946 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1947 u64 ignore_bits
= 0;
1951 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1952 * host CPUID is more efficient than testing guest CPUID
1953 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1955 if (boot_cpu_has(X86_FEATURE_SMEP
))
1956 guest_efer
|= EFER_NX
;
1957 else if (!(guest_efer
& EFER_NX
))
1958 ignore_bits
|= EFER_NX
;
1962 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1964 ignore_bits
|= EFER_SCE
;
1965 #ifdef CONFIG_X86_64
1966 ignore_bits
|= EFER_LMA
| EFER_LME
;
1967 /* SCE is meaningful only in long mode on Intel */
1968 if (guest_efer
& EFER_LMA
)
1969 ignore_bits
&= ~(u64
)EFER_SCE
;
1972 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1975 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1976 * On CPUs that support "load IA32_EFER", always switch EFER
1977 * atomically, since it's faster than switching it manually.
1979 if (cpu_has_load_ia32_efer
||
1980 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1981 if (!(guest_efer
& EFER_LMA
))
1982 guest_efer
&= ~EFER_LME
;
1983 if (guest_efer
!= host_efer
)
1984 add_atomic_switch_msr(vmx
, MSR_EFER
,
1985 guest_efer
, host_efer
);
1988 guest_efer
&= ~ignore_bits
;
1989 guest_efer
|= host_efer
& ignore_bits
;
1991 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1992 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1998 static unsigned long segment_base(u16 selector
)
2000 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2001 struct desc_struct
*d
;
2002 unsigned long table_base
;
2005 if (!(selector
& ~3))
2008 table_base
= gdt
->address
;
2010 if (selector
& 4) { /* from ldt */
2011 u16 ldt_selector
= kvm_read_ldt();
2013 if (!(ldt_selector
& ~3))
2016 table_base
= segment_base(ldt_selector
);
2018 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
2019 v
= get_desc_base(d
);
2020 #ifdef CONFIG_X86_64
2021 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
2022 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
2027 static inline unsigned long kvm_read_tr_base(void)
2030 asm("str %0" : "=g"(tr
));
2031 return segment_base(tr
);
2034 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2036 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2039 if (vmx
->host_state
.loaded
)
2042 vmx
->host_state
.loaded
= 1;
2044 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2045 * allow segment selectors with cpl > 0 or ti == 1.
2047 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2048 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2049 savesegment(fs
, vmx
->host_state
.fs_sel
);
2050 if (!(vmx
->host_state
.fs_sel
& 7)) {
2051 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2052 vmx
->host_state
.fs_reload_needed
= 0;
2054 vmcs_write16(HOST_FS_SELECTOR
, 0);
2055 vmx
->host_state
.fs_reload_needed
= 1;
2057 savesegment(gs
, vmx
->host_state
.gs_sel
);
2058 if (!(vmx
->host_state
.gs_sel
& 7))
2059 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2061 vmcs_write16(HOST_GS_SELECTOR
, 0);
2062 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2065 #ifdef CONFIG_X86_64
2066 savesegment(ds
, vmx
->host_state
.ds_sel
);
2067 savesegment(es
, vmx
->host_state
.es_sel
);
2070 #ifdef CONFIG_X86_64
2071 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2072 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2074 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2075 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2078 #ifdef CONFIG_X86_64
2079 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2080 if (is_long_mode(&vmx
->vcpu
))
2081 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2083 if (boot_cpu_has(X86_FEATURE_MPX
))
2084 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2085 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2086 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2087 vmx
->guest_msrs
[i
].data
,
2088 vmx
->guest_msrs
[i
].mask
);
2091 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2093 if (!vmx
->host_state
.loaded
)
2096 ++vmx
->vcpu
.stat
.host_state_reload
;
2097 vmx
->host_state
.loaded
= 0;
2098 #ifdef CONFIG_X86_64
2099 if (is_long_mode(&vmx
->vcpu
))
2100 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2102 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2103 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2104 #ifdef CONFIG_X86_64
2105 load_gs_index(vmx
->host_state
.gs_sel
);
2107 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2110 if (vmx
->host_state
.fs_reload_needed
)
2111 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2112 #ifdef CONFIG_X86_64
2113 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2114 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2115 loadsegment(es
, vmx
->host_state
.es_sel
);
2119 #ifdef CONFIG_X86_64
2120 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2122 if (vmx
->host_state
.msr_host_bndcfgs
)
2123 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2125 * If the FPU is not active (through the host task or
2126 * the guest vcpu), then restore the cr0.TS bit.
2128 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2130 load_gdt(this_cpu_ptr(&host_gdt
));
2133 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2136 __vmx_load_host_state(vmx
);
2140 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2142 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2143 struct pi_desc old
, new;
2146 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2147 !irq_remapping_cap(IRQ_POSTING_CAP
))
2151 old
.control
= new.control
= pi_desc
->control
;
2154 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2155 * are two possible cases:
2156 * 1. After running 'pre_block', context switch
2157 * happened. For this case, 'sn' was set in
2158 * vmx_vcpu_put(), so we need to clear it here.
2159 * 2. After running 'pre_block', we were blocked,
2160 * and woken up by some other guy. For this case,
2161 * we don't need to do anything, 'pi_post_block'
2162 * will do everything for us. However, we cannot
2163 * check whether it is case #1 or case #2 here
2164 * (maybe, not needed), so we also clear sn here,
2165 * I think it is not a big deal.
2167 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2168 if (vcpu
->cpu
!= cpu
) {
2169 dest
= cpu_physical_id(cpu
);
2171 if (x2apic_enabled())
2174 new.ndst
= (dest
<< 8) & 0xFF00;
2177 /* set 'NV' to 'notification vector' */
2178 new.nv
= POSTED_INTR_VECTOR
;
2181 /* Allow posting non-urgent interrupts */
2183 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2184 new.control
) != old
.control
);
2188 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2189 * vcpu mutex is already taken.
2191 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2194 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2197 kvm_cpu_vmxon(phys_addr
);
2198 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2199 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2201 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2202 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2203 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2206 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2207 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2208 unsigned long sysenter_esp
;
2210 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2211 local_irq_disable();
2212 crash_disable_local_vmclear(cpu
);
2215 * Read loaded_vmcs->cpu should be before fetching
2216 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2217 * See the comments in __loaded_vmcs_clear().
2221 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2222 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2223 crash_enable_local_vmclear(cpu
);
2227 * Linux uses per-cpu TSS and GDT, so set these when switching
2230 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2231 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2233 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2234 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2236 vmx
->loaded_vmcs
->cpu
= cpu
;
2239 /* Setup TSC multiplier */
2240 if (kvm_has_tsc_control
&&
2241 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
) {
2242 vmx
->current_tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2243 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2246 vmx_vcpu_pi_load(vcpu
, cpu
);
2247 vmx
->host_pkru
= read_pkru();
2250 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2252 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2254 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2255 !irq_remapping_cap(IRQ_POSTING_CAP
))
2258 /* Set SN when the vCPU is preempted */
2259 if (vcpu
->preempted
)
2263 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2265 vmx_vcpu_pi_put(vcpu
);
2267 __vmx_load_host_state(to_vmx(vcpu
));
2268 if (!vmm_exclusive
) {
2269 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2275 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2279 if (vcpu
->fpu_active
)
2281 vcpu
->fpu_active
= 1;
2282 cr0
= vmcs_readl(GUEST_CR0
);
2283 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2284 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2285 vmcs_writel(GUEST_CR0
, cr0
);
2286 update_exception_bitmap(vcpu
);
2287 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2288 if (is_guest_mode(vcpu
))
2289 vcpu
->arch
.cr0_guest_owned_bits
&=
2290 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2291 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2294 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2297 * Return the cr0 value that a nested guest would read. This is a combination
2298 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2299 * its hypervisor (cr0_read_shadow).
2301 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2303 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2304 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2306 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2308 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2309 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2312 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2314 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2315 * set this *before* calling this function.
2317 vmx_decache_cr0_guest_bits(vcpu
);
2318 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2319 update_exception_bitmap(vcpu
);
2320 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2321 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2322 if (is_guest_mode(vcpu
)) {
2324 * L1's specified read shadow might not contain the TS bit,
2325 * so now that we turned on shadowing of this bit, we need to
2326 * set this bit of the shadow. Like in nested_vmx_run we need
2327 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2328 * up-to-date here because we just decached cr0.TS (and we'll
2329 * only update vmcs12->guest_cr0 on nested exit).
2331 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2332 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2333 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2334 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2336 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2339 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2341 unsigned long rflags
, save_rflags
;
2343 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2344 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2345 rflags
= vmcs_readl(GUEST_RFLAGS
);
2346 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2347 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2348 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2349 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2351 to_vmx(vcpu
)->rflags
= rflags
;
2353 return to_vmx(vcpu
)->rflags
;
2356 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2358 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2359 to_vmx(vcpu
)->rflags
= rflags
;
2360 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2361 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2362 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2364 vmcs_writel(GUEST_RFLAGS
, rflags
);
2367 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2369 return to_vmx(vcpu
)->guest_pkru
;
2372 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2374 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2377 if (interruptibility
& GUEST_INTR_STATE_STI
)
2378 ret
|= KVM_X86_SHADOW_INT_STI
;
2379 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2380 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2385 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2387 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2388 u32 interruptibility
= interruptibility_old
;
2390 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2392 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2393 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2394 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2395 interruptibility
|= GUEST_INTR_STATE_STI
;
2397 if ((interruptibility
!= interruptibility_old
))
2398 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2401 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2405 rip
= kvm_rip_read(vcpu
);
2406 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2407 kvm_rip_write(vcpu
, rip
);
2409 /* skipping an emulated instruction also counts */
2410 vmx_set_interrupt_shadow(vcpu
, 0);
2414 * KVM wants to inject page-faults which it got to the guest. This function
2415 * checks whether in a nested guest, we need to inject them to L1 or L2.
2417 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2419 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2421 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2424 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2425 vmcs_read32(VM_EXIT_INTR_INFO
),
2426 vmcs_readl(EXIT_QUALIFICATION
));
2430 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2431 bool has_error_code
, u32 error_code
,
2434 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2435 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2437 if (!reinject
&& is_guest_mode(vcpu
) &&
2438 nested_vmx_check_exception(vcpu
, nr
))
2441 if (has_error_code
) {
2442 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2443 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2446 if (vmx
->rmode
.vm86_active
) {
2448 if (kvm_exception_is_soft(nr
))
2449 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2450 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2451 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2455 if (kvm_exception_is_soft(nr
)) {
2456 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2457 vmx
->vcpu
.arch
.event_exit_inst_len
);
2458 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2460 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2462 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2465 static bool vmx_rdtscp_supported(void)
2467 return cpu_has_vmx_rdtscp();
2470 static bool vmx_invpcid_supported(void)
2472 return cpu_has_vmx_invpcid() && enable_ept
;
2476 * Swap MSR entry in host/guest MSR entry array.
2478 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2480 struct shared_msr_entry tmp
;
2482 tmp
= vmx
->guest_msrs
[to
];
2483 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2484 vmx
->guest_msrs
[from
] = tmp
;
2487 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2489 unsigned long *msr_bitmap
;
2491 if (is_guest_mode(vcpu
))
2492 msr_bitmap
= vmx_msr_bitmap_nested
;
2493 else if (cpu_has_secondary_exec_ctrls() &&
2494 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2495 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2496 if (is_long_mode(vcpu
))
2497 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2499 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2501 if (is_long_mode(vcpu
))
2502 msr_bitmap
= vmx_msr_bitmap_longmode
;
2504 msr_bitmap
= vmx_msr_bitmap_legacy
;
2507 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2511 * Set up the vmcs to automatically save and restore system
2512 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2513 * mode, as fiddling with msrs is very expensive.
2515 static void setup_msrs(struct vcpu_vmx
*vmx
)
2517 int save_nmsrs
, index
;
2520 #ifdef CONFIG_X86_64
2521 if (is_long_mode(&vmx
->vcpu
)) {
2522 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2524 move_msr_up(vmx
, index
, save_nmsrs
++);
2525 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2527 move_msr_up(vmx
, index
, save_nmsrs
++);
2528 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2530 move_msr_up(vmx
, index
, save_nmsrs
++);
2531 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2532 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2533 move_msr_up(vmx
, index
, save_nmsrs
++);
2535 * MSR_STAR is only needed on long mode guests, and only
2536 * if efer.sce is enabled.
2538 index
= __find_msr_index(vmx
, MSR_STAR
);
2539 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2540 move_msr_up(vmx
, index
, save_nmsrs
++);
2543 index
= __find_msr_index(vmx
, MSR_EFER
);
2544 if (index
>= 0 && update_transition_efer(vmx
, index
))
2545 move_msr_up(vmx
, index
, save_nmsrs
++);
2547 vmx
->save_nmsrs
= save_nmsrs
;
2549 if (cpu_has_vmx_msr_bitmap())
2550 vmx_set_msr_bitmap(&vmx
->vcpu
);
2554 * reads and returns guest's timestamp counter "register"
2555 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2556 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2558 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2560 u64 host_tsc
, tsc_offset
;
2563 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2564 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2568 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2569 * counter, even if a nested guest (L2) is currently running.
2571 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2575 tsc_offset
= is_guest_mode(vcpu
) ?
2576 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2577 vmcs_read64(TSC_OFFSET
);
2578 return host_tsc
+ tsc_offset
;
2581 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2583 return vmcs_read64(TSC_OFFSET
);
2587 * writes 'offset' into guest's timestamp counter offset register
2589 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2591 if (is_guest_mode(vcpu
)) {
2593 * We're here if L1 chose not to trap WRMSR to TSC. According
2594 * to the spec, this should set L1's TSC; The offset that L1
2595 * set for L2 remains unchanged, and still needs to be added
2596 * to the newly set TSC to get L2's TSC.
2598 struct vmcs12
*vmcs12
;
2599 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2600 /* recalculate vmcs02.TSC_OFFSET: */
2601 vmcs12
= get_vmcs12(vcpu
);
2602 vmcs_write64(TSC_OFFSET
, offset
+
2603 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2604 vmcs12
->tsc_offset
: 0));
2606 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2607 vmcs_read64(TSC_OFFSET
), offset
);
2608 vmcs_write64(TSC_OFFSET
, offset
);
2612 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2614 u64 offset
= vmcs_read64(TSC_OFFSET
);
2616 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2617 if (is_guest_mode(vcpu
)) {
2618 /* Even when running L2, the adjustment needs to apply to L1 */
2619 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2621 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2622 offset
+ adjustment
);
2625 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2627 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2628 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2632 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2633 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2634 * all guests if the "nested" module option is off, and can also be disabled
2635 * for a single guest by disabling its VMX cpuid bit.
2637 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2639 return nested
&& guest_cpuid_has_vmx(vcpu
);
2643 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2644 * returned for the various VMX controls MSRs when nested VMX is enabled.
2645 * The same values should also be used to verify that vmcs12 control fields are
2646 * valid during nested entry from L1 to L2.
2647 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2648 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2649 * bit in the high half is on if the corresponding bit in the control field
2650 * may be on. See also vmx_control_verify().
2652 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2655 * Note that as a general rule, the high half of the MSRs (bits in
2656 * the control fields which may be 1) should be initialized by the
2657 * intersection of the underlying hardware's MSR (i.e., features which
2658 * can be supported) and the list of features we want to expose -
2659 * because they are known to be properly supported in our code.
2660 * Also, usually, the low half of the MSRs (bits which must be 1) can
2661 * be set to 0, meaning that L1 may turn off any of these bits. The
2662 * reason is that if one of these bits is necessary, it will appear
2663 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2664 * fields of vmcs01 and vmcs02, will turn these bits off - and
2665 * nested_vmx_exit_handled() will not pass related exits to L1.
2666 * These rules have exceptions below.
2669 /* pin-based controls */
2670 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2671 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2672 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2673 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2674 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2675 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2676 PIN_BASED_EXT_INTR_MASK
|
2677 PIN_BASED_NMI_EXITING
|
2678 PIN_BASED_VIRTUAL_NMIS
;
2679 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2680 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2681 PIN_BASED_VMX_PREEMPTION_TIMER
;
2682 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2683 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2684 PIN_BASED_POSTED_INTR
;
2687 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2688 vmx
->nested
.nested_vmx_exit_ctls_low
,
2689 vmx
->nested
.nested_vmx_exit_ctls_high
);
2690 vmx
->nested
.nested_vmx_exit_ctls_low
=
2691 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2693 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2694 #ifdef CONFIG_X86_64
2695 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2697 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2698 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2699 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2700 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2701 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2703 if (kvm_mpx_supported())
2704 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2706 /* We support free control of debug control saving. */
2707 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2708 vmx
->nested
.nested_vmx_exit_ctls_low
&
2709 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2711 /* entry controls */
2712 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2713 vmx
->nested
.nested_vmx_entry_ctls_low
,
2714 vmx
->nested
.nested_vmx_entry_ctls_high
);
2715 vmx
->nested
.nested_vmx_entry_ctls_low
=
2716 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2717 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2718 #ifdef CONFIG_X86_64
2719 VM_ENTRY_IA32E_MODE
|
2721 VM_ENTRY_LOAD_IA32_PAT
;
2722 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2723 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2724 if (kvm_mpx_supported())
2725 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2727 /* We support free control of debug control loading. */
2728 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2729 vmx
->nested
.nested_vmx_entry_ctls_low
&
2730 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2732 /* cpu-based controls */
2733 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2734 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2735 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2736 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2737 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2738 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2739 CPU_BASED_VIRTUAL_INTR_PENDING
|
2740 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2741 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2742 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2743 CPU_BASED_CR3_STORE_EXITING
|
2744 #ifdef CONFIG_X86_64
2745 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2747 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2748 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2749 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2750 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2751 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2753 * We can allow some features even when not supported by the
2754 * hardware. For example, L1 can specify an MSR bitmap - and we
2755 * can use it to avoid exits to L1 - even when L0 runs L2
2756 * without MSR bitmaps.
2758 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2759 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2760 CPU_BASED_USE_MSR_BITMAPS
;
2762 /* We support free control of CR3 access interception. */
2763 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2764 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2765 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2767 /* secondary cpu-based controls */
2768 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2769 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2770 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2771 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2772 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2773 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2774 SECONDARY_EXEC_RDTSCP
|
2775 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2776 SECONDARY_EXEC_ENABLE_VPID
|
2777 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2778 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2779 SECONDARY_EXEC_WBINVD_EXITING
|
2780 SECONDARY_EXEC_XSAVES
|
2781 SECONDARY_EXEC_PCOMMIT
;
2784 /* nested EPT: emulate EPT also to L1 */
2785 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2786 SECONDARY_EXEC_ENABLE_EPT
;
2787 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2788 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2790 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2792 * For nested guests, we don't do anything specific
2793 * for single context invalidation. Hence, only advertise
2794 * support for global context invalidation.
2796 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2798 vmx
->nested
.nested_vmx_ept_caps
= 0;
2801 * Old versions of KVM use the single-context version without
2802 * checking for support, so declare that it is supported even
2803 * though it is treated as global context. The alternative is
2804 * not failing the single-context invvpid, and it is worse.
2807 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2808 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
|
2809 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2811 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2813 if (enable_unrestricted_guest
)
2814 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2815 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2817 /* miscellaneous data */
2818 rdmsr(MSR_IA32_VMX_MISC
,
2819 vmx
->nested
.nested_vmx_misc_low
,
2820 vmx
->nested
.nested_vmx_misc_high
);
2821 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2822 vmx
->nested
.nested_vmx_misc_low
|=
2823 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2824 VMX_MISC_ACTIVITY_HLT
;
2825 vmx
->nested
.nested_vmx_misc_high
= 0;
2828 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2831 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2833 return ((control
& high
) | low
) == control
;
2836 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2838 return low
| ((u64
)high
<< 32);
2841 /* Returns 0 on success, non-0 otherwise. */
2842 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2844 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2846 switch (msr_index
) {
2847 case MSR_IA32_VMX_BASIC
:
2849 * This MSR reports some information about VMX support. We
2850 * should return information about the VMX we emulate for the
2851 * guest, and the VMCS structure we give it - not about the
2852 * VMX support of the underlying hardware.
2854 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2855 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2856 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2858 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2859 case MSR_IA32_VMX_PINBASED_CTLS
:
2860 *pdata
= vmx_control_msr(
2861 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2862 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2864 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2865 *pdata
= vmx_control_msr(
2866 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2867 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2869 case MSR_IA32_VMX_PROCBASED_CTLS
:
2870 *pdata
= vmx_control_msr(
2871 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2872 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2874 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2875 *pdata
= vmx_control_msr(
2876 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2877 vmx
->nested
.nested_vmx_exit_ctls_high
);
2879 case MSR_IA32_VMX_EXIT_CTLS
:
2880 *pdata
= vmx_control_msr(
2881 vmx
->nested
.nested_vmx_exit_ctls_low
,
2882 vmx
->nested
.nested_vmx_exit_ctls_high
);
2884 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2885 *pdata
= vmx_control_msr(
2886 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2887 vmx
->nested
.nested_vmx_entry_ctls_high
);
2889 case MSR_IA32_VMX_ENTRY_CTLS
:
2890 *pdata
= vmx_control_msr(
2891 vmx
->nested
.nested_vmx_entry_ctls_low
,
2892 vmx
->nested
.nested_vmx_entry_ctls_high
);
2894 case MSR_IA32_VMX_MISC
:
2895 *pdata
= vmx_control_msr(
2896 vmx
->nested
.nested_vmx_misc_low
,
2897 vmx
->nested
.nested_vmx_misc_high
);
2900 * These MSRs specify bits which the guest must keep fixed (on or off)
2901 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2902 * We picked the standard core2 setting.
2904 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2905 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2906 case MSR_IA32_VMX_CR0_FIXED0
:
2907 *pdata
= VMXON_CR0_ALWAYSON
;
2909 case MSR_IA32_VMX_CR0_FIXED1
:
2912 case MSR_IA32_VMX_CR4_FIXED0
:
2913 *pdata
= VMXON_CR4_ALWAYSON
;
2915 case MSR_IA32_VMX_CR4_FIXED1
:
2918 case MSR_IA32_VMX_VMCS_ENUM
:
2919 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2921 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2922 *pdata
= vmx_control_msr(
2923 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2924 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2926 case MSR_IA32_VMX_EPT_VPID_CAP
:
2927 /* Currently, no nested vpid support */
2928 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2929 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2938 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
2941 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
2943 return !(val
& ~valid_bits
);
2947 * Reads an msr value (of 'msr_index') into 'pdata'.
2948 * Returns 0 on success, non-0 otherwise.
2949 * Assumes vcpu_load() was already called.
2951 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2953 struct shared_msr_entry
*msr
;
2955 switch (msr_info
->index
) {
2956 #ifdef CONFIG_X86_64
2958 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2961 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2963 case MSR_KERNEL_GS_BASE
:
2964 vmx_load_host_state(to_vmx(vcpu
));
2965 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2969 return kvm_get_msr_common(vcpu
, msr_info
);
2971 msr_info
->data
= guest_read_tsc(vcpu
);
2973 case MSR_IA32_SYSENTER_CS
:
2974 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2976 case MSR_IA32_SYSENTER_EIP
:
2977 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2979 case MSR_IA32_SYSENTER_ESP
:
2980 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2982 case MSR_IA32_BNDCFGS
:
2983 if (!kvm_mpx_supported())
2985 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2987 case MSR_IA32_MCG_EXT_CTL
:
2988 if (!msr_info
->host_initiated
&&
2989 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
2990 FEATURE_CONTROL_LMCE
))
2992 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
2994 case MSR_IA32_FEATURE_CONTROL
:
2995 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
2997 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2998 if (!nested_vmx_allowed(vcpu
))
3000 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3002 if (!vmx_xsaves_supported())
3004 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3007 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3009 /* Otherwise falls through */
3011 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3013 msr_info
->data
= msr
->data
;
3016 return kvm_get_msr_common(vcpu
, msr_info
);
3022 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3025 * Writes msr value into into the appropriate "register".
3026 * Returns 0 on success, non-0 otherwise.
3027 * Assumes vcpu_load() was already called.
3029 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3031 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3032 struct shared_msr_entry
*msr
;
3034 u32 msr_index
= msr_info
->index
;
3035 u64 data
= msr_info
->data
;
3037 switch (msr_index
) {
3039 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3041 #ifdef CONFIG_X86_64
3043 vmx_segment_cache_clear(vmx
);
3044 vmcs_writel(GUEST_FS_BASE
, data
);
3047 vmx_segment_cache_clear(vmx
);
3048 vmcs_writel(GUEST_GS_BASE
, data
);
3050 case MSR_KERNEL_GS_BASE
:
3051 vmx_load_host_state(vmx
);
3052 vmx
->msr_guest_kernel_gs_base
= data
;
3055 case MSR_IA32_SYSENTER_CS
:
3056 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3058 case MSR_IA32_SYSENTER_EIP
:
3059 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3061 case MSR_IA32_SYSENTER_ESP
:
3062 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3064 case MSR_IA32_BNDCFGS
:
3065 if (!kvm_mpx_supported())
3067 vmcs_write64(GUEST_BNDCFGS
, data
);
3070 kvm_write_tsc(vcpu
, msr_info
);
3072 case MSR_IA32_CR_PAT
:
3073 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3074 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3076 vmcs_write64(GUEST_IA32_PAT
, data
);
3077 vcpu
->arch
.pat
= data
;
3080 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3082 case MSR_IA32_TSC_ADJUST
:
3083 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3085 case MSR_IA32_MCG_EXT_CTL
:
3086 if ((!msr_info
->host_initiated
&&
3087 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3088 FEATURE_CONTROL_LMCE
)) ||
3089 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3091 vcpu
->arch
.mcg_ext_ctl
= data
;
3093 case MSR_IA32_FEATURE_CONTROL
:
3094 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3095 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3096 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3098 vmx
->msr_ia32_feature_control
= data
;
3099 if (msr_info
->host_initiated
&& data
== 0)
3100 vmx_leave_nested(vcpu
);
3102 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3103 return 1; /* they are read-only */
3105 if (!vmx_xsaves_supported())
3108 * The only supported bit as of Skylake is bit 8, but
3109 * it is not supported on KVM.
3113 vcpu
->arch
.ia32_xss
= data
;
3114 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3115 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3116 vcpu
->arch
.ia32_xss
, host_xss
);
3118 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3121 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3123 /* Check reserved bit, higher 32 bits should be zero */
3124 if ((data
>> 32) != 0)
3126 /* Otherwise falls through */
3128 msr
= find_msr_entry(vmx
, msr_index
);
3130 u64 old_msr_data
= msr
->data
;
3132 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3134 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3138 msr
->data
= old_msr_data
;
3142 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3148 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3150 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3153 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3156 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3158 case VCPU_EXREG_PDPTR
:
3160 ept_save_pdptrs(vcpu
);
3167 static __init
int cpu_has_kvm_support(void)
3169 return cpu_has_vmx();
3172 static __init
int vmx_disabled_by_bios(void)
3176 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3177 if (msr
& FEATURE_CONTROL_LOCKED
) {
3178 /* launched w/ TXT and VMX disabled */
3179 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3182 /* launched w/o TXT and VMX only enabled w/ TXT */
3183 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3184 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3185 && !tboot_enabled()) {
3186 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3187 "activate TXT before enabling KVM\n");
3190 /* launched w/o TXT and VMX disabled */
3191 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3192 && !tboot_enabled())
3199 static void kvm_cpu_vmxon(u64 addr
)
3201 intel_pt_handle_vmx(1);
3203 asm volatile (ASM_VMX_VMXON_RAX
3204 : : "a"(&addr
), "m"(addr
)
3208 static int hardware_enable(void)
3210 int cpu
= raw_smp_processor_id();
3211 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3214 if (cr4_read_shadow() & X86_CR4_VMXE
)
3217 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3218 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3219 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3222 * Now we can enable the vmclear operation in kdump
3223 * since the loaded_vmcss_on_cpu list on this cpu
3224 * has been initialized.
3226 * Though the cpu is not in VMX operation now, there
3227 * is no problem to enable the vmclear operation
3228 * for the loaded_vmcss_on_cpu list is empty!
3230 crash_enable_local_vmclear(cpu
);
3232 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3234 test_bits
= FEATURE_CONTROL_LOCKED
;
3235 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3236 if (tboot_enabled())
3237 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3239 if ((old
& test_bits
) != test_bits
) {
3240 /* enable and lock */
3241 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3243 cr4_set_bits(X86_CR4_VMXE
);
3245 if (vmm_exclusive
) {
3246 kvm_cpu_vmxon(phys_addr
);
3250 native_store_gdt(this_cpu_ptr(&host_gdt
));
3255 static void vmclear_local_loaded_vmcss(void)
3257 int cpu
= raw_smp_processor_id();
3258 struct loaded_vmcs
*v
, *n
;
3260 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3261 loaded_vmcss_on_cpu_link
)
3262 __loaded_vmcs_clear(v
);
3266 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3269 static void kvm_cpu_vmxoff(void)
3271 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3273 intel_pt_handle_vmx(0);
3276 static void hardware_disable(void)
3278 if (vmm_exclusive
) {
3279 vmclear_local_loaded_vmcss();
3282 cr4_clear_bits(X86_CR4_VMXE
);
3285 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3286 u32 msr
, u32
*result
)
3288 u32 vmx_msr_low
, vmx_msr_high
;
3289 u32 ctl
= ctl_min
| ctl_opt
;
3291 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3293 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3294 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3296 /* Ensure minimum (required) set of control bits are supported. */
3304 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3306 u32 vmx_msr_low
, vmx_msr_high
;
3308 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3309 return vmx_msr_high
& ctl
;
3312 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3314 u32 vmx_msr_low
, vmx_msr_high
;
3315 u32 min
, opt
, min2
, opt2
;
3316 u32 _pin_based_exec_control
= 0;
3317 u32 _cpu_based_exec_control
= 0;
3318 u32 _cpu_based_2nd_exec_control
= 0;
3319 u32 _vmexit_control
= 0;
3320 u32 _vmentry_control
= 0;
3322 min
= CPU_BASED_HLT_EXITING
|
3323 #ifdef CONFIG_X86_64
3324 CPU_BASED_CR8_LOAD_EXITING
|
3325 CPU_BASED_CR8_STORE_EXITING
|
3327 CPU_BASED_CR3_LOAD_EXITING
|
3328 CPU_BASED_CR3_STORE_EXITING
|
3329 CPU_BASED_USE_IO_BITMAPS
|
3330 CPU_BASED_MOV_DR_EXITING
|
3331 CPU_BASED_USE_TSC_OFFSETING
|
3332 CPU_BASED_MWAIT_EXITING
|
3333 CPU_BASED_MONITOR_EXITING
|
3334 CPU_BASED_INVLPG_EXITING
|
3335 CPU_BASED_RDPMC_EXITING
;
3337 opt
= CPU_BASED_TPR_SHADOW
|
3338 CPU_BASED_USE_MSR_BITMAPS
|
3339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3340 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3341 &_cpu_based_exec_control
) < 0)
3343 #ifdef CONFIG_X86_64
3344 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3345 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3346 ~CPU_BASED_CR8_STORE_EXITING
;
3348 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3350 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3351 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3352 SECONDARY_EXEC_WBINVD_EXITING
|
3353 SECONDARY_EXEC_ENABLE_VPID
|
3354 SECONDARY_EXEC_ENABLE_EPT
|
3355 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3356 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3357 SECONDARY_EXEC_RDTSCP
|
3358 SECONDARY_EXEC_ENABLE_INVPCID
|
3359 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3360 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3361 SECONDARY_EXEC_SHADOW_VMCS
|
3362 SECONDARY_EXEC_XSAVES
|
3363 SECONDARY_EXEC_ENABLE_PML
|
3364 SECONDARY_EXEC_PCOMMIT
|
3365 SECONDARY_EXEC_TSC_SCALING
;
3366 if (adjust_vmx_controls(min2
, opt2
,
3367 MSR_IA32_VMX_PROCBASED_CTLS2
,
3368 &_cpu_based_2nd_exec_control
) < 0)
3371 #ifndef CONFIG_X86_64
3372 if (!(_cpu_based_2nd_exec_control
&
3373 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3374 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3377 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3378 _cpu_based_2nd_exec_control
&= ~(
3379 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3380 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3381 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3383 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3384 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3386 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3387 CPU_BASED_CR3_STORE_EXITING
|
3388 CPU_BASED_INVLPG_EXITING
);
3389 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3390 vmx_capability
.ept
, vmx_capability
.vpid
);
3393 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3394 #ifdef CONFIG_X86_64
3395 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3397 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3398 VM_EXIT_CLEAR_BNDCFGS
;
3399 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3400 &_vmexit_control
) < 0)
3403 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3404 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3405 PIN_BASED_VMX_PREEMPTION_TIMER
;
3406 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3407 &_pin_based_exec_control
) < 0)
3410 if (!(_cpu_based_2nd_exec_control
&
3411 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3412 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3414 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3415 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3416 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3417 &_vmentry_control
) < 0)
3420 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3422 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3423 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3426 #ifdef CONFIG_X86_64
3427 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3428 if (vmx_msr_high
& (1u<<16))
3432 /* Require Write-Back (WB) memory type for VMCS accesses. */
3433 if (((vmx_msr_high
>> 18) & 15) != 6)
3436 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3437 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3438 vmcs_conf
->revision_id
= vmx_msr_low
;
3440 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3441 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3442 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3443 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3444 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3446 cpu_has_load_ia32_efer
=
3447 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3448 VM_ENTRY_LOAD_IA32_EFER
)
3449 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3450 VM_EXIT_LOAD_IA32_EFER
);
3452 cpu_has_load_perf_global_ctrl
=
3453 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3454 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3455 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3456 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3459 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3460 * but due to errata below it can't be used. Workaround is to use
3461 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3463 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3468 * BC86,AAY89,BD102 (model 44)
3472 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3473 switch (boot_cpu_data
.x86_model
) {
3479 cpu_has_load_perf_global_ctrl
= false;
3480 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3481 "does not work properly. Using workaround\n");
3488 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3489 rdmsrl(MSR_IA32_XSS
, host_xss
);
3494 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3496 int node
= cpu_to_node(cpu
);
3500 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3503 vmcs
= page_address(pages
);
3504 memset(vmcs
, 0, vmcs_config
.size
);
3505 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3509 static struct vmcs
*alloc_vmcs(void)
3511 return alloc_vmcs_cpu(raw_smp_processor_id());
3514 static void free_vmcs(struct vmcs
*vmcs
)
3516 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3520 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3522 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3524 if (!loaded_vmcs
->vmcs
)
3526 loaded_vmcs_clear(loaded_vmcs
);
3527 free_vmcs(loaded_vmcs
->vmcs
);
3528 loaded_vmcs
->vmcs
= NULL
;
3531 static void free_kvm_area(void)
3535 for_each_possible_cpu(cpu
) {
3536 free_vmcs(per_cpu(vmxarea
, cpu
));
3537 per_cpu(vmxarea
, cpu
) = NULL
;
3541 static void init_vmcs_shadow_fields(void)
3545 /* No checks for read only fields yet */
3547 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3548 switch (shadow_read_write_fields
[i
]) {
3550 if (!kvm_mpx_supported())
3558 shadow_read_write_fields
[j
] =
3559 shadow_read_write_fields
[i
];
3562 max_shadow_read_write_fields
= j
;
3564 /* shadowed fields guest access without vmexit */
3565 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3566 clear_bit(shadow_read_write_fields
[i
],
3567 vmx_vmwrite_bitmap
);
3568 clear_bit(shadow_read_write_fields
[i
],
3571 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3572 clear_bit(shadow_read_only_fields
[i
],
3576 static __init
int alloc_kvm_area(void)
3580 for_each_possible_cpu(cpu
) {
3583 vmcs
= alloc_vmcs_cpu(cpu
);
3589 per_cpu(vmxarea
, cpu
) = vmcs
;
3594 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3596 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3599 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3600 struct kvm_segment
*save
)
3602 if (!emulate_invalid_guest_state
) {
3604 * CS and SS RPL should be equal during guest entry according
3605 * to VMX spec, but in reality it is not always so. Since vcpu
3606 * is in the middle of the transition from real mode to
3607 * protected mode it is safe to assume that RPL 0 is a good
3610 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3611 save
->selector
&= ~SEGMENT_RPL_MASK
;
3612 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3615 vmx_set_segment(vcpu
, save
, seg
);
3618 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3620 unsigned long flags
;
3621 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3624 * Update real mode segment cache. It may be not up-to-date if sement
3625 * register was written while vcpu was in a guest mode.
3627 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3628 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3629 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3630 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3631 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3632 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3634 vmx
->rmode
.vm86_active
= 0;
3636 vmx_segment_cache_clear(vmx
);
3638 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3640 flags
= vmcs_readl(GUEST_RFLAGS
);
3641 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3642 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3643 vmcs_writel(GUEST_RFLAGS
, flags
);
3645 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3646 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3648 update_exception_bitmap(vcpu
);
3650 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3651 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3652 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3653 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3654 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3655 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3658 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3660 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3661 struct kvm_segment var
= *save
;
3664 if (seg
== VCPU_SREG_CS
)
3667 if (!emulate_invalid_guest_state
) {
3668 var
.selector
= var
.base
>> 4;
3669 var
.base
= var
.base
& 0xffff0;
3679 if (save
->base
& 0xf)
3680 printk_once(KERN_WARNING
"kvm: segment base is not "
3681 "paragraph aligned when entering "
3682 "protected mode (seg=%d)", seg
);
3685 vmcs_write16(sf
->selector
, var
.selector
);
3686 vmcs_write32(sf
->base
, var
.base
);
3687 vmcs_write32(sf
->limit
, var
.limit
);
3688 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3691 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3693 unsigned long flags
;
3694 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3696 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3697 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3698 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3699 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3700 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3701 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3702 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3704 vmx
->rmode
.vm86_active
= 1;
3707 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3708 * vcpu. Warn the user that an update is overdue.
3710 if (!vcpu
->kvm
->arch
.tss_addr
)
3711 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3712 "called before entering vcpu\n");
3714 vmx_segment_cache_clear(vmx
);
3716 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3717 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3718 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3720 flags
= vmcs_readl(GUEST_RFLAGS
);
3721 vmx
->rmode
.save_rflags
= flags
;
3723 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3725 vmcs_writel(GUEST_RFLAGS
, flags
);
3726 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3727 update_exception_bitmap(vcpu
);
3729 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3730 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3731 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3732 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3733 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3734 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3736 kvm_mmu_reset_context(vcpu
);
3739 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3741 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3742 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3748 * Force kernel_gs_base reloading before EFER changes, as control
3749 * of this msr depends on is_long_mode().
3751 vmx_load_host_state(to_vmx(vcpu
));
3752 vcpu
->arch
.efer
= efer
;
3753 if (efer
& EFER_LMA
) {
3754 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3757 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3759 msr
->data
= efer
& ~EFER_LME
;
3764 #ifdef CONFIG_X86_64
3766 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3770 vmx_segment_cache_clear(to_vmx(vcpu
));
3772 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3773 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3774 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3776 vmcs_write32(GUEST_TR_AR_BYTES
,
3777 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3778 | VMX_AR_TYPE_BUSY_64_TSS
);
3780 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3783 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3785 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3786 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3791 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3793 vpid_sync_context(vpid
);
3795 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3797 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3801 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3803 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3806 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3808 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3810 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3811 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3814 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3816 if (enable_ept
&& is_paging(vcpu
))
3817 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3818 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3821 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3823 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3825 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3826 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3829 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3831 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3833 if (!test_bit(VCPU_EXREG_PDPTR
,
3834 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3837 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3838 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3839 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3840 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3841 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3845 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3847 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3849 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3850 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3851 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3852 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3853 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3856 __set_bit(VCPU_EXREG_PDPTR
,
3857 (unsigned long *)&vcpu
->arch
.regs_avail
);
3858 __set_bit(VCPU_EXREG_PDPTR
,
3859 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3862 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3864 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3866 struct kvm_vcpu
*vcpu
)
3868 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3869 vmx_decache_cr3(vcpu
);
3870 if (!(cr0
& X86_CR0_PG
)) {
3871 /* From paging/starting to nonpaging */
3872 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3873 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3874 (CPU_BASED_CR3_LOAD_EXITING
|
3875 CPU_BASED_CR3_STORE_EXITING
));
3876 vcpu
->arch
.cr0
= cr0
;
3877 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3878 } else if (!is_paging(vcpu
)) {
3879 /* From nonpaging to paging */
3880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3881 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3882 ~(CPU_BASED_CR3_LOAD_EXITING
|
3883 CPU_BASED_CR3_STORE_EXITING
));
3884 vcpu
->arch
.cr0
= cr0
;
3885 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3888 if (!(cr0
& X86_CR0_WP
))
3889 *hw_cr0
&= ~X86_CR0_WP
;
3892 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3894 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3895 unsigned long hw_cr0
;
3897 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3898 if (enable_unrestricted_guest
)
3899 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3901 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3903 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3906 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3910 #ifdef CONFIG_X86_64
3911 if (vcpu
->arch
.efer
& EFER_LME
) {
3912 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3914 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3920 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3922 if (!vcpu
->fpu_active
)
3923 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3925 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3926 vmcs_writel(GUEST_CR0
, hw_cr0
);
3927 vcpu
->arch
.cr0
= cr0
;
3929 /* depends on vcpu->arch.cr0 to be set to a new value */
3930 vmx
->emulation_required
= emulation_required(vcpu
);
3933 static u64
construct_eptp(unsigned long root_hpa
)
3937 /* TODO write the value reading from MSR */
3938 eptp
= VMX_EPT_DEFAULT_MT
|
3939 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3940 if (enable_ept_ad_bits
)
3941 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3942 eptp
|= (root_hpa
& PAGE_MASK
);
3947 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3949 unsigned long guest_cr3
;
3954 eptp
= construct_eptp(cr3
);
3955 vmcs_write64(EPT_POINTER
, eptp
);
3956 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3957 guest_cr3
= kvm_read_cr3(vcpu
);
3959 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3960 ept_load_pdptrs(vcpu
);
3963 vmx_flush_tlb(vcpu
);
3964 vmcs_writel(GUEST_CR3
, guest_cr3
);
3967 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3970 * Pass through host's Machine Check Enable value to hw_cr4, which
3971 * is in force while we are in guest mode. Do not let guests control
3972 * this bit, even if host CR4.MCE == 0.
3974 unsigned long hw_cr4
=
3975 (cr4_read_shadow() & X86_CR4_MCE
) |
3976 (cr4
& ~X86_CR4_MCE
) |
3977 (to_vmx(vcpu
)->rmode
.vm86_active
?
3978 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3980 if (cr4
& X86_CR4_VMXE
) {
3982 * To use VMXON (and later other VMX instructions), a guest
3983 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3984 * So basically the check on whether to allow nested VMX
3987 if (!nested_vmx_allowed(vcpu
))
3990 if (to_vmx(vcpu
)->nested
.vmxon
&&
3991 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3994 vcpu
->arch
.cr4
= cr4
;
3996 if (!is_paging(vcpu
)) {
3997 hw_cr4
&= ~X86_CR4_PAE
;
3998 hw_cr4
|= X86_CR4_PSE
;
3999 } else if (!(cr4
& X86_CR4_PAE
)) {
4000 hw_cr4
&= ~X86_CR4_PAE
;
4004 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4006 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4007 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4008 * to be manually disabled when guest switches to non-paging
4011 * If !enable_unrestricted_guest, the CPU is always running
4012 * with CR0.PG=1 and CR4 needs to be modified.
4013 * If enable_unrestricted_guest, the CPU automatically
4014 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4016 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4018 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4019 vmcs_writel(GUEST_CR4
, hw_cr4
);
4023 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4024 struct kvm_segment
*var
, int seg
)
4026 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4029 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4030 *var
= vmx
->rmode
.segs
[seg
];
4031 if (seg
== VCPU_SREG_TR
4032 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4034 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4035 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4038 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4039 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4040 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4041 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4042 var
->unusable
= (ar
>> 16) & 1;
4043 var
->type
= ar
& 15;
4044 var
->s
= (ar
>> 4) & 1;
4045 var
->dpl
= (ar
>> 5) & 3;
4047 * Some userspaces do not preserve unusable property. Since usable
4048 * segment has to be present according to VMX spec we can use present
4049 * property to amend userspace bug by making unusable segment always
4050 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4051 * segment as unusable.
4053 var
->present
= !var
->unusable
;
4054 var
->avl
= (ar
>> 12) & 1;
4055 var
->l
= (ar
>> 13) & 1;
4056 var
->db
= (ar
>> 14) & 1;
4057 var
->g
= (ar
>> 15) & 1;
4060 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4062 struct kvm_segment s
;
4064 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4065 vmx_get_segment(vcpu
, &s
, seg
);
4068 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4071 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4073 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4075 if (unlikely(vmx
->rmode
.vm86_active
))
4078 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4079 return VMX_AR_DPL(ar
);
4083 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4087 if (var
->unusable
|| !var
->present
)
4090 ar
= var
->type
& 15;
4091 ar
|= (var
->s
& 1) << 4;
4092 ar
|= (var
->dpl
& 3) << 5;
4093 ar
|= (var
->present
& 1) << 7;
4094 ar
|= (var
->avl
& 1) << 12;
4095 ar
|= (var
->l
& 1) << 13;
4096 ar
|= (var
->db
& 1) << 14;
4097 ar
|= (var
->g
& 1) << 15;
4103 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4104 struct kvm_segment
*var
, int seg
)
4106 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4107 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4109 vmx_segment_cache_clear(vmx
);
4111 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4112 vmx
->rmode
.segs
[seg
] = *var
;
4113 if (seg
== VCPU_SREG_TR
)
4114 vmcs_write16(sf
->selector
, var
->selector
);
4116 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4120 vmcs_writel(sf
->base
, var
->base
);
4121 vmcs_write32(sf
->limit
, var
->limit
);
4122 vmcs_write16(sf
->selector
, var
->selector
);
4125 * Fix the "Accessed" bit in AR field of segment registers for older
4127 * IA32 arch specifies that at the time of processor reset the
4128 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4129 * is setting it to 0 in the userland code. This causes invalid guest
4130 * state vmexit when "unrestricted guest" mode is turned on.
4131 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4132 * tree. Newer qemu binaries with that qemu fix would not need this
4135 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4136 var
->type
|= 0x1; /* Accessed */
4138 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4141 vmx
->emulation_required
= emulation_required(vcpu
);
4144 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4146 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4148 *db
= (ar
>> 14) & 1;
4149 *l
= (ar
>> 13) & 1;
4152 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4154 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4155 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4158 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4160 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4161 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4164 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4166 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4167 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4170 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4172 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4173 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4176 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4178 struct kvm_segment var
;
4181 vmx_get_segment(vcpu
, &var
, seg
);
4183 if (seg
== VCPU_SREG_CS
)
4185 ar
= vmx_segment_access_rights(&var
);
4187 if (var
.base
!= (var
.selector
<< 4))
4189 if (var
.limit
!= 0xffff)
4197 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4199 struct kvm_segment cs
;
4200 unsigned int cs_rpl
;
4202 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4203 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4207 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4211 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4212 if (cs
.dpl
> cs_rpl
)
4215 if (cs
.dpl
!= cs_rpl
)
4221 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4225 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4227 struct kvm_segment ss
;
4228 unsigned int ss_rpl
;
4230 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4231 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4235 if (ss
.type
!= 3 && ss
.type
!= 7)
4239 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4247 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4249 struct kvm_segment var
;
4252 vmx_get_segment(vcpu
, &var
, seg
);
4253 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4261 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4262 if (var
.dpl
< rpl
) /* DPL < RPL */
4266 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4272 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4274 struct kvm_segment tr
;
4276 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4280 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4282 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4290 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4292 struct kvm_segment ldtr
;
4294 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4298 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4308 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4310 struct kvm_segment cs
, ss
;
4312 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4313 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4315 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4316 (ss
.selector
& SEGMENT_RPL_MASK
));
4320 * Check if guest state is valid. Returns true if valid, false if
4322 * We assume that registers are always usable
4324 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4326 if (enable_unrestricted_guest
)
4329 /* real mode guest state checks */
4330 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4331 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4333 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4335 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4337 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4339 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4341 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4344 /* protected mode guest state checks */
4345 if (!cs_ss_rpl_check(vcpu
))
4347 if (!code_segment_valid(vcpu
))
4349 if (!stack_segment_valid(vcpu
))
4351 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4353 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4355 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4357 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4359 if (!tr_valid(vcpu
))
4361 if (!ldtr_valid(vcpu
))
4365 * - Add checks on RIP
4366 * - Add checks on RFLAGS
4372 static int init_rmode_tss(struct kvm
*kvm
)
4378 idx
= srcu_read_lock(&kvm
->srcu
);
4379 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4380 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4383 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4384 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4385 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4388 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4391 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4395 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4396 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4399 srcu_read_unlock(&kvm
->srcu
, idx
);
4403 static int init_rmode_identity_map(struct kvm
*kvm
)
4406 kvm_pfn_t identity_map_pfn
;
4412 /* Protect kvm->arch.ept_identity_pagetable_done. */
4413 mutex_lock(&kvm
->slots_lock
);
4415 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4418 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4420 r
= alloc_identity_pagetable(kvm
);
4424 idx
= srcu_read_lock(&kvm
->srcu
);
4425 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4428 /* Set up identity-mapping pagetable for EPT in real mode */
4429 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4430 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4431 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4432 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4433 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4437 kvm
->arch
.ept_identity_pagetable_done
= true;
4440 srcu_read_unlock(&kvm
->srcu
, idx
);
4443 mutex_unlock(&kvm
->slots_lock
);
4447 static void seg_setup(int seg
)
4449 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4452 vmcs_write16(sf
->selector
, 0);
4453 vmcs_writel(sf
->base
, 0);
4454 vmcs_write32(sf
->limit
, 0xffff);
4456 if (seg
== VCPU_SREG_CS
)
4457 ar
|= 0x08; /* code segment */
4459 vmcs_write32(sf
->ar_bytes
, ar
);
4462 static int alloc_apic_access_page(struct kvm
*kvm
)
4467 mutex_lock(&kvm
->slots_lock
);
4468 if (kvm
->arch
.apic_access_page_done
)
4470 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4471 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4475 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4476 if (is_error_page(page
)) {
4482 * Do not pin the page in memory, so that memory hot-unplug
4483 * is able to migrate it.
4486 kvm
->arch
.apic_access_page_done
= true;
4488 mutex_unlock(&kvm
->slots_lock
);
4492 static int alloc_identity_pagetable(struct kvm
*kvm
)
4494 /* Called with kvm->slots_lock held. */
4498 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4500 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4501 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4506 static int allocate_vpid(void)
4512 spin_lock(&vmx_vpid_lock
);
4513 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4514 if (vpid
< VMX_NR_VPIDS
)
4515 __set_bit(vpid
, vmx_vpid_bitmap
);
4518 spin_unlock(&vmx_vpid_lock
);
4522 static void free_vpid(int vpid
)
4524 if (!enable_vpid
|| vpid
== 0)
4526 spin_lock(&vmx_vpid_lock
);
4527 __clear_bit(vpid
, vmx_vpid_bitmap
);
4528 spin_unlock(&vmx_vpid_lock
);
4531 #define MSR_TYPE_R 1
4532 #define MSR_TYPE_W 2
4533 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4536 int f
= sizeof(unsigned long);
4538 if (!cpu_has_vmx_msr_bitmap())
4542 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4543 * have the write-low and read-high bitmap offsets the wrong way round.
4544 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4546 if (msr
<= 0x1fff) {
4547 if (type
& MSR_TYPE_R
)
4549 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4551 if (type
& MSR_TYPE_W
)
4553 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4555 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4557 if (type
& MSR_TYPE_R
)
4559 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4561 if (type
& MSR_TYPE_W
)
4563 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4568 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4571 int f
= sizeof(unsigned long);
4573 if (!cpu_has_vmx_msr_bitmap())
4577 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4578 * have the write-low and read-high bitmap offsets the wrong way round.
4579 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4581 if (msr
<= 0x1fff) {
4582 if (type
& MSR_TYPE_R
)
4584 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4586 if (type
& MSR_TYPE_W
)
4588 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4590 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4592 if (type
& MSR_TYPE_R
)
4594 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4596 if (type
& MSR_TYPE_W
)
4598 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4604 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4605 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4607 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4608 unsigned long *msr_bitmap_nested
,
4611 int f
= sizeof(unsigned long);
4613 if (!cpu_has_vmx_msr_bitmap()) {
4619 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4620 * have the write-low and read-high bitmap offsets the wrong way round.
4621 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4623 if (msr
<= 0x1fff) {
4624 if (type
& MSR_TYPE_R
&&
4625 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4627 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4629 if (type
& MSR_TYPE_W
&&
4630 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4632 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4634 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4636 if (type
& MSR_TYPE_R
&&
4637 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4639 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4641 if (type
& MSR_TYPE_W
&&
4642 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4644 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4649 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4652 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4653 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4654 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4655 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4658 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4660 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4662 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4666 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4668 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4670 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4674 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4676 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4678 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4682 static bool vmx_get_enable_apicv(void)
4684 return enable_apicv
;
4687 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4689 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4694 if (vmx
->nested
.pi_desc
&&
4695 vmx
->nested
.pi_pending
) {
4696 vmx
->nested
.pi_pending
= false;
4697 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4700 max_irr
= find_last_bit(
4701 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4706 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4711 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4712 kunmap(vmx
->nested
.virtual_apic_page
);
4714 status
= vmcs_read16(GUEST_INTR_STATUS
);
4715 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4717 status
|= (u8
)max_irr
;
4718 vmcs_write16(GUEST_INTR_STATUS
, status
);
4724 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4727 if (vcpu
->mode
== IN_GUEST_MODE
) {
4728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4731 * Currently, we don't support urgent interrupt,
4732 * all interrupts are recognized as non-urgent
4733 * interrupt, so we cannot post interrupts when
4736 * If the vcpu is in guest mode, it means it is
4737 * running instead of being scheduled out and
4738 * waiting in the run queue, and that's the only
4739 * case when 'SN' is set currently, warning if
4742 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4744 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4745 POSTED_INTR_VECTOR
);
4752 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4755 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4757 if (is_guest_mode(vcpu
) &&
4758 vector
== vmx
->nested
.posted_intr_nv
) {
4759 /* the PIR and ON have been set by L1. */
4760 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4762 * If a posted intr is not recognized by hardware,
4763 * we will accomplish it in the next vmentry.
4765 vmx
->nested
.pi_pending
= true;
4766 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4772 * Send interrupt to vcpu via posted interrupt way.
4773 * 1. If target vcpu is running(non-root mode), send posted interrupt
4774 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4775 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4776 * interrupt from PIR in next vmentry.
4778 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4780 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4783 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4787 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4790 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4791 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4792 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4793 kvm_vcpu_kick(vcpu
);
4796 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4798 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4800 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4803 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4807 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4808 * will not change in the lifetime of the guest.
4809 * Note that host-state that does change is set elsewhere. E.g., host-state
4810 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4812 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4819 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4820 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4822 /* Save the most likely value for this task's CR4 in the VMCS. */
4823 cr4
= cr4_read_shadow();
4824 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4825 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4827 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4828 #ifdef CONFIG_X86_64
4830 * Load null selectors, so we can avoid reloading them in
4831 * __vmx_load_host_state(), in case userspace uses the null selectors
4832 * too (the expected case).
4834 vmcs_write16(HOST_DS_SELECTOR
, 0);
4835 vmcs_write16(HOST_ES_SELECTOR
, 0);
4837 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4838 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4840 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4841 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4843 native_store_idt(&dt
);
4844 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4845 vmx
->host_idt_base
= dt
.address
;
4847 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4849 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4850 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4851 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4852 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4854 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4855 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4856 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4860 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4862 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4864 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4865 if (is_guest_mode(&vmx
->vcpu
))
4866 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4867 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4868 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4871 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4873 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4875 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4876 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4877 /* Enable the preemption timer dynamically */
4878 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4879 return pin_based_exec_ctrl
;
4882 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4884 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4886 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4887 if (cpu_has_secondary_exec_ctrls()) {
4888 if (kvm_vcpu_apicv_active(vcpu
))
4889 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4890 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4891 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4893 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4894 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4895 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4898 if (cpu_has_vmx_msr_bitmap())
4899 vmx_set_msr_bitmap(vcpu
);
4902 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4904 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4906 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4907 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4909 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4910 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4911 #ifdef CONFIG_X86_64
4912 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4913 CPU_BASED_CR8_LOAD_EXITING
;
4917 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4918 CPU_BASED_CR3_LOAD_EXITING
|
4919 CPU_BASED_INVLPG_EXITING
;
4920 return exec_control
;
4923 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4925 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4926 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4927 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4929 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4931 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4932 enable_unrestricted_guest
= 0;
4933 /* Enable INVPCID for non-ept guests may cause performance regression. */
4934 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4936 if (!enable_unrestricted_guest
)
4937 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4939 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4940 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4941 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4942 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4943 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4944 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4946 We can NOT enable shadow_vmcs here because we don't have yet
4949 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4952 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4954 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4955 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4957 return exec_control
;
4960 static void ept_set_mmio_spte_mask(void)
4963 * EPT Misconfigurations can be generated if the value of bits 2:0
4964 * of an EPT paging-structure entry is 110b (write/execute).
4965 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4968 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4971 #define VMX_XSS_EXIT_BITMAP 0
4973 * Sets up the vmcs for emulated real mode.
4975 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4977 #ifdef CONFIG_X86_64
4983 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4984 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4986 if (enable_shadow_vmcs
) {
4987 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4988 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4990 if (cpu_has_vmx_msr_bitmap())
4991 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4993 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4996 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4997 vmx
->hv_deadline_tsc
= -1;
4999 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5001 if (cpu_has_secondary_exec_ctrls())
5002 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5003 vmx_secondary_exec_control(vmx
));
5005 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5006 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5007 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5008 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5009 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5011 vmcs_write16(GUEST_INTR_STATUS
, 0);
5013 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5014 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5018 vmcs_write32(PLE_GAP
, ple_gap
);
5019 vmx
->ple_window
= ple_window
;
5020 vmx
->ple_window_dirty
= true;
5023 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5024 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5025 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5027 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5028 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5029 vmx_set_constant_host_state(vmx
);
5030 #ifdef CONFIG_X86_64
5031 rdmsrl(MSR_FS_BASE
, a
);
5032 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5033 rdmsrl(MSR_GS_BASE
, a
);
5034 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5036 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5037 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5040 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5041 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5042 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5043 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5044 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5046 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5047 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5049 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5050 u32 index
= vmx_msr_index
[i
];
5051 u32 data_low
, data_high
;
5054 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5056 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5058 vmx
->guest_msrs
[j
].index
= i
;
5059 vmx
->guest_msrs
[j
].data
= 0;
5060 vmx
->guest_msrs
[j
].mask
= -1ull;
5065 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5067 /* 22.2.1, 20.8.1 */
5068 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5070 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
5071 set_cr4_guest_host_mask(vmx
);
5073 if (vmx_xsaves_supported())
5074 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5079 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5081 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5082 struct msr_data apic_base_msr
;
5085 vmx
->rmode
.vm86_active
= 0;
5087 vmx
->soft_vnmi_blocked
= 0;
5089 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5090 kvm_set_cr8(vcpu
, 0);
5093 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5094 MSR_IA32_APICBASE_ENABLE
;
5095 if (kvm_vcpu_is_reset_bsp(vcpu
))
5096 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5097 apic_base_msr
.host_initiated
= true;
5098 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5101 vmx_segment_cache_clear(vmx
);
5103 seg_setup(VCPU_SREG_CS
);
5104 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5105 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5107 seg_setup(VCPU_SREG_DS
);
5108 seg_setup(VCPU_SREG_ES
);
5109 seg_setup(VCPU_SREG_FS
);
5110 seg_setup(VCPU_SREG_GS
);
5111 seg_setup(VCPU_SREG_SS
);
5113 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5114 vmcs_writel(GUEST_TR_BASE
, 0);
5115 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5116 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5118 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5119 vmcs_writel(GUEST_LDTR_BASE
, 0);
5120 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5121 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5124 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5125 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5126 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5127 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5130 vmcs_writel(GUEST_RFLAGS
, 0x02);
5131 kvm_rip_write(vcpu
, 0xfff0);
5133 vmcs_writel(GUEST_GDTR_BASE
, 0);
5134 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5136 vmcs_writel(GUEST_IDTR_BASE
, 0);
5137 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5139 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5140 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5141 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5145 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5147 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5148 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5149 if (cpu_need_tpr_shadow(vcpu
))
5150 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5151 __pa(vcpu
->arch
.apic
->regs
));
5152 vmcs_write32(TPR_THRESHOLD
, 0);
5155 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5157 if (kvm_vcpu_apicv_active(vcpu
))
5158 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5161 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5163 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5164 vmx
->vcpu
.arch
.cr0
= cr0
;
5165 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5166 vmx_set_cr4(vcpu
, 0);
5167 vmx_set_efer(vcpu
, 0);
5168 vmx_fpu_activate(vcpu
);
5169 update_exception_bitmap(vcpu
);
5171 vpid_sync_context(vmx
->vpid
);
5175 * In nested virtualization, check if L1 asked to exit on external interrupts.
5176 * For most existing hypervisors, this will always return true.
5178 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5180 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5181 PIN_BASED_EXT_INTR_MASK
;
5185 * In nested virtualization, check if L1 has set
5186 * VM_EXIT_ACK_INTR_ON_EXIT
5188 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5190 return get_vmcs12(vcpu
)->vm_exit_controls
&
5191 VM_EXIT_ACK_INTR_ON_EXIT
;
5194 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5196 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5197 PIN_BASED_NMI_EXITING
;
5200 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5202 u32 cpu_based_vm_exec_control
;
5204 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5205 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5206 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5209 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5211 u32 cpu_based_vm_exec_control
;
5213 if (!cpu_has_virtual_nmis() ||
5214 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5215 enable_irq_window(vcpu
);
5219 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5220 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5221 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5224 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5226 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5228 int irq
= vcpu
->arch
.interrupt
.nr
;
5230 trace_kvm_inj_virq(irq
);
5232 ++vcpu
->stat
.irq_injections
;
5233 if (vmx
->rmode
.vm86_active
) {
5235 if (vcpu
->arch
.interrupt
.soft
)
5236 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5237 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5238 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5241 intr
= irq
| INTR_INFO_VALID_MASK
;
5242 if (vcpu
->arch
.interrupt
.soft
) {
5243 intr
|= INTR_TYPE_SOFT_INTR
;
5244 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5245 vmx
->vcpu
.arch
.event_exit_inst_len
);
5247 intr
|= INTR_TYPE_EXT_INTR
;
5248 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5251 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5253 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5255 if (is_guest_mode(vcpu
))
5258 if (!cpu_has_virtual_nmis()) {
5260 * Tracking the NMI-blocked state in software is built upon
5261 * finding the next open IRQ window. This, in turn, depends on
5262 * well-behaving guests: They have to keep IRQs disabled at
5263 * least as long as the NMI handler runs. Otherwise we may
5264 * cause NMI nesting, maybe breaking the guest. But as this is
5265 * highly unlikely, we can live with the residual risk.
5267 vmx
->soft_vnmi_blocked
= 1;
5268 vmx
->vnmi_blocked_time
= 0;
5271 ++vcpu
->stat
.nmi_injections
;
5272 vmx
->nmi_known_unmasked
= false;
5273 if (vmx
->rmode
.vm86_active
) {
5274 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5275 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5278 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5279 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5282 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5284 if (!cpu_has_virtual_nmis())
5285 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5286 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5288 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5291 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5293 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5295 if (!cpu_has_virtual_nmis()) {
5296 if (vmx
->soft_vnmi_blocked
!= masked
) {
5297 vmx
->soft_vnmi_blocked
= masked
;
5298 vmx
->vnmi_blocked_time
= 0;
5301 vmx
->nmi_known_unmasked
= !masked
;
5303 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5304 GUEST_INTR_STATE_NMI
);
5306 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5307 GUEST_INTR_STATE_NMI
);
5311 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5313 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5316 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5319 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5320 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5321 | GUEST_INTR_STATE_NMI
));
5324 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5326 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5327 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5328 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5329 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5332 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5336 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5340 kvm
->arch
.tss_addr
= addr
;
5341 return init_rmode_tss(kvm
);
5344 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5349 * Update instruction length as we may reinject the exception
5350 * from user space while in guest debugging mode.
5352 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5353 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5354 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5358 if (vcpu
->guest_debug
&
5359 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5376 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5377 int vec
, u32 err_code
)
5380 * Instruction with address size override prefix opcode 0x67
5381 * Cause the #SS fault with 0 error code in VM86 mode.
5383 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5384 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5385 if (vcpu
->arch
.halt_request
) {
5386 vcpu
->arch
.halt_request
= 0;
5387 return kvm_vcpu_halt(vcpu
);
5395 * Forward all other exceptions that are valid in real mode.
5396 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5397 * the required debugging infrastructure rework.
5399 kvm_queue_exception(vcpu
, vec
);
5404 * Trigger machine check on the host. We assume all the MSRs are already set up
5405 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5406 * We pass a fake environment to the machine check handler because we want
5407 * the guest to be always treated like user space, no matter what context
5408 * it used internally.
5410 static void kvm_machine_check(void)
5412 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5413 struct pt_regs regs
= {
5414 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5415 .flags
= X86_EFLAGS_IF
,
5418 do_machine_check(®s
, 0);
5422 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5424 /* already handled by vcpu_run */
5428 static int handle_exception(struct kvm_vcpu
*vcpu
)
5430 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5431 struct kvm_run
*kvm_run
= vcpu
->run
;
5432 u32 intr_info
, ex_no
, error_code
;
5433 unsigned long cr2
, rip
, dr6
;
5435 enum emulation_result er
;
5437 vect_info
= vmx
->idt_vectoring_info
;
5438 intr_info
= vmx
->exit_intr_info
;
5440 if (is_machine_check(intr_info
))
5441 return handle_machine_check(vcpu
);
5443 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5444 return 1; /* already handled by vmx_vcpu_run() */
5446 if (is_no_device(intr_info
)) {
5447 vmx_fpu_activate(vcpu
);
5451 if (is_invalid_opcode(intr_info
)) {
5452 if (is_guest_mode(vcpu
)) {
5453 kvm_queue_exception(vcpu
, UD_VECTOR
);
5456 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5457 if (er
!= EMULATE_DONE
)
5458 kvm_queue_exception(vcpu
, UD_VECTOR
);
5463 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5464 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5467 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5468 * MMIO, it is better to report an internal error.
5469 * See the comments in vmx_handle_exit.
5471 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5472 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5473 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5474 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5475 vcpu
->run
->internal
.ndata
= 3;
5476 vcpu
->run
->internal
.data
[0] = vect_info
;
5477 vcpu
->run
->internal
.data
[1] = intr_info
;
5478 vcpu
->run
->internal
.data
[2] = error_code
;
5482 if (is_page_fault(intr_info
)) {
5483 /* EPT won't cause page fault directly */
5485 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5486 trace_kvm_page_fault(cr2
, error_code
);
5488 if (kvm_event_needs_reinjection(vcpu
))
5489 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5490 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5493 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5495 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5496 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5500 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5503 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5504 if (!(vcpu
->guest_debug
&
5505 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5506 vcpu
->arch
.dr6
&= ~15;
5507 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5508 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5509 skip_emulated_instruction(vcpu
);
5511 kvm_queue_exception(vcpu
, DB_VECTOR
);
5514 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5515 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5519 * Update instruction length as we may reinject #BP from
5520 * user space while in guest debugging mode. Reading it for
5521 * #DB as well causes no harm, it is not used in that case.
5523 vmx
->vcpu
.arch
.event_exit_inst_len
=
5524 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5525 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5526 rip
= kvm_rip_read(vcpu
);
5527 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5528 kvm_run
->debug
.arch
.exception
= ex_no
;
5531 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5532 kvm_run
->ex
.exception
= ex_no
;
5533 kvm_run
->ex
.error_code
= error_code
;
5539 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5541 ++vcpu
->stat
.irq_exits
;
5545 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5547 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5551 static int handle_io(struct kvm_vcpu
*vcpu
)
5553 unsigned long exit_qualification
;
5554 int size
, in
, string
;
5557 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5558 string
= (exit_qualification
& 16) != 0;
5559 in
= (exit_qualification
& 8) != 0;
5561 ++vcpu
->stat
.io_exits
;
5564 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5566 port
= exit_qualification
>> 16;
5567 size
= (exit_qualification
& 7) + 1;
5568 skip_emulated_instruction(vcpu
);
5570 return kvm_fast_pio_out(vcpu
, size
, port
);
5574 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5577 * Patch in the VMCALL instruction:
5579 hypercall
[0] = 0x0f;
5580 hypercall
[1] = 0x01;
5581 hypercall
[2] = 0xc1;
5584 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5586 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5587 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5589 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5590 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5591 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5592 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5593 return (val
& always_on
) == always_on
;
5596 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5597 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5599 if (is_guest_mode(vcpu
)) {
5600 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5601 unsigned long orig_val
= val
;
5604 * We get here when L2 changed cr0 in a way that did not change
5605 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5606 * but did change L0 shadowed bits. So we first calculate the
5607 * effective cr0 value that L1 would like to write into the
5608 * hardware. It consists of the L2-owned bits from the new
5609 * value combined with the L1-owned bits from L1's guest_cr0.
5611 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5612 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5614 if (!nested_cr0_valid(vcpu
, val
))
5617 if (kvm_set_cr0(vcpu
, val
))
5619 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5622 if (to_vmx(vcpu
)->nested
.vmxon
&&
5623 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5625 return kvm_set_cr0(vcpu
, val
);
5629 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5631 if (is_guest_mode(vcpu
)) {
5632 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5633 unsigned long orig_val
= val
;
5635 /* analogously to handle_set_cr0 */
5636 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5637 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5638 if (kvm_set_cr4(vcpu
, val
))
5640 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5643 return kvm_set_cr4(vcpu
, val
);
5646 /* called to set cr0 as appropriate for clts instruction exit. */
5647 static void handle_clts(struct kvm_vcpu
*vcpu
)
5649 if (is_guest_mode(vcpu
)) {
5651 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5652 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5653 * just pretend it's off (also in arch.cr0 for fpu_activate).
5655 vmcs_writel(CR0_READ_SHADOW
,
5656 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5657 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5659 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5662 static int handle_cr(struct kvm_vcpu
*vcpu
)
5664 unsigned long exit_qualification
, val
;
5669 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5670 cr
= exit_qualification
& 15;
5671 reg
= (exit_qualification
>> 8) & 15;
5672 switch ((exit_qualification
>> 4) & 3) {
5673 case 0: /* mov to cr */
5674 val
= kvm_register_readl(vcpu
, reg
);
5675 trace_kvm_cr_write(cr
, val
);
5678 err
= handle_set_cr0(vcpu
, val
);
5679 kvm_complete_insn_gp(vcpu
, err
);
5682 err
= kvm_set_cr3(vcpu
, val
);
5683 kvm_complete_insn_gp(vcpu
, err
);
5686 err
= handle_set_cr4(vcpu
, val
);
5687 kvm_complete_insn_gp(vcpu
, err
);
5690 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5692 err
= kvm_set_cr8(vcpu
, cr8
);
5693 kvm_complete_insn_gp(vcpu
, err
);
5694 if (lapic_in_kernel(vcpu
))
5696 if (cr8_prev
<= cr8
)
5698 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5705 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5706 skip_emulated_instruction(vcpu
);
5707 vmx_fpu_activate(vcpu
);
5709 case 1: /*mov from cr*/
5712 val
= kvm_read_cr3(vcpu
);
5713 kvm_register_write(vcpu
, reg
, val
);
5714 trace_kvm_cr_read(cr
, val
);
5715 skip_emulated_instruction(vcpu
);
5718 val
= kvm_get_cr8(vcpu
);
5719 kvm_register_write(vcpu
, reg
, val
);
5720 trace_kvm_cr_read(cr
, val
);
5721 skip_emulated_instruction(vcpu
);
5726 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5727 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5728 kvm_lmsw(vcpu
, val
);
5730 skip_emulated_instruction(vcpu
);
5735 vcpu
->run
->exit_reason
= 0;
5736 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5737 (int)(exit_qualification
>> 4) & 3, cr
);
5741 static int handle_dr(struct kvm_vcpu
*vcpu
)
5743 unsigned long exit_qualification
;
5746 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5747 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5749 /* First, if DR does not exist, trigger UD */
5750 if (!kvm_require_dr(vcpu
, dr
))
5753 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5754 if (!kvm_require_cpl(vcpu
, 0))
5756 dr7
= vmcs_readl(GUEST_DR7
);
5759 * As the vm-exit takes precedence over the debug trap, we
5760 * need to emulate the latter, either for the host or the
5761 * guest debugging itself.
5763 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5764 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5765 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5766 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5767 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5768 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5771 vcpu
->arch
.dr6
&= ~15;
5772 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5773 kvm_queue_exception(vcpu
, DB_VECTOR
);
5778 if (vcpu
->guest_debug
== 0) {
5779 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5780 CPU_BASED_MOV_DR_EXITING
);
5783 * No more DR vmexits; force a reload of the debug registers
5784 * and reenter on this instruction. The next vmexit will
5785 * retrieve the full state of the debug registers.
5787 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5791 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5792 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5795 if (kvm_get_dr(vcpu
, dr
, &val
))
5797 kvm_register_write(vcpu
, reg
, val
);
5799 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5802 skip_emulated_instruction(vcpu
);
5806 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5808 return vcpu
->arch
.dr6
;
5811 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5815 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5817 get_debugreg(vcpu
->arch
.db
[0], 0);
5818 get_debugreg(vcpu
->arch
.db
[1], 1);
5819 get_debugreg(vcpu
->arch
.db
[2], 2);
5820 get_debugreg(vcpu
->arch
.db
[3], 3);
5821 get_debugreg(vcpu
->arch
.dr6
, 6);
5822 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5824 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5825 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5828 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5830 vmcs_writel(GUEST_DR7
, val
);
5833 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5835 kvm_emulate_cpuid(vcpu
);
5839 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5841 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5842 struct msr_data msr_info
;
5844 msr_info
.index
= ecx
;
5845 msr_info
.host_initiated
= false;
5846 if (vmx_get_msr(vcpu
, &msr_info
)) {
5847 trace_kvm_msr_read_ex(ecx
);
5848 kvm_inject_gp(vcpu
, 0);
5852 trace_kvm_msr_read(ecx
, msr_info
.data
);
5854 /* FIXME: handling of bits 32:63 of rax, rdx */
5855 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5856 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5857 skip_emulated_instruction(vcpu
);
5861 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5863 struct msr_data msr
;
5864 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5865 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5866 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5870 msr
.host_initiated
= false;
5871 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5872 trace_kvm_msr_write_ex(ecx
, data
);
5873 kvm_inject_gp(vcpu
, 0);
5877 trace_kvm_msr_write(ecx
, data
);
5878 skip_emulated_instruction(vcpu
);
5882 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5884 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5888 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5890 u32 cpu_based_vm_exec_control
;
5892 /* clear pending irq */
5893 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5894 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5895 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5897 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5899 ++vcpu
->stat
.irq_window_exits
;
5903 static int handle_halt(struct kvm_vcpu
*vcpu
)
5905 return kvm_emulate_halt(vcpu
);
5908 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5910 return kvm_emulate_hypercall(vcpu
);
5913 static int handle_invd(struct kvm_vcpu
*vcpu
)
5915 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5918 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5920 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5922 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5923 skip_emulated_instruction(vcpu
);
5927 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5931 err
= kvm_rdpmc(vcpu
);
5932 kvm_complete_insn_gp(vcpu
, err
);
5937 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5939 kvm_emulate_wbinvd(vcpu
);
5943 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5945 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5946 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5948 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5949 skip_emulated_instruction(vcpu
);
5953 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5955 skip_emulated_instruction(vcpu
);
5956 WARN(1, "this should never happen\n");
5960 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5962 skip_emulated_instruction(vcpu
);
5963 WARN(1, "this should never happen\n");
5967 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5969 if (likely(fasteoi
)) {
5970 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5971 int access_type
, offset
;
5973 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5974 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5976 * Sane guest uses MOV to write EOI, with written value
5977 * not cared. So make a short-circuit here by avoiding
5978 * heavy instruction emulation.
5980 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5981 (offset
== APIC_EOI
)) {
5982 kvm_lapic_set_eoi(vcpu
);
5983 skip_emulated_instruction(vcpu
);
5987 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5990 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5992 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5993 int vector
= exit_qualification
& 0xff;
5995 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5996 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6000 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6002 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6003 u32 offset
= exit_qualification
& 0xfff;
6005 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6006 kvm_apic_write_nodecode(vcpu
, offset
);
6010 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6012 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6013 unsigned long exit_qualification
;
6014 bool has_error_code
= false;
6017 int reason
, type
, idt_v
, idt_index
;
6019 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6020 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6021 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6023 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6025 reason
= (u32
)exit_qualification
>> 30;
6026 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6028 case INTR_TYPE_NMI_INTR
:
6029 vcpu
->arch
.nmi_injected
= false;
6030 vmx_set_nmi_mask(vcpu
, true);
6032 case INTR_TYPE_EXT_INTR
:
6033 case INTR_TYPE_SOFT_INTR
:
6034 kvm_clear_interrupt_queue(vcpu
);
6036 case INTR_TYPE_HARD_EXCEPTION
:
6037 if (vmx
->idt_vectoring_info
&
6038 VECTORING_INFO_DELIVER_CODE_MASK
) {
6039 has_error_code
= true;
6041 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6044 case INTR_TYPE_SOFT_EXCEPTION
:
6045 kvm_clear_exception_queue(vcpu
);
6051 tss_selector
= exit_qualification
;
6053 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6054 type
!= INTR_TYPE_EXT_INTR
&&
6055 type
!= INTR_TYPE_NMI_INTR
))
6056 skip_emulated_instruction(vcpu
);
6058 if (kvm_task_switch(vcpu
, tss_selector
,
6059 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6060 has_error_code
, error_code
) == EMULATE_FAIL
) {
6061 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6062 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6063 vcpu
->run
->internal
.ndata
= 0;
6068 * TODO: What about debug traps on tss switch?
6069 * Are we supposed to inject them and update dr6?
6075 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6077 unsigned long exit_qualification
;
6082 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6084 gla_validity
= (exit_qualification
>> 7) & 0x3;
6085 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
6086 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6087 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6088 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6089 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6090 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6091 (long unsigned int)exit_qualification
);
6092 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6093 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6098 * EPT violation happened while executing iret from NMI,
6099 * "blocked by NMI" bit has to be set before next VM entry.
6100 * There are errata that may cause this bit to not be set:
6103 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6104 cpu_has_virtual_nmis() &&
6105 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6106 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6108 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6109 trace_kvm_page_fault(gpa
, exit_qualification
);
6111 /* It is a write fault? */
6112 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
6113 /* It is a fetch fault? */
6114 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6115 /* ept page table is present? */
6116 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
6118 vcpu
->arch
.exit_qualification
= exit_qualification
;
6120 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6123 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6128 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6129 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6130 skip_emulated_instruction(vcpu
);
6131 trace_kvm_fast_mmio(gpa
);
6135 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6136 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6137 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6140 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6141 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6143 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6146 /* It is the real ept misconfig */
6149 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6150 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6155 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6157 u32 cpu_based_vm_exec_control
;
6159 /* clear pending NMI */
6160 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6161 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6162 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6163 ++vcpu
->stat
.nmi_window_exits
;
6164 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6169 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6171 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6172 enum emulation_result err
= EMULATE_DONE
;
6175 bool intr_window_requested
;
6176 unsigned count
= 130;
6178 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6179 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6181 while (vmx
->emulation_required
&& count
-- != 0) {
6182 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6183 return handle_interrupt_window(&vmx
->vcpu
);
6185 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6188 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6190 if (err
== EMULATE_USER_EXIT
) {
6191 ++vcpu
->stat
.mmio_exits
;
6196 if (err
!= EMULATE_DONE
) {
6197 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6198 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6199 vcpu
->run
->internal
.ndata
= 0;
6203 if (vcpu
->arch
.halt_request
) {
6204 vcpu
->arch
.halt_request
= 0;
6205 ret
= kvm_vcpu_halt(vcpu
);
6209 if (signal_pending(current
))
6219 static int __grow_ple_window(int val
)
6221 if (ple_window_grow
< 1)
6224 val
= min(val
, ple_window_actual_max
);
6226 if (ple_window_grow
< ple_window
)
6227 val
*= ple_window_grow
;
6229 val
+= ple_window_grow
;
6234 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6239 if (modifier
< ple_window
)
6244 return max(val
, minimum
);
6247 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6249 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6250 int old
= vmx
->ple_window
;
6252 vmx
->ple_window
= __grow_ple_window(old
);
6254 if (vmx
->ple_window
!= old
)
6255 vmx
->ple_window_dirty
= true;
6257 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6260 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6263 int old
= vmx
->ple_window
;
6265 vmx
->ple_window
= __shrink_ple_window(old
,
6266 ple_window_shrink
, ple_window
);
6268 if (vmx
->ple_window
!= old
)
6269 vmx
->ple_window_dirty
= true;
6271 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6275 * ple_window_actual_max is computed to be one grow_ple_window() below
6276 * ple_window_max. (See __grow_ple_window for the reason.)
6277 * This prevents overflows, because ple_window_max is int.
6278 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6280 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6282 static void update_ple_window_actual_max(void)
6284 ple_window_actual_max
=
6285 __shrink_ple_window(max(ple_window_max
, ple_window
),
6286 ple_window_grow
, INT_MIN
);
6290 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6292 static void wakeup_handler(void)
6294 struct kvm_vcpu
*vcpu
;
6295 int cpu
= smp_processor_id();
6297 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6298 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6299 blocked_vcpu_list
) {
6300 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6302 if (pi_test_on(pi_desc
) == 1)
6303 kvm_vcpu_kick(vcpu
);
6305 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6308 static __init
int hardware_setup(void)
6310 int r
= -ENOMEM
, i
, msr
;
6312 rdmsrl_safe(MSR_EFER
, &host_efer
);
6314 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6315 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6317 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6318 if (!vmx_io_bitmap_a
)
6321 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6322 if (!vmx_io_bitmap_b
)
6325 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6326 if (!vmx_msr_bitmap_legacy
)
6329 vmx_msr_bitmap_legacy_x2apic
=
6330 (unsigned long *)__get_free_page(GFP_KERNEL
);
6331 if (!vmx_msr_bitmap_legacy_x2apic
)
6334 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6335 if (!vmx_msr_bitmap_longmode
)
6338 vmx_msr_bitmap_longmode_x2apic
=
6339 (unsigned long *)__get_free_page(GFP_KERNEL
);
6340 if (!vmx_msr_bitmap_longmode_x2apic
)
6344 vmx_msr_bitmap_nested
=
6345 (unsigned long *)__get_free_page(GFP_KERNEL
);
6346 if (!vmx_msr_bitmap_nested
)
6350 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6351 if (!vmx_vmread_bitmap
)
6354 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6355 if (!vmx_vmwrite_bitmap
)
6358 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6359 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6362 * Allow direct access to the PC debug port (it is often used for I/O
6363 * delays, but the vmexits simply slow things down).
6365 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6366 clear_bit(0x80, vmx_io_bitmap_a
);
6368 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6370 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6371 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6373 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6375 if (setup_vmcs_config(&vmcs_config
) < 0) {
6380 if (boot_cpu_has(X86_FEATURE_NX
))
6381 kvm_enable_efer_bits(EFER_NX
);
6383 if (!cpu_has_vmx_vpid())
6385 if (!cpu_has_vmx_shadow_vmcs())
6386 enable_shadow_vmcs
= 0;
6387 if (enable_shadow_vmcs
)
6388 init_vmcs_shadow_fields();
6390 if (!cpu_has_vmx_ept() ||
6391 !cpu_has_vmx_ept_4levels()) {
6393 enable_unrestricted_guest
= 0;
6394 enable_ept_ad_bits
= 0;
6397 if (!cpu_has_vmx_ept_ad_bits())
6398 enable_ept_ad_bits
= 0;
6400 if (!cpu_has_vmx_unrestricted_guest())
6401 enable_unrestricted_guest
= 0;
6403 if (!cpu_has_vmx_flexpriority())
6404 flexpriority_enabled
= 0;
6407 * set_apic_access_page_addr() is used to reload apic access
6408 * page upon invalidation. No need to do anything if not
6409 * using the APIC_ACCESS_ADDR VMCS field.
6411 if (!flexpriority_enabled
)
6412 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6414 if (!cpu_has_vmx_tpr_shadow())
6415 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6417 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6418 kvm_disable_largepages();
6420 if (!cpu_has_vmx_ple())
6423 if (!cpu_has_vmx_apicv())
6426 if (cpu_has_vmx_tsc_scaling()) {
6427 kvm_has_tsc_control
= true;
6428 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6429 kvm_tsc_scaling_ratio_frac_bits
= 48;
6432 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6433 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6434 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6435 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6436 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6437 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6438 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6440 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6441 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6442 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6443 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6445 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6447 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6448 vmx_disable_intercept_msr_read_x2apic(msr
);
6450 /* According SDM, in x2apic mode, the whole id reg is used. But in
6451 * KVM, it only use the highest eight bits. Need to intercept it */
6452 vmx_enable_intercept_msr_read_x2apic(0x802);
6454 vmx_enable_intercept_msr_read_x2apic(0x839);
6456 vmx_disable_intercept_msr_write_x2apic(0x808);
6458 vmx_disable_intercept_msr_write_x2apic(0x80b);
6460 vmx_disable_intercept_msr_write_x2apic(0x83f);
6463 kvm_mmu_set_mask_ptes(0ull,
6464 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6465 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6466 0ull, VMX_EPT_EXECUTABLE_MASK
);
6467 ept_set_mmio_spte_mask();
6472 update_ple_window_actual_max();
6475 * Only enable PML when hardware supports PML feature, and both EPT
6476 * and EPT A/D bit features are enabled -- PML depends on them to work.
6478 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6482 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6483 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6484 kvm_x86_ops
->flush_log_dirty
= NULL
;
6485 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6488 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6491 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6492 cpu_preemption_timer_multi
=
6493 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6495 kvm_x86_ops
->set_hv_timer
= NULL
;
6496 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6499 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6501 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6503 return alloc_kvm_area();
6506 free_page((unsigned long)vmx_vmwrite_bitmap
);
6508 free_page((unsigned long)vmx_vmread_bitmap
);
6511 free_page((unsigned long)vmx_msr_bitmap_nested
);
6513 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6515 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6517 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6519 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6521 free_page((unsigned long)vmx_io_bitmap_b
);
6523 free_page((unsigned long)vmx_io_bitmap_a
);
6528 static __exit
void hardware_unsetup(void)
6530 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6531 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6532 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6533 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6534 free_page((unsigned long)vmx_io_bitmap_b
);
6535 free_page((unsigned long)vmx_io_bitmap_a
);
6536 free_page((unsigned long)vmx_vmwrite_bitmap
);
6537 free_page((unsigned long)vmx_vmread_bitmap
);
6539 free_page((unsigned long)vmx_msr_bitmap_nested
);
6545 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6546 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6548 static int handle_pause(struct kvm_vcpu
*vcpu
)
6551 grow_ple_window(vcpu
);
6553 skip_emulated_instruction(vcpu
);
6554 kvm_vcpu_on_spin(vcpu
);
6559 static int handle_nop(struct kvm_vcpu
*vcpu
)
6561 skip_emulated_instruction(vcpu
);
6565 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6567 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6568 return handle_nop(vcpu
);
6571 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6576 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6578 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6579 return handle_nop(vcpu
);
6583 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6584 * We could reuse a single VMCS for all the L2 guests, but we also want the
6585 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6586 * allows keeping them loaded on the processor, and in the future will allow
6587 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6588 * every entry if they never change.
6589 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6590 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6592 * The following functions allocate and free a vmcs02 in this pool.
6595 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6596 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6598 struct vmcs02_list
*item
;
6599 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6600 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6601 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6602 return &item
->vmcs02
;
6605 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6606 /* Recycle the least recently used VMCS. */
6607 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6608 struct vmcs02_list
, list
);
6609 item
->vmptr
= vmx
->nested
.current_vmptr
;
6610 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6611 return &item
->vmcs02
;
6614 /* Create a new VMCS */
6615 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6618 item
->vmcs02
.vmcs
= alloc_vmcs();
6619 if (!item
->vmcs02
.vmcs
) {
6623 loaded_vmcs_init(&item
->vmcs02
);
6624 item
->vmptr
= vmx
->nested
.current_vmptr
;
6625 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6626 vmx
->nested
.vmcs02_num
++;
6627 return &item
->vmcs02
;
6630 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6631 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6633 struct vmcs02_list
*item
;
6634 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6635 if (item
->vmptr
== vmptr
) {
6636 free_loaded_vmcs(&item
->vmcs02
);
6637 list_del(&item
->list
);
6639 vmx
->nested
.vmcs02_num
--;
6645 * Free all VMCSs saved for this vcpu, except the one pointed by
6646 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6647 * must be &vmx->vmcs01.
6649 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6651 struct vmcs02_list
*item
, *n
;
6653 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6654 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6656 * Something will leak if the above WARN triggers. Better than
6659 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6662 free_loaded_vmcs(&item
->vmcs02
);
6663 list_del(&item
->list
);
6665 vmx
->nested
.vmcs02_num
--;
6670 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6671 * set the success or error code of an emulated VMX instruction, as specified
6672 * by Vol 2B, VMX Instruction Reference, "Conventions".
6674 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6676 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6677 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6678 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6681 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6683 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6684 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6685 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6689 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6690 u32 vm_instruction_error
)
6692 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6694 * failValid writes the error number to the current VMCS, which
6695 * can't be done there isn't a current VMCS.
6697 nested_vmx_failInvalid(vcpu
);
6700 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6701 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6702 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6704 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6706 * We don't need to force a shadow sync because
6707 * VM_INSTRUCTION_ERROR is not shadowed
6711 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6713 /* TODO: not to reset guest simply here. */
6714 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6715 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6718 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6720 struct vcpu_vmx
*vmx
=
6721 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6723 vmx
->nested
.preemption_timer_expired
= true;
6724 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6725 kvm_vcpu_kick(&vmx
->vcpu
);
6727 return HRTIMER_NORESTART
;
6731 * Decode the memory-address operand of a vmx instruction, as recorded on an
6732 * exit caused by such an instruction (run by a guest hypervisor).
6733 * On success, returns 0. When the operand is invalid, returns 1 and throws
6736 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6737 unsigned long exit_qualification
,
6738 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6742 struct kvm_segment s
;
6745 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6746 * Execution", on an exit, vmx_instruction_info holds most of the
6747 * addressing components of the operand. Only the displacement part
6748 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6749 * For how an actual address is calculated from all these components,
6750 * refer to Vol. 1, "Operand Addressing".
6752 int scaling
= vmx_instruction_info
& 3;
6753 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6754 bool is_reg
= vmx_instruction_info
& (1u << 10);
6755 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6756 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6757 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6758 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6759 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6762 kvm_queue_exception(vcpu
, UD_VECTOR
);
6766 /* Addr = segment_base + offset */
6767 /* offset = base + [index * scale] + displacement */
6768 off
= exit_qualification
; /* holds the displacement */
6770 off
+= kvm_register_read(vcpu
, base_reg
);
6772 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6773 vmx_get_segment(vcpu
, &s
, seg_reg
);
6774 *ret
= s
.base
+ off
;
6776 if (addr_size
== 1) /* 32 bit */
6779 /* Checks for #GP/#SS exceptions. */
6781 if (is_protmode(vcpu
)) {
6782 /* Protected mode: apply checks for segment validity in the
6784 * - segment type check (#GP(0) may be thrown)
6785 * - usability check (#GP(0)/#SS(0))
6786 * - limit check (#GP(0)/#SS(0))
6789 /* #GP(0) if the destination operand is located in a
6790 * read-only data segment or any code segment.
6792 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6794 /* #GP(0) if the source operand is located in an
6795 * execute-only code segment
6797 exn
= ((s
.type
& 0xa) == 8);
6800 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6803 if (is_long_mode(vcpu
)) {
6804 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6805 * non-canonical form. This is an only check for long mode.
6807 exn
= is_noncanonical_address(*ret
);
6808 } else if (is_protmode(vcpu
)) {
6809 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6811 exn
= (s
.unusable
!= 0);
6812 /* Protected mode: #GP(0)/#SS(0) if the memory
6813 * operand is outside the segment limit.
6815 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6818 kvm_queue_exception_e(vcpu
,
6819 seg_reg
== VCPU_SREG_SS
?
6820 SS_VECTOR
: GP_VECTOR
,
6829 * This function performs the various checks including
6830 * - if it's 4KB aligned
6831 * - No bits beyond the physical address width are set
6832 * - Returns 0 on success or else 1
6833 * (Intel SDM Section 30.3)
6835 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6840 struct x86_exception e
;
6842 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6843 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6845 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6846 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6849 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6850 sizeof(vmptr
), &e
)) {
6851 kvm_inject_page_fault(vcpu
, &e
);
6855 switch (exit_reason
) {
6856 case EXIT_REASON_VMON
:
6859 * The first 4 bytes of VMXON region contain the supported
6860 * VMCS revision identifier
6862 * Note - IA32_VMX_BASIC[48] will never be 1
6863 * for the nested case;
6864 * which replaces physical address width with 32
6867 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6868 nested_vmx_failInvalid(vcpu
);
6869 skip_emulated_instruction(vcpu
);
6873 page
= nested_get_page(vcpu
, vmptr
);
6875 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6876 nested_vmx_failInvalid(vcpu
);
6878 skip_emulated_instruction(vcpu
);
6882 vmx
->nested
.vmxon_ptr
= vmptr
;
6884 case EXIT_REASON_VMCLEAR
:
6885 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6886 nested_vmx_failValid(vcpu
,
6887 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6888 skip_emulated_instruction(vcpu
);
6892 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6893 nested_vmx_failValid(vcpu
,
6894 VMXERR_VMCLEAR_VMXON_POINTER
);
6895 skip_emulated_instruction(vcpu
);
6899 case EXIT_REASON_VMPTRLD
:
6900 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6901 nested_vmx_failValid(vcpu
,
6902 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6903 skip_emulated_instruction(vcpu
);
6907 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6908 nested_vmx_failValid(vcpu
,
6909 VMXERR_VMCLEAR_VMXON_POINTER
);
6910 skip_emulated_instruction(vcpu
);
6915 return 1; /* shouldn't happen */
6924 * Emulate the VMXON instruction.
6925 * Currently, we just remember that VMX is active, and do not save or even
6926 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6927 * do not currently need to store anything in that guest-allocated memory
6928 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6929 * argument is different from the VMXON pointer (which the spec says they do).
6931 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6933 struct kvm_segment cs
;
6934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6935 struct vmcs
*shadow_vmcs
;
6936 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6937 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6939 /* The Intel VMX Instruction Reference lists a bunch of bits that
6940 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6941 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6942 * Otherwise, we should fail with #UD. We test these now:
6944 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6945 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6946 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6947 kvm_queue_exception(vcpu
, UD_VECTOR
);
6951 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6952 if (is_long_mode(vcpu
) && !cs
.l
) {
6953 kvm_queue_exception(vcpu
, UD_VECTOR
);
6957 if (vmx_get_cpl(vcpu
)) {
6958 kvm_inject_gp(vcpu
, 0);
6962 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6965 if (vmx
->nested
.vmxon
) {
6966 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6967 skip_emulated_instruction(vcpu
);
6971 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6972 != VMXON_NEEDED_FEATURES
) {
6973 kvm_inject_gp(vcpu
, 0);
6977 if (enable_shadow_vmcs
) {
6978 shadow_vmcs
= alloc_vmcs();
6981 /* mark vmcs as shadow */
6982 shadow_vmcs
->revision_id
|= (1u << 31);
6983 /* init shadow vmcs */
6984 vmcs_clear(shadow_vmcs
);
6985 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6988 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6989 vmx
->nested
.vmcs02_num
= 0;
6991 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6993 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6995 vmx
->nested
.vmxon
= true;
6997 skip_emulated_instruction(vcpu
);
6998 nested_vmx_succeed(vcpu
);
7003 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7004 * for running VMX instructions (except VMXON, whose prerequisites are
7005 * slightly different). It also specifies what exception to inject otherwise.
7007 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7009 struct kvm_segment cs
;
7010 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7012 if (!vmx
->nested
.vmxon
) {
7013 kvm_queue_exception(vcpu
, UD_VECTOR
);
7017 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7018 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
7019 (is_long_mode(vcpu
) && !cs
.l
)) {
7020 kvm_queue_exception(vcpu
, UD_VECTOR
);
7024 if (vmx_get_cpl(vcpu
)) {
7025 kvm_inject_gp(vcpu
, 0);
7032 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7034 if (vmx
->nested
.current_vmptr
== -1ull)
7037 /* current_vmptr and current_vmcs12 are always set/reset together */
7038 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7041 if (enable_shadow_vmcs
) {
7042 /* copy to memory all shadowed fields in case
7043 they were modified */
7044 copy_shadow_to_vmcs12(vmx
);
7045 vmx
->nested
.sync_shadow_vmcs
= false;
7046 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7047 SECONDARY_EXEC_SHADOW_VMCS
);
7048 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7050 vmx
->nested
.posted_intr_nv
= -1;
7051 kunmap(vmx
->nested
.current_vmcs12_page
);
7052 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7053 vmx
->nested
.current_vmptr
= -1ull;
7054 vmx
->nested
.current_vmcs12
= NULL
;
7058 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7059 * just stops using VMX.
7061 static void free_nested(struct vcpu_vmx
*vmx
)
7063 if (!vmx
->nested
.vmxon
)
7066 vmx
->nested
.vmxon
= false;
7067 free_vpid(vmx
->nested
.vpid02
);
7068 nested_release_vmcs12(vmx
);
7069 if (enable_shadow_vmcs
)
7070 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
7071 /* Unpin physical memory we referred to in current vmcs02 */
7072 if (vmx
->nested
.apic_access_page
) {
7073 nested_release_page(vmx
->nested
.apic_access_page
);
7074 vmx
->nested
.apic_access_page
= NULL
;
7076 if (vmx
->nested
.virtual_apic_page
) {
7077 nested_release_page(vmx
->nested
.virtual_apic_page
);
7078 vmx
->nested
.virtual_apic_page
= NULL
;
7080 if (vmx
->nested
.pi_desc_page
) {
7081 kunmap(vmx
->nested
.pi_desc_page
);
7082 nested_release_page(vmx
->nested
.pi_desc_page
);
7083 vmx
->nested
.pi_desc_page
= NULL
;
7084 vmx
->nested
.pi_desc
= NULL
;
7087 nested_free_all_saved_vmcss(vmx
);
7090 /* Emulate the VMXOFF instruction */
7091 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7093 if (!nested_vmx_check_permission(vcpu
))
7095 free_nested(to_vmx(vcpu
));
7096 skip_emulated_instruction(vcpu
);
7097 nested_vmx_succeed(vcpu
);
7101 /* Emulate the VMCLEAR instruction */
7102 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7104 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7106 struct vmcs12
*vmcs12
;
7109 if (!nested_vmx_check_permission(vcpu
))
7112 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7115 if (vmptr
== vmx
->nested
.current_vmptr
)
7116 nested_release_vmcs12(vmx
);
7118 page
= nested_get_page(vcpu
, vmptr
);
7121 * For accurate processor emulation, VMCLEAR beyond available
7122 * physical memory should do nothing at all. However, it is
7123 * possible that a nested vmx bug, not a guest hypervisor bug,
7124 * resulted in this case, so let's shut down before doing any
7127 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7130 vmcs12
= kmap(page
);
7131 vmcs12
->launch_state
= 0;
7133 nested_release_page(page
);
7135 nested_free_vmcs02(vmx
, vmptr
);
7137 skip_emulated_instruction(vcpu
);
7138 nested_vmx_succeed(vcpu
);
7142 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7144 /* Emulate the VMLAUNCH instruction */
7145 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7147 return nested_vmx_run(vcpu
, true);
7150 /* Emulate the VMRESUME instruction */
7151 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7154 return nested_vmx_run(vcpu
, false);
7157 enum vmcs_field_type
{
7158 VMCS_FIELD_TYPE_U16
= 0,
7159 VMCS_FIELD_TYPE_U64
= 1,
7160 VMCS_FIELD_TYPE_U32
= 2,
7161 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7164 static inline int vmcs_field_type(unsigned long field
)
7166 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7167 return VMCS_FIELD_TYPE_U32
;
7168 return (field
>> 13) & 0x3 ;
7171 static inline int vmcs_field_readonly(unsigned long field
)
7173 return (((field
>> 10) & 0x3) == 1);
7177 * Read a vmcs12 field. Since these can have varying lengths and we return
7178 * one type, we chose the biggest type (u64) and zero-extend the return value
7179 * to that size. Note that the caller, handle_vmread, might need to use only
7180 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7181 * 64-bit fields are to be returned).
7183 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7184 unsigned long field
, u64
*ret
)
7186 short offset
= vmcs_field_to_offset(field
);
7192 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7194 switch (vmcs_field_type(field
)) {
7195 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7196 *ret
= *((natural_width
*)p
);
7198 case VMCS_FIELD_TYPE_U16
:
7201 case VMCS_FIELD_TYPE_U32
:
7204 case VMCS_FIELD_TYPE_U64
:
7214 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7215 unsigned long field
, u64 field_value
){
7216 short offset
= vmcs_field_to_offset(field
);
7217 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7221 switch (vmcs_field_type(field
)) {
7222 case VMCS_FIELD_TYPE_U16
:
7223 *(u16
*)p
= field_value
;
7225 case VMCS_FIELD_TYPE_U32
:
7226 *(u32
*)p
= field_value
;
7228 case VMCS_FIELD_TYPE_U64
:
7229 *(u64
*)p
= field_value
;
7231 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7232 *(natural_width
*)p
= field_value
;
7241 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7244 unsigned long field
;
7246 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7247 const unsigned long *fields
= shadow_read_write_fields
;
7248 const int num_fields
= max_shadow_read_write_fields
;
7252 vmcs_load(shadow_vmcs
);
7254 for (i
= 0; i
< num_fields
; i
++) {
7256 switch (vmcs_field_type(field
)) {
7257 case VMCS_FIELD_TYPE_U16
:
7258 field_value
= vmcs_read16(field
);
7260 case VMCS_FIELD_TYPE_U32
:
7261 field_value
= vmcs_read32(field
);
7263 case VMCS_FIELD_TYPE_U64
:
7264 field_value
= vmcs_read64(field
);
7266 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7267 field_value
= vmcs_readl(field
);
7273 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7276 vmcs_clear(shadow_vmcs
);
7277 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7282 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7284 const unsigned long *fields
[] = {
7285 shadow_read_write_fields
,
7286 shadow_read_only_fields
7288 const int max_fields
[] = {
7289 max_shadow_read_write_fields
,
7290 max_shadow_read_only_fields
7293 unsigned long field
;
7294 u64 field_value
= 0;
7295 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7297 vmcs_load(shadow_vmcs
);
7299 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7300 for (i
= 0; i
< max_fields
[q
]; i
++) {
7301 field
= fields
[q
][i
];
7302 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7304 switch (vmcs_field_type(field
)) {
7305 case VMCS_FIELD_TYPE_U16
:
7306 vmcs_write16(field
, (u16
)field_value
);
7308 case VMCS_FIELD_TYPE_U32
:
7309 vmcs_write32(field
, (u32
)field_value
);
7311 case VMCS_FIELD_TYPE_U64
:
7312 vmcs_write64(field
, (u64
)field_value
);
7314 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7315 vmcs_writel(field
, (long)field_value
);
7324 vmcs_clear(shadow_vmcs
);
7325 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7329 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7330 * used before) all generate the same failure when it is missing.
7332 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7335 if (vmx
->nested
.current_vmptr
== -1ull) {
7336 nested_vmx_failInvalid(vcpu
);
7337 skip_emulated_instruction(vcpu
);
7343 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7345 unsigned long field
;
7347 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7348 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7351 if (!nested_vmx_check_permission(vcpu
) ||
7352 !nested_vmx_check_vmcs12(vcpu
))
7355 /* Decode instruction info and find the field to read */
7356 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7357 /* Read the field, zero-extended to a u64 field_value */
7358 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7359 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7360 skip_emulated_instruction(vcpu
);
7364 * Now copy part of this value to register or memory, as requested.
7365 * Note that the number of bits actually copied is 32 or 64 depending
7366 * on the guest's mode (32 or 64 bit), not on the given field's length.
7368 if (vmx_instruction_info
& (1u << 10)) {
7369 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7372 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7373 vmx_instruction_info
, true, &gva
))
7375 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7376 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7377 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7380 nested_vmx_succeed(vcpu
);
7381 skip_emulated_instruction(vcpu
);
7386 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7388 unsigned long field
;
7390 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7391 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7392 /* The value to write might be 32 or 64 bits, depending on L1's long
7393 * mode, and eventually we need to write that into a field of several
7394 * possible lengths. The code below first zero-extends the value to 64
7395 * bit (field_value), and then copies only the appropriate number of
7396 * bits into the vmcs12 field.
7398 u64 field_value
= 0;
7399 struct x86_exception e
;
7401 if (!nested_vmx_check_permission(vcpu
) ||
7402 !nested_vmx_check_vmcs12(vcpu
))
7405 if (vmx_instruction_info
& (1u << 10))
7406 field_value
= kvm_register_readl(vcpu
,
7407 (((vmx_instruction_info
) >> 3) & 0xf));
7409 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7410 vmx_instruction_info
, false, &gva
))
7412 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7413 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7414 kvm_inject_page_fault(vcpu
, &e
);
7420 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7421 if (vmcs_field_readonly(field
)) {
7422 nested_vmx_failValid(vcpu
,
7423 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7424 skip_emulated_instruction(vcpu
);
7428 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7429 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7430 skip_emulated_instruction(vcpu
);
7434 nested_vmx_succeed(vcpu
);
7435 skip_emulated_instruction(vcpu
);
7439 /* Emulate the VMPTRLD instruction */
7440 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7442 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7445 if (!nested_vmx_check_permission(vcpu
))
7448 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7451 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7452 struct vmcs12
*new_vmcs12
;
7454 page
= nested_get_page(vcpu
, vmptr
);
7456 nested_vmx_failInvalid(vcpu
);
7457 skip_emulated_instruction(vcpu
);
7460 new_vmcs12
= kmap(page
);
7461 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7463 nested_release_page_clean(page
);
7464 nested_vmx_failValid(vcpu
,
7465 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7466 skip_emulated_instruction(vcpu
);
7470 nested_release_vmcs12(vmx
);
7471 vmx
->nested
.current_vmptr
= vmptr
;
7472 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7473 vmx
->nested
.current_vmcs12_page
= page
;
7474 if (enable_shadow_vmcs
) {
7475 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7476 SECONDARY_EXEC_SHADOW_VMCS
);
7477 vmcs_write64(VMCS_LINK_POINTER
,
7478 __pa(vmx
->nested
.current_shadow_vmcs
));
7479 vmx
->nested
.sync_shadow_vmcs
= true;
7483 nested_vmx_succeed(vcpu
);
7484 skip_emulated_instruction(vcpu
);
7488 /* Emulate the VMPTRST instruction */
7489 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7491 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7492 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7494 struct x86_exception e
;
7496 if (!nested_vmx_check_permission(vcpu
))
7499 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7500 vmx_instruction_info
, true, &vmcs_gva
))
7502 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7503 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7504 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7506 kvm_inject_page_fault(vcpu
, &e
);
7509 nested_vmx_succeed(vcpu
);
7510 skip_emulated_instruction(vcpu
);
7514 /* Emulate the INVEPT instruction */
7515 static int handle_invept(struct kvm_vcpu
*vcpu
)
7517 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7518 u32 vmx_instruction_info
, types
;
7521 struct x86_exception e
;
7526 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7527 SECONDARY_EXEC_ENABLE_EPT
) ||
7528 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7529 kvm_queue_exception(vcpu
, UD_VECTOR
);
7533 if (!nested_vmx_check_permission(vcpu
))
7536 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7537 kvm_queue_exception(vcpu
, UD_VECTOR
);
7541 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7542 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7544 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7546 if (!(types
& (1UL << type
))) {
7547 nested_vmx_failValid(vcpu
,
7548 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7549 skip_emulated_instruction(vcpu
);
7553 /* According to the Intel VMX instruction reference, the memory
7554 * operand is read even if it isn't needed (e.g., for type==global)
7556 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7557 vmx_instruction_info
, false, &gva
))
7559 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7560 sizeof(operand
), &e
)) {
7561 kvm_inject_page_fault(vcpu
, &e
);
7566 case VMX_EPT_EXTENT_GLOBAL
:
7567 kvm_mmu_sync_roots(vcpu
);
7568 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7569 nested_vmx_succeed(vcpu
);
7572 /* Trap single context invalidation invept calls */
7577 skip_emulated_instruction(vcpu
);
7581 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7583 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7584 u32 vmx_instruction_info
;
7585 unsigned long type
, types
;
7587 struct x86_exception e
;
7590 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7591 SECONDARY_EXEC_ENABLE_VPID
) ||
7592 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7593 kvm_queue_exception(vcpu
, UD_VECTOR
);
7597 if (!nested_vmx_check_permission(vcpu
))
7600 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7601 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7603 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7605 if (!(types
& (1UL << type
))) {
7606 nested_vmx_failValid(vcpu
,
7607 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7608 skip_emulated_instruction(vcpu
);
7612 /* according to the intel vmx instruction reference, the memory
7613 * operand is read even if it isn't needed (e.g., for type==global)
7615 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7616 vmx_instruction_info
, false, &gva
))
7618 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7620 kvm_inject_page_fault(vcpu
, &e
);
7625 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7627 * Old versions of KVM use the single-context version so we
7628 * have to support it; just treat it the same as all-context.
7630 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7631 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7632 nested_vmx_succeed(vcpu
);
7635 /* Trap individual address invalidation invvpid calls */
7640 skip_emulated_instruction(vcpu
);
7644 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7646 unsigned long exit_qualification
;
7648 trace_kvm_pml_full(vcpu
->vcpu_id
);
7650 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7653 * PML buffer FULL happened while executing iret from NMI,
7654 * "blocked by NMI" bit has to be set before next VM entry.
7656 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7657 cpu_has_virtual_nmis() &&
7658 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7659 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7660 GUEST_INTR_STATE_NMI
);
7663 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7664 * here.., and there's no userspace involvement needed for PML.
7669 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7671 /* we never catch pcommit instruct for L1 guest. */
7676 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7678 kvm_lapic_expired_hv_timer(vcpu
);
7683 * The exit handlers return 1 if the exit was handled fully and guest execution
7684 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7685 * to be done to userspace and return 0.
7687 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7688 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7689 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7690 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7691 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7692 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7693 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7694 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7695 [EXIT_REASON_CPUID
] = handle_cpuid
,
7696 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7697 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7698 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7699 [EXIT_REASON_HLT
] = handle_halt
,
7700 [EXIT_REASON_INVD
] = handle_invd
,
7701 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7702 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7703 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7704 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7705 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7706 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7707 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7708 [EXIT_REASON_VMREAD
] = handle_vmread
,
7709 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7710 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7711 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7712 [EXIT_REASON_VMON
] = handle_vmon
,
7713 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7714 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7715 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7716 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7717 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7718 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7719 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7720 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7721 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7722 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7723 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7724 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7725 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7726 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7727 [EXIT_REASON_INVEPT
] = handle_invept
,
7728 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7729 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7730 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7731 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7732 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7733 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7736 static const int kvm_vmx_max_exit_handlers
=
7737 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7739 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7740 struct vmcs12
*vmcs12
)
7742 unsigned long exit_qualification
;
7743 gpa_t bitmap
, last_bitmap
;
7748 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7749 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7751 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7753 port
= exit_qualification
>> 16;
7754 size
= (exit_qualification
& 7) + 1;
7756 last_bitmap
= (gpa_t
)-1;
7761 bitmap
= vmcs12
->io_bitmap_a
;
7762 else if (port
< 0x10000)
7763 bitmap
= vmcs12
->io_bitmap_b
;
7766 bitmap
+= (port
& 0x7fff) / 8;
7768 if (last_bitmap
!= bitmap
)
7769 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7771 if (b
& (1 << (port
& 7)))
7776 last_bitmap
= bitmap
;
7783 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7784 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7785 * disinterest in the current event (read or write a specific MSR) by using an
7786 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7788 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7789 struct vmcs12
*vmcs12
, u32 exit_reason
)
7791 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7794 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7798 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7799 * for the four combinations of read/write and low/high MSR numbers.
7800 * First we need to figure out which of the four to use:
7802 bitmap
= vmcs12
->msr_bitmap
;
7803 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7805 if (msr_index
>= 0xc0000000) {
7806 msr_index
-= 0xc0000000;
7810 /* Then read the msr_index'th bit from this bitmap: */
7811 if (msr_index
< 1024*8) {
7813 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7815 return 1 & (b
>> (msr_index
& 7));
7817 return true; /* let L1 handle the wrong parameter */
7821 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7822 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7823 * intercept (via guest_host_mask etc.) the current event.
7825 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7826 struct vmcs12
*vmcs12
)
7828 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7829 int cr
= exit_qualification
& 15;
7830 int reg
= (exit_qualification
>> 8) & 15;
7831 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7833 switch ((exit_qualification
>> 4) & 3) {
7834 case 0: /* mov to cr */
7837 if (vmcs12
->cr0_guest_host_mask
&
7838 (val
^ vmcs12
->cr0_read_shadow
))
7842 if ((vmcs12
->cr3_target_count
>= 1 &&
7843 vmcs12
->cr3_target_value0
== val
) ||
7844 (vmcs12
->cr3_target_count
>= 2 &&
7845 vmcs12
->cr3_target_value1
== val
) ||
7846 (vmcs12
->cr3_target_count
>= 3 &&
7847 vmcs12
->cr3_target_value2
== val
) ||
7848 (vmcs12
->cr3_target_count
>= 4 &&
7849 vmcs12
->cr3_target_value3
== val
))
7851 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7855 if (vmcs12
->cr4_guest_host_mask
&
7856 (vmcs12
->cr4_read_shadow
^ val
))
7860 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7866 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7867 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7870 case 1: /* mov from cr */
7873 if (vmcs12
->cpu_based_vm_exec_control
&
7874 CPU_BASED_CR3_STORE_EXITING
)
7878 if (vmcs12
->cpu_based_vm_exec_control
&
7879 CPU_BASED_CR8_STORE_EXITING
)
7886 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7887 * cr0. Other attempted changes are ignored, with no exit.
7889 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7890 (val
^ vmcs12
->cr0_read_shadow
))
7892 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7893 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7902 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7903 * should handle it ourselves in L0 (and then continue L2). Only call this
7904 * when in is_guest_mode (L2).
7906 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7908 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7909 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7910 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7911 u32 exit_reason
= vmx
->exit_reason
;
7913 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7914 vmcs_readl(EXIT_QUALIFICATION
),
7915 vmx
->idt_vectoring_info
,
7917 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7920 if (vmx
->nested
.nested_run_pending
)
7923 if (unlikely(vmx
->fail
)) {
7924 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7925 vmcs_read32(VM_INSTRUCTION_ERROR
));
7929 switch (exit_reason
) {
7930 case EXIT_REASON_EXCEPTION_NMI
:
7931 if (!is_exception(intr_info
))
7933 else if (is_page_fault(intr_info
))
7935 else if (is_no_device(intr_info
) &&
7936 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7938 else if (is_debug(intr_info
) &&
7940 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7942 else if (is_breakpoint(intr_info
) &&
7943 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7945 return vmcs12
->exception_bitmap
&
7946 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7947 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7949 case EXIT_REASON_TRIPLE_FAULT
:
7951 case EXIT_REASON_PENDING_INTERRUPT
:
7952 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7953 case EXIT_REASON_NMI_WINDOW
:
7954 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7955 case EXIT_REASON_TASK_SWITCH
:
7957 case EXIT_REASON_CPUID
:
7958 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7961 case EXIT_REASON_HLT
:
7962 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7963 case EXIT_REASON_INVD
:
7965 case EXIT_REASON_INVLPG
:
7966 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7967 case EXIT_REASON_RDPMC
:
7968 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7969 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7970 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7971 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7972 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7973 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7974 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7975 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7976 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7978 * VMX instructions trap unconditionally. This allows L1 to
7979 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7982 case EXIT_REASON_CR_ACCESS
:
7983 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7984 case EXIT_REASON_DR_ACCESS
:
7985 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7986 case EXIT_REASON_IO_INSTRUCTION
:
7987 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7988 case EXIT_REASON_MSR_READ
:
7989 case EXIT_REASON_MSR_WRITE
:
7990 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7991 case EXIT_REASON_INVALID_STATE
:
7993 case EXIT_REASON_MWAIT_INSTRUCTION
:
7994 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7995 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7996 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7997 case EXIT_REASON_MONITOR_INSTRUCTION
:
7998 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7999 case EXIT_REASON_PAUSE_INSTRUCTION
:
8000 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8001 nested_cpu_has2(vmcs12
,
8002 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8003 case EXIT_REASON_MCE_DURING_VMENTRY
:
8005 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8006 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8007 case EXIT_REASON_APIC_ACCESS
:
8008 return nested_cpu_has2(vmcs12
,
8009 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8010 case EXIT_REASON_APIC_WRITE
:
8011 case EXIT_REASON_EOI_INDUCED
:
8012 /* apic_write and eoi_induced should exit unconditionally. */
8014 case EXIT_REASON_EPT_VIOLATION
:
8016 * L0 always deals with the EPT violation. If nested EPT is
8017 * used, and the nested mmu code discovers that the address is
8018 * missing in the guest EPT table (EPT12), the EPT violation
8019 * will be injected with nested_ept_inject_page_fault()
8022 case EXIT_REASON_EPT_MISCONFIG
:
8024 * L2 never uses directly L1's EPT, but rather L0's own EPT
8025 * table (shadow on EPT) or a merged EPT table that L0 built
8026 * (EPT on EPT). So any problems with the structure of the
8027 * table is L0's fault.
8030 case EXIT_REASON_WBINVD
:
8031 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8032 case EXIT_REASON_XSETBV
:
8034 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8036 * This should never happen, since it is not possible to
8037 * set XSS to a non-zero value---neither in L1 nor in L2.
8038 * If if it were, XSS would have to be checked against
8039 * the XSS exit bitmap in vmcs12.
8041 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8042 case EXIT_REASON_PCOMMIT
:
8043 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
8049 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8051 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8052 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8055 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
8057 struct page
*pml_pg
;
8059 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
8063 vmx
->pml_pg
= pml_pg
;
8065 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
8066 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8071 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8074 __free_page(vmx
->pml_pg
);
8079 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8081 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8085 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8087 /* Do nothing if PML buffer is empty */
8088 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8091 /* PML index always points to next available PML buffer entity */
8092 if (pml_idx
>= PML_ENTITY_NUM
)
8097 pml_buf
= page_address(vmx
->pml_pg
);
8098 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8101 gpa
= pml_buf
[pml_idx
];
8102 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8103 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8106 /* reset PML index */
8107 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8111 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8112 * Called before reporting dirty_bitmap to userspace.
8114 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8117 struct kvm_vcpu
*vcpu
;
8119 * We only need to kick vcpu out of guest mode here, as PML buffer
8120 * is flushed at beginning of all VMEXITs, and it's obvious that only
8121 * vcpus running in guest are possible to have unflushed GPAs in PML
8124 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8125 kvm_vcpu_kick(vcpu
);
8128 static void vmx_dump_sel(char *name
, uint32_t sel
)
8130 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8131 name
, vmcs_read32(sel
),
8132 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8133 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8134 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8137 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8139 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8140 name
, vmcs_read32(limit
),
8141 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8144 static void dump_vmcs(void)
8146 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8147 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8148 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8149 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8150 u32 secondary_exec_control
= 0;
8151 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8152 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8155 if (cpu_has_secondary_exec_ctrls())
8156 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8158 pr_err("*** Guest State ***\n");
8159 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8160 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8161 vmcs_readl(CR0_GUEST_HOST_MASK
));
8162 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8163 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8164 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8165 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8166 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8168 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8169 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8170 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8171 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8173 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8174 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8175 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8176 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8177 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8178 vmcs_readl(GUEST_SYSENTER_ESP
),
8179 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8180 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8181 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8182 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8183 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8184 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8185 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8186 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8187 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8188 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8189 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8190 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8191 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8192 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8193 efer
, vmcs_read64(GUEST_IA32_PAT
));
8194 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8195 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8196 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8197 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8198 pr_err("PerfGlobCtl = 0x%016llx\n",
8199 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8200 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8201 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8202 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8203 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8204 vmcs_read32(GUEST_ACTIVITY_STATE
));
8205 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8206 pr_err("InterruptStatus = %04x\n",
8207 vmcs_read16(GUEST_INTR_STATUS
));
8209 pr_err("*** Host State ***\n");
8210 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8211 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8212 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8213 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8214 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8215 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8216 vmcs_read16(HOST_TR_SELECTOR
));
8217 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8218 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8219 vmcs_readl(HOST_TR_BASE
));
8220 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8221 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8222 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8223 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8224 vmcs_readl(HOST_CR4
));
8225 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8226 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8227 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8228 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8229 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8230 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8231 vmcs_read64(HOST_IA32_EFER
),
8232 vmcs_read64(HOST_IA32_PAT
));
8233 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8234 pr_err("PerfGlobCtl = 0x%016llx\n",
8235 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8237 pr_err("*** Control State ***\n");
8238 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8239 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8240 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8241 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8242 vmcs_read32(EXCEPTION_BITMAP
),
8243 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8244 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8245 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8246 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8247 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8248 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8249 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8250 vmcs_read32(VM_EXIT_INTR_INFO
),
8251 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8252 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8253 pr_err(" reason=%08x qualification=%016lx\n",
8254 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8255 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8256 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8257 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8258 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8259 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8260 pr_err("TSC Multiplier = 0x%016llx\n",
8261 vmcs_read64(TSC_MULTIPLIER
));
8262 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8263 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8264 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8265 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8266 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8267 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8268 n
= vmcs_read32(CR3_TARGET_COUNT
);
8269 for (i
= 0; i
+ 1 < n
; i
+= 4)
8270 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8271 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8272 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8274 pr_err("CR3 target%u=%016lx\n",
8275 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8276 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8277 pr_err("PLE Gap=%08x Window=%08x\n",
8278 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8279 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8280 pr_err("Virtual processor ID = 0x%04x\n",
8281 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8285 * The guest has exited. See if we can fix it or if we need userspace
8288 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8290 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8291 u32 exit_reason
= vmx
->exit_reason
;
8292 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8294 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8297 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8298 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8299 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8300 * mode as if vcpus is in root mode, the PML buffer must has been
8304 vmx_flush_pml_buffer(vcpu
);
8306 /* If guest state is invalid, start emulating */
8307 if (vmx
->emulation_required
)
8308 return handle_invalid_guest_state(vcpu
);
8310 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8311 nested_vmx_vmexit(vcpu
, exit_reason
,
8312 vmcs_read32(VM_EXIT_INTR_INFO
),
8313 vmcs_readl(EXIT_QUALIFICATION
));
8317 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8319 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8320 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8325 if (unlikely(vmx
->fail
)) {
8326 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8327 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8328 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8334 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8335 * delivery event since it indicates guest is accessing MMIO.
8336 * The vm-exit can be triggered again after return to guest that
8337 * will cause infinite loop.
8339 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8340 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8341 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8342 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8343 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8344 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8345 vcpu
->run
->internal
.ndata
= 2;
8346 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8347 vcpu
->run
->internal
.data
[1] = exit_reason
;
8351 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8352 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8353 get_vmcs12(vcpu
))))) {
8354 if (vmx_interrupt_allowed(vcpu
)) {
8355 vmx
->soft_vnmi_blocked
= 0;
8356 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8357 vcpu
->arch
.nmi_pending
) {
8359 * This CPU don't support us in finding the end of an
8360 * NMI-blocked window if the guest runs with IRQs
8361 * disabled. So we pull the trigger after 1 s of
8362 * futile waiting, but inform the user about this.
8364 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8365 "state on VCPU %d after 1 s timeout\n",
8366 __func__
, vcpu
->vcpu_id
);
8367 vmx
->soft_vnmi_blocked
= 0;
8371 if (exit_reason
< kvm_vmx_max_exit_handlers
8372 && kvm_vmx_exit_handlers
[exit_reason
])
8373 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8375 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8376 kvm_queue_exception(vcpu
, UD_VECTOR
);
8381 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8383 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8385 if (is_guest_mode(vcpu
) &&
8386 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8389 if (irr
== -1 || tpr
< irr
) {
8390 vmcs_write32(TPR_THRESHOLD
, 0);
8394 vmcs_write32(TPR_THRESHOLD
, irr
);
8397 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8399 u32 sec_exec_control
;
8402 * There is not point to enable virtualize x2apic without enable
8405 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8406 !kvm_vcpu_apicv_active(vcpu
))
8409 if (!cpu_need_tpr_shadow(vcpu
))
8412 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8415 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8416 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8418 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8419 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8421 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8423 vmx_set_msr_bitmap(vcpu
);
8426 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8431 * Currently we do not handle the nested case where L2 has an
8432 * APIC access page of its own; that page is still pinned.
8433 * Hence, we skip the case where the VCPU is in guest mode _and_
8434 * L1 prepared an APIC access page for L2.
8436 * For the case where L1 and L2 share the same APIC access page
8437 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8438 * in the vmcs12), this function will only update either the vmcs01
8439 * or the vmcs02. If the former, the vmcs02 will be updated by
8440 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8441 * the next L2->L1 exit.
8443 if (!is_guest_mode(vcpu
) ||
8444 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8445 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8446 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8449 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8457 status
= vmcs_read16(GUEST_INTR_STATUS
);
8459 if (max_isr
!= old
) {
8461 status
|= max_isr
<< 8;
8462 vmcs_write16(GUEST_INTR_STATUS
, status
);
8466 static void vmx_set_rvi(int vector
)
8474 status
= vmcs_read16(GUEST_INTR_STATUS
);
8475 old
= (u8
)status
& 0xff;
8476 if ((u8
)vector
!= old
) {
8478 status
|= (u8
)vector
;
8479 vmcs_write16(GUEST_INTR_STATUS
, status
);
8483 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8485 if (!is_guest_mode(vcpu
)) {
8486 vmx_set_rvi(max_irr
);
8494 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8497 if (nested_exit_on_intr(vcpu
))
8501 * Else, fall back to pre-APICv interrupt injection since L2
8502 * is run without virtual interrupt delivery.
8504 if (!kvm_event_needs_reinjection(vcpu
) &&
8505 vmx_interrupt_allowed(vcpu
)) {
8506 kvm_queue_interrupt(vcpu
, max_irr
, false);
8507 vmx_inject_irq(vcpu
);
8511 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8513 if (!kvm_vcpu_apicv_active(vcpu
))
8516 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8517 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8518 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8519 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8522 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8526 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8527 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8530 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8531 exit_intr_info
= vmx
->exit_intr_info
;
8533 /* Handle machine checks before interrupts are enabled */
8534 if (is_machine_check(exit_intr_info
))
8535 kvm_machine_check();
8537 /* We need to handle NMIs before interrupts are enabled */
8538 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8539 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8540 kvm_before_handle_nmi(&vmx
->vcpu
);
8542 kvm_after_handle_nmi(&vmx
->vcpu
);
8546 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8548 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8549 register void *__sp
asm(_ASM_SP
);
8552 * If external interrupt exists, IF bit is set in rflags/eflags on the
8553 * interrupt stack frame, and interrupt will be enabled on a return
8554 * from interrupt handler.
8556 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8557 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8558 unsigned int vector
;
8559 unsigned long entry
;
8561 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8562 #ifdef CONFIG_X86_64
8566 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8567 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8568 entry
= gate_offset(*desc
);
8570 #ifdef CONFIG_X86_64
8571 "mov %%" _ASM_SP
", %[sp]\n\t"
8572 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8577 __ASM_SIZE(push
) " $%c[cs]\n\t"
8578 "call *%[entry]\n\t"
8580 #ifdef CONFIG_X86_64
8586 [ss
]"i"(__KERNEL_DS
),
8587 [cs
]"i"(__KERNEL_CS
)
8592 static bool vmx_has_high_real_mode_segbase(void)
8594 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8597 static bool vmx_mpx_supported(void)
8599 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8600 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8603 static bool vmx_xsaves_supported(void)
8605 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8606 SECONDARY_EXEC_XSAVES
;
8609 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8614 bool idtv_info_valid
;
8616 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8618 if (cpu_has_virtual_nmis()) {
8619 if (vmx
->nmi_known_unmasked
)
8622 * Can't use vmx->exit_intr_info since we're not sure what
8623 * the exit reason is.
8625 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8626 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8627 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8629 * SDM 3: 27.7.1.2 (September 2008)
8630 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8631 * a guest IRET fault.
8632 * SDM 3: 23.2.2 (September 2008)
8633 * Bit 12 is undefined in any of the following cases:
8634 * If the VM exit sets the valid bit in the IDT-vectoring
8635 * information field.
8636 * If the VM exit is due to a double fault.
8638 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8639 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8640 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8641 GUEST_INTR_STATE_NMI
);
8643 vmx
->nmi_known_unmasked
=
8644 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8645 & GUEST_INTR_STATE_NMI
);
8646 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8647 vmx
->vnmi_blocked_time
+=
8648 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8651 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8652 u32 idt_vectoring_info
,
8653 int instr_len_field
,
8654 int error_code_field
)
8658 bool idtv_info_valid
;
8660 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8662 vcpu
->arch
.nmi_injected
= false;
8663 kvm_clear_exception_queue(vcpu
);
8664 kvm_clear_interrupt_queue(vcpu
);
8666 if (!idtv_info_valid
)
8669 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8671 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8672 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8675 case INTR_TYPE_NMI_INTR
:
8676 vcpu
->arch
.nmi_injected
= true;
8678 * SDM 3: 27.7.1.2 (September 2008)
8679 * Clear bit "block by NMI" before VM entry if a NMI
8682 vmx_set_nmi_mask(vcpu
, false);
8684 case INTR_TYPE_SOFT_EXCEPTION
:
8685 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8687 case INTR_TYPE_HARD_EXCEPTION
:
8688 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8689 u32 err
= vmcs_read32(error_code_field
);
8690 kvm_requeue_exception_e(vcpu
, vector
, err
);
8692 kvm_requeue_exception(vcpu
, vector
);
8694 case INTR_TYPE_SOFT_INTR
:
8695 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8697 case INTR_TYPE_EXT_INTR
:
8698 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8705 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8707 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8708 VM_EXIT_INSTRUCTION_LEN
,
8709 IDT_VECTORING_ERROR_CODE
);
8712 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8714 __vmx_complete_interrupts(vcpu
,
8715 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8716 VM_ENTRY_INSTRUCTION_LEN
,
8717 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8722 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8725 struct perf_guest_switch_msr
*msrs
;
8727 msrs
= perf_guest_get_msrs(&nr_msrs
);
8732 for (i
= 0; i
< nr_msrs
; i
++)
8733 if (msrs
[i
].host
== msrs
[i
].guest
)
8734 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8736 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8740 void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8742 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8746 if (vmx
->hv_deadline_tsc
== -1)
8750 if (vmx
->hv_deadline_tsc
> tscl
)
8751 /* sure to be 32 bit only because checked on set_hv_timer */
8752 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8753 cpu_preemption_timer_multi
);
8757 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8760 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8763 unsigned long debugctlmsr
, cr4
;
8765 /* Record the guest's net vcpu time for enforced NMI injections. */
8766 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8767 vmx
->entry_time
= ktime_get();
8769 /* Don't enter VMX if guest state is invalid, let the exit handler
8770 start emulation until we arrive back to a valid state */
8771 if (vmx
->emulation_required
)
8774 if (vmx
->ple_window_dirty
) {
8775 vmx
->ple_window_dirty
= false;
8776 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8779 if (vmx
->nested
.sync_shadow_vmcs
) {
8780 copy_vmcs12_to_shadow(vmx
);
8781 vmx
->nested
.sync_shadow_vmcs
= false;
8784 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8785 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8786 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8787 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8789 cr4
= cr4_read_shadow();
8790 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8791 vmcs_writel(HOST_CR4
, cr4
);
8792 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8795 /* When single-stepping over STI and MOV SS, we must clear the
8796 * corresponding interruptibility bits in the guest state. Otherwise
8797 * vmentry fails as it then expects bit 14 (BS) in pending debug
8798 * exceptions being set, but that's not correct for the guest debugging
8800 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8801 vmx_set_interrupt_shadow(vcpu
, 0);
8803 if (vmx
->guest_pkru_valid
)
8804 __write_pkru(vmx
->guest_pkru
);
8806 atomic_switch_perf_msrs(vmx
);
8807 debugctlmsr
= get_debugctlmsr();
8809 vmx_arm_hv_timer(vcpu
);
8811 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8813 /* Store host registers */
8814 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8815 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8816 "push %%" _ASM_CX
" \n\t"
8817 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8819 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8820 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8822 /* Reload cr2 if changed */
8823 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8824 "mov %%cr2, %%" _ASM_DX
" \n\t"
8825 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8827 "mov %%" _ASM_AX
", %%cr2 \n\t"
8829 /* Check if vmlaunch of vmresume is needed */
8830 "cmpl $0, %c[launched](%0) \n\t"
8831 /* Load guest registers. Don't clobber flags. */
8832 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8833 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8834 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8835 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8836 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8837 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8838 #ifdef CONFIG_X86_64
8839 "mov %c[r8](%0), %%r8 \n\t"
8840 "mov %c[r9](%0), %%r9 \n\t"
8841 "mov %c[r10](%0), %%r10 \n\t"
8842 "mov %c[r11](%0), %%r11 \n\t"
8843 "mov %c[r12](%0), %%r12 \n\t"
8844 "mov %c[r13](%0), %%r13 \n\t"
8845 "mov %c[r14](%0), %%r14 \n\t"
8846 "mov %c[r15](%0), %%r15 \n\t"
8848 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8850 /* Enter guest mode */
8852 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8854 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8856 /* Save guest registers, load host registers, keep flags */
8857 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8859 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8860 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8861 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8862 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8863 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8864 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8865 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8866 #ifdef CONFIG_X86_64
8867 "mov %%r8, %c[r8](%0) \n\t"
8868 "mov %%r9, %c[r9](%0) \n\t"
8869 "mov %%r10, %c[r10](%0) \n\t"
8870 "mov %%r11, %c[r11](%0) \n\t"
8871 "mov %%r12, %c[r12](%0) \n\t"
8872 "mov %%r13, %c[r13](%0) \n\t"
8873 "mov %%r14, %c[r14](%0) \n\t"
8874 "mov %%r15, %c[r15](%0) \n\t"
8876 "mov %%cr2, %%" _ASM_AX
" \n\t"
8877 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8879 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8880 "setbe %c[fail](%0) \n\t"
8881 ".pushsection .rodata \n\t"
8882 ".global vmx_return \n\t"
8883 "vmx_return: " _ASM_PTR
" 2b \n\t"
8885 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8886 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8887 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8888 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8889 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8890 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8891 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8892 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8893 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8894 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8895 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8896 #ifdef CONFIG_X86_64
8897 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8898 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8899 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8900 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8901 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8902 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8903 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8904 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8906 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8907 [wordsize
]"i"(sizeof(ulong
))
8909 #ifdef CONFIG_X86_64
8910 , "rax", "rbx", "rdi", "rsi"
8911 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8913 , "eax", "ebx", "edi", "esi"
8917 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8919 update_debugctlmsr(debugctlmsr
);
8921 #ifndef CONFIG_X86_64
8923 * The sysexit path does not restore ds/es, so we must set them to
8924 * a reasonable value ourselves.
8926 * We can't defer this to vmx_load_host_state() since that function
8927 * may be executed in interrupt context, which saves and restore segments
8928 * around it, nullifying its effect.
8930 loadsegment(ds
, __USER_DS
);
8931 loadsegment(es
, __USER_DS
);
8934 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8935 | (1 << VCPU_EXREG_RFLAGS
)
8936 | (1 << VCPU_EXREG_PDPTR
)
8937 | (1 << VCPU_EXREG_SEGMENTS
)
8938 | (1 << VCPU_EXREG_CR3
));
8939 vcpu
->arch
.regs_dirty
= 0;
8941 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8943 vmx
->loaded_vmcs
->launched
= 1;
8945 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8948 * eager fpu is enabled if PKEY is supported and CR4 is switched
8949 * back on host, so it is safe to read guest PKRU from current
8952 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8953 vmx
->guest_pkru
= __read_pkru();
8954 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
8955 vmx
->guest_pkru_valid
= true;
8956 __write_pkru(vmx
->host_pkru
);
8958 vmx
->guest_pkru_valid
= false;
8962 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8963 * we did not inject a still-pending event to L1 now because of
8964 * nested_run_pending, we need to re-enable this bit.
8966 if (vmx
->nested
.nested_run_pending
)
8967 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8969 vmx
->nested
.nested_run_pending
= 0;
8971 vmx_complete_atomic_exit(vmx
);
8972 vmx_recover_nmi_blocking(vmx
);
8973 vmx_complete_interrupts(vmx
);
8976 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8978 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8981 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8985 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8987 vmx_vcpu_load(vcpu
, cpu
);
8992 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8994 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8997 vmx_destroy_pml_buffer(vmx
);
8998 free_vpid(vmx
->vpid
);
8999 leave_guest_mode(vcpu
);
9000 vmx_load_vmcs01(vcpu
);
9002 free_loaded_vmcs(vmx
->loaded_vmcs
);
9003 kfree(vmx
->guest_msrs
);
9004 kvm_vcpu_uninit(vcpu
);
9005 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9008 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9011 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9015 return ERR_PTR(-ENOMEM
);
9017 vmx
->vpid
= allocate_vpid();
9019 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9023 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9024 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9028 if (!vmx
->guest_msrs
) {
9032 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9033 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9034 if (!vmx
->loaded_vmcs
->vmcs
)
9037 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9038 loaded_vmcs_init(vmx
->loaded_vmcs
);
9043 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9044 vmx
->vcpu
.cpu
= cpu
;
9045 err
= vmx_vcpu_setup(vmx
);
9046 vmx_vcpu_put(&vmx
->vcpu
);
9050 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9051 err
= alloc_apic_access_page(kvm
);
9057 if (!kvm
->arch
.ept_identity_map_addr
)
9058 kvm
->arch
.ept_identity_map_addr
=
9059 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9060 err
= init_rmode_identity_map(kvm
);
9066 nested_vmx_setup_ctls_msrs(vmx
);
9067 vmx
->nested
.vpid02
= allocate_vpid();
9070 vmx
->nested
.posted_intr_nv
= -1;
9071 vmx
->nested
.current_vmptr
= -1ull;
9072 vmx
->nested
.current_vmcs12
= NULL
;
9075 * If PML is turned on, failure on enabling PML just results in failure
9076 * of creating the vcpu, therefore we can simplify PML logic (by
9077 * avoiding dealing with cases, such as enabling PML partially on vcpus
9078 * for the guest, etc.
9081 err
= vmx_create_pml_buffer(vmx
);
9086 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9091 free_vpid(vmx
->nested
.vpid02
);
9092 free_loaded_vmcs(vmx
->loaded_vmcs
);
9094 kfree(vmx
->guest_msrs
);
9096 kvm_vcpu_uninit(&vmx
->vcpu
);
9098 free_vpid(vmx
->vpid
);
9099 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9100 return ERR_PTR(err
);
9103 static void __init
vmx_check_processor_compat(void *rtn
)
9105 struct vmcs_config vmcs_conf
;
9108 if (setup_vmcs_config(&vmcs_conf
) < 0)
9110 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9111 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9112 smp_processor_id());
9117 static int get_ept_level(void)
9119 return VMX_EPT_DEFAULT_GAW
+ 1;
9122 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9127 /* For VT-d and EPT combination
9128 * 1. MMIO: always map as UC
9130 * a. VT-d without snooping control feature: can't guarantee the
9131 * result, try to trust guest.
9132 * b. VT-d with snooping control feature: snooping control feature of
9133 * VT-d engine can guarantee the cache correctness. Just set it
9134 * to WB to keep consistent with host. So the same as item 3.
9135 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9136 * consistent with host MTRR
9139 cache
= MTRR_TYPE_UNCACHABLE
;
9143 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9144 ipat
= VMX_EPT_IPAT_BIT
;
9145 cache
= MTRR_TYPE_WRBACK
;
9149 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9150 ipat
= VMX_EPT_IPAT_BIT
;
9151 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9152 cache
= MTRR_TYPE_WRBACK
;
9154 cache
= MTRR_TYPE_UNCACHABLE
;
9158 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9161 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9164 static int vmx_get_lpage_level(void)
9166 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9167 return PT_DIRECTORY_LEVEL
;
9169 /* For shadow and EPT supported 1GB page */
9170 return PT_PDPE_LEVEL
;
9173 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9176 * These bits in the secondary execution controls field
9177 * are dynamic, the others are mostly based on the hypervisor
9178 * architecture and the guest's CPUID. Do not touch the
9182 SECONDARY_EXEC_SHADOW_VMCS
|
9183 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9184 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9186 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9188 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9189 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9192 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9194 struct kvm_cpuid_entry2
*best
;
9195 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9196 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9198 if (vmx_rdtscp_supported()) {
9199 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9200 if (!rdtscp_enabled
)
9201 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9205 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9206 SECONDARY_EXEC_RDTSCP
;
9208 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9209 ~SECONDARY_EXEC_RDTSCP
;
9213 /* Exposing INVPCID only when PCID is exposed */
9214 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9215 if (vmx_invpcid_supported() &&
9216 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9217 !guest_cpuid_has_pcid(vcpu
))) {
9218 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9221 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9224 if (cpu_has_secondary_exec_ctrls())
9225 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9227 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
9228 if (guest_cpuid_has_pcommit(vcpu
))
9229 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9230 SECONDARY_EXEC_PCOMMIT
;
9232 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9233 ~SECONDARY_EXEC_PCOMMIT
;
9236 if (nested_vmx_allowed(vcpu
))
9237 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9238 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9240 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9241 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9244 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9246 if (func
== 1 && nested
)
9247 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9250 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9251 struct x86_exception
*fault
)
9253 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9256 if (fault
->error_code
& PFERR_RSVD_MASK
)
9257 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9259 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9260 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9261 vmcs12
->guest_physical_address
= fault
->address
;
9264 /* Callbacks for nested_ept_init_mmu_context: */
9266 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9268 /* return the page table to be shadowed - in our case, EPT12 */
9269 return get_vmcs12(vcpu
)->ept_pointer
;
9272 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9274 WARN_ON(mmu_is_nested(vcpu
));
9275 kvm_init_shadow_ept_mmu(vcpu
,
9276 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9277 VMX_EPT_EXECUTE_ONLY_BIT
);
9278 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9279 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9280 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9282 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9285 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9287 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9290 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9293 bool inequality
, bit
;
9295 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9297 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9298 vmcs12
->page_fault_error_code_match
;
9299 return inequality
^ bit
;
9302 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9303 struct x86_exception
*fault
)
9305 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9307 WARN_ON(!is_guest_mode(vcpu
));
9309 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9310 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9311 vmcs_read32(VM_EXIT_INTR_INFO
),
9312 vmcs_readl(EXIT_QUALIFICATION
));
9314 kvm_inject_page_fault(vcpu
, fault
);
9317 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9318 struct vmcs12
*vmcs12
)
9320 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9321 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9323 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9324 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9325 vmcs12
->apic_access_addr
>> maxphyaddr
)
9329 * Translate L1 physical address to host physical
9330 * address for vmcs02. Keep the page pinned, so this
9331 * physical address remains valid. We keep a reference
9332 * to it so we can release it later.
9334 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9335 nested_release_page(vmx
->nested
.apic_access_page
);
9336 vmx
->nested
.apic_access_page
=
9337 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9340 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9341 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9342 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9345 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9346 nested_release_page(vmx
->nested
.virtual_apic_page
);
9347 vmx
->nested
.virtual_apic_page
=
9348 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9351 * Failing the vm entry is _not_ what the processor does
9352 * but it's basically the only possibility we have.
9353 * We could still enter the guest if CR8 load exits are
9354 * enabled, CR8 store exits are enabled, and virtualize APIC
9355 * access is disabled; in this case the processor would never
9356 * use the TPR shadow and we could simply clear the bit from
9357 * the execution control. But such a configuration is useless,
9358 * so let's keep the code simple.
9360 if (!vmx
->nested
.virtual_apic_page
)
9364 if (nested_cpu_has_posted_intr(vmcs12
)) {
9365 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9366 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9369 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9370 kunmap(vmx
->nested
.pi_desc_page
);
9371 nested_release_page(vmx
->nested
.pi_desc_page
);
9373 vmx
->nested
.pi_desc_page
=
9374 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9375 if (!vmx
->nested
.pi_desc_page
)
9378 vmx
->nested
.pi_desc
=
9379 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9380 if (!vmx
->nested
.pi_desc
) {
9381 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9384 vmx
->nested
.pi_desc
=
9385 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9386 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9393 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9395 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9396 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9398 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9401 /* Make sure short timeouts reliably trigger an immediate vmexit.
9402 * hrtimer_start does not guarantee this. */
9403 if (preemption_timeout
<= 1) {
9404 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9408 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9409 preemption_timeout
*= 1000000;
9410 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9411 hrtimer_start(&vmx
->nested
.preemption_timer
,
9412 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9415 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9416 struct vmcs12
*vmcs12
)
9421 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9424 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9428 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9430 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9431 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9438 * Merge L0's and L1's MSR bitmap, return false to indicate that
9439 * we do not use the hardware.
9441 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9442 struct vmcs12
*vmcs12
)
9446 unsigned long *msr_bitmap
;
9448 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9451 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9456 msr_bitmap
= (unsigned long *)kmap(page
);
9458 nested_release_page_clean(page
);
9463 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9464 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9465 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9466 nested_vmx_disable_intercept_for_msr(
9468 vmx_msr_bitmap_nested
,
9470 /* TPR is allowed */
9471 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9472 vmx_msr_bitmap_nested
,
9473 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9474 MSR_TYPE_R
| MSR_TYPE_W
);
9475 if (nested_cpu_has_vid(vmcs12
)) {
9476 /* EOI and self-IPI are allowed */
9477 nested_vmx_disable_intercept_for_msr(
9479 vmx_msr_bitmap_nested
,
9480 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9482 nested_vmx_disable_intercept_for_msr(
9484 vmx_msr_bitmap_nested
,
9485 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9490 * Enable reading intercept of all the x2apic
9491 * MSRs. We should not rely on vmcs12 to do any
9492 * optimizations here, it may have been modified
9495 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9496 __vmx_enable_intercept_for_msr(
9497 vmx_msr_bitmap_nested
,
9501 __vmx_enable_intercept_for_msr(
9502 vmx_msr_bitmap_nested
,
9503 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9505 __vmx_enable_intercept_for_msr(
9506 vmx_msr_bitmap_nested
,
9507 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9509 __vmx_enable_intercept_for_msr(
9510 vmx_msr_bitmap_nested
,
9511 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9515 nested_release_page_clean(page
);
9520 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9521 struct vmcs12
*vmcs12
)
9523 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9524 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9525 !nested_cpu_has_vid(vmcs12
) &&
9526 !nested_cpu_has_posted_intr(vmcs12
))
9530 * If virtualize x2apic mode is enabled,
9531 * virtualize apic access must be disabled.
9533 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9534 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9538 * If virtual interrupt delivery is enabled,
9539 * we must exit on external interrupts.
9541 if (nested_cpu_has_vid(vmcs12
) &&
9542 !nested_exit_on_intr(vcpu
))
9546 * bits 15:8 should be zero in posted_intr_nv,
9547 * the descriptor address has been already checked
9548 * in nested_get_vmcs12_pages.
9550 if (nested_cpu_has_posted_intr(vmcs12
) &&
9551 (!nested_cpu_has_vid(vmcs12
) ||
9552 !nested_exit_intr_ack_set(vcpu
) ||
9553 vmcs12
->posted_intr_nv
& 0xff00))
9556 /* tpr shadow is needed by all apicv features. */
9557 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9563 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9564 unsigned long count_field
,
9565 unsigned long addr_field
)
9570 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9571 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9577 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9578 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9579 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9580 pr_warn_ratelimited(
9581 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9582 addr_field
, maxphyaddr
, count
, addr
);
9588 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9589 struct vmcs12
*vmcs12
)
9591 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9592 vmcs12
->vm_exit_msr_store_count
== 0 &&
9593 vmcs12
->vm_entry_msr_load_count
== 0)
9594 return 0; /* Fast path */
9595 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9596 VM_EXIT_MSR_LOAD_ADDR
) ||
9597 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9598 VM_EXIT_MSR_STORE_ADDR
) ||
9599 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9600 VM_ENTRY_MSR_LOAD_ADDR
))
9605 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9606 struct vmx_msr_entry
*e
)
9608 /* x2APIC MSR accesses are not allowed */
9609 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9611 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9612 e
->index
== MSR_IA32_UCODE_REV
)
9614 if (e
->reserved
!= 0)
9619 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9620 struct vmx_msr_entry
*e
)
9622 if (e
->index
== MSR_FS_BASE
||
9623 e
->index
== MSR_GS_BASE
||
9624 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9625 nested_vmx_msr_check_common(vcpu
, e
))
9630 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9631 struct vmx_msr_entry
*e
)
9633 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9634 nested_vmx_msr_check_common(vcpu
, e
))
9640 * Load guest's/host's msr at nested entry/exit.
9641 * return 0 for success, entry index for failure.
9643 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9646 struct vmx_msr_entry e
;
9647 struct msr_data msr
;
9649 msr
.host_initiated
= false;
9650 for (i
= 0; i
< count
; i
++) {
9651 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9653 pr_warn_ratelimited(
9654 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9655 __func__
, i
, gpa
+ i
* sizeof(e
));
9658 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9659 pr_warn_ratelimited(
9660 "%s check failed (%u, 0x%x, 0x%x)\n",
9661 __func__
, i
, e
.index
, e
.reserved
);
9664 msr
.index
= e
.index
;
9666 if (kvm_set_msr(vcpu
, &msr
)) {
9667 pr_warn_ratelimited(
9668 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9669 __func__
, i
, e
.index
, e
.value
);
9678 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9681 struct vmx_msr_entry e
;
9683 for (i
= 0; i
< count
; i
++) {
9684 struct msr_data msr_info
;
9685 if (kvm_vcpu_read_guest(vcpu
,
9686 gpa
+ i
* sizeof(e
),
9687 &e
, 2 * sizeof(u32
))) {
9688 pr_warn_ratelimited(
9689 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9690 __func__
, i
, gpa
+ i
* sizeof(e
));
9693 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9694 pr_warn_ratelimited(
9695 "%s check failed (%u, 0x%x, 0x%x)\n",
9696 __func__
, i
, e
.index
, e
.reserved
);
9699 msr_info
.host_initiated
= false;
9700 msr_info
.index
= e
.index
;
9701 if (kvm_get_msr(vcpu
, &msr_info
)) {
9702 pr_warn_ratelimited(
9703 "%s cannot read MSR (%u, 0x%x)\n",
9704 __func__
, i
, e
.index
);
9707 if (kvm_vcpu_write_guest(vcpu
,
9708 gpa
+ i
* sizeof(e
) +
9709 offsetof(struct vmx_msr_entry
, value
),
9710 &msr_info
.data
, sizeof(msr_info
.data
))) {
9711 pr_warn_ratelimited(
9712 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9713 __func__
, i
, e
.index
, msr_info
.data
);
9721 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9722 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9723 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9724 * guest in a way that will both be appropriate to L1's requests, and our
9725 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9726 * function also has additional necessary side-effects, like setting various
9727 * vcpu->arch fields.
9729 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9731 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9734 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9735 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9736 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9737 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9738 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9739 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9740 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9741 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9742 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9743 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9744 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9745 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9746 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9747 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9748 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9749 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9750 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9751 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9752 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9753 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9754 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9755 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9756 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9757 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9758 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9759 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9760 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9761 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9762 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9763 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9764 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9765 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9766 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9767 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9768 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9769 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9771 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9772 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9773 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9775 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9776 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9778 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9779 vmcs12
->vm_entry_intr_info_field
);
9780 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9781 vmcs12
->vm_entry_exception_error_code
);
9782 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9783 vmcs12
->vm_entry_instruction_len
);
9784 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9785 vmcs12
->guest_interruptibility_info
);
9786 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9787 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9788 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9789 vmcs12
->guest_pending_dbg_exceptions
);
9790 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9791 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9793 if (nested_cpu_has_xsaves(vmcs12
))
9794 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9795 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9797 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9798 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9799 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9801 if (nested_cpu_has_posted_intr(vmcs12
)) {
9803 * Note that we use L0's vector here and in
9804 * vmx_deliver_nested_posted_interrupt.
9806 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9807 vmx
->nested
.pi_pending
= false;
9808 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9809 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9810 page_to_phys(vmx
->nested
.pi_desc_page
) +
9811 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9814 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9816 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9818 vmx
->nested
.preemption_timer_expired
= false;
9819 if (nested_cpu_has_preemption_timer(vmcs12
))
9820 vmx_start_preemption_timer(vcpu
);
9823 * Whether page-faults are trapped is determined by a combination of
9824 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9825 * If enable_ept, L0 doesn't care about page faults and we should
9826 * set all of these to L1's desires. However, if !enable_ept, L0 does
9827 * care about (at least some) page faults, and because it is not easy
9828 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9829 * to exit on each and every L2 page fault. This is done by setting
9830 * MASK=MATCH=0 and (see below) EB.PF=1.
9831 * Note that below we don't need special code to set EB.PF beyond the
9832 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9833 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9834 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9836 * A problem with this approach (when !enable_ept) is that L1 may be
9837 * injected with more page faults than it asked for. This could have
9838 * caused problems, but in practice existing hypervisors don't care.
9839 * To fix this, we will need to emulate the PFEC checking (on the L1
9840 * page tables), using walk_addr(), when injecting PFs to L1.
9842 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9843 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9844 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9845 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9847 if (cpu_has_secondary_exec_ctrls()) {
9848 exec_control
= vmx_secondary_exec_control(vmx
);
9850 /* Take the following fields only from vmcs12 */
9851 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9852 SECONDARY_EXEC_RDTSCP
|
9853 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9854 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9855 SECONDARY_EXEC_PCOMMIT
);
9856 if (nested_cpu_has(vmcs12
,
9857 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9858 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9860 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9862 * If translation failed, no matter: This feature asks
9863 * to exit when accessing the given address, and if it
9864 * can never be accessed, this feature won't do
9867 if (!vmx
->nested
.apic_access_page
)
9869 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9871 vmcs_write64(APIC_ACCESS_ADDR
,
9872 page_to_phys(vmx
->nested
.apic_access_page
));
9873 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9874 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9876 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9877 kvm_vcpu_reload_apic_access_page(vcpu
);
9880 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9881 vmcs_write64(EOI_EXIT_BITMAP0
,
9882 vmcs12
->eoi_exit_bitmap0
);
9883 vmcs_write64(EOI_EXIT_BITMAP1
,
9884 vmcs12
->eoi_exit_bitmap1
);
9885 vmcs_write64(EOI_EXIT_BITMAP2
,
9886 vmcs12
->eoi_exit_bitmap2
);
9887 vmcs_write64(EOI_EXIT_BITMAP3
,
9888 vmcs12
->eoi_exit_bitmap3
);
9889 vmcs_write16(GUEST_INTR_STATUS
,
9890 vmcs12
->guest_intr_status
);
9893 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9898 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9899 * Some constant fields are set here by vmx_set_constant_host_state().
9900 * Other fields are different per CPU, and will be set later when
9901 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9903 vmx_set_constant_host_state(vmx
);
9906 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9907 * entry, but only if the current (host) sp changed from the value
9908 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9909 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9910 * here we just force the write to happen on entry.
9914 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9915 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9916 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9917 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9918 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9920 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9921 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9922 page_to_phys(vmx
->nested
.virtual_apic_page
));
9923 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9926 if (cpu_has_vmx_msr_bitmap() &&
9927 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9928 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9929 /* MSR_BITMAP will be set by following vmx_set_efer. */
9931 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9934 * Merging of IO bitmap not currently supported.
9935 * Rather, exit every time.
9937 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9938 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9940 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9942 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9943 * bitwise-or of what L1 wants to trap for L2, and what we want to
9944 * trap. Note that CR0.TS also needs updating - we do this later.
9946 update_exception_bitmap(vcpu
);
9947 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9948 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9950 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9951 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9952 * bits are further modified by vmx_set_efer() below.
9954 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9956 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9957 * emulated by vmx_set_efer(), below.
9959 vm_entry_controls_init(vmx
,
9960 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9961 ~VM_ENTRY_IA32E_MODE
) |
9962 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9964 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9965 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9966 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9967 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9968 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9971 set_cr4_guest_host_mask(vmx
);
9973 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9974 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9976 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9977 vmcs_write64(TSC_OFFSET
,
9978 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9980 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9984 * There is no direct mapping between vpid02 and vpid12, the
9985 * vpid02 is per-vCPU for L0 and reused while the value of
9986 * vpid12 is changed w/ one invvpid during nested vmentry.
9987 * The vpid12 is allocated by L1 for L2, so it will not
9988 * influence global bitmap(for vpid01 and vpid02 allocation)
9989 * even if spawn a lot of nested vCPUs.
9991 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9992 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9993 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9994 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9995 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9998 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9999 vmx_flush_tlb(vcpu
);
10004 if (nested_cpu_has_ept(vmcs12
)) {
10005 kvm_mmu_unload(vcpu
);
10006 nested_ept_init_mmu_context(vcpu
);
10009 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
10010 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10011 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10012 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10014 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10015 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10016 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10019 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10020 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10021 * The CR0_READ_SHADOW is what L2 should have expected to read given
10022 * the specifications by L1; It's not enough to take
10023 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10024 * have more bits than L1 expected.
10026 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10027 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10029 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10030 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10032 /* shadow page tables on either EPT or shadow page tables */
10033 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
10034 kvm_mmu_reset_context(vcpu
);
10037 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10040 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10043 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10044 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10045 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10046 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10049 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10050 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10054 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10055 * for running an L2 nested guest.
10057 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10059 struct vmcs12
*vmcs12
;
10060 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10062 struct loaded_vmcs
*vmcs02
;
10066 if (!nested_vmx_check_permission(vcpu
) ||
10067 !nested_vmx_check_vmcs12(vcpu
))
10070 skip_emulated_instruction(vcpu
);
10071 vmcs12
= get_vmcs12(vcpu
);
10073 if (enable_shadow_vmcs
)
10074 copy_shadow_to_vmcs12(vmx
);
10077 * The nested entry process starts with enforcing various prerequisites
10078 * on vmcs12 as required by the Intel SDM, and act appropriately when
10079 * they fail: As the SDM explains, some conditions should cause the
10080 * instruction to fail, while others will cause the instruction to seem
10081 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10082 * To speed up the normal (success) code path, we should avoid checking
10083 * for misconfigurations which will anyway be caught by the processor
10084 * when using the merged vmcs02.
10086 if (vmcs12
->launch_state
== launch
) {
10087 nested_vmx_failValid(vcpu
,
10088 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10089 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10093 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10094 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
10095 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10099 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
10100 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10104 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
10105 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10109 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
10110 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10114 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
10115 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10119 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10120 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
10121 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10122 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10123 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10124 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10125 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10126 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10127 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10128 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10129 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
10130 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10131 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10132 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
10133 vmx
->nested
.nested_vmx_entry_ctls_high
))
10135 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10139 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
10140 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10141 nested_vmx_failValid(vcpu
,
10142 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
10146 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10147 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10148 nested_vmx_entry_failure(vcpu
, vmcs12
,
10149 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10152 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
10153 nested_vmx_entry_failure(vcpu
, vmcs12
,
10154 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
10159 * If the load IA32_EFER VM-entry control is 1, the following checks
10160 * are performed on the field for the IA32_EFER MSR:
10161 * - Bits reserved in the IA32_EFER MSR must be 0.
10162 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10163 * the IA-32e mode guest VM-exit control. It must also be identical
10164 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10167 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10168 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10169 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10170 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10171 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10172 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10173 nested_vmx_entry_failure(vcpu
, vmcs12
,
10174 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10180 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10181 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10182 * the values of the LMA and LME bits in the field must each be that of
10183 * the host address-space size VM-exit control.
10185 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10186 ia32e
= (vmcs12
->vm_exit_controls
&
10187 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10188 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10189 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10190 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10191 nested_vmx_entry_failure(vcpu
, vmcs12
,
10192 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10198 * We're finally done with prerequisite checking, and can start with
10199 * the nested entry.
10202 vmcs02
= nested_get_current_vmcs02(vmx
);
10206 enter_guest_mode(vcpu
);
10208 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
10210 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10211 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10214 vmx
->loaded_vmcs
= vmcs02
;
10215 vmx_vcpu_put(vcpu
);
10216 vmx_vcpu_load(vcpu
, cpu
);
10220 vmx_segment_cache_clear(vmx
);
10222 prepare_vmcs02(vcpu
, vmcs12
);
10224 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10225 vmcs12
->vm_entry_msr_load_addr
,
10226 vmcs12
->vm_entry_msr_load_count
);
10227 if (msr_entry_idx
) {
10228 leave_guest_mode(vcpu
);
10229 vmx_load_vmcs01(vcpu
);
10230 nested_vmx_entry_failure(vcpu
, vmcs12
,
10231 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10235 vmcs12
->launch_state
= 1;
10237 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10238 return kvm_vcpu_halt(vcpu
);
10240 vmx
->nested
.nested_run_pending
= 1;
10243 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10244 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10245 * returned as far as L1 is concerned. It will only return (and set
10246 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10252 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10253 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10254 * This function returns the new value we should put in vmcs12.guest_cr0.
10255 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10256 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10257 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10258 * didn't trap the bit, because if L1 did, so would L0).
10259 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10260 * been modified by L2, and L1 knows it. So just leave the old value of
10261 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10262 * isn't relevant, because if L0 traps this bit it can set it to anything.
10263 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10264 * changed these bits, and therefore they need to be updated, but L0
10265 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10266 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10268 static inline unsigned long
10269 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10272 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10273 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10274 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10275 vcpu
->arch
.cr0_guest_owned_bits
));
10278 static inline unsigned long
10279 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10282 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10283 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10284 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10285 vcpu
->arch
.cr4_guest_owned_bits
));
10288 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10289 struct vmcs12
*vmcs12
)
10294 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10295 nr
= vcpu
->arch
.exception
.nr
;
10296 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10298 if (kvm_exception_is_soft(nr
)) {
10299 vmcs12
->vm_exit_instruction_len
=
10300 vcpu
->arch
.event_exit_inst_len
;
10301 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10303 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10305 if (vcpu
->arch
.exception
.has_error_code
) {
10306 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10307 vmcs12
->idt_vectoring_error_code
=
10308 vcpu
->arch
.exception
.error_code
;
10311 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10312 } else if (vcpu
->arch
.nmi_injected
) {
10313 vmcs12
->idt_vectoring_info_field
=
10314 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10315 } else if (vcpu
->arch
.interrupt
.pending
) {
10316 nr
= vcpu
->arch
.interrupt
.nr
;
10317 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10319 if (vcpu
->arch
.interrupt
.soft
) {
10320 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10321 vmcs12
->vm_entry_instruction_len
=
10322 vcpu
->arch
.event_exit_inst_len
;
10324 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10326 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10330 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10334 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10335 vmx
->nested
.preemption_timer_expired
) {
10336 if (vmx
->nested
.nested_run_pending
)
10338 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10342 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10343 if (vmx
->nested
.nested_run_pending
||
10344 vcpu
->arch
.interrupt
.pending
)
10346 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10347 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10348 INTR_INFO_VALID_MASK
, 0);
10350 * The NMI-triggered VM exit counts as injection:
10351 * clear this one and block further NMIs.
10353 vcpu
->arch
.nmi_pending
= 0;
10354 vmx_set_nmi_mask(vcpu
, true);
10358 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10359 nested_exit_on_intr(vcpu
)) {
10360 if (vmx
->nested
.nested_run_pending
)
10362 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10366 return vmx_complete_nested_posted_interrupt(vcpu
);
10369 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10371 ktime_t remaining
=
10372 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10375 if (ktime_to_ns(remaining
) <= 0)
10378 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10379 do_div(value
, 1000000);
10380 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10384 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10385 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10386 * and this function updates it to reflect the changes to the guest state while
10387 * L2 was running (and perhaps made some exits which were handled directly by L0
10388 * without going back to L1), and to reflect the exit reason.
10389 * Note that we do not have to copy here all VMCS fields, just those that
10390 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10391 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10392 * which already writes to vmcs12 directly.
10394 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10395 u32 exit_reason
, u32 exit_intr_info
,
10396 unsigned long exit_qualification
)
10398 /* update guest state fields: */
10399 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10400 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10402 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10403 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10404 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10406 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10407 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10408 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10409 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10410 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10411 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10412 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10413 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10414 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10415 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10416 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10417 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10418 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10419 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10420 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10421 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10422 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10423 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10424 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10425 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10426 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10427 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10428 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10429 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10430 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10431 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10432 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10433 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10434 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10435 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10436 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10437 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10438 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10439 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10440 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10441 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10443 vmcs12
->guest_interruptibility_info
=
10444 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10445 vmcs12
->guest_pending_dbg_exceptions
=
10446 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10447 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10448 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10450 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10452 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10453 if (vmcs12
->vm_exit_controls
&
10454 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10455 vmcs12
->vmx_preemption_timer_value
=
10456 vmx_get_preemption_timer_value(vcpu
);
10457 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10461 * In some cases (usually, nested EPT), L2 is allowed to change its
10462 * own CR3 without exiting. If it has changed it, we must keep it.
10463 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10464 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10466 * Additionally, restore L2's PDPTR to vmcs12.
10469 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10470 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10471 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10472 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10473 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10476 if (nested_cpu_has_vid(vmcs12
))
10477 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10479 vmcs12
->vm_entry_controls
=
10480 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10481 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10483 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10484 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10485 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10488 /* TODO: These cannot have changed unless we have MSR bitmaps and
10489 * the relevant bit asks not to trap the change */
10490 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10491 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10492 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10493 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10494 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10495 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10496 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10497 if (kvm_mpx_supported())
10498 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10499 if (nested_cpu_has_xsaves(vmcs12
))
10500 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10502 /* update exit information fields: */
10504 vmcs12
->vm_exit_reason
= exit_reason
;
10505 vmcs12
->exit_qualification
= exit_qualification
;
10507 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10508 if ((vmcs12
->vm_exit_intr_info
&
10509 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10510 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10511 vmcs12
->vm_exit_intr_error_code
=
10512 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10513 vmcs12
->idt_vectoring_info_field
= 0;
10514 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10515 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10517 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10518 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10519 * instead of reading the real value. */
10520 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10523 * Transfer the event that L0 or L1 may wanted to inject into
10524 * L2 to IDT_VECTORING_INFO_FIELD.
10526 vmcs12_save_pending_event(vcpu
, vmcs12
);
10530 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10531 * preserved above and would only end up incorrectly in L1.
10533 vcpu
->arch
.nmi_injected
= false;
10534 kvm_clear_exception_queue(vcpu
);
10535 kvm_clear_interrupt_queue(vcpu
);
10539 * A part of what we need to when the nested L2 guest exits and we want to
10540 * run its L1 parent, is to reset L1's guest state to the host state specified
10542 * This function is to be called not only on normal nested exit, but also on
10543 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10544 * Failures During or After Loading Guest State").
10545 * This function should be called when the active VMCS is L1's (vmcs01).
10547 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10548 struct vmcs12
*vmcs12
)
10550 struct kvm_segment seg
;
10552 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10553 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10554 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10555 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10557 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10558 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10560 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10561 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10562 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10564 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10565 * actually changed, because it depends on the current state of
10566 * fpu_active (which may have changed).
10567 * Note that vmx_set_cr0 refers to efer set above.
10569 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10571 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10572 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10573 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10575 update_exception_bitmap(vcpu
);
10576 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10577 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10580 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10581 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10583 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10584 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10586 nested_ept_uninit_mmu_context(vcpu
);
10588 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10589 kvm_mmu_reset_context(vcpu
);
10592 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10596 * Trivially support vpid by letting L2s share their parent
10597 * L1's vpid. TODO: move to a more elaborate solution, giving
10598 * each L2 its own vpid and exposing the vpid feature to L1.
10600 vmx_flush_tlb(vcpu
);
10604 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10605 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10606 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10607 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10608 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10610 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10611 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10612 vmcs_write64(GUEST_BNDCFGS
, 0);
10614 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10615 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10616 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10618 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10619 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10620 vmcs12
->host_ia32_perf_global_ctrl
);
10622 /* Set L1 segment info according to Intel SDM
10623 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10624 seg
= (struct kvm_segment
) {
10626 .limit
= 0xFFFFFFFF,
10627 .selector
= vmcs12
->host_cs_selector
,
10633 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10637 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10638 seg
= (struct kvm_segment
) {
10640 .limit
= 0xFFFFFFFF,
10647 seg
.selector
= vmcs12
->host_ds_selector
;
10648 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10649 seg
.selector
= vmcs12
->host_es_selector
;
10650 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10651 seg
.selector
= vmcs12
->host_ss_selector
;
10652 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10653 seg
.selector
= vmcs12
->host_fs_selector
;
10654 seg
.base
= vmcs12
->host_fs_base
;
10655 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10656 seg
.selector
= vmcs12
->host_gs_selector
;
10657 seg
.base
= vmcs12
->host_gs_base
;
10658 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10659 seg
= (struct kvm_segment
) {
10660 .base
= vmcs12
->host_tr_base
,
10662 .selector
= vmcs12
->host_tr_selector
,
10666 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10668 kvm_set_dr(vcpu
, 7, 0x400);
10669 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10671 if (cpu_has_vmx_msr_bitmap())
10672 vmx_set_msr_bitmap(vcpu
);
10674 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10675 vmcs12
->vm_exit_msr_load_count
))
10676 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10680 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10681 * and modify vmcs12 to make it see what it would expect to see there if
10682 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10684 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10685 u32 exit_intr_info
,
10686 unsigned long exit_qualification
)
10688 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10689 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10691 /* trying to cancel vmlaunch/vmresume is a bug */
10692 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10694 leave_guest_mode(vcpu
);
10695 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10696 exit_qualification
);
10698 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10699 vmcs12
->vm_exit_msr_store_count
))
10700 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10702 vmx_load_vmcs01(vcpu
);
10704 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10705 && nested_exit_intr_ack_set(vcpu
)) {
10706 int irq
= kvm_cpu_get_interrupt(vcpu
);
10708 vmcs12
->vm_exit_intr_info
= irq
|
10709 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10712 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10713 vmcs12
->exit_qualification
,
10714 vmcs12
->idt_vectoring_info_field
,
10715 vmcs12
->vm_exit_intr_info
,
10716 vmcs12
->vm_exit_intr_error_code
,
10719 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10720 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10721 vmx_segment_cache_clear(vmx
);
10723 /* if no vmcs02 cache requested, remove the one we used */
10724 if (VMCS02_POOL_SIZE
== 0)
10725 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10727 load_vmcs12_host_state(vcpu
, vmcs12
);
10729 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10730 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10732 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10735 /* Unpin physical memory we referred to in vmcs02 */
10736 if (vmx
->nested
.apic_access_page
) {
10737 nested_release_page(vmx
->nested
.apic_access_page
);
10738 vmx
->nested
.apic_access_page
= NULL
;
10740 if (vmx
->nested
.virtual_apic_page
) {
10741 nested_release_page(vmx
->nested
.virtual_apic_page
);
10742 vmx
->nested
.virtual_apic_page
= NULL
;
10744 if (vmx
->nested
.pi_desc_page
) {
10745 kunmap(vmx
->nested
.pi_desc_page
);
10746 nested_release_page(vmx
->nested
.pi_desc_page
);
10747 vmx
->nested
.pi_desc_page
= NULL
;
10748 vmx
->nested
.pi_desc
= NULL
;
10752 * We are now running in L2, mmu_notifier will force to reload the
10753 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10755 kvm_vcpu_reload_apic_access_page(vcpu
);
10758 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10759 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10760 * success or failure flag accordingly.
10762 if (unlikely(vmx
->fail
)) {
10764 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10766 nested_vmx_succeed(vcpu
);
10767 if (enable_shadow_vmcs
)
10768 vmx
->nested
.sync_shadow_vmcs
= true;
10770 /* in case we halted in L2 */
10771 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10775 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10777 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10779 if (is_guest_mode(vcpu
))
10780 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10781 free_nested(to_vmx(vcpu
));
10785 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10786 * 23.7 "VM-entry failures during or after loading guest state" (this also
10787 * lists the acceptable exit-reason and exit-qualification parameters).
10788 * It should only be called before L2 actually succeeded to run, and when
10789 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10791 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10792 struct vmcs12
*vmcs12
,
10793 u32 reason
, unsigned long qualification
)
10795 load_vmcs12_host_state(vcpu
, vmcs12
);
10796 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10797 vmcs12
->exit_qualification
= qualification
;
10798 nested_vmx_succeed(vcpu
);
10799 if (enable_shadow_vmcs
)
10800 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10803 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10804 struct x86_instruction_info
*info
,
10805 enum x86_intercept_stage stage
)
10807 return X86EMUL_CONTINUE
;
10810 #ifdef CONFIG_X86_64
10811 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10812 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
10813 u64 divisor
, u64
*result
)
10815 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
10817 /* To avoid the overflow on divq */
10818 if (high
>= divisor
)
10821 /* Low hold the result, high hold rem which is discarded */
10822 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
10823 "rm" (divisor
), "0" (low
), "1" (high
));
10829 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
10831 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10832 u64 tscl
= rdtsc();
10833 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
10834 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
10836 /* Convert to host delta tsc if tsc scaling is enabled */
10837 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
10838 u64_shl_div_u64(delta_tsc
,
10839 kvm_tsc_scaling_ratio_frac_bits
,
10840 vcpu
->arch
.tsc_scaling_ratio
,
10845 * If the delta tsc can't fit in the 32 bit after the multi shift,
10846 * we can't use the preemption timer.
10847 * It's possible that it fits on later vmentries, but checking
10848 * on every vmentry is costly so we just use an hrtimer.
10850 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
10853 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
10854 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10855 PIN_BASED_VMX_PREEMPTION_TIMER
);
10859 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
10861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10862 vmx
->hv_deadline_tsc
= -1;
10863 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10864 PIN_BASED_VMX_PREEMPTION_TIMER
);
10868 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10871 shrink_ple_window(vcpu
);
10874 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10875 struct kvm_memory_slot
*slot
)
10877 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10878 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10881 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10882 struct kvm_memory_slot
*slot
)
10884 kvm_mmu_slot_set_dirty(kvm
, slot
);
10887 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10889 kvm_flush_pml_buffers(kvm
);
10892 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10893 struct kvm_memory_slot
*memslot
,
10894 gfn_t offset
, unsigned long mask
)
10896 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10900 * This routine does the following things for vCPU which is going
10901 * to be blocked if VT-d PI is enabled.
10902 * - Store the vCPU to the wakeup list, so when interrupts happen
10903 * we can find the right vCPU to wake up.
10904 * - Change the Posted-interrupt descriptor as below:
10905 * 'NDST' <-- vcpu->pre_pcpu
10906 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10907 * - If 'ON' is set during this process, which means at least one
10908 * interrupt is posted for this vCPU, we cannot block it, in
10909 * this case, return 1, otherwise, return 0.
10912 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
10914 unsigned long flags
;
10916 struct pi_desc old
, new;
10917 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10919 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10920 !irq_remapping_cap(IRQ_POSTING_CAP
))
10923 vcpu
->pre_pcpu
= vcpu
->cpu
;
10924 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10925 vcpu
->pre_pcpu
), flags
);
10926 list_add_tail(&vcpu
->blocked_vcpu_list
,
10927 &per_cpu(blocked_vcpu_on_cpu
,
10929 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10930 vcpu
->pre_pcpu
), flags
);
10933 old
.control
= new.control
= pi_desc
->control
;
10936 * We should not block the vCPU if
10937 * an interrupt is posted for it.
10939 if (pi_test_on(pi_desc
) == 1) {
10940 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10941 vcpu
->pre_pcpu
), flags
);
10942 list_del(&vcpu
->blocked_vcpu_list
);
10943 spin_unlock_irqrestore(
10944 &per_cpu(blocked_vcpu_on_cpu_lock
,
10945 vcpu
->pre_pcpu
), flags
);
10946 vcpu
->pre_pcpu
= -1;
10951 WARN((pi_desc
->sn
== 1),
10952 "Warning: SN field of posted-interrupts "
10953 "is set before blocking\n");
10956 * Since vCPU can be preempted during this process,
10957 * vcpu->cpu could be different with pre_pcpu, we
10958 * need to set pre_pcpu as the destination of wakeup
10959 * notification event, then we can find the right vCPU
10960 * to wakeup in wakeup handler if interrupts happen
10961 * when the vCPU is in blocked state.
10963 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10965 if (x2apic_enabled())
10968 new.ndst
= (dest
<< 8) & 0xFF00;
10970 /* set 'NV' to 'wakeup vector' */
10971 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10972 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10973 new.control
) != old
.control
);
10978 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10980 if (pi_pre_block(vcpu
))
10983 if (kvm_lapic_hv_timer_in_use(vcpu
))
10984 kvm_lapic_switch_to_sw_timer(vcpu
);
10989 static void pi_post_block(struct kvm_vcpu
*vcpu
)
10991 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10992 struct pi_desc old
, new;
10994 unsigned long flags
;
10996 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10997 !irq_remapping_cap(IRQ_POSTING_CAP
))
11001 old
.control
= new.control
= pi_desc
->control
;
11003 dest
= cpu_physical_id(vcpu
->cpu
);
11005 if (x2apic_enabled())
11008 new.ndst
= (dest
<< 8) & 0xFF00;
11010 /* Allow posting non-urgent interrupts */
11013 /* set 'NV' to 'notification vector' */
11014 new.nv
= POSTED_INTR_VECTOR
;
11015 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11016 new.control
) != old
.control
);
11018 if(vcpu
->pre_pcpu
!= -1) {
11020 &per_cpu(blocked_vcpu_on_cpu_lock
,
11021 vcpu
->pre_pcpu
), flags
);
11022 list_del(&vcpu
->blocked_vcpu_list
);
11023 spin_unlock_irqrestore(
11024 &per_cpu(blocked_vcpu_on_cpu_lock
,
11025 vcpu
->pre_pcpu
), flags
);
11026 vcpu
->pre_pcpu
= -1;
11030 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11032 if (kvm_x86_ops
->set_hv_timer
)
11033 kvm_lapic_switch_to_hv_timer(vcpu
);
11035 pi_post_block(vcpu
);
11039 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11042 * @host_irq: host irq of the interrupt
11043 * @guest_irq: gsi of the interrupt
11044 * @set: set or unset PI
11045 * returns 0 on success, < 0 on failure
11047 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11048 uint32_t guest_irq
, bool set
)
11050 struct kvm_kernel_irq_routing_entry
*e
;
11051 struct kvm_irq_routing_table
*irq_rt
;
11052 struct kvm_lapic_irq irq
;
11053 struct kvm_vcpu
*vcpu
;
11054 struct vcpu_data vcpu_info
;
11055 int idx
, ret
= -EINVAL
;
11057 if (!kvm_arch_has_assigned_device(kvm
) ||
11058 !irq_remapping_cap(IRQ_POSTING_CAP
))
11061 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11062 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11063 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11065 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11066 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11069 * VT-d PI cannot support posting multicast/broadcast
11070 * interrupts to a vCPU, we still use interrupt remapping
11071 * for these kind of interrupts.
11073 * For lowest-priority interrupts, we only support
11074 * those with single CPU as the destination, e.g. user
11075 * configures the interrupts via /proc/irq or uses
11076 * irqbalance to make the interrupts single-CPU.
11078 * We will support full lowest-priority interrupt later.
11081 kvm_set_msi_irq(e
, &irq
);
11082 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11084 * Make sure the IRTE is in remapped mode if
11085 * we don't handle it in posted mode.
11087 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11090 "failed to back to remapped mode, irq: %u\n",
11098 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11099 vcpu_info
.vector
= irq
.vector
;
11101 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11102 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11105 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11107 /* suppress notification event before unposting */
11108 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11109 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11110 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11114 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11122 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11126 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11128 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11129 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11130 FEATURE_CONTROL_LMCE
;
11132 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11133 ~FEATURE_CONTROL_LMCE
;
11136 static struct kvm_x86_ops vmx_x86_ops
= {
11137 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11138 .disabled_by_bios
= vmx_disabled_by_bios
,
11139 .hardware_setup
= hardware_setup
,
11140 .hardware_unsetup
= hardware_unsetup
,
11141 .check_processor_compatibility
= vmx_check_processor_compat
,
11142 .hardware_enable
= hardware_enable
,
11143 .hardware_disable
= hardware_disable
,
11144 .cpu_has_accelerated_tpr
= report_flexpriority
,
11145 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11147 .vcpu_create
= vmx_create_vcpu
,
11148 .vcpu_free
= vmx_free_vcpu
,
11149 .vcpu_reset
= vmx_vcpu_reset
,
11151 .prepare_guest_switch
= vmx_save_host_state
,
11152 .vcpu_load
= vmx_vcpu_load
,
11153 .vcpu_put
= vmx_vcpu_put
,
11155 .update_bp_intercept
= update_exception_bitmap
,
11156 .get_msr
= vmx_get_msr
,
11157 .set_msr
= vmx_set_msr
,
11158 .get_segment_base
= vmx_get_segment_base
,
11159 .get_segment
= vmx_get_segment
,
11160 .set_segment
= vmx_set_segment
,
11161 .get_cpl
= vmx_get_cpl
,
11162 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11163 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11164 .decache_cr3
= vmx_decache_cr3
,
11165 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11166 .set_cr0
= vmx_set_cr0
,
11167 .set_cr3
= vmx_set_cr3
,
11168 .set_cr4
= vmx_set_cr4
,
11169 .set_efer
= vmx_set_efer
,
11170 .get_idt
= vmx_get_idt
,
11171 .set_idt
= vmx_set_idt
,
11172 .get_gdt
= vmx_get_gdt
,
11173 .set_gdt
= vmx_set_gdt
,
11174 .get_dr6
= vmx_get_dr6
,
11175 .set_dr6
= vmx_set_dr6
,
11176 .set_dr7
= vmx_set_dr7
,
11177 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11178 .cache_reg
= vmx_cache_reg
,
11179 .get_rflags
= vmx_get_rflags
,
11180 .set_rflags
= vmx_set_rflags
,
11182 .get_pkru
= vmx_get_pkru
,
11184 .fpu_activate
= vmx_fpu_activate
,
11185 .fpu_deactivate
= vmx_fpu_deactivate
,
11187 .tlb_flush
= vmx_flush_tlb
,
11189 .run
= vmx_vcpu_run
,
11190 .handle_exit
= vmx_handle_exit
,
11191 .skip_emulated_instruction
= skip_emulated_instruction
,
11192 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11193 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11194 .patch_hypercall
= vmx_patch_hypercall
,
11195 .set_irq
= vmx_inject_irq
,
11196 .set_nmi
= vmx_inject_nmi
,
11197 .queue_exception
= vmx_queue_exception
,
11198 .cancel_injection
= vmx_cancel_injection
,
11199 .interrupt_allowed
= vmx_interrupt_allowed
,
11200 .nmi_allowed
= vmx_nmi_allowed
,
11201 .get_nmi_mask
= vmx_get_nmi_mask
,
11202 .set_nmi_mask
= vmx_set_nmi_mask
,
11203 .enable_nmi_window
= enable_nmi_window
,
11204 .enable_irq_window
= enable_irq_window
,
11205 .update_cr8_intercept
= update_cr8_intercept
,
11206 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11207 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11208 .get_enable_apicv
= vmx_get_enable_apicv
,
11209 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11210 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11211 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11212 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11213 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11214 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11216 .set_tss_addr
= vmx_set_tss_addr
,
11217 .get_tdp_level
= get_ept_level
,
11218 .get_mt_mask
= vmx_get_mt_mask
,
11220 .get_exit_info
= vmx_get_exit_info
,
11222 .get_lpage_level
= vmx_get_lpage_level
,
11224 .cpuid_update
= vmx_cpuid_update
,
11226 .rdtscp_supported
= vmx_rdtscp_supported
,
11227 .invpcid_supported
= vmx_invpcid_supported
,
11229 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11231 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11233 .read_tsc_offset
= vmx_read_tsc_offset
,
11234 .write_tsc_offset
= vmx_write_tsc_offset
,
11235 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
11236 .read_l1_tsc
= vmx_read_l1_tsc
,
11238 .set_tdp_cr3
= vmx_set_cr3
,
11240 .check_intercept
= vmx_check_intercept
,
11241 .handle_external_intr
= vmx_handle_external_intr
,
11242 .mpx_supported
= vmx_mpx_supported
,
11243 .xsaves_supported
= vmx_xsaves_supported
,
11245 .check_nested_events
= vmx_check_nested_events
,
11247 .sched_in
= vmx_sched_in
,
11249 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11250 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11251 .flush_log_dirty
= vmx_flush_log_dirty
,
11252 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11254 .pre_block
= vmx_pre_block
,
11255 .post_block
= vmx_post_block
,
11257 .pmu_ops
= &intel_pmu_ops
,
11259 .update_pi_irte
= vmx_update_pi_irte
,
11261 #ifdef CONFIG_X86_64
11262 .set_hv_timer
= vmx_set_hv_timer
,
11263 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11266 .setup_mce
= vmx_setup_mce
,
11269 static int __init
vmx_init(void)
11271 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11272 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11276 #ifdef CONFIG_KEXEC_CORE
11277 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11278 crash_vmclear_local_loaded_vmcss
);
11284 static void __exit
vmx_exit(void)
11286 #ifdef CONFIG_KEXEC_CORE
11287 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11294 module_init(vmx_init
)
11295 module_exit(vmx_exit
)