2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf
= 1;
53 module_param(bypass_guest_pf
, bool, S_IRUGO
);
55 static int __read_mostly enable_vpid
= 1;
56 module_param_named(vpid
, enable_vpid
, bool, 0444);
58 static int __read_mostly flexpriority_enabled
= 1;
59 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
61 static int __read_mostly enable_ept
= 1;
62 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
64 static int __read_mostly enable_unrestricted_guest
= 1;
65 module_param_named(unrestricted_guest
,
66 enable_unrestricted_guest
, bool, S_IRUGO
);
68 static int __read_mostly emulate_invalid_guest_state
= 0;
69 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
71 static int __read_mostly vmm_exclusive
= 1;
72 module_param(vmm_exclusive
, bool, S_IRUGO
);
74 static int __read_mostly yield_on_hlt
= 1;
75 module_param(yield_on_hlt
, bool, S_IRUGO
);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested
= 0;
83 module_param(nested
, bool, S_IRUGO
);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
116 module_param(ple_gap
, int, S_IRUGO
);
118 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
119 module_param(ple_window
, int, S_IRUGO
);
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
139 struct list_head loaded_vmcss_on_cpu_link
;
142 struct shared_msr_entry
{
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 typedef u64 natural_width
;
162 struct __packed vmcs12
{
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
169 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding
[7]; /* room for future expansion */
175 u64 vm_exit_msr_store_addr
;
176 u64 vm_exit_msr_load_addr
;
177 u64 vm_entry_msr_load_addr
;
179 u64 virtual_apic_page_addr
;
180 u64 apic_access_addr
;
182 u64 guest_physical_address
;
183 u64 vmcs_link_pointer
;
184 u64 guest_ia32_debugctl
;
187 u64 guest_ia32_perf_global_ctrl
;
194 u64 host_ia32_perf_global_ctrl
;
195 u64 padding64
[8]; /* room for future expansion */
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
202 natural_width cr0_guest_host_mask
;
203 natural_width cr4_guest_host_mask
;
204 natural_width cr0_read_shadow
;
205 natural_width cr4_read_shadow
;
206 natural_width cr3_target_value0
;
207 natural_width cr3_target_value1
;
208 natural_width cr3_target_value2
;
209 natural_width cr3_target_value3
;
210 natural_width exit_qualification
;
211 natural_width guest_linear_address
;
212 natural_width guest_cr0
;
213 natural_width guest_cr3
;
214 natural_width guest_cr4
;
215 natural_width guest_es_base
;
216 natural_width guest_cs_base
;
217 natural_width guest_ss_base
;
218 natural_width guest_ds_base
;
219 natural_width guest_fs_base
;
220 natural_width guest_gs_base
;
221 natural_width guest_ldtr_base
;
222 natural_width guest_tr_base
;
223 natural_width guest_gdtr_base
;
224 natural_width guest_idtr_base
;
225 natural_width guest_dr7
;
226 natural_width guest_rsp
;
227 natural_width guest_rip
;
228 natural_width guest_rflags
;
229 natural_width guest_pending_dbg_exceptions
;
230 natural_width guest_sysenter_esp
;
231 natural_width guest_sysenter_eip
;
232 natural_width host_cr0
;
233 natural_width host_cr3
;
234 natural_width host_cr4
;
235 natural_width host_fs_base
;
236 natural_width host_gs_base
;
237 natural_width host_tr_base
;
238 natural_width host_gdtr_base
;
239 natural_width host_idtr_base
;
240 natural_width host_ia32_sysenter_esp
;
241 natural_width host_ia32_sysenter_eip
;
242 natural_width host_rsp
;
243 natural_width host_rip
;
244 natural_width paddingl
[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control
;
246 u32 cpu_based_vm_exec_control
;
247 u32 exception_bitmap
;
248 u32 page_fault_error_code_mask
;
249 u32 page_fault_error_code_match
;
250 u32 cr3_target_count
;
251 u32 vm_exit_controls
;
252 u32 vm_exit_msr_store_count
;
253 u32 vm_exit_msr_load_count
;
254 u32 vm_entry_controls
;
255 u32 vm_entry_msr_load_count
;
256 u32 vm_entry_intr_info_field
;
257 u32 vm_entry_exception_error_code
;
258 u32 vm_entry_instruction_len
;
260 u32 secondary_vm_exec_control
;
261 u32 vm_instruction_error
;
263 u32 vm_exit_intr_info
;
264 u32 vm_exit_intr_error_code
;
265 u32 idt_vectoring_info_field
;
266 u32 idt_vectoring_error_code
;
267 u32 vm_exit_instruction_len
;
268 u32 vmx_instruction_info
;
275 u32 guest_ldtr_limit
;
277 u32 guest_gdtr_limit
;
278 u32 guest_idtr_limit
;
279 u32 guest_es_ar_bytes
;
280 u32 guest_cs_ar_bytes
;
281 u32 guest_ss_ar_bytes
;
282 u32 guest_ds_ar_bytes
;
283 u32 guest_fs_ar_bytes
;
284 u32 guest_gs_ar_bytes
;
285 u32 guest_ldtr_ar_bytes
;
286 u32 guest_tr_ar_bytes
;
287 u32 guest_interruptibility_info
;
288 u32 guest_activity_state
;
289 u32 guest_sysenter_cs
;
290 u32 host_ia32_sysenter_cs
;
291 u32 padding32
[8]; /* room for future expansion */
292 u16 virtual_processor_id
;
293 u16 guest_es_selector
;
294 u16 guest_cs_selector
;
295 u16 guest_ss_selector
;
296 u16 guest_ds_selector
;
297 u16 guest_fs_selector
;
298 u16 guest_gs_selector
;
299 u16 guest_ldtr_selector
;
300 u16 guest_tr_selector
;
301 u16 host_es_selector
;
302 u16 host_cs_selector
;
303 u16 host_ss_selector
;
304 u16 host_ds_selector
;
305 u16 host_fs_selector
;
306 u16 host_gs_selector
;
307 u16 host_tr_selector
;
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 #define VMCS12_REVISION 0x11e57ed0
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
322 #define VMCS12_SIZE 0x1000
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct list_head list
;
328 struct loaded_vmcs vmcs02
;
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 /* Has the level1 guest done vmxon? */
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 /* The host-usable pointer to the above */
342 struct page
*current_vmcs12_page
;
343 struct vmcs12
*current_vmcs12
;
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool
;
351 struct kvm_vcpu vcpu
;
352 unsigned long host_rsp
;
355 bool nmi_known_unmasked
;
357 u32 idt_vectoring_info
;
359 struct shared_msr_entry
*guest_msrs
;
363 u64 msr_host_kernel_gs_base
;
364 u64 msr_guest_kernel_gs_base
;
367 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
368 * non-nested (L1) guest, it always points to vmcs01. For a nested
369 * guest (L2), it points to a different VMCS.
371 struct loaded_vmcs vmcs01
;
372 struct loaded_vmcs
*loaded_vmcs
;
373 bool __launched
; /* temporary, used in vmx_vcpu_run */
374 struct msr_autoload
{
376 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
377 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
381 u16 fs_sel
, gs_sel
, ldt_sel
;
382 int gs_ldt_reload_needed
;
383 int fs_reload_needed
;
388 struct kvm_save_segment
{
393 } tr
, es
, ds
, fs
, gs
;
396 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
397 struct kvm_save_segment seg
[8];
400 bool emulation_required
;
402 /* Support for vnmi-less CPUs */
403 int soft_vnmi_blocked
;
405 s64 vnmi_blocked_time
;
410 /* Support for a guest hypervisor (nested VMX) */
411 struct nested_vmx nested
;
414 enum segment_cache_field
{
423 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
425 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
428 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
429 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
430 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
431 [number##_HIGH] = VMCS12_OFFSET(name)+4
433 static unsigned short vmcs_field_to_offset_table
[] = {
434 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
435 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
436 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
437 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
438 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
439 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
440 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
441 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
442 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
443 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
444 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
445 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
446 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
447 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
448 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
449 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
450 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
451 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
452 FIELD64(MSR_BITMAP
, msr_bitmap
),
453 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
454 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
455 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
456 FIELD64(TSC_OFFSET
, tsc_offset
),
457 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
458 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
459 FIELD64(EPT_POINTER
, ept_pointer
),
460 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
461 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
462 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
463 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
464 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
465 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
466 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
467 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
468 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
469 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
470 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
471 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
472 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
473 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
474 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
475 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
476 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
477 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
478 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
479 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
480 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
481 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
482 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
483 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
484 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
485 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
486 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
487 FIELD(TPR_THRESHOLD
, tpr_threshold
),
488 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
489 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
490 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
491 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
492 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
493 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
494 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
495 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
496 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
497 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
498 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
499 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
500 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
501 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
502 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
503 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
504 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
505 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
506 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
507 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
508 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
509 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
510 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
511 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
512 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
513 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
514 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
515 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
516 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
517 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
518 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
519 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
520 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
521 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
522 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
523 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
524 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
525 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
526 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
527 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
528 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
529 FIELD(GUEST_CR0
, guest_cr0
),
530 FIELD(GUEST_CR3
, guest_cr3
),
531 FIELD(GUEST_CR4
, guest_cr4
),
532 FIELD(GUEST_ES_BASE
, guest_es_base
),
533 FIELD(GUEST_CS_BASE
, guest_cs_base
),
534 FIELD(GUEST_SS_BASE
, guest_ss_base
),
535 FIELD(GUEST_DS_BASE
, guest_ds_base
),
536 FIELD(GUEST_FS_BASE
, guest_fs_base
),
537 FIELD(GUEST_GS_BASE
, guest_gs_base
),
538 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
539 FIELD(GUEST_TR_BASE
, guest_tr_base
),
540 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
541 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
542 FIELD(GUEST_DR7
, guest_dr7
),
543 FIELD(GUEST_RSP
, guest_rsp
),
544 FIELD(GUEST_RIP
, guest_rip
),
545 FIELD(GUEST_RFLAGS
, guest_rflags
),
546 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
547 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
548 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
549 FIELD(HOST_CR0
, host_cr0
),
550 FIELD(HOST_CR3
, host_cr3
),
551 FIELD(HOST_CR4
, host_cr4
),
552 FIELD(HOST_FS_BASE
, host_fs_base
),
553 FIELD(HOST_GS_BASE
, host_gs_base
),
554 FIELD(HOST_TR_BASE
, host_tr_base
),
555 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
556 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
557 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
558 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
559 FIELD(HOST_RSP
, host_rsp
),
560 FIELD(HOST_RIP
, host_rip
),
562 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
564 static inline short vmcs_field_to_offset(unsigned long field
)
566 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
568 return vmcs_field_to_offset_table
[field
];
571 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
573 return to_vmx(vcpu
)->nested
.current_vmcs12
;
576 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
578 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
579 if (is_error_page(page
)) {
580 kvm_release_page_clean(page
);
586 static void nested_release_page(struct page
*page
)
588 kvm_release_page_dirty(page
);
591 static void nested_release_page_clean(struct page
*page
)
593 kvm_release_page_clean(page
);
596 static u64
construct_eptp(unsigned long root_hpa
);
597 static void kvm_cpu_vmxon(u64 addr
);
598 static void kvm_cpu_vmxoff(void);
599 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
600 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
602 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
603 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
605 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
606 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
608 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
609 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
611 static unsigned long *vmx_io_bitmap_a
;
612 static unsigned long *vmx_io_bitmap_b
;
613 static unsigned long *vmx_msr_bitmap_legacy
;
614 static unsigned long *vmx_msr_bitmap_longmode
;
616 static bool cpu_has_load_ia32_efer
;
618 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
619 static DEFINE_SPINLOCK(vmx_vpid_lock
);
621 static struct vmcs_config
{
625 u32 pin_based_exec_ctrl
;
626 u32 cpu_based_exec_ctrl
;
627 u32 cpu_based_2nd_exec_ctrl
;
632 static struct vmx_capability
{
637 #define VMX_SEGMENT_FIELD(seg) \
638 [VCPU_SREG_##seg] = { \
639 .selector = GUEST_##seg##_SELECTOR, \
640 .base = GUEST_##seg##_BASE, \
641 .limit = GUEST_##seg##_LIMIT, \
642 .ar_bytes = GUEST_##seg##_AR_BYTES, \
645 static struct kvm_vmx_segment_field
{
650 } kvm_vmx_segment_fields
[] = {
651 VMX_SEGMENT_FIELD(CS
),
652 VMX_SEGMENT_FIELD(DS
),
653 VMX_SEGMENT_FIELD(ES
),
654 VMX_SEGMENT_FIELD(FS
),
655 VMX_SEGMENT_FIELD(GS
),
656 VMX_SEGMENT_FIELD(SS
),
657 VMX_SEGMENT_FIELD(TR
),
658 VMX_SEGMENT_FIELD(LDTR
),
661 static u64 host_efer
;
663 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
666 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
667 * away by decrementing the array size.
669 static const u32 vmx_msr_index
[] = {
671 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
673 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
675 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
677 static inline bool is_page_fault(u32 intr_info
)
679 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
680 INTR_INFO_VALID_MASK
)) ==
681 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
684 static inline bool is_no_device(u32 intr_info
)
686 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
687 INTR_INFO_VALID_MASK
)) ==
688 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
691 static inline bool is_invalid_opcode(u32 intr_info
)
693 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
694 INTR_INFO_VALID_MASK
)) ==
695 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
698 static inline bool is_external_interrupt(u32 intr_info
)
700 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
701 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
704 static inline bool is_machine_check(u32 intr_info
)
706 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
707 INTR_INFO_VALID_MASK
)) ==
708 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
711 static inline bool cpu_has_vmx_msr_bitmap(void)
713 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
716 static inline bool cpu_has_vmx_tpr_shadow(void)
718 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
721 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
723 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
726 static inline bool cpu_has_secondary_exec_ctrls(void)
728 return vmcs_config
.cpu_based_exec_ctrl
&
729 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
732 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
734 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
735 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
738 static inline bool cpu_has_vmx_flexpriority(void)
740 return cpu_has_vmx_tpr_shadow() &&
741 cpu_has_vmx_virtualize_apic_accesses();
744 static inline bool cpu_has_vmx_ept_execute_only(void)
746 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
749 static inline bool cpu_has_vmx_eptp_uncacheable(void)
751 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
754 static inline bool cpu_has_vmx_eptp_writeback(void)
756 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
759 static inline bool cpu_has_vmx_ept_2m_page(void)
761 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
764 static inline bool cpu_has_vmx_ept_1g_page(void)
766 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
769 static inline bool cpu_has_vmx_ept_4levels(void)
771 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
774 static inline bool cpu_has_vmx_invept_individual_addr(void)
776 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
779 static inline bool cpu_has_vmx_invept_context(void)
781 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
784 static inline bool cpu_has_vmx_invept_global(void)
786 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
789 static inline bool cpu_has_vmx_invvpid_single(void)
791 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
794 static inline bool cpu_has_vmx_invvpid_global(void)
796 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
799 static inline bool cpu_has_vmx_ept(void)
801 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
802 SECONDARY_EXEC_ENABLE_EPT
;
805 static inline bool cpu_has_vmx_unrestricted_guest(void)
807 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
808 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
811 static inline bool cpu_has_vmx_ple(void)
813 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
814 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
817 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
819 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
822 static inline bool cpu_has_vmx_vpid(void)
824 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
825 SECONDARY_EXEC_ENABLE_VPID
;
828 static inline bool cpu_has_vmx_rdtscp(void)
830 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
831 SECONDARY_EXEC_RDTSCP
;
834 static inline bool cpu_has_virtual_nmis(void)
836 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
839 static inline bool cpu_has_vmx_wbinvd_exit(void)
841 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
842 SECONDARY_EXEC_WBINVD_EXITING
;
845 static inline bool report_flexpriority(void)
847 return flexpriority_enabled
;
850 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
854 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
855 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
860 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
866 } operand
= { vpid
, 0, gva
};
868 asm volatile (__ex(ASM_VMX_INVVPID
)
869 /* CF==1 or ZF==1 --> rc = -1 */
871 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
874 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
878 } operand
= {eptp
, gpa
};
880 asm volatile (__ex(ASM_VMX_INVEPT
)
881 /* CF==1 or ZF==1 --> rc = -1 */
882 "; ja 1f ; ud2 ; 1:\n"
883 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
886 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
890 i
= __find_msr_index(vmx
, msr
);
892 return &vmx
->guest_msrs
[i
];
896 static void vmcs_clear(struct vmcs
*vmcs
)
898 u64 phys_addr
= __pa(vmcs
);
901 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
902 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
905 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
909 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
911 vmcs_clear(loaded_vmcs
->vmcs
);
912 loaded_vmcs
->cpu
= -1;
913 loaded_vmcs
->launched
= 0;
916 static void vmcs_load(struct vmcs
*vmcs
)
918 u64 phys_addr
= __pa(vmcs
);
921 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
922 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
925 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
929 static void __loaded_vmcs_clear(void *arg
)
931 struct loaded_vmcs
*loaded_vmcs
= arg
;
932 int cpu
= raw_smp_processor_id();
934 if (loaded_vmcs
->cpu
!= cpu
)
935 return; /* vcpu migration can race with cpu offline */
936 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
937 per_cpu(current_vmcs
, cpu
) = NULL
;
938 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
939 loaded_vmcs_init(loaded_vmcs
);
942 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
944 if (loaded_vmcs
->cpu
!= -1)
945 smp_call_function_single(
946 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
949 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
954 if (cpu_has_vmx_invvpid_single())
955 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
958 static inline void vpid_sync_vcpu_global(void)
960 if (cpu_has_vmx_invvpid_global())
961 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
964 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
966 if (cpu_has_vmx_invvpid_single())
967 vpid_sync_vcpu_single(vmx
);
969 vpid_sync_vcpu_global();
972 static inline void ept_sync_global(void)
974 if (cpu_has_vmx_invept_global())
975 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
978 static inline void ept_sync_context(u64 eptp
)
981 if (cpu_has_vmx_invept_context())
982 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
988 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
991 if (cpu_has_vmx_invept_individual_addr())
992 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
995 ept_sync_context(eptp
);
999 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1001 unsigned long value
;
1003 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1004 : "=a"(value
) : "d"(field
) : "cc");
1008 static __always_inline u16
vmcs_read16(unsigned long field
)
1010 return vmcs_readl(field
);
1013 static __always_inline u32
vmcs_read32(unsigned long field
)
1015 return vmcs_readl(field
);
1018 static __always_inline u64
vmcs_read64(unsigned long field
)
1020 #ifdef CONFIG_X86_64
1021 return vmcs_readl(field
);
1023 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1027 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1029 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1030 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1034 static void vmcs_writel(unsigned long field
, unsigned long value
)
1038 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1039 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1040 if (unlikely(error
))
1041 vmwrite_error(field
, value
);
1044 static void vmcs_write16(unsigned long field
, u16 value
)
1046 vmcs_writel(field
, value
);
1049 static void vmcs_write32(unsigned long field
, u32 value
)
1051 vmcs_writel(field
, value
);
1054 static void vmcs_write64(unsigned long field
, u64 value
)
1056 vmcs_writel(field
, value
);
1057 #ifndef CONFIG_X86_64
1059 vmcs_writel(field
+1, value
>> 32);
1063 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1065 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1068 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1070 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1073 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1075 vmx
->segment_cache
.bitmask
= 0;
1078 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1082 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1084 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1085 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1086 vmx
->segment_cache
.bitmask
= 0;
1088 ret
= vmx
->segment_cache
.bitmask
& mask
;
1089 vmx
->segment_cache
.bitmask
|= mask
;
1093 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1095 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1097 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1098 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1102 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1104 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1106 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1107 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1111 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1113 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1115 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1116 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1120 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1122 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1124 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1125 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1129 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1133 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1134 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1135 if ((vcpu
->guest_debug
&
1136 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1137 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1138 eb
|= 1u << BP_VECTOR
;
1139 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1142 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1143 if (vcpu
->fpu_active
)
1144 eb
&= ~(1u << NM_VECTOR
);
1145 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1148 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1151 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1153 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1154 vmcs_clear_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1155 vmcs_clear_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1159 for (i
= 0; i
< m
->nr
; ++i
)
1160 if (m
->guest
[i
].index
== msr
)
1166 m
->guest
[i
] = m
->guest
[m
->nr
];
1167 m
->host
[i
] = m
->host
[m
->nr
];
1168 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1169 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1172 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1173 u64 guest_val
, u64 host_val
)
1176 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1178 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1179 vmcs_write64(GUEST_IA32_EFER
, guest_val
);
1180 vmcs_write64(HOST_IA32_EFER
, host_val
);
1181 vmcs_set_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1182 vmcs_set_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1186 for (i
= 0; i
< m
->nr
; ++i
)
1187 if (m
->guest
[i
].index
== msr
)
1192 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1193 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1196 m
->guest
[i
].index
= msr
;
1197 m
->guest
[i
].value
= guest_val
;
1198 m
->host
[i
].index
= msr
;
1199 m
->host
[i
].value
= host_val
;
1202 static void reload_tss(void)
1205 * VT restores TR but not its size. Useless.
1207 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1208 struct desc_struct
*descs
;
1210 descs
= (void *)gdt
->address
;
1211 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1215 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1220 guest_efer
= vmx
->vcpu
.arch
.efer
;
1223 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1226 ignore_bits
= EFER_NX
| EFER_SCE
;
1227 #ifdef CONFIG_X86_64
1228 ignore_bits
|= EFER_LMA
| EFER_LME
;
1229 /* SCE is meaningful only in long mode on Intel */
1230 if (guest_efer
& EFER_LMA
)
1231 ignore_bits
&= ~(u64
)EFER_SCE
;
1233 guest_efer
&= ~ignore_bits
;
1234 guest_efer
|= host_efer
& ignore_bits
;
1235 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1236 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1238 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1239 /* On ept, can't emulate nx, and must switch nx atomically */
1240 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1241 guest_efer
= vmx
->vcpu
.arch
.efer
;
1242 if (!(guest_efer
& EFER_LMA
))
1243 guest_efer
&= ~EFER_LME
;
1244 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1251 static unsigned long segment_base(u16 selector
)
1253 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1254 struct desc_struct
*d
;
1255 unsigned long table_base
;
1258 if (!(selector
& ~3))
1261 table_base
= gdt
->address
;
1263 if (selector
& 4) { /* from ldt */
1264 u16 ldt_selector
= kvm_read_ldt();
1266 if (!(ldt_selector
& ~3))
1269 table_base
= segment_base(ldt_selector
);
1271 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1272 v
= get_desc_base(d
);
1273 #ifdef CONFIG_X86_64
1274 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1275 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1280 static inline unsigned long kvm_read_tr_base(void)
1283 asm("str %0" : "=g"(tr
));
1284 return segment_base(tr
);
1287 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1289 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1292 if (vmx
->host_state
.loaded
)
1295 vmx
->host_state
.loaded
= 1;
1297 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1298 * allow segment selectors with cpl > 0 or ti == 1.
1300 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1301 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1302 savesegment(fs
, vmx
->host_state
.fs_sel
);
1303 if (!(vmx
->host_state
.fs_sel
& 7)) {
1304 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1305 vmx
->host_state
.fs_reload_needed
= 0;
1307 vmcs_write16(HOST_FS_SELECTOR
, 0);
1308 vmx
->host_state
.fs_reload_needed
= 1;
1310 savesegment(gs
, vmx
->host_state
.gs_sel
);
1311 if (!(vmx
->host_state
.gs_sel
& 7))
1312 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1314 vmcs_write16(HOST_GS_SELECTOR
, 0);
1315 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1318 #ifdef CONFIG_X86_64
1319 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1320 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1322 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1323 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1326 #ifdef CONFIG_X86_64
1327 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1328 if (is_long_mode(&vmx
->vcpu
))
1329 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1331 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1332 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1333 vmx
->guest_msrs
[i
].data
,
1334 vmx
->guest_msrs
[i
].mask
);
1337 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1339 if (!vmx
->host_state
.loaded
)
1342 ++vmx
->vcpu
.stat
.host_state_reload
;
1343 vmx
->host_state
.loaded
= 0;
1344 #ifdef CONFIG_X86_64
1345 if (is_long_mode(&vmx
->vcpu
))
1346 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1348 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1349 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1350 #ifdef CONFIG_X86_64
1351 load_gs_index(vmx
->host_state
.gs_sel
);
1353 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1356 if (vmx
->host_state
.fs_reload_needed
)
1357 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1359 #ifdef CONFIG_X86_64
1360 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1362 if (current_thread_info()->status
& TS_USEDFPU
)
1364 load_gdt(&__get_cpu_var(host_gdt
));
1367 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1370 __vmx_load_host_state(vmx
);
1375 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1376 * vcpu mutex is already taken.
1378 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1380 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1381 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1384 kvm_cpu_vmxon(phys_addr
);
1385 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1386 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1388 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1389 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1390 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1393 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1394 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1395 unsigned long sysenter_esp
;
1397 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1398 local_irq_disable();
1399 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1400 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1404 * Linux uses per-cpu TSS and GDT, so set these when switching
1407 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1408 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1410 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1411 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1412 vmx
->loaded_vmcs
->cpu
= cpu
;
1416 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1418 __vmx_load_host_state(to_vmx(vcpu
));
1419 if (!vmm_exclusive
) {
1420 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1426 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1430 if (vcpu
->fpu_active
)
1432 vcpu
->fpu_active
= 1;
1433 cr0
= vmcs_readl(GUEST_CR0
);
1434 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1435 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1436 vmcs_writel(GUEST_CR0
, cr0
);
1437 update_exception_bitmap(vcpu
);
1438 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1439 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1442 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1444 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1446 vmx_decache_cr0_guest_bits(vcpu
);
1447 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1448 update_exception_bitmap(vcpu
);
1449 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1450 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1451 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1454 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1456 unsigned long rflags
, save_rflags
;
1458 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1459 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1460 rflags
= vmcs_readl(GUEST_RFLAGS
);
1461 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1462 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1463 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1464 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1466 to_vmx(vcpu
)->rflags
= rflags
;
1468 return to_vmx(vcpu
)->rflags
;
1471 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1473 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1474 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1475 to_vmx(vcpu
)->rflags
= rflags
;
1476 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1477 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1478 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1480 vmcs_writel(GUEST_RFLAGS
, rflags
);
1483 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1485 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1488 if (interruptibility
& GUEST_INTR_STATE_STI
)
1489 ret
|= KVM_X86_SHADOW_INT_STI
;
1490 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1491 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1496 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1498 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1499 u32 interruptibility
= interruptibility_old
;
1501 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1503 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1504 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1505 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1506 interruptibility
|= GUEST_INTR_STATE_STI
;
1508 if ((interruptibility
!= interruptibility_old
))
1509 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1512 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1516 rip
= kvm_rip_read(vcpu
);
1517 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1518 kvm_rip_write(vcpu
, rip
);
1520 /* skipping an emulated instruction also counts */
1521 vmx_set_interrupt_shadow(vcpu
, 0);
1524 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1526 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1527 * explicitly skip the instruction because if the HLT state is set, then
1528 * the instruction is already executing and RIP has already been
1530 if (!yield_on_hlt
&&
1531 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1532 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1535 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1536 bool has_error_code
, u32 error_code
,
1539 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1540 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1542 if (has_error_code
) {
1543 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1544 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1547 if (vmx
->rmode
.vm86_active
) {
1549 if (kvm_exception_is_soft(nr
))
1550 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1551 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1552 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1556 if (kvm_exception_is_soft(nr
)) {
1557 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1558 vmx
->vcpu
.arch
.event_exit_inst_len
);
1559 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1561 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1563 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1564 vmx_clear_hlt(vcpu
);
1567 static bool vmx_rdtscp_supported(void)
1569 return cpu_has_vmx_rdtscp();
1573 * Swap MSR entry in host/guest MSR entry array.
1575 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1577 struct shared_msr_entry tmp
;
1579 tmp
= vmx
->guest_msrs
[to
];
1580 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1581 vmx
->guest_msrs
[from
] = tmp
;
1585 * Set up the vmcs to automatically save and restore system
1586 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1587 * mode, as fiddling with msrs is very expensive.
1589 static void setup_msrs(struct vcpu_vmx
*vmx
)
1591 int save_nmsrs
, index
;
1592 unsigned long *msr_bitmap
;
1594 vmx_load_host_state(vmx
);
1596 #ifdef CONFIG_X86_64
1597 if (is_long_mode(&vmx
->vcpu
)) {
1598 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1600 move_msr_up(vmx
, index
, save_nmsrs
++);
1601 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1603 move_msr_up(vmx
, index
, save_nmsrs
++);
1604 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1606 move_msr_up(vmx
, index
, save_nmsrs
++);
1607 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1608 if (index
>= 0 && vmx
->rdtscp_enabled
)
1609 move_msr_up(vmx
, index
, save_nmsrs
++);
1611 * MSR_STAR is only needed on long mode guests, and only
1612 * if efer.sce is enabled.
1614 index
= __find_msr_index(vmx
, MSR_STAR
);
1615 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1616 move_msr_up(vmx
, index
, save_nmsrs
++);
1619 index
= __find_msr_index(vmx
, MSR_EFER
);
1620 if (index
>= 0 && update_transition_efer(vmx
, index
))
1621 move_msr_up(vmx
, index
, save_nmsrs
++);
1623 vmx
->save_nmsrs
= save_nmsrs
;
1625 if (cpu_has_vmx_msr_bitmap()) {
1626 if (is_long_mode(&vmx
->vcpu
))
1627 msr_bitmap
= vmx_msr_bitmap_longmode
;
1629 msr_bitmap
= vmx_msr_bitmap_legacy
;
1631 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1636 * reads and returns guest's timestamp counter "register"
1637 * guest_tsc = host_tsc + tsc_offset -- 21.3
1639 static u64
guest_read_tsc(void)
1641 u64 host_tsc
, tsc_offset
;
1644 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1645 return host_tsc
+ tsc_offset
;
1649 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1650 * ioctl. In this case the call-back should update internal vmx state to make
1651 * the changes effective.
1653 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
)
1655 /* Nothing to do here */
1659 * writes 'offset' into guest's timestamp counter offset register
1661 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1663 vmcs_write64(TSC_OFFSET
, offset
);
1666 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1668 u64 offset
= vmcs_read64(TSC_OFFSET
);
1669 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1672 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1674 return target_tsc
- native_read_tsc();
1677 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1679 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1680 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1684 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1685 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1686 * all guests if the "nested" module option is off, and can also be disabled
1687 * for a single guest by disabling its VMX cpuid bit.
1689 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1691 return nested
&& guest_cpuid_has_vmx(vcpu
);
1695 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1696 * returned for the various VMX controls MSRs when nested VMX is enabled.
1697 * The same values should also be used to verify that vmcs12 control fields are
1698 * valid during nested entry from L1 to L2.
1699 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1700 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1701 * bit in the high half is on if the corresponding bit in the control field
1702 * may be on. See also vmx_control_verify().
1703 * TODO: allow these variables to be modified (downgraded) by module options
1706 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1707 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1708 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1709 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1710 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1711 static __init
void nested_vmx_setup_ctls_msrs(void)
1714 * Note that as a general rule, the high half of the MSRs (bits in
1715 * the control fields which may be 1) should be initialized by the
1716 * intersection of the underlying hardware's MSR (i.e., features which
1717 * can be supported) and the list of features we want to expose -
1718 * because they are known to be properly supported in our code.
1719 * Also, usually, the low half of the MSRs (bits which must be 1) can
1720 * be set to 0, meaning that L1 may turn off any of these bits. The
1721 * reason is that if one of these bits is necessary, it will appear
1722 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1723 * fields of vmcs01 and vmcs02, will turn these bits off - and
1724 * nested_vmx_exit_handled() will not pass related exits to L1.
1725 * These rules have exceptions below.
1728 /* pin-based controls */
1730 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1731 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1733 nested_vmx_pinbased_ctls_low
= 0x16 ;
1734 nested_vmx_pinbased_ctls_high
= 0x16 |
1735 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1736 PIN_BASED_VIRTUAL_NMIS
;
1739 nested_vmx_exit_ctls_low
= 0;
1740 #ifdef CONFIG_X86_64
1741 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1743 nested_vmx_exit_ctls_high
= 0;
1746 /* entry controls */
1747 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1748 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1749 nested_vmx_entry_ctls_low
= 0;
1750 nested_vmx_entry_ctls_high
&=
1751 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1753 /* cpu-based controls */
1754 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1755 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1756 nested_vmx_procbased_ctls_low
= 0;
1757 nested_vmx_procbased_ctls_high
&=
1758 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1759 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1760 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1761 CPU_BASED_CR3_STORE_EXITING
|
1762 #ifdef CONFIG_X86_64
1763 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1765 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1766 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1767 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1769 * We can allow some features even when not supported by the
1770 * hardware. For example, L1 can specify an MSR bitmap - and we
1771 * can use it to avoid exits to L1 - even when L0 runs L2
1772 * without MSR bitmaps.
1774 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
1776 /* secondary cpu-based controls */
1777 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1778 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
1779 nested_vmx_secondary_ctls_low
= 0;
1780 nested_vmx_secondary_ctls_high
&=
1781 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1784 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
1787 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1789 return ((control
& high
) | low
) == control
;
1792 static inline u64
vmx_control_msr(u32 low
, u32 high
)
1794 return low
| ((u64
)high
<< 32);
1798 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1799 * also let it use VMX-specific MSRs.
1800 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1801 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1802 * like all other MSRs).
1804 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1806 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
1807 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
1809 * According to the spec, processors which do not support VMX
1810 * should throw a #GP(0) when VMX capability MSRs are read.
1812 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
1816 switch (msr_index
) {
1817 case MSR_IA32_FEATURE_CONTROL
:
1820 case MSR_IA32_VMX_BASIC
:
1822 * This MSR reports some information about VMX support. We
1823 * should return information about the VMX we emulate for the
1824 * guest, and the VMCS structure we give it - not about the
1825 * VMX support of the underlying hardware.
1827 *pdata
= VMCS12_REVISION
|
1828 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
1829 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
1831 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
1832 case MSR_IA32_VMX_PINBASED_CTLS
:
1833 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
1834 nested_vmx_pinbased_ctls_high
);
1836 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
1837 case MSR_IA32_VMX_PROCBASED_CTLS
:
1838 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
1839 nested_vmx_procbased_ctls_high
);
1841 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
1842 case MSR_IA32_VMX_EXIT_CTLS
:
1843 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
1844 nested_vmx_exit_ctls_high
);
1846 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
1847 case MSR_IA32_VMX_ENTRY_CTLS
:
1848 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
1849 nested_vmx_entry_ctls_high
);
1851 case MSR_IA32_VMX_MISC
:
1855 * These MSRs specify bits which the guest must keep fixed (on or off)
1856 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1857 * We picked the standard core2 setting.
1859 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1860 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1861 case MSR_IA32_VMX_CR0_FIXED0
:
1862 *pdata
= VMXON_CR0_ALWAYSON
;
1864 case MSR_IA32_VMX_CR0_FIXED1
:
1867 case MSR_IA32_VMX_CR4_FIXED0
:
1868 *pdata
= VMXON_CR4_ALWAYSON
;
1870 case MSR_IA32_VMX_CR4_FIXED1
:
1873 case MSR_IA32_VMX_VMCS_ENUM
:
1876 case MSR_IA32_VMX_PROCBASED_CTLS2
:
1877 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
1878 nested_vmx_secondary_ctls_high
);
1880 case MSR_IA32_VMX_EPT_VPID_CAP
:
1881 /* Currently, no nested ept or nested vpid */
1891 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1893 if (!nested_vmx_allowed(vcpu
))
1896 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
1897 /* TODO: the right thing. */
1900 * No need to treat VMX capability MSRs specially: If we don't handle
1901 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1907 * Reads an msr value (of 'msr_index') into 'pdata'.
1908 * Returns 0 on success, non-0 otherwise.
1909 * Assumes vcpu_load() was already called.
1911 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1914 struct shared_msr_entry
*msr
;
1917 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1921 switch (msr_index
) {
1922 #ifdef CONFIG_X86_64
1924 data
= vmcs_readl(GUEST_FS_BASE
);
1927 data
= vmcs_readl(GUEST_GS_BASE
);
1929 case MSR_KERNEL_GS_BASE
:
1930 vmx_load_host_state(to_vmx(vcpu
));
1931 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1935 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1937 data
= guest_read_tsc();
1939 case MSR_IA32_SYSENTER_CS
:
1940 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1942 case MSR_IA32_SYSENTER_EIP
:
1943 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1945 case MSR_IA32_SYSENTER_ESP
:
1946 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1949 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1951 /* Otherwise falls through */
1953 vmx_load_host_state(to_vmx(vcpu
));
1954 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
1956 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1958 vmx_load_host_state(to_vmx(vcpu
));
1962 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1970 * Writes msr value into into the appropriate "register".
1971 * Returns 0 on success, non-0 otherwise.
1972 * Assumes vcpu_load() was already called.
1974 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1976 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1977 struct shared_msr_entry
*msr
;
1980 switch (msr_index
) {
1982 vmx_load_host_state(vmx
);
1983 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1985 #ifdef CONFIG_X86_64
1987 vmx_segment_cache_clear(vmx
);
1988 vmcs_writel(GUEST_FS_BASE
, data
);
1991 vmx_segment_cache_clear(vmx
);
1992 vmcs_writel(GUEST_GS_BASE
, data
);
1994 case MSR_KERNEL_GS_BASE
:
1995 vmx_load_host_state(vmx
);
1996 vmx
->msr_guest_kernel_gs_base
= data
;
1999 case MSR_IA32_SYSENTER_CS
:
2000 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2002 case MSR_IA32_SYSENTER_EIP
:
2003 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2005 case MSR_IA32_SYSENTER_ESP
:
2006 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2009 kvm_write_tsc(vcpu
, data
);
2011 case MSR_IA32_CR_PAT
:
2012 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2013 vmcs_write64(GUEST_IA32_PAT
, data
);
2014 vcpu
->arch
.pat
= data
;
2017 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2020 if (!vmx
->rdtscp_enabled
)
2022 /* Check reserved bit, higher 32 bits should be zero */
2023 if ((data
>> 32) != 0)
2025 /* Otherwise falls through */
2027 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2029 msr
= find_msr_entry(vmx
, msr_index
);
2031 vmx_load_host_state(vmx
);
2035 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2041 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2043 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2046 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2049 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2051 case VCPU_EXREG_PDPTR
:
2053 ept_save_pdptrs(vcpu
);
2060 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
2062 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
2063 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
2065 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2067 update_exception_bitmap(vcpu
);
2070 static __init
int cpu_has_kvm_support(void)
2072 return cpu_has_vmx();
2075 static __init
int vmx_disabled_by_bios(void)
2079 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2080 if (msr
& FEATURE_CONTROL_LOCKED
) {
2081 /* launched w/ TXT and VMX disabled */
2082 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2085 /* launched w/o TXT and VMX only enabled w/ TXT */
2086 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2087 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2088 && !tboot_enabled()) {
2089 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2090 "activate TXT before enabling KVM\n");
2093 /* launched w/o TXT and VMX disabled */
2094 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2095 && !tboot_enabled())
2102 static void kvm_cpu_vmxon(u64 addr
)
2104 asm volatile (ASM_VMX_VMXON_RAX
2105 : : "a"(&addr
), "m"(addr
)
2109 static int hardware_enable(void *garbage
)
2111 int cpu
= raw_smp_processor_id();
2112 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2115 if (read_cr4() & X86_CR4_VMXE
)
2118 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2119 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2121 test_bits
= FEATURE_CONTROL_LOCKED
;
2122 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2123 if (tboot_enabled())
2124 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2126 if ((old
& test_bits
) != test_bits
) {
2127 /* enable and lock */
2128 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2130 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2132 if (vmm_exclusive
) {
2133 kvm_cpu_vmxon(phys_addr
);
2137 store_gdt(&__get_cpu_var(host_gdt
));
2142 static void vmclear_local_loaded_vmcss(void)
2144 int cpu
= raw_smp_processor_id();
2145 struct loaded_vmcs
*v
, *n
;
2147 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2148 loaded_vmcss_on_cpu_link
)
2149 __loaded_vmcs_clear(v
);
2153 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2156 static void kvm_cpu_vmxoff(void)
2158 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2161 static void hardware_disable(void *garbage
)
2163 if (vmm_exclusive
) {
2164 vmclear_local_loaded_vmcss();
2167 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2170 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2171 u32 msr
, u32
*result
)
2173 u32 vmx_msr_low
, vmx_msr_high
;
2174 u32 ctl
= ctl_min
| ctl_opt
;
2176 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2178 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2179 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2181 /* Ensure minimum (required) set of control bits are supported. */
2189 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2191 u32 vmx_msr_low
, vmx_msr_high
;
2193 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2194 return vmx_msr_high
& ctl
;
2197 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2199 u32 vmx_msr_low
, vmx_msr_high
;
2200 u32 min
, opt
, min2
, opt2
;
2201 u32 _pin_based_exec_control
= 0;
2202 u32 _cpu_based_exec_control
= 0;
2203 u32 _cpu_based_2nd_exec_control
= 0;
2204 u32 _vmexit_control
= 0;
2205 u32 _vmentry_control
= 0;
2207 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2208 opt
= PIN_BASED_VIRTUAL_NMIS
;
2209 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2210 &_pin_based_exec_control
) < 0)
2214 #ifdef CONFIG_X86_64
2215 CPU_BASED_CR8_LOAD_EXITING
|
2216 CPU_BASED_CR8_STORE_EXITING
|
2218 CPU_BASED_CR3_LOAD_EXITING
|
2219 CPU_BASED_CR3_STORE_EXITING
|
2220 CPU_BASED_USE_IO_BITMAPS
|
2221 CPU_BASED_MOV_DR_EXITING
|
2222 CPU_BASED_USE_TSC_OFFSETING
|
2223 CPU_BASED_MWAIT_EXITING
|
2224 CPU_BASED_MONITOR_EXITING
|
2225 CPU_BASED_INVLPG_EXITING
;
2228 min
|= CPU_BASED_HLT_EXITING
;
2230 opt
= CPU_BASED_TPR_SHADOW
|
2231 CPU_BASED_USE_MSR_BITMAPS
|
2232 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2233 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2234 &_cpu_based_exec_control
) < 0)
2236 #ifdef CONFIG_X86_64
2237 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2238 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2239 ~CPU_BASED_CR8_STORE_EXITING
;
2241 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2243 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2244 SECONDARY_EXEC_WBINVD_EXITING
|
2245 SECONDARY_EXEC_ENABLE_VPID
|
2246 SECONDARY_EXEC_ENABLE_EPT
|
2247 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2248 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2249 SECONDARY_EXEC_RDTSCP
;
2250 if (adjust_vmx_controls(min2
, opt2
,
2251 MSR_IA32_VMX_PROCBASED_CTLS2
,
2252 &_cpu_based_2nd_exec_control
) < 0)
2255 #ifndef CONFIG_X86_64
2256 if (!(_cpu_based_2nd_exec_control
&
2257 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2258 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2260 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2261 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2263 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2264 CPU_BASED_CR3_STORE_EXITING
|
2265 CPU_BASED_INVLPG_EXITING
);
2266 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2267 vmx_capability
.ept
, vmx_capability
.vpid
);
2271 #ifdef CONFIG_X86_64
2272 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2274 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2275 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2276 &_vmexit_control
) < 0)
2280 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2281 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2282 &_vmentry_control
) < 0)
2285 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2287 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2288 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2291 #ifdef CONFIG_X86_64
2292 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2293 if (vmx_msr_high
& (1u<<16))
2297 /* Require Write-Back (WB) memory type for VMCS accesses. */
2298 if (((vmx_msr_high
>> 18) & 15) != 6)
2301 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2302 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2303 vmcs_conf
->revision_id
= vmx_msr_low
;
2305 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2306 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2307 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2308 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2309 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2311 cpu_has_load_ia32_efer
=
2312 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2313 VM_ENTRY_LOAD_IA32_EFER
)
2314 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2315 VM_EXIT_LOAD_IA32_EFER
);
2320 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2322 int node
= cpu_to_node(cpu
);
2326 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2329 vmcs
= page_address(pages
);
2330 memset(vmcs
, 0, vmcs_config
.size
);
2331 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2335 static struct vmcs
*alloc_vmcs(void)
2337 return alloc_vmcs_cpu(raw_smp_processor_id());
2340 static void free_vmcs(struct vmcs
*vmcs
)
2342 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2346 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2348 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2350 if (!loaded_vmcs
->vmcs
)
2352 loaded_vmcs_clear(loaded_vmcs
);
2353 free_vmcs(loaded_vmcs
->vmcs
);
2354 loaded_vmcs
->vmcs
= NULL
;
2357 static void free_kvm_area(void)
2361 for_each_possible_cpu(cpu
) {
2362 free_vmcs(per_cpu(vmxarea
, cpu
));
2363 per_cpu(vmxarea
, cpu
) = NULL
;
2367 static __init
int alloc_kvm_area(void)
2371 for_each_possible_cpu(cpu
) {
2374 vmcs
= alloc_vmcs_cpu(cpu
);
2380 per_cpu(vmxarea
, cpu
) = vmcs
;
2385 static __init
int hardware_setup(void)
2387 if (setup_vmcs_config(&vmcs_config
) < 0)
2390 if (boot_cpu_has(X86_FEATURE_NX
))
2391 kvm_enable_efer_bits(EFER_NX
);
2393 if (!cpu_has_vmx_vpid())
2396 if (!cpu_has_vmx_ept() ||
2397 !cpu_has_vmx_ept_4levels()) {
2399 enable_unrestricted_guest
= 0;
2402 if (!cpu_has_vmx_unrestricted_guest())
2403 enable_unrestricted_guest
= 0;
2405 if (!cpu_has_vmx_flexpriority())
2406 flexpriority_enabled
= 0;
2408 if (!cpu_has_vmx_tpr_shadow())
2409 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2411 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2412 kvm_disable_largepages();
2414 if (!cpu_has_vmx_ple())
2418 nested_vmx_setup_ctls_msrs();
2420 return alloc_kvm_area();
2423 static __exit
void hardware_unsetup(void)
2428 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2430 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2432 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2433 vmcs_write16(sf
->selector
, save
->selector
);
2434 vmcs_writel(sf
->base
, save
->base
);
2435 vmcs_write32(sf
->limit
, save
->limit
);
2436 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2438 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2440 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2444 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2446 unsigned long flags
;
2447 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2449 vmx
->emulation_required
= 1;
2450 vmx
->rmode
.vm86_active
= 0;
2452 vmx_segment_cache_clear(vmx
);
2454 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2455 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2456 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2457 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2459 flags
= vmcs_readl(GUEST_RFLAGS
);
2460 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2461 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2462 vmcs_writel(GUEST_RFLAGS
, flags
);
2464 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2465 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2467 update_exception_bitmap(vcpu
);
2469 if (emulate_invalid_guest_state
)
2472 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2473 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2474 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2475 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2477 vmx_segment_cache_clear(vmx
);
2479 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2480 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2482 vmcs_write16(GUEST_CS_SELECTOR
,
2483 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2484 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2487 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2489 if (!kvm
->arch
.tss_addr
) {
2490 struct kvm_memslots
*slots
;
2493 slots
= kvm_memslots(kvm
);
2494 base_gfn
= slots
->memslots
[0].base_gfn
+
2495 kvm
->memslots
->memslots
[0].npages
- 3;
2496 return base_gfn
<< PAGE_SHIFT
;
2498 return kvm
->arch
.tss_addr
;
2501 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2503 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2505 save
->selector
= vmcs_read16(sf
->selector
);
2506 save
->base
= vmcs_readl(sf
->base
);
2507 save
->limit
= vmcs_read32(sf
->limit
);
2508 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2509 vmcs_write16(sf
->selector
, save
->base
>> 4);
2510 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2511 vmcs_write32(sf
->limit
, 0xffff);
2512 vmcs_write32(sf
->ar_bytes
, 0xf3);
2513 if (save
->base
& 0xf)
2514 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2515 " aligned when entering protected mode (seg=%d)",
2519 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2521 unsigned long flags
;
2522 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2524 if (enable_unrestricted_guest
)
2527 vmx
->emulation_required
= 1;
2528 vmx
->rmode
.vm86_active
= 1;
2531 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2532 * vcpu. Call it here with phys address pointing 16M below 4G.
2534 if (!vcpu
->kvm
->arch
.tss_addr
) {
2535 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2536 "called before entering vcpu\n");
2537 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2538 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2539 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2542 vmx_segment_cache_clear(vmx
);
2544 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2545 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2546 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2548 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2549 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2551 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2552 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2554 flags
= vmcs_readl(GUEST_RFLAGS
);
2555 vmx
->rmode
.save_rflags
= flags
;
2557 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2559 vmcs_writel(GUEST_RFLAGS
, flags
);
2560 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2561 update_exception_bitmap(vcpu
);
2563 if (emulate_invalid_guest_state
)
2564 goto continue_rmode
;
2566 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
2567 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
2568 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
2570 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
2571 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
2572 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
2573 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
2574 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
2576 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2577 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2578 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2579 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2582 kvm_mmu_reset_context(vcpu
);
2585 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2588 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2594 * Force kernel_gs_base reloading before EFER changes, as control
2595 * of this msr depends on is_long_mode().
2597 vmx_load_host_state(to_vmx(vcpu
));
2598 vcpu
->arch
.efer
= efer
;
2599 if (efer
& EFER_LMA
) {
2600 vmcs_write32(VM_ENTRY_CONTROLS
,
2601 vmcs_read32(VM_ENTRY_CONTROLS
) |
2602 VM_ENTRY_IA32E_MODE
);
2605 vmcs_write32(VM_ENTRY_CONTROLS
,
2606 vmcs_read32(VM_ENTRY_CONTROLS
) &
2607 ~VM_ENTRY_IA32E_MODE
);
2609 msr
->data
= efer
& ~EFER_LME
;
2614 #ifdef CONFIG_X86_64
2616 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2620 vmx_segment_cache_clear(to_vmx(vcpu
));
2622 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2623 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2624 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
2626 vmcs_write32(GUEST_TR_AR_BYTES
,
2627 (guest_tr_ar
& ~AR_TYPE_MASK
)
2628 | AR_TYPE_BUSY_64_TSS
);
2630 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2633 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2635 vmcs_write32(VM_ENTRY_CONTROLS
,
2636 vmcs_read32(VM_ENTRY_CONTROLS
)
2637 & ~VM_ENTRY_IA32E_MODE
);
2638 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2643 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2645 vpid_sync_context(to_vmx(vcpu
));
2647 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2649 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2653 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2655 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2657 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2658 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2661 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2663 if (enable_ept
&& is_paging(vcpu
))
2664 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2665 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2668 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2670 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2672 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2673 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2676 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2678 if (!test_bit(VCPU_EXREG_PDPTR
,
2679 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2682 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2683 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2684 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2685 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2686 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2690 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2692 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2693 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2694 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2695 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2696 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2699 __set_bit(VCPU_EXREG_PDPTR
,
2700 (unsigned long *)&vcpu
->arch
.regs_avail
);
2701 __set_bit(VCPU_EXREG_PDPTR
,
2702 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2705 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2707 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2709 struct kvm_vcpu
*vcpu
)
2711 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2712 vmx_decache_cr3(vcpu
);
2713 if (!(cr0
& X86_CR0_PG
)) {
2714 /* From paging/starting to nonpaging */
2715 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2716 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2717 (CPU_BASED_CR3_LOAD_EXITING
|
2718 CPU_BASED_CR3_STORE_EXITING
));
2719 vcpu
->arch
.cr0
= cr0
;
2720 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2721 } else if (!is_paging(vcpu
)) {
2722 /* From nonpaging to paging */
2723 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2724 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
2725 ~(CPU_BASED_CR3_LOAD_EXITING
|
2726 CPU_BASED_CR3_STORE_EXITING
));
2727 vcpu
->arch
.cr0
= cr0
;
2728 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2731 if (!(cr0
& X86_CR0_WP
))
2732 *hw_cr0
&= ~X86_CR0_WP
;
2735 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2738 unsigned long hw_cr0
;
2740 if (enable_unrestricted_guest
)
2741 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
2742 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
2744 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
2746 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
2749 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
2752 #ifdef CONFIG_X86_64
2753 if (vcpu
->arch
.efer
& EFER_LME
) {
2754 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
2756 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
2762 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
2764 if (!vcpu
->fpu_active
)
2765 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
2767 vmcs_writel(CR0_READ_SHADOW
, cr0
);
2768 vmcs_writel(GUEST_CR0
, hw_cr0
);
2769 vcpu
->arch
.cr0
= cr0
;
2770 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2773 static u64
construct_eptp(unsigned long root_hpa
)
2777 /* TODO write the value reading from MSR */
2778 eptp
= VMX_EPT_DEFAULT_MT
|
2779 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
2780 eptp
|= (root_hpa
& PAGE_MASK
);
2785 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
2787 unsigned long guest_cr3
;
2792 eptp
= construct_eptp(cr3
);
2793 vmcs_write64(EPT_POINTER
, eptp
);
2794 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
2795 vcpu
->kvm
->arch
.ept_identity_map_addr
;
2796 ept_load_pdptrs(vcpu
);
2799 vmx_flush_tlb(vcpu
);
2800 vmcs_writel(GUEST_CR3
, guest_cr3
);
2803 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2805 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
2806 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
2808 if (cr4
& X86_CR4_VMXE
) {
2810 * To use VMXON (and later other VMX instructions), a guest
2811 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2812 * So basically the check on whether to allow nested VMX
2815 if (!nested_vmx_allowed(vcpu
))
2817 } else if (to_vmx(vcpu
)->nested
.vmxon
)
2820 vcpu
->arch
.cr4
= cr4
;
2822 if (!is_paging(vcpu
)) {
2823 hw_cr4
&= ~X86_CR4_PAE
;
2824 hw_cr4
|= X86_CR4_PSE
;
2825 } else if (!(cr4
& X86_CR4_PAE
)) {
2826 hw_cr4
&= ~X86_CR4_PAE
;
2830 vmcs_writel(CR4_READ_SHADOW
, cr4
);
2831 vmcs_writel(GUEST_CR4
, hw_cr4
);
2835 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2836 struct kvm_segment
*var
, int seg
)
2838 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2839 struct kvm_save_segment
*save
;
2842 if (vmx
->rmode
.vm86_active
2843 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
2844 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
2845 || seg
== VCPU_SREG_GS
)
2846 && !emulate_invalid_guest_state
) {
2848 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
2849 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
2850 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
2851 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
2852 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
2855 var
->selector
= save
->selector
;
2856 var
->base
= save
->base
;
2857 var
->limit
= save
->limit
;
2859 if (seg
== VCPU_SREG_TR
2860 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
2861 goto use_saved_rmode_seg
;
2863 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
2864 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
2865 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
2866 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
2867 use_saved_rmode_seg
:
2868 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2870 var
->type
= ar
& 15;
2871 var
->s
= (ar
>> 4) & 1;
2872 var
->dpl
= (ar
>> 5) & 3;
2873 var
->present
= (ar
>> 7) & 1;
2874 var
->avl
= (ar
>> 12) & 1;
2875 var
->l
= (ar
>> 13) & 1;
2876 var
->db
= (ar
>> 14) & 1;
2877 var
->g
= (ar
>> 15) & 1;
2878 var
->unusable
= (ar
>> 16) & 1;
2881 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2883 struct kvm_segment s
;
2885 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2886 vmx_get_segment(vcpu
, &s
, seg
);
2889 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
2892 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2894 if (!is_protmode(vcpu
))
2897 if (!is_long_mode(vcpu
)
2898 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
2901 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
2904 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2906 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2907 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2908 to_vmx(vcpu
)->cpl
= __vmx_get_cpl(vcpu
);
2910 return to_vmx(vcpu
)->cpl
;
2914 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
2921 ar
= var
->type
& 15;
2922 ar
|= (var
->s
& 1) << 4;
2923 ar
|= (var
->dpl
& 3) << 5;
2924 ar
|= (var
->present
& 1) << 7;
2925 ar
|= (var
->avl
& 1) << 12;
2926 ar
|= (var
->l
& 1) << 13;
2927 ar
|= (var
->db
& 1) << 14;
2928 ar
|= (var
->g
& 1) << 15;
2930 if (ar
== 0) /* a 0 value means unusable */
2931 ar
= AR_UNUSABLE_MASK
;
2936 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
2937 struct kvm_segment
*var
, int seg
)
2939 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2940 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2943 vmx_segment_cache_clear(vmx
);
2945 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2946 vmcs_write16(sf
->selector
, var
->selector
);
2947 vmx
->rmode
.tr
.selector
= var
->selector
;
2948 vmx
->rmode
.tr
.base
= var
->base
;
2949 vmx
->rmode
.tr
.limit
= var
->limit
;
2950 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2953 vmcs_writel(sf
->base
, var
->base
);
2954 vmcs_write32(sf
->limit
, var
->limit
);
2955 vmcs_write16(sf
->selector
, var
->selector
);
2956 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2958 * Hack real-mode segments into vm86 compatibility.
2960 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2961 vmcs_writel(sf
->base
, 0xf0000);
2964 ar
= vmx_segment_access_rights(var
);
2967 * Fix the "Accessed" bit in AR field of segment registers for older
2969 * IA32 arch specifies that at the time of processor reset the
2970 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2971 * is setting it to 0 in the usedland code. This causes invalid guest
2972 * state vmexit when "unrestricted guest" mode is turned on.
2973 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2974 * tree. Newer qemu binaries with that qemu fix would not need this
2977 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2978 ar
|= 0x1; /* Accessed */
2980 vmcs_write32(sf
->ar_bytes
, ar
);
2981 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2984 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2986 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
2988 *db
= (ar
>> 14) & 1;
2989 *l
= (ar
>> 13) & 1;
2992 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2994 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2995 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2998 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3000 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3001 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3004 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3006 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3007 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3010 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3012 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3013 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3016 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3018 struct kvm_segment var
;
3021 vmx_get_segment(vcpu
, &var
, seg
);
3022 ar
= vmx_segment_access_rights(&var
);
3024 if (var
.base
!= (var
.selector
<< 4))
3026 if (var
.limit
!= 0xffff)
3034 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3036 struct kvm_segment cs
;
3037 unsigned int cs_rpl
;
3039 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3040 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3044 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3048 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3049 if (cs
.dpl
> cs_rpl
)
3052 if (cs
.dpl
!= cs_rpl
)
3058 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3062 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3064 struct kvm_segment ss
;
3065 unsigned int ss_rpl
;
3067 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3068 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3072 if (ss
.type
!= 3 && ss
.type
!= 7)
3076 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3084 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3086 struct kvm_segment var
;
3089 vmx_get_segment(vcpu
, &var
, seg
);
3090 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3098 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3099 if (var
.dpl
< rpl
) /* DPL < RPL */
3103 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3109 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3111 struct kvm_segment tr
;
3113 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3117 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3119 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3127 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3129 struct kvm_segment ldtr
;
3131 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3135 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3145 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3147 struct kvm_segment cs
, ss
;
3149 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3150 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3152 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3153 (ss
.selector
& SELECTOR_RPL_MASK
));
3157 * Check if guest state is valid. Returns true if valid, false if
3159 * We assume that registers are always usable
3161 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3163 /* real mode guest state checks */
3164 if (!is_protmode(vcpu
)) {
3165 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3167 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3169 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3171 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3173 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3175 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3178 /* protected mode guest state checks */
3179 if (!cs_ss_rpl_check(vcpu
))
3181 if (!code_segment_valid(vcpu
))
3183 if (!stack_segment_valid(vcpu
))
3185 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3187 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3189 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3191 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3193 if (!tr_valid(vcpu
))
3195 if (!ldtr_valid(vcpu
))
3199 * - Add checks on RIP
3200 * - Add checks on RFLAGS
3206 static int init_rmode_tss(struct kvm
*kvm
)
3210 int r
, idx
, ret
= 0;
3212 idx
= srcu_read_lock(&kvm
->srcu
);
3213 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3214 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3217 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3218 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3219 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3222 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3225 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3229 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3230 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3237 srcu_read_unlock(&kvm
->srcu
, idx
);
3241 static int init_rmode_identity_map(struct kvm
*kvm
)
3244 pfn_t identity_map_pfn
;
3249 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3250 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3251 "haven't been allocated!\n");
3254 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3257 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3258 idx
= srcu_read_lock(&kvm
->srcu
);
3259 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3262 /* Set up identity-mapping pagetable for EPT in real mode */
3263 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3264 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3265 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3266 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3267 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3271 kvm
->arch
.ept_identity_pagetable_done
= true;
3274 srcu_read_unlock(&kvm
->srcu
, idx
);
3278 static void seg_setup(int seg
)
3280 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3283 vmcs_write16(sf
->selector
, 0);
3284 vmcs_writel(sf
->base
, 0);
3285 vmcs_write32(sf
->limit
, 0xffff);
3286 if (enable_unrestricted_guest
) {
3288 if (seg
== VCPU_SREG_CS
)
3289 ar
|= 0x08; /* code segment */
3293 vmcs_write32(sf
->ar_bytes
, ar
);
3296 static int alloc_apic_access_page(struct kvm
*kvm
)
3298 struct kvm_userspace_memory_region kvm_userspace_mem
;
3301 mutex_lock(&kvm
->slots_lock
);
3302 if (kvm
->arch
.apic_access_page
)
3304 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3305 kvm_userspace_mem
.flags
= 0;
3306 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3307 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3308 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3312 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3314 mutex_unlock(&kvm
->slots_lock
);
3318 static int alloc_identity_pagetable(struct kvm
*kvm
)
3320 struct kvm_userspace_memory_region kvm_userspace_mem
;
3323 mutex_lock(&kvm
->slots_lock
);
3324 if (kvm
->arch
.ept_identity_pagetable
)
3326 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3327 kvm_userspace_mem
.flags
= 0;
3328 kvm_userspace_mem
.guest_phys_addr
=
3329 kvm
->arch
.ept_identity_map_addr
;
3330 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3331 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3335 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3336 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3338 mutex_unlock(&kvm
->slots_lock
);
3342 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3349 spin_lock(&vmx_vpid_lock
);
3350 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3351 if (vpid
< VMX_NR_VPIDS
) {
3353 __set_bit(vpid
, vmx_vpid_bitmap
);
3355 spin_unlock(&vmx_vpid_lock
);
3358 static void free_vpid(struct vcpu_vmx
*vmx
)
3362 spin_lock(&vmx_vpid_lock
);
3364 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3365 spin_unlock(&vmx_vpid_lock
);
3368 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3370 int f
= sizeof(unsigned long);
3372 if (!cpu_has_vmx_msr_bitmap())
3376 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3377 * have the write-low and read-high bitmap offsets the wrong way round.
3378 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3380 if (msr
<= 0x1fff) {
3381 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3382 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3383 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3385 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3386 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3390 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3393 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3394 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3398 * Sets up the vmcs for emulated real mode.
3400 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3402 u32 host_sysenter_cs
, msr_low
, msr_high
;
3408 unsigned long kvm_vmx_return
;
3412 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3413 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3415 if (cpu_has_vmx_msr_bitmap())
3416 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3418 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3421 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3422 vmcs_config
.pin_based_exec_ctrl
);
3424 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3425 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3426 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3427 #ifdef CONFIG_X86_64
3428 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3429 CPU_BASED_CR8_LOAD_EXITING
;
3433 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3434 CPU_BASED_CR3_LOAD_EXITING
|
3435 CPU_BASED_INVLPG_EXITING
;
3436 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
3438 if (cpu_has_secondary_exec_ctrls()) {
3439 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3440 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3442 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3444 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3446 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3447 enable_unrestricted_guest
= 0;
3449 if (!enable_unrestricted_guest
)
3450 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3452 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3453 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
3457 vmcs_write32(PLE_GAP
, ple_gap
);
3458 vmcs_write32(PLE_WINDOW
, ple_window
);
3461 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
3462 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
3463 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3465 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3466 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3467 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3469 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3470 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3471 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3472 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3473 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3474 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3475 #ifdef CONFIG_X86_64
3476 rdmsrl(MSR_FS_BASE
, a
);
3477 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3478 rdmsrl(MSR_GS_BASE
, a
);
3479 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3481 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3482 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3485 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3487 native_store_idt(&dt
);
3488 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3490 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
3491 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
3492 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3493 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3494 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3495 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3496 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3498 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
3499 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
3500 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
3501 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
3502 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
3503 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
3505 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3506 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3507 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3508 vmcs_write64(HOST_IA32_PAT
, host_pat
);
3510 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3511 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3512 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3513 /* Write the default value follow host pat */
3514 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3515 /* Keep arch.pat sync with GUEST_IA32_PAT */
3516 vmx
->vcpu
.arch
.pat
= host_pat
;
3519 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3520 u32 index
= vmx_msr_index
[i
];
3521 u32 data_low
, data_high
;
3524 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3526 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3528 vmx
->guest_msrs
[j
].index
= i
;
3529 vmx
->guest_msrs
[j
].data
= 0;
3530 vmx
->guest_msrs
[j
].mask
= -1ull;
3534 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3536 /* 22.2.1, 20.8.1 */
3537 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3539 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3540 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3542 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3543 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3545 kvm_write_tsc(&vmx
->vcpu
, 0);
3550 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3552 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3556 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3558 vmx
->rmode
.vm86_active
= 0;
3560 vmx
->soft_vnmi_blocked
= 0;
3562 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3563 kvm_set_cr8(&vmx
->vcpu
, 0);
3564 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3565 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3566 msr
|= MSR_IA32_APICBASE_BSP
;
3567 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3569 ret
= fx_init(&vmx
->vcpu
);
3573 vmx_segment_cache_clear(vmx
);
3575 seg_setup(VCPU_SREG_CS
);
3577 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3578 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3580 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3581 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3582 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3584 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3585 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3588 seg_setup(VCPU_SREG_DS
);
3589 seg_setup(VCPU_SREG_ES
);
3590 seg_setup(VCPU_SREG_FS
);
3591 seg_setup(VCPU_SREG_GS
);
3592 seg_setup(VCPU_SREG_SS
);
3594 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3595 vmcs_writel(GUEST_TR_BASE
, 0);
3596 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3597 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3599 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3600 vmcs_writel(GUEST_LDTR_BASE
, 0);
3601 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3602 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3604 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3605 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3606 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3608 vmcs_writel(GUEST_RFLAGS
, 0x02);
3609 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3610 kvm_rip_write(vcpu
, 0xfff0);
3612 kvm_rip_write(vcpu
, 0);
3613 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3615 vmcs_writel(GUEST_DR7
, 0x400);
3617 vmcs_writel(GUEST_GDTR_BASE
, 0);
3618 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3620 vmcs_writel(GUEST_IDTR_BASE
, 0);
3621 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3623 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3624 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3625 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3627 /* Special registers */
3628 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
3632 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
3634 if (cpu_has_vmx_tpr_shadow()) {
3635 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
3636 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
3637 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
3638 __pa(vmx
->vcpu
.arch
.apic
->regs
));
3639 vmcs_write32(TPR_THRESHOLD
, 0);
3642 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3643 vmcs_write64(APIC_ACCESS_ADDR
,
3644 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
3647 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
3649 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
3650 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
3651 vmx_set_cr4(&vmx
->vcpu
, 0);
3652 vmx_set_efer(&vmx
->vcpu
, 0);
3653 vmx_fpu_activate(&vmx
->vcpu
);
3654 update_exception_bitmap(&vmx
->vcpu
);
3656 vpid_sync_context(vmx
);
3660 /* HACK: Don't enable emulation on guest boot/reset */
3661 vmx
->emulation_required
= 0;
3667 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3669 u32 cpu_based_vm_exec_control
;
3671 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3672 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
3673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3676 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3678 u32 cpu_based_vm_exec_control
;
3680 if (!cpu_has_virtual_nmis()) {
3681 enable_irq_window(vcpu
);
3685 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
3686 enable_irq_window(vcpu
);
3689 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3690 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
3691 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3694 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
3696 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3698 int irq
= vcpu
->arch
.interrupt
.nr
;
3700 trace_kvm_inj_virq(irq
);
3702 ++vcpu
->stat
.irq_injections
;
3703 if (vmx
->rmode
.vm86_active
) {
3705 if (vcpu
->arch
.interrupt
.soft
)
3706 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
3707 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
3708 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3711 intr
= irq
| INTR_INFO_VALID_MASK
;
3712 if (vcpu
->arch
.interrupt
.soft
) {
3713 intr
|= INTR_TYPE_SOFT_INTR
;
3714 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
3715 vmx
->vcpu
.arch
.event_exit_inst_len
);
3717 intr
|= INTR_TYPE_EXT_INTR
;
3718 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
3719 vmx_clear_hlt(vcpu
);
3722 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
3724 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3726 if (!cpu_has_virtual_nmis()) {
3728 * Tracking the NMI-blocked state in software is built upon
3729 * finding the next open IRQ window. This, in turn, depends on
3730 * well-behaving guests: They have to keep IRQs disabled at
3731 * least as long as the NMI handler runs. Otherwise we may
3732 * cause NMI nesting, maybe breaking the guest. But as this is
3733 * highly unlikely, we can live with the residual risk.
3735 vmx
->soft_vnmi_blocked
= 1;
3736 vmx
->vnmi_blocked_time
= 0;
3739 ++vcpu
->stat
.nmi_injections
;
3740 vmx
->nmi_known_unmasked
= false;
3741 if (vmx
->rmode
.vm86_active
) {
3742 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
3743 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
3747 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
3748 vmx_clear_hlt(vcpu
);
3751 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
3753 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
3756 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3757 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
3758 | GUEST_INTR_STATE_NMI
));
3761 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3763 if (!cpu_has_virtual_nmis())
3764 return to_vmx(vcpu
)->soft_vnmi_blocked
;
3765 if (to_vmx(vcpu
)->nmi_known_unmasked
)
3767 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
3770 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3774 if (!cpu_has_virtual_nmis()) {
3775 if (vmx
->soft_vnmi_blocked
!= masked
) {
3776 vmx
->soft_vnmi_blocked
= masked
;
3777 vmx
->vnmi_blocked_time
= 0;
3780 vmx
->nmi_known_unmasked
= !masked
;
3782 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3783 GUEST_INTR_STATE_NMI
);
3785 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3786 GUEST_INTR_STATE_NMI
);
3790 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3792 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
3793 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3794 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
3797 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3800 struct kvm_userspace_memory_region tss_mem
= {
3801 .slot
= TSS_PRIVATE_MEMSLOT
,
3802 .guest_phys_addr
= addr
,
3803 .memory_size
= PAGE_SIZE
* 3,
3807 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
3810 kvm
->arch
.tss_addr
= addr
;
3811 if (!init_rmode_tss(kvm
))
3817 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
3818 int vec
, u32 err_code
)
3821 * Instruction with address size override prefix opcode 0x67
3822 * Cause the #SS fault with 0 error code in VM86 mode.
3824 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
3825 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
3828 * Forward all other exceptions that are valid in real mode.
3829 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3830 * the required debugging infrastructure rework.
3834 if (vcpu
->guest_debug
&
3835 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
3837 kvm_queue_exception(vcpu
, vec
);
3841 * Update instruction length as we may reinject the exception
3842 * from user space while in guest debugging mode.
3844 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
3845 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3846 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
3857 kvm_queue_exception(vcpu
, vec
);
3864 * Trigger machine check on the host. We assume all the MSRs are already set up
3865 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3866 * We pass a fake environment to the machine check handler because we want
3867 * the guest to be always treated like user space, no matter what context
3868 * it used internally.
3870 static void kvm_machine_check(void)
3872 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3873 struct pt_regs regs
= {
3874 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
3875 .flags
= X86_EFLAGS_IF
,
3878 do_machine_check(®s
, 0);
3882 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
3884 /* already handled by vcpu_run */
3888 static int handle_exception(struct kvm_vcpu
*vcpu
)
3890 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3891 struct kvm_run
*kvm_run
= vcpu
->run
;
3892 u32 intr_info
, ex_no
, error_code
;
3893 unsigned long cr2
, rip
, dr6
;
3895 enum emulation_result er
;
3897 vect_info
= vmx
->idt_vectoring_info
;
3898 intr_info
= vmx
->exit_intr_info
;
3900 if (is_machine_check(intr_info
))
3901 return handle_machine_check(vcpu
);
3903 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
3904 !is_page_fault(intr_info
)) {
3905 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3906 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
3907 vcpu
->run
->internal
.ndata
= 2;
3908 vcpu
->run
->internal
.data
[0] = vect_info
;
3909 vcpu
->run
->internal
.data
[1] = intr_info
;
3913 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
3914 return 1; /* already handled by vmx_vcpu_run() */
3916 if (is_no_device(intr_info
)) {
3917 vmx_fpu_activate(vcpu
);
3921 if (is_invalid_opcode(intr_info
)) {
3922 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
3923 if (er
!= EMULATE_DONE
)
3924 kvm_queue_exception(vcpu
, UD_VECTOR
);
3929 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
3930 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
3931 if (is_page_fault(intr_info
)) {
3932 /* EPT won't cause page fault directly */
3935 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3936 trace_kvm_page_fault(cr2
, error_code
);
3938 if (kvm_event_needs_reinjection(vcpu
))
3939 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3940 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
3943 if (vmx
->rmode
.vm86_active
&&
3944 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3946 if (vcpu
->arch
.halt_request
) {
3947 vcpu
->arch
.halt_request
= 0;
3948 return kvm_emulate_halt(vcpu
);
3953 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3956 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3957 if (!(vcpu
->guest_debug
&
3958 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3959 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3960 kvm_queue_exception(vcpu
, DB_VECTOR
);
3963 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3964 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3968 * Update instruction length as we may reinject #BP from
3969 * user space while in guest debugging mode. Reading it for
3970 * #DB as well causes no harm, it is not used in that case.
3972 vmx
->vcpu
.arch
.event_exit_inst_len
=
3973 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3974 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3975 rip
= kvm_rip_read(vcpu
);
3976 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3977 kvm_run
->debug
.arch
.exception
= ex_no
;
3980 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3981 kvm_run
->ex
.exception
= ex_no
;
3982 kvm_run
->ex
.error_code
= error_code
;
3988 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3990 ++vcpu
->stat
.irq_exits
;
3994 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3996 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4000 static int handle_io(struct kvm_vcpu
*vcpu
)
4002 unsigned long exit_qualification
;
4003 int size
, in
, string
;
4006 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4007 string
= (exit_qualification
& 16) != 0;
4008 in
= (exit_qualification
& 8) != 0;
4010 ++vcpu
->stat
.io_exits
;
4013 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4015 port
= exit_qualification
>> 16;
4016 size
= (exit_qualification
& 7) + 1;
4017 skip_emulated_instruction(vcpu
);
4019 return kvm_fast_pio_out(vcpu
, size
, port
);
4023 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4026 * Patch in the VMCALL instruction:
4028 hypercall
[0] = 0x0f;
4029 hypercall
[1] = 0x01;
4030 hypercall
[2] = 0xc1;
4033 static int handle_cr(struct kvm_vcpu
*vcpu
)
4035 unsigned long exit_qualification
, val
;
4040 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4041 cr
= exit_qualification
& 15;
4042 reg
= (exit_qualification
>> 8) & 15;
4043 switch ((exit_qualification
>> 4) & 3) {
4044 case 0: /* mov to cr */
4045 val
= kvm_register_read(vcpu
, reg
);
4046 trace_kvm_cr_write(cr
, val
);
4049 err
= kvm_set_cr0(vcpu
, val
);
4050 kvm_complete_insn_gp(vcpu
, err
);
4053 err
= kvm_set_cr3(vcpu
, val
);
4054 kvm_complete_insn_gp(vcpu
, err
);
4057 err
= kvm_set_cr4(vcpu
, val
);
4058 kvm_complete_insn_gp(vcpu
, err
);
4061 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4062 u8 cr8
= kvm_register_read(vcpu
, reg
);
4063 err
= kvm_set_cr8(vcpu
, cr8
);
4064 kvm_complete_insn_gp(vcpu
, err
);
4065 if (irqchip_in_kernel(vcpu
->kvm
))
4067 if (cr8_prev
<= cr8
)
4069 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4075 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4076 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4077 skip_emulated_instruction(vcpu
);
4078 vmx_fpu_activate(vcpu
);
4080 case 1: /*mov from cr*/
4083 val
= kvm_read_cr3(vcpu
);
4084 kvm_register_write(vcpu
, reg
, val
);
4085 trace_kvm_cr_read(cr
, val
);
4086 skip_emulated_instruction(vcpu
);
4089 val
= kvm_get_cr8(vcpu
);
4090 kvm_register_write(vcpu
, reg
, val
);
4091 trace_kvm_cr_read(cr
, val
);
4092 skip_emulated_instruction(vcpu
);
4097 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4098 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4099 kvm_lmsw(vcpu
, val
);
4101 skip_emulated_instruction(vcpu
);
4106 vcpu
->run
->exit_reason
= 0;
4107 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4108 (int)(exit_qualification
>> 4) & 3, cr
);
4112 static int handle_dr(struct kvm_vcpu
*vcpu
)
4114 unsigned long exit_qualification
;
4117 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4118 if (!kvm_require_cpl(vcpu
, 0))
4120 dr
= vmcs_readl(GUEST_DR7
);
4123 * As the vm-exit takes precedence over the debug trap, we
4124 * need to emulate the latter, either for the host or the
4125 * guest debugging itself.
4127 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4128 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4129 vcpu
->run
->debug
.arch
.dr7
= dr
;
4130 vcpu
->run
->debug
.arch
.pc
=
4131 vmcs_readl(GUEST_CS_BASE
) +
4132 vmcs_readl(GUEST_RIP
);
4133 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4134 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4137 vcpu
->arch
.dr7
&= ~DR7_GD
;
4138 vcpu
->arch
.dr6
|= DR6_BD
;
4139 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4140 kvm_queue_exception(vcpu
, DB_VECTOR
);
4145 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4146 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4147 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4148 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4150 if (!kvm_get_dr(vcpu
, dr
, &val
))
4151 kvm_register_write(vcpu
, reg
, val
);
4153 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4154 skip_emulated_instruction(vcpu
);
4158 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4160 vmcs_writel(GUEST_DR7
, val
);
4163 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4165 kvm_emulate_cpuid(vcpu
);
4169 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4171 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4174 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4175 trace_kvm_msr_read_ex(ecx
);
4176 kvm_inject_gp(vcpu
, 0);
4180 trace_kvm_msr_read(ecx
, data
);
4182 /* FIXME: handling of bits 32:63 of rax, rdx */
4183 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4184 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4185 skip_emulated_instruction(vcpu
);
4189 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4191 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4192 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4193 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4195 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
4196 trace_kvm_msr_write_ex(ecx
, data
);
4197 kvm_inject_gp(vcpu
, 0);
4201 trace_kvm_msr_write(ecx
, data
);
4202 skip_emulated_instruction(vcpu
);
4206 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4208 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4212 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4214 u32 cpu_based_vm_exec_control
;
4216 /* clear pending irq */
4217 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4218 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4219 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4221 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4223 ++vcpu
->stat
.irq_window_exits
;
4226 * If the user space waits to inject interrupts, exit as soon as
4229 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4230 vcpu
->run
->request_interrupt_window
&&
4231 !kvm_cpu_has_interrupt(vcpu
)) {
4232 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4238 static int handle_halt(struct kvm_vcpu
*vcpu
)
4240 skip_emulated_instruction(vcpu
);
4241 return kvm_emulate_halt(vcpu
);
4244 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4246 skip_emulated_instruction(vcpu
);
4247 kvm_emulate_hypercall(vcpu
);
4251 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
4253 kvm_queue_exception(vcpu
, UD_VECTOR
);
4257 static int handle_invd(struct kvm_vcpu
*vcpu
)
4259 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4262 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4266 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4267 skip_emulated_instruction(vcpu
);
4271 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4273 skip_emulated_instruction(vcpu
);
4274 kvm_emulate_wbinvd(vcpu
);
4278 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4280 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4281 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4283 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4284 skip_emulated_instruction(vcpu
);
4288 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4290 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4293 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4296 unsigned long exit_qualification
;
4297 bool has_error_code
= false;
4300 int reason
, type
, idt_v
;
4302 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4303 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4305 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4307 reason
= (u32
)exit_qualification
>> 30;
4308 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4310 case INTR_TYPE_NMI_INTR
:
4311 vcpu
->arch
.nmi_injected
= false;
4312 vmx_set_nmi_mask(vcpu
, true);
4314 case INTR_TYPE_EXT_INTR
:
4315 case INTR_TYPE_SOFT_INTR
:
4316 kvm_clear_interrupt_queue(vcpu
);
4318 case INTR_TYPE_HARD_EXCEPTION
:
4319 if (vmx
->idt_vectoring_info
&
4320 VECTORING_INFO_DELIVER_CODE_MASK
) {
4321 has_error_code
= true;
4323 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4326 case INTR_TYPE_SOFT_EXCEPTION
:
4327 kvm_clear_exception_queue(vcpu
);
4333 tss_selector
= exit_qualification
;
4335 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4336 type
!= INTR_TYPE_EXT_INTR
&&
4337 type
!= INTR_TYPE_NMI_INTR
))
4338 skip_emulated_instruction(vcpu
);
4340 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
4341 has_error_code
, error_code
) == EMULATE_FAIL
) {
4342 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4343 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4344 vcpu
->run
->internal
.ndata
= 0;
4348 /* clear all local breakpoint enable flags */
4349 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4352 * TODO: What about debug traps on tss switch?
4353 * Are we supposed to inject them and update dr6?
4359 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4361 unsigned long exit_qualification
;
4365 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4367 if (exit_qualification
& (1 << 6)) {
4368 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4372 gla_validity
= (exit_qualification
>> 7) & 0x3;
4373 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4374 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4375 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4376 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4377 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4378 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4379 (long unsigned int)exit_qualification
);
4380 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4381 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4385 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4386 trace_kvm_page_fault(gpa
, exit_qualification
);
4387 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
4390 static u64
ept_rsvd_mask(u64 spte
, int level
)
4395 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4396 mask
|= (1ULL << i
);
4399 /* bits 7:3 reserved */
4401 else if (level
== 2) {
4402 if (spte
& (1ULL << 7))
4403 /* 2MB ref, bits 20:12 reserved */
4406 /* bits 6:3 reserved */
4413 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4416 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4418 /* 010b (write-only) */
4419 WARN_ON((spte
& 0x7) == 0x2);
4421 /* 110b (write/execute) */
4422 WARN_ON((spte
& 0x7) == 0x6);
4424 /* 100b (execute-only) and value not supported by logical processor */
4425 if (!cpu_has_vmx_ept_execute_only())
4426 WARN_ON((spte
& 0x7) == 0x4);
4430 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4432 if (rsvd_bits
!= 0) {
4433 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4434 __func__
, rsvd_bits
);
4438 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4439 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4441 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4442 ept_mem_type
== 7) {
4443 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4444 __func__
, ept_mem_type
);
4451 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4457 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4459 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4460 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4462 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4464 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4465 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4467 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4468 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4473 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4475 u32 cpu_based_vm_exec_control
;
4477 /* clear pending NMI */
4478 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4479 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4480 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4481 ++vcpu
->stat
.nmi_window_exits
;
4482 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4487 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4490 enum emulation_result err
= EMULATE_DONE
;
4493 bool intr_window_requested
;
4495 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4496 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4498 while (!guest_state_valid(vcpu
)) {
4499 if (intr_window_requested
4500 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
4501 return handle_interrupt_window(&vmx
->vcpu
);
4503 err
= emulate_instruction(vcpu
, 0);
4505 if (err
== EMULATE_DO_MMIO
) {
4510 if (err
!= EMULATE_DONE
)
4513 if (signal_pending(current
))
4519 vmx
->emulation_required
= 0;
4525 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4526 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4528 static int handle_pause(struct kvm_vcpu
*vcpu
)
4530 skip_emulated_instruction(vcpu
);
4531 kvm_vcpu_on_spin(vcpu
);
4536 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
4538 kvm_queue_exception(vcpu
, UD_VECTOR
);
4543 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4544 * We could reuse a single VMCS for all the L2 guests, but we also want the
4545 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4546 * allows keeping them loaded on the processor, and in the future will allow
4547 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4548 * every entry if they never change.
4549 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4550 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4552 * The following functions allocate and free a vmcs02 in this pool.
4555 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4556 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
4558 struct vmcs02_list
*item
;
4559 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4560 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
4561 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4562 return &item
->vmcs02
;
4565 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
4566 /* Recycle the least recently used VMCS. */
4567 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
4568 struct vmcs02_list
, list
);
4569 item
->vmptr
= vmx
->nested
.current_vmptr
;
4570 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4571 return &item
->vmcs02
;
4574 /* Create a new VMCS */
4575 item
= (struct vmcs02_list
*)
4576 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
4579 item
->vmcs02
.vmcs
= alloc_vmcs();
4580 if (!item
->vmcs02
.vmcs
) {
4584 loaded_vmcs_init(&item
->vmcs02
);
4585 item
->vmptr
= vmx
->nested
.current_vmptr
;
4586 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
4587 vmx
->nested
.vmcs02_num
++;
4588 return &item
->vmcs02
;
4591 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4592 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
4594 struct vmcs02_list
*item
;
4595 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4596 if (item
->vmptr
== vmptr
) {
4597 free_loaded_vmcs(&item
->vmcs02
);
4598 list_del(&item
->list
);
4600 vmx
->nested
.vmcs02_num
--;
4606 * Free all VMCSs saved for this vcpu, except the one pointed by
4607 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4608 * currently used, if running L2), and vmcs01 when running L2.
4610 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
4612 struct vmcs02_list
*item
, *n
;
4613 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
4614 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
4615 free_loaded_vmcs(&item
->vmcs02
);
4616 list_del(&item
->list
);
4619 vmx
->nested
.vmcs02_num
= 0;
4621 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
4622 free_loaded_vmcs(&vmx
->vmcs01
);
4626 * Emulate the VMXON instruction.
4627 * Currently, we just remember that VMX is active, and do not save or even
4628 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4629 * do not currently need to store anything in that guest-allocated memory
4630 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4631 * argument is different from the VMXON pointer (which the spec says they do).
4633 static int handle_vmon(struct kvm_vcpu
*vcpu
)
4635 struct kvm_segment cs
;
4636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4638 /* The Intel VMX Instruction Reference lists a bunch of bits that
4639 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4640 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4641 * Otherwise, we should fail with #UD. We test these now:
4643 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
4644 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
4645 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4646 kvm_queue_exception(vcpu
, UD_VECTOR
);
4650 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4651 if (is_long_mode(vcpu
) && !cs
.l
) {
4652 kvm_queue_exception(vcpu
, UD_VECTOR
);
4656 if (vmx_get_cpl(vcpu
)) {
4657 kvm_inject_gp(vcpu
, 0);
4661 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
4662 vmx
->nested
.vmcs02_num
= 0;
4664 vmx
->nested
.vmxon
= true;
4666 skip_emulated_instruction(vcpu
);
4671 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4672 * for running VMX instructions (except VMXON, whose prerequisites are
4673 * slightly different). It also specifies what exception to inject otherwise.
4675 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
4677 struct kvm_segment cs
;
4678 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4680 if (!vmx
->nested
.vmxon
) {
4681 kvm_queue_exception(vcpu
, UD_VECTOR
);
4685 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4686 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
4687 (is_long_mode(vcpu
) && !cs
.l
)) {
4688 kvm_queue_exception(vcpu
, UD_VECTOR
);
4692 if (vmx_get_cpl(vcpu
)) {
4693 kvm_inject_gp(vcpu
, 0);
4701 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4702 * just stops using VMX.
4704 static void free_nested(struct vcpu_vmx
*vmx
)
4706 if (!vmx
->nested
.vmxon
)
4708 vmx
->nested
.vmxon
= false;
4709 if (vmx
->nested
.current_vmptr
!= -1ull) {
4710 kunmap(vmx
->nested
.current_vmcs12_page
);
4711 nested_release_page(vmx
->nested
.current_vmcs12_page
);
4712 vmx
->nested
.current_vmptr
= -1ull;
4713 vmx
->nested
.current_vmcs12
= NULL
;
4716 nested_free_all_saved_vmcss(vmx
);
4719 /* Emulate the VMXOFF instruction */
4720 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
4722 if (!nested_vmx_check_permission(vcpu
))
4724 free_nested(to_vmx(vcpu
));
4725 skip_emulated_instruction(vcpu
);
4730 * Decode the memory-address operand of a vmx instruction, as recorded on an
4731 * exit caused by such an instruction (run by a guest hypervisor).
4732 * On success, returns 0. When the operand is invalid, returns 1 and throws
4735 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
4736 unsigned long exit_qualification
,
4737 u32 vmx_instruction_info
, gva_t
*ret
)
4740 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4741 * Execution", on an exit, vmx_instruction_info holds most of the
4742 * addressing components of the operand. Only the displacement part
4743 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4744 * For how an actual address is calculated from all these components,
4745 * refer to Vol. 1, "Operand Addressing".
4747 int scaling
= vmx_instruction_info
& 3;
4748 int addr_size
= (vmx_instruction_info
>> 7) & 7;
4749 bool is_reg
= vmx_instruction_info
& (1u << 10);
4750 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
4751 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
4752 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
4753 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
4754 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
4757 kvm_queue_exception(vcpu
, UD_VECTOR
);
4761 /* Addr = segment_base + offset */
4762 /* offset = base + [index * scale] + displacement */
4763 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
4765 *ret
+= kvm_register_read(vcpu
, base_reg
);
4767 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
4768 *ret
+= exit_qualification
; /* holds the displacement */
4770 if (addr_size
== 1) /* 32 bit */
4774 * TODO: throw #GP (and return 1) in various cases that the VM*
4775 * instructions require it - e.g., offset beyond segment limit,
4776 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4777 * address, and so on. Currently these are not checked.
4783 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4784 * set the success or error code of an emulated VMX instruction, as specified
4785 * by Vol 2B, VMX Instruction Reference, "Conventions".
4787 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
4789 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
4790 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
4791 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
4794 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
4796 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
4797 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
4798 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
4802 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
4803 u32 vm_instruction_error
)
4805 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
4807 * failValid writes the error number to the current VMCS, which
4808 * can't be done there isn't a current VMCS.
4810 nested_vmx_failInvalid(vcpu
);
4813 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
4814 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
4815 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
4817 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
4820 /* Emulate the VMCLEAR instruction */
4821 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
4823 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4826 struct vmcs12
*vmcs12
;
4828 struct x86_exception e
;
4830 if (!nested_vmx_check_permission(vcpu
))
4833 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
4834 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
4837 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
4838 sizeof(vmptr
), &e
)) {
4839 kvm_inject_page_fault(vcpu
, &e
);
4843 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
4844 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
4845 skip_emulated_instruction(vcpu
);
4849 if (vmptr
== vmx
->nested
.current_vmptr
) {
4850 kunmap(vmx
->nested
.current_vmcs12_page
);
4851 nested_release_page(vmx
->nested
.current_vmcs12_page
);
4852 vmx
->nested
.current_vmptr
= -1ull;
4853 vmx
->nested
.current_vmcs12
= NULL
;
4856 page
= nested_get_page(vcpu
, vmptr
);
4859 * For accurate processor emulation, VMCLEAR beyond available
4860 * physical memory should do nothing at all. However, it is
4861 * possible that a nested vmx bug, not a guest hypervisor bug,
4862 * resulted in this case, so let's shut down before doing any
4865 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4868 vmcs12
= kmap(page
);
4869 vmcs12
->launch_state
= 0;
4871 nested_release_page(page
);
4873 nested_free_vmcs02(vmx
, vmptr
);
4875 skip_emulated_instruction(vcpu
);
4876 nested_vmx_succeed(vcpu
);
4881 * The exit handlers return 1 if the exit was handled fully and guest execution
4882 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
4883 * to be done to userspace and return 0.
4885 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
4886 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
4887 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
4888 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
4889 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
4890 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
4891 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
4892 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
4893 [EXIT_REASON_CPUID
] = handle_cpuid
,
4894 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
4895 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
4896 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
4897 [EXIT_REASON_HLT
] = handle_halt
,
4898 [EXIT_REASON_INVD
] = handle_invd
,
4899 [EXIT_REASON_INVLPG
] = handle_invlpg
,
4900 [EXIT_REASON_VMCALL
] = handle_vmcall
,
4901 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
4902 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
4903 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
4904 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
4905 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
4906 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
4907 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
4908 [EXIT_REASON_VMOFF
] = handle_vmoff
,
4909 [EXIT_REASON_VMON
] = handle_vmon
,
4910 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
4911 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
4912 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
4913 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
4914 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
4915 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
4916 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
4917 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
4918 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
4919 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
4920 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
4923 static const int kvm_vmx_max_exit_handlers
=
4924 ARRAY_SIZE(kvm_vmx_exit_handlers
);
4926 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4928 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
4929 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
4933 * The guest has exited. See if we can fix it or if we need userspace
4936 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
4938 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4939 u32 exit_reason
= vmx
->exit_reason
;
4940 u32 vectoring_info
= vmx
->idt_vectoring_info
;
4942 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
4944 /* If guest state is invalid, start emulating */
4945 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
4946 return handle_invalid_guest_state(vcpu
);
4948 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
4949 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4950 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
4955 if (unlikely(vmx
->fail
)) {
4956 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4957 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
4958 = vmcs_read32(VM_INSTRUCTION_ERROR
);
4962 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
4963 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
4964 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
4965 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
4966 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
4967 "(0x%x) and exit reason is 0x%x\n",
4968 __func__
, vectoring_info
, exit_reason
);
4970 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
4971 if (vmx_interrupt_allowed(vcpu
)) {
4972 vmx
->soft_vnmi_blocked
= 0;
4973 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
4974 vcpu
->arch
.nmi_pending
) {
4976 * This CPU don't support us in finding the end of an
4977 * NMI-blocked window if the guest runs with IRQs
4978 * disabled. So we pull the trigger after 1 s of
4979 * futile waiting, but inform the user about this.
4981 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
4982 "state on VCPU %d after 1 s timeout\n",
4983 __func__
, vcpu
->vcpu_id
);
4984 vmx
->soft_vnmi_blocked
= 0;
4988 if (exit_reason
< kvm_vmx_max_exit_handlers
4989 && kvm_vmx_exit_handlers
[exit_reason
])
4990 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
4992 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4993 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
4998 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5000 if (irr
== -1 || tpr
< irr
) {
5001 vmcs_write32(TPR_THRESHOLD
, 0);
5005 vmcs_write32(TPR_THRESHOLD
, irr
);
5008 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
5012 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
5013 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
5016 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5017 exit_intr_info
= vmx
->exit_intr_info
;
5019 /* Handle machine checks before interrupts are enabled */
5020 if (is_machine_check(exit_intr_info
))
5021 kvm_machine_check();
5023 /* We need to handle NMIs before interrupts are enabled */
5024 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
5025 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
5026 kvm_before_handle_nmi(&vmx
->vcpu
);
5028 kvm_after_handle_nmi(&vmx
->vcpu
);
5032 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
5037 bool idtv_info_valid
;
5039 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5041 if (cpu_has_virtual_nmis()) {
5042 if (vmx
->nmi_known_unmasked
)
5045 * Can't use vmx->exit_intr_info since we're not sure what
5046 * the exit reason is.
5048 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5049 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
5050 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
5052 * SDM 3: 27.7.1.2 (September 2008)
5053 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5054 * a guest IRET fault.
5055 * SDM 3: 23.2.2 (September 2008)
5056 * Bit 12 is undefined in any of the following cases:
5057 * If the VM exit sets the valid bit in the IDT-vectoring
5058 * information field.
5059 * If the VM exit is due to a double fault.
5061 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
5062 vector
!= DF_VECTOR
&& !idtv_info_valid
)
5063 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5064 GUEST_INTR_STATE_NMI
);
5066 vmx
->nmi_known_unmasked
=
5067 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
5068 & GUEST_INTR_STATE_NMI
);
5069 } else if (unlikely(vmx
->soft_vnmi_blocked
))
5070 vmx
->vnmi_blocked_time
+=
5071 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
5074 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
5075 u32 idt_vectoring_info
,
5076 int instr_len_field
,
5077 int error_code_field
)
5081 bool idtv_info_valid
;
5083 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5085 vmx
->vcpu
.arch
.nmi_injected
= false;
5086 kvm_clear_exception_queue(&vmx
->vcpu
);
5087 kvm_clear_interrupt_queue(&vmx
->vcpu
);
5089 if (!idtv_info_valid
)
5092 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5094 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
5095 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
5098 case INTR_TYPE_NMI_INTR
:
5099 vmx
->vcpu
.arch
.nmi_injected
= true;
5101 * SDM 3: 27.7.1.2 (September 2008)
5102 * Clear bit "block by NMI" before VM entry if a NMI
5105 vmx_set_nmi_mask(&vmx
->vcpu
, false);
5107 case INTR_TYPE_SOFT_EXCEPTION
:
5108 vmx
->vcpu
.arch
.event_exit_inst_len
=
5109 vmcs_read32(instr_len_field
);
5111 case INTR_TYPE_HARD_EXCEPTION
:
5112 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
5113 u32 err
= vmcs_read32(error_code_field
);
5114 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
5116 kvm_queue_exception(&vmx
->vcpu
, vector
);
5118 case INTR_TYPE_SOFT_INTR
:
5119 vmx
->vcpu
.arch
.event_exit_inst_len
=
5120 vmcs_read32(instr_len_field
);
5122 case INTR_TYPE_EXT_INTR
:
5123 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
5124 type
== INTR_TYPE_SOFT_INTR
);
5131 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
5133 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
5134 VM_EXIT_INSTRUCTION_LEN
,
5135 IDT_VECTORING_ERROR_CODE
);
5138 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
5140 __vmx_complete_interrupts(to_vmx(vcpu
),
5141 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
5142 VM_ENTRY_INSTRUCTION_LEN
,
5143 VM_ENTRY_EXCEPTION_ERROR_CODE
);
5145 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
5148 #ifdef CONFIG_X86_64
5156 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
5158 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5160 /* Record the guest's net vcpu time for enforced NMI injections. */
5161 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
5162 vmx
->entry_time
= ktime_get();
5164 /* Don't enter VMX if guest state is invalid, let the exit handler
5165 start emulation until we arrive back to a valid state */
5166 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5169 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
5170 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
5171 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
5172 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
5174 /* When single-stepping over STI and MOV SS, we must clear the
5175 * corresponding interruptibility bits in the guest state. Otherwise
5176 * vmentry fails as it then expects bit 14 (BS) in pending debug
5177 * exceptions being set, but that's not correct for the guest debugging
5179 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
5180 vmx_set_interrupt_shadow(vcpu
, 0);
5182 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
5184 /* Store host registers */
5185 "push %%"R
"dx; push %%"R
"bp;"
5186 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
5188 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
5190 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
5191 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
5193 /* Reload cr2 if changed */
5194 "mov %c[cr2](%0), %%"R
"ax \n\t"
5195 "mov %%cr2, %%"R
"dx \n\t"
5196 "cmp %%"R
"ax, %%"R
"dx \n\t"
5198 "mov %%"R
"ax, %%cr2 \n\t"
5200 /* Check if vmlaunch of vmresume is needed */
5201 "cmpl $0, %c[launched](%0) \n\t"
5202 /* Load guest registers. Don't clobber flags. */
5203 "mov %c[rax](%0), %%"R
"ax \n\t"
5204 "mov %c[rbx](%0), %%"R
"bx \n\t"
5205 "mov %c[rdx](%0), %%"R
"dx \n\t"
5206 "mov %c[rsi](%0), %%"R
"si \n\t"
5207 "mov %c[rdi](%0), %%"R
"di \n\t"
5208 "mov %c[rbp](%0), %%"R
"bp \n\t"
5209 #ifdef CONFIG_X86_64
5210 "mov %c[r8](%0), %%r8 \n\t"
5211 "mov %c[r9](%0), %%r9 \n\t"
5212 "mov %c[r10](%0), %%r10 \n\t"
5213 "mov %c[r11](%0), %%r11 \n\t"
5214 "mov %c[r12](%0), %%r12 \n\t"
5215 "mov %c[r13](%0), %%r13 \n\t"
5216 "mov %c[r14](%0), %%r14 \n\t"
5217 "mov %c[r15](%0), %%r15 \n\t"
5219 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
5221 /* Enter guest mode */
5222 "jne .Llaunched \n\t"
5223 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
5224 "jmp .Lkvm_vmx_return \n\t"
5225 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
5226 ".Lkvm_vmx_return: "
5227 /* Save guest registers, load host registers, keep flags */
5228 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
5230 "mov %%"R
"ax, %c[rax](%0) \n\t"
5231 "mov %%"R
"bx, %c[rbx](%0) \n\t"
5232 "pop"Q
" %c[rcx](%0) \n\t"
5233 "mov %%"R
"dx, %c[rdx](%0) \n\t"
5234 "mov %%"R
"si, %c[rsi](%0) \n\t"
5235 "mov %%"R
"di, %c[rdi](%0) \n\t"
5236 "mov %%"R
"bp, %c[rbp](%0) \n\t"
5237 #ifdef CONFIG_X86_64
5238 "mov %%r8, %c[r8](%0) \n\t"
5239 "mov %%r9, %c[r9](%0) \n\t"
5240 "mov %%r10, %c[r10](%0) \n\t"
5241 "mov %%r11, %c[r11](%0) \n\t"
5242 "mov %%r12, %c[r12](%0) \n\t"
5243 "mov %%r13, %c[r13](%0) \n\t"
5244 "mov %%r14, %c[r14](%0) \n\t"
5245 "mov %%r15, %c[r15](%0) \n\t"
5247 "mov %%cr2, %%"R
"ax \n\t"
5248 "mov %%"R
"ax, %c[cr2](%0) \n\t"
5250 "pop %%"R
"bp; pop %%"R
"dx \n\t"
5251 "setbe %c[fail](%0) \n\t"
5252 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
5253 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
5254 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
5255 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
5256 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
5257 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5258 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5259 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5260 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5261 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5262 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
5263 #ifdef CONFIG_X86_64
5264 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5265 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5266 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5267 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5268 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5269 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5270 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5271 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
5273 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
5274 [wordsize
]"i"(sizeof(ulong
))
5276 , R
"ax", R
"bx", R
"di", R
"si"
5277 #ifdef CONFIG_X86_64
5278 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5282 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
5283 | (1 << VCPU_EXREG_RFLAGS
)
5284 | (1 << VCPU_EXREG_CPL
)
5285 | (1 << VCPU_EXREG_PDPTR
)
5286 | (1 << VCPU_EXREG_SEGMENTS
)
5287 | (1 << VCPU_EXREG_CR3
));
5288 vcpu
->arch
.regs_dirty
= 0;
5290 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
5292 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
5293 vmx
->loaded_vmcs
->launched
= 1;
5295 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5297 vmx_complete_atomic_exit(vmx
);
5298 vmx_recover_nmi_blocking(vmx
);
5299 vmx_complete_interrupts(vmx
);
5305 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
5307 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5311 free_loaded_vmcs(vmx
->loaded_vmcs
);
5312 kfree(vmx
->guest_msrs
);
5313 kvm_vcpu_uninit(vcpu
);
5314 kmem_cache_free(kvm_vcpu_cache
, vmx
);
5317 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
5320 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
5324 return ERR_PTR(-ENOMEM
);
5328 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
5332 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
5334 if (!vmx
->guest_msrs
) {
5338 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
5339 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
5340 if (!vmx
->loaded_vmcs
->vmcs
)
5343 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
5344 loaded_vmcs_init(vmx
->loaded_vmcs
);
5349 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
5350 vmx
->vcpu
.cpu
= cpu
;
5351 err
= vmx_vcpu_setup(vmx
);
5352 vmx_vcpu_put(&vmx
->vcpu
);
5356 if (vm_need_virtualize_apic_accesses(kvm
))
5357 err
= alloc_apic_access_page(kvm
);
5362 if (!kvm
->arch
.ept_identity_map_addr
)
5363 kvm
->arch
.ept_identity_map_addr
=
5364 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
5366 if (alloc_identity_pagetable(kvm
) != 0)
5368 if (!init_rmode_identity_map(kvm
))
5372 vmx
->nested
.current_vmptr
= -1ull;
5373 vmx
->nested
.current_vmcs12
= NULL
;
5378 free_vmcs(vmx
->loaded_vmcs
->vmcs
);
5380 kfree(vmx
->guest_msrs
);
5382 kvm_vcpu_uninit(&vmx
->vcpu
);
5385 kmem_cache_free(kvm_vcpu_cache
, vmx
);
5386 return ERR_PTR(err
);
5389 static void __init
vmx_check_processor_compat(void *rtn
)
5391 struct vmcs_config vmcs_conf
;
5394 if (setup_vmcs_config(&vmcs_conf
) < 0)
5396 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
5397 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
5398 smp_processor_id());
5403 static int get_ept_level(void)
5405 return VMX_EPT_DEFAULT_GAW
+ 1;
5408 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5412 /* For VT-d and EPT combination
5413 * 1. MMIO: always map as UC
5415 * a. VT-d without snooping control feature: can't guarantee the
5416 * result, try to trust guest.
5417 * b. VT-d with snooping control feature: snooping control feature of
5418 * VT-d engine can guarantee the cache correctness. Just set it
5419 * to WB to keep consistent with host. So the same as item 3.
5420 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
5421 * consistent with host MTRR
5424 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
5425 else if (vcpu
->kvm
->arch
.iommu_domain
&&
5426 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
5427 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
5428 VMX_EPT_MT_EPTE_SHIFT
;
5430 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
5436 #define _ER(x) { EXIT_REASON_##x, #x }
5438 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
5440 _ER(EXTERNAL_INTERRUPT
),
5442 _ER(PENDING_INTERRUPT
),
5462 _ER(IO_INSTRUCTION
),
5465 _ER(MWAIT_INSTRUCTION
),
5466 _ER(MONITOR_INSTRUCTION
),
5467 _ER(PAUSE_INSTRUCTION
),
5468 _ER(MCE_DURING_VMENTRY
),
5469 _ER(TPR_BELOW_THRESHOLD
),
5479 static int vmx_get_lpage_level(void)
5481 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
5482 return PT_DIRECTORY_LEVEL
;
5484 /* For shadow and EPT supported 1GB page */
5485 return PT_PDPE_LEVEL
;
5488 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
5490 struct kvm_cpuid_entry2
*best
;
5491 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5494 vmx
->rdtscp_enabled
= false;
5495 if (vmx_rdtscp_supported()) {
5496 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5497 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
5498 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
5499 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
5500 vmx
->rdtscp_enabled
= true;
5502 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5503 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5510 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5514 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
5515 struct x86_instruction_info
*info
,
5516 enum x86_intercept_stage stage
)
5518 return X86EMUL_CONTINUE
;
5521 static struct kvm_x86_ops vmx_x86_ops
= {
5522 .cpu_has_kvm_support
= cpu_has_kvm_support
,
5523 .disabled_by_bios
= vmx_disabled_by_bios
,
5524 .hardware_setup
= hardware_setup
,
5525 .hardware_unsetup
= hardware_unsetup
,
5526 .check_processor_compatibility
= vmx_check_processor_compat
,
5527 .hardware_enable
= hardware_enable
,
5528 .hardware_disable
= hardware_disable
,
5529 .cpu_has_accelerated_tpr
= report_flexpriority
,
5531 .vcpu_create
= vmx_create_vcpu
,
5532 .vcpu_free
= vmx_free_vcpu
,
5533 .vcpu_reset
= vmx_vcpu_reset
,
5535 .prepare_guest_switch
= vmx_save_host_state
,
5536 .vcpu_load
= vmx_vcpu_load
,
5537 .vcpu_put
= vmx_vcpu_put
,
5539 .set_guest_debug
= set_guest_debug
,
5540 .get_msr
= vmx_get_msr
,
5541 .set_msr
= vmx_set_msr
,
5542 .get_segment_base
= vmx_get_segment_base
,
5543 .get_segment
= vmx_get_segment
,
5544 .set_segment
= vmx_set_segment
,
5545 .get_cpl
= vmx_get_cpl
,
5546 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
5547 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
5548 .decache_cr3
= vmx_decache_cr3
,
5549 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
5550 .set_cr0
= vmx_set_cr0
,
5551 .set_cr3
= vmx_set_cr3
,
5552 .set_cr4
= vmx_set_cr4
,
5553 .set_efer
= vmx_set_efer
,
5554 .get_idt
= vmx_get_idt
,
5555 .set_idt
= vmx_set_idt
,
5556 .get_gdt
= vmx_get_gdt
,
5557 .set_gdt
= vmx_set_gdt
,
5558 .set_dr7
= vmx_set_dr7
,
5559 .cache_reg
= vmx_cache_reg
,
5560 .get_rflags
= vmx_get_rflags
,
5561 .set_rflags
= vmx_set_rflags
,
5562 .fpu_activate
= vmx_fpu_activate
,
5563 .fpu_deactivate
= vmx_fpu_deactivate
,
5565 .tlb_flush
= vmx_flush_tlb
,
5567 .run
= vmx_vcpu_run
,
5568 .handle_exit
= vmx_handle_exit
,
5569 .skip_emulated_instruction
= skip_emulated_instruction
,
5570 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
5571 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
5572 .patch_hypercall
= vmx_patch_hypercall
,
5573 .set_irq
= vmx_inject_irq
,
5574 .set_nmi
= vmx_inject_nmi
,
5575 .queue_exception
= vmx_queue_exception
,
5576 .cancel_injection
= vmx_cancel_injection
,
5577 .interrupt_allowed
= vmx_interrupt_allowed
,
5578 .nmi_allowed
= vmx_nmi_allowed
,
5579 .get_nmi_mask
= vmx_get_nmi_mask
,
5580 .set_nmi_mask
= vmx_set_nmi_mask
,
5581 .enable_nmi_window
= enable_nmi_window
,
5582 .enable_irq_window
= enable_irq_window
,
5583 .update_cr8_intercept
= update_cr8_intercept
,
5585 .set_tss_addr
= vmx_set_tss_addr
,
5586 .get_tdp_level
= get_ept_level
,
5587 .get_mt_mask
= vmx_get_mt_mask
,
5589 .get_exit_info
= vmx_get_exit_info
,
5590 .exit_reasons_str
= vmx_exit_reasons_str
,
5592 .get_lpage_level
= vmx_get_lpage_level
,
5594 .cpuid_update
= vmx_cpuid_update
,
5596 .rdtscp_supported
= vmx_rdtscp_supported
,
5598 .set_supported_cpuid
= vmx_set_supported_cpuid
,
5600 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
5602 .set_tsc_khz
= vmx_set_tsc_khz
,
5603 .write_tsc_offset
= vmx_write_tsc_offset
,
5604 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
5605 .compute_tsc_offset
= vmx_compute_tsc_offset
,
5607 .set_tdp_cr3
= vmx_set_cr3
,
5609 .check_intercept
= vmx_check_intercept
,
5612 static int __init
vmx_init(void)
5616 rdmsrl_safe(MSR_EFER
, &host_efer
);
5618 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
5619 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5621 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5622 if (!vmx_io_bitmap_a
)
5625 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5626 if (!vmx_io_bitmap_b
) {
5631 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5632 if (!vmx_msr_bitmap_legacy
) {
5637 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5638 if (!vmx_msr_bitmap_longmode
) {
5644 * Allow direct access to the PC debug port (it is often used for I/O
5645 * delays, but the vmexits simply slow things down).
5647 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
5648 clear_bit(0x80, vmx_io_bitmap_a
);
5650 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
5652 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
5653 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
5655 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
5657 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
5658 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
5662 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
5663 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
5664 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
5665 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
5666 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
5667 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
5670 bypass_guest_pf
= 0;
5671 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5672 VMX_EPT_EXECUTABLE_MASK
);
5677 if (bypass_guest_pf
)
5678 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
5683 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5685 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5687 free_page((unsigned long)vmx_io_bitmap_b
);
5689 free_page((unsigned long)vmx_io_bitmap_a
);
5693 static void __exit
vmx_exit(void)
5695 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5696 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5697 free_page((unsigned long)vmx_io_bitmap_b
);
5698 free_page((unsigned long)vmx_io_bitmap_a
);
5703 module_init(vmx_init
)
5704 module_exit(vmx_exit
)