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KVM: VMX: Avoid duplicate ept tlb flush when setting cr3
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int __read_mostly bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, S_IRUGO);
44
45 static int __read_mostly enable_vpid = 1;
46 module_param_named(vpid, enable_vpid, bool, 0444);
47
48 static int __read_mostly flexpriority_enabled = 1;
49 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
50
51 static int __read_mostly enable_ept = 1;
52 module_param_named(ept, enable_ept, bool, S_IRUGO);
53
54 static int __read_mostly emulate_invalid_guest_state = 0;
55 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
56
57 struct vmcs {
58 u32 revision_id;
59 u32 abort;
60 char data[0];
61 };
62
63 struct vcpu_vmx {
64 struct kvm_vcpu vcpu;
65 struct list_head local_vcpus_link;
66 unsigned long host_rsp;
67 int launched;
68 u8 fail;
69 u32 idt_vectoring_info;
70 struct kvm_msr_entry *guest_msrs;
71 struct kvm_msr_entry *host_msrs;
72 int nmsrs;
73 int save_nmsrs;
74 int msr_offset_efer;
75 #ifdef CONFIG_X86_64
76 int msr_offset_kernel_gs_base;
77 #endif
78 struct vmcs *vmcs;
79 struct {
80 int loaded;
81 u16 fs_sel, gs_sel, ldt_sel;
82 int gs_ldt_reload_needed;
83 int fs_reload_needed;
84 int guest_efer_loaded;
85 } host_state;
86 struct {
87 struct {
88 bool pending;
89 u8 vector;
90 unsigned rip;
91 } irq;
92 } rmode;
93 int vpid;
94 bool emulation_required;
95 enum emulation_result invalid_state_emulation_result;
96
97 /* Support for vnmi-less CPUs */
98 int soft_vnmi_blocked;
99 ktime_t entry_time;
100 s64 vnmi_blocked_time;
101 u32 exit_reason;
102 };
103
104 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
105 {
106 return container_of(vcpu, struct vcpu_vmx, vcpu);
107 }
108
109 static int init_rmode(struct kvm *kvm);
110 static u64 construct_eptp(unsigned long root_hpa);
111
112 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
113 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
114 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
115
116 static unsigned long *vmx_io_bitmap_a;
117 static unsigned long *vmx_io_bitmap_b;
118 static unsigned long *vmx_msr_bitmap_legacy;
119 static unsigned long *vmx_msr_bitmap_longmode;
120
121 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
122 static DEFINE_SPINLOCK(vmx_vpid_lock);
123
124 static struct vmcs_config {
125 int size;
126 int order;
127 u32 revision_id;
128 u32 pin_based_exec_ctrl;
129 u32 cpu_based_exec_ctrl;
130 u32 cpu_based_2nd_exec_ctrl;
131 u32 vmexit_ctrl;
132 u32 vmentry_ctrl;
133 } vmcs_config;
134
135 static struct vmx_capability {
136 u32 ept;
137 u32 vpid;
138 } vmx_capability;
139
140 #define VMX_SEGMENT_FIELD(seg) \
141 [VCPU_SREG_##seg] = { \
142 .selector = GUEST_##seg##_SELECTOR, \
143 .base = GUEST_##seg##_BASE, \
144 .limit = GUEST_##seg##_LIMIT, \
145 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 }
147
148 static struct kvm_vmx_segment_field {
149 unsigned selector;
150 unsigned base;
151 unsigned limit;
152 unsigned ar_bytes;
153 } kvm_vmx_segment_fields[] = {
154 VMX_SEGMENT_FIELD(CS),
155 VMX_SEGMENT_FIELD(DS),
156 VMX_SEGMENT_FIELD(ES),
157 VMX_SEGMENT_FIELD(FS),
158 VMX_SEGMENT_FIELD(GS),
159 VMX_SEGMENT_FIELD(SS),
160 VMX_SEGMENT_FIELD(TR),
161 VMX_SEGMENT_FIELD(LDTR),
162 };
163
164 /*
165 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
166 * away by decrementing the array size.
167 */
168 static const u32 vmx_msr_index[] = {
169 #ifdef CONFIG_X86_64
170 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
171 #endif
172 MSR_EFER, MSR_K6_STAR,
173 };
174 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
175
176 static void load_msrs(struct kvm_msr_entry *e, int n)
177 {
178 int i;
179
180 for (i = 0; i < n; ++i)
181 wrmsrl(e[i].index, e[i].data);
182 }
183
184 static void save_msrs(struct kvm_msr_entry *e, int n)
185 {
186 int i;
187
188 for (i = 0; i < n; ++i)
189 rdmsrl(e[i].index, e[i].data);
190 }
191
192 static inline int is_page_fault(u32 intr_info)
193 {
194 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
195 INTR_INFO_VALID_MASK)) ==
196 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
197 }
198
199 static inline int is_no_device(u32 intr_info)
200 {
201 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
202 INTR_INFO_VALID_MASK)) ==
203 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
204 }
205
206 static inline int is_invalid_opcode(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_external_interrupt(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
216 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
217 }
218
219 static inline int is_machine_check(u32 intr_info)
220 {
221 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
222 INTR_INFO_VALID_MASK)) ==
223 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
224 }
225
226 static inline int cpu_has_vmx_msr_bitmap(void)
227 {
228 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
229 }
230
231 static inline int cpu_has_vmx_tpr_shadow(void)
232 {
233 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
234 }
235
236 static inline int vm_need_tpr_shadow(struct kvm *kvm)
237 {
238 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
239 }
240
241 static inline int cpu_has_secondary_exec_ctrls(void)
242 {
243 return vmcs_config.cpu_based_exec_ctrl &
244 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
245 }
246
247 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
248 {
249 return vmcs_config.cpu_based_2nd_exec_ctrl &
250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
251 }
252
253 static inline bool cpu_has_vmx_flexpriority(void)
254 {
255 return cpu_has_vmx_tpr_shadow() &&
256 cpu_has_vmx_virtualize_apic_accesses();
257 }
258
259 static inline int cpu_has_vmx_invept_individual_addr(void)
260 {
261 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
262 }
263
264 static inline int cpu_has_vmx_invept_context(void)
265 {
266 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
267 }
268
269 static inline int cpu_has_vmx_invept_global(void)
270 {
271 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
272 }
273
274 static inline int cpu_has_vmx_ept(void)
275 {
276 return vmcs_config.cpu_based_2nd_exec_ctrl &
277 SECONDARY_EXEC_ENABLE_EPT;
278 }
279
280 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
281 {
282 return flexpriority_enabled &&
283 (cpu_has_vmx_virtualize_apic_accesses()) &&
284 (irqchip_in_kernel(kvm));
285 }
286
287 static inline int cpu_has_vmx_vpid(void)
288 {
289 return vmcs_config.cpu_based_2nd_exec_ctrl &
290 SECONDARY_EXEC_ENABLE_VPID;
291 }
292
293 static inline int cpu_has_virtual_nmis(void)
294 {
295 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
296 }
297
298 static inline bool report_flexpriority(void)
299 {
300 return flexpriority_enabled;
301 }
302
303 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
304 {
305 int i;
306
307 for (i = 0; i < vmx->nmsrs; ++i)
308 if (vmx->guest_msrs[i].index == msr)
309 return i;
310 return -1;
311 }
312
313 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
314 {
315 struct {
316 u64 vpid : 16;
317 u64 rsvd : 48;
318 u64 gva;
319 } operand = { vpid, 0, gva };
320
321 asm volatile (__ex(ASM_VMX_INVVPID)
322 /* CF==1 or ZF==1 --> rc = -1 */
323 "; ja 1f ; ud2 ; 1:"
324 : : "a"(&operand), "c"(ext) : "cc", "memory");
325 }
326
327 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
328 {
329 struct {
330 u64 eptp, gpa;
331 } operand = {eptp, gpa};
332
333 asm volatile (__ex(ASM_VMX_INVEPT)
334 /* CF==1 or ZF==1 --> rc = -1 */
335 "; ja 1f ; ud2 ; 1:\n"
336 : : "a" (&operand), "c" (ext) : "cc", "memory");
337 }
338
339 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
340 {
341 int i;
342
343 i = __find_msr_index(vmx, msr);
344 if (i >= 0)
345 return &vmx->guest_msrs[i];
346 return NULL;
347 }
348
349 static void vmcs_clear(struct vmcs *vmcs)
350 {
351 u64 phys_addr = __pa(vmcs);
352 u8 error;
353
354 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
355 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
356 : "cc", "memory");
357 if (error)
358 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
359 vmcs, phys_addr);
360 }
361
362 static void __vcpu_clear(void *arg)
363 {
364 struct vcpu_vmx *vmx = arg;
365 int cpu = raw_smp_processor_id();
366
367 if (vmx->vcpu.cpu == cpu)
368 vmcs_clear(vmx->vmcs);
369 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
370 per_cpu(current_vmcs, cpu) = NULL;
371 rdtscll(vmx->vcpu.arch.host_tsc);
372 list_del(&vmx->local_vcpus_link);
373 vmx->vcpu.cpu = -1;
374 vmx->launched = 0;
375 }
376
377 static void vcpu_clear(struct vcpu_vmx *vmx)
378 {
379 if (vmx->vcpu.cpu == -1)
380 return;
381 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
382 }
383
384 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
385 {
386 if (vmx->vpid == 0)
387 return;
388
389 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
390 }
391
392 static inline void ept_sync_global(void)
393 {
394 if (cpu_has_vmx_invept_global())
395 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
396 }
397
398 static inline void ept_sync_context(u64 eptp)
399 {
400 if (enable_ept) {
401 if (cpu_has_vmx_invept_context())
402 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
403 else
404 ept_sync_global();
405 }
406 }
407
408 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
409 {
410 if (enable_ept) {
411 if (cpu_has_vmx_invept_individual_addr())
412 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
413 eptp, gpa);
414 else
415 ept_sync_context(eptp);
416 }
417 }
418
419 static unsigned long vmcs_readl(unsigned long field)
420 {
421 unsigned long value;
422
423 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
424 : "=a"(value) : "d"(field) : "cc");
425 return value;
426 }
427
428 static u16 vmcs_read16(unsigned long field)
429 {
430 return vmcs_readl(field);
431 }
432
433 static u32 vmcs_read32(unsigned long field)
434 {
435 return vmcs_readl(field);
436 }
437
438 static u64 vmcs_read64(unsigned long field)
439 {
440 #ifdef CONFIG_X86_64
441 return vmcs_readl(field);
442 #else
443 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
444 #endif
445 }
446
447 static noinline void vmwrite_error(unsigned long field, unsigned long value)
448 {
449 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
450 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
451 dump_stack();
452 }
453
454 static void vmcs_writel(unsigned long field, unsigned long value)
455 {
456 u8 error;
457
458 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
459 : "=q"(error) : "a"(value), "d"(field) : "cc");
460 if (unlikely(error))
461 vmwrite_error(field, value);
462 }
463
464 static void vmcs_write16(unsigned long field, u16 value)
465 {
466 vmcs_writel(field, value);
467 }
468
469 static void vmcs_write32(unsigned long field, u32 value)
470 {
471 vmcs_writel(field, value);
472 }
473
474 static void vmcs_write64(unsigned long field, u64 value)
475 {
476 vmcs_writel(field, value);
477 #ifndef CONFIG_X86_64
478 asm volatile ("");
479 vmcs_writel(field+1, value >> 32);
480 #endif
481 }
482
483 static void vmcs_clear_bits(unsigned long field, u32 mask)
484 {
485 vmcs_writel(field, vmcs_readl(field) & ~mask);
486 }
487
488 static void vmcs_set_bits(unsigned long field, u32 mask)
489 {
490 vmcs_writel(field, vmcs_readl(field) | mask);
491 }
492
493 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
494 {
495 u32 eb;
496
497 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
498 if (!vcpu->fpu_active)
499 eb |= 1u << NM_VECTOR;
500 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
501 if (vcpu->guest_debug &
502 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
503 eb |= 1u << DB_VECTOR;
504 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
505 eb |= 1u << BP_VECTOR;
506 }
507 if (vcpu->arch.rmode.vm86_active)
508 eb = ~0;
509 if (enable_ept)
510 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
511 vmcs_write32(EXCEPTION_BITMAP, eb);
512 }
513
514 static void reload_tss(void)
515 {
516 /*
517 * VT restores TR but not its size. Useless.
518 */
519 struct descriptor_table gdt;
520 struct desc_struct *descs;
521
522 kvm_get_gdt(&gdt);
523 descs = (void *)gdt.base;
524 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
525 load_TR_desc();
526 }
527
528 static void load_transition_efer(struct vcpu_vmx *vmx)
529 {
530 int efer_offset = vmx->msr_offset_efer;
531 u64 host_efer = vmx->host_msrs[efer_offset].data;
532 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
533 u64 ignore_bits;
534
535 if (efer_offset < 0)
536 return;
537 /*
538 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
539 * outside long mode
540 */
541 ignore_bits = EFER_NX | EFER_SCE;
542 #ifdef CONFIG_X86_64
543 ignore_bits |= EFER_LMA | EFER_LME;
544 /* SCE is meaningful only in long mode on Intel */
545 if (guest_efer & EFER_LMA)
546 ignore_bits &= ~(u64)EFER_SCE;
547 #endif
548 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
549 return;
550
551 vmx->host_state.guest_efer_loaded = 1;
552 guest_efer &= ~ignore_bits;
553 guest_efer |= host_efer & ignore_bits;
554 wrmsrl(MSR_EFER, guest_efer);
555 vmx->vcpu.stat.efer_reload++;
556 }
557
558 static void reload_host_efer(struct vcpu_vmx *vmx)
559 {
560 if (vmx->host_state.guest_efer_loaded) {
561 vmx->host_state.guest_efer_loaded = 0;
562 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
563 }
564 }
565
566 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
567 {
568 struct vcpu_vmx *vmx = to_vmx(vcpu);
569
570 if (vmx->host_state.loaded)
571 return;
572
573 vmx->host_state.loaded = 1;
574 /*
575 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
576 * allow segment selectors with cpl > 0 or ti == 1.
577 */
578 vmx->host_state.ldt_sel = kvm_read_ldt();
579 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
580 vmx->host_state.fs_sel = kvm_read_fs();
581 if (!(vmx->host_state.fs_sel & 7)) {
582 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
583 vmx->host_state.fs_reload_needed = 0;
584 } else {
585 vmcs_write16(HOST_FS_SELECTOR, 0);
586 vmx->host_state.fs_reload_needed = 1;
587 }
588 vmx->host_state.gs_sel = kvm_read_gs();
589 if (!(vmx->host_state.gs_sel & 7))
590 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
591 else {
592 vmcs_write16(HOST_GS_SELECTOR, 0);
593 vmx->host_state.gs_ldt_reload_needed = 1;
594 }
595
596 #ifdef CONFIG_X86_64
597 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
598 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
599 #else
600 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
601 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
602 #endif
603
604 #ifdef CONFIG_X86_64
605 if (is_long_mode(&vmx->vcpu))
606 save_msrs(vmx->host_msrs +
607 vmx->msr_offset_kernel_gs_base, 1);
608
609 #endif
610 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
611 load_transition_efer(vmx);
612 }
613
614 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
615 {
616 unsigned long flags;
617
618 if (!vmx->host_state.loaded)
619 return;
620
621 ++vmx->vcpu.stat.host_state_reload;
622 vmx->host_state.loaded = 0;
623 if (vmx->host_state.fs_reload_needed)
624 kvm_load_fs(vmx->host_state.fs_sel);
625 if (vmx->host_state.gs_ldt_reload_needed) {
626 kvm_load_ldt(vmx->host_state.ldt_sel);
627 /*
628 * If we have to reload gs, we must take care to
629 * preserve our gs base.
630 */
631 local_irq_save(flags);
632 kvm_load_gs(vmx->host_state.gs_sel);
633 #ifdef CONFIG_X86_64
634 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
635 #endif
636 local_irq_restore(flags);
637 }
638 reload_tss();
639 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
640 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
641 reload_host_efer(vmx);
642 }
643
644 static void vmx_load_host_state(struct vcpu_vmx *vmx)
645 {
646 preempt_disable();
647 __vmx_load_host_state(vmx);
648 preempt_enable();
649 }
650
651 /*
652 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
653 * vcpu mutex is already taken.
654 */
655 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
656 {
657 struct vcpu_vmx *vmx = to_vmx(vcpu);
658 u64 phys_addr = __pa(vmx->vmcs);
659 u64 tsc_this, delta, new_offset;
660
661 if (vcpu->cpu != cpu) {
662 vcpu_clear(vmx);
663 kvm_migrate_timers(vcpu);
664 vpid_sync_vcpu_all(vmx);
665 local_irq_disable();
666 list_add(&vmx->local_vcpus_link,
667 &per_cpu(vcpus_on_cpu, cpu));
668 local_irq_enable();
669 }
670
671 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
672 u8 error;
673
674 per_cpu(current_vmcs, cpu) = vmx->vmcs;
675 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
676 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
677 : "cc");
678 if (error)
679 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
680 vmx->vmcs, phys_addr);
681 }
682
683 if (vcpu->cpu != cpu) {
684 struct descriptor_table dt;
685 unsigned long sysenter_esp;
686
687 vcpu->cpu = cpu;
688 /*
689 * Linux uses per-cpu TSS and GDT, so set these when switching
690 * processors.
691 */
692 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
693 kvm_get_gdt(&dt);
694 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
695
696 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
697 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
698
699 /*
700 * Make sure the time stamp counter is monotonous.
701 */
702 rdtscll(tsc_this);
703 if (tsc_this < vcpu->arch.host_tsc) {
704 delta = vcpu->arch.host_tsc - tsc_this;
705 new_offset = vmcs_read64(TSC_OFFSET) + delta;
706 vmcs_write64(TSC_OFFSET, new_offset);
707 }
708 }
709 }
710
711 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
712 {
713 __vmx_load_host_state(to_vmx(vcpu));
714 }
715
716 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
717 {
718 if (vcpu->fpu_active)
719 return;
720 vcpu->fpu_active = 1;
721 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
722 if (vcpu->arch.cr0 & X86_CR0_TS)
723 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
724 update_exception_bitmap(vcpu);
725 }
726
727 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
728 {
729 if (!vcpu->fpu_active)
730 return;
731 vcpu->fpu_active = 0;
732 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
733 update_exception_bitmap(vcpu);
734 }
735
736 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
737 {
738 return vmcs_readl(GUEST_RFLAGS);
739 }
740
741 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
742 {
743 if (vcpu->arch.rmode.vm86_active)
744 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
745 vmcs_writel(GUEST_RFLAGS, rflags);
746 }
747
748 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
749 {
750 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
751 int ret = 0;
752
753 if (interruptibility & GUEST_INTR_STATE_STI)
754 ret |= X86_SHADOW_INT_STI;
755 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
756 ret |= X86_SHADOW_INT_MOV_SS;
757
758 return ret & mask;
759 }
760
761 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
762 {
763 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
764 u32 interruptibility = interruptibility_old;
765
766 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
767
768 if (mask & X86_SHADOW_INT_MOV_SS)
769 interruptibility |= GUEST_INTR_STATE_MOV_SS;
770 if (mask & X86_SHADOW_INT_STI)
771 interruptibility |= GUEST_INTR_STATE_STI;
772
773 if ((interruptibility != interruptibility_old))
774 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
775 }
776
777 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
778 {
779 unsigned long rip;
780
781 rip = kvm_rip_read(vcpu);
782 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
783 kvm_rip_write(vcpu, rip);
784
785 /* skipping an emulated instruction also counts */
786 vmx_set_interrupt_shadow(vcpu, 0);
787 }
788
789 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
790 bool has_error_code, u32 error_code)
791 {
792 struct vcpu_vmx *vmx = to_vmx(vcpu);
793 u32 intr_info = nr | INTR_INFO_VALID_MASK;
794
795 if (has_error_code) {
796 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
797 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
798 }
799
800 if (vcpu->arch.rmode.vm86_active) {
801 vmx->rmode.irq.pending = true;
802 vmx->rmode.irq.vector = nr;
803 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
804 if (kvm_exception_is_soft(nr))
805 vmx->rmode.irq.rip +=
806 vmx->vcpu.arch.event_exit_inst_len;
807 intr_info |= INTR_TYPE_SOFT_INTR;
808 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
809 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
810 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
811 return;
812 }
813
814 if (kvm_exception_is_soft(nr)) {
815 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
816 vmx->vcpu.arch.event_exit_inst_len);
817 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
818 } else
819 intr_info |= INTR_TYPE_HARD_EXCEPTION;
820
821 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
822 }
823
824 /*
825 * Swap MSR entry in host/guest MSR entry array.
826 */
827 #ifdef CONFIG_X86_64
828 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
829 {
830 struct kvm_msr_entry tmp;
831
832 tmp = vmx->guest_msrs[to];
833 vmx->guest_msrs[to] = vmx->guest_msrs[from];
834 vmx->guest_msrs[from] = tmp;
835 tmp = vmx->host_msrs[to];
836 vmx->host_msrs[to] = vmx->host_msrs[from];
837 vmx->host_msrs[from] = tmp;
838 }
839 #endif
840
841 /*
842 * Set up the vmcs to automatically save and restore system
843 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
844 * mode, as fiddling with msrs is very expensive.
845 */
846 static void setup_msrs(struct vcpu_vmx *vmx)
847 {
848 int save_nmsrs;
849 unsigned long *msr_bitmap;
850
851 vmx_load_host_state(vmx);
852 save_nmsrs = 0;
853 #ifdef CONFIG_X86_64
854 if (is_long_mode(&vmx->vcpu)) {
855 int index;
856
857 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
858 if (index >= 0)
859 move_msr_up(vmx, index, save_nmsrs++);
860 index = __find_msr_index(vmx, MSR_LSTAR);
861 if (index >= 0)
862 move_msr_up(vmx, index, save_nmsrs++);
863 index = __find_msr_index(vmx, MSR_CSTAR);
864 if (index >= 0)
865 move_msr_up(vmx, index, save_nmsrs++);
866 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
867 if (index >= 0)
868 move_msr_up(vmx, index, save_nmsrs++);
869 /*
870 * MSR_K6_STAR is only needed on long mode guests, and only
871 * if efer.sce is enabled.
872 */
873 index = __find_msr_index(vmx, MSR_K6_STAR);
874 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
875 move_msr_up(vmx, index, save_nmsrs++);
876 }
877 #endif
878 vmx->save_nmsrs = save_nmsrs;
879
880 #ifdef CONFIG_X86_64
881 vmx->msr_offset_kernel_gs_base =
882 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
883 #endif
884 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
885
886 if (cpu_has_vmx_msr_bitmap()) {
887 if (is_long_mode(&vmx->vcpu))
888 msr_bitmap = vmx_msr_bitmap_longmode;
889 else
890 msr_bitmap = vmx_msr_bitmap_legacy;
891
892 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
893 }
894 }
895
896 /*
897 * reads and returns guest's timestamp counter "register"
898 * guest_tsc = host_tsc + tsc_offset -- 21.3
899 */
900 static u64 guest_read_tsc(void)
901 {
902 u64 host_tsc, tsc_offset;
903
904 rdtscll(host_tsc);
905 tsc_offset = vmcs_read64(TSC_OFFSET);
906 return host_tsc + tsc_offset;
907 }
908
909 /*
910 * writes 'guest_tsc' into guest's timestamp counter "register"
911 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
912 */
913 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
914 {
915 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
916 }
917
918 /*
919 * Reads an msr value (of 'msr_index') into 'pdata'.
920 * Returns 0 on success, non-0 otherwise.
921 * Assumes vcpu_load() was already called.
922 */
923 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
924 {
925 u64 data;
926 struct kvm_msr_entry *msr;
927
928 if (!pdata) {
929 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
930 return -EINVAL;
931 }
932
933 switch (msr_index) {
934 #ifdef CONFIG_X86_64
935 case MSR_FS_BASE:
936 data = vmcs_readl(GUEST_FS_BASE);
937 break;
938 case MSR_GS_BASE:
939 data = vmcs_readl(GUEST_GS_BASE);
940 break;
941 case MSR_EFER:
942 return kvm_get_msr_common(vcpu, msr_index, pdata);
943 #endif
944 case MSR_IA32_TSC:
945 data = guest_read_tsc();
946 break;
947 case MSR_IA32_SYSENTER_CS:
948 data = vmcs_read32(GUEST_SYSENTER_CS);
949 break;
950 case MSR_IA32_SYSENTER_EIP:
951 data = vmcs_readl(GUEST_SYSENTER_EIP);
952 break;
953 case MSR_IA32_SYSENTER_ESP:
954 data = vmcs_readl(GUEST_SYSENTER_ESP);
955 break;
956 default:
957 vmx_load_host_state(to_vmx(vcpu));
958 msr = find_msr_entry(to_vmx(vcpu), msr_index);
959 if (msr) {
960 data = msr->data;
961 break;
962 }
963 return kvm_get_msr_common(vcpu, msr_index, pdata);
964 }
965
966 *pdata = data;
967 return 0;
968 }
969
970 /*
971 * Writes msr value into into the appropriate "register".
972 * Returns 0 on success, non-0 otherwise.
973 * Assumes vcpu_load() was already called.
974 */
975 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
976 {
977 struct vcpu_vmx *vmx = to_vmx(vcpu);
978 struct kvm_msr_entry *msr;
979 u64 host_tsc;
980 int ret = 0;
981
982 switch (msr_index) {
983 case MSR_EFER:
984 vmx_load_host_state(vmx);
985 ret = kvm_set_msr_common(vcpu, msr_index, data);
986 break;
987 #ifdef CONFIG_X86_64
988 case MSR_FS_BASE:
989 vmcs_writel(GUEST_FS_BASE, data);
990 break;
991 case MSR_GS_BASE:
992 vmcs_writel(GUEST_GS_BASE, data);
993 break;
994 #endif
995 case MSR_IA32_SYSENTER_CS:
996 vmcs_write32(GUEST_SYSENTER_CS, data);
997 break;
998 case MSR_IA32_SYSENTER_EIP:
999 vmcs_writel(GUEST_SYSENTER_EIP, data);
1000 break;
1001 case MSR_IA32_SYSENTER_ESP:
1002 vmcs_writel(GUEST_SYSENTER_ESP, data);
1003 break;
1004 case MSR_IA32_TSC:
1005 rdtscll(host_tsc);
1006 guest_write_tsc(data, host_tsc);
1007 break;
1008 case MSR_P6_PERFCTR0:
1009 case MSR_P6_PERFCTR1:
1010 case MSR_P6_EVNTSEL0:
1011 case MSR_P6_EVNTSEL1:
1012 /*
1013 * Just discard all writes to the performance counters; this
1014 * should keep both older linux and windows 64-bit guests
1015 * happy
1016 */
1017 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
1018
1019 break;
1020 case MSR_IA32_CR_PAT:
1021 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1022 vmcs_write64(GUEST_IA32_PAT, data);
1023 vcpu->arch.pat = data;
1024 break;
1025 }
1026 /* Otherwise falls through to kvm_set_msr_common */
1027 default:
1028 vmx_load_host_state(vmx);
1029 msr = find_msr_entry(vmx, msr_index);
1030 if (msr) {
1031 msr->data = data;
1032 break;
1033 }
1034 ret = kvm_set_msr_common(vcpu, msr_index, data);
1035 }
1036
1037 return ret;
1038 }
1039
1040 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1041 {
1042 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1043 switch (reg) {
1044 case VCPU_REGS_RSP:
1045 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1046 break;
1047 case VCPU_REGS_RIP:
1048 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1049 break;
1050 default:
1051 break;
1052 }
1053 }
1054
1055 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1056 {
1057 int old_debug = vcpu->guest_debug;
1058 unsigned long flags;
1059
1060 vcpu->guest_debug = dbg->control;
1061 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1062 vcpu->guest_debug = 0;
1063
1064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1065 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1066 else
1067 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1068
1069 flags = vmcs_readl(GUEST_RFLAGS);
1070 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1071 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1072 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1073 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1074 vmcs_writel(GUEST_RFLAGS, flags);
1075
1076 update_exception_bitmap(vcpu);
1077
1078 return 0;
1079 }
1080
1081 static __init int cpu_has_kvm_support(void)
1082 {
1083 return cpu_has_vmx();
1084 }
1085
1086 static __init int vmx_disabled_by_bios(void)
1087 {
1088 u64 msr;
1089
1090 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1091 return (msr & (FEATURE_CONTROL_LOCKED |
1092 FEATURE_CONTROL_VMXON_ENABLED))
1093 == FEATURE_CONTROL_LOCKED;
1094 /* locked but not enabled */
1095 }
1096
1097 static void hardware_enable(void *garbage)
1098 {
1099 int cpu = raw_smp_processor_id();
1100 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1101 u64 old;
1102
1103 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1104 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1105 if ((old & (FEATURE_CONTROL_LOCKED |
1106 FEATURE_CONTROL_VMXON_ENABLED))
1107 != (FEATURE_CONTROL_LOCKED |
1108 FEATURE_CONTROL_VMXON_ENABLED))
1109 /* enable and lock */
1110 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1111 FEATURE_CONTROL_LOCKED |
1112 FEATURE_CONTROL_VMXON_ENABLED);
1113 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1114 asm volatile (ASM_VMX_VMXON_RAX
1115 : : "a"(&phys_addr), "m"(phys_addr)
1116 : "memory", "cc");
1117 }
1118
1119 static void vmclear_local_vcpus(void)
1120 {
1121 int cpu = raw_smp_processor_id();
1122 struct vcpu_vmx *vmx, *n;
1123
1124 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1125 local_vcpus_link)
1126 __vcpu_clear(vmx);
1127 }
1128
1129
1130 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1131 * tricks.
1132 */
1133 static void kvm_cpu_vmxoff(void)
1134 {
1135 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1136 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1137 }
1138
1139 static void hardware_disable(void *garbage)
1140 {
1141 vmclear_local_vcpus();
1142 kvm_cpu_vmxoff();
1143 }
1144
1145 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1146 u32 msr, u32 *result)
1147 {
1148 u32 vmx_msr_low, vmx_msr_high;
1149 u32 ctl = ctl_min | ctl_opt;
1150
1151 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1152
1153 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1154 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1155
1156 /* Ensure minimum (required) set of control bits are supported. */
1157 if (ctl_min & ~ctl)
1158 return -EIO;
1159
1160 *result = ctl;
1161 return 0;
1162 }
1163
1164 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1165 {
1166 u32 vmx_msr_low, vmx_msr_high;
1167 u32 min, opt, min2, opt2;
1168 u32 _pin_based_exec_control = 0;
1169 u32 _cpu_based_exec_control = 0;
1170 u32 _cpu_based_2nd_exec_control = 0;
1171 u32 _vmexit_control = 0;
1172 u32 _vmentry_control = 0;
1173
1174 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1175 opt = PIN_BASED_VIRTUAL_NMIS;
1176 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1177 &_pin_based_exec_control) < 0)
1178 return -EIO;
1179
1180 min = CPU_BASED_HLT_EXITING |
1181 #ifdef CONFIG_X86_64
1182 CPU_BASED_CR8_LOAD_EXITING |
1183 CPU_BASED_CR8_STORE_EXITING |
1184 #endif
1185 CPU_BASED_CR3_LOAD_EXITING |
1186 CPU_BASED_CR3_STORE_EXITING |
1187 CPU_BASED_USE_IO_BITMAPS |
1188 CPU_BASED_MOV_DR_EXITING |
1189 CPU_BASED_USE_TSC_OFFSETING |
1190 CPU_BASED_INVLPG_EXITING;
1191 opt = CPU_BASED_TPR_SHADOW |
1192 CPU_BASED_USE_MSR_BITMAPS |
1193 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1194 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1195 &_cpu_based_exec_control) < 0)
1196 return -EIO;
1197 #ifdef CONFIG_X86_64
1198 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1199 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1200 ~CPU_BASED_CR8_STORE_EXITING;
1201 #endif
1202 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1203 min2 = 0;
1204 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1205 SECONDARY_EXEC_WBINVD_EXITING |
1206 SECONDARY_EXEC_ENABLE_VPID |
1207 SECONDARY_EXEC_ENABLE_EPT;
1208 if (adjust_vmx_controls(min2, opt2,
1209 MSR_IA32_VMX_PROCBASED_CTLS2,
1210 &_cpu_based_2nd_exec_control) < 0)
1211 return -EIO;
1212 }
1213 #ifndef CONFIG_X86_64
1214 if (!(_cpu_based_2nd_exec_control &
1215 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1216 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1217 #endif
1218 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1219 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1220 enabled */
1221 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1222 CPU_BASED_CR3_STORE_EXITING |
1223 CPU_BASED_INVLPG_EXITING);
1224 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1225 &_cpu_based_exec_control) < 0)
1226 return -EIO;
1227 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1228 vmx_capability.ept, vmx_capability.vpid);
1229 }
1230
1231 min = 0;
1232 #ifdef CONFIG_X86_64
1233 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1234 #endif
1235 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1236 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1237 &_vmexit_control) < 0)
1238 return -EIO;
1239
1240 min = 0;
1241 opt = VM_ENTRY_LOAD_IA32_PAT;
1242 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1243 &_vmentry_control) < 0)
1244 return -EIO;
1245
1246 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1247
1248 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1249 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1250 return -EIO;
1251
1252 #ifdef CONFIG_X86_64
1253 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1254 if (vmx_msr_high & (1u<<16))
1255 return -EIO;
1256 #endif
1257
1258 /* Require Write-Back (WB) memory type for VMCS accesses. */
1259 if (((vmx_msr_high >> 18) & 15) != 6)
1260 return -EIO;
1261
1262 vmcs_conf->size = vmx_msr_high & 0x1fff;
1263 vmcs_conf->order = get_order(vmcs_config.size);
1264 vmcs_conf->revision_id = vmx_msr_low;
1265
1266 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1267 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1268 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1269 vmcs_conf->vmexit_ctrl = _vmexit_control;
1270 vmcs_conf->vmentry_ctrl = _vmentry_control;
1271
1272 return 0;
1273 }
1274
1275 static struct vmcs *alloc_vmcs_cpu(int cpu)
1276 {
1277 int node = cpu_to_node(cpu);
1278 struct page *pages;
1279 struct vmcs *vmcs;
1280
1281 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1282 if (!pages)
1283 return NULL;
1284 vmcs = page_address(pages);
1285 memset(vmcs, 0, vmcs_config.size);
1286 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1287 return vmcs;
1288 }
1289
1290 static struct vmcs *alloc_vmcs(void)
1291 {
1292 return alloc_vmcs_cpu(raw_smp_processor_id());
1293 }
1294
1295 static void free_vmcs(struct vmcs *vmcs)
1296 {
1297 free_pages((unsigned long)vmcs, vmcs_config.order);
1298 }
1299
1300 static void free_kvm_area(void)
1301 {
1302 int cpu;
1303
1304 for_each_online_cpu(cpu)
1305 free_vmcs(per_cpu(vmxarea, cpu));
1306 }
1307
1308 static __init int alloc_kvm_area(void)
1309 {
1310 int cpu;
1311
1312 for_each_online_cpu(cpu) {
1313 struct vmcs *vmcs;
1314
1315 vmcs = alloc_vmcs_cpu(cpu);
1316 if (!vmcs) {
1317 free_kvm_area();
1318 return -ENOMEM;
1319 }
1320
1321 per_cpu(vmxarea, cpu) = vmcs;
1322 }
1323 return 0;
1324 }
1325
1326 static __init int hardware_setup(void)
1327 {
1328 if (setup_vmcs_config(&vmcs_config) < 0)
1329 return -EIO;
1330
1331 if (boot_cpu_has(X86_FEATURE_NX))
1332 kvm_enable_efer_bits(EFER_NX);
1333
1334 if (!cpu_has_vmx_vpid())
1335 enable_vpid = 0;
1336
1337 if (!cpu_has_vmx_ept())
1338 enable_ept = 0;
1339
1340 if (!cpu_has_vmx_flexpriority())
1341 flexpriority_enabled = 0;
1342
1343 if (!cpu_has_vmx_tpr_shadow())
1344 kvm_x86_ops->update_cr8_intercept = NULL;
1345
1346 return alloc_kvm_area();
1347 }
1348
1349 static __exit void hardware_unsetup(void)
1350 {
1351 free_kvm_area();
1352 }
1353
1354 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1355 {
1356 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1357
1358 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1359 vmcs_write16(sf->selector, save->selector);
1360 vmcs_writel(sf->base, save->base);
1361 vmcs_write32(sf->limit, save->limit);
1362 vmcs_write32(sf->ar_bytes, save->ar);
1363 } else {
1364 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1365 << AR_DPL_SHIFT;
1366 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1367 }
1368 }
1369
1370 static void enter_pmode(struct kvm_vcpu *vcpu)
1371 {
1372 unsigned long flags;
1373 struct vcpu_vmx *vmx = to_vmx(vcpu);
1374
1375 vmx->emulation_required = 1;
1376 vcpu->arch.rmode.vm86_active = 0;
1377
1378 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1379 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1380 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1381
1382 flags = vmcs_readl(GUEST_RFLAGS);
1383 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1384 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1385 vmcs_writel(GUEST_RFLAGS, flags);
1386
1387 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1388 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1389
1390 update_exception_bitmap(vcpu);
1391
1392 if (emulate_invalid_guest_state)
1393 return;
1394
1395 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1396 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1397 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1398 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1399
1400 vmcs_write16(GUEST_SS_SELECTOR, 0);
1401 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1402
1403 vmcs_write16(GUEST_CS_SELECTOR,
1404 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1405 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1406 }
1407
1408 static gva_t rmode_tss_base(struct kvm *kvm)
1409 {
1410 if (!kvm->arch.tss_addr) {
1411 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1412 kvm->memslots[0].npages - 3;
1413 return base_gfn << PAGE_SHIFT;
1414 }
1415 return kvm->arch.tss_addr;
1416 }
1417
1418 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1419 {
1420 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1421
1422 save->selector = vmcs_read16(sf->selector);
1423 save->base = vmcs_readl(sf->base);
1424 save->limit = vmcs_read32(sf->limit);
1425 save->ar = vmcs_read32(sf->ar_bytes);
1426 vmcs_write16(sf->selector, save->base >> 4);
1427 vmcs_write32(sf->base, save->base & 0xfffff);
1428 vmcs_write32(sf->limit, 0xffff);
1429 vmcs_write32(sf->ar_bytes, 0xf3);
1430 }
1431
1432 static void enter_rmode(struct kvm_vcpu *vcpu)
1433 {
1434 unsigned long flags;
1435 struct vcpu_vmx *vmx = to_vmx(vcpu);
1436
1437 vmx->emulation_required = 1;
1438 vcpu->arch.rmode.vm86_active = 1;
1439
1440 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1441 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1442
1443 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1444 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1445
1446 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1447 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1448
1449 flags = vmcs_readl(GUEST_RFLAGS);
1450 vcpu->arch.rmode.save_iopl
1451 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1452
1453 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1454
1455 vmcs_writel(GUEST_RFLAGS, flags);
1456 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1457 update_exception_bitmap(vcpu);
1458
1459 if (emulate_invalid_guest_state)
1460 goto continue_rmode;
1461
1462 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1463 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1464 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1465
1466 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1467 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1468 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1469 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1470 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1471
1472 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1473 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1474 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1475 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1476
1477 continue_rmode:
1478 kvm_mmu_reset_context(vcpu);
1479 init_rmode(vcpu->kvm);
1480 }
1481
1482 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1483 {
1484 struct vcpu_vmx *vmx = to_vmx(vcpu);
1485 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1486
1487 vcpu->arch.shadow_efer = efer;
1488 if (!msr)
1489 return;
1490 if (efer & EFER_LMA) {
1491 vmcs_write32(VM_ENTRY_CONTROLS,
1492 vmcs_read32(VM_ENTRY_CONTROLS) |
1493 VM_ENTRY_IA32E_MODE);
1494 msr->data = efer;
1495 } else {
1496 vmcs_write32(VM_ENTRY_CONTROLS,
1497 vmcs_read32(VM_ENTRY_CONTROLS) &
1498 ~VM_ENTRY_IA32E_MODE);
1499
1500 msr->data = efer & ~EFER_LME;
1501 }
1502 setup_msrs(vmx);
1503 }
1504
1505 #ifdef CONFIG_X86_64
1506
1507 static void enter_lmode(struct kvm_vcpu *vcpu)
1508 {
1509 u32 guest_tr_ar;
1510
1511 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1512 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1513 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1514 __func__);
1515 vmcs_write32(GUEST_TR_AR_BYTES,
1516 (guest_tr_ar & ~AR_TYPE_MASK)
1517 | AR_TYPE_BUSY_64_TSS);
1518 }
1519 vcpu->arch.shadow_efer |= EFER_LMA;
1520 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1521 }
1522
1523 static void exit_lmode(struct kvm_vcpu *vcpu)
1524 {
1525 vcpu->arch.shadow_efer &= ~EFER_LMA;
1526
1527 vmcs_write32(VM_ENTRY_CONTROLS,
1528 vmcs_read32(VM_ENTRY_CONTROLS)
1529 & ~VM_ENTRY_IA32E_MODE);
1530 }
1531
1532 #endif
1533
1534 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1535 {
1536 vpid_sync_vcpu_all(to_vmx(vcpu));
1537 if (enable_ept)
1538 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1539 }
1540
1541 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1542 {
1543 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1544 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1545 }
1546
1547 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1548 {
1549 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1550 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1551 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1552 return;
1553 }
1554 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1555 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1556 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1557 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1558 }
1559 }
1560
1561 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1562
1563 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1564 unsigned long cr0,
1565 struct kvm_vcpu *vcpu)
1566 {
1567 if (!(cr0 & X86_CR0_PG)) {
1568 /* From paging/starting to nonpaging */
1569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1570 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1571 (CPU_BASED_CR3_LOAD_EXITING |
1572 CPU_BASED_CR3_STORE_EXITING));
1573 vcpu->arch.cr0 = cr0;
1574 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1575 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1576 *hw_cr0 &= ~X86_CR0_WP;
1577 } else if (!is_paging(vcpu)) {
1578 /* From nonpaging to paging */
1579 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1580 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1581 ~(CPU_BASED_CR3_LOAD_EXITING |
1582 CPU_BASED_CR3_STORE_EXITING));
1583 vcpu->arch.cr0 = cr0;
1584 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1585 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1586 *hw_cr0 &= ~X86_CR0_WP;
1587 }
1588 }
1589
1590 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1591 struct kvm_vcpu *vcpu)
1592 {
1593 if (!is_paging(vcpu)) {
1594 *hw_cr4 &= ~X86_CR4_PAE;
1595 *hw_cr4 |= X86_CR4_PSE;
1596 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1597 *hw_cr4 &= ~X86_CR4_PAE;
1598 }
1599
1600 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1601 {
1602 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1603 KVM_VM_CR0_ALWAYS_ON;
1604
1605 vmx_fpu_deactivate(vcpu);
1606
1607 if (vcpu->arch.rmode.vm86_active && (cr0 & X86_CR0_PE))
1608 enter_pmode(vcpu);
1609
1610 if (!vcpu->arch.rmode.vm86_active && !(cr0 & X86_CR0_PE))
1611 enter_rmode(vcpu);
1612
1613 #ifdef CONFIG_X86_64
1614 if (vcpu->arch.shadow_efer & EFER_LME) {
1615 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1616 enter_lmode(vcpu);
1617 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1618 exit_lmode(vcpu);
1619 }
1620 #endif
1621
1622 if (enable_ept)
1623 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1624
1625 vmcs_writel(CR0_READ_SHADOW, cr0);
1626 vmcs_writel(GUEST_CR0, hw_cr0);
1627 vcpu->arch.cr0 = cr0;
1628
1629 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1630 vmx_fpu_activate(vcpu);
1631 }
1632
1633 static u64 construct_eptp(unsigned long root_hpa)
1634 {
1635 u64 eptp;
1636
1637 /* TODO write the value reading from MSR */
1638 eptp = VMX_EPT_DEFAULT_MT |
1639 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1640 eptp |= (root_hpa & PAGE_MASK);
1641
1642 return eptp;
1643 }
1644
1645 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1646 {
1647 unsigned long guest_cr3;
1648 u64 eptp;
1649
1650 guest_cr3 = cr3;
1651 if (enable_ept) {
1652 eptp = construct_eptp(cr3);
1653 vmcs_write64(EPT_POINTER, eptp);
1654 ept_load_pdptrs(vcpu);
1655 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1656 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1657 }
1658
1659 vmx_flush_tlb(vcpu);
1660 vmcs_writel(GUEST_CR3, guest_cr3);
1661 if (vcpu->arch.cr0 & X86_CR0_PE)
1662 vmx_fpu_deactivate(vcpu);
1663 }
1664
1665 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1666 {
1667 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.vm86_active ?
1668 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1669
1670 vcpu->arch.cr4 = cr4;
1671 if (enable_ept)
1672 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1673
1674 vmcs_writel(CR4_READ_SHADOW, cr4);
1675 vmcs_writel(GUEST_CR4, hw_cr4);
1676 }
1677
1678 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1679 {
1680 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1681
1682 return vmcs_readl(sf->base);
1683 }
1684
1685 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1686 struct kvm_segment *var, int seg)
1687 {
1688 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1689 u32 ar;
1690
1691 var->base = vmcs_readl(sf->base);
1692 var->limit = vmcs_read32(sf->limit);
1693 var->selector = vmcs_read16(sf->selector);
1694 ar = vmcs_read32(sf->ar_bytes);
1695 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1696 ar = 0;
1697 var->type = ar & 15;
1698 var->s = (ar >> 4) & 1;
1699 var->dpl = (ar >> 5) & 3;
1700 var->present = (ar >> 7) & 1;
1701 var->avl = (ar >> 12) & 1;
1702 var->l = (ar >> 13) & 1;
1703 var->db = (ar >> 14) & 1;
1704 var->g = (ar >> 15) & 1;
1705 var->unusable = (ar >> 16) & 1;
1706 }
1707
1708 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1709 {
1710 struct kvm_segment kvm_seg;
1711
1712 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1713 return 0;
1714
1715 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1716 return 3;
1717
1718 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1719 return kvm_seg.selector & 3;
1720 }
1721
1722 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1723 {
1724 u32 ar;
1725
1726 if (var->unusable)
1727 ar = 1 << 16;
1728 else {
1729 ar = var->type & 15;
1730 ar |= (var->s & 1) << 4;
1731 ar |= (var->dpl & 3) << 5;
1732 ar |= (var->present & 1) << 7;
1733 ar |= (var->avl & 1) << 12;
1734 ar |= (var->l & 1) << 13;
1735 ar |= (var->db & 1) << 14;
1736 ar |= (var->g & 1) << 15;
1737 }
1738 if (ar == 0) /* a 0 value means unusable */
1739 ar = AR_UNUSABLE_MASK;
1740
1741 return ar;
1742 }
1743
1744 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1745 struct kvm_segment *var, int seg)
1746 {
1747 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1748 u32 ar;
1749
1750 if (vcpu->arch.rmode.vm86_active && seg == VCPU_SREG_TR) {
1751 vcpu->arch.rmode.tr.selector = var->selector;
1752 vcpu->arch.rmode.tr.base = var->base;
1753 vcpu->arch.rmode.tr.limit = var->limit;
1754 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1755 return;
1756 }
1757 vmcs_writel(sf->base, var->base);
1758 vmcs_write32(sf->limit, var->limit);
1759 vmcs_write16(sf->selector, var->selector);
1760 if (vcpu->arch.rmode.vm86_active && var->s) {
1761 /*
1762 * Hack real-mode segments into vm86 compatibility.
1763 */
1764 if (var->base == 0xffff0000 && var->selector == 0xf000)
1765 vmcs_writel(sf->base, 0xf0000);
1766 ar = 0xf3;
1767 } else
1768 ar = vmx_segment_access_rights(var);
1769 vmcs_write32(sf->ar_bytes, ar);
1770 }
1771
1772 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1773 {
1774 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1775
1776 *db = (ar >> 14) & 1;
1777 *l = (ar >> 13) & 1;
1778 }
1779
1780 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1781 {
1782 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1783 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1784 }
1785
1786 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1787 {
1788 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1789 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1790 }
1791
1792 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1793 {
1794 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1795 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1796 }
1797
1798 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1799 {
1800 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1801 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1802 }
1803
1804 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1805 {
1806 struct kvm_segment var;
1807 u32 ar;
1808
1809 vmx_get_segment(vcpu, &var, seg);
1810 ar = vmx_segment_access_rights(&var);
1811
1812 if (var.base != (var.selector << 4))
1813 return false;
1814 if (var.limit != 0xffff)
1815 return false;
1816 if (ar != 0xf3)
1817 return false;
1818
1819 return true;
1820 }
1821
1822 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1823 {
1824 struct kvm_segment cs;
1825 unsigned int cs_rpl;
1826
1827 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1828 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1829
1830 if (cs.unusable)
1831 return false;
1832 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1833 return false;
1834 if (!cs.s)
1835 return false;
1836 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1837 if (cs.dpl > cs_rpl)
1838 return false;
1839 } else {
1840 if (cs.dpl != cs_rpl)
1841 return false;
1842 }
1843 if (!cs.present)
1844 return false;
1845
1846 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1847 return true;
1848 }
1849
1850 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1851 {
1852 struct kvm_segment ss;
1853 unsigned int ss_rpl;
1854
1855 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1856 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1857
1858 if (ss.unusable)
1859 return true;
1860 if (ss.type != 3 && ss.type != 7)
1861 return false;
1862 if (!ss.s)
1863 return false;
1864 if (ss.dpl != ss_rpl) /* DPL != RPL */
1865 return false;
1866 if (!ss.present)
1867 return false;
1868
1869 return true;
1870 }
1871
1872 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1873 {
1874 struct kvm_segment var;
1875 unsigned int rpl;
1876
1877 vmx_get_segment(vcpu, &var, seg);
1878 rpl = var.selector & SELECTOR_RPL_MASK;
1879
1880 if (var.unusable)
1881 return true;
1882 if (!var.s)
1883 return false;
1884 if (!var.present)
1885 return false;
1886 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1887 if (var.dpl < rpl) /* DPL < RPL */
1888 return false;
1889 }
1890
1891 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1892 * rights flags
1893 */
1894 return true;
1895 }
1896
1897 static bool tr_valid(struct kvm_vcpu *vcpu)
1898 {
1899 struct kvm_segment tr;
1900
1901 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1902
1903 if (tr.unusable)
1904 return false;
1905 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1906 return false;
1907 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1908 return false;
1909 if (!tr.present)
1910 return false;
1911
1912 return true;
1913 }
1914
1915 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1916 {
1917 struct kvm_segment ldtr;
1918
1919 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1920
1921 if (ldtr.unusable)
1922 return true;
1923 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1924 return false;
1925 if (ldtr.type != 2)
1926 return false;
1927 if (!ldtr.present)
1928 return false;
1929
1930 return true;
1931 }
1932
1933 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1934 {
1935 struct kvm_segment cs, ss;
1936
1937 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1938 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1939
1940 return ((cs.selector & SELECTOR_RPL_MASK) ==
1941 (ss.selector & SELECTOR_RPL_MASK));
1942 }
1943
1944 /*
1945 * Check if guest state is valid. Returns true if valid, false if
1946 * not.
1947 * We assume that registers are always usable
1948 */
1949 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1950 {
1951 /* real mode guest state checks */
1952 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1953 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1954 return false;
1955 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1956 return false;
1957 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1958 return false;
1959 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1960 return false;
1961 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1962 return false;
1963 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1964 return false;
1965 } else {
1966 /* protected mode guest state checks */
1967 if (!cs_ss_rpl_check(vcpu))
1968 return false;
1969 if (!code_segment_valid(vcpu))
1970 return false;
1971 if (!stack_segment_valid(vcpu))
1972 return false;
1973 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1974 return false;
1975 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1976 return false;
1977 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1978 return false;
1979 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1980 return false;
1981 if (!tr_valid(vcpu))
1982 return false;
1983 if (!ldtr_valid(vcpu))
1984 return false;
1985 }
1986 /* TODO:
1987 * - Add checks on RIP
1988 * - Add checks on RFLAGS
1989 */
1990
1991 return true;
1992 }
1993
1994 static int init_rmode_tss(struct kvm *kvm)
1995 {
1996 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1997 u16 data = 0;
1998 int ret = 0;
1999 int r;
2000
2001 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2002 if (r < 0)
2003 goto out;
2004 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2005 r = kvm_write_guest_page(kvm, fn++, &data,
2006 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2007 if (r < 0)
2008 goto out;
2009 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2010 if (r < 0)
2011 goto out;
2012 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2013 if (r < 0)
2014 goto out;
2015 data = ~0;
2016 r = kvm_write_guest_page(kvm, fn, &data,
2017 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2018 sizeof(u8));
2019 if (r < 0)
2020 goto out;
2021
2022 ret = 1;
2023 out:
2024 return ret;
2025 }
2026
2027 static int init_rmode_identity_map(struct kvm *kvm)
2028 {
2029 int i, r, ret;
2030 pfn_t identity_map_pfn;
2031 u32 tmp;
2032
2033 if (!enable_ept)
2034 return 1;
2035 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2036 printk(KERN_ERR "EPT: identity-mapping pagetable "
2037 "haven't been allocated!\n");
2038 return 0;
2039 }
2040 if (likely(kvm->arch.ept_identity_pagetable_done))
2041 return 1;
2042 ret = 0;
2043 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2044 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2045 if (r < 0)
2046 goto out;
2047 /* Set up identity-mapping pagetable for EPT in real mode */
2048 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2049 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2050 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2051 r = kvm_write_guest_page(kvm, identity_map_pfn,
2052 &tmp, i * sizeof(tmp), sizeof(tmp));
2053 if (r < 0)
2054 goto out;
2055 }
2056 kvm->arch.ept_identity_pagetable_done = true;
2057 ret = 1;
2058 out:
2059 return ret;
2060 }
2061
2062 static void seg_setup(int seg)
2063 {
2064 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2065
2066 vmcs_write16(sf->selector, 0);
2067 vmcs_writel(sf->base, 0);
2068 vmcs_write32(sf->limit, 0xffff);
2069 vmcs_write32(sf->ar_bytes, 0xf3);
2070 }
2071
2072 static int alloc_apic_access_page(struct kvm *kvm)
2073 {
2074 struct kvm_userspace_memory_region kvm_userspace_mem;
2075 int r = 0;
2076
2077 down_write(&kvm->slots_lock);
2078 if (kvm->arch.apic_access_page)
2079 goto out;
2080 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2081 kvm_userspace_mem.flags = 0;
2082 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2083 kvm_userspace_mem.memory_size = PAGE_SIZE;
2084 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2085 if (r)
2086 goto out;
2087
2088 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2089 out:
2090 up_write(&kvm->slots_lock);
2091 return r;
2092 }
2093
2094 static int alloc_identity_pagetable(struct kvm *kvm)
2095 {
2096 struct kvm_userspace_memory_region kvm_userspace_mem;
2097 int r = 0;
2098
2099 down_write(&kvm->slots_lock);
2100 if (kvm->arch.ept_identity_pagetable)
2101 goto out;
2102 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2103 kvm_userspace_mem.flags = 0;
2104 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2105 kvm_userspace_mem.memory_size = PAGE_SIZE;
2106 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2107 if (r)
2108 goto out;
2109
2110 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2111 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2112 out:
2113 up_write(&kvm->slots_lock);
2114 return r;
2115 }
2116
2117 static void allocate_vpid(struct vcpu_vmx *vmx)
2118 {
2119 int vpid;
2120
2121 vmx->vpid = 0;
2122 if (!enable_vpid)
2123 return;
2124 spin_lock(&vmx_vpid_lock);
2125 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2126 if (vpid < VMX_NR_VPIDS) {
2127 vmx->vpid = vpid;
2128 __set_bit(vpid, vmx_vpid_bitmap);
2129 }
2130 spin_unlock(&vmx_vpid_lock);
2131 }
2132
2133 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2134 {
2135 int f = sizeof(unsigned long);
2136
2137 if (!cpu_has_vmx_msr_bitmap())
2138 return;
2139
2140 /*
2141 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2142 * have the write-low and read-high bitmap offsets the wrong way round.
2143 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2144 */
2145 if (msr <= 0x1fff) {
2146 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2147 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2148 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2149 msr &= 0x1fff;
2150 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2151 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2152 }
2153 }
2154
2155 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2156 {
2157 if (!longmode_only)
2158 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2159 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2160 }
2161
2162 /*
2163 * Sets up the vmcs for emulated real mode.
2164 */
2165 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2166 {
2167 u32 host_sysenter_cs, msr_low, msr_high;
2168 u32 junk;
2169 u64 host_pat, tsc_this, tsc_base;
2170 unsigned long a;
2171 struct descriptor_table dt;
2172 int i;
2173 unsigned long kvm_vmx_return;
2174 u32 exec_control;
2175
2176 /* I/O */
2177 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2178 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2179
2180 if (cpu_has_vmx_msr_bitmap())
2181 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2182
2183 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2184
2185 /* Control */
2186 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2187 vmcs_config.pin_based_exec_ctrl);
2188
2189 exec_control = vmcs_config.cpu_based_exec_ctrl;
2190 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2191 exec_control &= ~CPU_BASED_TPR_SHADOW;
2192 #ifdef CONFIG_X86_64
2193 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2194 CPU_BASED_CR8_LOAD_EXITING;
2195 #endif
2196 }
2197 if (!enable_ept)
2198 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2199 CPU_BASED_CR3_LOAD_EXITING |
2200 CPU_BASED_INVLPG_EXITING;
2201 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2202
2203 if (cpu_has_secondary_exec_ctrls()) {
2204 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2205 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2206 exec_control &=
2207 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2208 if (vmx->vpid == 0)
2209 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2210 if (!enable_ept)
2211 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2212 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2213 }
2214
2215 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2216 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2217 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2218
2219 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2220 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2221 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2222
2223 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2224 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2225 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2226 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2227 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2228 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2229 #ifdef CONFIG_X86_64
2230 rdmsrl(MSR_FS_BASE, a);
2231 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2232 rdmsrl(MSR_GS_BASE, a);
2233 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2234 #else
2235 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2236 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2237 #endif
2238
2239 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2240
2241 kvm_get_idt(&dt);
2242 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2243
2244 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2245 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2246 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2247 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2248 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2249
2250 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2251 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2252 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2253 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2254 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2255 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2256
2257 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2258 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2259 host_pat = msr_low | ((u64) msr_high << 32);
2260 vmcs_write64(HOST_IA32_PAT, host_pat);
2261 }
2262 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2263 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2264 host_pat = msr_low | ((u64) msr_high << 32);
2265 /* Write the default value follow host pat */
2266 vmcs_write64(GUEST_IA32_PAT, host_pat);
2267 /* Keep arch.pat sync with GUEST_IA32_PAT */
2268 vmx->vcpu.arch.pat = host_pat;
2269 }
2270
2271 for (i = 0; i < NR_VMX_MSR; ++i) {
2272 u32 index = vmx_msr_index[i];
2273 u32 data_low, data_high;
2274 u64 data;
2275 int j = vmx->nmsrs;
2276
2277 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2278 continue;
2279 if (wrmsr_safe(index, data_low, data_high) < 0)
2280 continue;
2281 data = data_low | ((u64)data_high << 32);
2282 vmx->host_msrs[j].index = index;
2283 vmx->host_msrs[j].reserved = 0;
2284 vmx->host_msrs[j].data = data;
2285 vmx->guest_msrs[j] = vmx->host_msrs[j];
2286 ++vmx->nmsrs;
2287 }
2288
2289 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2290
2291 /* 22.2.1, 20.8.1 */
2292 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2293
2294 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2295 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2296
2297 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2298 rdtscll(tsc_this);
2299 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2300 tsc_base = tsc_this;
2301
2302 guest_write_tsc(0, tsc_base);
2303
2304 return 0;
2305 }
2306
2307 static int init_rmode(struct kvm *kvm)
2308 {
2309 if (!init_rmode_tss(kvm))
2310 return 0;
2311 if (!init_rmode_identity_map(kvm))
2312 return 0;
2313 return 1;
2314 }
2315
2316 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2317 {
2318 struct vcpu_vmx *vmx = to_vmx(vcpu);
2319 u64 msr;
2320 int ret;
2321
2322 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2323 down_read(&vcpu->kvm->slots_lock);
2324 if (!init_rmode(vmx->vcpu.kvm)) {
2325 ret = -ENOMEM;
2326 goto out;
2327 }
2328
2329 vmx->vcpu.arch.rmode.vm86_active = 0;
2330
2331 vmx->soft_vnmi_blocked = 0;
2332
2333 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2334 kvm_set_cr8(&vmx->vcpu, 0);
2335 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2336 if (vmx->vcpu.vcpu_id == 0)
2337 msr |= MSR_IA32_APICBASE_BSP;
2338 kvm_set_apic_base(&vmx->vcpu, msr);
2339
2340 fx_init(&vmx->vcpu);
2341
2342 seg_setup(VCPU_SREG_CS);
2343 /*
2344 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2345 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2346 */
2347 if (vmx->vcpu.vcpu_id == 0) {
2348 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2349 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2350 } else {
2351 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2352 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2353 }
2354
2355 seg_setup(VCPU_SREG_DS);
2356 seg_setup(VCPU_SREG_ES);
2357 seg_setup(VCPU_SREG_FS);
2358 seg_setup(VCPU_SREG_GS);
2359 seg_setup(VCPU_SREG_SS);
2360
2361 vmcs_write16(GUEST_TR_SELECTOR, 0);
2362 vmcs_writel(GUEST_TR_BASE, 0);
2363 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2364 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2365
2366 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2367 vmcs_writel(GUEST_LDTR_BASE, 0);
2368 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2369 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2370
2371 vmcs_write32(GUEST_SYSENTER_CS, 0);
2372 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2373 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2374
2375 vmcs_writel(GUEST_RFLAGS, 0x02);
2376 if (vmx->vcpu.vcpu_id == 0)
2377 kvm_rip_write(vcpu, 0xfff0);
2378 else
2379 kvm_rip_write(vcpu, 0);
2380 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2381
2382 vmcs_writel(GUEST_DR7, 0x400);
2383
2384 vmcs_writel(GUEST_GDTR_BASE, 0);
2385 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2386
2387 vmcs_writel(GUEST_IDTR_BASE, 0);
2388 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2389
2390 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2391 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2392 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2393
2394 /* Special registers */
2395 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2396
2397 setup_msrs(vmx);
2398
2399 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2400
2401 if (cpu_has_vmx_tpr_shadow()) {
2402 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2403 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2404 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2405 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2406 vmcs_write32(TPR_THRESHOLD, 0);
2407 }
2408
2409 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2410 vmcs_write64(APIC_ACCESS_ADDR,
2411 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2412
2413 if (vmx->vpid != 0)
2414 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2415
2416 vmx->vcpu.arch.cr0 = 0x60000010;
2417 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2418 vmx_set_cr4(&vmx->vcpu, 0);
2419 vmx_set_efer(&vmx->vcpu, 0);
2420 vmx_fpu_activate(&vmx->vcpu);
2421 update_exception_bitmap(&vmx->vcpu);
2422
2423 vpid_sync_vcpu_all(vmx);
2424
2425 ret = 0;
2426
2427 /* HACK: Don't enable emulation on guest boot/reset */
2428 vmx->emulation_required = 0;
2429
2430 out:
2431 up_read(&vcpu->kvm->slots_lock);
2432 return ret;
2433 }
2434
2435 static void enable_irq_window(struct kvm_vcpu *vcpu)
2436 {
2437 u32 cpu_based_vm_exec_control;
2438
2439 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2440 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2441 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2442 }
2443
2444 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2445 {
2446 u32 cpu_based_vm_exec_control;
2447
2448 if (!cpu_has_virtual_nmis()) {
2449 enable_irq_window(vcpu);
2450 return;
2451 }
2452
2453 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2454 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2455 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2456 }
2457
2458 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2459 {
2460 struct vcpu_vmx *vmx = to_vmx(vcpu);
2461 uint32_t intr;
2462 int irq = vcpu->arch.interrupt.nr;
2463
2464 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2465
2466 ++vcpu->stat.irq_injections;
2467 if (vcpu->arch.rmode.vm86_active) {
2468 vmx->rmode.irq.pending = true;
2469 vmx->rmode.irq.vector = irq;
2470 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2471 if (vcpu->arch.interrupt.soft)
2472 vmx->rmode.irq.rip +=
2473 vmx->vcpu.arch.event_exit_inst_len;
2474 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2475 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2476 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2477 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2478 return;
2479 }
2480 intr = irq | INTR_INFO_VALID_MASK;
2481 if (vcpu->arch.interrupt.soft) {
2482 intr |= INTR_TYPE_SOFT_INTR;
2483 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2484 vmx->vcpu.arch.event_exit_inst_len);
2485 } else
2486 intr |= INTR_TYPE_EXT_INTR;
2487 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2488 }
2489
2490 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2491 {
2492 struct vcpu_vmx *vmx = to_vmx(vcpu);
2493
2494 if (!cpu_has_virtual_nmis()) {
2495 /*
2496 * Tracking the NMI-blocked state in software is built upon
2497 * finding the next open IRQ window. This, in turn, depends on
2498 * well-behaving guests: They have to keep IRQs disabled at
2499 * least as long as the NMI handler runs. Otherwise we may
2500 * cause NMI nesting, maybe breaking the guest. But as this is
2501 * highly unlikely, we can live with the residual risk.
2502 */
2503 vmx->soft_vnmi_blocked = 1;
2504 vmx->vnmi_blocked_time = 0;
2505 }
2506
2507 ++vcpu->stat.nmi_injections;
2508 if (vcpu->arch.rmode.vm86_active) {
2509 vmx->rmode.irq.pending = true;
2510 vmx->rmode.irq.vector = NMI_VECTOR;
2511 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2512 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2513 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2514 INTR_INFO_VALID_MASK);
2515 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2516 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2517 return;
2518 }
2519 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2520 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2521 }
2522
2523 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2524 {
2525 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2526 return 0;
2527
2528 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2529 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2530 GUEST_INTR_STATE_NMI));
2531 }
2532
2533 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2534 {
2535 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2536 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2537 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2538 }
2539
2540 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2541 {
2542 int ret;
2543 struct kvm_userspace_memory_region tss_mem = {
2544 .slot = TSS_PRIVATE_MEMSLOT,
2545 .guest_phys_addr = addr,
2546 .memory_size = PAGE_SIZE * 3,
2547 .flags = 0,
2548 };
2549
2550 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2551 if (ret)
2552 return ret;
2553 kvm->arch.tss_addr = addr;
2554 return 0;
2555 }
2556
2557 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2558 int vec, u32 err_code)
2559 {
2560 /*
2561 * Instruction with address size override prefix opcode 0x67
2562 * Cause the #SS fault with 0 error code in VM86 mode.
2563 */
2564 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2565 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2566 return 1;
2567 /*
2568 * Forward all other exceptions that are valid in real mode.
2569 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2570 * the required debugging infrastructure rework.
2571 */
2572 switch (vec) {
2573 case DB_VECTOR:
2574 if (vcpu->guest_debug &
2575 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2576 return 0;
2577 kvm_queue_exception(vcpu, vec);
2578 return 1;
2579 case BP_VECTOR:
2580 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2581 return 0;
2582 /* fall through */
2583 case DE_VECTOR:
2584 case OF_VECTOR:
2585 case BR_VECTOR:
2586 case UD_VECTOR:
2587 case DF_VECTOR:
2588 case SS_VECTOR:
2589 case GP_VECTOR:
2590 case MF_VECTOR:
2591 kvm_queue_exception(vcpu, vec);
2592 return 1;
2593 }
2594 return 0;
2595 }
2596
2597 /*
2598 * Trigger machine check on the host. We assume all the MSRs are already set up
2599 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2600 * We pass a fake environment to the machine check handler because we want
2601 * the guest to be always treated like user space, no matter what context
2602 * it used internally.
2603 */
2604 static void kvm_machine_check(void)
2605 {
2606 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2607 struct pt_regs regs = {
2608 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2609 .flags = X86_EFLAGS_IF,
2610 };
2611
2612 do_machine_check(&regs, 0);
2613 #endif
2614 }
2615
2616 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2617 {
2618 /* already handled by vcpu_run */
2619 return 1;
2620 }
2621
2622 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2623 {
2624 struct vcpu_vmx *vmx = to_vmx(vcpu);
2625 u32 intr_info, ex_no, error_code;
2626 unsigned long cr2, rip, dr6;
2627 u32 vect_info;
2628 enum emulation_result er;
2629
2630 vect_info = vmx->idt_vectoring_info;
2631 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2632
2633 if (is_machine_check(intr_info))
2634 return handle_machine_check(vcpu, kvm_run);
2635
2636 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2637 !is_page_fault(intr_info))
2638 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2639 "intr info 0x%x\n", __func__, vect_info, intr_info);
2640
2641 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2642 return 1; /* already handled by vmx_vcpu_run() */
2643
2644 if (is_no_device(intr_info)) {
2645 vmx_fpu_activate(vcpu);
2646 return 1;
2647 }
2648
2649 if (is_invalid_opcode(intr_info)) {
2650 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2651 if (er != EMULATE_DONE)
2652 kvm_queue_exception(vcpu, UD_VECTOR);
2653 return 1;
2654 }
2655
2656 error_code = 0;
2657 rip = kvm_rip_read(vcpu);
2658 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2659 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2660 if (is_page_fault(intr_info)) {
2661 /* EPT won't cause page fault directly */
2662 if (enable_ept)
2663 BUG();
2664 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2665 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2666 (u32)((u64)cr2 >> 32), handler);
2667 if (kvm_event_needs_reinjection(vcpu))
2668 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2669 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2670 }
2671
2672 if (vcpu->arch.rmode.vm86_active &&
2673 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2674 error_code)) {
2675 if (vcpu->arch.halt_request) {
2676 vcpu->arch.halt_request = 0;
2677 return kvm_emulate_halt(vcpu);
2678 }
2679 return 1;
2680 }
2681
2682 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2683 switch (ex_no) {
2684 case DB_VECTOR:
2685 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2686 if (!(vcpu->guest_debug &
2687 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2688 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2689 kvm_queue_exception(vcpu, DB_VECTOR);
2690 return 1;
2691 }
2692 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2693 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2694 /* fall through */
2695 case BP_VECTOR:
2696 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2697 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2698 kvm_run->debug.arch.exception = ex_no;
2699 break;
2700 default:
2701 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2702 kvm_run->ex.exception = ex_no;
2703 kvm_run->ex.error_code = error_code;
2704 break;
2705 }
2706 return 0;
2707 }
2708
2709 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2710 struct kvm_run *kvm_run)
2711 {
2712 ++vcpu->stat.irq_exits;
2713 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2714 return 1;
2715 }
2716
2717 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2718 {
2719 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2720 return 0;
2721 }
2722
2723 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2724 {
2725 unsigned long exit_qualification;
2726 int size, in, string;
2727 unsigned port;
2728
2729 ++vcpu->stat.io_exits;
2730 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2731 string = (exit_qualification & 16) != 0;
2732
2733 if (string) {
2734 if (emulate_instruction(vcpu,
2735 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2736 return 0;
2737 return 1;
2738 }
2739
2740 size = (exit_qualification & 7) + 1;
2741 in = (exit_qualification & 8) != 0;
2742 port = exit_qualification >> 16;
2743
2744 skip_emulated_instruction(vcpu);
2745 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2746 }
2747
2748 static void
2749 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2750 {
2751 /*
2752 * Patch in the VMCALL instruction:
2753 */
2754 hypercall[0] = 0x0f;
2755 hypercall[1] = 0x01;
2756 hypercall[2] = 0xc1;
2757 }
2758
2759 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2760 {
2761 unsigned long exit_qualification;
2762 int cr;
2763 int reg;
2764
2765 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2766 cr = exit_qualification & 15;
2767 reg = (exit_qualification >> 8) & 15;
2768 switch ((exit_qualification >> 4) & 3) {
2769 case 0: /* mov to cr */
2770 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2771 (u32)kvm_register_read(vcpu, reg),
2772 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2773 handler);
2774 switch (cr) {
2775 case 0:
2776 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2777 skip_emulated_instruction(vcpu);
2778 return 1;
2779 case 3:
2780 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2781 skip_emulated_instruction(vcpu);
2782 return 1;
2783 case 4:
2784 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2785 skip_emulated_instruction(vcpu);
2786 return 1;
2787 case 8: {
2788 u8 cr8_prev = kvm_get_cr8(vcpu);
2789 u8 cr8 = kvm_register_read(vcpu, reg);
2790 kvm_set_cr8(vcpu, cr8);
2791 skip_emulated_instruction(vcpu);
2792 if (irqchip_in_kernel(vcpu->kvm))
2793 return 1;
2794 if (cr8_prev <= cr8)
2795 return 1;
2796 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2797 return 0;
2798 }
2799 };
2800 break;
2801 case 2: /* clts */
2802 vmx_fpu_deactivate(vcpu);
2803 vcpu->arch.cr0 &= ~X86_CR0_TS;
2804 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2805 vmx_fpu_activate(vcpu);
2806 KVMTRACE_0D(CLTS, vcpu, handler);
2807 skip_emulated_instruction(vcpu);
2808 return 1;
2809 case 1: /*mov from cr*/
2810 switch (cr) {
2811 case 3:
2812 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2813 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2814 (u32)kvm_register_read(vcpu, reg),
2815 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2816 handler);
2817 skip_emulated_instruction(vcpu);
2818 return 1;
2819 case 8:
2820 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2821 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2822 (u32)kvm_register_read(vcpu, reg), handler);
2823 skip_emulated_instruction(vcpu);
2824 return 1;
2825 }
2826 break;
2827 case 3: /* lmsw */
2828 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2829
2830 skip_emulated_instruction(vcpu);
2831 return 1;
2832 default:
2833 break;
2834 }
2835 kvm_run->exit_reason = 0;
2836 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2837 (int)(exit_qualification >> 4) & 3, cr);
2838 return 0;
2839 }
2840
2841 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2842 {
2843 unsigned long exit_qualification;
2844 unsigned long val;
2845 int dr, reg;
2846
2847 dr = vmcs_readl(GUEST_DR7);
2848 if (dr & DR7_GD) {
2849 /*
2850 * As the vm-exit takes precedence over the debug trap, we
2851 * need to emulate the latter, either for the host or the
2852 * guest debugging itself.
2853 */
2854 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2855 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2856 kvm_run->debug.arch.dr7 = dr;
2857 kvm_run->debug.arch.pc =
2858 vmcs_readl(GUEST_CS_BASE) +
2859 vmcs_readl(GUEST_RIP);
2860 kvm_run->debug.arch.exception = DB_VECTOR;
2861 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2862 return 0;
2863 } else {
2864 vcpu->arch.dr7 &= ~DR7_GD;
2865 vcpu->arch.dr6 |= DR6_BD;
2866 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2867 kvm_queue_exception(vcpu, DB_VECTOR);
2868 return 1;
2869 }
2870 }
2871
2872 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2873 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2874 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2875 if (exit_qualification & TYPE_MOV_FROM_DR) {
2876 switch (dr) {
2877 case 0 ... 3:
2878 val = vcpu->arch.db[dr];
2879 break;
2880 case 6:
2881 val = vcpu->arch.dr6;
2882 break;
2883 case 7:
2884 val = vcpu->arch.dr7;
2885 break;
2886 default:
2887 val = 0;
2888 }
2889 kvm_register_write(vcpu, reg, val);
2890 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2891 } else {
2892 val = vcpu->arch.regs[reg];
2893 switch (dr) {
2894 case 0 ... 3:
2895 vcpu->arch.db[dr] = val;
2896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2897 vcpu->arch.eff_db[dr] = val;
2898 break;
2899 case 4 ... 5:
2900 if (vcpu->arch.cr4 & X86_CR4_DE)
2901 kvm_queue_exception(vcpu, UD_VECTOR);
2902 break;
2903 case 6:
2904 if (val & 0xffffffff00000000ULL) {
2905 kvm_queue_exception(vcpu, GP_VECTOR);
2906 break;
2907 }
2908 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2909 break;
2910 case 7:
2911 if (val & 0xffffffff00000000ULL) {
2912 kvm_queue_exception(vcpu, GP_VECTOR);
2913 break;
2914 }
2915 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2916 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2917 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2918 vcpu->arch.switch_db_regs =
2919 (val & DR7_BP_EN_MASK);
2920 }
2921 break;
2922 }
2923 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2924 }
2925 skip_emulated_instruction(vcpu);
2926 return 1;
2927 }
2928
2929 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2930 {
2931 kvm_emulate_cpuid(vcpu);
2932 return 1;
2933 }
2934
2935 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2936 {
2937 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2938 u64 data;
2939
2940 if (vmx_get_msr(vcpu, ecx, &data)) {
2941 kvm_inject_gp(vcpu, 0);
2942 return 1;
2943 }
2944
2945 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2946 handler);
2947
2948 /* FIXME: handling of bits 32:63 of rax, rdx */
2949 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2950 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2951 skip_emulated_instruction(vcpu);
2952 return 1;
2953 }
2954
2955 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2956 {
2957 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2958 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2959 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2960
2961 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2962 handler);
2963
2964 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2965 kvm_inject_gp(vcpu, 0);
2966 return 1;
2967 }
2968
2969 skip_emulated_instruction(vcpu);
2970 return 1;
2971 }
2972
2973 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2974 struct kvm_run *kvm_run)
2975 {
2976 return 1;
2977 }
2978
2979 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2980 struct kvm_run *kvm_run)
2981 {
2982 u32 cpu_based_vm_exec_control;
2983
2984 /* clear pending irq */
2985 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2986 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2987 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2988
2989 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2990 ++vcpu->stat.irq_window_exits;
2991
2992 /*
2993 * If the user space waits to inject interrupts, exit as soon as
2994 * possible
2995 */
2996 if (!irqchip_in_kernel(vcpu->kvm) &&
2997 kvm_run->request_interrupt_window &&
2998 !kvm_cpu_has_interrupt(vcpu)) {
2999 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3000 return 0;
3001 }
3002 return 1;
3003 }
3004
3005 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3006 {
3007 skip_emulated_instruction(vcpu);
3008 return kvm_emulate_halt(vcpu);
3009 }
3010
3011 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3012 {
3013 skip_emulated_instruction(vcpu);
3014 kvm_emulate_hypercall(vcpu);
3015 return 1;
3016 }
3017
3018 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3019 {
3020 kvm_queue_exception(vcpu, UD_VECTOR);
3021 return 1;
3022 }
3023
3024 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3025 {
3026 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3027
3028 kvm_mmu_invlpg(vcpu, exit_qualification);
3029 skip_emulated_instruction(vcpu);
3030 return 1;
3031 }
3032
3033 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3034 {
3035 skip_emulated_instruction(vcpu);
3036 /* TODO: Add support for VT-d/pass-through device */
3037 return 1;
3038 }
3039
3040 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3041 {
3042 unsigned long exit_qualification;
3043 enum emulation_result er;
3044 unsigned long offset;
3045
3046 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3047 offset = exit_qualification & 0xffful;
3048
3049 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3050
3051 if (er != EMULATE_DONE) {
3052 printk(KERN_ERR
3053 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3054 offset);
3055 return -ENOTSUPP;
3056 }
3057 return 1;
3058 }
3059
3060 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3061 {
3062 struct vcpu_vmx *vmx = to_vmx(vcpu);
3063 unsigned long exit_qualification;
3064 u16 tss_selector;
3065 int reason, type, idt_v;
3066
3067 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3068 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3069
3070 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3071
3072 reason = (u32)exit_qualification >> 30;
3073 if (reason == TASK_SWITCH_GATE && idt_v) {
3074 switch (type) {
3075 case INTR_TYPE_NMI_INTR:
3076 vcpu->arch.nmi_injected = false;
3077 if (cpu_has_virtual_nmis())
3078 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3079 GUEST_INTR_STATE_NMI);
3080 break;
3081 case INTR_TYPE_EXT_INTR:
3082 case INTR_TYPE_SOFT_INTR:
3083 kvm_clear_interrupt_queue(vcpu);
3084 break;
3085 case INTR_TYPE_HARD_EXCEPTION:
3086 case INTR_TYPE_SOFT_EXCEPTION:
3087 kvm_clear_exception_queue(vcpu);
3088 break;
3089 default:
3090 break;
3091 }
3092 }
3093 tss_selector = exit_qualification;
3094
3095 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3096 type != INTR_TYPE_EXT_INTR &&
3097 type != INTR_TYPE_NMI_INTR))
3098 skip_emulated_instruction(vcpu);
3099
3100 if (!kvm_task_switch(vcpu, tss_selector, reason))
3101 return 0;
3102
3103 /* clear all local breakpoint enable flags */
3104 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3105
3106 /*
3107 * TODO: What about debug traps on tss switch?
3108 * Are we supposed to inject them and update dr6?
3109 */
3110
3111 return 1;
3112 }
3113
3114 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3115 {
3116 unsigned long exit_qualification;
3117 gpa_t gpa;
3118 int gla_validity;
3119
3120 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3121
3122 if (exit_qualification & (1 << 6)) {
3123 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3124 return -ENOTSUPP;
3125 }
3126
3127 gla_validity = (exit_qualification >> 7) & 0x3;
3128 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3129 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3130 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3131 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3132 vmcs_readl(GUEST_LINEAR_ADDRESS));
3133 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3134 (long unsigned int)exit_qualification);
3135 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3136 kvm_run->hw.hardware_exit_reason = 0;
3137 return -ENOTSUPP;
3138 }
3139
3140 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3141 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3142 }
3143
3144 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3145 {
3146 u32 cpu_based_vm_exec_control;
3147
3148 /* clear pending NMI */
3149 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3150 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3151 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3152 ++vcpu->stat.nmi_window_exits;
3153
3154 return 1;
3155 }
3156
3157 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3158 struct kvm_run *kvm_run)
3159 {
3160 struct vcpu_vmx *vmx = to_vmx(vcpu);
3161 enum emulation_result err = EMULATE_DONE;
3162
3163 local_irq_enable();
3164 preempt_enable();
3165
3166 while (!guest_state_valid(vcpu)) {
3167 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3168
3169 if (err == EMULATE_DO_MMIO)
3170 break;
3171
3172 if (err != EMULATE_DONE) {
3173 kvm_report_emulation_failure(vcpu, "emulation failure");
3174 break;
3175 }
3176
3177 if (signal_pending(current))
3178 break;
3179 if (need_resched())
3180 schedule();
3181 }
3182
3183 preempt_disable();
3184 local_irq_disable();
3185
3186 vmx->invalid_state_emulation_result = err;
3187 }
3188
3189 /*
3190 * The exit handlers return 1 if the exit was handled fully and guest execution
3191 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3192 * to be done to userspace and return 0.
3193 */
3194 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3195 struct kvm_run *kvm_run) = {
3196 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3197 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3198 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3199 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3200 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3201 [EXIT_REASON_CR_ACCESS] = handle_cr,
3202 [EXIT_REASON_DR_ACCESS] = handle_dr,
3203 [EXIT_REASON_CPUID] = handle_cpuid,
3204 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3205 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3206 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3207 [EXIT_REASON_HLT] = handle_halt,
3208 [EXIT_REASON_INVLPG] = handle_invlpg,
3209 [EXIT_REASON_VMCALL] = handle_vmcall,
3210 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3211 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3212 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3213 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3214 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3215 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3216 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3217 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3218 [EXIT_REASON_VMON] = handle_vmx_insn,
3219 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3220 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3221 [EXIT_REASON_WBINVD] = handle_wbinvd,
3222 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3223 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3224 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3225 };
3226
3227 static const int kvm_vmx_max_exit_handlers =
3228 ARRAY_SIZE(kvm_vmx_exit_handlers);
3229
3230 /*
3231 * The guest has exited. See if we can fix it or if we need userspace
3232 * assistance.
3233 */
3234 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3235 {
3236 struct vcpu_vmx *vmx = to_vmx(vcpu);
3237 u32 exit_reason = vmx->exit_reason;
3238 u32 vectoring_info = vmx->idt_vectoring_info;
3239
3240 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3241 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3242
3243 /* If we need to emulate an MMIO from handle_invalid_guest_state
3244 * we just return 0 */
3245 if (vmx->emulation_required && emulate_invalid_guest_state) {
3246 if (guest_state_valid(vcpu))
3247 vmx->emulation_required = 0;
3248 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3249 }
3250
3251 /* Access CR3 don't cause VMExit in paging mode, so we need
3252 * to sync with guest real CR3. */
3253 if (enable_ept && is_paging(vcpu)) {
3254 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3255 ept_load_pdptrs(vcpu);
3256 }
3257
3258 if (unlikely(vmx->fail)) {
3259 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3260 kvm_run->fail_entry.hardware_entry_failure_reason
3261 = vmcs_read32(VM_INSTRUCTION_ERROR);
3262 return 0;
3263 }
3264
3265 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3266 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3267 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3268 exit_reason != EXIT_REASON_TASK_SWITCH))
3269 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3270 "(0x%x) and exit reason is 0x%x\n",
3271 __func__, vectoring_info, exit_reason);
3272
3273 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3274 if (vmx_interrupt_allowed(vcpu)) {
3275 vmx->soft_vnmi_blocked = 0;
3276 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3277 vcpu->arch.nmi_pending) {
3278 /*
3279 * This CPU don't support us in finding the end of an
3280 * NMI-blocked window if the guest runs with IRQs
3281 * disabled. So we pull the trigger after 1 s of
3282 * futile waiting, but inform the user about this.
3283 */
3284 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3285 "state on VCPU %d after 1 s timeout\n",
3286 __func__, vcpu->vcpu_id);
3287 vmx->soft_vnmi_blocked = 0;
3288 }
3289 }
3290
3291 if (exit_reason < kvm_vmx_max_exit_handlers
3292 && kvm_vmx_exit_handlers[exit_reason])
3293 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3294 else {
3295 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3296 kvm_run->hw.hardware_exit_reason = exit_reason;
3297 }
3298 return 0;
3299 }
3300
3301 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3302 {
3303 if (irr == -1 || tpr < irr) {
3304 vmcs_write32(TPR_THRESHOLD, 0);
3305 return;
3306 }
3307
3308 vmcs_write32(TPR_THRESHOLD, irr);
3309 }
3310
3311 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3312 {
3313 u32 exit_intr_info;
3314 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3315 bool unblock_nmi;
3316 u8 vector;
3317 int type;
3318 bool idtv_info_valid;
3319
3320 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3321
3322 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3323
3324 /* Handle machine checks before interrupts are enabled */
3325 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3326 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3327 && is_machine_check(exit_intr_info)))
3328 kvm_machine_check();
3329
3330 /* We need to handle NMIs before interrupts are enabled */
3331 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3332 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3333 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3334 asm("int $2");
3335 }
3336
3337 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3338
3339 if (cpu_has_virtual_nmis()) {
3340 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3341 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3342 /*
3343 * SDM 3: 27.7.1.2 (September 2008)
3344 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3345 * a guest IRET fault.
3346 * SDM 3: 23.2.2 (September 2008)
3347 * Bit 12 is undefined in any of the following cases:
3348 * If the VM exit sets the valid bit in the IDT-vectoring
3349 * information field.
3350 * If the VM exit is due to a double fault.
3351 */
3352 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3353 vector != DF_VECTOR && !idtv_info_valid)
3354 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3355 GUEST_INTR_STATE_NMI);
3356 } else if (unlikely(vmx->soft_vnmi_blocked))
3357 vmx->vnmi_blocked_time +=
3358 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3359
3360 vmx->vcpu.arch.nmi_injected = false;
3361 kvm_clear_exception_queue(&vmx->vcpu);
3362 kvm_clear_interrupt_queue(&vmx->vcpu);
3363
3364 if (!idtv_info_valid)
3365 return;
3366
3367 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3368 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3369
3370 switch (type) {
3371 case INTR_TYPE_NMI_INTR:
3372 vmx->vcpu.arch.nmi_injected = true;
3373 /*
3374 * SDM 3: 27.7.1.2 (September 2008)
3375 * Clear bit "block by NMI" before VM entry if a NMI
3376 * delivery faulted.
3377 */
3378 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3379 GUEST_INTR_STATE_NMI);
3380 break;
3381 case INTR_TYPE_SOFT_EXCEPTION:
3382 vmx->vcpu.arch.event_exit_inst_len =
3383 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3384 /* fall through */
3385 case INTR_TYPE_HARD_EXCEPTION:
3386 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3387 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3388 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3389 } else
3390 kvm_queue_exception(&vmx->vcpu, vector);
3391 break;
3392 case INTR_TYPE_SOFT_INTR:
3393 vmx->vcpu.arch.event_exit_inst_len =
3394 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3395 /* fall through */
3396 case INTR_TYPE_EXT_INTR:
3397 kvm_queue_interrupt(&vmx->vcpu, vector,
3398 type == INTR_TYPE_SOFT_INTR);
3399 break;
3400 default:
3401 break;
3402 }
3403 }
3404
3405 /*
3406 * Failure to inject an interrupt should give us the information
3407 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3408 * when fetching the interrupt redirection bitmap in the real-mode
3409 * tss, this doesn't happen. So we do it ourselves.
3410 */
3411 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3412 {
3413 vmx->rmode.irq.pending = 0;
3414 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3415 return;
3416 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3417 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3418 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3419 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3420 return;
3421 }
3422 vmx->idt_vectoring_info =
3423 VECTORING_INFO_VALID_MASK
3424 | INTR_TYPE_EXT_INTR
3425 | vmx->rmode.irq.vector;
3426 }
3427
3428 #ifdef CONFIG_X86_64
3429 #define R "r"
3430 #define Q "q"
3431 #else
3432 #define R "e"
3433 #define Q "l"
3434 #endif
3435
3436 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3437 {
3438 struct vcpu_vmx *vmx = to_vmx(vcpu);
3439
3440 /* Record the guest's net vcpu time for enforced NMI injections. */
3441 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3442 vmx->entry_time = ktime_get();
3443
3444 /* Handle invalid guest state instead of entering VMX */
3445 if (vmx->emulation_required && emulate_invalid_guest_state) {
3446 handle_invalid_guest_state(vcpu, kvm_run);
3447 return;
3448 }
3449
3450 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3451 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3452 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3453 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3454
3455 /* When single-stepping over STI and MOV SS, we must clear the
3456 * corresponding interruptibility bits in the guest state. Otherwise
3457 * vmentry fails as it then expects bit 14 (BS) in pending debug
3458 * exceptions being set, but that's not correct for the guest debugging
3459 * case. */
3460 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3461 vmx_set_interrupt_shadow(vcpu, 0);
3462
3463 /*
3464 * Loading guest fpu may have cleared host cr0.ts
3465 */
3466 vmcs_writel(HOST_CR0, read_cr0());
3467
3468 set_debugreg(vcpu->arch.dr6, 6);
3469
3470 asm(
3471 /* Store host registers */
3472 "push %%"R"dx; push %%"R"bp;"
3473 "push %%"R"cx \n\t"
3474 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3475 "je 1f \n\t"
3476 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3477 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3478 "1: \n\t"
3479 /* Check if vmlaunch of vmresume is needed */
3480 "cmpl $0, %c[launched](%0) \n\t"
3481 /* Load guest registers. Don't clobber flags. */
3482 "mov %c[cr2](%0), %%"R"ax \n\t"
3483 "mov %%"R"ax, %%cr2 \n\t"
3484 "mov %c[rax](%0), %%"R"ax \n\t"
3485 "mov %c[rbx](%0), %%"R"bx \n\t"
3486 "mov %c[rdx](%0), %%"R"dx \n\t"
3487 "mov %c[rsi](%0), %%"R"si \n\t"
3488 "mov %c[rdi](%0), %%"R"di \n\t"
3489 "mov %c[rbp](%0), %%"R"bp \n\t"
3490 #ifdef CONFIG_X86_64
3491 "mov %c[r8](%0), %%r8 \n\t"
3492 "mov %c[r9](%0), %%r9 \n\t"
3493 "mov %c[r10](%0), %%r10 \n\t"
3494 "mov %c[r11](%0), %%r11 \n\t"
3495 "mov %c[r12](%0), %%r12 \n\t"
3496 "mov %c[r13](%0), %%r13 \n\t"
3497 "mov %c[r14](%0), %%r14 \n\t"
3498 "mov %c[r15](%0), %%r15 \n\t"
3499 #endif
3500 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3501
3502 /* Enter guest mode */
3503 "jne .Llaunched \n\t"
3504 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3505 "jmp .Lkvm_vmx_return \n\t"
3506 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3507 ".Lkvm_vmx_return: "
3508 /* Save guest registers, load host registers, keep flags */
3509 "xchg %0, (%%"R"sp) \n\t"
3510 "mov %%"R"ax, %c[rax](%0) \n\t"
3511 "mov %%"R"bx, %c[rbx](%0) \n\t"
3512 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3513 "mov %%"R"dx, %c[rdx](%0) \n\t"
3514 "mov %%"R"si, %c[rsi](%0) \n\t"
3515 "mov %%"R"di, %c[rdi](%0) \n\t"
3516 "mov %%"R"bp, %c[rbp](%0) \n\t"
3517 #ifdef CONFIG_X86_64
3518 "mov %%r8, %c[r8](%0) \n\t"
3519 "mov %%r9, %c[r9](%0) \n\t"
3520 "mov %%r10, %c[r10](%0) \n\t"
3521 "mov %%r11, %c[r11](%0) \n\t"
3522 "mov %%r12, %c[r12](%0) \n\t"
3523 "mov %%r13, %c[r13](%0) \n\t"
3524 "mov %%r14, %c[r14](%0) \n\t"
3525 "mov %%r15, %c[r15](%0) \n\t"
3526 #endif
3527 "mov %%cr2, %%"R"ax \n\t"
3528 "mov %%"R"ax, %c[cr2](%0) \n\t"
3529
3530 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3531 "setbe %c[fail](%0) \n\t"
3532 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3533 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3534 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3535 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3536 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3537 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3538 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3539 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3540 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3541 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3542 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3543 #ifdef CONFIG_X86_64
3544 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3545 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3546 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3547 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3548 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3549 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3550 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3551 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3552 #endif
3553 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3554 : "cc", "memory"
3555 , R"bx", R"di", R"si"
3556 #ifdef CONFIG_X86_64
3557 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3558 #endif
3559 );
3560
3561 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3562 vcpu->arch.regs_dirty = 0;
3563
3564 get_debugreg(vcpu->arch.dr6, 6);
3565
3566 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3567 if (vmx->rmode.irq.pending)
3568 fixup_rmode_irq(vmx);
3569
3570 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3571 vmx->launched = 1;
3572
3573 vmx_complete_interrupts(vmx);
3574 }
3575
3576 #undef R
3577 #undef Q
3578
3579 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3580 {
3581 struct vcpu_vmx *vmx = to_vmx(vcpu);
3582
3583 if (vmx->vmcs) {
3584 vcpu_clear(vmx);
3585 free_vmcs(vmx->vmcs);
3586 vmx->vmcs = NULL;
3587 }
3588 }
3589
3590 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3591 {
3592 struct vcpu_vmx *vmx = to_vmx(vcpu);
3593
3594 spin_lock(&vmx_vpid_lock);
3595 if (vmx->vpid != 0)
3596 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3597 spin_unlock(&vmx_vpid_lock);
3598 vmx_free_vmcs(vcpu);
3599 kfree(vmx->host_msrs);
3600 kfree(vmx->guest_msrs);
3601 kvm_vcpu_uninit(vcpu);
3602 kmem_cache_free(kvm_vcpu_cache, vmx);
3603 }
3604
3605 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3606 {
3607 int err;
3608 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3609 int cpu;
3610
3611 if (!vmx)
3612 return ERR_PTR(-ENOMEM);
3613
3614 allocate_vpid(vmx);
3615
3616 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3617 if (err)
3618 goto free_vcpu;
3619
3620 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3621 if (!vmx->guest_msrs) {
3622 err = -ENOMEM;
3623 goto uninit_vcpu;
3624 }
3625
3626 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3627 if (!vmx->host_msrs)
3628 goto free_guest_msrs;
3629
3630 vmx->vmcs = alloc_vmcs();
3631 if (!vmx->vmcs)
3632 goto free_msrs;
3633
3634 vmcs_clear(vmx->vmcs);
3635
3636 cpu = get_cpu();
3637 vmx_vcpu_load(&vmx->vcpu, cpu);
3638 err = vmx_vcpu_setup(vmx);
3639 vmx_vcpu_put(&vmx->vcpu);
3640 put_cpu();
3641 if (err)
3642 goto free_vmcs;
3643 if (vm_need_virtualize_apic_accesses(kvm))
3644 if (alloc_apic_access_page(kvm) != 0)
3645 goto free_vmcs;
3646
3647 if (enable_ept)
3648 if (alloc_identity_pagetable(kvm) != 0)
3649 goto free_vmcs;
3650
3651 return &vmx->vcpu;
3652
3653 free_vmcs:
3654 free_vmcs(vmx->vmcs);
3655 free_msrs:
3656 kfree(vmx->host_msrs);
3657 free_guest_msrs:
3658 kfree(vmx->guest_msrs);
3659 uninit_vcpu:
3660 kvm_vcpu_uninit(&vmx->vcpu);
3661 free_vcpu:
3662 kmem_cache_free(kvm_vcpu_cache, vmx);
3663 return ERR_PTR(err);
3664 }
3665
3666 static void __init vmx_check_processor_compat(void *rtn)
3667 {
3668 struct vmcs_config vmcs_conf;
3669
3670 *(int *)rtn = 0;
3671 if (setup_vmcs_config(&vmcs_conf) < 0)
3672 *(int *)rtn = -EIO;
3673 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3674 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3675 smp_processor_id());
3676 *(int *)rtn = -EIO;
3677 }
3678 }
3679
3680 static int get_ept_level(void)
3681 {
3682 return VMX_EPT_DEFAULT_GAW + 1;
3683 }
3684
3685 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3686 {
3687 u64 ret;
3688
3689 /* For VT-d and EPT combination
3690 * 1. MMIO: always map as UC
3691 * 2. EPT with VT-d:
3692 * a. VT-d without snooping control feature: can't guarantee the
3693 * result, try to trust guest.
3694 * b. VT-d with snooping control feature: snooping control feature of
3695 * VT-d engine can guarantee the cache correctness. Just set it
3696 * to WB to keep consistent with host. So the same as item 3.
3697 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3698 * consistent with host MTRR
3699 */
3700 if (is_mmio)
3701 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3702 else if (vcpu->kvm->arch.iommu_domain &&
3703 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3704 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3705 VMX_EPT_MT_EPTE_SHIFT;
3706 else
3707 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3708 | VMX_EPT_IGMT_BIT;
3709
3710 return ret;
3711 }
3712
3713 static struct kvm_x86_ops vmx_x86_ops = {
3714 .cpu_has_kvm_support = cpu_has_kvm_support,
3715 .disabled_by_bios = vmx_disabled_by_bios,
3716 .hardware_setup = hardware_setup,
3717 .hardware_unsetup = hardware_unsetup,
3718 .check_processor_compatibility = vmx_check_processor_compat,
3719 .hardware_enable = hardware_enable,
3720 .hardware_disable = hardware_disable,
3721 .cpu_has_accelerated_tpr = report_flexpriority,
3722
3723 .vcpu_create = vmx_create_vcpu,
3724 .vcpu_free = vmx_free_vcpu,
3725 .vcpu_reset = vmx_vcpu_reset,
3726
3727 .prepare_guest_switch = vmx_save_host_state,
3728 .vcpu_load = vmx_vcpu_load,
3729 .vcpu_put = vmx_vcpu_put,
3730
3731 .set_guest_debug = set_guest_debug,
3732 .get_msr = vmx_get_msr,
3733 .set_msr = vmx_set_msr,
3734 .get_segment_base = vmx_get_segment_base,
3735 .get_segment = vmx_get_segment,
3736 .set_segment = vmx_set_segment,
3737 .get_cpl = vmx_get_cpl,
3738 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3739 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3740 .set_cr0 = vmx_set_cr0,
3741 .set_cr3 = vmx_set_cr3,
3742 .set_cr4 = vmx_set_cr4,
3743 .set_efer = vmx_set_efer,
3744 .get_idt = vmx_get_idt,
3745 .set_idt = vmx_set_idt,
3746 .get_gdt = vmx_get_gdt,
3747 .set_gdt = vmx_set_gdt,
3748 .cache_reg = vmx_cache_reg,
3749 .get_rflags = vmx_get_rflags,
3750 .set_rflags = vmx_set_rflags,
3751
3752 .tlb_flush = vmx_flush_tlb,
3753
3754 .run = vmx_vcpu_run,
3755 .handle_exit = vmx_handle_exit,
3756 .skip_emulated_instruction = skip_emulated_instruction,
3757 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3758 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3759 .patch_hypercall = vmx_patch_hypercall,
3760 .set_irq = vmx_inject_irq,
3761 .set_nmi = vmx_inject_nmi,
3762 .queue_exception = vmx_queue_exception,
3763 .interrupt_allowed = vmx_interrupt_allowed,
3764 .nmi_allowed = vmx_nmi_allowed,
3765 .enable_nmi_window = enable_nmi_window,
3766 .enable_irq_window = enable_irq_window,
3767 .update_cr8_intercept = update_cr8_intercept,
3768
3769 .set_tss_addr = vmx_set_tss_addr,
3770 .get_tdp_level = get_ept_level,
3771 .get_mt_mask = vmx_get_mt_mask,
3772 };
3773
3774 static int __init vmx_init(void)
3775 {
3776 int r;
3777
3778 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3779 if (!vmx_io_bitmap_a)
3780 return -ENOMEM;
3781
3782 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3783 if (!vmx_io_bitmap_b) {
3784 r = -ENOMEM;
3785 goto out;
3786 }
3787
3788 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3789 if (!vmx_msr_bitmap_legacy) {
3790 r = -ENOMEM;
3791 goto out1;
3792 }
3793
3794 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3795 if (!vmx_msr_bitmap_longmode) {
3796 r = -ENOMEM;
3797 goto out2;
3798 }
3799
3800 /*
3801 * Allow direct access to the PC debug port (it is often used for I/O
3802 * delays, but the vmexits simply slow things down).
3803 */
3804 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3805 clear_bit(0x80, vmx_io_bitmap_a);
3806
3807 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3808
3809 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3810 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3811
3812 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3813
3814 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3815 if (r)
3816 goto out3;
3817
3818 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3819 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3820 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3821 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3822 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3823 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3824
3825 if (enable_ept) {
3826 bypass_guest_pf = 0;
3827 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3828 VMX_EPT_WRITABLE_MASK);
3829 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3830 VMX_EPT_EXECUTABLE_MASK);
3831 kvm_enable_tdp();
3832 } else
3833 kvm_disable_tdp();
3834
3835 if (bypass_guest_pf)
3836 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3837
3838 ept_sync_global();
3839
3840 return 0;
3841
3842 out3:
3843 free_page((unsigned long)vmx_msr_bitmap_longmode);
3844 out2:
3845 free_page((unsigned long)vmx_msr_bitmap_legacy);
3846 out1:
3847 free_page((unsigned long)vmx_io_bitmap_b);
3848 out:
3849 free_page((unsigned long)vmx_io_bitmap_a);
3850 return r;
3851 }
3852
3853 static void __exit vmx_exit(void)
3854 {
3855 free_page((unsigned long)vmx_msr_bitmap_legacy);
3856 free_page((unsigned long)vmx_msr_bitmap_longmode);
3857 free_page((unsigned long)vmx_io_bitmap_b);
3858 free_page((unsigned long)vmx_io_bitmap_a);
3859
3860 kvm_exit();
3861 }
3862
3863 module_init(vmx_init)
3864 module_exit(vmx_exit)
Linux kernel - Deliverables
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