projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: x86: add functions to get the cpl of vcpu
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29
30 #include <asm/io.h>
31 #include <asm/desc.h>
32
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
35
36 static int bypass_guest_pf = 1;
37 module_param(bypass_guest_pf, bool, 0);
38
39 static int enable_vpid = 1;
40 module_param(enable_vpid, bool, 0);
41
42 static int flexpriority_enabled = 1;
43 module_param(flexpriority_enabled, bool, 0);
44
45 struct vmcs {
46 u32 revision_id;
47 u32 abort;
48 char data[0];
49 };
50
51 struct vcpu_vmx {
52 struct kvm_vcpu vcpu;
53 int launched;
54 u8 fail;
55 u32 idt_vectoring_info;
56 struct kvm_msr_entry *guest_msrs;
57 struct kvm_msr_entry *host_msrs;
58 int nmsrs;
59 int save_nmsrs;
60 int msr_offset_efer;
61 #ifdef CONFIG_X86_64
62 int msr_offset_kernel_gs_base;
63 #endif
64 struct vmcs *vmcs;
65 struct {
66 int loaded;
67 u16 fs_sel, gs_sel, ldt_sel;
68 int gs_ldt_reload_needed;
69 int fs_reload_needed;
70 int guest_efer_loaded;
71 } host_state;
72 struct {
73 struct {
74 bool pending;
75 u8 vector;
76 unsigned rip;
77 } irq;
78 } rmode;
79 int vpid;
80 };
81
82 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
83 {
84 return container_of(vcpu, struct vcpu_vmx, vcpu);
85 }
86
87 static int init_rmode_tss(struct kvm *kvm);
88
89 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
90 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
91
92 static struct page *vmx_io_bitmap_a;
93 static struct page *vmx_io_bitmap_b;
94
95 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
96 static DEFINE_SPINLOCK(vmx_vpid_lock);
97
98 static struct vmcs_config {
99 int size;
100 int order;
101 u32 revision_id;
102 u32 pin_based_exec_ctrl;
103 u32 cpu_based_exec_ctrl;
104 u32 cpu_based_2nd_exec_ctrl;
105 u32 vmexit_ctrl;
106 u32 vmentry_ctrl;
107 } vmcs_config;
108
109 #define VMX_SEGMENT_FIELD(seg) \
110 [VCPU_SREG_##seg] = { \
111 .selector = GUEST_##seg##_SELECTOR, \
112 .base = GUEST_##seg##_BASE, \
113 .limit = GUEST_##seg##_LIMIT, \
114 .ar_bytes = GUEST_##seg##_AR_BYTES, \
115 }
116
117 static struct kvm_vmx_segment_field {
118 unsigned selector;
119 unsigned base;
120 unsigned limit;
121 unsigned ar_bytes;
122 } kvm_vmx_segment_fields[] = {
123 VMX_SEGMENT_FIELD(CS),
124 VMX_SEGMENT_FIELD(DS),
125 VMX_SEGMENT_FIELD(ES),
126 VMX_SEGMENT_FIELD(FS),
127 VMX_SEGMENT_FIELD(GS),
128 VMX_SEGMENT_FIELD(SS),
129 VMX_SEGMENT_FIELD(TR),
130 VMX_SEGMENT_FIELD(LDTR),
131 };
132
133 /*
134 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
135 * away by decrementing the array size.
136 */
137 static const u32 vmx_msr_index[] = {
138 #ifdef CONFIG_X86_64
139 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
140 #endif
141 MSR_EFER, MSR_K6_STAR,
142 };
143 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
144
145 static void load_msrs(struct kvm_msr_entry *e, int n)
146 {
147 int i;
148
149 for (i = 0; i < n; ++i)
150 wrmsrl(e[i].index, e[i].data);
151 }
152
153 static void save_msrs(struct kvm_msr_entry *e, int n)
154 {
155 int i;
156
157 for (i = 0; i < n; ++i)
158 rdmsrl(e[i].index, e[i].data);
159 }
160
161 static inline int is_page_fault(u32 intr_info)
162 {
163 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
164 INTR_INFO_VALID_MASK)) ==
165 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
166 }
167
168 static inline int is_no_device(u32 intr_info)
169 {
170 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
171 INTR_INFO_VALID_MASK)) ==
172 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
173 }
174
175 static inline int is_invalid_opcode(u32 intr_info)
176 {
177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
178 INTR_INFO_VALID_MASK)) ==
179 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
180 }
181
182 static inline int is_external_interrupt(u32 intr_info)
183 {
184 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
185 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
186 }
187
188 static inline int cpu_has_vmx_tpr_shadow(void)
189 {
190 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
191 }
192
193 static inline int vm_need_tpr_shadow(struct kvm *kvm)
194 {
195 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
196 }
197
198 static inline int cpu_has_secondary_exec_ctrls(void)
199 {
200 return (vmcs_config.cpu_based_exec_ctrl &
201 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
202 }
203
204 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
205 {
206 return flexpriority_enabled
207 && (vmcs_config.cpu_based_2nd_exec_ctrl &
208 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
209 }
210
211 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
212 {
213 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
214 (irqchip_in_kernel(kvm)));
215 }
216
217 static inline int cpu_has_vmx_vpid(void)
218 {
219 return (vmcs_config.cpu_based_2nd_exec_ctrl &
220 SECONDARY_EXEC_ENABLE_VPID);
221 }
222
223 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
224 {
225 int i;
226
227 for (i = 0; i < vmx->nmsrs; ++i)
228 if (vmx->guest_msrs[i].index == msr)
229 return i;
230 return -1;
231 }
232
233 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
234 {
235 struct {
236 u64 vpid : 16;
237 u64 rsvd : 48;
238 u64 gva;
239 } operand = { vpid, 0, gva };
240
241 asm volatile (ASM_VMX_INVVPID
242 /* CF==1 or ZF==1 --> rc = -1 */
243 "; ja 1f ; ud2 ; 1:"
244 : : "a"(&operand), "c"(ext) : "cc", "memory");
245 }
246
247 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
248 {
249 int i;
250
251 i = __find_msr_index(vmx, msr);
252 if (i >= 0)
253 return &vmx->guest_msrs[i];
254 return NULL;
255 }
256
257 static void vmcs_clear(struct vmcs *vmcs)
258 {
259 u64 phys_addr = __pa(vmcs);
260 u8 error;
261
262 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
263 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
264 : "cc", "memory");
265 if (error)
266 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
267 vmcs, phys_addr);
268 }
269
270 static void __vcpu_clear(void *arg)
271 {
272 struct vcpu_vmx *vmx = arg;
273 int cpu = raw_smp_processor_id();
274
275 if (vmx->vcpu.cpu == cpu)
276 vmcs_clear(vmx->vmcs);
277 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
278 per_cpu(current_vmcs, cpu) = NULL;
279 rdtscll(vmx->vcpu.arch.host_tsc);
280 }
281
282 static void vcpu_clear(struct vcpu_vmx *vmx)
283 {
284 if (vmx->vcpu.cpu == -1)
285 return;
286 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
287 vmx->launched = 0;
288 }
289
290 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
291 {
292 if (vmx->vpid == 0)
293 return;
294
295 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
296 }
297
298 static unsigned long vmcs_readl(unsigned long field)
299 {
300 unsigned long value;
301
302 asm volatile (ASM_VMX_VMREAD_RDX_RAX
303 : "=a"(value) : "d"(field) : "cc");
304 return value;
305 }
306
307 static u16 vmcs_read16(unsigned long field)
308 {
309 return vmcs_readl(field);
310 }
311
312 static u32 vmcs_read32(unsigned long field)
313 {
314 return vmcs_readl(field);
315 }
316
317 static u64 vmcs_read64(unsigned long field)
318 {
319 #ifdef CONFIG_X86_64
320 return vmcs_readl(field);
321 #else
322 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
323 #endif
324 }
325
326 static noinline void vmwrite_error(unsigned long field, unsigned long value)
327 {
328 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
329 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
330 dump_stack();
331 }
332
333 static void vmcs_writel(unsigned long field, unsigned long value)
334 {
335 u8 error;
336
337 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
338 : "=q"(error) : "a"(value), "d"(field) : "cc");
339 if (unlikely(error))
340 vmwrite_error(field, value);
341 }
342
343 static void vmcs_write16(unsigned long field, u16 value)
344 {
345 vmcs_writel(field, value);
346 }
347
348 static void vmcs_write32(unsigned long field, u32 value)
349 {
350 vmcs_writel(field, value);
351 }
352
353 static void vmcs_write64(unsigned long field, u64 value)
354 {
355 #ifdef CONFIG_X86_64
356 vmcs_writel(field, value);
357 #else
358 vmcs_writel(field, value);
359 asm volatile ("");
360 vmcs_writel(field+1, value >> 32);
361 #endif
362 }
363
364 static void vmcs_clear_bits(unsigned long field, u32 mask)
365 {
366 vmcs_writel(field, vmcs_readl(field) & ~mask);
367 }
368
369 static void vmcs_set_bits(unsigned long field, u32 mask)
370 {
371 vmcs_writel(field, vmcs_readl(field) | mask);
372 }
373
374 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
375 {
376 u32 eb;
377
378 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
379 if (!vcpu->fpu_active)
380 eb |= 1u << NM_VECTOR;
381 if (vcpu->guest_debug.enabled)
382 eb |= 1u << 1;
383 if (vcpu->arch.rmode.active)
384 eb = ~0;
385 vmcs_write32(EXCEPTION_BITMAP, eb);
386 }
387
388 static void reload_tss(void)
389 {
390 /*
391 * VT restores TR but not its size. Useless.
392 */
393 struct descriptor_table gdt;
394 struct desc_struct *descs;
395
396 get_gdt(&gdt);
397 descs = (void *)gdt.base;
398 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
399 load_TR_desc();
400 }
401
402 static void load_transition_efer(struct vcpu_vmx *vmx)
403 {
404 int efer_offset = vmx->msr_offset_efer;
405 u64 host_efer = vmx->host_msrs[efer_offset].data;
406 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
407 u64 ignore_bits;
408
409 if (efer_offset < 0)
410 return;
411 /*
412 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
413 * outside long mode
414 */
415 ignore_bits = EFER_NX | EFER_SCE;
416 #ifdef CONFIG_X86_64
417 ignore_bits |= EFER_LMA | EFER_LME;
418 /* SCE is meaningful only in long mode on Intel */
419 if (guest_efer & EFER_LMA)
420 ignore_bits &= ~(u64)EFER_SCE;
421 #endif
422 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
423 return;
424
425 vmx->host_state.guest_efer_loaded = 1;
426 guest_efer &= ~ignore_bits;
427 guest_efer |= host_efer & ignore_bits;
428 wrmsrl(MSR_EFER, guest_efer);
429 vmx->vcpu.stat.efer_reload++;
430 }
431
432 static void reload_host_efer(struct vcpu_vmx *vmx)
433 {
434 if (vmx->host_state.guest_efer_loaded) {
435 vmx->host_state.guest_efer_loaded = 0;
436 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
437 }
438 }
439
440 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
441 {
442 struct vcpu_vmx *vmx = to_vmx(vcpu);
443
444 if (vmx->host_state.loaded)
445 return;
446
447 vmx->host_state.loaded = 1;
448 /*
449 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
450 * allow segment selectors with cpl > 0 or ti == 1.
451 */
452 vmx->host_state.ldt_sel = read_ldt();
453 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
454 vmx->host_state.fs_sel = read_fs();
455 if (!(vmx->host_state.fs_sel & 7)) {
456 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
457 vmx->host_state.fs_reload_needed = 0;
458 } else {
459 vmcs_write16(HOST_FS_SELECTOR, 0);
460 vmx->host_state.fs_reload_needed = 1;
461 }
462 vmx->host_state.gs_sel = read_gs();
463 if (!(vmx->host_state.gs_sel & 7))
464 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
465 else {
466 vmcs_write16(HOST_GS_SELECTOR, 0);
467 vmx->host_state.gs_ldt_reload_needed = 1;
468 }
469
470 #ifdef CONFIG_X86_64
471 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
472 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
473 #else
474 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
475 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
476 #endif
477
478 #ifdef CONFIG_X86_64
479 if (is_long_mode(&vmx->vcpu))
480 save_msrs(vmx->host_msrs +
481 vmx->msr_offset_kernel_gs_base, 1);
482
483 #endif
484 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
485 load_transition_efer(vmx);
486 }
487
488 static void vmx_load_host_state(struct vcpu_vmx *vmx)
489 {
490 unsigned long flags;
491
492 if (!vmx->host_state.loaded)
493 return;
494
495 ++vmx->vcpu.stat.host_state_reload;
496 vmx->host_state.loaded = 0;
497 if (vmx->host_state.fs_reload_needed)
498 load_fs(vmx->host_state.fs_sel);
499 if (vmx->host_state.gs_ldt_reload_needed) {
500 load_ldt(vmx->host_state.ldt_sel);
501 /*
502 * If we have to reload gs, we must take care to
503 * preserve our gs base.
504 */
505 local_irq_save(flags);
506 load_gs(vmx->host_state.gs_sel);
507 #ifdef CONFIG_X86_64
508 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
509 #endif
510 local_irq_restore(flags);
511 }
512 reload_tss();
513 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
514 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
515 reload_host_efer(vmx);
516 }
517
518 /*
519 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
520 * vcpu mutex is already taken.
521 */
522 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
523 {
524 struct vcpu_vmx *vmx = to_vmx(vcpu);
525 u64 phys_addr = __pa(vmx->vmcs);
526 u64 tsc_this, delta, new_offset;
527
528 if (vcpu->cpu != cpu) {
529 vcpu_clear(vmx);
530 kvm_migrate_apic_timer(vcpu);
531 vpid_sync_vcpu_all(vmx);
532 }
533
534 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
535 u8 error;
536
537 per_cpu(current_vmcs, cpu) = vmx->vmcs;
538 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
539 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
540 : "cc");
541 if (error)
542 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
543 vmx->vmcs, phys_addr);
544 }
545
546 if (vcpu->cpu != cpu) {
547 struct descriptor_table dt;
548 unsigned long sysenter_esp;
549
550 vcpu->cpu = cpu;
551 /*
552 * Linux uses per-cpu TSS and GDT, so set these when switching
553 * processors.
554 */
555 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
556 get_gdt(&dt);
557 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
558
559 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
560 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
561
562 /*
563 * Make sure the time stamp counter is monotonous.
564 */
565 rdtscll(tsc_this);
566 if (tsc_this < vcpu->arch.host_tsc) {
567 delta = vcpu->arch.host_tsc - tsc_this;
568 new_offset = vmcs_read64(TSC_OFFSET) + delta;
569 vmcs_write64(TSC_OFFSET, new_offset);
570 }
571 }
572 }
573
574 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
575 {
576 vmx_load_host_state(to_vmx(vcpu));
577 }
578
579 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
580 {
581 if (vcpu->fpu_active)
582 return;
583 vcpu->fpu_active = 1;
584 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
585 if (vcpu->arch.cr0 & X86_CR0_TS)
586 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
587 update_exception_bitmap(vcpu);
588 }
589
590 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
591 {
592 if (!vcpu->fpu_active)
593 return;
594 vcpu->fpu_active = 0;
595 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
596 update_exception_bitmap(vcpu);
597 }
598
599 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
600 {
601 vcpu_clear(to_vmx(vcpu));
602 }
603
604 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
605 {
606 return vmcs_readl(GUEST_RFLAGS);
607 }
608
609 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
610 {
611 if (vcpu->arch.rmode.active)
612 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
613 vmcs_writel(GUEST_RFLAGS, rflags);
614 }
615
616 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
617 {
618 unsigned long rip;
619 u32 interruptibility;
620
621 rip = vmcs_readl(GUEST_RIP);
622 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
623 vmcs_writel(GUEST_RIP, rip);
624
625 /*
626 * We emulated an instruction, so temporary interrupt blocking
627 * should be removed, if set.
628 */
629 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
630 if (interruptibility & 3)
631 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
632 interruptibility & ~3);
633 vcpu->arch.interrupt_window_open = 1;
634 }
635
636 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
637 bool has_error_code, u32 error_code)
638 {
639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
640 nr | INTR_TYPE_EXCEPTION
641 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
642 | INTR_INFO_VALID_MASK);
643 if (has_error_code)
644 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
645 }
646
647 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
648 {
649 struct vcpu_vmx *vmx = to_vmx(vcpu);
650
651 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
652 }
653
654 /*
655 * Swap MSR entry in host/guest MSR entry array.
656 */
657 #ifdef CONFIG_X86_64
658 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
659 {
660 struct kvm_msr_entry tmp;
661
662 tmp = vmx->guest_msrs[to];
663 vmx->guest_msrs[to] = vmx->guest_msrs[from];
664 vmx->guest_msrs[from] = tmp;
665 tmp = vmx->host_msrs[to];
666 vmx->host_msrs[to] = vmx->host_msrs[from];
667 vmx->host_msrs[from] = tmp;
668 }
669 #endif
670
671 /*
672 * Set up the vmcs to automatically save and restore system
673 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
674 * mode, as fiddling with msrs is very expensive.
675 */
676 static void setup_msrs(struct vcpu_vmx *vmx)
677 {
678 int save_nmsrs;
679
680 vmx_load_host_state(vmx);
681 save_nmsrs = 0;
682 #ifdef CONFIG_X86_64
683 if (is_long_mode(&vmx->vcpu)) {
684 int index;
685
686 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
687 if (index >= 0)
688 move_msr_up(vmx, index, save_nmsrs++);
689 index = __find_msr_index(vmx, MSR_LSTAR);
690 if (index >= 0)
691 move_msr_up(vmx, index, save_nmsrs++);
692 index = __find_msr_index(vmx, MSR_CSTAR);
693 if (index >= 0)
694 move_msr_up(vmx, index, save_nmsrs++);
695 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
696 if (index >= 0)
697 move_msr_up(vmx, index, save_nmsrs++);
698 /*
699 * MSR_K6_STAR is only needed on long mode guests, and only
700 * if efer.sce is enabled.
701 */
702 index = __find_msr_index(vmx, MSR_K6_STAR);
703 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
704 move_msr_up(vmx, index, save_nmsrs++);
705 }
706 #endif
707 vmx->save_nmsrs = save_nmsrs;
708
709 #ifdef CONFIG_X86_64
710 vmx->msr_offset_kernel_gs_base =
711 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
712 #endif
713 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
714 }
715
716 /*
717 * reads and returns guest's timestamp counter "register"
718 * guest_tsc = host_tsc + tsc_offset -- 21.3
719 */
720 static u64 guest_read_tsc(void)
721 {
722 u64 host_tsc, tsc_offset;
723
724 rdtscll(host_tsc);
725 tsc_offset = vmcs_read64(TSC_OFFSET);
726 return host_tsc + tsc_offset;
727 }
728
729 /*
730 * writes 'guest_tsc' into guest's timestamp counter "register"
731 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
732 */
733 static void guest_write_tsc(u64 guest_tsc)
734 {
735 u64 host_tsc;
736
737 rdtscll(host_tsc);
738 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
739 }
740
741 /*
742 * Reads an msr value (of 'msr_index') into 'pdata'.
743 * Returns 0 on success, non-0 otherwise.
744 * Assumes vcpu_load() was already called.
745 */
746 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
747 {
748 u64 data;
749 struct kvm_msr_entry *msr;
750
751 if (!pdata) {
752 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
753 return -EINVAL;
754 }
755
756 switch (msr_index) {
757 #ifdef CONFIG_X86_64
758 case MSR_FS_BASE:
759 data = vmcs_readl(GUEST_FS_BASE);
760 break;
761 case MSR_GS_BASE:
762 data = vmcs_readl(GUEST_GS_BASE);
763 break;
764 case MSR_EFER:
765 return kvm_get_msr_common(vcpu, msr_index, pdata);
766 #endif
767 case MSR_IA32_TIME_STAMP_COUNTER:
768 data = guest_read_tsc();
769 break;
770 case MSR_IA32_SYSENTER_CS:
771 data = vmcs_read32(GUEST_SYSENTER_CS);
772 break;
773 case MSR_IA32_SYSENTER_EIP:
774 data = vmcs_readl(GUEST_SYSENTER_EIP);
775 break;
776 case MSR_IA32_SYSENTER_ESP:
777 data = vmcs_readl(GUEST_SYSENTER_ESP);
778 break;
779 default:
780 msr = find_msr_entry(to_vmx(vcpu), msr_index);
781 if (msr) {
782 data = msr->data;
783 break;
784 }
785 return kvm_get_msr_common(vcpu, msr_index, pdata);
786 }
787
788 *pdata = data;
789 return 0;
790 }
791
792 /*
793 * Writes msr value into into the appropriate "register".
794 * Returns 0 on success, non-0 otherwise.
795 * Assumes vcpu_load() was already called.
796 */
797 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
798 {
799 struct vcpu_vmx *vmx = to_vmx(vcpu);
800 struct kvm_msr_entry *msr;
801 int ret = 0;
802
803 switch (msr_index) {
804 #ifdef CONFIG_X86_64
805 case MSR_EFER:
806 ret = kvm_set_msr_common(vcpu, msr_index, data);
807 if (vmx->host_state.loaded) {
808 reload_host_efer(vmx);
809 load_transition_efer(vmx);
810 }
811 break;
812 case MSR_FS_BASE:
813 vmcs_writel(GUEST_FS_BASE, data);
814 break;
815 case MSR_GS_BASE:
816 vmcs_writel(GUEST_GS_BASE, data);
817 break;
818 #endif
819 case MSR_IA32_SYSENTER_CS:
820 vmcs_write32(GUEST_SYSENTER_CS, data);
821 break;
822 case MSR_IA32_SYSENTER_EIP:
823 vmcs_writel(GUEST_SYSENTER_EIP, data);
824 break;
825 case MSR_IA32_SYSENTER_ESP:
826 vmcs_writel(GUEST_SYSENTER_ESP, data);
827 break;
828 case MSR_IA32_TIME_STAMP_COUNTER:
829 guest_write_tsc(data);
830 break;
831 default:
832 msr = find_msr_entry(vmx, msr_index);
833 if (msr) {
834 msr->data = data;
835 if (vmx->host_state.loaded)
836 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
837 break;
838 }
839 ret = kvm_set_msr_common(vcpu, msr_index, data);
840 }
841
842 return ret;
843 }
844
845 /*
846 * Sync the rsp and rip registers into the vcpu structure. This allows
847 * registers to be accessed by indexing vcpu->arch.regs.
848 */
849 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
850 {
851 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
852 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
853 }
854
855 /*
856 * Syncs rsp and rip back into the vmcs. Should be called after possible
857 * modification.
858 */
859 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
860 {
861 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
862 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
863 }
864
865 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
866 {
867 unsigned long dr7 = 0x400;
868 int old_singlestep;
869
870 old_singlestep = vcpu->guest_debug.singlestep;
871
872 vcpu->guest_debug.enabled = dbg->enabled;
873 if (vcpu->guest_debug.enabled) {
874 int i;
875
876 dr7 |= 0x200; /* exact */
877 for (i = 0; i < 4; ++i) {
878 if (!dbg->breakpoints[i].enabled)
879 continue;
880 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
881 dr7 |= 2 << (i*2); /* global enable */
882 dr7 |= 0 << (i*4+16); /* execution breakpoint */
883 }
884
885 vcpu->guest_debug.singlestep = dbg->singlestep;
886 } else
887 vcpu->guest_debug.singlestep = 0;
888
889 if (old_singlestep && !vcpu->guest_debug.singlestep) {
890 unsigned long flags;
891
892 flags = vmcs_readl(GUEST_RFLAGS);
893 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
894 vmcs_writel(GUEST_RFLAGS, flags);
895 }
896
897 update_exception_bitmap(vcpu);
898 vmcs_writel(GUEST_DR7, dr7);
899
900 return 0;
901 }
902
903 static int vmx_get_irq(struct kvm_vcpu *vcpu)
904 {
905 struct vcpu_vmx *vmx = to_vmx(vcpu);
906 u32 idtv_info_field;
907
908 idtv_info_field = vmx->idt_vectoring_info;
909 if (idtv_info_field & INTR_INFO_VALID_MASK) {
910 if (is_external_interrupt(idtv_info_field))
911 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
912 else
913 printk(KERN_DEBUG "pending exception: not handled yet\n");
914 }
915 return -1;
916 }
917
918 static __init int cpu_has_kvm_support(void)
919 {
920 unsigned long ecx = cpuid_ecx(1);
921 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
922 }
923
924 static __init int vmx_disabled_by_bios(void)
925 {
926 u64 msr;
927
928 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
929 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
930 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
931 == MSR_IA32_FEATURE_CONTROL_LOCKED;
932 /* locked but not enabled */
933 }
934
935 static void hardware_enable(void *garbage)
936 {
937 int cpu = raw_smp_processor_id();
938 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
939 u64 old;
940
941 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
942 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
943 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
944 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
945 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
946 /* enable and lock */
947 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
948 MSR_IA32_FEATURE_CONTROL_LOCKED |
949 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
950 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
951 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
952 : "memory", "cc");
953 }
954
955 static void hardware_disable(void *garbage)
956 {
957 asm volatile (ASM_VMX_VMXOFF : : : "cc");
958 }
959
960 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
961 u32 msr, u32 *result)
962 {
963 u32 vmx_msr_low, vmx_msr_high;
964 u32 ctl = ctl_min | ctl_opt;
965
966 rdmsr(msr, vmx_msr_low, vmx_msr_high);
967
968 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
969 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
970
971 /* Ensure minimum (required) set of control bits are supported. */
972 if (ctl_min & ~ctl)
973 return -EIO;
974
975 *result = ctl;
976 return 0;
977 }
978
979 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
980 {
981 u32 vmx_msr_low, vmx_msr_high;
982 u32 min, opt;
983 u32 _pin_based_exec_control = 0;
984 u32 _cpu_based_exec_control = 0;
985 u32 _cpu_based_2nd_exec_control = 0;
986 u32 _vmexit_control = 0;
987 u32 _vmentry_control = 0;
988
989 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
990 opt = 0;
991 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
992 &_pin_based_exec_control) < 0)
993 return -EIO;
994
995 min = CPU_BASED_HLT_EXITING |
996 #ifdef CONFIG_X86_64
997 CPU_BASED_CR8_LOAD_EXITING |
998 CPU_BASED_CR8_STORE_EXITING |
999 #endif
1000 CPU_BASED_USE_IO_BITMAPS |
1001 CPU_BASED_MOV_DR_EXITING |
1002 CPU_BASED_USE_TSC_OFFSETING;
1003 opt = CPU_BASED_TPR_SHADOW |
1004 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1005 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1006 &_cpu_based_exec_control) < 0)
1007 return -EIO;
1008 #ifdef CONFIG_X86_64
1009 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1010 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1011 ~CPU_BASED_CR8_STORE_EXITING;
1012 #endif
1013 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1014 min = 0;
1015 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1016 SECONDARY_EXEC_WBINVD_EXITING |
1017 SECONDARY_EXEC_ENABLE_VPID;
1018 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
1019 &_cpu_based_2nd_exec_control) < 0)
1020 return -EIO;
1021 }
1022 #ifndef CONFIG_X86_64
1023 if (!(_cpu_based_2nd_exec_control &
1024 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1025 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1026 #endif
1027
1028 min = 0;
1029 #ifdef CONFIG_X86_64
1030 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1031 #endif
1032 opt = 0;
1033 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1034 &_vmexit_control) < 0)
1035 return -EIO;
1036
1037 min = opt = 0;
1038 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1039 &_vmentry_control) < 0)
1040 return -EIO;
1041
1042 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1043
1044 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1045 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1046 return -EIO;
1047
1048 #ifdef CONFIG_X86_64
1049 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1050 if (vmx_msr_high & (1u<<16))
1051 return -EIO;
1052 #endif
1053
1054 /* Require Write-Back (WB) memory type for VMCS accesses. */
1055 if (((vmx_msr_high >> 18) & 15) != 6)
1056 return -EIO;
1057
1058 vmcs_conf->size = vmx_msr_high & 0x1fff;
1059 vmcs_conf->order = get_order(vmcs_config.size);
1060 vmcs_conf->revision_id = vmx_msr_low;
1061
1062 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1063 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1064 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1065 vmcs_conf->vmexit_ctrl = _vmexit_control;
1066 vmcs_conf->vmentry_ctrl = _vmentry_control;
1067
1068 return 0;
1069 }
1070
1071 static struct vmcs *alloc_vmcs_cpu(int cpu)
1072 {
1073 int node = cpu_to_node(cpu);
1074 struct page *pages;
1075 struct vmcs *vmcs;
1076
1077 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1078 if (!pages)
1079 return NULL;
1080 vmcs = page_address(pages);
1081 memset(vmcs, 0, vmcs_config.size);
1082 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1083 return vmcs;
1084 }
1085
1086 static struct vmcs *alloc_vmcs(void)
1087 {
1088 return alloc_vmcs_cpu(raw_smp_processor_id());
1089 }
1090
1091 static void free_vmcs(struct vmcs *vmcs)
1092 {
1093 free_pages((unsigned long)vmcs, vmcs_config.order);
1094 }
1095
1096 static void free_kvm_area(void)
1097 {
1098 int cpu;
1099
1100 for_each_online_cpu(cpu)
1101 free_vmcs(per_cpu(vmxarea, cpu));
1102 }
1103
1104 static __init int alloc_kvm_area(void)
1105 {
1106 int cpu;
1107
1108 for_each_online_cpu(cpu) {
1109 struct vmcs *vmcs;
1110
1111 vmcs = alloc_vmcs_cpu(cpu);
1112 if (!vmcs) {
1113 free_kvm_area();
1114 return -ENOMEM;
1115 }
1116
1117 per_cpu(vmxarea, cpu) = vmcs;
1118 }
1119 return 0;
1120 }
1121
1122 static __init int hardware_setup(void)
1123 {
1124 if (setup_vmcs_config(&vmcs_config) < 0)
1125 return -EIO;
1126
1127 if (boot_cpu_has(X86_FEATURE_NX))
1128 kvm_enable_efer_bits(EFER_NX);
1129
1130 return alloc_kvm_area();
1131 }
1132
1133 static __exit void hardware_unsetup(void)
1134 {
1135 free_kvm_area();
1136 }
1137
1138 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1139 {
1140 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1141
1142 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1143 vmcs_write16(sf->selector, save->selector);
1144 vmcs_writel(sf->base, save->base);
1145 vmcs_write32(sf->limit, save->limit);
1146 vmcs_write32(sf->ar_bytes, save->ar);
1147 } else {
1148 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1149 << AR_DPL_SHIFT;
1150 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1151 }
1152 }
1153
1154 static void enter_pmode(struct kvm_vcpu *vcpu)
1155 {
1156 unsigned long flags;
1157
1158 vcpu->arch.rmode.active = 0;
1159
1160 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1161 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1162 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1163
1164 flags = vmcs_readl(GUEST_RFLAGS);
1165 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1166 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1167 vmcs_writel(GUEST_RFLAGS, flags);
1168
1169 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1170 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1171
1172 update_exception_bitmap(vcpu);
1173
1174 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1175 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1176 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1177 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1178
1179 vmcs_write16(GUEST_SS_SELECTOR, 0);
1180 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1181
1182 vmcs_write16(GUEST_CS_SELECTOR,
1183 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1184 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1185 }
1186
1187 static gva_t rmode_tss_base(struct kvm *kvm)
1188 {
1189 if (!kvm->arch.tss_addr) {
1190 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1191 kvm->memslots[0].npages - 3;
1192 return base_gfn << PAGE_SHIFT;
1193 }
1194 return kvm->arch.tss_addr;
1195 }
1196
1197 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1198 {
1199 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1200
1201 save->selector = vmcs_read16(sf->selector);
1202 save->base = vmcs_readl(sf->base);
1203 save->limit = vmcs_read32(sf->limit);
1204 save->ar = vmcs_read32(sf->ar_bytes);
1205 vmcs_write16(sf->selector, save->base >> 4);
1206 vmcs_write32(sf->base, save->base & 0xfffff);
1207 vmcs_write32(sf->limit, 0xffff);
1208 vmcs_write32(sf->ar_bytes, 0xf3);
1209 }
1210
1211 static void enter_rmode(struct kvm_vcpu *vcpu)
1212 {
1213 unsigned long flags;
1214
1215 vcpu->arch.rmode.active = 1;
1216
1217 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1218 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1219
1220 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1221 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1222
1223 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1224 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1225
1226 flags = vmcs_readl(GUEST_RFLAGS);
1227 vcpu->arch.rmode.save_iopl
1228 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1229
1230 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1231
1232 vmcs_writel(GUEST_RFLAGS, flags);
1233 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1234 update_exception_bitmap(vcpu);
1235
1236 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1237 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1238 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1239
1240 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1241 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1242 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1243 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1244 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1245
1246 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1247 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1248 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1249 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1250
1251 kvm_mmu_reset_context(vcpu);
1252 init_rmode_tss(vcpu->kvm);
1253 }
1254
1255 #ifdef CONFIG_X86_64
1256
1257 static void enter_lmode(struct kvm_vcpu *vcpu)
1258 {
1259 u32 guest_tr_ar;
1260
1261 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1262 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1263 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1264 __func__);
1265 vmcs_write32(GUEST_TR_AR_BYTES,
1266 (guest_tr_ar & ~AR_TYPE_MASK)
1267 | AR_TYPE_BUSY_64_TSS);
1268 }
1269
1270 vcpu->arch.shadow_efer |= EFER_LMA;
1271
1272 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1273 vmcs_write32(VM_ENTRY_CONTROLS,
1274 vmcs_read32(VM_ENTRY_CONTROLS)
1275 | VM_ENTRY_IA32E_MODE);
1276 }
1277
1278 static void exit_lmode(struct kvm_vcpu *vcpu)
1279 {
1280 vcpu->arch.shadow_efer &= ~EFER_LMA;
1281
1282 vmcs_write32(VM_ENTRY_CONTROLS,
1283 vmcs_read32(VM_ENTRY_CONTROLS)
1284 & ~VM_ENTRY_IA32E_MODE);
1285 }
1286
1287 #endif
1288
1289 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1290 {
1291 vpid_sync_vcpu_all(to_vmx(vcpu));
1292 }
1293
1294 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1295 {
1296 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1297 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1298 }
1299
1300 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1301 {
1302 vmx_fpu_deactivate(vcpu);
1303
1304 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1305 enter_pmode(vcpu);
1306
1307 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1308 enter_rmode(vcpu);
1309
1310 #ifdef CONFIG_X86_64
1311 if (vcpu->arch.shadow_efer & EFER_LME) {
1312 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1313 enter_lmode(vcpu);
1314 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1315 exit_lmode(vcpu);
1316 }
1317 #endif
1318
1319 vmcs_writel(CR0_READ_SHADOW, cr0);
1320 vmcs_writel(GUEST_CR0,
1321 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1322 vcpu->arch.cr0 = cr0;
1323
1324 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1325 vmx_fpu_activate(vcpu);
1326 }
1327
1328 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1329 {
1330 vmx_flush_tlb(vcpu);
1331 vmcs_writel(GUEST_CR3, cr3);
1332 if (vcpu->arch.cr0 & X86_CR0_PE)
1333 vmx_fpu_deactivate(vcpu);
1334 }
1335
1336 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1337 {
1338 vmcs_writel(CR4_READ_SHADOW, cr4);
1339 vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1340 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1341 vcpu->arch.cr4 = cr4;
1342 }
1343
1344 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1345 {
1346 struct vcpu_vmx *vmx = to_vmx(vcpu);
1347 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1348
1349 vcpu->arch.shadow_efer = efer;
1350 if (!msr)
1351 return;
1352 if (efer & EFER_LMA) {
1353 vmcs_write32(VM_ENTRY_CONTROLS,
1354 vmcs_read32(VM_ENTRY_CONTROLS) |
1355 VM_ENTRY_IA32E_MODE);
1356 msr->data = efer;
1357
1358 } else {
1359 vmcs_write32(VM_ENTRY_CONTROLS,
1360 vmcs_read32(VM_ENTRY_CONTROLS) &
1361 ~VM_ENTRY_IA32E_MODE);
1362
1363 msr->data = efer & ~EFER_LME;
1364 }
1365 setup_msrs(vmx);
1366 }
1367
1368 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1369 {
1370 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1371
1372 return vmcs_readl(sf->base);
1373 }
1374
1375 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1376 struct kvm_segment *var, int seg)
1377 {
1378 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1379 u32 ar;
1380
1381 var->base = vmcs_readl(sf->base);
1382 var->limit = vmcs_read32(sf->limit);
1383 var->selector = vmcs_read16(sf->selector);
1384 ar = vmcs_read32(sf->ar_bytes);
1385 if (ar & AR_UNUSABLE_MASK)
1386 ar = 0;
1387 var->type = ar & 15;
1388 var->s = (ar >> 4) & 1;
1389 var->dpl = (ar >> 5) & 3;
1390 var->present = (ar >> 7) & 1;
1391 var->avl = (ar >> 12) & 1;
1392 var->l = (ar >> 13) & 1;
1393 var->db = (ar >> 14) & 1;
1394 var->g = (ar >> 15) & 1;
1395 var->unusable = (ar >> 16) & 1;
1396 }
1397
1398 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1399 {
1400 struct kvm_segment kvm_seg;
1401
1402 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1403 return 0;
1404
1405 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1406 return 3;
1407
1408 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1409 return kvm_seg.selector & 3;
1410 }
1411
1412 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1413 {
1414 u32 ar;
1415
1416 if (var->unusable)
1417 ar = 1 << 16;
1418 else {
1419 ar = var->type & 15;
1420 ar |= (var->s & 1) << 4;
1421 ar |= (var->dpl & 3) << 5;
1422 ar |= (var->present & 1) << 7;
1423 ar |= (var->avl & 1) << 12;
1424 ar |= (var->l & 1) << 13;
1425 ar |= (var->db & 1) << 14;
1426 ar |= (var->g & 1) << 15;
1427 }
1428 if (ar == 0) /* a 0 value means unusable */
1429 ar = AR_UNUSABLE_MASK;
1430
1431 return ar;
1432 }
1433
1434 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1435 struct kvm_segment *var, int seg)
1436 {
1437 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1438 u32 ar;
1439
1440 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1441 vcpu->arch.rmode.tr.selector = var->selector;
1442 vcpu->arch.rmode.tr.base = var->base;
1443 vcpu->arch.rmode.tr.limit = var->limit;
1444 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1445 return;
1446 }
1447 vmcs_writel(sf->base, var->base);
1448 vmcs_write32(sf->limit, var->limit);
1449 vmcs_write16(sf->selector, var->selector);
1450 if (vcpu->arch.rmode.active && var->s) {
1451 /*
1452 * Hack real-mode segments into vm86 compatibility.
1453 */
1454 if (var->base == 0xffff0000 && var->selector == 0xf000)
1455 vmcs_writel(sf->base, 0xf0000);
1456 ar = 0xf3;
1457 } else
1458 ar = vmx_segment_access_rights(var);
1459 vmcs_write32(sf->ar_bytes, ar);
1460 }
1461
1462 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1463 {
1464 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1465
1466 *db = (ar >> 14) & 1;
1467 *l = (ar >> 13) & 1;
1468 }
1469
1470 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1471 {
1472 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1473 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1474 }
1475
1476 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1477 {
1478 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1479 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1480 }
1481
1482 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1483 {
1484 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1485 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1486 }
1487
1488 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1489 {
1490 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1491 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1492 }
1493
1494 static int init_rmode_tss(struct kvm *kvm)
1495 {
1496 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1497 u16 data = 0;
1498 int ret = 0;
1499 int r;
1500
1501 down_read(&kvm->slots_lock);
1502 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1503 if (r < 0)
1504 goto out;
1505 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1506 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1507 if (r < 0)
1508 goto out;
1509 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1510 if (r < 0)
1511 goto out;
1512 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1513 if (r < 0)
1514 goto out;
1515 data = ~0;
1516 r = kvm_write_guest_page(kvm, fn, &data,
1517 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1518 sizeof(u8));
1519 if (r < 0)
1520 goto out;
1521
1522 ret = 1;
1523 out:
1524 up_read(&kvm->slots_lock);
1525 return ret;
1526 }
1527
1528 static void seg_setup(int seg)
1529 {
1530 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1531
1532 vmcs_write16(sf->selector, 0);
1533 vmcs_writel(sf->base, 0);
1534 vmcs_write32(sf->limit, 0xffff);
1535 vmcs_write32(sf->ar_bytes, 0x93);
1536 }
1537
1538 static int alloc_apic_access_page(struct kvm *kvm)
1539 {
1540 struct kvm_userspace_memory_region kvm_userspace_mem;
1541 int r = 0;
1542
1543 down_write(&kvm->slots_lock);
1544 if (kvm->arch.apic_access_page)
1545 goto out;
1546 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1547 kvm_userspace_mem.flags = 0;
1548 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1549 kvm_userspace_mem.memory_size = PAGE_SIZE;
1550 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1551 if (r)
1552 goto out;
1553
1554 down_read(&current->mm->mmap_sem);
1555 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1556 up_read(&current->mm->mmap_sem);
1557 out:
1558 up_write(&kvm->slots_lock);
1559 return r;
1560 }
1561
1562 static void allocate_vpid(struct vcpu_vmx *vmx)
1563 {
1564 int vpid;
1565
1566 vmx->vpid = 0;
1567 if (!enable_vpid || !cpu_has_vmx_vpid())
1568 return;
1569 spin_lock(&vmx_vpid_lock);
1570 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1571 if (vpid < VMX_NR_VPIDS) {
1572 vmx->vpid = vpid;
1573 __set_bit(vpid, vmx_vpid_bitmap);
1574 }
1575 spin_unlock(&vmx_vpid_lock);
1576 }
1577
1578 /*
1579 * Sets up the vmcs for emulated real mode.
1580 */
1581 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1582 {
1583 u32 host_sysenter_cs;
1584 u32 junk;
1585 unsigned long a;
1586 struct descriptor_table dt;
1587 int i;
1588 unsigned long kvm_vmx_return;
1589 u32 exec_control;
1590
1591 /* I/O */
1592 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1593 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1594
1595 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1596
1597 /* Control */
1598 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1599 vmcs_config.pin_based_exec_ctrl);
1600
1601 exec_control = vmcs_config.cpu_based_exec_ctrl;
1602 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1603 exec_control &= ~CPU_BASED_TPR_SHADOW;
1604 #ifdef CONFIG_X86_64
1605 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1606 CPU_BASED_CR8_LOAD_EXITING;
1607 #endif
1608 }
1609 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1610
1611 if (cpu_has_secondary_exec_ctrls()) {
1612 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1613 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1614 exec_control &=
1615 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1616 if (vmx->vpid == 0)
1617 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1618 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1619 }
1620
1621 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1622 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1623 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1624
1625 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1626 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1627 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1628
1629 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1630 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1631 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1632 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1633 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1634 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1635 #ifdef CONFIG_X86_64
1636 rdmsrl(MSR_FS_BASE, a);
1637 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1638 rdmsrl(MSR_GS_BASE, a);
1639 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1640 #else
1641 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1642 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1643 #endif
1644
1645 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1646
1647 get_idt(&dt);
1648 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1649
1650 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1651 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1652 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1653 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1654 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1655
1656 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1657 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1658 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1659 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1660 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1661 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1662
1663 for (i = 0; i < NR_VMX_MSR; ++i) {
1664 u32 index = vmx_msr_index[i];
1665 u32 data_low, data_high;
1666 u64 data;
1667 int j = vmx->nmsrs;
1668
1669 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1670 continue;
1671 if (wrmsr_safe(index, data_low, data_high) < 0)
1672 continue;
1673 data = data_low | ((u64)data_high << 32);
1674 vmx->host_msrs[j].index = index;
1675 vmx->host_msrs[j].reserved = 0;
1676 vmx->host_msrs[j].data = data;
1677 vmx->guest_msrs[j] = vmx->host_msrs[j];
1678 ++vmx->nmsrs;
1679 }
1680
1681 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1682
1683 /* 22.2.1, 20.8.1 */
1684 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1685
1686 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1687 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1688
1689
1690 return 0;
1691 }
1692
1693 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1694 {
1695 struct vcpu_vmx *vmx = to_vmx(vcpu);
1696 u64 msr;
1697 int ret;
1698
1699 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1700 ret = -ENOMEM;
1701 goto out;
1702 }
1703
1704 vmx->vcpu.arch.rmode.active = 0;
1705
1706 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1707 kvm_set_cr8(&vmx->vcpu, 0);
1708 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1709 if (vmx->vcpu.vcpu_id == 0)
1710 msr |= MSR_IA32_APICBASE_BSP;
1711 kvm_set_apic_base(&vmx->vcpu, msr);
1712
1713 fx_init(&vmx->vcpu);
1714
1715 /*
1716 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1717 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1718 */
1719 if (vmx->vcpu.vcpu_id == 0) {
1720 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1721 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1722 } else {
1723 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1724 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1725 }
1726 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1727 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1728
1729 seg_setup(VCPU_SREG_DS);
1730 seg_setup(VCPU_SREG_ES);
1731 seg_setup(VCPU_SREG_FS);
1732 seg_setup(VCPU_SREG_GS);
1733 seg_setup(VCPU_SREG_SS);
1734
1735 vmcs_write16(GUEST_TR_SELECTOR, 0);
1736 vmcs_writel(GUEST_TR_BASE, 0);
1737 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1738 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1739
1740 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1741 vmcs_writel(GUEST_LDTR_BASE, 0);
1742 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1743 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1744
1745 vmcs_write32(GUEST_SYSENTER_CS, 0);
1746 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1747 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1748
1749 vmcs_writel(GUEST_RFLAGS, 0x02);
1750 if (vmx->vcpu.vcpu_id == 0)
1751 vmcs_writel(GUEST_RIP, 0xfff0);
1752 else
1753 vmcs_writel(GUEST_RIP, 0);
1754 vmcs_writel(GUEST_RSP, 0);
1755
1756 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1757 vmcs_writel(GUEST_DR7, 0x400);
1758
1759 vmcs_writel(GUEST_GDTR_BASE, 0);
1760 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1761
1762 vmcs_writel(GUEST_IDTR_BASE, 0);
1763 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1764
1765 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1766 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1767 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1768
1769 guest_write_tsc(0);
1770
1771 /* Special registers */
1772 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1773
1774 setup_msrs(vmx);
1775
1776 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1777
1778 if (cpu_has_vmx_tpr_shadow()) {
1779 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1780 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1781 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1782 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1783 vmcs_write32(TPR_THRESHOLD, 0);
1784 }
1785
1786 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1787 vmcs_write64(APIC_ACCESS_ADDR,
1788 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1789
1790 if (vmx->vpid != 0)
1791 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1792
1793 vmx->vcpu.arch.cr0 = 0x60000010;
1794 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1795 vmx_set_cr4(&vmx->vcpu, 0);
1796 vmx_set_efer(&vmx->vcpu, 0);
1797 vmx_fpu_activate(&vmx->vcpu);
1798 update_exception_bitmap(&vmx->vcpu);
1799
1800 vpid_sync_vcpu_all(vmx);
1801
1802 return 0;
1803
1804 out:
1805 return ret;
1806 }
1807
1808 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1809 {
1810 struct vcpu_vmx *vmx = to_vmx(vcpu);
1811
1812 if (vcpu->arch.rmode.active) {
1813 vmx->rmode.irq.pending = true;
1814 vmx->rmode.irq.vector = irq;
1815 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1816 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1817 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1818 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1819 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1820 return;
1821 }
1822 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1823 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1824 }
1825
1826 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1827 {
1828 int word_index = __ffs(vcpu->arch.irq_summary);
1829 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1830 int irq = word_index * BITS_PER_LONG + bit_index;
1831
1832 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1833 if (!vcpu->arch.irq_pending[word_index])
1834 clear_bit(word_index, &vcpu->arch.irq_summary);
1835 vmx_inject_irq(vcpu, irq);
1836 }
1837
1838
1839 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1840 struct kvm_run *kvm_run)
1841 {
1842 u32 cpu_based_vm_exec_control;
1843
1844 vcpu->arch.interrupt_window_open =
1845 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1846 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1847
1848 if (vcpu->arch.interrupt_window_open &&
1849 vcpu->arch.irq_summary &&
1850 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1851 /*
1852 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1853 */
1854 kvm_do_inject_irq(vcpu);
1855
1856 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1857 if (!vcpu->arch.interrupt_window_open &&
1858 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1859 /*
1860 * Interrupts blocked. Wait for unblock.
1861 */
1862 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1863 else
1864 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1865 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1866 }
1867
1868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1869 {
1870 int ret;
1871 struct kvm_userspace_memory_region tss_mem = {
1872 .slot = 8,
1873 .guest_phys_addr = addr,
1874 .memory_size = PAGE_SIZE * 3,
1875 .flags = 0,
1876 };
1877
1878 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1879 if (ret)
1880 return ret;
1881 kvm->arch.tss_addr = addr;
1882 return 0;
1883 }
1884
1885 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1886 {
1887 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1888
1889 set_debugreg(dbg->bp[0], 0);
1890 set_debugreg(dbg->bp[1], 1);
1891 set_debugreg(dbg->bp[2], 2);
1892 set_debugreg(dbg->bp[3], 3);
1893
1894 if (dbg->singlestep) {
1895 unsigned long flags;
1896
1897 flags = vmcs_readl(GUEST_RFLAGS);
1898 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1899 vmcs_writel(GUEST_RFLAGS, flags);
1900 }
1901 }
1902
1903 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1904 int vec, u32 err_code)
1905 {
1906 if (!vcpu->arch.rmode.active)
1907 return 0;
1908
1909 /*
1910 * Instruction with address size override prefix opcode 0x67
1911 * Cause the #SS fault with 0 error code in VM86 mode.
1912 */
1913 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1914 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1915 return 1;
1916 return 0;
1917 }
1918
1919 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1920 {
1921 struct vcpu_vmx *vmx = to_vmx(vcpu);
1922 u32 intr_info, error_code;
1923 unsigned long cr2, rip;
1924 u32 vect_info;
1925 enum emulation_result er;
1926
1927 vect_info = vmx->idt_vectoring_info;
1928 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1929
1930 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1931 !is_page_fault(intr_info))
1932 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1933 "intr info 0x%x\n", __func__, vect_info, intr_info);
1934
1935 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1936 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1937 set_bit(irq, vcpu->arch.irq_pending);
1938 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1939 }
1940
1941 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1942 return 1; /* already handled by vmx_vcpu_run() */
1943
1944 if (is_no_device(intr_info)) {
1945 vmx_fpu_activate(vcpu);
1946 return 1;
1947 }
1948
1949 if (is_invalid_opcode(intr_info)) {
1950 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1951 if (er != EMULATE_DONE)
1952 kvm_queue_exception(vcpu, UD_VECTOR);
1953 return 1;
1954 }
1955
1956 error_code = 0;
1957 rip = vmcs_readl(GUEST_RIP);
1958 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
1959 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1960 if (is_page_fault(intr_info)) {
1961 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1962 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1963 }
1964
1965 if (vcpu->arch.rmode.active &&
1966 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1967 error_code)) {
1968 if (vcpu->arch.halt_request) {
1969 vcpu->arch.halt_request = 0;
1970 return kvm_emulate_halt(vcpu);
1971 }
1972 return 1;
1973 }
1974
1975 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1976 (INTR_TYPE_EXCEPTION | 1)) {
1977 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1978 return 0;
1979 }
1980 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1981 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1982 kvm_run->ex.error_code = error_code;
1983 return 0;
1984 }
1985
1986 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1987 struct kvm_run *kvm_run)
1988 {
1989 ++vcpu->stat.irq_exits;
1990 return 1;
1991 }
1992
1993 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1994 {
1995 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1996 return 0;
1997 }
1998
1999 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2000 {
2001 unsigned long exit_qualification;
2002 int size, down, in, string, rep;
2003 unsigned port;
2004
2005 ++vcpu->stat.io_exits;
2006 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2007 string = (exit_qualification & 16) != 0;
2008
2009 if (string) {
2010 if (emulate_instruction(vcpu,
2011 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2012 return 0;
2013 return 1;
2014 }
2015
2016 size = (exit_qualification & 7) + 1;
2017 in = (exit_qualification & 8) != 0;
2018 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2019 rep = (exit_qualification & 32) != 0;
2020 port = exit_qualification >> 16;
2021
2022 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2023 }
2024
2025 static void
2026 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2027 {
2028 /*
2029 * Patch in the VMCALL instruction:
2030 */
2031 hypercall[0] = 0x0f;
2032 hypercall[1] = 0x01;
2033 hypercall[2] = 0xc1;
2034 }
2035
2036 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2037 {
2038 unsigned long exit_qualification;
2039 int cr;
2040 int reg;
2041
2042 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2043 cr = exit_qualification & 15;
2044 reg = (exit_qualification >> 8) & 15;
2045 switch ((exit_qualification >> 4) & 3) {
2046 case 0: /* mov to cr */
2047 switch (cr) {
2048 case 0:
2049 vcpu_load_rsp_rip(vcpu);
2050 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2051 skip_emulated_instruction(vcpu);
2052 return 1;
2053 case 3:
2054 vcpu_load_rsp_rip(vcpu);
2055 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2056 skip_emulated_instruction(vcpu);
2057 return 1;
2058 case 4:
2059 vcpu_load_rsp_rip(vcpu);
2060 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2061 skip_emulated_instruction(vcpu);
2062 return 1;
2063 case 8:
2064 vcpu_load_rsp_rip(vcpu);
2065 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2066 skip_emulated_instruction(vcpu);
2067 if (irqchip_in_kernel(vcpu->kvm))
2068 return 1;
2069 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2070 return 0;
2071 };
2072 break;
2073 case 2: /* clts */
2074 vcpu_load_rsp_rip(vcpu);
2075 vmx_fpu_deactivate(vcpu);
2076 vcpu->arch.cr0 &= ~X86_CR0_TS;
2077 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2078 vmx_fpu_activate(vcpu);
2079 skip_emulated_instruction(vcpu);
2080 return 1;
2081 case 1: /*mov from cr*/
2082 switch (cr) {
2083 case 3:
2084 vcpu_load_rsp_rip(vcpu);
2085 vcpu->arch.regs[reg] = vcpu->arch.cr3;
2086 vcpu_put_rsp_rip(vcpu);
2087 skip_emulated_instruction(vcpu);
2088 return 1;
2089 case 8:
2090 vcpu_load_rsp_rip(vcpu);
2091 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2092 vcpu_put_rsp_rip(vcpu);
2093 skip_emulated_instruction(vcpu);
2094 return 1;
2095 }
2096 break;
2097 case 3: /* lmsw */
2098 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2099
2100 skip_emulated_instruction(vcpu);
2101 return 1;
2102 default:
2103 break;
2104 }
2105 kvm_run->exit_reason = 0;
2106 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2107 (int)(exit_qualification >> 4) & 3, cr);
2108 return 0;
2109 }
2110
2111 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2112 {
2113 unsigned long exit_qualification;
2114 unsigned long val;
2115 int dr, reg;
2116
2117 /*
2118 * FIXME: this code assumes the host is debugging the guest.
2119 * need to deal with guest debugging itself too.
2120 */
2121 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2122 dr = exit_qualification & 7;
2123 reg = (exit_qualification >> 8) & 15;
2124 vcpu_load_rsp_rip(vcpu);
2125 if (exit_qualification & 16) {
2126 /* mov from dr */
2127 switch (dr) {
2128 case 6:
2129 val = 0xffff0ff0;
2130 break;
2131 case 7:
2132 val = 0x400;
2133 break;
2134 default:
2135 val = 0;
2136 }
2137 vcpu->arch.regs[reg] = val;
2138 } else {
2139 /* mov to dr */
2140 }
2141 vcpu_put_rsp_rip(vcpu);
2142 skip_emulated_instruction(vcpu);
2143 return 1;
2144 }
2145
2146 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2147 {
2148 kvm_emulate_cpuid(vcpu);
2149 return 1;
2150 }
2151
2152 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2153 {
2154 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2155 u64 data;
2156
2157 if (vmx_get_msr(vcpu, ecx, &data)) {
2158 kvm_inject_gp(vcpu, 0);
2159 return 1;
2160 }
2161
2162 /* FIXME: handling of bits 32:63 of rax, rdx */
2163 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2164 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2165 skip_emulated_instruction(vcpu);
2166 return 1;
2167 }
2168
2169 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2170 {
2171 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2172 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2173 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2174
2175 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2176 kvm_inject_gp(vcpu, 0);
2177 return 1;
2178 }
2179
2180 skip_emulated_instruction(vcpu);
2181 return 1;
2182 }
2183
2184 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2185 struct kvm_run *kvm_run)
2186 {
2187 return 1;
2188 }
2189
2190 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2191 struct kvm_run *kvm_run)
2192 {
2193 u32 cpu_based_vm_exec_control;
2194
2195 /* clear pending irq */
2196 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2197 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2199 /*
2200 * If the user space waits to inject interrupts, exit as soon as
2201 * possible
2202 */
2203 if (kvm_run->request_interrupt_window &&
2204 !vcpu->arch.irq_summary) {
2205 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2206 ++vcpu->stat.irq_window_exits;
2207 return 0;
2208 }
2209 return 1;
2210 }
2211
2212 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2213 {
2214 skip_emulated_instruction(vcpu);
2215 return kvm_emulate_halt(vcpu);
2216 }
2217
2218 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2219 {
2220 skip_emulated_instruction(vcpu);
2221 kvm_emulate_hypercall(vcpu);
2222 return 1;
2223 }
2224
2225 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2226 {
2227 skip_emulated_instruction(vcpu);
2228 /* TODO: Add support for VT-d/pass-through device */
2229 return 1;
2230 }
2231
2232 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2233 {
2234 u64 exit_qualification;
2235 enum emulation_result er;
2236 unsigned long offset;
2237
2238 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2239 offset = exit_qualification & 0xffful;
2240
2241 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2242
2243 if (er != EMULATE_DONE) {
2244 printk(KERN_ERR
2245 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2246 offset);
2247 return -ENOTSUPP;
2248 }
2249 return 1;
2250 }
2251
2252 /*
2253 * The exit handlers return 1 if the exit was handled fully and guest execution
2254 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2255 * to be done to userspace and return 0.
2256 */
2257 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2258 struct kvm_run *kvm_run) = {
2259 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2260 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2261 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2262 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2263 [EXIT_REASON_CR_ACCESS] = handle_cr,
2264 [EXIT_REASON_DR_ACCESS] = handle_dr,
2265 [EXIT_REASON_CPUID] = handle_cpuid,
2266 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2267 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2268 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2269 [EXIT_REASON_HLT] = handle_halt,
2270 [EXIT_REASON_VMCALL] = handle_vmcall,
2271 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2272 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2273 [EXIT_REASON_WBINVD] = handle_wbinvd,
2274 };
2275
2276 static const int kvm_vmx_max_exit_handlers =
2277 ARRAY_SIZE(kvm_vmx_exit_handlers);
2278
2279 /*
2280 * The guest has exited. See if we can fix it or if we need userspace
2281 * assistance.
2282 */
2283 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2284 {
2285 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2286 struct vcpu_vmx *vmx = to_vmx(vcpu);
2287 u32 vectoring_info = vmx->idt_vectoring_info;
2288
2289 if (unlikely(vmx->fail)) {
2290 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2291 kvm_run->fail_entry.hardware_entry_failure_reason
2292 = vmcs_read32(VM_INSTRUCTION_ERROR);
2293 return 0;
2294 }
2295
2296 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2297 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2298 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2299 "exit reason is 0x%x\n", __func__, exit_reason);
2300 if (exit_reason < kvm_vmx_max_exit_handlers
2301 && kvm_vmx_exit_handlers[exit_reason])
2302 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2303 else {
2304 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2305 kvm_run->hw.hardware_exit_reason = exit_reason;
2306 }
2307 return 0;
2308 }
2309
2310 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2311 {
2312 int max_irr, tpr;
2313
2314 if (!vm_need_tpr_shadow(vcpu->kvm))
2315 return;
2316
2317 if (!kvm_lapic_enabled(vcpu) ||
2318 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2319 vmcs_write32(TPR_THRESHOLD, 0);
2320 return;
2321 }
2322
2323 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2324 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2325 }
2326
2327 static void enable_irq_window(struct kvm_vcpu *vcpu)
2328 {
2329 u32 cpu_based_vm_exec_control;
2330
2331 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2332 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2333 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2334 }
2335
2336 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2337 {
2338 struct vcpu_vmx *vmx = to_vmx(vcpu);
2339 u32 idtv_info_field, intr_info_field;
2340 int has_ext_irq, interrupt_window_open;
2341 int vector;
2342
2343 update_tpr_threshold(vcpu);
2344
2345 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2346 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2347 idtv_info_field = vmx->idt_vectoring_info;
2348 if (intr_info_field & INTR_INFO_VALID_MASK) {
2349 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2350 /* TODO: fault when IDT_Vectoring */
2351 if (printk_ratelimit())
2352 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2353 }
2354 if (has_ext_irq)
2355 enable_irq_window(vcpu);
2356 return;
2357 }
2358 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2359 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2360 == INTR_TYPE_EXT_INTR
2361 && vcpu->arch.rmode.active) {
2362 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2363
2364 vmx_inject_irq(vcpu, vect);
2365 if (unlikely(has_ext_irq))
2366 enable_irq_window(vcpu);
2367 return;
2368 }
2369
2370 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2371 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2372 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2373
2374 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2375 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2376 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2377 if (unlikely(has_ext_irq))
2378 enable_irq_window(vcpu);
2379 return;
2380 }
2381 if (!has_ext_irq)
2382 return;
2383 interrupt_window_open =
2384 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2385 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2386 if (interrupt_window_open) {
2387 vector = kvm_cpu_get_interrupt(vcpu);
2388 vmx_inject_irq(vcpu, vector);
2389 kvm_timer_intr_post(vcpu, vector);
2390 } else
2391 enable_irq_window(vcpu);
2392 }
2393
2394 /*
2395 * Failure to inject an interrupt should give us the information
2396 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2397 * when fetching the interrupt redirection bitmap in the real-mode
2398 * tss, this doesn't happen. So we do it ourselves.
2399 */
2400 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2401 {
2402 vmx->rmode.irq.pending = 0;
2403 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2404 return;
2405 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2406 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2407 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2408 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2409 return;
2410 }
2411 vmx->idt_vectoring_info =
2412 VECTORING_INFO_VALID_MASK
2413 | INTR_TYPE_EXT_INTR
2414 | vmx->rmode.irq.vector;
2415 }
2416
2417 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2418 {
2419 struct vcpu_vmx *vmx = to_vmx(vcpu);
2420 u32 intr_info;
2421
2422 /*
2423 * Loading guest fpu may have cleared host cr0.ts
2424 */
2425 vmcs_writel(HOST_CR0, read_cr0());
2426
2427 asm(
2428 /* Store host registers */
2429 #ifdef CONFIG_X86_64
2430 "push %%rdx; push %%rbp;"
2431 "push %%rcx \n\t"
2432 #else
2433 "push %%edx; push %%ebp;"
2434 "push %%ecx \n\t"
2435 #endif
2436 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2437 /* Check if vmlaunch of vmresume is needed */
2438 "cmpl $0, %c[launched](%0) \n\t"
2439 /* Load guest registers. Don't clobber flags. */
2440 #ifdef CONFIG_X86_64
2441 "mov %c[cr2](%0), %%rax \n\t"
2442 "mov %%rax, %%cr2 \n\t"
2443 "mov %c[rax](%0), %%rax \n\t"
2444 "mov %c[rbx](%0), %%rbx \n\t"
2445 "mov %c[rdx](%0), %%rdx \n\t"
2446 "mov %c[rsi](%0), %%rsi \n\t"
2447 "mov %c[rdi](%0), %%rdi \n\t"
2448 "mov %c[rbp](%0), %%rbp \n\t"
2449 "mov %c[r8](%0), %%r8 \n\t"
2450 "mov %c[r9](%0), %%r9 \n\t"
2451 "mov %c[r10](%0), %%r10 \n\t"
2452 "mov %c[r11](%0), %%r11 \n\t"
2453 "mov %c[r12](%0), %%r12 \n\t"
2454 "mov %c[r13](%0), %%r13 \n\t"
2455 "mov %c[r14](%0), %%r14 \n\t"
2456 "mov %c[r15](%0), %%r15 \n\t"
2457 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2458 #else
2459 "mov %c[cr2](%0), %%eax \n\t"
2460 "mov %%eax, %%cr2 \n\t"
2461 "mov %c[rax](%0), %%eax \n\t"
2462 "mov %c[rbx](%0), %%ebx \n\t"
2463 "mov %c[rdx](%0), %%edx \n\t"
2464 "mov %c[rsi](%0), %%esi \n\t"
2465 "mov %c[rdi](%0), %%edi \n\t"
2466 "mov %c[rbp](%0), %%ebp \n\t"
2467 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2468 #endif
2469 /* Enter guest mode */
2470 "jne .Llaunched \n\t"
2471 ASM_VMX_VMLAUNCH "\n\t"
2472 "jmp .Lkvm_vmx_return \n\t"
2473 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2474 ".Lkvm_vmx_return: "
2475 /* Save guest registers, load host registers, keep flags */
2476 #ifdef CONFIG_X86_64
2477 "xchg %0, (%%rsp) \n\t"
2478 "mov %%rax, %c[rax](%0) \n\t"
2479 "mov %%rbx, %c[rbx](%0) \n\t"
2480 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2481 "mov %%rdx, %c[rdx](%0) \n\t"
2482 "mov %%rsi, %c[rsi](%0) \n\t"
2483 "mov %%rdi, %c[rdi](%0) \n\t"
2484 "mov %%rbp, %c[rbp](%0) \n\t"
2485 "mov %%r8, %c[r8](%0) \n\t"
2486 "mov %%r9, %c[r9](%0) \n\t"
2487 "mov %%r10, %c[r10](%0) \n\t"
2488 "mov %%r11, %c[r11](%0) \n\t"
2489 "mov %%r12, %c[r12](%0) \n\t"
2490 "mov %%r13, %c[r13](%0) \n\t"
2491 "mov %%r14, %c[r14](%0) \n\t"
2492 "mov %%r15, %c[r15](%0) \n\t"
2493 "mov %%cr2, %%rax \n\t"
2494 "mov %%rax, %c[cr2](%0) \n\t"
2495
2496 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
2497 #else
2498 "xchg %0, (%%esp) \n\t"
2499 "mov %%eax, %c[rax](%0) \n\t"
2500 "mov %%ebx, %c[rbx](%0) \n\t"
2501 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2502 "mov %%edx, %c[rdx](%0) \n\t"
2503 "mov %%esi, %c[rsi](%0) \n\t"
2504 "mov %%edi, %c[rdi](%0) \n\t"
2505 "mov %%ebp, %c[rbp](%0) \n\t"
2506 "mov %%cr2, %%eax \n\t"
2507 "mov %%eax, %c[cr2](%0) \n\t"
2508
2509 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2510 #endif
2511 "setbe %c[fail](%0) \n\t"
2512 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2513 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2514 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2515 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2516 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2517 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2518 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2519 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2520 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2521 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2522 #ifdef CONFIG_X86_64
2523 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2524 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2525 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2526 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2527 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2528 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2529 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2530 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2531 #endif
2532 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2533 : "cc", "memory"
2534 #ifdef CONFIG_X86_64
2535 , "rbx", "rdi", "rsi"
2536 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2537 #else
2538 , "ebx", "edi", "rsi"
2539 #endif
2540 );
2541
2542 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2543 if (vmx->rmode.irq.pending)
2544 fixup_rmode_irq(vmx);
2545
2546 vcpu->arch.interrupt_window_open =
2547 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2548
2549 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2550 vmx->launched = 1;
2551
2552 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2553
2554 /* We need to handle NMIs before interrupts are enabled */
2555 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2556 asm("int $2");
2557 }
2558
2559 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2560 {
2561 struct vcpu_vmx *vmx = to_vmx(vcpu);
2562
2563 if (vmx->vmcs) {
2564 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2565 free_vmcs(vmx->vmcs);
2566 vmx->vmcs = NULL;
2567 }
2568 }
2569
2570 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2571 {
2572 struct vcpu_vmx *vmx = to_vmx(vcpu);
2573
2574 spin_lock(&vmx_vpid_lock);
2575 if (vmx->vpid != 0)
2576 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2577 spin_unlock(&vmx_vpid_lock);
2578 vmx_free_vmcs(vcpu);
2579 kfree(vmx->host_msrs);
2580 kfree(vmx->guest_msrs);
2581 kvm_vcpu_uninit(vcpu);
2582 kmem_cache_free(kvm_vcpu_cache, vmx);
2583 }
2584
2585 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2586 {
2587 int err;
2588 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2589 int cpu;
2590
2591 if (!vmx)
2592 return ERR_PTR(-ENOMEM);
2593
2594 allocate_vpid(vmx);
2595
2596 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2597 if (err)
2598 goto free_vcpu;
2599
2600 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2601 if (!vmx->guest_msrs) {
2602 err = -ENOMEM;
2603 goto uninit_vcpu;
2604 }
2605
2606 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2607 if (!vmx->host_msrs)
2608 goto free_guest_msrs;
2609
2610 vmx->vmcs = alloc_vmcs();
2611 if (!vmx->vmcs)
2612 goto free_msrs;
2613
2614 vmcs_clear(vmx->vmcs);
2615
2616 cpu = get_cpu();
2617 vmx_vcpu_load(&vmx->vcpu, cpu);
2618 err = vmx_vcpu_setup(vmx);
2619 vmx_vcpu_put(&vmx->vcpu);
2620 put_cpu();
2621 if (err)
2622 goto free_vmcs;
2623 if (vm_need_virtualize_apic_accesses(kvm))
2624 if (alloc_apic_access_page(kvm) != 0)
2625 goto free_vmcs;
2626
2627 return &vmx->vcpu;
2628
2629 free_vmcs:
2630 free_vmcs(vmx->vmcs);
2631 free_msrs:
2632 kfree(vmx->host_msrs);
2633 free_guest_msrs:
2634 kfree(vmx->guest_msrs);
2635 uninit_vcpu:
2636 kvm_vcpu_uninit(&vmx->vcpu);
2637 free_vcpu:
2638 kmem_cache_free(kvm_vcpu_cache, vmx);
2639 return ERR_PTR(err);
2640 }
2641
2642 static void __init vmx_check_processor_compat(void *rtn)
2643 {
2644 struct vmcs_config vmcs_conf;
2645
2646 *(int *)rtn = 0;
2647 if (setup_vmcs_config(&vmcs_conf) < 0)
2648 *(int *)rtn = -EIO;
2649 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2650 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2651 smp_processor_id());
2652 *(int *)rtn = -EIO;
2653 }
2654 }
2655
2656 static struct kvm_x86_ops vmx_x86_ops = {
2657 .cpu_has_kvm_support = cpu_has_kvm_support,
2658 .disabled_by_bios = vmx_disabled_by_bios,
2659 .hardware_setup = hardware_setup,
2660 .hardware_unsetup = hardware_unsetup,
2661 .check_processor_compatibility = vmx_check_processor_compat,
2662 .hardware_enable = hardware_enable,
2663 .hardware_disable = hardware_disable,
2664 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2665
2666 .vcpu_create = vmx_create_vcpu,
2667 .vcpu_free = vmx_free_vcpu,
2668 .vcpu_reset = vmx_vcpu_reset,
2669
2670 .prepare_guest_switch = vmx_save_host_state,
2671 .vcpu_load = vmx_vcpu_load,
2672 .vcpu_put = vmx_vcpu_put,
2673 .vcpu_decache = vmx_vcpu_decache,
2674
2675 .set_guest_debug = set_guest_debug,
2676 .guest_debug_pre = kvm_guest_debug_pre,
2677 .get_msr = vmx_get_msr,
2678 .set_msr = vmx_set_msr,
2679 .get_segment_base = vmx_get_segment_base,
2680 .get_segment = vmx_get_segment,
2681 .set_segment = vmx_set_segment,
2682 .get_cpl = vmx_get_cpl,
2683 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2684 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2685 .set_cr0 = vmx_set_cr0,
2686 .set_cr3 = vmx_set_cr3,
2687 .set_cr4 = vmx_set_cr4,
2688 .set_efer = vmx_set_efer,
2689 .get_idt = vmx_get_idt,
2690 .set_idt = vmx_set_idt,
2691 .get_gdt = vmx_get_gdt,
2692 .set_gdt = vmx_set_gdt,
2693 .cache_regs = vcpu_load_rsp_rip,
2694 .decache_regs = vcpu_put_rsp_rip,
2695 .get_rflags = vmx_get_rflags,
2696 .set_rflags = vmx_set_rflags,
2697
2698 .tlb_flush = vmx_flush_tlb,
2699
2700 .run = vmx_vcpu_run,
2701 .handle_exit = kvm_handle_exit,
2702 .skip_emulated_instruction = skip_emulated_instruction,
2703 .patch_hypercall = vmx_patch_hypercall,
2704 .get_irq = vmx_get_irq,
2705 .set_irq = vmx_inject_irq,
2706 .queue_exception = vmx_queue_exception,
2707 .exception_injected = vmx_exception_injected,
2708 .inject_pending_irq = vmx_intr_assist,
2709 .inject_pending_vectors = do_interrupt_requests,
2710
2711 .set_tss_addr = vmx_set_tss_addr,
2712 };
2713
2714 static int __init vmx_init(void)
2715 {
2716 void *iova;
2717 int r;
2718
2719 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2720 if (!vmx_io_bitmap_a)
2721 return -ENOMEM;
2722
2723 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2724 if (!vmx_io_bitmap_b) {
2725 r = -ENOMEM;
2726 goto out;
2727 }
2728
2729 /*
2730 * Allow direct access to the PC debug port (it is often used for I/O
2731 * delays, but the vmexits simply slow things down).
2732 */
2733 iova = kmap(vmx_io_bitmap_a);
2734 memset(iova, 0xff, PAGE_SIZE);
2735 clear_bit(0x80, iova);
2736 kunmap(vmx_io_bitmap_a);
2737
2738 iova = kmap(vmx_io_bitmap_b);
2739 memset(iova, 0xff, PAGE_SIZE);
2740 kunmap(vmx_io_bitmap_b);
2741
2742 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2743
2744 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2745 if (r)
2746 goto out1;
2747
2748 if (bypass_guest_pf)
2749 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2750
2751 return 0;
2752
2753 out1:
2754 __free_page(vmx_io_bitmap_b);
2755 out:
2756 __free_page(vmx_io_bitmap_a);
2757 return r;
2758 }
2759
2760 static void __exit vmx_exit(void)
2761 {
2762 __free_page(vmx_io_bitmap_b);
2763 __free_page(vmx_io_bitmap_a);
2764
2765 kvm_exit();
2766 }
2767
2768 module_init(vmx_init)
2769 module_exit(vmx_exit)
Linux kernel - Deliverables
This page took 0.127963 seconds and 6 git commands to generate.