2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
131 module_param(ple_gap
, int, S_IRUGO
);
133 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
134 module_param(ple_window
, int, S_IRUGO
);
136 extern const ulong vmx_return
;
138 #define NR_AUTOLOAD_MSRS 8
139 #define VMCS02_POOL_SIZE 1
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
156 struct list_head loaded_vmcss_on_cpu_link
;
159 struct shared_msr_entry
{
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
178 typedef u64 natural_width
;
179 struct __packed vmcs12
{
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
186 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding
[7]; /* room for future expansion */
192 u64 vm_exit_msr_store_addr
;
193 u64 vm_exit_msr_load_addr
;
194 u64 vm_entry_msr_load_addr
;
196 u64 virtual_apic_page_addr
;
197 u64 apic_access_addr
;
199 u64 guest_physical_address
;
200 u64 vmcs_link_pointer
;
201 u64 guest_ia32_debugctl
;
204 u64 guest_ia32_perf_global_ctrl
;
212 u64 host_ia32_perf_global_ctrl
;
213 u64 padding64
[8]; /* room for future expansion */
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
220 natural_width cr0_guest_host_mask
;
221 natural_width cr4_guest_host_mask
;
222 natural_width cr0_read_shadow
;
223 natural_width cr4_read_shadow
;
224 natural_width cr3_target_value0
;
225 natural_width cr3_target_value1
;
226 natural_width cr3_target_value2
;
227 natural_width cr3_target_value3
;
228 natural_width exit_qualification
;
229 natural_width guest_linear_address
;
230 natural_width guest_cr0
;
231 natural_width guest_cr3
;
232 natural_width guest_cr4
;
233 natural_width guest_es_base
;
234 natural_width guest_cs_base
;
235 natural_width guest_ss_base
;
236 natural_width guest_ds_base
;
237 natural_width guest_fs_base
;
238 natural_width guest_gs_base
;
239 natural_width guest_ldtr_base
;
240 natural_width guest_tr_base
;
241 natural_width guest_gdtr_base
;
242 natural_width guest_idtr_base
;
243 natural_width guest_dr7
;
244 natural_width guest_rsp
;
245 natural_width guest_rip
;
246 natural_width guest_rflags
;
247 natural_width guest_pending_dbg_exceptions
;
248 natural_width guest_sysenter_esp
;
249 natural_width guest_sysenter_eip
;
250 natural_width host_cr0
;
251 natural_width host_cr3
;
252 natural_width host_cr4
;
253 natural_width host_fs_base
;
254 natural_width host_gs_base
;
255 natural_width host_tr_base
;
256 natural_width host_gdtr_base
;
257 natural_width host_idtr_base
;
258 natural_width host_ia32_sysenter_esp
;
259 natural_width host_ia32_sysenter_eip
;
260 natural_width host_rsp
;
261 natural_width host_rip
;
262 natural_width paddingl
[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control
;
264 u32 cpu_based_vm_exec_control
;
265 u32 exception_bitmap
;
266 u32 page_fault_error_code_mask
;
267 u32 page_fault_error_code_match
;
268 u32 cr3_target_count
;
269 u32 vm_exit_controls
;
270 u32 vm_exit_msr_store_count
;
271 u32 vm_exit_msr_load_count
;
272 u32 vm_entry_controls
;
273 u32 vm_entry_msr_load_count
;
274 u32 vm_entry_intr_info_field
;
275 u32 vm_entry_exception_error_code
;
276 u32 vm_entry_instruction_len
;
278 u32 secondary_vm_exec_control
;
279 u32 vm_instruction_error
;
281 u32 vm_exit_intr_info
;
282 u32 vm_exit_intr_error_code
;
283 u32 idt_vectoring_info_field
;
284 u32 idt_vectoring_error_code
;
285 u32 vm_exit_instruction_len
;
286 u32 vmx_instruction_info
;
293 u32 guest_ldtr_limit
;
295 u32 guest_gdtr_limit
;
296 u32 guest_idtr_limit
;
297 u32 guest_es_ar_bytes
;
298 u32 guest_cs_ar_bytes
;
299 u32 guest_ss_ar_bytes
;
300 u32 guest_ds_ar_bytes
;
301 u32 guest_fs_ar_bytes
;
302 u32 guest_gs_ar_bytes
;
303 u32 guest_ldtr_ar_bytes
;
304 u32 guest_tr_ar_bytes
;
305 u32 guest_interruptibility_info
;
306 u32 guest_activity_state
;
307 u32 guest_sysenter_cs
;
308 u32 host_ia32_sysenter_cs
;
309 u32 vmx_preemption_timer_value
;
310 u32 padding32
[7]; /* room for future expansion */
311 u16 virtual_processor_id
;
312 u16 guest_es_selector
;
313 u16 guest_cs_selector
;
314 u16 guest_ss_selector
;
315 u16 guest_ds_selector
;
316 u16 guest_fs_selector
;
317 u16 guest_gs_selector
;
318 u16 guest_ldtr_selector
;
319 u16 guest_tr_selector
;
320 u16 host_es_selector
;
321 u16 host_cs_selector
;
322 u16 host_ss_selector
;
323 u16 host_ds_selector
;
324 u16 host_fs_selector
;
325 u16 host_gs_selector
;
326 u16 host_tr_selector
;
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
334 #define VMCS12_REVISION 0x11e57ed0
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
341 #define VMCS12_SIZE 0x1000
343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
345 struct list_head list
;
347 struct loaded_vmcs vmcs02
;
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
355 /* Has the level1 guest done vmxon? */
358 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 /* The host-usable pointer to the above */
361 struct page
*current_vmcs12_page
;
362 struct vmcs12
*current_vmcs12
;
363 struct vmcs
*current_shadow_vmcs
;
365 * Indicates if the shadow vmcs must be updated with the
366 * data hold by vmcs12
368 bool sync_shadow_vmcs
;
370 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
371 struct list_head vmcs02_pool
;
373 u64 vmcs01_tsc_offset
;
374 /* L2 must run next, and mustn't decide to exit to L1. */
375 bool nested_run_pending
;
377 * Guest pages referred to in vmcs02 with host-physical pointers, so
378 * we must keep them pinned while L2 runs.
380 struct page
*apic_access_page
;
381 u64 msr_ia32_feature_control
;
383 struct hrtimer preemption_timer
;
384 bool preemption_timer_expired
;
387 #define POSTED_INTR_ON 0
388 /* Posted-Interrupt Descriptor */
390 u32 pir
[8]; /* Posted interrupt requested */
391 u32 control
; /* bit 0 of control is outstanding notification bit */
395 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
397 return test_and_set_bit(POSTED_INTR_ON
,
398 (unsigned long *)&pi_desc
->control
);
401 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
403 return test_and_clear_bit(POSTED_INTR_ON
,
404 (unsigned long *)&pi_desc
->control
);
407 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
409 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
413 struct kvm_vcpu vcpu
;
414 unsigned long host_rsp
;
417 bool nmi_known_unmasked
;
419 u32 idt_vectoring_info
;
421 struct shared_msr_entry
*guest_msrs
;
424 unsigned long host_idt_base
;
426 u64 msr_host_kernel_gs_base
;
427 u64 msr_guest_kernel_gs_base
;
429 u32 vm_entry_controls_shadow
;
430 u32 vm_exit_controls_shadow
;
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
436 struct loaded_vmcs vmcs01
;
437 struct loaded_vmcs
*loaded_vmcs
;
438 bool __launched
; /* temporary, used in vmx_vcpu_run */
439 struct msr_autoload
{
441 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
442 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
446 u16 fs_sel
, gs_sel
, ldt_sel
;
450 int gs_ldt_reload_needed
;
451 int fs_reload_needed
;
452 u64 msr_host_bndcfgs
;
457 struct kvm_segment segs
[8];
460 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
461 struct kvm_save_segment
{
469 bool emulation_required
;
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked
;
474 s64 vnmi_blocked_time
;
479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc
;
482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested
;
486 enum segment_cache_field
{
495 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
497 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
506 static const unsigned long shadow_read_only_fields
[] = {
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
521 VM_EXIT_INSTRUCTION_LEN
,
522 IDT_VECTORING_INFO_FIELD
,
523 IDT_VECTORING_ERROR_CODE
,
524 VM_EXIT_INTR_ERROR_CODE
,
526 GUEST_LINEAR_ADDRESS
,
527 GUEST_PHYSICAL_ADDRESS
529 static const int max_shadow_read_only_fields
=
530 ARRAY_SIZE(shadow_read_only_fields
);
532 static const unsigned long shadow_read_write_fields
[] = {
538 GUEST_INTERRUPTIBILITY_INFO
,
551 CPU_BASED_VM_EXEC_CONTROL
,
552 VM_ENTRY_EXCEPTION_ERROR_CODE
,
553 VM_ENTRY_INTR_INFO_FIELD
,
554 VM_ENTRY_INSTRUCTION_LEN
,
555 VM_ENTRY_EXCEPTION_ERROR_CODE
,
561 static const int max_shadow_read_write_fields
=
562 ARRAY_SIZE(shadow_read_write_fields
);
564 static const unsigned short vmcs_field_to_offset_table
[] = {
565 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
566 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
567 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
568 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
569 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
570 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
571 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
572 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
573 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
574 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
575 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
576 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
577 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
578 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
579 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
580 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
581 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
582 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
583 FIELD64(MSR_BITMAP
, msr_bitmap
),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
587 FIELD64(TSC_OFFSET
, tsc_offset
),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
589 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
590 FIELD64(EPT_POINTER
, ept_pointer
),
591 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
592 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
593 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
594 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
595 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
597 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
598 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
599 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
600 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
601 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
602 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
603 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
607 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
610 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
611 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
612 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
614 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
619 FIELD(TPR_THRESHOLD
, tpr_threshold
),
620 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
621 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
622 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
623 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
624 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
625 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
626 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
627 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
628 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
629 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
630 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
631 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
632 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
633 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
634 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
635 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
636 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
637 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
638 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
639 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
640 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
641 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
642 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
643 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
644 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
645 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
646 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
648 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
649 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
650 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
651 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
652 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
653 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
654 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
655 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
656 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
657 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
658 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
659 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
660 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
661 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
662 FIELD(GUEST_CR0
, guest_cr0
),
663 FIELD(GUEST_CR3
, guest_cr3
),
664 FIELD(GUEST_CR4
, guest_cr4
),
665 FIELD(GUEST_ES_BASE
, guest_es_base
),
666 FIELD(GUEST_CS_BASE
, guest_cs_base
),
667 FIELD(GUEST_SS_BASE
, guest_ss_base
),
668 FIELD(GUEST_DS_BASE
, guest_ds_base
),
669 FIELD(GUEST_FS_BASE
, guest_fs_base
),
670 FIELD(GUEST_GS_BASE
, guest_gs_base
),
671 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
672 FIELD(GUEST_TR_BASE
, guest_tr_base
),
673 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
674 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
675 FIELD(GUEST_DR7
, guest_dr7
),
676 FIELD(GUEST_RSP
, guest_rsp
),
677 FIELD(GUEST_RIP
, guest_rip
),
678 FIELD(GUEST_RFLAGS
, guest_rflags
),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
680 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
681 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
682 FIELD(HOST_CR0
, host_cr0
),
683 FIELD(HOST_CR3
, host_cr3
),
684 FIELD(HOST_CR4
, host_cr4
),
685 FIELD(HOST_FS_BASE
, host_fs_base
),
686 FIELD(HOST_GS_BASE
, host_gs_base
),
687 FIELD(HOST_TR_BASE
, host_tr_base
),
688 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
689 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
690 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
691 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
692 FIELD(HOST_RSP
, host_rsp
),
693 FIELD(HOST_RIP
, host_rip
),
695 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
697 static inline short vmcs_field_to_offset(unsigned long field
)
699 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
701 return vmcs_field_to_offset_table
[field
];
704 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
706 return to_vmx(vcpu
)->nested
.current_vmcs12
;
709 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
711 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
712 if (is_error_page(page
))
718 static void nested_release_page(struct page
*page
)
720 kvm_release_page_dirty(page
);
723 static void nested_release_page_clean(struct page
*page
)
725 kvm_release_page_clean(page
);
728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
729 static u64
construct_eptp(unsigned long root_hpa
);
730 static void kvm_cpu_vmxon(u64 addr
);
731 static void kvm_cpu_vmxoff(void);
732 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
733 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
734 struct kvm_segment
*var
, int seg
);
735 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
736 struct kvm_segment
*var
, int seg
);
737 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
738 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
739 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
740 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
741 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
742 static bool vmx_mpx_supported(void);
744 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
745 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
747 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
748 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
750 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
751 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
753 static unsigned long *vmx_io_bitmap_a
;
754 static unsigned long *vmx_io_bitmap_b
;
755 static unsigned long *vmx_msr_bitmap_legacy
;
756 static unsigned long *vmx_msr_bitmap_longmode
;
757 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
758 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
759 static unsigned long *vmx_vmread_bitmap
;
760 static unsigned long *vmx_vmwrite_bitmap
;
762 static bool cpu_has_load_ia32_efer
;
763 static bool cpu_has_load_perf_global_ctrl
;
765 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
766 static DEFINE_SPINLOCK(vmx_vpid_lock
);
768 static struct vmcs_config
{
772 u32 pin_based_exec_ctrl
;
773 u32 cpu_based_exec_ctrl
;
774 u32 cpu_based_2nd_exec_ctrl
;
779 static struct vmx_capability
{
784 #define VMX_SEGMENT_FIELD(seg) \
785 [VCPU_SREG_##seg] = { \
786 .selector = GUEST_##seg##_SELECTOR, \
787 .base = GUEST_##seg##_BASE, \
788 .limit = GUEST_##seg##_LIMIT, \
789 .ar_bytes = GUEST_##seg##_AR_BYTES, \
792 static const struct kvm_vmx_segment_field
{
797 } kvm_vmx_segment_fields
[] = {
798 VMX_SEGMENT_FIELD(CS
),
799 VMX_SEGMENT_FIELD(DS
),
800 VMX_SEGMENT_FIELD(ES
),
801 VMX_SEGMENT_FIELD(FS
),
802 VMX_SEGMENT_FIELD(GS
),
803 VMX_SEGMENT_FIELD(SS
),
804 VMX_SEGMENT_FIELD(TR
),
805 VMX_SEGMENT_FIELD(LDTR
),
808 static u64 host_efer
;
810 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
813 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
814 * away by decrementing the array size.
816 static const u32 vmx_msr_index
[] = {
818 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
820 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
822 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
824 static inline bool is_page_fault(u32 intr_info
)
826 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
827 INTR_INFO_VALID_MASK
)) ==
828 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
831 static inline bool is_no_device(u32 intr_info
)
833 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
834 INTR_INFO_VALID_MASK
)) ==
835 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
838 static inline bool is_invalid_opcode(u32 intr_info
)
840 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
841 INTR_INFO_VALID_MASK
)) ==
842 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
845 static inline bool is_external_interrupt(u32 intr_info
)
847 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
848 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
851 static inline bool is_machine_check(u32 intr_info
)
853 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
854 INTR_INFO_VALID_MASK
)) ==
855 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
858 static inline bool cpu_has_vmx_msr_bitmap(void)
860 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
863 static inline bool cpu_has_vmx_tpr_shadow(void)
865 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
868 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
870 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
873 static inline bool cpu_has_secondary_exec_ctrls(void)
875 return vmcs_config
.cpu_based_exec_ctrl
&
876 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
879 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
881 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
882 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
885 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
887 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
888 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
891 static inline bool cpu_has_vmx_apic_register_virt(void)
893 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
894 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
897 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
899 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
900 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
903 static inline bool cpu_has_vmx_posted_intr(void)
905 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
908 static inline bool cpu_has_vmx_apicv(void)
910 return cpu_has_vmx_apic_register_virt() &&
911 cpu_has_vmx_virtual_intr_delivery() &&
912 cpu_has_vmx_posted_intr();
915 static inline bool cpu_has_vmx_flexpriority(void)
917 return cpu_has_vmx_tpr_shadow() &&
918 cpu_has_vmx_virtualize_apic_accesses();
921 static inline bool cpu_has_vmx_ept_execute_only(void)
923 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
926 static inline bool cpu_has_vmx_eptp_uncacheable(void)
928 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
931 static inline bool cpu_has_vmx_eptp_writeback(void)
933 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
936 static inline bool cpu_has_vmx_ept_2m_page(void)
938 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
941 static inline bool cpu_has_vmx_ept_1g_page(void)
943 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
946 static inline bool cpu_has_vmx_ept_4levels(void)
948 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
951 static inline bool cpu_has_vmx_ept_ad_bits(void)
953 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
956 static inline bool cpu_has_vmx_invept_context(void)
958 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
961 static inline bool cpu_has_vmx_invept_global(void)
963 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
966 static inline bool cpu_has_vmx_invvpid_single(void)
968 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
971 static inline bool cpu_has_vmx_invvpid_global(void)
973 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
976 static inline bool cpu_has_vmx_ept(void)
978 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
979 SECONDARY_EXEC_ENABLE_EPT
;
982 static inline bool cpu_has_vmx_unrestricted_guest(void)
984 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
985 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
988 static inline bool cpu_has_vmx_ple(void)
990 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
991 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
994 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
996 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
999 static inline bool cpu_has_vmx_vpid(void)
1001 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1002 SECONDARY_EXEC_ENABLE_VPID
;
1005 static inline bool cpu_has_vmx_rdtscp(void)
1007 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1008 SECONDARY_EXEC_RDTSCP
;
1011 static inline bool cpu_has_vmx_invpcid(void)
1013 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1014 SECONDARY_EXEC_ENABLE_INVPCID
;
1017 static inline bool cpu_has_virtual_nmis(void)
1019 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1022 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1025 SECONDARY_EXEC_WBINVD_EXITING
;
1028 static inline bool cpu_has_vmx_shadow_vmcs(void)
1031 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1032 /* check if the cpu supports writing r/o exit information fields */
1033 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1036 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1037 SECONDARY_EXEC_SHADOW_VMCS
;
1040 static inline bool report_flexpriority(void)
1042 return flexpriority_enabled
;
1045 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1047 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1050 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1052 return (vmcs12
->cpu_based_vm_exec_control
&
1053 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1054 (vmcs12
->secondary_vm_exec_control
& bit
);
1057 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1059 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1062 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1064 return vmcs12
->pin_based_vm_exec_control
&
1065 PIN_BASED_VMX_PREEMPTION_TIMER
;
1068 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1070 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1073 static inline bool is_exception(u32 intr_info
)
1075 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1076 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1079 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1081 unsigned long exit_qualification
);
1082 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1083 struct vmcs12
*vmcs12
,
1084 u32 reason
, unsigned long qualification
);
1086 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1090 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1091 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1096 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1102 } operand
= { vpid
, 0, gva
};
1104 asm volatile (__ex(ASM_VMX_INVVPID
)
1105 /* CF==1 or ZF==1 --> rc = -1 */
1106 "; ja 1f ; ud2 ; 1:"
1107 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1110 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1114 } operand
= {eptp
, gpa
};
1116 asm volatile (__ex(ASM_VMX_INVEPT
)
1117 /* CF==1 or ZF==1 --> rc = -1 */
1118 "; ja 1f ; ud2 ; 1:\n"
1119 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1122 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1126 i
= __find_msr_index(vmx
, msr
);
1128 return &vmx
->guest_msrs
[i
];
1132 static void vmcs_clear(struct vmcs
*vmcs
)
1134 u64 phys_addr
= __pa(vmcs
);
1137 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1138 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1141 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1145 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1147 vmcs_clear(loaded_vmcs
->vmcs
);
1148 loaded_vmcs
->cpu
= -1;
1149 loaded_vmcs
->launched
= 0;
1152 static void vmcs_load(struct vmcs
*vmcs
)
1154 u64 phys_addr
= __pa(vmcs
);
1157 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1158 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1161 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1167 * This bitmap is used to indicate whether the vmclear
1168 * operation is enabled on all cpus. All disabled by
1171 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1173 static inline void crash_enable_local_vmclear(int cpu
)
1175 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1178 static inline void crash_disable_local_vmclear(int cpu
)
1180 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1183 static inline int crash_local_vmclear_enabled(int cpu
)
1185 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1188 static void crash_vmclear_local_loaded_vmcss(void)
1190 int cpu
= raw_smp_processor_id();
1191 struct loaded_vmcs
*v
;
1193 if (!crash_local_vmclear_enabled(cpu
))
1196 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1197 loaded_vmcss_on_cpu_link
)
1198 vmcs_clear(v
->vmcs
);
1201 static inline void crash_enable_local_vmclear(int cpu
) { }
1202 static inline void crash_disable_local_vmclear(int cpu
) { }
1203 #endif /* CONFIG_KEXEC */
1205 static void __loaded_vmcs_clear(void *arg
)
1207 struct loaded_vmcs
*loaded_vmcs
= arg
;
1208 int cpu
= raw_smp_processor_id();
1210 if (loaded_vmcs
->cpu
!= cpu
)
1211 return; /* vcpu migration can race with cpu offline */
1212 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1213 per_cpu(current_vmcs
, cpu
) = NULL
;
1214 crash_disable_local_vmclear(cpu
);
1215 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1218 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1219 * is before setting loaded_vmcs->vcpu to -1 which is done in
1220 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1221 * then adds the vmcs into percpu list before it is deleted.
1225 loaded_vmcs_init(loaded_vmcs
);
1226 crash_enable_local_vmclear(cpu
);
1229 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1231 int cpu
= loaded_vmcs
->cpu
;
1234 smp_call_function_single(cpu
,
1235 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1238 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1243 if (cpu_has_vmx_invvpid_single())
1244 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1247 static inline void vpid_sync_vcpu_global(void)
1249 if (cpu_has_vmx_invvpid_global())
1250 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1253 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1255 if (cpu_has_vmx_invvpid_single())
1256 vpid_sync_vcpu_single(vmx
);
1258 vpid_sync_vcpu_global();
1261 static inline void ept_sync_global(void)
1263 if (cpu_has_vmx_invept_global())
1264 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1267 static inline void ept_sync_context(u64 eptp
)
1270 if (cpu_has_vmx_invept_context())
1271 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1277 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1279 unsigned long value
;
1281 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1282 : "=a"(value
) : "d"(field
) : "cc");
1286 static __always_inline u16
vmcs_read16(unsigned long field
)
1288 return vmcs_readl(field
);
1291 static __always_inline u32
vmcs_read32(unsigned long field
)
1293 return vmcs_readl(field
);
1296 static __always_inline u64
vmcs_read64(unsigned long field
)
1298 #ifdef CONFIG_X86_64
1299 return vmcs_readl(field
);
1301 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1305 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1307 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1308 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1312 static void vmcs_writel(unsigned long field
, unsigned long value
)
1316 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1317 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1318 if (unlikely(error
))
1319 vmwrite_error(field
, value
);
1322 static void vmcs_write16(unsigned long field
, u16 value
)
1324 vmcs_writel(field
, value
);
1327 static void vmcs_write32(unsigned long field
, u32 value
)
1329 vmcs_writel(field
, value
);
1332 static void vmcs_write64(unsigned long field
, u64 value
)
1334 vmcs_writel(field
, value
);
1335 #ifndef CONFIG_X86_64
1337 vmcs_writel(field
+1, value
>> 32);
1341 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1343 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1346 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1348 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1351 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1353 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1354 vmx
->vm_entry_controls_shadow
= val
;
1357 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1359 if (vmx
->vm_entry_controls_shadow
!= val
)
1360 vm_entry_controls_init(vmx
, val
);
1363 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1365 return vmx
->vm_entry_controls_shadow
;
1369 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1371 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1374 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1376 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1379 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1381 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1382 vmx
->vm_exit_controls_shadow
= val
;
1385 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1387 if (vmx
->vm_exit_controls_shadow
!= val
)
1388 vm_exit_controls_init(vmx
, val
);
1391 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1393 return vmx
->vm_exit_controls_shadow
;
1397 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1399 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1402 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1404 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1407 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1409 vmx
->segment_cache
.bitmask
= 0;
1412 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1416 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1418 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1419 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1420 vmx
->segment_cache
.bitmask
= 0;
1422 ret
= vmx
->segment_cache
.bitmask
& mask
;
1423 vmx
->segment_cache
.bitmask
|= mask
;
1427 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1429 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1431 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1432 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1436 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1438 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1440 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1441 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1445 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1447 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1449 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1450 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1454 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1456 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1458 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1459 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1463 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1467 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1468 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1469 if ((vcpu
->guest_debug
&
1470 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1471 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1472 eb
|= 1u << BP_VECTOR
;
1473 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1476 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1477 if (vcpu
->fpu_active
)
1478 eb
&= ~(1u << NM_VECTOR
);
1480 /* When we are running a nested L2 guest and L1 specified for it a
1481 * certain exception bitmap, we must trap the same exceptions and pass
1482 * them to L1. When running L2, we will only handle the exceptions
1483 * specified above if L1 did not want them.
1485 if (is_guest_mode(vcpu
))
1486 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1488 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1491 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1492 unsigned long entry
, unsigned long exit
)
1494 vm_entry_controls_clearbit(vmx
, entry
);
1495 vm_exit_controls_clearbit(vmx
, exit
);
1498 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1501 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1505 if (cpu_has_load_ia32_efer
) {
1506 clear_atomic_switch_msr_special(vmx
,
1507 VM_ENTRY_LOAD_IA32_EFER
,
1508 VM_EXIT_LOAD_IA32_EFER
);
1512 case MSR_CORE_PERF_GLOBAL_CTRL
:
1513 if (cpu_has_load_perf_global_ctrl
) {
1514 clear_atomic_switch_msr_special(vmx
,
1515 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1516 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1522 for (i
= 0; i
< m
->nr
; ++i
)
1523 if (m
->guest
[i
].index
== msr
)
1529 m
->guest
[i
] = m
->guest
[m
->nr
];
1530 m
->host
[i
] = m
->host
[m
->nr
];
1531 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1532 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1535 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1536 unsigned long entry
, unsigned long exit
,
1537 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1538 u64 guest_val
, u64 host_val
)
1540 vmcs_write64(guest_val_vmcs
, guest_val
);
1541 vmcs_write64(host_val_vmcs
, host_val
);
1542 vm_entry_controls_setbit(vmx
, entry
);
1543 vm_exit_controls_setbit(vmx
, exit
);
1546 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1547 u64 guest_val
, u64 host_val
)
1550 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1554 if (cpu_has_load_ia32_efer
) {
1555 add_atomic_switch_msr_special(vmx
,
1556 VM_ENTRY_LOAD_IA32_EFER
,
1557 VM_EXIT_LOAD_IA32_EFER
,
1560 guest_val
, host_val
);
1564 case MSR_CORE_PERF_GLOBAL_CTRL
:
1565 if (cpu_has_load_perf_global_ctrl
) {
1566 add_atomic_switch_msr_special(vmx
,
1567 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1568 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1569 GUEST_IA32_PERF_GLOBAL_CTRL
,
1570 HOST_IA32_PERF_GLOBAL_CTRL
,
1571 guest_val
, host_val
);
1577 for (i
= 0; i
< m
->nr
; ++i
)
1578 if (m
->guest
[i
].index
== msr
)
1581 if (i
== NR_AUTOLOAD_MSRS
) {
1582 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1583 "Can't add msr %x\n", msr
);
1585 } else if (i
== m
->nr
) {
1587 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1588 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1591 m
->guest
[i
].index
= msr
;
1592 m
->guest
[i
].value
= guest_val
;
1593 m
->host
[i
].index
= msr
;
1594 m
->host
[i
].value
= host_val
;
1597 static void reload_tss(void)
1600 * VT restores TR but not its size. Useless.
1602 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1603 struct desc_struct
*descs
;
1605 descs
= (void *)gdt
->address
;
1606 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1610 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1615 guest_efer
= vmx
->vcpu
.arch
.efer
;
1618 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1621 ignore_bits
= EFER_NX
| EFER_SCE
;
1622 #ifdef CONFIG_X86_64
1623 ignore_bits
|= EFER_LMA
| EFER_LME
;
1624 /* SCE is meaningful only in long mode on Intel */
1625 if (guest_efer
& EFER_LMA
)
1626 ignore_bits
&= ~(u64
)EFER_SCE
;
1628 guest_efer
&= ~ignore_bits
;
1629 guest_efer
|= host_efer
& ignore_bits
;
1630 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1631 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1633 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1634 /* On ept, can't emulate nx, and must switch nx atomically */
1635 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1636 guest_efer
= vmx
->vcpu
.arch
.efer
;
1637 if (!(guest_efer
& EFER_LMA
))
1638 guest_efer
&= ~EFER_LME
;
1639 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1646 static unsigned long segment_base(u16 selector
)
1648 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1649 struct desc_struct
*d
;
1650 unsigned long table_base
;
1653 if (!(selector
& ~3))
1656 table_base
= gdt
->address
;
1658 if (selector
& 4) { /* from ldt */
1659 u16 ldt_selector
= kvm_read_ldt();
1661 if (!(ldt_selector
& ~3))
1664 table_base
= segment_base(ldt_selector
);
1666 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1667 v
= get_desc_base(d
);
1668 #ifdef CONFIG_X86_64
1669 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1670 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1675 static inline unsigned long kvm_read_tr_base(void)
1678 asm("str %0" : "=g"(tr
));
1679 return segment_base(tr
);
1682 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1687 if (vmx
->host_state
.loaded
)
1690 vmx
->host_state
.loaded
= 1;
1692 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1693 * allow segment selectors with cpl > 0 or ti == 1.
1695 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1696 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1697 savesegment(fs
, vmx
->host_state
.fs_sel
);
1698 if (!(vmx
->host_state
.fs_sel
& 7)) {
1699 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1700 vmx
->host_state
.fs_reload_needed
= 0;
1702 vmcs_write16(HOST_FS_SELECTOR
, 0);
1703 vmx
->host_state
.fs_reload_needed
= 1;
1705 savesegment(gs
, vmx
->host_state
.gs_sel
);
1706 if (!(vmx
->host_state
.gs_sel
& 7))
1707 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1709 vmcs_write16(HOST_GS_SELECTOR
, 0);
1710 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1713 #ifdef CONFIG_X86_64
1714 savesegment(ds
, vmx
->host_state
.ds_sel
);
1715 savesegment(es
, vmx
->host_state
.es_sel
);
1718 #ifdef CONFIG_X86_64
1719 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1720 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1722 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1723 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1726 #ifdef CONFIG_X86_64
1727 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1728 if (is_long_mode(&vmx
->vcpu
))
1729 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1731 if (boot_cpu_has(X86_FEATURE_MPX
))
1732 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1733 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1734 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1735 vmx
->guest_msrs
[i
].data
,
1736 vmx
->guest_msrs
[i
].mask
);
1739 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1741 if (!vmx
->host_state
.loaded
)
1744 ++vmx
->vcpu
.stat
.host_state_reload
;
1745 vmx
->host_state
.loaded
= 0;
1746 #ifdef CONFIG_X86_64
1747 if (is_long_mode(&vmx
->vcpu
))
1748 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1750 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1751 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1752 #ifdef CONFIG_X86_64
1753 load_gs_index(vmx
->host_state
.gs_sel
);
1755 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1758 if (vmx
->host_state
.fs_reload_needed
)
1759 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1760 #ifdef CONFIG_X86_64
1761 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1762 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1763 loadsegment(es
, vmx
->host_state
.es_sel
);
1767 #ifdef CONFIG_X86_64
1768 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1770 if (vmx
->host_state
.msr_host_bndcfgs
)
1771 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1773 * If the FPU is not active (through the host task or
1774 * the guest vcpu), then restore the cr0.TS bit.
1776 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1778 load_gdt(&__get_cpu_var(host_gdt
));
1781 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1784 __vmx_load_host_state(vmx
);
1789 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1790 * vcpu mutex is already taken.
1792 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1794 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1795 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1798 kvm_cpu_vmxon(phys_addr
);
1799 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1800 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1802 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1803 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1804 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1807 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1808 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1809 unsigned long sysenter_esp
;
1811 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1812 local_irq_disable();
1813 crash_disable_local_vmclear(cpu
);
1816 * Read loaded_vmcs->cpu should be before fetching
1817 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1818 * See the comments in __loaded_vmcs_clear().
1822 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1823 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1824 crash_enable_local_vmclear(cpu
);
1828 * Linux uses per-cpu TSS and GDT, so set these when switching
1831 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1832 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1834 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1835 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1836 vmx
->loaded_vmcs
->cpu
= cpu
;
1840 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1842 __vmx_load_host_state(to_vmx(vcpu
));
1843 if (!vmm_exclusive
) {
1844 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1850 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1854 if (vcpu
->fpu_active
)
1856 vcpu
->fpu_active
= 1;
1857 cr0
= vmcs_readl(GUEST_CR0
);
1858 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1859 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1860 vmcs_writel(GUEST_CR0
, cr0
);
1861 update_exception_bitmap(vcpu
);
1862 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1863 if (is_guest_mode(vcpu
))
1864 vcpu
->arch
.cr0_guest_owned_bits
&=
1865 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1866 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1869 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1872 * Return the cr0 value that a nested guest would read. This is a combination
1873 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1874 * its hypervisor (cr0_read_shadow).
1876 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1878 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1879 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1881 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1883 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1884 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1887 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1889 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1890 * set this *before* calling this function.
1892 vmx_decache_cr0_guest_bits(vcpu
);
1893 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1894 update_exception_bitmap(vcpu
);
1895 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1896 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1897 if (is_guest_mode(vcpu
)) {
1899 * L1's specified read shadow might not contain the TS bit,
1900 * so now that we turned on shadowing of this bit, we need to
1901 * set this bit of the shadow. Like in nested_vmx_run we need
1902 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1903 * up-to-date here because we just decached cr0.TS (and we'll
1904 * only update vmcs12->guest_cr0 on nested exit).
1906 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1907 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1908 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1909 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1911 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1914 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1916 unsigned long rflags
, save_rflags
;
1918 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1919 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1920 rflags
= vmcs_readl(GUEST_RFLAGS
);
1921 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1922 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1923 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1924 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1926 to_vmx(vcpu
)->rflags
= rflags
;
1928 return to_vmx(vcpu
)->rflags
;
1931 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1933 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1934 to_vmx(vcpu
)->rflags
= rflags
;
1935 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1936 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1937 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1939 vmcs_writel(GUEST_RFLAGS
, rflags
);
1942 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1944 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1947 if (interruptibility
& GUEST_INTR_STATE_STI
)
1948 ret
|= KVM_X86_SHADOW_INT_STI
;
1949 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1950 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1955 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1957 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1958 u32 interruptibility
= interruptibility_old
;
1960 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1962 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1963 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1964 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1965 interruptibility
|= GUEST_INTR_STATE_STI
;
1967 if ((interruptibility
!= interruptibility_old
))
1968 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1971 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1975 rip
= kvm_rip_read(vcpu
);
1976 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1977 kvm_rip_write(vcpu
, rip
);
1979 /* skipping an emulated instruction also counts */
1980 vmx_set_interrupt_shadow(vcpu
, 0);
1984 * KVM wants to inject page-faults which it got to the guest. This function
1985 * checks whether in a nested guest, we need to inject them to L1 or L2.
1987 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1989 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1991 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1994 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
1995 vmcs_read32(VM_EXIT_INTR_INFO
),
1996 vmcs_readl(EXIT_QUALIFICATION
));
2000 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2001 bool has_error_code
, u32 error_code
,
2004 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2005 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2007 if (!reinject
&& is_guest_mode(vcpu
) &&
2008 nested_vmx_check_exception(vcpu
, nr
))
2011 if (has_error_code
) {
2012 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2013 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2016 if (vmx
->rmode
.vm86_active
) {
2018 if (kvm_exception_is_soft(nr
))
2019 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2020 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2021 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2025 if (kvm_exception_is_soft(nr
)) {
2026 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2027 vmx
->vcpu
.arch
.event_exit_inst_len
);
2028 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2030 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2032 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2035 static bool vmx_rdtscp_supported(void)
2037 return cpu_has_vmx_rdtscp();
2040 static bool vmx_invpcid_supported(void)
2042 return cpu_has_vmx_invpcid() && enable_ept
;
2046 * Swap MSR entry in host/guest MSR entry array.
2048 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2050 struct shared_msr_entry tmp
;
2052 tmp
= vmx
->guest_msrs
[to
];
2053 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2054 vmx
->guest_msrs
[from
] = tmp
;
2057 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2059 unsigned long *msr_bitmap
;
2061 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2062 if (is_long_mode(vcpu
))
2063 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2065 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2067 if (is_long_mode(vcpu
))
2068 msr_bitmap
= vmx_msr_bitmap_longmode
;
2070 msr_bitmap
= vmx_msr_bitmap_legacy
;
2073 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2077 * Set up the vmcs to automatically save and restore system
2078 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2079 * mode, as fiddling with msrs is very expensive.
2081 static void setup_msrs(struct vcpu_vmx
*vmx
)
2083 int save_nmsrs
, index
;
2086 #ifdef CONFIG_X86_64
2087 if (is_long_mode(&vmx
->vcpu
)) {
2088 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2090 move_msr_up(vmx
, index
, save_nmsrs
++);
2091 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2093 move_msr_up(vmx
, index
, save_nmsrs
++);
2094 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2096 move_msr_up(vmx
, index
, save_nmsrs
++);
2097 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2098 if (index
>= 0 && vmx
->rdtscp_enabled
)
2099 move_msr_up(vmx
, index
, save_nmsrs
++);
2101 * MSR_STAR is only needed on long mode guests, and only
2102 * if efer.sce is enabled.
2104 index
= __find_msr_index(vmx
, MSR_STAR
);
2105 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2106 move_msr_up(vmx
, index
, save_nmsrs
++);
2109 index
= __find_msr_index(vmx
, MSR_EFER
);
2110 if (index
>= 0 && update_transition_efer(vmx
, index
))
2111 move_msr_up(vmx
, index
, save_nmsrs
++);
2113 vmx
->save_nmsrs
= save_nmsrs
;
2115 if (cpu_has_vmx_msr_bitmap())
2116 vmx_set_msr_bitmap(&vmx
->vcpu
);
2120 * reads and returns guest's timestamp counter "register"
2121 * guest_tsc = host_tsc + tsc_offset -- 21.3
2123 static u64
guest_read_tsc(void)
2125 u64 host_tsc
, tsc_offset
;
2128 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2129 return host_tsc
+ tsc_offset
;
2133 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2134 * counter, even if a nested guest (L2) is currently running.
2136 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2140 tsc_offset
= is_guest_mode(vcpu
) ?
2141 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2142 vmcs_read64(TSC_OFFSET
);
2143 return host_tsc
+ tsc_offset
;
2147 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2148 * software catchup for faster rates on slower CPUs.
2150 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2155 if (user_tsc_khz
> tsc_khz
) {
2156 vcpu
->arch
.tsc_catchup
= 1;
2157 vcpu
->arch
.tsc_always_catchup
= 1;
2159 WARN(1, "user requested TSC rate below hardware speed\n");
2162 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2164 return vmcs_read64(TSC_OFFSET
);
2168 * writes 'offset' into guest's timestamp counter offset register
2170 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2172 if (is_guest_mode(vcpu
)) {
2174 * We're here if L1 chose not to trap WRMSR to TSC. According
2175 * to the spec, this should set L1's TSC; The offset that L1
2176 * set for L2 remains unchanged, and still needs to be added
2177 * to the newly set TSC to get L2's TSC.
2179 struct vmcs12
*vmcs12
;
2180 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2181 /* recalculate vmcs02.TSC_OFFSET: */
2182 vmcs12
= get_vmcs12(vcpu
);
2183 vmcs_write64(TSC_OFFSET
, offset
+
2184 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2185 vmcs12
->tsc_offset
: 0));
2187 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2188 vmcs_read64(TSC_OFFSET
), offset
);
2189 vmcs_write64(TSC_OFFSET
, offset
);
2193 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2195 u64 offset
= vmcs_read64(TSC_OFFSET
);
2197 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2198 if (is_guest_mode(vcpu
)) {
2199 /* Even when running L2, the adjustment needs to apply to L1 */
2200 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2202 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2203 offset
+ adjustment
);
2206 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2208 return target_tsc
- native_read_tsc();
2211 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2213 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2214 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2218 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2219 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2220 * all guests if the "nested" module option is off, and can also be disabled
2221 * for a single guest by disabling its VMX cpuid bit.
2223 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2225 return nested
&& guest_cpuid_has_vmx(vcpu
);
2229 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2230 * returned for the various VMX controls MSRs when nested VMX is enabled.
2231 * The same values should also be used to verify that vmcs12 control fields are
2232 * valid during nested entry from L1 to L2.
2233 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2234 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2235 * bit in the high half is on if the corresponding bit in the control field
2236 * may be on. See also vmx_control_verify().
2237 * TODO: allow these variables to be modified (downgraded) by module options
2240 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2241 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2242 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2243 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2244 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2245 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2246 static u32 nested_vmx_ept_caps
;
2247 static __init
void nested_vmx_setup_ctls_msrs(void)
2250 * Note that as a general rule, the high half of the MSRs (bits in
2251 * the control fields which may be 1) should be initialized by the
2252 * intersection of the underlying hardware's MSR (i.e., features which
2253 * can be supported) and the list of features we want to expose -
2254 * because they are known to be properly supported in our code.
2255 * Also, usually, the low half of the MSRs (bits which must be 1) can
2256 * be set to 0, meaning that L1 may turn off any of these bits. The
2257 * reason is that if one of these bits is necessary, it will appear
2258 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2259 * fields of vmcs01 and vmcs02, will turn these bits off - and
2260 * nested_vmx_exit_handled() will not pass related exits to L1.
2261 * These rules have exceptions below.
2264 /* pin-based controls */
2265 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2266 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2268 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2269 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2272 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2273 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2274 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2275 PIN_BASED_VMX_PREEMPTION_TIMER
;
2279 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2282 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2283 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2284 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2285 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2286 nested_vmx_exit_ctls_high
&=
2287 #ifdef CONFIG_X86_64
2288 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2290 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2291 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2292 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2293 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2294 if (vmx_mpx_supported())
2295 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2297 /* entry controls */
2298 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2299 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2300 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2301 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2302 nested_vmx_entry_ctls_high
&=
2303 #ifdef CONFIG_X86_64
2304 VM_ENTRY_IA32E_MODE
|
2306 VM_ENTRY_LOAD_IA32_PAT
;
2307 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2308 VM_ENTRY_LOAD_IA32_EFER
);
2309 if (vmx_mpx_supported())
2310 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2312 /* cpu-based controls */
2313 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2314 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2315 nested_vmx_procbased_ctls_low
= 0;
2316 nested_vmx_procbased_ctls_high
&=
2317 CPU_BASED_VIRTUAL_INTR_PENDING
|
2318 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2319 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2320 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2321 CPU_BASED_CR3_STORE_EXITING
|
2322 #ifdef CONFIG_X86_64
2323 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2325 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2326 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2327 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2328 CPU_BASED_PAUSE_EXITING
|
2329 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2331 * We can allow some features even when not supported by the
2332 * hardware. For example, L1 can specify an MSR bitmap - and we
2333 * can use it to avoid exits to L1 - even when L0 runs L2
2334 * without MSR bitmaps.
2336 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2338 /* secondary cpu-based controls */
2339 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2340 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2341 nested_vmx_secondary_ctls_low
= 0;
2342 nested_vmx_secondary_ctls_high
&=
2343 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2344 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2345 SECONDARY_EXEC_WBINVD_EXITING
;
2348 /* nested EPT: emulate EPT also to L1 */
2349 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2350 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2351 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2353 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2355 * Since invept is completely emulated we support both global
2356 * and context invalidation independent of what host cpu
2359 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2360 VMX_EPT_EXTENT_CONTEXT_BIT
;
2362 nested_vmx_ept_caps
= 0;
2364 /* miscellaneous data */
2365 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2366 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2367 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2368 VMX_MISC_ACTIVITY_HLT
;
2369 nested_vmx_misc_high
= 0;
2372 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2375 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377 return ((control
& high
) | low
) == control
;
2380 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2382 return low
| ((u64
)high
<< 32);
2385 /* Returns 0 on success, non-0 otherwise. */
2386 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2388 switch (msr_index
) {
2389 case MSR_IA32_VMX_BASIC
:
2391 * This MSR reports some information about VMX support. We
2392 * should return information about the VMX we emulate for the
2393 * guest, and the VMCS structure we give it - not about the
2394 * VMX support of the underlying hardware.
2396 *pdata
= VMCS12_REVISION
|
2397 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2398 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2400 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2401 case MSR_IA32_VMX_PINBASED_CTLS
:
2402 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2403 nested_vmx_pinbased_ctls_high
);
2405 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2406 case MSR_IA32_VMX_PROCBASED_CTLS
:
2407 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2408 nested_vmx_procbased_ctls_high
);
2410 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2411 case MSR_IA32_VMX_EXIT_CTLS
:
2412 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2413 nested_vmx_exit_ctls_high
);
2415 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2416 case MSR_IA32_VMX_ENTRY_CTLS
:
2417 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2418 nested_vmx_entry_ctls_high
);
2420 case MSR_IA32_VMX_MISC
:
2421 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2422 nested_vmx_misc_high
);
2425 * These MSRs specify bits which the guest must keep fixed (on or off)
2426 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2427 * We picked the standard core2 setting.
2429 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2430 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2431 case MSR_IA32_VMX_CR0_FIXED0
:
2432 *pdata
= VMXON_CR0_ALWAYSON
;
2434 case MSR_IA32_VMX_CR0_FIXED1
:
2437 case MSR_IA32_VMX_CR4_FIXED0
:
2438 *pdata
= VMXON_CR4_ALWAYSON
;
2440 case MSR_IA32_VMX_CR4_FIXED1
:
2443 case MSR_IA32_VMX_VMCS_ENUM
:
2446 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2447 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2448 nested_vmx_secondary_ctls_high
);
2450 case MSR_IA32_VMX_EPT_VPID_CAP
:
2451 /* Currently, no nested vpid support */
2452 *pdata
= nested_vmx_ept_caps
;
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2466 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2469 struct shared_msr_entry
*msr
;
2472 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2476 switch (msr_index
) {
2477 #ifdef CONFIG_X86_64
2479 data
= vmcs_readl(GUEST_FS_BASE
);
2482 data
= vmcs_readl(GUEST_GS_BASE
);
2484 case MSR_KERNEL_GS_BASE
:
2485 vmx_load_host_state(to_vmx(vcpu
));
2486 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2490 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2492 data
= guest_read_tsc();
2494 case MSR_IA32_SYSENTER_CS
:
2495 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2497 case MSR_IA32_SYSENTER_EIP
:
2498 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2500 case MSR_IA32_SYSENTER_ESP
:
2501 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2503 case MSR_IA32_BNDCFGS
:
2504 data
= vmcs_read64(GUEST_BNDCFGS
);
2506 case MSR_IA32_FEATURE_CONTROL
:
2507 if (!nested_vmx_allowed(vcpu
))
2509 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2511 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2512 if (!nested_vmx_allowed(vcpu
))
2514 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2516 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2518 /* Otherwise falls through */
2520 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2525 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2532 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2535 * Writes msr value into into the appropriate "register".
2536 * Returns 0 on success, non-0 otherwise.
2537 * Assumes vcpu_load() was already called.
2539 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2542 struct shared_msr_entry
*msr
;
2544 u32 msr_index
= msr_info
->index
;
2545 u64 data
= msr_info
->data
;
2547 switch (msr_index
) {
2549 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2551 #ifdef CONFIG_X86_64
2553 vmx_segment_cache_clear(vmx
);
2554 vmcs_writel(GUEST_FS_BASE
, data
);
2557 vmx_segment_cache_clear(vmx
);
2558 vmcs_writel(GUEST_GS_BASE
, data
);
2560 case MSR_KERNEL_GS_BASE
:
2561 vmx_load_host_state(vmx
);
2562 vmx
->msr_guest_kernel_gs_base
= data
;
2565 case MSR_IA32_SYSENTER_CS
:
2566 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2568 case MSR_IA32_SYSENTER_EIP
:
2569 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2571 case MSR_IA32_SYSENTER_ESP
:
2572 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2574 case MSR_IA32_BNDCFGS
:
2575 vmcs_write64(GUEST_BNDCFGS
, data
);
2578 kvm_write_tsc(vcpu
, msr_info
);
2580 case MSR_IA32_CR_PAT
:
2581 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2582 vmcs_write64(GUEST_IA32_PAT
, data
);
2583 vcpu
->arch
.pat
= data
;
2586 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2588 case MSR_IA32_TSC_ADJUST
:
2589 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2591 case MSR_IA32_FEATURE_CONTROL
:
2592 if (!nested_vmx_allowed(vcpu
) ||
2593 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2594 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2596 vmx
->nested
.msr_ia32_feature_control
= data
;
2597 if (msr_info
->host_initiated
&& data
== 0)
2598 vmx_leave_nested(vcpu
);
2600 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2601 return 1; /* they are read-only */
2603 if (!vmx
->rdtscp_enabled
)
2605 /* Check reserved bit, higher 32 bits should be zero */
2606 if ((data
>> 32) != 0)
2608 /* Otherwise falls through */
2610 msr
= find_msr_entry(vmx
, msr_index
);
2613 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2615 kvm_set_shared_msr(msr
->index
, msr
->data
,
2621 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2627 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2629 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2632 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2635 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2637 case VCPU_EXREG_PDPTR
:
2639 ept_save_pdptrs(vcpu
);
2646 static __init
int cpu_has_kvm_support(void)
2648 return cpu_has_vmx();
2651 static __init
int vmx_disabled_by_bios(void)
2655 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2656 if (msr
& FEATURE_CONTROL_LOCKED
) {
2657 /* launched w/ TXT and VMX disabled */
2658 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2661 /* launched w/o TXT and VMX only enabled w/ TXT */
2662 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2663 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2664 && !tboot_enabled()) {
2665 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2666 "activate TXT before enabling KVM\n");
2669 /* launched w/o TXT and VMX disabled */
2670 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2671 && !tboot_enabled())
2678 static void kvm_cpu_vmxon(u64 addr
)
2680 asm volatile (ASM_VMX_VMXON_RAX
2681 : : "a"(&addr
), "m"(addr
)
2685 static int hardware_enable(void *garbage
)
2687 int cpu
= raw_smp_processor_id();
2688 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2691 if (read_cr4() & X86_CR4_VMXE
)
2694 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2697 * Now we can enable the vmclear operation in kdump
2698 * since the loaded_vmcss_on_cpu list on this cpu
2699 * has been initialized.
2701 * Though the cpu is not in VMX operation now, there
2702 * is no problem to enable the vmclear operation
2703 * for the loaded_vmcss_on_cpu list is empty!
2705 crash_enable_local_vmclear(cpu
);
2707 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2709 test_bits
= FEATURE_CONTROL_LOCKED
;
2710 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2711 if (tboot_enabled())
2712 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2714 if ((old
& test_bits
) != test_bits
) {
2715 /* enable and lock */
2716 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2718 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2720 if (vmm_exclusive
) {
2721 kvm_cpu_vmxon(phys_addr
);
2725 native_store_gdt(&__get_cpu_var(host_gdt
));
2730 static void vmclear_local_loaded_vmcss(void)
2732 int cpu
= raw_smp_processor_id();
2733 struct loaded_vmcs
*v
, *n
;
2735 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2736 loaded_vmcss_on_cpu_link
)
2737 __loaded_vmcs_clear(v
);
2741 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2744 static void kvm_cpu_vmxoff(void)
2746 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2749 static void hardware_disable(void *garbage
)
2751 if (vmm_exclusive
) {
2752 vmclear_local_loaded_vmcss();
2755 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2758 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2759 u32 msr
, u32
*result
)
2761 u32 vmx_msr_low
, vmx_msr_high
;
2762 u32 ctl
= ctl_min
| ctl_opt
;
2764 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2766 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2767 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2769 /* Ensure minimum (required) set of control bits are supported. */
2777 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2779 u32 vmx_msr_low
, vmx_msr_high
;
2781 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2782 return vmx_msr_high
& ctl
;
2785 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2787 u32 vmx_msr_low
, vmx_msr_high
;
2788 u32 min
, opt
, min2
, opt2
;
2789 u32 _pin_based_exec_control
= 0;
2790 u32 _cpu_based_exec_control
= 0;
2791 u32 _cpu_based_2nd_exec_control
= 0;
2792 u32 _vmexit_control
= 0;
2793 u32 _vmentry_control
= 0;
2795 min
= CPU_BASED_HLT_EXITING
|
2796 #ifdef CONFIG_X86_64
2797 CPU_BASED_CR8_LOAD_EXITING
|
2798 CPU_BASED_CR8_STORE_EXITING
|
2800 CPU_BASED_CR3_LOAD_EXITING
|
2801 CPU_BASED_CR3_STORE_EXITING
|
2802 CPU_BASED_USE_IO_BITMAPS
|
2803 CPU_BASED_MOV_DR_EXITING
|
2804 CPU_BASED_USE_TSC_OFFSETING
|
2805 CPU_BASED_MWAIT_EXITING
|
2806 CPU_BASED_MONITOR_EXITING
|
2807 CPU_BASED_INVLPG_EXITING
|
2808 CPU_BASED_RDPMC_EXITING
;
2810 opt
= CPU_BASED_TPR_SHADOW
|
2811 CPU_BASED_USE_MSR_BITMAPS
|
2812 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2813 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2814 &_cpu_based_exec_control
) < 0)
2816 #ifdef CONFIG_X86_64
2817 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2818 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2819 ~CPU_BASED_CR8_STORE_EXITING
;
2821 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2823 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2824 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2825 SECONDARY_EXEC_WBINVD_EXITING
|
2826 SECONDARY_EXEC_ENABLE_VPID
|
2827 SECONDARY_EXEC_ENABLE_EPT
|
2828 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2829 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2830 SECONDARY_EXEC_RDTSCP
|
2831 SECONDARY_EXEC_ENABLE_INVPCID
|
2832 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2833 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2834 SECONDARY_EXEC_SHADOW_VMCS
;
2835 if (adjust_vmx_controls(min2
, opt2
,
2836 MSR_IA32_VMX_PROCBASED_CTLS2
,
2837 &_cpu_based_2nd_exec_control
) < 0)
2840 #ifndef CONFIG_X86_64
2841 if (!(_cpu_based_2nd_exec_control
&
2842 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2843 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2846 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2847 _cpu_based_2nd_exec_control
&= ~(
2848 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2849 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2850 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2852 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2853 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2855 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2856 CPU_BASED_CR3_STORE_EXITING
|
2857 CPU_BASED_INVLPG_EXITING
);
2858 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2859 vmx_capability
.ept
, vmx_capability
.vpid
);
2862 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2863 #ifdef CONFIG_X86_64
2864 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2866 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2867 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2868 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2869 &_vmexit_control
) < 0)
2872 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2873 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2874 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2875 &_pin_based_exec_control
) < 0)
2878 if (!(_cpu_based_2nd_exec_control
&
2879 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2880 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2881 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2883 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2884 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2885 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2886 &_vmentry_control
) < 0)
2889 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2891 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2892 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2895 #ifdef CONFIG_X86_64
2896 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2897 if (vmx_msr_high
& (1u<<16))
2901 /* Require Write-Back (WB) memory type for VMCS accesses. */
2902 if (((vmx_msr_high
>> 18) & 15) != 6)
2905 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2906 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2907 vmcs_conf
->revision_id
= vmx_msr_low
;
2909 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2910 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2911 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2912 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2913 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2915 cpu_has_load_ia32_efer
=
2916 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2917 VM_ENTRY_LOAD_IA32_EFER
)
2918 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2919 VM_EXIT_LOAD_IA32_EFER
);
2921 cpu_has_load_perf_global_ctrl
=
2922 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2923 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2924 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2925 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2928 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2929 * but due to arrata below it can't be used. Workaround is to use
2930 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2932 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2937 * BC86,AAY89,BD102 (model 44)
2941 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2942 switch (boot_cpu_data
.x86_model
) {
2948 cpu_has_load_perf_global_ctrl
= false;
2949 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2950 "does not work properly. Using workaround\n");
2960 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2962 int node
= cpu_to_node(cpu
);
2966 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2969 vmcs
= page_address(pages
);
2970 memset(vmcs
, 0, vmcs_config
.size
);
2971 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2975 static struct vmcs
*alloc_vmcs(void)
2977 return alloc_vmcs_cpu(raw_smp_processor_id());
2980 static void free_vmcs(struct vmcs
*vmcs
)
2982 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2986 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2988 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2990 if (!loaded_vmcs
->vmcs
)
2992 loaded_vmcs_clear(loaded_vmcs
);
2993 free_vmcs(loaded_vmcs
->vmcs
);
2994 loaded_vmcs
->vmcs
= NULL
;
2997 static void free_kvm_area(void)
3001 for_each_possible_cpu(cpu
) {
3002 free_vmcs(per_cpu(vmxarea
, cpu
));
3003 per_cpu(vmxarea
, cpu
) = NULL
;
3007 static __init
int alloc_kvm_area(void)
3011 for_each_possible_cpu(cpu
) {
3014 vmcs
= alloc_vmcs_cpu(cpu
);
3020 per_cpu(vmxarea
, cpu
) = vmcs
;
3025 static __init
int hardware_setup(void)
3027 if (setup_vmcs_config(&vmcs_config
) < 0)
3030 if (boot_cpu_has(X86_FEATURE_NX
))
3031 kvm_enable_efer_bits(EFER_NX
);
3033 if (!cpu_has_vmx_vpid())
3035 if (!cpu_has_vmx_shadow_vmcs())
3036 enable_shadow_vmcs
= 0;
3038 if (!cpu_has_vmx_ept() ||
3039 !cpu_has_vmx_ept_4levels()) {
3041 enable_unrestricted_guest
= 0;
3042 enable_ept_ad_bits
= 0;
3045 if (!cpu_has_vmx_ept_ad_bits())
3046 enable_ept_ad_bits
= 0;
3048 if (!cpu_has_vmx_unrestricted_guest())
3049 enable_unrestricted_guest
= 0;
3051 if (!cpu_has_vmx_flexpriority())
3052 flexpriority_enabled
= 0;
3054 if (!cpu_has_vmx_tpr_shadow())
3055 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3057 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3058 kvm_disable_largepages();
3060 if (!cpu_has_vmx_ple())
3063 if (!cpu_has_vmx_apicv())
3067 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3069 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3070 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3071 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3075 nested_vmx_setup_ctls_msrs();
3077 return alloc_kvm_area();
3080 static __exit
void hardware_unsetup(void)
3085 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3087 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3090 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3091 struct kvm_segment
*save
)
3093 if (!emulate_invalid_guest_state
) {
3095 * CS and SS RPL should be equal during guest entry according
3096 * to VMX spec, but in reality it is not always so. Since vcpu
3097 * is in the middle of the transition from real mode to
3098 * protected mode it is safe to assume that RPL 0 is a good
3101 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3102 save
->selector
&= ~SELECTOR_RPL_MASK
;
3103 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3106 vmx_set_segment(vcpu
, save
, seg
);
3109 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3111 unsigned long flags
;
3112 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3115 * Update real mode segment cache. It may be not up-to-date if sement
3116 * register was written while vcpu was in a guest mode.
3118 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3119 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3120 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3121 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3122 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3123 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3125 vmx
->rmode
.vm86_active
= 0;
3127 vmx_segment_cache_clear(vmx
);
3129 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3131 flags
= vmcs_readl(GUEST_RFLAGS
);
3132 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3133 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3134 vmcs_writel(GUEST_RFLAGS
, flags
);
3136 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3137 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3139 update_exception_bitmap(vcpu
);
3141 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3142 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3143 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3144 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3145 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3146 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3148 /* CPL is always 0 when CPU enters protected mode */
3149 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3153 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3155 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3156 struct kvm_segment var
= *save
;
3159 if (seg
== VCPU_SREG_CS
)
3162 if (!emulate_invalid_guest_state
) {
3163 var
.selector
= var
.base
>> 4;
3164 var
.base
= var
.base
& 0xffff0;
3174 if (save
->base
& 0xf)
3175 printk_once(KERN_WARNING
"kvm: segment base is not "
3176 "paragraph aligned when entering "
3177 "protected mode (seg=%d)", seg
);
3180 vmcs_write16(sf
->selector
, var
.selector
);
3181 vmcs_write32(sf
->base
, var
.base
);
3182 vmcs_write32(sf
->limit
, var
.limit
);
3183 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3186 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3188 unsigned long flags
;
3189 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3191 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3192 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3193 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3194 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3195 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3196 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3197 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3199 vmx
->rmode
.vm86_active
= 1;
3202 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3203 * vcpu. Warn the user that an update is overdue.
3205 if (!vcpu
->kvm
->arch
.tss_addr
)
3206 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3207 "called before entering vcpu\n");
3209 vmx_segment_cache_clear(vmx
);
3211 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3212 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3213 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3215 flags
= vmcs_readl(GUEST_RFLAGS
);
3216 vmx
->rmode
.save_rflags
= flags
;
3218 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3220 vmcs_writel(GUEST_RFLAGS
, flags
);
3221 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3222 update_exception_bitmap(vcpu
);
3224 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3225 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3226 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3227 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3228 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3229 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3231 kvm_mmu_reset_context(vcpu
);
3234 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3237 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3243 * Force kernel_gs_base reloading before EFER changes, as control
3244 * of this msr depends on is_long_mode().
3246 vmx_load_host_state(to_vmx(vcpu
));
3247 vcpu
->arch
.efer
= efer
;
3248 if (efer
& EFER_LMA
) {
3249 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3252 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3254 msr
->data
= efer
& ~EFER_LME
;
3259 #ifdef CONFIG_X86_64
3261 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3265 vmx_segment_cache_clear(to_vmx(vcpu
));
3267 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3268 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3269 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3271 vmcs_write32(GUEST_TR_AR_BYTES
,
3272 (guest_tr_ar
& ~AR_TYPE_MASK
)
3273 | AR_TYPE_BUSY_64_TSS
);
3275 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3278 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3280 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3281 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3286 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3288 vpid_sync_context(to_vmx(vcpu
));
3290 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3292 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3296 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3298 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3300 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3301 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3304 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3306 if (enable_ept
&& is_paging(vcpu
))
3307 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3308 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3311 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3313 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3315 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3316 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3319 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3321 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3323 if (!test_bit(VCPU_EXREG_PDPTR
,
3324 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3327 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3328 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3329 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3330 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3331 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3335 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3337 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3339 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3340 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3341 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3342 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3343 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3346 __set_bit(VCPU_EXREG_PDPTR
,
3347 (unsigned long *)&vcpu
->arch
.regs_avail
);
3348 __set_bit(VCPU_EXREG_PDPTR
,
3349 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3352 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3354 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3356 struct kvm_vcpu
*vcpu
)
3358 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3359 vmx_decache_cr3(vcpu
);
3360 if (!(cr0
& X86_CR0_PG
)) {
3361 /* From paging/starting to nonpaging */
3362 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3363 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3364 (CPU_BASED_CR3_LOAD_EXITING
|
3365 CPU_BASED_CR3_STORE_EXITING
));
3366 vcpu
->arch
.cr0
= cr0
;
3367 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3368 } else if (!is_paging(vcpu
)) {
3369 /* From nonpaging to paging */
3370 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3371 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3372 ~(CPU_BASED_CR3_LOAD_EXITING
|
3373 CPU_BASED_CR3_STORE_EXITING
));
3374 vcpu
->arch
.cr0
= cr0
;
3375 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3378 if (!(cr0
& X86_CR0_WP
))
3379 *hw_cr0
&= ~X86_CR0_WP
;
3382 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3384 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3385 unsigned long hw_cr0
;
3387 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3388 if (enable_unrestricted_guest
)
3389 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3391 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3393 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3396 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3400 #ifdef CONFIG_X86_64
3401 if (vcpu
->arch
.efer
& EFER_LME
) {
3402 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3404 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3410 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3412 if (!vcpu
->fpu_active
)
3413 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3415 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3416 vmcs_writel(GUEST_CR0
, hw_cr0
);
3417 vcpu
->arch
.cr0
= cr0
;
3419 /* depends on vcpu->arch.cr0 to be set to a new value */
3420 vmx
->emulation_required
= emulation_required(vcpu
);
3423 static u64
construct_eptp(unsigned long root_hpa
)
3427 /* TODO write the value reading from MSR */
3428 eptp
= VMX_EPT_DEFAULT_MT
|
3429 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3430 if (enable_ept_ad_bits
)
3431 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3432 eptp
|= (root_hpa
& PAGE_MASK
);
3437 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3439 unsigned long guest_cr3
;
3444 eptp
= construct_eptp(cr3
);
3445 vmcs_write64(EPT_POINTER
, eptp
);
3446 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3447 guest_cr3
= kvm_read_cr3(vcpu
);
3449 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3450 ept_load_pdptrs(vcpu
);
3453 vmx_flush_tlb(vcpu
);
3454 vmcs_writel(GUEST_CR3
, guest_cr3
);
3457 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3459 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3460 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3462 if (cr4
& X86_CR4_VMXE
) {
3464 * To use VMXON (and later other VMX instructions), a guest
3465 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3466 * So basically the check on whether to allow nested VMX
3469 if (!nested_vmx_allowed(vcpu
))
3472 if (to_vmx(vcpu
)->nested
.vmxon
&&
3473 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3476 vcpu
->arch
.cr4
= cr4
;
3478 if (!is_paging(vcpu
)) {
3479 hw_cr4
&= ~X86_CR4_PAE
;
3480 hw_cr4
|= X86_CR4_PSE
;
3482 * SMEP is disabled if CPU is in non-paging mode in
3483 * hardware. However KVM always uses paging mode to
3484 * emulate guest non-paging mode with TDP.
3485 * To emulate this behavior, SMEP needs to be manually
3486 * disabled when guest switches to non-paging mode.
3488 hw_cr4
&= ~X86_CR4_SMEP
;
3489 } else if (!(cr4
& X86_CR4_PAE
)) {
3490 hw_cr4
&= ~X86_CR4_PAE
;
3494 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3495 vmcs_writel(GUEST_CR4
, hw_cr4
);
3499 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3500 struct kvm_segment
*var
, int seg
)
3502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3505 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3506 *var
= vmx
->rmode
.segs
[seg
];
3507 if (seg
== VCPU_SREG_TR
3508 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3510 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3511 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3514 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3515 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3516 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3517 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3518 var
->unusable
= (ar
>> 16) & 1;
3519 var
->type
= ar
& 15;
3520 var
->s
= (ar
>> 4) & 1;
3521 var
->dpl
= (ar
>> 5) & 3;
3523 * Some userspaces do not preserve unusable property. Since usable
3524 * segment has to be present according to VMX spec we can use present
3525 * property to amend userspace bug by making unusable segment always
3526 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3527 * segment as unusable.
3529 var
->present
= !var
->unusable
;
3530 var
->avl
= (ar
>> 12) & 1;
3531 var
->l
= (ar
>> 13) & 1;
3532 var
->db
= (ar
>> 14) & 1;
3533 var
->g
= (ar
>> 15) & 1;
3536 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3538 struct kvm_segment s
;
3540 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3541 vmx_get_segment(vcpu
, &s
, seg
);
3544 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3547 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3549 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3551 if (!is_protmode(vcpu
))
3554 if (!is_long_mode(vcpu
)
3555 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3558 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3559 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3560 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3567 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3571 if (var
->unusable
|| !var
->present
)
3574 ar
= var
->type
& 15;
3575 ar
|= (var
->s
& 1) << 4;
3576 ar
|= (var
->dpl
& 3) << 5;
3577 ar
|= (var
->present
& 1) << 7;
3578 ar
|= (var
->avl
& 1) << 12;
3579 ar
|= (var
->l
& 1) << 13;
3580 ar
|= (var
->db
& 1) << 14;
3581 ar
|= (var
->g
& 1) << 15;
3587 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3588 struct kvm_segment
*var
, int seg
)
3590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3591 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3593 vmx_segment_cache_clear(vmx
);
3594 if (seg
== VCPU_SREG_CS
)
3595 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3597 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3598 vmx
->rmode
.segs
[seg
] = *var
;
3599 if (seg
== VCPU_SREG_TR
)
3600 vmcs_write16(sf
->selector
, var
->selector
);
3602 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3606 vmcs_writel(sf
->base
, var
->base
);
3607 vmcs_write32(sf
->limit
, var
->limit
);
3608 vmcs_write16(sf
->selector
, var
->selector
);
3611 * Fix the "Accessed" bit in AR field of segment registers for older
3613 * IA32 arch specifies that at the time of processor reset the
3614 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3615 * is setting it to 0 in the userland code. This causes invalid guest
3616 * state vmexit when "unrestricted guest" mode is turned on.
3617 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3618 * tree. Newer qemu binaries with that qemu fix would not need this
3621 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3622 var
->type
|= 0x1; /* Accessed */
3624 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3627 vmx
->emulation_required
|= emulation_required(vcpu
);
3630 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3632 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3634 *db
= (ar
>> 14) & 1;
3635 *l
= (ar
>> 13) & 1;
3638 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3640 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3641 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3644 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3646 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3647 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3650 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3652 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3653 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3656 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3658 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3659 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3662 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3664 struct kvm_segment var
;
3667 vmx_get_segment(vcpu
, &var
, seg
);
3669 if (seg
== VCPU_SREG_CS
)
3671 ar
= vmx_segment_access_rights(&var
);
3673 if (var
.base
!= (var
.selector
<< 4))
3675 if (var
.limit
!= 0xffff)
3683 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3685 struct kvm_segment cs
;
3686 unsigned int cs_rpl
;
3688 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3689 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3693 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3697 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3698 if (cs
.dpl
> cs_rpl
)
3701 if (cs
.dpl
!= cs_rpl
)
3707 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3711 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3713 struct kvm_segment ss
;
3714 unsigned int ss_rpl
;
3716 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3717 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3721 if (ss
.type
!= 3 && ss
.type
!= 7)
3725 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3733 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3735 struct kvm_segment var
;
3738 vmx_get_segment(vcpu
, &var
, seg
);
3739 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3747 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3748 if (var
.dpl
< rpl
) /* DPL < RPL */
3752 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3758 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3760 struct kvm_segment tr
;
3762 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3766 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3768 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3776 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3778 struct kvm_segment ldtr
;
3780 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3784 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3794 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3796 struct kvm_segment cs
, ss
;
3798 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3799 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3801 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3802 (ss
.selector
& SELECTOR_RPL_MASK
));
3806 * Check if guest state is valid. Returns true if valid, false if
3808 * We assume that registers are always usable
3810 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3812 if (enable_unrestricted_guest
)
3815 /* real mode guest state checks */
3816 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3817 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3819 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3821 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3823 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3825 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3827 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3830 /* protected mode guest state checks */
3831 if (!cs_ss_rpl_check(vcpu
))
3833 if (!code_segment_valid(vcpu
))
3835 if (!stack_segment_valid(vcpu
))
3837 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3839 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3841 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3843 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3845 if (!tr_valid(vcpu
))
3847 if (!ldtr_valid(vcpu
))
3851 * - Add checks on RIP
3852 * - Add checks on RFLAGS
3858 static int init_rmode_tss(struct kvm
*kvm
)
3862 int r
, idx
, ret
= 0;
3864 idx
= srcu_read_lock(&kvm
->srcu
);
3865 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3866 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3869 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3870 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3871 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3874 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3877 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3881 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3882 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3889 srcu_read_unlock(&kvm
->srcu
, idx
);
3893 static int init_rmode_identity_map(struct kvm
*kvm
)
3896 pfn_t identity_map_pfn
;
3901 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3902 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3903 "haven't been allocated!\n");
3906 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3909 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3910 idx
= srcu_read_lock(&kvm
->srcu
);
3911 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3914 /* Set up identity-mapping pagetable for EPT in real mode */
3915 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3916 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3917 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3918 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3919 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3923 kvm
->arch
.ept_identity_pagetable_done
= true;
3926 srcu_read_unlock(&kvm
->srcu
, idx
);
3930 static void seg_setup(int seg
)
3932 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3935 vmcs_write16(sf
->selector
, 0);
3936 vmcs_writel(sf
->base
, 0);
3937 vmcs_write32(sf
->limit
, 0xffff);
3939 if (seg
== VCPU_SREG_CS
)
3940 ar
|= 0x08; /* code segment */
3942 vmcs_write32(sf
->ar_bytes
, ar
);
3945 static int alloc_apic_access_page(struct kvm
*kvm
)
3948 struct kvm_userspace_memory_region kvm_userspace_mem
;
3951 mutex_lock(&kvm
->slots_lock
);
3952 if (kvm
->arch
.apic_access_page
)
3954 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3955 kvm_userspace_mem
.flags
= 0;
3956 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3957 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3958 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3962 page
= gfn_to_page(kvm
, 0xfee00);
3963 if (is_error_page(page
)) {
3968 kvm
->arch
.apic_access_page
= page
;
3970 mutex_unlock(&kvm
->slots_lock
);
3974 static int alloc_identity_pagetable(struct kvm
*kvm
)
3977 struct kvm_userspace_memory_region kvm_userspace_mem
;
3980 mutex_lock(&kvm
->slots_lock
);
3981 if (kvm
->arch
.ept_identity_pagetable
)
3983 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3984 kvm_userspace_mem
.flags
= 0;
3985 kvm_userspace_mem
.guest_phys_addr
=
3986 kvm
->arch
.ept_identity_map_addr
;
3987 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3988 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3992 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3993 if (is_error_page(page
)) {
3998 kvm
->arch
.ept_identity_pagetable
= page
;
4000 mutex_unlock(&kvm
->slots_lock
);
4004 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4011 spin_lock(&vmx_vpid_lock
);
4012 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4013 if (vpid
< VMX_NR_VPIDS
) {
4015 __set_bit(vpid
, vmx_vpid_bitmap
);
4017 spin_unlock(&vmx_vpid_lock
);
4020 static void free_vpid(struct vcpu_vmx
*vmx
)
4024 spin_lock(&vmx_vpid_lock
);
4026 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4027 spin_unlock(&vmx_vpid_lock
);
4030 #define MSR_TYPE_R 1
4031 #define MSR_TYPE_W 2
4032 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4035 int f
= sizeof(unsigned long);
4037 if (!cpu_has_vmx_msr_bitmap())
4041 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4042 * have the write-low and read-high bitmap offsets the wrong way round.
4043 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4045 if (msr
<= 0x1fff) {
4046 if (type
& MSR_TYPE_R
)
4048 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4050 if (type
& MSR_TYPE_W
)
4052 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4054 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4056 if (type
& MSR_TYPE_R
)
4058 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4060 if (type
& MSR_TYPE_W
)
4062 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4067 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4070 int f
= sizeof(unsigned long);
4072 if (!cpu_has_vmx_msr_bitmap())
4076 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4077 * have the write-low and read-high bitmap offsets the wrong way round.
4078 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4080 if (msr
<= 0x1fff) {
4081 if (type
& MSR_TYPE_R
)
4083 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4085 if (type
& MSR_TYPE_W
)
4087 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4089 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4091 if (type
& MSR_TYPE_R
)
4093 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4095 if (type
& MSR_TYPE_W
)
4097 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4102 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4105 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4106 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4107 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4108 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4111 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4113 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4115 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4119 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4121 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4123 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4127 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4129 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4131 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4135 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4137 return enable_apicv
&& irqchip_in_kernel(kvm
);
4141 * Send interrupt to vcpu via posted interrupt way.
4142 * 1. If target vcpu is running(non-root mode), send posted interrupt
4143 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4144 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4145 * interrupt from PIR in next vmentry.
4147 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4149 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4152 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4155 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4156 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4158 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4159 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4160 POSTED_INTR_VECTOR
);
4163 kvm_vcpu_kick(vcpu
);
4166 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4168 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4170 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4173 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4176 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4182 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4183 * will not change in the lifetime of the guest.
4184 * Note that host-state that does change is set elsewhere. E.g., host-state
4185 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4187 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4193 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4194 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4195 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4197 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4198 #ifdef CONFIG_X86_64
4200 * Load null selectors, so we can avoid reloading them in
4201 * __vmx_load_host_state(), in case userspace uses the null selectors
4202 * too (the expected case).
4204 vmcs_write16(HOST_DS_SELECTOR
, 0);
4205 vmcs_write16(HOST_ES_SELECTOR
, 0);
4207 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4208 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4210 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4211 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4213 native_store_idt(&dt
);
4214 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4215 vmx
->host_idt_base
= dt
.address
;
4217 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4219 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4220 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4221 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4222 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4224 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4225 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4226 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4230 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4232 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4234 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4235 if (is_guest_mode(&vmx
->vcpu
))
4236 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4237 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4238 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4241 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4243 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4245 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4246 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4247 return pin_based_exec_ctrl
;
4250 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4252 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4254 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4255 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4257 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4258 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4259 #ifdef CONFIG_X86_64
4260 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4261 CPU_BASED_CR8_LOAD_EXITING
;
4265 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4266 CPU_BASED_CR3_LOAD_EXITING
|
4267 CPU_BASED_INVLPG_EXITING
;
4268 return exec_control
;
4271 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4273 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4274 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4275 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4277 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4279 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4280 enable_unrestricted_guest
= 0;
4281 /* Enable INVPCID for non-ept guests may cause performance regression. */
4282 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4284 if (!enable_unrestricted_guest
)
4285 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4287 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4288 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4289 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4290 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4291 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4292 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4294 We can NOT enable shadow_vmcs here because we don't have yet
4297 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4298 return exec_control
;
4301 static void ept_set_mmio_spte_mask(void)
4304 * EPT Misconfigurations can be generated if the value of bits 2:0
4305 * of an EPT paging-structure entry is 110b (write/execute).
4306 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4309 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4313 * Sets up the vmcs for emulated real mode.
4315 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4317 #ifdef CONFIG_X86_64
4323 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4324 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4326 if (enable_shadow_vmcs
) {
4327 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4328 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4330 if (cpu_has_vmx_msr_bitmap())
4331 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4333 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4336 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4338 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4340 if (cpu_has_secondary_exec_ctrls()) {
4341 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4342 vmx_secondary_exec_control(vmx
));
4345 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4346 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4347 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4348 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4349 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4351 vmcs_write16(GUEST_INTR_STATUS
, 0);
4353 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4354 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4358 vmcs_write32(PLE_GAP
, ple_gap
);
4359 vmcs_write32(PLE_WINDOW
, ple_window
);
4362 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4363 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4364 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4366 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4367 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4368 vmx_set_constant_host_state(vmx
);
4369 #ifdef CONFIG_X86_64
4370 rdmsrl(MSR_FS_BASE
, a
);
4371 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4372 rdmsrl(MSR_GS_BASE
, a
);
4373 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4375 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4376 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4379 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4380 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4381 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4382 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4383 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4385 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4386 u32 msr_low
, msr_high
;
4388 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4389 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4390 /* Write the default value follow host pat */
4391 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4392 /* Keep arch.pat sync with GUEST_IA32_PAT */
4393 vmx
->vcpu
.arch
.pat
= host_pat
;
4396 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4397 u32 index
= vmx_msr_index
[i
];
4398 u32 data_low
, data_high
;
4401 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4403 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4405 vmx
->guest_msrs
[j
].index
= i
;
4406 vmx
->guest_msrs
[j
].data
= 0;
4407 vmx
->guest_msrs
[j
].mask
= -1ull;
4412 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4414 /* 22.2.1, 20.8.1 */
4415 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4417 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4418 set_cr4_guest_host_mask(vmx
);
4423 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4426 struct msr_data apic_base_msr
;
4428 vmx
->rmode
.vm86_active
= 0;
4430 vmx
->soft_vnmi_blocked
= 0;
4432 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4433 kvm_set_cr8(&vmx
->vcpu
, 0);
4434 apic_base_msr
.data
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4435 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4436 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4437 apic_base_msr
.host_initiated
= true;
4438 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4440 vmx_segment_cache_clear(vmx
);
4442 seg_setup(VCPU_SREG_CS
);
4443 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4444 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4446 seg_setup(VCPU_SREG_DS
);
4447 seg_setup(VCPU_SREG_ES
);
4448 seg_setup(VCPU_SREG_FS
);
4449 seg_setup(VCPU_SREG_GS
);
4450 seg_setup(VCPU_SREG_SS
);
4452 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4453 vmcs_writel(GUEST_TR_BASE
, 0);
4454 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4455 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4457 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4458 vmcs_writel(GUEST_LDTR_BASE
, 0);
4459 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4460 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4462 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4463 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4464 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4466 vmcs_writel(GUEST_RFLAGS
, 0x02);
4467 kvm_rip_write(vcpu
, 0xfff0);
4469 vmcs_writel(GUEST_GDTR_BASE
, 0);
4470 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4472 vmcs_writel(GUEST_IDTR_BASE
, 0);
4473 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4475 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4476 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4477 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4479 /* Special registers */
4480 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4486 if (cpu_has_vmx_tpr_shadow()) {
4487 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4488 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4489 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4490 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4491 vmcs_write32(TPR_THRESHOLD
, 0);
4494 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4495 vmcs_write64(APIC_ACCESS_ADDR
,
4496 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4498 if (vmx_vm_has_apicv(vcpu
->kvm
))
4499 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4502 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4504 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4505 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4506 vmx_set_cr4(&vmx
->vcpu
, 0);
4507 vmx_set_efer(&vmx
->vcpu
, 0);
4508 vmx_fpu_activate(&vmx
->vcpu
);
4509 update_exception_bitmap(&vmx
->vcpu
);
4511 vpid_sync_context(vmx
);
4515 * In nested virtualization, check if L1 asked to exit on external interrupts.
4516 * For most existing hypervisors, this will always return true.
4518 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4520 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4521 PIN_BASED_EXT_INTR_MASK
;
4524 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4526 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4527 PIN_BASED_NMI_EXITING
;
4530 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4532 u32 cpu_based_vm_exec_control
;
4534 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4535 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4539 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4541 u32 cpu_based_vm_exec_control
;
4543 if (!cpu_has_virtual_nmis() ||
4544 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4545 enable_irq_window(vcpu
);
4549 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4550 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4554 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4556 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4558 int irq
= vcpu
->arch
.interrupt
.nr
;
4560 trace_kvm_inj_virq(irq
);
4562 ++vcpu
->stat
.irq_injections
;
4563 if (vmx
->rmode
.vm86_active
) {
4565 if (vcpu
->arch
.interrupt
.soft
)
4566 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4567 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4568 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4571 intr
= irq
| INTR_INFO_VALID_MASK
;
4572 if (vcpu
->arch
.interrupt
.soft
) {
4573 intr
|= INTR_TYPE_SOFT_INTR
;
4574 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4575 vmx
->vcpu
.arch
.event_exit_inst_len
);
4577 intr
|= INTR_TYPE_EXT_INTR
;
4578 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4581 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4583 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4585 if (is_guest_mode(vcpu
))
4588 if (!cpu_has_virtual_nmis()) {
4590 * Tracking the NMI-blocked state in software is built upon
4591 * finding the next open IRQ window. This, in turn, depends on
4592 * well-behaving guests: They have to keep IRQs disabled at
4593 * least as long as the NMI handler runs. Otherwise we may
4594 * cause NMI nesting, maybe breaking the guest. But as this is
4595 * highly unlikely, we can live with the residual risk.
4597 vmx
->soft_vnmi_blocked
= 1;
4598 vmx
->vnmi_blocked_time
= 0;
4601 ++vcpu
->stat
.nmi_injections
;
4602 vmx
->nmi_known_unmasked
= false;
4603 if (vmx
->rmode
.vm86_active
) {
4604 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4605 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4608 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4609 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4612 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4614 if (!cpu_has_virtual_nmis())
4615 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4616 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4618 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4621 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4623 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4625 if (!cpu_has_virtual_nmis()) {
4626 if (vmx
->soft_vnmi_blocked
!= masked
) {
4627 vmx
->soft_vnmi_blocked
= masked
;
4628 vmx
->vnmi_blocked_time
= 0;
4631 vmx
->nmi_known_unmasked
= !masked
;
4633 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4634 GUEST_INTR_STATE_NMI
);
4636 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4637 GUEST_INTR_STATE_NMI
);
4641 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4643 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4646 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4649 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4650 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4651 | GUEST_INTR_STATE_NMI
));
4654 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4656 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4657 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4658 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4659 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4662 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4665 struct kvm_userspace_memory_region tss_mem
= {
4666 .slot
= TSS_PRIVATE_MEMSLOT
,
4667 .guest_phys_addr
= addr
,
4668 .memory_size
= PAGE_SIZE
* 3,
4672 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4675 kvm
->arch
.tss_addr
= addr
;
4676 if (!init_rmode_tss(kvm
))
4682 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4687 * Update instruction length as we may reinject the exception
4688 * from user space while in guest debugging mode.
4690 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4691 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4692 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4696 if (vcpu
->guest_debug
&
4697 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4714 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4715 int vec
, u32 err_code
)
4718 * Instruction with address size override prefix opcode 0x67
4719 * Cause the #SS fault with 0 error code in VM86 mode.
4721 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4722 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4723 if (vcpu
->arch
.halt_request
) {
4724 vcpu
->arch
.halt_request
= 0;
4725 return kvm_emulate_halt(vcpu
);
4733 * Forward all other exceptions that are valid in real mode.
4734 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4735 * the required debugging infrastructure rework.
4737 kvm_queue_exception(vcpu
, vec
);
4742 * Trigger machine check on the host. We assume all the MSRs are already set up
4743 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4744 * We pass a fake environment to the machine check handler because we want
4745 * the guest to be always treated like user space, no matter what context
4746 * it used internally.
4748 static void kvm_machine_check(void)
4750 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4751 struct pt_regs regs
= {
4752 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4753 .flags
= X86_EFLAGS_IF
,
4756 do_machine_check(®s
, 0);
4760 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4762 /* already handled by vcpu_run */
4766 static int handle_exception(struct kvm_vcpu
*vcpu
)
4768 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4769 struct kvm_run
*kvm_run
= vcpu
->run
;
4770 u32 intr_info
, ex_no
, error_code
;
4771 unsigned long cr2
, rip
, dr6
;
4773 enum emulation_result er
;
4775 vect_info
= vmx
->idt_vectoring_info
;
4776 intr_info
= vmx
->exit_intr_info
;
4778 if (is_machine_check(intr_info
))
4779 return handle_machine_check(vcpu
);
4781 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4782 return 1; /* already handled by vmx_vcpu_run() */
4784 if (is_no_device(intr_info
)) {
4785 vmx_fpu_activate(vcpu
);
4789 if (is_invalid_opcode(intr_info
)) {
4790 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4791 if (er
!= EMULATE_DONE
)
4792 kvm_queue_exception(vcpu
, UD_VECTOR
);
4797 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4798 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4801 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4802 * MMIO, it is better to report an internal error.
4803 * See the comments in vmx_handle_exit.
4805 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4806 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4807 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4808 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4809 vcpu
->run
->internal
.ndata
= 2;
4810 vcpu
->run
->internal
.data
[0] = vect_info
;
4811 vcpu
->run
->internal
.data
[1] = intr_info
;
4815 if (is_page_fault(intr_info
)) {
4816 /* EPT won't cause page fault directly */
4818 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4819 trace_kvm_page_fault(cr2
, error_code
);
4821 if (kvm_event_needs_reinjection(vcpu
))
4822 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4823 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4826 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4828 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4829 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4833 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4834 if (!(vcpu
->guest_debug
&
4835 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4836 vcpu
->arch
.dr6
&= ~15;
4837 vcpu
->arch
.dr6
|= dr6
;
4838 kvm_queue_exception(vcpu
, DB_VECTOR
);
4841 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4842 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4846 * Update instruction length as we may reinject #BP from
4847 * user space while in guest debugging mode. Reading it for
4848 * #DB as well causes no harm, it is not used in that case.
4850 vmx
->vcpu
.arch
.event_exit_inst_len
=
4851 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4852 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4853 rip
= kvm_rip_read(vcpu
);
4854 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4855 kvm_run
->debug
.arch
.exception
= ex_no
;
4858 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4859 kvm_run
->ex
.exception
= ex_no
;
4860 kvm_run
->ex
.error_code
= error_code
;
4866 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4868 ++vcpu
->stat
.irq_exits
;
4872 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4874 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4878 static int handle_io(struct kvm_vcpu
*vcpu
)
4880 unsigned long exit_qualification
;
4881 int size
, in
, string
;
4884 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4885 string
= (exit_qualification
& 16) != 0;
4886 in
= (exit_qualification
& 8) != 0;
4888 ++vcpu
->stat
.io_exits
;
4891 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4893 port
= exit_qualification
>> 16;
4894 size
= (exit_qualification
& 7) + 1;
4895 skip_emulated_instruction(vcpu
);
4897 return kvm_fast_pio_out(vcpu
, size
, port
);
4901 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4904 * Patch in the VMCALL instruction:
4906 hypercall
[0] = 0x0f;
4907 hypercall
[1] = 0x01;
4908 hypercall
[2] = 0xc1;
4911 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4913 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4915 if (nested_vmx_secondary_ctls_high
&
4916 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4917 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4918 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4919 return (val
& always_on
) == always_on
;
4922 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4923 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4925 if (is_guest_mode(vcpu
)) {
4926 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4927 unsigned long orig_val
= val
;
4930 * We get here when L2 changed cr0 in a way that did not change
4931 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4932 * but did change L0 shadowed bits. So we first calculate the
4933 * effective cr0 value that L1 would like to write into the
4934 * hardware. It consists of the L2-owned bits from the new
4935 * value combined with the L1-owned bits from L1's guest_cr0.
4937 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4938 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4940 if (!nested_cr0_valid(vmcs12
, val
))
4943 if (kvm_set_cr0(vcpu
, val
))
4945 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4948 if (to_vmx(vcpu
)->nested
.vmxon
&&
4949 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4951 return kvm_set_cr0(vcpu
, val
);
4955 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4957 if (is_guest_mode(vcpu
)) {
4958 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4959 unsigned long orig_val
= val
;
4961 /* analogously to handle_set_cr0 */
4962 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4963 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4964 if (kvm_set_cr4(vcpu
, val
))
4966 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4969 return kvm_set_cr4(vcpu
, val
);
4972 /* called to set cr0 as approriate for clts instruction exit. */
4973 static void handle_clts(struct kvm_vcpu
*vcpu
)
4975 if (is_guest_mode(vcpu
)) {
4977 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4978 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4979 * just pretend it's off (also in arch.cr0 for fpu_activate).
4981 vmcs_writel(CR0_READ_SHADOW
,
4982 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4983 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4985 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4988 static int handle_cr(struct kvm_vcpu
*vcpu
)
4990 unsigned long exit_qualification
, val
;
4995 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4996 cr
= exit_qualification
& 15;
4997 reg
= (exit_qualification
>> 8) & 15;
4998 switch ((exit_qualification
>> 4) & 3) {
4999 case 0: /* mov to cr */
5000 val
= kvm_register_read(vcpu
, reg
);
5001 trace_kvm_cr_write(cr
, val
);
5004 err
= handle_set_cr0(vcpu
, val
);
5005 kvm_complete_insn_gp(vcpu
, err
);
5008 err
= kvm_set_cr3(vcpu
, val
);
5009 kvm_complete_insn_gp(vcpu
, err
);
5012 err
= handle_set_cr4(vcpu
, val
);
5013 kvm_complete_insn_gp(vcpu
, err
);
5016 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5017 u8 cr8
= kvm_register_read(vcpu
, reg
);
5018 err
= kvm_set_cr8(vcpu
, cr8
);
5019 kvm_complete_insn_gp(vcpu
, err
);
5020 if (irqchip_in_kernel(vcpu
->kvm
))
5022 if (cr8_prev
<= cr8
)
5024 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5031 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5032 skip_emulated_instruction(vcpu
);
5033 vmx_fpu_activate(vcpu
);
5035 case 1: /*mov from cr*/
5038 val
= kvm_read_cr3(vcpu
);
5039 kvm_register_write(vcpu
, reg
, val
);
5040 trace_kvm_cr_read(cr
, val
);
5041 skip_emulated_instruction(vcpu
);
5044 val
= kvm_get_cr8(vcpu
);
5045 kvm_register_write(vcpu
, reg
, val
);
5046 trace_kvm_cr_read(cr
, val
);
5047 skip_emulated_instruction(vcpu
);
5052 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5053 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5054 kvm_lmsw(vcpu
, val
);
5056 skip_emulated_instruction(vcpu
);
5061 vcpu
->run
->exit_reason
= 0;
5062 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5063 (int)(exit_qualification
>> 4) & 3, cr
);
5067 static int handle_dr(struct kvm_vcpu
*vcpu
)
5069 unsigned long exit_qualification
;
5072 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5073 if (!kvm_require_cpl(vcpu
, 0))
5075 dr
= vmcs_readl(GUEST_DR7
);
5078 * As the vm-exit takes precedence over the debug trap, we
5079 * need to emulate the latter, either for the host or the
5080 * guest debugging itself.
5082 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5083 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5084 vcpu
->run
->debug
.arch
.dr7
= dr
;
5085 vcpu
->run
->debug
.arch
.pc
=
5086 vmcs_readl(GUEST_CS_BASE
) +
5087 vmcs_readl(GUEST_RIP
);
5088 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5089 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5092 vcpu
->arch
.dr7
&= ~DR7_GD
;
5093 vcpu
->arch
.dr6
|= DR6_BD
;
5094 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5095 kvm_queue_exception(vcpu
, DB_VECTOR
);
5100 if (vcpu
->guest_debug
== 0) {
5101 u32 cpu_based_vm_exec_control
;
5103 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5104 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5105 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5108 * No more DR vmexits; force a reload of the debug registers
5109 * and reenter on this instruction. The next vmexit will
5110 * retrieve the full state of the debug registers.
5112 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5116 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5117 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5118 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5119 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5122 if (kvm_get_dr(vcpu
, dr
, &val
))
5124 kvm_register_write(vcpu
, reg
, val
);
5126 if (kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]))
5129 skip_emulated_instruction(vcpu
);
5133 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5135 return vcpu
->arch
.dr6
;
5138 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5142 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5144 u32 cpu_based_vm_exec_control
;
5146 get_debugreg(vcpu
->arch
.db
[0], 0);
5147 get_debugreg(vcpu
->arch
.db
[1], 1);
5148 get_debugreg(vcpu
->arch
.db
[2], 2);
5149 get_debugreg(vcpu
->arch
.db
[3], 3);
5150 get_debugreg(vcpu
->arch
.dr6
, 6);
5151 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5153 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5155 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5156 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5157 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5160 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5162 vmcs_writel(GUEST_DR7
, val
);
5165 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5167 kvm_emulate_cpuid(vcpu
);
5171 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5173 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5176 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5177 trace_kvm_msr_read_ex(ecx
);
5178 kvm_inject_gp(vcpu
, 0);
5182 trace_kvm_msr_read(ecx
, data
);
5184 /* FIXME: handling of bits 32:63 of rax, rdx */
5185 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5186 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5187 skip_emulated_instruction(vcpu
);
5191 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5193 struct msr_data msr
;
5194 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5195 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5196 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5200 msr
.host_initiated
= false;
5201 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5202 trace_kvm_msr_write_ex(ecx
, data
);
5203 kvm_inject_gp(vcpu
, 0);
5207 trace_kvm_msr_write(ecx
, data
);
5208 skip_emulated_instruction(vcpu
);
5212 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5214 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5218 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5220 u32 cpu_based_vm_exec_control
;
5222 /* clear pending irq */
5223 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5224 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5225 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5227 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5229 ++vcpu
->stat
.irq_window_exits
;
5232 * If the user space waits to inject interrupts, exit as soon as
5235 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5236 vcpu
->run
->request_interrupt_window
&&
5237 !kvm_cpu_has_interrupt(vcpu
)) {
5238 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5244 static int handle_halt(struct kvm_vcpu
*vcpu
)
5246 skip_emulated_instruction(vcpu
);
5247 return kvm_emulate_halt(vcpu
);
5250 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5252 skip_emulated_instruction(vcpu
);
5253 kvm_emulate_hypercall(vcpu
);
5257 static int handle_invd(struct kvm_vcpu
*vcpu
)
5259 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5262 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5266 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5267 skip_emulated_instruction(vcpu
);
5271 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5275 err
= kvm_rdpmc(vcpu
);
5276 kvm_complete_insn_gp(vcpu
, err
);
5281 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5283 skip_emulated_instruction(vcpu
);
5284 kvm_emulate_wbinvd(vcpu
);
5288 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5290 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5291 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5293 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5294 skip_emulated_instruction(vcpu
);
5298 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5300 if (likely(fasteoi
)) {
5301 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5302 int access_type
, offset
;
5304 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5305 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5307 * Sane guest uses MOV to write EOI, with written value
5308 * not cared. So make a short-circuit here by avoiding
5309 * heavy instruction emulation.
5311 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5312 (offset
== APIC_EOI
)) {
5313 kvm_lapic_set_eoi(vcpu
);
5314 skip_emulated_instruction(vcpu
);
5318 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5321 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5323 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5324 int vector
= exit_qualification
& 0xff;
5326 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5327 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5331 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5333 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5334 u32 offset
= exit_qualification
& 0xfff;
5336 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5337 kvm_apic_write_nodecode(vcpu
, offset
);
5341 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5343 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5344 unsigned long exit_qualification
;
5345 bool has_error_code
= false;
5348 int reason
, type
, idt_v
, idt_index
;
5350 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5351 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5352 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5354 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5356 reason
= (u32
)exit_qualification
>> 30;
5357 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5359 case INTR_TYPE_NMI_INTR
:
5360 vcpu
->arch
.nmi_injected
= false;
5361 vmx_set_nmi_mask(vcpu
, true);
5363 case INTR_TYPE_EXT_INTR
:
5364 case INTR_TYPE_SOFT_INTR
:
5365 kvm_clear_interrupt_queue(vcpu
);
5367 case INTR_TYPE_HARD_EXCEPTION
:
5368 if (vmx
->idt_vectoring_info
&
5369 VECTORING_INFO_DELIVER_CODE_MASK
) {
5370 has_error_code
= true;
5372 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5375 case INTR_TYPE_SOFT_EXCEPTION
:
5376 kvm_clear_exception_queue(vcpu
);
5382 tss_selector
= exit_qualification
;
5384 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5385 type
!= INTR_TYPE_EXT_INTR
&&
5386 type
!= INTR_TYPE_NMI_INTR
))
5387 skip_emulated_instruction(vcpu
);
5389 if (kvm_task_switch(vcpu
, tss_selector
,
5390 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5391 has_error_code
, error_code
) == EMULATE_FAIL
) {
5392 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5393 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5394 vcpu
->run
->internal
.ndata
= 0;
5398 /* clear all local breakpoint enable flags */
5399 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5402 * TODO: What about debug traps on tss switch?
5403 * Are we supposed to inject them and update dr6?
5409 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5411 unsigned long exit_qualification
;
5416 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5418 gla_validity
= (exit_qualification
>> 7) & 0x3;
5419 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5420 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5421 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5422 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5423 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5424 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5425 (long unsigned int)exit_qualification
);
5426 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5427 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5432 * EPT violation happened while executing iret from NMI,
5433 * "blocked by NMI" bit has to be set before next VM entry.
5434 * There are errata that may cause this bit to not be set:
5437 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5438 cpu_has_virtual_nmis() &&
5439 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5440 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5442 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5443 trace_kvm_page_fault(gpa
, exit_qualification
);
5445 /* It is a write fault? */
5446 error_code
= exit_qualification
& (1U << 1);
5447 /* It is a fetch fault? */
5448 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5449 /* ept page table is present? */
5450 error_code
|= (exit_qualification
>> 3) & 0x1;
5452 vcpu
->arch
.exit_qualification
= exit_qualification
;
5454 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5457 static u64
ept_rsvd_mask(u64 spte
, int level
)
5462 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5463 mask
|= (1ULL << i
);
5466 /* bits 7:3 reserved */
5468 else if (level
== 2) {
5469 if (spte
& (1ULL << 7))
5470 /* 2MB ref, bits 20:12 reserved */
5473 /* bits 6:3 reserved */
5480 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5483 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5485 /* 010b (write-only) */
5486 WARN_ON((spte
& 0x7) == 0x2);
5488 /* 110b (write/execute) */
5489 WARN_ON((spte
& 0x7) == 0x6);
5491 /* 100b (execute-only) and value not supported by logical processor */
5492 if (!cpu_has_vmx_ept_execute_only())
5493 WARN_ON((spte
& 0x7) == 0x4);
5497 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5499 if (rsvd_bits
!= 0) {
5500 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5501 __func__
, rsvd_bits
);
5505 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5506 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5508 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5509 ept_mem_type
== 7) {
5510 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5511 __func__
, ept_mem_type
);
5518 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5521 int nr_sptes
, i
, ret
;
5524 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5526 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5527 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5528 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5531 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5532 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5534 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5537 /* It is the real ept misconfig */
5538 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5539 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5541 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5543 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5544 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5546 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5547 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5552 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5554 u32 cpu_based_vm_exec_control
;
5556 /* clear pending NMI */
5557 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5558 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5559 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5560 ++vcpu
->stat
.nmi_window_exits
;
5561 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5566 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5568 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5569 enum emulation_result err
= EMULATE_DONE
;
5572 bool intr_window_requested
;
5573 unsigned count
= 130;
5575 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5576 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5578 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5579 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5580 return handle_interrupt_window(&vmx
->vcpu
);
5582 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5585 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5587 if (err
== EMULATE_USER_EXIT
) {
5588 ++vcpu
->stat
.mmio_exits
;
5593 if (err
!= EMULATE_DONE
) {
5594 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5595 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5596 vcpu
->run
->internal
.ndata
= 0;
5600 if (vcpu
->arch
.halt_request
) {
5601 vcpu
->arch
.halt_request
= 0;
5602 ret
= kvm_emulate_halt(vcpu
);
5606 if (signal_pending(current
))
5612 vmx
->emulation_required
= emulation_required(vcpu
);
5618 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5619 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5621 static int handle_pause(struct kvm_vcpu
*vcpu
)
5623 skip_emulated_instruction(vcpu
);
5624 kvm_vcpu_on_spin(vcpu
);
5629 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5631 kvm_queue_exception(vcpu
, UD_VECTOR
);
5636 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5637 * We could reuse a single VMCS for all the L2 guests, but we also want the
5638 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5639 * allows keeping them loaded on the processor, and in the future will allow
5640 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5641 * every entry if they never change.
5642 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5643 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5645 * The following functions allocate and free a vmcs02 in this pool.
5648 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5649 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5651 struct vmcs02_list
*item
;
5652 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5653 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5654 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5655 return &item
->vmcs02
;
5658 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5659 /* Recycle the least recently used VMCS. */
5660 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5661 struct vmcs02_list
, list
);
5662 item
->vmptr
= vmx
->nested
.current_vmptr
;
5663 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5664 return &item
->vmcs02
;
5667 /* Create a new VMCS */
5668 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5671 item
->vmcs02
.vmcs
= alloc_vmcs();
5672 if (!item
->vmcs02
.vmcs
) {
5676 loaded_vmcs_init(&item
->vmcs02
);
5677 item
->vmptr
= vmx
->nested
.current_vmptr
;
5678 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5679 vmx
->nested
.vmcs02_num
++;
5680 return &item
->vmcs02
;
5683 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5684 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5686 struct vmcs02_list
*item
;
5687 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5688 if (item
->vmptr
== vmptr
) {
5689 free_loaded_vmcs(&item
->vmcs02
);
5690 list_del(&item
->list
);
5692 vmx
->nested
.vmcs02_num
--;
5698 * Free all VMCSs saved for this vcpu, except the one pointed by
5699 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5700 * currently used, if running L2), and vmcs01 when running L2.
5702 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5704 struct vmcs02_list
*item
, *n
;
5705 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5706 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5707 free_loaded_vmcs(&item
->vmcs02
);
5708 list_del(&item
->list
);
5711 vmx
->nested
.vmcs02_num
= 0;
5713 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5714 free_loaded_vmcs(&vmx
->vmcs01
);
5718 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5719 * set the success or error code of an emulated VMX instruction, as specified
5720 * by Vol 2B, VMX Instruction Reference, "Conventions".
5722 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5724 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5725 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5726 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5729 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5731 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5732 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5733 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5737 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5738 u32 vm_instruction_error
)
5740 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5742 * failValid writes the error number to the current VMCS, which
5743 * can't be done there isn't a current VMCS.
5745 nested_vmx_failInvalid(vcpu
);
5748 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5749 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5750 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5752 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5754 * We don't need to force a shadow sync because
5755 * VM_INSTRUCTION_ERROR is not shadowed
5759 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
5761 struct vcpu_vmx
*vmx
=
5762 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
5764 vmx
->nested
.preemption_timer_expired
= true;
5765 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5766 kvm_vcpu_kick(&vmx
->vcpu
);
5768 return HRTIMER_NORESTART
;
5772 * Emulate the VMXON instruction.
5773 * Currently, we just remember that VMX is active, and do not save or even
5774 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5775 * do not currently need to store anything in that guest-allocated memory
5776 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5777 * argument is different from the VMXON pointer (which the spec says they do).
5779 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5781 struct kvm_segment cs
;
5782 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5783 struct vmcs
*shadow_vmcs
;
5784 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5785 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5787 /* The Intel VMX Instruction Reference lists a bunch of bits that
5788 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5789 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5790 * Otherwise, we should fail with #UD. We test these now:
5792 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5793 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5794 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5795 kvm_queue_exception(vcpu
, UD_VECTOR
);
5799 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5800 if (is_long_mode(vcpu
) && !cs
.l
) {
5801 kvm_queue_exception(vcpu
, UD_VECTOR
);
5805 if (vmx_get_cpl(vcpu
)) {
5806 kvm_inject_gp(vcpu
, 0);
5809 if (vmx
->nested
.vmxon
) {
5810 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5811 skip_emulated_instruction(vcpu
);
5815 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5816 != VMXON_NEEDED_FEATURES
) {
5817 kvm_inject_gp(vcpu
, 0);
5821 if (enable_shadow_vmcs
) {
5822 shadow_vmcs
= alloc_vmcs();
5825 /* mark vmcs as shadow */
5826 shadow_vmcs
->revision_id
|= (1u << 31);
5827 /* init shadow vmcs */
5828 vmcs_clear(shadow_vmcs
);
5829 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5832 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5833 vmx
->nested
.vmcs02_num
= 0;
5835 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
5837 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
5839 vmx
->nested
.vmxon
= true;
5841 skip_emulated_instruction(vcpu
);
5842 nested_vmx_succeed(vcpu
);
5847 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5848 * for running VMX instructions (except VMXON, whose prerequisites are
5849 * slightly different). It also specifies what exception to inject otherwise.
5851 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5853 struct kvm_segment cs
;
5854 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5856 if (!vmx
->nested
.vmxon
) {
5857 kvm_queue_exception(vcpu
, UD_VECTOR
);
5861 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5862 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5863 (is_long_mode(vcpu
) && !cs
.l
)) {
5864 kvm_queue_exception(vcpu
, UD_VECTOR
);
5868 if (vmx_get_cpl(vcpu
)) {
5869 kvm_inject_gp(vcpu
, 0);
5876 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5879 if (enable_shadow_vmcs
) {
5880 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5881 /* copy to memory all shadowed fields in case
5882 they were modified */
5883 copy_shadow_to_vmcs12(vmx
);
5884 vmx
->nested
.sync_shadow_vmcs
= false;
5885 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5886 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5887 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5888 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5891 kunmap(vmx
->nested
.current_vmcs12_page
);
5892 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5896 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5897 * just stops using VMX.
5899 static void free_nested(struct vcpu_vmx
*vmx
)
5901 if (!vmx
->nested
.vmxon
)
5903 vmx
->nested
.vmxon
= false;
5904 if (vmx
->nested
.current_vmptr
!= -1ull) {
5905 nested_release_vmcs12(vmx
);
5906 vmx
->nested
.current_vmptr
= -1ull;
5907 vmx
->nested
.current_vmcs12
= NULL
;
5909 if (enable_shadow_vmcs
)
5910 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5911 /* Unpin physical memory we referred to in current vmcs02 */
5912 if (vmx
->nested
.apic_access_page
) {
5913 nested_release_page(vmx
->nested
.apic_access_page
);
5914 vmx
->nested
.apic_access_page
= 0;
5917 nested_free_all_saved_vmcss(vmx
);
5920 /* Emulate the VMXOFF instruction */
5921 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5923 if (!nested_vmx_check_permission(vcpu
))
5925 free_nested(to_vmx(vcpu
));
5926 skip_emulated_instruction(vcpu
);
5927 nested_vmx_succeed(vcpu
);
5932 * Decode the memory-address operand of a vmx instruction, as recorded on an
5933 * exit caused by such an instruction (run by a guest hypervisor).
5934 * On success, returns 0. When the operand is invalid, returns 1 and throws
5937 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5938 unsigned long exit_qualification
,
5939 u32 vmx_instruction_info
, gva_t
*ret
)
5942 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5943 * Execution", on an exit, vmx_instruction_info holds most of the
5944 * addressing components of the operand. Only the displacement part
5945 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5946 * For how an actual address is calculated from all these components,
5947 * refer to Vol. 1, "Operand Addressing".
5949 int scaling
= vmx_instruction_info
& 3;
5950 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5951 bool is_reg
= vmx_instruction_info
& (1u << 10);
5952 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5953 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5954 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5955 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5956 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5959 kvm_queue_exception(vcpu
, UD_VECTOR
);
5963 /* Addr = segment_base + offset */
5964 /* offset = base + [index * scale] + displacement */
5965 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5967 *ret
+= kvm_register_read(vcpu
, base_reg
);
5969 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5970 *ret
+= exit_qualification
; /* holds the displacement */
5972 if (addr_size
== 1) /* 32 bit */
5976 * TODO: throw #GP (and return 1) in various cases that the VM*
5977 * instructions require it - e.g., offset beyond segment limit,
5978 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5979 * address, and so on. Currently these are not checked.
5984 /* Emulate the VMCLEAR instruction */
5985 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5990 struct vmcs12
*vmcs12
;
5992 struct x86_exception e
;
5994 if (!nested_vmx_check_permission(vcpu
))
5997 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5998 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6001 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6002 sizeof(vmptr
), &e
)) {
6003 kvm_inject_page_fault(vcpu
, &e
);
6007 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6008 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
6009 skip_emulated_instruction(vcpu
);
6013 if (vmptr
== vmx
->nested
.current_vmptr
) {
6014 nested_release_vmcs12(vmx
);
6015 vmx
->nested
.current_vmptr
= -1ull;
6016 vmx
->nested
.current_vmcs12
= NULL
;
6019 page
= nested_get_page(vcpu
, vmptr
);
6022 * For accurate processor emulation, VMCLEAR beyond available
6023 * physical memory should do nothing at all. However, it is
6024 * possible that a nested vmx bug, not a guest hypervisor bug,
6025 * resulted in this case, so let's shut down before doing any
6028 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6031 vmcs12
= kmap(page
);
6032 vmcs12
->launch_state
= 0;
6034 nested_release_page(page
);
6036 nested_free_vmcs02(vmx
, vmptr
);
6038 skip_emulated_instruction(vcpu
);
6039 nested_vmx_succeed(vcpu
);
6043 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6045 /* Emulate the VMLAUNCH instruction */
6046 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6048 return nested_vmx_run(vcpu
, true);
6051 /* Emulate the VMRESUME instruction */
6052 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6055 return nested_vmx_run(vcpu
, false);
6058 enum vmcs_field_type
{
6059 VMCS_FIELD_TYPE_U16
= 0,
6060 VMCS_FIELD_TYPE_U64
= 1,
6061 VMCS_FIELD_TYPE_U32
= 2,
6062 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6065 static inline int vmcs_field_type(unsigned long field
)
6067 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6068 return VMCS_FIELD_TYPE_U32
;
6069 return (field
>> 13) & 0x3 ;
6072 static inline int vmcs_field_readonly(unsigned long field
)
6074 return (((field
>> 10) & 0x3) == 1);
6078 * Read a vmcs12 field. Since these can have varying lengths and we return
6079 * one type, we chose the biggest type (u64) and zero-extend the return value
6080 * to that size. Note that the caller, handle_vmread, might need to use only
6081 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6082 * 64-bit fields are to be returned).
6084 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6085 unsigned long field
, u64
*ret
)
6087 short offset
= vmcs_field_to_offset(field
);
6093 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6095 switch (vmcs_field_type(field
)) {
6096 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6097 *ret
= *((natural_width
*)p
);
6099 case VMCS_FIELD_TYPE_U16
:
6102 case VMCS_FIELD_TYPE_U32
:
6105 case VMCS_FIELD_TYPE_U64
:
6109 return 0; /* can never happen. */
6114 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6115 unsigned long field
, u64 field_value
){
6116 short offset
= vmcs_field_to_offset(field
);
6117 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6121 switch (vmcs_field_type(field
)) {
6122 case VMCS_FIELD_TYPE_U16
:
6123 *(u16
*)p
= field_value
;
6125 case VMCS_FIELD_TYPE_U32
:
6126 *(u32
*)p
= field_value
;
6128 case VMCS_FIELD_TYPE_U64
:
6129 *(u64
*)p
= field_value
;
6131 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6132 *(natural_width
*)p
= field_value
;
6135 return false; /* can never happen. */
6140 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6143 unsigned long field
;
6145 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6146 const unsigned long *fields
= shadow_read_write_fields
;
6147 const int num_fields
= max_shadow_read_write_fields
;
6149 vmcs_load(shadow_vmcs
);
6151 for (i
= 0; i
< num_fields
; i
++) {
6153 switch (vmcs_field_type(field
)) {
6154 case VMCS_FIELD_TYPE_U16
:
6155 field_value
= vmcs_read16(field
);
6157 case VMCS_FIELD_TYPE_U32
:
6158 field_value
= vmcs_read32(field
);
6160 case VMCS_FIELD_TYPE_U64
:
6161 field_value
= vmcs_read64(field
);
6163 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6164 field_value
= vmcs_readl(field
);
6167 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6170 vmcs_clear(shadow_vmcs
);
6171 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6174 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6176 const unsigned long *fields
[] = {
6177 shadow_read_write_fields
,
6178 shadow_read_only_fields
6180 const int max_fields
[] = {
6181 max_shadow_read_write_fields
,
6182 max_shadow_read_only_fields
6185 unsigned long field
;
6186 u64 field_value
= 0;
6187 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6189 vmcs_load(shadow_vmcs
);
6191 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6192 for (i
= 0; i
< max_fields
[q
]; i
++) {
6193 field
= fields
[q
][i
];
6194 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6196 switch (vmcs_field_type(field
)) {
6197 case VMCS_FIELD_TYPE_U16
:
6198 vmcs_write16(field
, (u16
)field_value
);
6200 case VMCS_FIELD_TYPE_U32
:
6201 vmcs_write32(field
, (u32
)field_value
);
6203 case VMCS_FIELD_TYPE_U64
:
6204 vmcs_write64(field
, (u64
)field_value
);
6206 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6207 vmcs_writel(field
, (long)field_value
);
6213 vmcs_clear(shadow_vmcs
);
6214 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6218 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6219 * used before) all generate the same failure when it is missing.
6221 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6223 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6224 if (vmx
->nested
.current_vmptr
== -1ull) {
6225 nested_vmx_failInvalid(vcpu
);
6226 skip_emulated_instruction(vcpu
);
6232 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6234 unsigned long field
;
6236 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6237 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6240 if (!nested_vmx_check_permission(vcpu
) ||
6241 !nested_vmx_check_vmcs12(vcpu
))
6244 /* Decode instruction info and find the field to read */
6245 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6246 /* Read the field, zero-extended to a u64 field_value */
6247 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6248 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6249 skip_emulated_instruction(vcpu
);
6253 * Now copy part of this value to register or memory, as requested.
6254 * Note that the number of bits actually copied is 32 or 64 depending
6255 * on the guest's mode (32 or 64 bit), not on the given field's length.
6257 if (vmx_instruction_info
& (1u << 10)) {
6258 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6261 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6262 vmx_instruction_info
, &gva
))
6264 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6265 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6266 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6269 nested_vmx_succeed(vcpu
);
6270 skip_emulated_instruction(vcpu
);
6275 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6277 unsigned long field
;
6279 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6280 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6281 /* The value to write might be 32 or 64 bits, depending on L1's long
6282 * mode, and eventually we need to write that into a field of several
6283 * possible lengths. The code below first zero-extends the value to 64
6284 * bit (field_value), and then copies only the approriate number of
6285 * bits into the vmcs12 field.
6287 u64 field_value
= 0;
6288 struct x86_exception e
;
6290 if (!nested_vmx_check_permission(vcpu
) ||
6291 !nested_vmx_check_vmcs12(vcpu
))
6294 if (vmx_instruction_info
& (1u << 10))
6295 field_value
= kvm_register_read(vcpu
,
6296 (((vmx_instruction_info
) >> 3) & 0xf));
6298 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6299 vmx_instruction_info
, &gva
))
6301 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6302 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6303 kvm_inject_page_fault(vcpu
, &e
);
6309 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6310 if (vmcs_field_readonly(field
)) {
6311 nested_vmx_failValid(vcpu
,
6312 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6313 skip_emulated_instruction(vcpu
);
6317 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6318 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6319 skip_emulated_instruction(vcpu
);
6323 nested_vmx_succeed(vcpu
);
6324 skip_emulated_instruction(vcpu
);
6328 /* Emulate the VMPTRLD instruction */
6329 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6334 struct x86_exception e
;
6337 if (!nested_vmx_check_permission(vcpu
))
6340 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6341 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6344 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6345 sizeof(vmptr
), &e
)) {
6346 kvm_inject_page_fault(vcpu
, &e
);
6350 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6351 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6352 skip_emulated_instruction(vcpu
);
6356 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6357 struct vmcs12
*new_vmcs12
;
6359 page
= nested_get_page(vcpu
, vmptr
);
6361 nested_vmx_failInvalid(vcpu
);
6362 skip_emulated_instruction(vcpu
);
6365 new_vmcs12
= kmap(page
);
6366 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6368 nested_release_page_clean(page
);
6369 nested_vmx_failValid(vcpu
,
6370 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6371 skip_emulated_instruction(vcpu
);
6374 if (vmx
->nested
.current_vmptr
!= -1ull)
6375 nested_release_vmcs12(vmx
);
6377 vmx
->nested
.current_vmptr
= vmptr
;
6378 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6379 vmx
->nested
.current_vmcs12_page
= page
;
6380 if (enable_shadow_vmcs
) {
6381 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6382 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6383 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6384 vmcs_write64(VMCS_LINK_POINTER
,
6385 __pa(vmx
->nested
.current_shadow_vmcs
));
6386 vmx
->nested
.sync_shadow_vmcs
= true;
6390 nested_vmx_succeed(vcpu
);
6391 skip_emulated_instruction(vcpu
);
6395 /* Emulate the VMPTRST instruction */
6396 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6398 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6399 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6401 struct x86_exception e
;
6403 if (!nested_vmx_check_permission(vcpu
))
6406 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6407 vmx_instruction_info
, &vmcs_gva
))
6409 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6410 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6411 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6413 kvm_inject_page_fault(vcpu
, &e
);
6416 nested_vmx_succeed(vcpu
);
6417 skip_emulated_instruction(vcpu
);
6421 /* Emulate the INVEPT instruction */
6422 static int handle_invept(struct kvm_vcpu
*vcpu
)
6424 u32 vmx_instruction_info
, types
;
6427 struct x86_exception e
;
6431 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6433 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6434 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6435 kvm_queue_exception(vcpu
, UD_VECTOR
);
6439 if (!nested_vmx_check_permission(vcpu
))
6442 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6443 kvm_queue_exception(vcpu
, UD_VECTOR
);
6447 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6448 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6450 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6452 if (!(types
& (1UL << type
))) {
6453 nested_vmx_failValid(vcpu
,
6454 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6458 /* According to the Intel VMX instruction reference, the memory
6459 * operand is read even if it isn't needed (e.g., for type==global)
6461 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6462 vmx_instruction_info
, &gva
))
6464 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6465 sizeof(operand
), &e
)) {
6466 kvm_inject_page_fault(vcpu
, &e
);
6471 case VMX_EPT_EXTENT_CONTEXT
:
6472 if ((operand
.eptp
& eptp_mask
) !=
6473 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6475 case VMX_EPT_EXTENT_GLOBAL
:
6476 kvm_mmu_sync_roots(vcpu
);
6477 kvm_mmu_flush_tlb(vcpu
);
6478 nested_vmx_succeed(vcpu
);
6485 skip_emulated_instruction(vcpu
);
6490 * The exit handlers return 1 if the exit was handled fully and guest execution
6491 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6492 * to be done to userspace and return 0.
6494 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6495 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6496 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6497 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6498 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6499 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6500 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6501 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6502 [EXIT_REASON_CPUID
] = handle_cpuid
,
6503 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6504 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6505 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6506 [EXIT_REASON_HLT
] = handle_halt
,
6507 [EXIT_REASON_INVD
] = handle_invd
,
6508 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6509 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6510 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6511 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6512 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6513 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6514 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6515 [EXIT_REASON_VMREAD
] = handle_vmread
,
6516 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6517 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6518 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6519 [EXIT_REASON_VMON
] = handle_vmon
,
6520 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6521 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6522 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6523 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6524 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6525 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6526 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6527 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6528 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6529 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6530 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6531 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6532 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6533 [EXIT_REASON_INVEPT
] = handle_invept
,
6536 static const int kvm_vmx_max_exit_handlers
=
6537 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6539 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6540 struct vmcs12
*vmcs12
)
6542 unsigned long exit_qualification
;
6543 gpa_t bitmap
, last_bitmap
;
6548 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6549 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6551 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6553 port
= exit_qualification
>> 16;
6554 size
= (exit_qualification
& 7) + 1;
6556 last_bitmap
= (gpa_t
)-1;
6561 bitmap
= vmcs12
->io_bitmap_a
;
6562 else if (port
< 0x10000)
6563 bitmap
= vmcs12
->io_bitmap_b
;
6566 bitmap
+= (port
& 0x7fff) / 8;
6568 if (last_bitmap
!= bitmap
)
6569 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6571 if (b
& (1 << (port
& 7)))
6576 last_bitmap
= bitmap
;
6583 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6584 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6585 * disinterest in the current event (read or write a specific MSR) by using an
6586 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6588 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6589 struct vmcs12
*vmcs12
, u32 exit_reason
)
6591 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6594 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6598 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6599 * for the four combinations of read/write and low/high MSR numbers.
6600 * First we need to figure out which of the four to use:
6602 bitmap
= vmcs12
->msr_bitmap
;
6603 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6605 if (msr_index
>= 0xc0000000) {
6606 msr_index
-= 0xc0000000;
6610 /* Then read the msr_index'th bit from this bitmap: */
6611 if (msr_index
< 1024*8) {
6613 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6615 return 1 & (b
>> (msr_index
& 7));
6617 return 1; /* let L1 handle the wrong parameter */
6621 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6622 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6623 * intercept (via guest_host_mask etc.) the current event.
6625 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6626 struct vmcs12
*vmcs12
)
6628 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6629 int cr
= exit_qualification
& 15;
6630 int reg
= (exit_qualification
>> 8) & 15;
6631 unsigned long val
= kvm_register_read(vcpu
, reg
);
6633 switch ((exit_qualification
>> 4) & 3) {
6634 case 0: /* mov to cr */
6637 if (vmcs12
->cr0_guest_host_mask
&
6638 (val
^ vmcs12
->cr0_read_shadow
))
6642 if ((vmcs12
->cr3_target_count
>= 1 &&
6643 vmcs12
->cr3_target_value0
== val
) ||
6644 (vmcs12
->cr3_target_count
>= 2 &&
6645 vmcs12
->cr3_target_value1
== val
) ||
6646 (vmcs12
->cr3_target_count
>= 3 &&
6647 vmcs12
->cr3_target_value2
== val
) ||
6648 (vmcs12
->cr3_target_count
>= 4 &&
6649 vmcs12
->cr3_target_value3
== val
))
6651 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6655 if (vmcs12
->cr4_guest_host_mask
&
6656 (vmcs12
->cr4_read_shadow
^ val
))
6660 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6666 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6667 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6670 case 1: /* mov from cr */
6673 if (vmcs12
->cpu_based_vm_exec_control
&
6674 CPU_BASED_CR3_STORE_EXITING
)
6678 if (vmcs12
->cpu_based_vm_exec_control
&
6679 CPU_BASED_CR8_STORE_EXITING
)
6686 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6687 * cr0. Other attempted changes are ignored, with no exit.
6689 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6690 (val
^ vmcs12
->cr0_read_shadow
))
6692 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6693 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6702 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6703 * should handle it ourselves in L0 (and then continue L2). Only call this
6704 * when in is_guest_mode (L2).
6706 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6708 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6709 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6710 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6711 u32 exit_reason
= vmx
->exit_reason
;
6713 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6714 vmcs_readl(EXIT_QUALIFICATION
),
6715 vmx
->idt_vectoring_info
,
6717 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6720 if (vmx
->nested
.nested_run_pending
)
6723 if (unlikely(vmx
->fail
)) {
6724 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6725 vmcs_read32(VM_INSTRUCTION_ERROR
));
6729 switch (exit_reason
) {
6730 case EXIT_REASON_EXCEPTION_NMI
:
6731 if (!is_exception(intr_info
))
6733 else if (is_page_fault(intr_info
))
6735 else if (is_no_device(intr_info
) &&
6736 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
6738 return vmcs12
->exception_bitmap
&
6739 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6740 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6742 case EXIT_REASON_TRIPLE_FAULT
:
6744 case EXIT_REASON_PENDING_INTERRUPT
:
6745 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6746 case EXIT_REASON_NMI_WINDOW
:
6747 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6748 case EXIT_REASON_TASK_SWITCH
:
6750 case EXIT_REASON_CPUID
:
6752 case EXIT_REASON_HLT
:
6753 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6754 case EXIT_REASON_INVD
:
6756 case EXIT_REASON_INVLPG
:
6757 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6758 case EXIT_REASON_RDPMC
:
6759 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6760 case EXIT_REASON_RDTSC
:
6761 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6762 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6763 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6764 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6765 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6766 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6767 case EXIT_REASON_INVEPT
:
6769 * VMX instructions trap unconditionally. This allows L1 to
6770 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6773 case EXIT_REASON_CR_ACCESS
:
6774 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6775 case EXIT_REASON_DR_ACCESS
:
6776 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6777 case EXIT_REASON_IO_INSTRUCTION
:
6778 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6779 case EXIT_REASON_MSR_READ
:
6780 case EXIT_REASON_MSR_WRITE
:
6781 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6782 case EXIT_REASON_INVALID_STATE
:
6784 case EXIT_REASON_MWAIT_INSTRUCTION
:
6785 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6786 case EXIT_REASON_MONITOR_INSTRUCTION
:
6787 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6788 case EXIT_REASON_PAUSE_INSTRUCTION
:
6789 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6790 nested_cpu_has2(vmcs12
,
6791 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6792 case EXIT_REASON_MCE_DURING_VMENTRY
:
6794 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6796 case EXIT_REASON_APIC_ACCESS
:
6797 return nested_cpu_has2(vmcs12
,
6798 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6799 case EXIT_REASON_EPT_VIOLATION
:
6801 * L0 always deals with the EPT violation. If nested EPT is
6802 * used, and the nested mmu code discovers that the address is
6803 * missing in the guest EPT table (EPT12), the EPT violation
6804 * will be injected with nested_ept_inject_page_fault()
6807 case EXIT_REASON_EPT_MISCONFIG
:
6809 * L2 never uses directly L1's EPT, but rather L0's own EPT
6810 * table (shadow on EPT) or a merged EPT table that L0 built
6811 * (EPT on EPT). So any problems with the structure of the
6812 * table is L0's fault.
6815 case EXIT_REASON_WBINVD
:
6816 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6817 case EXIT_REASON_XSETBV
:
6824 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6826 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6827 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6831 * The guest has exited. See if we can fix it or if we need userspace
6834 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6836 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6837 u32 exit_reason
= vmx
->exit_reason
;
6838 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6840 /* If guest state is invalid, start emulating */
6841 if (vmx
->emulation_required
)
6842 return handle_invalid_guest_state(vcpu
);
6844 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6845 nested_vmx_vmexit(vcpu
, exit_reason
,
6846 vmcs_read32(VM_EXIT_INTR_INFO
),
6847 vmcs_readl(EXIT_QUALIFICATION
));
6851 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6852 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6853 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6858 if (unlikely(vmx
->fail
)) {
6859 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6860 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6861 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6867 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6868 * delivery event since it indicates guest is accessing MMIO.
6869 * The vm-exit can be triggered again after return to guest that
6870 * will cause infinite loop.
6872 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6873 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6874 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6875 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6876 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6877 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6878 vcpu
->run
->internal
.ndata
= 2;
6879 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6880 vcpu
->run
->internal
.data
[1] = exit_reason
;
6884 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6885 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6886 get_vmcs12(vcpu
))))) {
6887 if (vmx_interrupt_allowed(vcpu
)) {
6888 vmx
->soft_vnmi_blocked
= 0;
6889 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6890 vcpu
->arch
.nmi_pending
) {
6892 * This CPU don't support us in finding the end of an
6893 * NMI-blocked window if the guest runs with IRQs
6894 * disabled. So we pull the trigger after 1 s of
6895 * futile waiting, but inform the user about this.
6897 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6898 "state on VCPU %d after 1 s timeout\n",
6899 __func__
, vcpu
->vcpu_id
);
6900 vmx
->soft_vnmi_blocked
= 0;
6904 if (exit_reason
< kvm_vmx_max_exit_handlers
6905 && kvm_vmx_exit_handlers
[exit_reason
])
6906 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6908 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6909 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6914 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6916 if (irr
== -1 || tpr
< irr
) {
6917 vmcs_write32(TPR_THRESHOLD
, 0);
6921 vmcs_write32(TPR_THRESHOLD
, irr
);
6924 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6926 u32 sec_exec_control
;
6929 * There is not point to enable virtualize x2apic without enable
6932 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6933 !vmx_vm_has_apicv(vcpu
->kvm
))
6936 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6939 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6942 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6943 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6945 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6946 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6948 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6950 vmx_set_msr_bitmap(vcpu
);
6953 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6958 if (!vmx_vm_has_apicv(kvm
))
6964 status
= vmcs_read16(GUEST_INTR_STATUS
);
6969 vmcs_write16(GUEST_INTR_STATUS
, status
);
6973 static void vmx_set_rvi(int vector
)
6978 status
= vmcs_read16(GUEST_INTR_STATUS
);
6979 old
= (u8
)status
& 0xff;
6980 if ((u8
)vector
!= old
) {
6982 status
|= (u8
)vector
;
6983 vmcs_write16(GUEST_INTR_STATUS
, status
);
6987 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6992 vmx_set_rvi(max_irr
);
6995 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6997 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7000 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7001 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7002 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7003 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7006 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7010 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7011 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7014 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7015 exit_intr_info
= vmx
->exit_intr_info
;
7017 /* Handle machine checks before interrupts are enabled */
7018 if (is_machine_check(exit_intr_info
))
7019 kvm_machine_check();
7021 /* We need to handle NMIs before interrupts are enabled */
7022 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7023 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7024 kvm_before_handle_nmi(&vmx
->vcpu
);
7026 kvm_after_handle_nmi(&vmx
->vcpu
);
7030 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7032 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7035 * If external interrupt exists, IF bit is set in rflags/eflags on the
7036 * interrupt stack frame, and interrupt will be enabled on a return
7037 * from interrupt handler.
7039 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7040 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7041 unsigned int vector
;
7042 unsigned long entry
;
7044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7045 #ifdef CONFIG_X86_64
7049 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7050 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7051 entry
= gate_offset(*desc
);
7053 #ifdef CONFIG_X86_64
7054 "mov %%" _ASM_SP
", %[sp]\n\t"
7055 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7060 "orl $0x200, (%%" _ASM_SP
")\n\t"
7061 __ASM_SIZE(push
) " $%c[cs]\n\t"
7062 "call *%[entry]\n\t"
7064 #ifdef CONFIG_X86_64
7069 [ss
]"i"(__KERNEL_DS
),
7070 [cs
]"i"(__KERNEL_CS
)
7076 static bool vmx_mpx_supported(void)
7078 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7079 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7082 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7087 bool idtv_info_valid
;
7089 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7091 if (cpu_has_virtual_nmis()) {
7092 if (vmx
->nmi_known_unmasked
)
7095 * Can't use vmx->exit_intr_info since we're not sure what
7096 * the exit reason is.
7098 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7099 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7100 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7102 * SDM 3: 27.7.1.2 (September 2008)
7103 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7104 * a guest IRET fault.
7105 * SDM 3: 23.2.2 (September 2008)
7106 * Bit 12 is undefined in any of the following cases:
7107 * If the VM exit sets the valid bit in the IDT-vectoring
7108 * information field.
7109 * If the VM exit is due to a double fault.
7111 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7112 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7113 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7114 GUEST_INTR_STATE_NMI
);
7116 vmx
->nmi_known_unmasked
=
7117 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7118 & GUEST_INTR_STATE_NMI
);
7119 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7120 vmx
->vnmi_blocked_time
+=
7121 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7124 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7125 u32 idt_vectoring_info
,
7126 int instr_len_field
,
7127 int error_code_field
)
7131 bool idtv_info_valid
;
7133 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7135 vcpu
->arch
.nmi_injected
= false;
7136 kvm_clear_exception_queue(vcpu
);
7137 kvm_clear_interrupt_queue(vcpu
);
7139 if (!idtv_info_valid
)
7142 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7144 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7145 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7148 case INTR_TYPE_NMI_INTR
:
7149 vcpu
->arch
.nmi_injected
= true;
7151 * SDM 3: 27.7.1.2 (September 2008)
7152 * Clear bit "block by NMI" before VM entry if a NMI
7155 vmx_set_nmi_mask(vcpu
, false);
7157 case INTR_TYPE_SOFT_EXCEPTION
:
7158 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7160 case INTR_TYPE_HARD_EXCEPTION
:
7161 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7162 u32 err
= vmcs_read32(error_code_field
);
7163 kvm_requeue_exception_e(vcpu
, vector
, err
);
7165 kvm_requeue_exception(vcpu
, vector
);
7167 case INTR_TYPE_SOFT_INTR
:
7168 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7170 case INTR_TYPE_EXT_INTR
:
7171 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7178 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7180 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7181 VM_EXIT_INSTRUCTION_LEN
,
7182 IDT_VECTORING_ERROR_CODE
);
7185 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7187 __vmx_complete_interrupts(vcpu
,
7188 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7189 VM_ENTRY_INSTRUCTION_LEN
,
7190 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7192 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7195 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7198 struct perf_guest_switch_msr
*msrs
;
7200 msrs
= perf_guest_get_msrs(&nr_msrs
);
7205 for (i
= 0; i
< nr_msrs
; i
++)
7206 if (msrs
[i
].host
== msrs
[i
].guest
)
7207 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7209 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7213 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7215 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7216 unsigned long debugctlmsr
;
7218 /* Record the guest's net vcpu time for enforced NMI injections. */
7219 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7220 vmx
->entry_time
= ktime_get();
7222 /* Don't enter VMX if guest state is invalid, let the exit handler
7223 start emulation until we arrive back to a valid state */
7224 if (vmx
->emulation_required
)
7227 if (vmx
->nested
.sync_shadow_vmcs
) {
7228 copy_vmcs12_to_shadow(vmx
);
7229 vmx
->nested
.sync_shadow_vmcs
= false;
7232 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7233 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7234 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7235 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7237 /* When single-stepping over STI and MOV SS, we must clear the
7238 * corresponding interruptibility bits in the guest state. Otherwise
7239 * vmentry fails as it then expects bit 14 (BS) in pending debug
7240 * exceptions being set, but that's not correct for the guest debugging
7242 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7243 vmx_set_interrupt_shadow(vcpu
, 0);
7245 atomic_switch_perf_msrs(vmx
);
7246 debugctlmsr
= get_debugctlmsr();
7248 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7250 /* Store host registers */
7251 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7252 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7253 "push %%" _ASM_CX
" \n\t"
7254 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7256 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7257 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7259 /* Reload cr2 if changed */
7260 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7261 "mov %%cr2, %%" _ASM_DX
" \n\t"
7262 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7264 "mov %%" _ASM_AX
", %%cr2 \n\t"
7266 /* Check if vmlaunch of vmresume is needed */
7267 "cmpl $0, %c[launched](%0) \n\t"
7268 /* Load guest registers. Don't clobber flags. */
7269 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7270 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7271 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7272 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7273 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7274 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7275 #ifdef CONFIG_X86_64
7276 "mov %c[r8](%0), %%r8 \n\t"
7277 "mov %c[r9](%0), %%r9 \n\t"
7278 "mov %c[r10](%0), %%r10 \n\t"
7279 "mov %c[r11](%0), %%r11 \n\t"
7280 "mov %c[r12](%0), %%r12 \n\t"
7281 "mov %c[r13](%0), %%r13 \n\t"
7282 "mov %c[r14](%0), %%r14 \n\t"
7283 "mov %c[r15](%0), %%r15 \n\t"
7285 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7287 /* Enter guest mode */
7289 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7291 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7293 /* Save guest registers, load host registers, keep flags */
7294 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7296 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7297 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7298 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7299 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7300 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7301 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7302 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7303 #ifdef CONFIG_X86_64
7304 "mov %%r8, %c[r8](%0) \n\t"
7305 "mov %%r9, %c[r9](%0) \n\t"
7306 "mov %%r10, %c[r10](%0) \n\t"
7307 "mov %%r11, %c[r11](%0) \n\t"
7308 "mov %%r12, %c[r12](%0) \n\t"
7309 "mov %%r13, %c[r13](%0) \n\t"
7310 "mov %%r14, %c[r14](%0) \n\t"
7311 "mov %%r15, %c[r15](%0) \n\t"
7313 "mov %%cr2, %%" _ASM_AX
" \n\t"
7314 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7316 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7317 "setbe %c[fail](%0) \n\t"
7318 ".pushsection .rodata \n\t"
7319 ".global vmx_return \n\t"
7320 "vmx_return: " _ASM_PTR
" 2b \n\t"
7322 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7323 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7324 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7325 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7326 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7327 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7328 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7329 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7330 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7331 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7332 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7333 #ifdef CONFIG_X86_64
7334 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7335 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7336 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7337 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7338 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7339 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7340 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7341 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7343 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7344 [wordsize
]"i"(sizeof(ulong
))
7346 #ifdef CONFIG_X86_64
7347 , "rax", "rbx", "rdi", "rsi"
7348 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7350 , "eax", "ebx", "edi", "esi"
7354 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7356 update_debugctlmsr(debugctlmsr
);
7358 #ifndef CONFIG_X86_64
7360 * The sysexit path does not restore ds/es, so we must set them to
7361 * a reasonable value ourselves.
7363 * We can't defer this to vmx_load_host_state() since that function
7364 * may be executed in interrupt context, which saves and restore segments
7365 * around it, nullifying its effect.
7367 loadsegment(ds
, __USER_DS
);
7368 loadsegment(es
, __USER_DS
);
7371 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7372 | (1 << VCPU_EXREG_RFLAGS
)
7373 | (1 << VCPU_EXREG_CPL
)
7374 | (1 << VCPU_EXREG_PDPTR
)
7375 | (1 << VCPU_EXREG_SEGMENTS
)
7376 | (1 << VCPU_EXREG_CR3
));
7377 vcpu
->arch
.regs_dirty
= 0;
7379 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7381 vmx
->loaded_vmcs
->launched
= 1;
7383 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7384 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7387 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7388 * we did not inject a still-pending event to L1 now because of
7389 * nested_run_pending, we need to re-enable this bit.
7391 if (vmx
->nested
.nested_run_pending
)
7392 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7394 vmx
->nested
.nested_run_pending
= 0;
7396 vmx_complete_atomic_exit(vmx
);
7397 vmx_recover_nmi_blocking(vmx
);
7398 vmx_complete_interrupts(vmx
);
7401 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7403 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7406 free_loaded_vmcs(vmx
->loaded_vmcs
);
7408 kfree(vmx
->guest_msrs
);
7409 kvm_vcpu_uninit(vcpu
);
7410 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7413 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7416 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7420 return ERR_PTR(-ENOMEM
);
7424 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7428 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7430 if (!vmx
->guest_msrs
) {
7434 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7435 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7436 if (!vmx
->loaded_vmcs
->vmcs
)
7439 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7440 loaded_vmcs_init(vmx
->loaded_vmcs
);
7445 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7446 vmx
->vcpu
.cpu
= cpu
;
7447 err
= vmx_vcpu_setup(vmx
);
7448 vmx_vcpu_put(&vmx
->vcpu
);
7452 if (vm_need_virtualize_apic_accesses(kvm
)) {
7453 err
= alloc_apic_access_page(kvm
);
7459 if (!kvm
->arch
.ept_identity_map_addr
)
7460 kvm
->arch
.ept_identity_map_addr
=
7461 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7463 if (alloc_identity_pagetable(kvm
) != 0)
7465 if (!init_rmode_identity_map(kvm
))
7469 vmx
->nested
.current_vmptr
= -1ull;
7470 vmx
->nested
.current_vmcs12
= NULL
;
7475 free_loaded_vmcs(vmx
->loaded_vmcs
);
7477 kfree(vmx
->guest_msrs
);
7479 kvm_vcpu_uninit(&vmx
->vcpu
);
7482 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7483 return ERR_PTR(err
);
7486 static void __init
vmx_check_processor_compat(void *rtn
)
7488 struct vmcs_config vmcs_conf
;
7491 if (setup_vmcs_config(&vmcs_conf
) < 0)
7493 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7494 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7495 smp_processor_id());
7500 static int get_ept_level(void)
7502 return VMX_EPT_DEFAULT_GAW
+ 1;
7505 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7509 /* For VT-d and EPT combination
7510 * 1. MMIO: always map as UC
7512 * a. VT-d without snooping control feature: can't guarantee the
7513 * result, try to trust guest.
7514 * b. VT-d with snooping control feature: snooping control feature of
7515 * VT-d engine can guarantee the cache correctness. Just set it
7516 * to WB to keep consistent with host. So the same as item 3.
7517 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7518 * consistent with host MTRR
7521 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7522 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7523 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7524 VMX_EPT_MT_EPTE_SHIFT
;
7526 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7532 static int vmx_get_lpage_level(void)
7534 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7535 return PT_DIRECTORY_LEVEL
;
7537 /* For shadow and EPT supported 1GB page */
7538 return PT_PDPE_LEVEL
;
7541 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7543 struct kvm_cpuid_entry2
*best
;
7544 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7547 vmx
->rdtscp_enabled
= false;
7548 if (vmx_rdtscp_supported()) {
7549 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7550 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7551 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7552 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7553 vmx
->rdtscp_enabled
= true;
7555 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7556 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7562 /* Exposing INVPCID only when PCID is exposed */
7563 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7564 if (vmx_invpcid_supported() &&
7565 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7566 guest_cpuid_has_pcid(vcpu
)) {
7567 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7568 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7569 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7572 if (cpu_has_secondary_exec_ctrls()) {
7573 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7574 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7575 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7579 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7583 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7585 if (func
== 1 && nested
)
7586 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7589 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7590 struct x86_exception
*fault
)
7592 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7595 if (fault
->error_code
& PFERR_RSVD_MASK
)
7596 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7598 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7599 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7600 vmcs12
->guest_physical_address
= fault
->address
;
7603 /* Callbacks for nested_ept_init_mmu_context: */
7605 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7607 /* return the page table to be shadowed - in our case, EPT12 */
7608 return get_vmcs12(vcpu
)->ept_pointer
;
7611 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7613 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7614 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7616 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7617 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7618 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7620 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7623 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7625 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7628 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7629 struct x86_exception
*fault
)
7631 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7633 WARN_ON(!is_guest_mode(vcpu
));
7635 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7636 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7637 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7638 vmcs_read32(VM_EXIT_INTR_INFO
),
7639 vmcs_readl(EXIT_QUALIFICATION
));
7641 kvm_inject_page_fault(vcpu
, fault
);
7644 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
7646 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
7647 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7649 if (vcpu
->arch
.virtual_tsc_khz
== 0)
7652 /* Make sure short timeouts reliably trigger an immediate vmexit.
7653 * hrtimer_start does not guarantee this. */
7654 if (preemption_timeout
<= 1) {
7655 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
7659 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
7660 preemption_timeout
*= 1000000;
7661 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
7662 hrtimer_start(&vmx
->nested
.preemption_timer
,
7663 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
7667 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7668 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7669 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7670 * guest in a way that will both be appropriate to L1's requests, and our
7671 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7672 * function also has additional necessary side-effects, like setting various
7673 * vcpu->arch fields.
7675 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7680 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7681 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7682 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7683 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7684 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7685 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7686 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7687 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7688 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7689 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7690 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7691 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7692 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7693 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7694 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7695 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7696 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7697 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7698 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7699 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7700 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7701 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7702 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7703 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7704 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7705 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7706 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7707 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7708 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7709 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7710 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7711 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7712 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7713 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7714 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7715 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7717 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7718 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7719 vmcs12
->vm_entry_intr_info_field
);
7720 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7721 vmcs12
->vm_entry_exception_error_code
);
7722 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7723 vmcs12
->vm_entry_instruction_len
);
7724 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7725 vmcs12
->guest_interruptibility_info
);
7726 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7727 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7728 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7729 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7730 vmcs12
->guest_pending_dbg_exceptions
);
7731 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7732 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7734 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7736 exec_control
= vmcs12
->pin_based_vm_exec_control
;
7737 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
7738 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
7739 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
7741 vmx
->nested
.preemption_timer_expired
= false;
7742 if (nested_cpu_has_preemption_timer(vmcs12
))
7743 vmx_start_preemption_timer(vcpu
);
7746 * Whether page-faults are trapped is determined by a combination of
7747 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7748 * If enable_ept, L0 doesn't care about page faults and we should
7749 * set all of these to L1's desires. However, if !enable_ept, L0 does
7750 * care about (at least some) page faults, and because it is not easy
7751 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7752 * to exit on each and every L2 page fault. This is done by setting
7753 * MASK=MATCH=0 and (see below) EB.PF=1.
7754 * Note that below we don't need special code to set EB.PF beyond the
7755 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7756 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7757 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7759 * A problem with this approach (when !enable_ept) is that L1 may be
7760 * injected with more page faults than it asked for. This could have
7761 * caused problems, but in practice existing hypervisors don't care.
7762 * To fix this, we will need to emulate the PFEC checking (on the L1
7763 * page tables), using walk_addr(), when injecting PFs to L1.
7765 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7766 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7767 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7768 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7770 if (cpu_has_secondary_exec_ctrls()) {
7771 exec_control
= vmx_secondary_exec_control(vmx
);
7772 if (!vmx
->rdtscp_enabled
)
7773 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7774 /* Take the following fields only from vmcs12 */
7775 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7776 if (nested_cpu_has(vmcs12
,
7777 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7778 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7780 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7782 * Translate L1 physical address to host physical
7783 * address for vmcs02. Keep the page pinned, so this
7784 * physical address remains valid. We keep a reference
7785 * to it so we can release it later.
7787 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7788 nested_release_page(vmx
->nested
.apic_access_page
);
7789 vmx
->nested
.apic_access_page
=
7790 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7792 * If translation failed, no matter: This feature asks
7793 * to exit when accessing the given address, and if it
7794 * can never be accessed, this feature won't do
7797 if (!vmx
->nested
.apic_access_page
)
7799 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7801 vmcs_write64(APIC_ACCESS_ADDR
,
7802 page_to_phys(vmx
->nested
.apic_access_page
));
7803 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
7805 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7806 vmcs_write64(APIC_ACCESS_ADDR
,
7807 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
7810 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7815 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7816 * Some constant fields are set here by vmx_set_constant_host_state().
7817 * Other fields are different per CPU, and will be set later when
7818 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7820 vmx_set_constant_host_state(vmx
);
7823 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7824 * entry, but only if the current (host) sp changed from the value
7825 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7826 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7827 * here we just force the write to happen on entry.
7831 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7832 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7833 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7834 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7835 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7837 * Merging of IO and MSR bitmaps not currently supported.
7838 * Rather, exit every time.
7840 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7841 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7842 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7846 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7847 * bitwise-or of what L1 wants to trap for L2, and what we want to
7848 * trap. Note that CR0.TS also needs updating - we do this later.
7850 update_exception_bitmap(vcpu
);
7851 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7852 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7854 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7855 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7856 * bits are further modified by vmx_set_efer() below.
7858 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
7860 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7861 * emulated by vmx_set_efer(), below.
7863 vm_entry_controls_init(vmx
,
7864 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7865 ~VM_ENTRY_IA32E_MODE
) |
7866 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7868 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7869 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7870 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7871 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7872 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7875 set_cr4_guest_host_mask(vmx
);
7877 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
7878 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
7880 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7881 vmcs_write64(TSC_OFFSET
,
7882 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7884 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7888 * Trivially support vpid by letting L2s share their parent
7889 * L1's vpid. TODO: move to a more elaborate solution, giving
7890 * each L2 its own vpid and exposing the vpid feature to L1.
7892 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7893 vmx_flush_tlb(vcpu
);
7896 if (nested_cpu_has_ept(vmcs12
)) {
7897 kvm_mmu_unload(vcpu
);
7898 nested_ept_init_mmu_context(vcpu
);
7901 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7902 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7903 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7904 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7906 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7907 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7908 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7911 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7912 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7913 * The CR0_READ_SHADOW is what L2 should have expected to read given
7914 * the specifications by L1; It's not enough to take
7915 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7916 * have more bits than L1 expected.
7918 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7919 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7921 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7922 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7924 /* shadow page tables on either EPT or shadow page tables */
7925 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7926 kvm_mmu_reset_context(vcpu
);
7929 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7932 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7935 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7936 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7937 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7938 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7941 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7942 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7946 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7947 * for running an L2 nested guest.
7949 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7951 struct vmcs12
*vmcs12
;
7952 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7954 struct loaded_vmcs
*vmcs02
;
7957 if (!nested_vmx_check_permission(vcpu
) ||
7958 !nested_vmx_check_vmcs12(vcpu
))
7961 skip_emulated_instruction(vcpu
);
7962 vmcs12
= get_vmcs12(vcpu
);
7964 if (enable_shadow_vmcs
)
7965 copy_shadow_to_vmcs12(vmx
);
7968 * The nested entry process starts with enforcing various prerequisites
7969 * on vmcs12 as required by the Intel SDM, and act appropriately when
7970 * they fail: As the SDM explains, some conditions should cause the
7971 * instruction to fail, while others will cause the instruction to seem
7972 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7973 * To speed up the normal (success) code path, we should avoid checking
7974 * for misconfigurations which will anyway be caught by the processor
7975 * when using the merged vmcs02.
7977 if (vmcs12
->launch_state
== launch
) {
7978 nested_vmx_failValid(vcpu
,
7979 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7980 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7984 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
7985 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
7986 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7990 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7991 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7992 /*TODO: Also verify bits beyond physical address width are 0*/
7993 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7997 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7998 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7999 /*TODO: Also verify bits beyond physical address width are 0*/
8000 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8004 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8005 vmcs12
->vm_exit_msr_load_count
> 0 ||
8006 vmcs12
->vm_exit_msr_store_count
> 0) {
8007 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8009 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8013 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8014 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
8015 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8016 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8017 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8018 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8019 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8020 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
8021 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8022 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
8024 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8028 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8029 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8030 nested_vmx_failValid(vcpu
,
8031 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8035 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8036 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8037 nested_vmx_entry_failure(vcpu
, vmcs12
,
8038 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8041 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8042 nested_vmx_entry_failure(vcpu
, vmcs12
,
8043 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8048 * If the load IA32_EFER VM-entry control is 1, the following checks
8049 * are performed on the field for the IA32_EFER MSR:
8050 * - Bits reserved in the IA32_EFER MSR must be 0.
8051 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8052 * the IA-32e mode guest VM-exit control. It must also be identical
8053 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8056 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8057 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8058 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8059 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8060 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8061 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8062 nested_vmx_entry_failure(vcpu
, vmcs12
,
8063 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8069 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8070 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8071 * the values of the LMA and LME bits in the field must each be that of
8072 * the host address-space size VM-exit control.
8074 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8075 ia32e
= (vmcs12
->vm_exit_controls
&
8076 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8077 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8078 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8079 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8080 nested_vmx_entry_failure(vcpu
, vmcs12
,
8081 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8087 * We're finally done with prerequisite checking, and can start with
8091 vmcs02
= nested_get_current_vmcs02(vmx
);
8095 enter_guest_mode(vcpu
);
8097 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8100 vmx
->loaded_vmcs
= vmcs02
;
8102 vmx_vcpu_load(vcpu
, cpu
);
8106 vmx_segment_cache_clear(vmx
);
8108 vmcs12
->launch_state
= 1;
8110 prepare_vmcs02(vcpu
, vmcs12
);
8112 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8113 return kvm_emulate_halt(vcpu
);
8115 vmx
->nested
.nested_run_pending
= 1;
8118 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8119 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8120 * returned as far as L1 is concerned. It will only return (and set
8121 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8127 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8128 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8129 * This function returns the new value we should put in vmcs12.guest_cr0.
8130 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8131 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8132 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8133 * didn't trap the bit, because if L1 did, so would L0).
8134 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8135 * been modified by L2, and L1 knows it. So just leave the old value of
8136 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8137 * isn't relevant, because if L0 traps this bit it can set it to anything.
8138 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8139 * changed these bits, and therefore they need to be updated, but L0
8140 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8141 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8143 static inline unsigned long
8144 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8147 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8148 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8149 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8150 vcpu
->arch
.cr0_guest_owned_bits
));
8153 static inline unsigned long
8154 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8157 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8158 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8159 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8160 vcpu
->arch
.cr4_guest_owned_bits
));
8163 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8164 struct vmcs12
*vmcs12
)
8169 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8170 nr
= vcpu
->arch
.exception
.nr
;
8171 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8173 if (kvm_exception_is_soft(nr
)) {
8174 vmcs12
->vm_exit_instruction_len
=
8175 vcpu
->arch
.event_exit_inst_len
;
8176 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8178 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8180 if (vcpu
->arch
.exception
.has_error_code
) {
8181 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8182 vmcs12
->idt_vectoring_error_code
=
8183 vcpu
->arch
.exception
.error_code
;
8186 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8187 } else if (vcpu
->arch
.nmi_injected
) {
8188 vmcs12
->idt_vectoring_info_field
=
8189 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8190 } else if (vcpu
->arch
.interrupt
.pending
) {
8191 nr
= vcpu
->arch
.interrupt
.nr
;
8192 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8194 if (vcpu
->arch
.interrupt
.soft
) {
8195 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8196 vmcs12
->vm_entry_instruction_len
=
8197 vcpu
->arch
.event_exit_inst_len
;
8199 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8201 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8205 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8207 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8209 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8210 vmx
->nested
.preemption_timer_expired
) {
8211 if (vmx
->nested
.nested_run_pending
)
8213 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8217 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8218 if (vmx
->nested
.nested_run_pending
||
8219 vcpu
->arch
.interrupt
.pending
)
8221 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8222 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8223 INTR_INFO_VALID_MASK
, 0);
8225 * The NMI-triggered VM exit counts as injection:
8226 * clear this one and block further NMIs.
8228 vcpu
->arch
.nmi_pending
= 0;
8229 vmx_set_nmi_mask(vcpu
, true);
8233 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8234 nested_exit_on_intr(vcpu
)) {
8235 if (vmx
->nested
.nested_run_pending
)
8237 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8243 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8246 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8249 if (ktime_to_ns(remaining
) <= 0)
8252 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8253 do_div(value
, 1000000);
8254 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8258 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8259 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8260 * and this function updates it to reflect the changes to the guest state while
8261 * L2 was running (and perhaps made some exits which were handled directly by L0
8262 * without going back to L1), and to reflect the exit reason.
8263 * Note that we do not have to copy here all VMCS fields, just those that
8264 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8265 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8266 * which already writes to vmcs12 directly.
8268 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8269 u32 exit_reason
, u32 exit_intr_info
,
8270 unsigned long exit_qualification
)
8272 /* update guest state fields: */
8273 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8274 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8276 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8277 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8278 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8279 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8281 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8282 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8283 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8284 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8285 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8286 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8287 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8288 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8289 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8290 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8291 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8292 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8293 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8294 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8295 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8296 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8297 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8298 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8299 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8300 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8301 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8302 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8303 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8304 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8305 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8306 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8307 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8308 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8309 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8310 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8311 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8312 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8313 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8314 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8315 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8316 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8318 vmcs12
->guest_interruptibility_info
=
8319 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8320 vmcs12
->guest_pending_dbg_exceptions
=
8321 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8322 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8323 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8325 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8327 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8328 if (vmcs12
->vm_exit_controls
&
8329 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8330 vmcs12
->vmx_preemption_timer_value
=
8331 vmx_get_preemption_timer_value(vcpu
);
8332 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8336 * In some cases (usually, nested EPT), L2 is allowed to change its
8337 * own CR3 without exiting. If it has changed it, we must keep it.
8338 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8339 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8341 * Additionally, restore L2's PDPTR to vmcs12.
8344 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8345 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8346 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8347 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8348 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8351 vmcs12
->vm_entry_controls
=
8352 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8353 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8355 /* TODO: These cannot have changed unless we have MSR bitmaps and
8356 * the relevant bit asks not to trap the change */
8357 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8358 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8359 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8360 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8361 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8362 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8363 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8364 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8365 if (vmx_mpx_supported())
8366 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8368 /* update exit information fields: */
8370 vmcs12
->vm_exit_reason
= exit_reason
;
8371 vmcs12
->exit_qualification
= exit_qualification
;
8373 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8374 if ((vmcs12
->vm_exit_intr_info
&
8375 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8376 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8377 vmcs12
->vm_exit_intr_error_code
=
8378 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8379 vmcs12
->idt_vectoring_info_field
= 0;
8380 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8381 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8383 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8384 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8385 * instead of reading the real value. */
8386 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8389 * Transfer the event that L0 or L1 may wanted to inject into
8390 * L2 to IDT_VECTORING_INFO_FIELD.
8392 vmcs12_save_pending_event(vcpu
, vmcs12
);
8396 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8397 * preserved above and would only end up incorrectly in L1.
8399 vcpu
->arch
.nmi_injected
= false;
8400 kvm_clear_exception_queue(vcpu
);
8401 kvm_clear_interrupt_queue(vcpu
);
8405 * A part of what we need to when the nested L2 guest exits and we want to
8406 * run its L1 parent, is to reset L1's guest state to the host state specified
8408 * This function is to be called not only on normal nested exit, but also on
8409 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8410 * Failures During or After Loading Guest State").
8411 * This function should be called when the active VMCS is L1's (vmcs01).
8413 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8414 struct vmcs12
*vmcs12
)
8416 struct kvm_segment seg
;
8418 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8419 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8420 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8421 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8423 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8424 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8426 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8427 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8428 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8430 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8431 * actually changed, because it depends on the current state of
8432 * fpu_active (which may have changed).
8433 * Note that vmx_set_cr0 refers to efer set above.
8435 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8437 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8438 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8439 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8441 update_exception_bitmap(vcpu
);
8442 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8443 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8446 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8447 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8449 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8450 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8452 nested_ept_uninit_mmu_context(vcpu
);
8454 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8455 kvm_mmu_reset_context(vcpu
);
8458 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8462 * Trivially support vpid by letting L2s share their parent
8463 * L1's vpid. TODO: move to a more elaborate solution, giving
8464 * each L2 its own vpid and exposing the vpid feature to L1.
8466 vmx_flush_tlb(vcpu
);
8470 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8471 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8472 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8473 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8474 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8476 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8477 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
8478 vmcs_write64(GUEST_BNDCFGS
, 0);
8480 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8481 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8482 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8484 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8485 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8486 vmcs12
->host_ia32_perf_global_ctrl
);
8488 /* Set L1 segment info according to Intel SDM
8489 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8490 seg
= (struct kvm_segment
) {
8492 .limit
= 0xFFFFFFFF,
8493 .selector
= vmcs12
->host_cs_selector
,
8499 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8503 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8504 seg
= (struct kvm_segment
) {
8506 .limit
= 0xFFFFFFFF,
8513 seg
.selector
= vmcs12
->host_ds_selector
;
8514 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8515 seg
.selector
= vmcs12
->host_es_selector
;
8516 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8517 seg
.selector
= vmcs12
->host_ss_selector
;
8518 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8519 seg
.selector
= vmcs12
->host_fs_selector
;
8520 seg
.base
= vmcs12
->host_fs_base
;
8521 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8522 seg
.selector
= vmcs12
->host_gs_selector
;
8523 seg
.base
= vmcs12
->host_gs_base
;
8524 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8525 seg
= (struct kvm_segment
) {
8526 .base
= vmcs12
->host_tr_base
,
8528 .selector
= vmcs12
->host_tr_selector
,
8532 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8534 kvm_set_dr(vcpu
, 7, 0x400);
8535 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8539 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8540 * and modify vmcs12 to make it see what it would expect to see there if
8541 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8543 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8545 unsigned long exit_qualification
)
8547 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8549 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8551 /* trying to cancel vmlaunch/vmresume is a bug */
8552 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8554 leave_guest_mode(vcpu
);
8555 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8556 exit_qualification
);
8558 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8559 vmcs12
->exit_qualification
,
8560 vmcs12
->idt_vectoring_info_field
,
8561 vmcs12
->vm_exit_intr_info
,
8562 vmcs12
->vm_exit_intr_error_code
,
8566 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8568 vmx_vcpu_load(vcpu
, cpu
);
8572 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8573 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8574 vmx_segment_cache_clear(vmx
);
8576 /* if no vmcs02 cache requested, remove the one we used */
8577 if (VMCS02_POOL_SIZE
== 0)
8578 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8580 load_vmcs12_host_state(vcpu
, vmcs12
);
8582 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8583 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8585 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8588 /* Unpin physical memory we referred to in vmcs02 */
8589 if (vmx
->nested
.apic_access_page
) {
8590 nested_release_page(vmx
->nested
.apic_access_page
);
8591 vmx
->nested
.apic_access_page
= 0;
8595 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8596 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8597 * success or failure flag accordingly.
8599 if (unlikely(vmx
->fail
)) {
8601 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8603 nested_vmx_succeed(vcpu
);
8604 if (enable_shadow_vmcs
)
8605 vmx
->nested
.sync_shadow_vmcs
= true;
8607 /* in case we halted in L2 */
8608 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
8612 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8614 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8616 if (is_guest_mode(vcpu
))
8617 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8618 free_nested(to_vmx(vcpu
));
8622 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8623 * 23.7 "VM-entry failures during or after loading guest state" (this also
8624 * lists the acceptable exit-reason and exit-qualification parameters).
8625 * It should only be called before L2 actually succeeded to run, and when
8626 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8628 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8629 struct vmcs12
*vmcs12
,
8630 u32 reason
, unsigned long qualification
)
8632 load_vmcs12_host_state(vcpu
, vmcs12
);
8633 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8634 vmcs12
->exit_qualification
= qualification
;
8635 nested_vmx_succeed(vcpu
);
8636 if (enable_shadow_vmcs
)
8637 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8640 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8641 struct x86_instruction_info
*info
,
8642 enum x86_intercept_stage stage
)
8644 return X86EMUL_CONTINUE
;
8647 static struct kvm_x86_ops vmx_x86_ops
= {
8648 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8649 .disabled_by_bios
= vmx_disabled_by_bios
,
8650 .hardware_setup
= hardware_setup
,
8651 .hardware_unsetup
= hardware_unsetup
,
8652 .check_processor_compatibility
= vmx_check_processor_compat
,
8653 .hardware_enable
= hardware_enable
,
8654 .hardware_disable
= hardware_disable
,
8655 .cpu_has_accelerated_tpr
= report_flexpriority
,
8657 .vcpu_create
= vmx_create_vcpu
,
8658 .vcpu_free
= vmx_free_vcpu
,
8659 .vcpu_reset
= vmx_vcpu_reset
,
8661 .prepare_guest_switch
= vmx_save_host_state
,
8662 .vcpu_load
= vmx_vcpu_load
,
8663 .vcpu_put
= vmx_vcpu_put
,
8665 .update_db_bp_intercept
= update_exception_bitmap
,
8666 .get_msr
= vmx_get_msr
,
8667 .set_msr
= vmx_set_msr
,
8668 .get_segment_base
= vmx_get_segment_base
,
8669 .get_segment
= vmx_get_segment
,
8670 .set_segment
= vmx_set_segment
,
8671 .get_cpl
= vmx_get_cpl
,
8672 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8673 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8674 .decache_cr3
= vmx_decache_cr3
,
8675 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8676 .set_cr0
= vmx_set_cr0
,
8677 .set_cr3
= vmx_set_cr3
,
8678 .set_cr4
= vmx_set_cr4
,
8679 .set_efer
= vmx_set_efer
,
8680 .get_idt
= vmx_get_idt
,
8681 .set_idt
= vmx_set_idt
,
8682 .get_gdt
= vmx_get_gdt
,
8683 .set_gdt
= vmx_set_gdt
,
8684 .get_dr6
= vmx_get_dr6
,
8685 .set_dr6
= vmx_set_dr6
,
8686 .set_dr7
= vmx_set_dr7
,
8687 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
8688 .cache_reg
= vmx_cache_reg
,
8689 .get_rflags
= vmx_get_rflags
,
8690 .set_rflags
= vmx_set_rflags
,
8691 .fpu_activate
= vmx_fpu_activate
,
8692 .fpu_deactivate
= vmx_fpu_deactivate
,
8694 .tlb_flush
= vmx_flush_tlb
,
8696 .run
= vmx_vcpu_run
,
8697 .handle_exit
= vmx_handle_exit
,
8698 .skip_emulated_instruction
= skip_emulated_instruction
,
8699 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8700 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8701 .patch_hypercall
= vmx_patch_hypercall
,
8702 .set_irq
= vmx_inject_irq
,
8703 .set_nmi
= vmx_inject_nmi
,
8704 .queue_exception
= vmx_queue_exception
,
8705 .cancel_injection
= vmx_cancel_injection
,
8706 .interrupt_allowed
= vmx_interrupt_allowed
,
8707 .nmi_allowed
= vmx_nmi_allowed
,
8708 .get_nmi_mask
= vmx_get_nmi_mask
,
8709 .set_nmi_mask
= vmx_set_nmi_mask
,
8710 .enable_nmi_window
= enable_nmi_window
,
8711 .enable_irq_window
= enable_irq_window
,
8712 .update_cr8_intercept
= update_cr8_intercept
,
8713 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8714 .vm_has_apicv
= vmx_vm_has_apicv
,
8715 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8716 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8717 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8718 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8719 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8721 .set_tss_addr
= vmx_set_tss_addr
,
8722 .get_tdp_level
= get_ept_level
,
8723 .get_mt_mask
= vmx_get_mt_mask
,
8725 .get_exit_info
= vmx_get_exit_info
,
8727 .get_lpage_level
= vmx_get_lpage_level
,
8729 .cpuid_update
= vmx_cpuid_update
,
8731 .rdtscp_supported
= vmx_rdtscp_supported
,
8732 .invpcid_supported
= vmx_invpcid_supported
,
8734 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8736 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8738 .set_tsc_khz
= vmx_set_tsc_khz
,
8739 .read_tsc_offset
= vmx_read_tsc_offset
,
8740 .write_tsc_offset
= vmx_write_tsc_offset
,
8741 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8742 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8743 .read_l1_tsc
= vmx_read_l1_tsc
,
8745 .set_tdp_cr3
= vmx_set_cr3
,
8747 .check_intercept
= vmx_check_intercept
,
8748 .handle_external_intr
= vmx_handle_external_intr
,
8749 .mpx_supported
= vmx_mpx_supported
,
8751 .check_nested_events
= vmx_check_nested_events
,
8754 static int __init
vmx_init(void)
8758 rdmsrl_safe(MSR_EFER
, &host_efer
);
8760 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8761 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8763 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8764 if (!vmx_io_bitmap_a
)
8769 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8770 if (!vmx_io_bitmap_b
)
8773 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8774 if (!vmx_msr_bitmap_legacy
)
8777 vmx_msr_bitmap_legacy_x2apic
=
8778 (unsigned long *)__get_free_page(GFP_KERNEL
);
8779 if (!vmx_msr_bitmap_legacy_x2apic
)
8782 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8783 if (!vmx_msr_bitmap_longmode
)
8786 vmx_msr_bitmap_longmode_x2apic
=
8787 (unsigned long *)__get_free_page(GFP_KERNEL
);
8788 if (!vmx_msr_bitmap_longmode_x2apic
)
8790 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8791 if (!vmx_vmread_bitmap
)
8794 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8795 if (!vmx_vmwrite_bitmap
)
8798 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8799 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8800 /* shadowed read/write fields */
8801 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8802 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8803 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8805 /* shadowed read only fields */
8806 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8807 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8810 * Allow direct access to the PC debug port (it is often used for I/O
8811 * delays, but the vmexits simply slow things down).
8813 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8814 clear_bit(0x80, vmx_io_bitmap_a
);
8816 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8818 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8819 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8821 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8823 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8824 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8829 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8830 crash_vmclear_local_loaded_vmcss
);
8833 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8834 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8835 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8836 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8837 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8838 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8839 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
8841 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8842 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8843 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8844 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8847 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8848 vmx_disable_intercept_msr_read_x2apic(msr
);
8850 /* According SDM, in x2apic mode, the whole id reg is used.
8851 * But in KVM, it only use the highest eight bits. Need to
8853 vmx_enable_intercept_msr_read_x2apic(0x802);
8855 vmx_enable_intercept_msr_read_x2apic(0x839);
8857 vmx_disable_intercept_msr_write_x2apic(0x808);
8859 vmx_disable_intercept_msr_write_x2apic(0x80b);
8861 vmx_disable_intercept_msr_write_x2apic(0x83f);
8865 kvm_mmu_set_mask_ptes(0ull,
8866 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8867 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8868 0ull, VMX_EPT_EXECUTABLE_MASK
);
8869 ept_set_mmio_spte_mask();
8877 free_page((unsigned long)vmx_vmwrite_bitmap
);
8879 free_page((unsigned long)vmx_vmread_bitmap
);
8881 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8883 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8885 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8887 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8889 free_page((unsigned long)vmx_io_bitmap_b
);
8891 free_page((unsigned long)vmx_io_bitmap_a
);
8895 static void __exit
vmx_exit(void)
8897 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8898 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8899 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8900 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8901 free_page((unsigned long)vmx_io_bitmap_b
);
8902 free_page((unsigned long)vmx_io_bitmap_a
);
8903 free_page((unsigned long)vmx_vmwrite_bitmap
);
8904 free_page((unsigned long)vmx_vmread_bitmap
);
8907 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8914 module_init(vmx_init
)
8915 module_exit(vmx_exit
)